#include <stdint.h>#include <gpxe/if_ether.h>#include <gpxe/iobuf.h>#include "vxge_reg.h"#include "vxge_version.h"Go to the source code of this file.
| #define VXGE_HW_DTR_MAX_T_CODE 16 |
Definition at line 27 of file vxge_traffic.h.
| #define VXGE_HW_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL |
Definition at line 28 of file vxge_traffic.h.
Referenced by __vxge_hw_vpath_alarm_process(), and vxge_hw_device_begin_irq().
| #define VXGE_HW_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL |
Definition at line 29 of file vxge_traffic.h.
Referenced by __vxge_hw_vpath_alarm_process(), __vxge_hw_vpath_pci_read(), vxge_hw_device_intr_disable(), vxge_hw_vpath_intr_disable(), and vxge_hw_vpath_intr_enable().
| #define VXGE_HW_MAX_VIRTUAL_PATHS 17 |
Definition at line 30 of file vxge_traffic.h.
Referenced by __vxge_hw_device_host_info_get(), __vxge_hw_vpath_initialize(), vxge_hw_device_begin_irq(), vxge_hw_device_hw_info_get(), vxge_hw_vpath_strip_fcs_check(), and vxge_probe().
| #define VXGE_HW_MAX_VIRTUAL_FUNCTIONS 8 |
Definition at line 32 of file vxge_traffic.h.
| #define VXGE_HW_MAC_MAX_MAC_PORT_ID 3 |
Definition at line 34 of file vxge_traffic.h.
Referenced by __vxge_hw_vpath_mgmt_read(), and vxge_hw_vpath_strip_fcs_check().
| #define VXGE_HW_DEFAULT_32 0xffffffff |
| #define VXGE_HW_HEADER_802_2_SIZE 3 |
Definition at line 38 of file vxge_traffic.h.
| #define VXGE_HW_HEADER_SNAP_SIZE 5 |
Definition at line 39 of file vxge_traffic.h.
| #define VXGE_HW_HEADER_VLAN_SIZE 4 |
Definition at line 40 of file vxge_traffic.h.
| #define VXGE_HW_MAC_HEADER_MAX_SIZE |
Value:
Definition at line 41 of file vxge_traffic.h.
Referenced by __vxge_hw_vpath_mgmt_read(), and vxge_hw_vpath_mtu_set().
| #define VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN 0x12 |
Definition at line 61 of file vxge_traffic.h.
| #define VXGE_HW_HEADER_802_2_SNAP_ALIGN 2 |
Definition at line 62 of file vxge_traffic.h.
| #define VXGE_HW_HEADER_802_2_ALIGN 3 |
Definition at line 63 of file vxge_traffic.h.
| #define VXGE_HW_HEADER_SNAP_ALIGN 1 |
Definition at line 64 of file vxge_traffic.h.
| #define VXGE_HW_L3_CKSUM_OK 0xFFFF |
Definition at line 66 of file vxge_traffic.h.
| #define VXGE_HW_L4_CKSUM_OK 0xFFFF |
Definition at line 67 of file vxge_traffic.h.
| #define TRUE 1 |
Definition at line 78 of file vxge_traffic.h.
| #define FALSE 0 |
Definition at line 82 of file vxge_traffic.h.
| #define VXGE_HW_EVENT_BASE 0 |
Definition at line 86 of file vxge_traffic.h.
| #define VXGE_LL_EVENT_BASE 100 |
Definition at line 87 of file vxge_traffic.h.
| #define VXGE_HW_MAX_INTR_PER_VP 4 |
Definition at line 129 of file vxge_traffic.h.
Referenced by __vxge_hw_fifo_create(), and __vxge_hw_vpath_tim_configure().
| #define VXGE_HW_VPATH_INTR_TX 0 |
Definition at line 130 of file vxge_traffic.h.
Referenced by __vxge_hw_fifo_create(), __vxge_hw_vpath_tim_configure(), vxge_hw_device_clear_tx_rx(), and vxge_hw_device_intr_enable().
| #define VXGE_HW_VPATH_INTR_RX 1 |
Definition at line 131 of file vxge_traffic.h.
Referenced by __vxge_hw_vpath_tim_configure(), vxge_hw_device_clear_tx_rx(), and vxge_hw_device_intr_enable().
| #define VXGE_HW_VPATH_INTR_EINTA 2 |
| #define VXGE_HW_VPATH_INTR_BMAP 3 |
| #define VXGE_HW_BLOCK_SIZE 4096 |
Definition at line 135 of file vxge_traffic.h.
| #define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL 17 |
| #define VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL 18 |
| #define VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL 19 |
Definition at line 139 of file vxge_traffic.h.
| #define VXGE_HW_TIM_UTIL_SEL_PER_VPATH 63 |
Definition at line 140 of file vxge_traffic.h.
| enum vxge_hw_event |
enum vxge_hw_event- Enumerates slow-path HW events.
: Unknown (and invalid) event. : Serious vpath hardware error event. : vpath ECC error event. : Error local to the respective vpath : FIFO Doorbell fifo error. : srpcim hardware error event. : mrpcim hardware error event. : mrpcim ecc error event. : Privileged entity is starting device reset : Device reset has been completed : Slot-freeze event. Driver tries to distinguish slot-freeze from the rest critical events (e.g. ECC) when it is impossible to PIO read "through" the bus, i.e. when getting all-foxes.
enum vxge_hw_event enumerates slow-path HW eventis.
See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{}, vxge_uld_link_down_f{}.
Definition at line 110 of file vxge_traffic.h.
00110 { 00111 VXGE_HW_EVENT_UNKNOWN = 0, 00112 /* HW events */ 00113 VXGE_HW_EVENT_RESET_START = VXGE_HW_EVENT_BASE + 1, 00114 VXGE_HW_EVENT_RESET_COMPLETE = VXGE_HW_EVENT_BASE + 2, 00115 VXGE_HW_EVENT_LINK_DOWN = VXGE_HW_EVENT_BASE + 3, 00116 VXGE_HW_EVENT_LINK_UP = VXGE_HW_EVENT_BASE + 4, 00117 VXGE_HW_EVENT_ALARM_CLEARED = VXGE_HW_EVENT_BASE + 5, 00118 VXGE_HW_EVENT_ECCERR = VXGE_HW_EVENT_BASE + 6, 00119 VXGE_HW_EVENT_MRPCIM_ECCERR = VXGE_HW_EVENT_BASE + 7, 00120 VXGE_HW_EVENT_FIFO_ERR = VXGE_HW_EVENT_BASE + 8, 00121 VXGE_HW_EVENT_VPATH_ERR = VXGE_HW_EVENT_BASE + 9, 00122 VXGE_HW_EVENT_CRITICAL_ERR = VXGE_HW_EVENT_BASE + 10, 00123 VXGE_HW_EVENT_SERR = VXGE_HW_EVENT_BASE + 11, 00124 VXGE_HW_EVENT_SRPCIM_SERR = VXGE_HW_EVENT_BASE + 12, 00125 VXGE_HW_EVENT_MRPCIM_SERR = VXGE_HW_EVENT_BASE + 13, 00126 VXGE_HW_EVENT_SLOT_FREEZE = VXGE_HW_EVENT_BASE + 14, 00127 };
| enum vxge_hw_ring_tcode |
enum vxge_hw_ring_tcode - Transfer codes returned by adapter : Transfer ok.
: Layer 3 checksum presentation configuration mismatch. : Layer 4 checksum presentation configuration mismatch. : Layer 3 and Layer 4 checksum presentation configuration mismatch. : Layer 3 error unparseable packet, such as unknown IPv6 header. : Layer 2 error frame integrity error, such as FCS or ECC). : Buffer size error the RxD buffer( s) were not appropriately sized and data loss occurred. : Internal ECC error RxD corrupted. : Benign overflow the contents of Segment1 exceeded the capacity of Buffer1 and the remainder was placed in Buffer2. Segment2 now starts in Buffer3. No data loss or errors occurred. : Buffer size 0 one of the RxDs assigned buffers has a size of 0 bytes. : Frame dropped either due to VPath Reset or because of a VPIN mismatch. : Unused : Multiple errors more than one transfer code condition occurred.
Transfer codes returned by adapter.
Definition at line 172 of file vxge_traffic.h.
00172 { 00173 VXGE_HW_RING_T_CODE_OK = 0x0, 00174 VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH = 0x1, 00175 VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH = 0x2, 00176 VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH = 0x3, 00177 VXGE_HW_RING_T_CODE_L3_PKT_ERR = 0x5, 00178 VXGE_HW_RING_T_CODE_L2_FRM_ERR = 0x6, 00179 VXGE_HW_RING_T_CODE_BUF_SIZE_ERR = 0x7, 00180 VXGE_HW_RING_T_CODE_INT_ECC_ERR = 0x8, 00181 VXGE_HW_RING_T_CODE_BENIGN_OVFLOW = 0x9, 00182 VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF = 0xA, 00183 VXGE_HW_RING_T_CODE_FRM_DROP = 0xC, 00184 VXGE_HW_RING_T_CODE_UNUSED = 0xE, 00185 VXGE_HW_RING_T_CODE_MULTI_ERR = 0xF 00186 };
enum enum vxge_hw_fifo_gather_code - Gather codes used in fifo TxD : First TxDL : Middle TxDL : Last TxDL : First and Last TxDL.
These gather codes are used to indicate the position of a TxD in a TxD list
| VXGE_HW_FIFO_GATHER_CODE_FIRST | |
| VXGE_HW_FIFO_GATHER_CODE_MIDDLE | |
| VXGE_HW_FIFO_GATHER_CODE_LAST | |
| VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST |
Definition at line 198 of file vxge_traffic.h.
00198 { 00199 VXGE_HW_FIFO_GATHER_CODE_FIRST = 0x2, 00200 VXGE_HW_FIFO_GATHER_CODE_MIDDLE = 0x0, 00201 VXGE_HW_FIFO_GATHER_CODE_LAST = 0x1, 00202 VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST = 0x3 00203 };
| enum vxge_hw_fifo_tcode |
enum enum vxge_hw_fifo_tcode - tcodes used in fifo : Transfer OK : PCI read transaction (either TxD or frame data) returned with corrupt data.
:PCI read transaction was returned with no data. : The host attempted to send either a frame or LSO MSS that was too long (>9800B). : Error detected during TCP/UDP Large Send Offload operation, due to improper header template, unsupported protocol, etc. : Unused : Set to 1 by the adapter if multiple data buffer transfer errors are encountered (see below). Otherwise it is set to 0.
These tcodes are returned in various API for TxD status
Definition at line 224 of file vxge_traffic.h.
00224 { 00225 VXGE_HW_FIFO_T_CODE_OK = 0x0, 00226 VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT = 0x1, 00227 VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL = 0x2, 00228 VXGE_HW_FIFO_T_CODE_INVALID_MSS = 0x3, 00229 VXGE_HW_FIFO_T_CODE_LSO_ERROR = 0x4, 00230 VXGE_HW_FIFO_T_CODE_UNUSED = 0x7, 00231 VXGE_HW_FIFO_T_CODE_MULTI_ERROR = 0x8 00232 };
| FILE_LICENCE | ( | GPL2_ONLY | ) |
| enum vxge_hw_status vxge_hw_ring_replenish | ( | struct __vxge_hw_ring * | ring | ) |
Definition at line 523 of file vxge_config.c.
References alloc_iob(), ARRAY_SIZE, __vxge_hw_ring::buf_per_block, vxge_hw_ring_rxd_1::control_0, vxge_hw_ring_rxd_1::control_1, free_iob(), __vxge_hw_virtualpath::hldev, __vxge_hw_ring::iobuf, NULL, offset, __vxge_hw_ring_block::pNext_RxD_Blk_physical, __vxge_hw_ring_block::reserved_2_pNext_RxD_block, __vxge_hw_ring_block::rxd, rxd, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, u8, __vxge_hw_device::vdev, virt_to_bus(), __vxge_hw_ring::vpathh, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_MAX_RXDS_PER_BLOCK_1, VXGE_HW_OK, VXGE_HW_RING_BUF_PER_BLOCK, vxge_hw_ring_rxd_1b_set(), vxge_hw_ring_rxd_post(), VXGE_LL_MAX_FRAME_SIZE, and vxge_trace.
Referenced by __vxge_hw_ring_create().
00524 { 00525 struct __vxge_hw_device *hldev; 00526 struct vxge_hw_ring_rxd_1 *rxd; 00527 enum vxge_hw_status status = VXGE_HW_OK; 00528 u8 offset = 0; 00529 struct __vxge_hw_ring_block *block; 00530 u8 i, iob_off; 00531 00532 vxge_trace(); 00533 00534 hldev = ring->vpathh->hldev; 00535 /* 00536 * We allocate all the dma buffers first and then share the 00537 * these buffers among the all rx descriptors in the block. 00538 */ 00539 for (i = 0; i < ARRAY_SIZE(ring->iobuf); i++) { 00540 ring->iobuf[i] = alloc_iob(VXGE_LL_MAX_FRAME_SIZE(hldev->vdev)); 00541 if (!ring->iobuf[i]) { 00542 while (i) { 00543 free_iob(ring->iobuf[--i]); 00544 ring->iobuf[i] = NULL; 00545 } 00546 status = VXGE_HW_ERR_OUT_OF_MEMORY; 00547 goto iobuf_err; 00548 } 00549 } 00550 00551 for (offset = 0; offset < VXGE_HW_MAX_RXDS_PER_BLOCK_1; offset++) { 00552 00553 rxd = &ring->rxdl->rxd[offset]; 00554 if (offset == (VXGE_HW_MAX_RXDS_PER_BLOCK_1 - 1)) 00555 iob_off = VXGE_HW_RING_BUF_PER_BLOCK; 00556 else 00557 iob_off = offset % ring->buf_per_block; 00558 00559 rxd->control_0 = rxd->control_1 = 0; 00560 vxge_hw_ring_rxd_1b_set(rxd, ring->iobuf[iob_off], 00561 VXGE_LL_MAX_FRAME_SIZE(hldev->vdev)); 00562 00563 vxge_hw_ring_rxd_post(ring, rxd); 00564 } 00565 /* linking the block to itself as we use only one rx block*/ 00566 block = ring->rxdl; 00567 block->reserved_2_pNext_RxD_block = (unsigned long) block; 00568 block->pNext_RxD_Blk_physical = (u64)virt_to_bus(block); 00569 00570 ring->rxd_offset = 0; 00571 iobuf_err: 00572 return status; 00573 }
| void vxge_hw_ring_rxd_post | ( | struct __vxge_hw_ring * | ring_handle, | |
| struct vxge_hw_ring_rxd_1 * | rxdp | |||
| ) |
| void vxge_hw_fifo_txdl_buffer_set | ( | struct __vxge_hw_fifo * | fifo, | |
| struct vxge_hw_fifo_txd * | txdp, | |||
| struct io_buffer * | iob | |||
| ) |
vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the descriptor.
: Handle to the fifo object used for non offload send : Descriptor handle. : data buffer.
Definition at line 378 of file vxge_traffic.c.
References vxge_hw_fifo_txd::buffer_pointer, vxge_hw_fifo_txd::control_0, vxge_hw_fifo_txd::control_1, io_buffer::data, vxge_hw_fifo_txd::host_control, iob_len(), __vxge_hw_fifo::tx_intr_num, virt_to_bus(), VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST, VXGE_HW_FIFO_TXD_BUFFER_SIZE, VXGE_HW_FIFO_TXD_GATHER_CODE, VXGE_HW_FIFO_TXD_INT_NUMBER, and VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST.
Referenced by vxge_xmit().
00381 { 00382 txdp->control_0 = VXGE_HW_FIFO_TXD_GATHER_CODE( 00383 VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST); 00384 txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(iob_len(iob)); 00385 00386 txdp->control_1 = VXGE_HW_FIFO_TXD_INT_NUMBER(fifo->tx_intr_num); 00387 txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST; 00388 00389 txdp->host_control = (intptr_t)iob; 00390 txdp->buffer_pointer = virt_to_bus(iob->data); 00391 }
| void vxge_hw_fifo_txdl_post | ( | struct __vxge_hw_fifo * | fifo, | |
| struct vxge_hw_fifo_txd * | txdp | |||
| ) |
vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
: Handle to the fifo object used for non offload send : Tx Descriptor
Post descriptor on the 'fifo' type channel for transmission. Prior to posting the descriptor should be filled in accordance with Host/Titan interface specification for a given service (LL, etc.).
Definition at line 403 of file vxge_traffic.c.
References __vxge_hw_non_offload_db_post(), vxge_hw_fifo_txd::control_0, __vxge_hw_fifo::sw_offset, virt_to_bus(), VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER, and vxge_hw_fifo_txd_offset_up().
Referenced by vxge_xmit().
00405 { 00406 txdp->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER; 00407 00408 __vxge_hw_non_offload_db_post(fifo, (u64) virt_to_bus(txdp), 0); 00409 00410 vxge_hw_fifo_txd_offset_up(&fifo->sw_offset); 00411 }
| enum vxge_hw_status __vxge_hw_ring_create | ( | struct __vxge_hw_virtualpath * | vpath, | |
| struct __vxge_hw_ring * | ring | |||
| ) |
Definition at line 581 of file vxge_config.c.
References __vxge_hw_ring_delete(), __vxge_hw_ring::buf_per_block, __vxge_hw_device::common_reg, __vxge_hw_ring::common_reg, __vxge_hw_virtualpath::hldev, malloc_dma(), __vxge_hw_ring::rx_poll_weight, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxd_qword_limit, __vxge_hw_ring::rxdl, u32, __vxge_hw_ring::vp_id, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_reg, __vxge_hw_ring::vp_reg, __vxge_hw_ring::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_OK, VXGE_HW_RING_BUF_PER_BLOCK, vxge_hw_ring_replenish(), VXGE_HW_RING_RX_POLL_WEIGHT, VXGE_HW_RING_RXD_QWORD_LIMIT, and vxge_trace.
Referenced by vxge_hw_vpath_open().
00583 { 00584 enum vxge_hw_status status = VXGE_HW_OK; 00585 struct __vxge_hw_device *hldev; 00586 u32 vp_id; 00587 00588 vxge_trace(); 00589 00590 hldev = vpath->hldev; 00591 vp_id = vpath->vp_id; 00592 00593 ring->rxdl = malloc_dma(sizeof(struct __vxge_hw_ring_block), 00594 sizeof(struct __vxge_hw_ring_block)); 00595 if (!ring->rxdl) { 00596 vxge_debug(VXGE_ERR, "%s:%d malloc_dma error\n", 00597 __func__, __LINE__); 00598 status = VXGE_HW_ERR_OUT_OF_MEMORY; 00599 goto exit; 00600 } 00601 ring->rxd_offset = 0; 00602 ring->vpathh = vpath; 00603 ring->buf_per_block = VXGE_HW_RING_BUF_PER_BLOCK; 00604 ring->rx_poll_weight = VXGE_HW_RING_RX_POLL_WEIGHT; 00605 ring->vp_id = vp_id; 00606 ring->vp_reg = vpath->vp_reg; 00607 ring->common_reg = hldev->common_reg; 00608 00609 ring->rxd_qword_limit = VXGE_HW_RING_RXD_QWORD_LIMIT; 00610 00611 status = vxge_hw_ring_replenish(ring); 00612 if (status != VXGE_HW_OK) { 00613 __vxge_hw_ring_delete(ring); 00614 goto exit; 00615 } 00616 exit: 00617 return status; 00618 }
| enum vxge_hw_status __vxge_hw_ring_delete | ( | struct __vxge_hw_ring * | ringh | ) |
Definition at line 624 of file vxge_config.c.
References ARRAY_SIZE, free_dma(), free_iob(), __vxge_hw_ring::iobuf, NULL, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, u8, VXGE_HW_OK, and vxge_trace.
Referenced by __vxge_hw_ring_create(), and vxge_hw_vpath_close().
00625 { 00626 u8 i; 00627 00628 vxge_trace(); 00629 00630 for (i = 0; (i < ARRAY_SIZE(ring->iobuf)) && ring->iobuf[i]; i++) { 00631 free_iob(ring->iobuf[i]); 00632 ring->iobuf[i] = NULL; 00633 } 00634 00635 if (ring->rxdl) { 00636 free_dma(ring->rxdl, sizeof(struct __vxge_hw_ring_block)); 00637 ring->rxdl = NULL; 00638 } 00639 ring->rxd_offset = 0; 00640 00641 return VXGE_HW_OK; 00642 }
| enum vxge_hw_status __vxge_hw_fifo_create | ( | struct __vxge_hw_virtualpath * | vpath, | |
| struct __vxge_hw_fifo * | fifo | |||
| ) |
Definition at line 779 of file vxge_config.c.
References __vxge_hw_fifo::depth, __vxge_hw_fifo::hw_offset, malloc_dma(), memset(), __vxge_hw_virtualpath::nofl_db, __vxge_hw_fifo::nofl_db, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::tx_intr_num, __vxge_hw_fifo::txdl, __vxge_hw_virtualpath::vp_id, __vxge_hw_fifo::vp_id, __vxge_hw_virtualpath::vp_reg, __vxge_hw_fifo::vp_reg, __vxge_hw_fifo::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_FIFO_TXD_DEPTH, VXGE_HW_MAX_INTR_PER_VP, VXGE_HW_OK, VXGE_HW_VPATH_INTR_TX, and vxge_trace.
Referenced by vxge_hw_vpath_open().
00781 { 00782 enum vxge_hw_status status = VXGE_HW_OK; 00783 00784 vxge_trace(); 00785 00786 fifo->vpathh = vpath; 00787 fifo->depth = VXGE_HW_FIFO_TXD_DEPTH; 00788 fifo->hw_offset = fifo->sw_offset = 0; 00789 fifo->nofl_db = vpath->nofl_db; 00790 fifo->vp_id = vpath->vp_id; 00791 fifo->vp_reg = vpath->vp_reg; 00792 fifo->tx_intr_num = (vpath->vp_id * VXGE_HW_MAX_INTR_PER_VP) 00793 + VXGE_HW_VPATH_INTR_TX; 00794 00795 fifo->txdl = malloc_dma(sizeof(struct vxge_hw_fifo_txd) 00796 * fifo->depth, fifo->depth); 00797 if (!fifo->txdl) { 00798 vxge_debug(VXGE_ERR, "%s:%d malloc_dma error\n", 00799 __func__, __LINE__); 00800 return VXGE_HW_ERR_OUT_OF_MEMORY; 00801 } 00802 memset(fifo->txdl, 0, sizeof(struct vxge_hw_fifo_txd) * fifo->depth); 00803 return status; 00804 }
| enum vxge_hw_status __vxge_hw_fifo_delete | ( | struct __vxge_hw_fifo * | fifo | ) |
Definition at line 810 of file vxge_config.c.
References __vxge_hw_fifo::depth, free_dma(), __vxge_hw_fifo::hw_offset, NULL, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::txdl, VXGE_HW_OK, and vxge_trace.
Referenced by vxge_hw_vpath_close(), and vxge_hw_vpath_open().
00811 { 00812 vxge_trace(); 00813 00814 if (fifo->txdl) 00815 free_dma(fifo->txdl, 00816 sizeof(struct vxge_hw_fifo_txd) * fifo->depth); 00817 00818 fifo->txdl = NULL; 00819 fifo->hw_offset = fifo->sw_offset = 0; 00820 00821 return VXGE_HW_OK; 00822 }
| enum vxge_hw_status __vxge_hw_vpath_reset | ( | struct __vxge_hw_device * | devh, | |
| u32 | vp_id | |||
| ) |
Definition at line 1235 of file vxge_config.c.
References __vxge_hw_pio_mem_write32_upper(), vxge_hw_common_reg::cmn_rsthdlr_cfg0, __vxge_hw_device::common_reg, u32, vxge_bVALn, VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH, VXGE_HW_OK, and vxge_trace.
Referenced by __vxge_hw_vp_initialize(), and vxge_hw_vpath_reset().
01236 { 01237 u64 val64; 01238 enum vxge_hw_status status = VXGE_HW_OK; 01239 01240 vxge_trace(); 01241 01242 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id)); 01243 01244 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 01245 &hldev->common_reg->cmn_rsthdlr_cfg0); 01246 01247 return status; 01248 }
| enum vxge_hw_status __vxge_hw_vpath_enable | ( | struct __vxge_hw_device * | devh, | |
| u32 | vp_id | |||
| ) |
| void __vxge_hw_vpath_prc_configure | ( | struct __vxge_hw_device * | hldev | ) |
Definition at line 1256 of file vxge_config.c.
References vxge_hw_vpath_reg::prc_cfg1, vxge_hw_vpath_reg::prc_cfg4, vxge_hw_vpath_reg::prc_cfg5, vxge_hw_vpath_reg::prc_cfg6, readq, __vxge_hw_virtualpath::ringh, __vxge_hw_ring::rxdl, virt_to_bus(), __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE, VXGE_HW_PRC_CFG4_IN_SVC, VXGE_HW_PRC_CFG4_RING_MODE, VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER, VXGE_HW_PRC_CFG4_RTH_DISABLE, VXGE_HW_PRC_CFG5_RXD0_ADD, VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN, VXGE_HW_PRC_CFG6_RXD_CRXDT, VXGE_HW_PRC_CFG6_RXD_SPAT, vxge_trace, and writeq.
Referenced by vxge_hw_vpath_open(), and vxge_hw_vpath_recover_from_reset().
01257 { 01258 u64 val64; 01259 struct __vxge_hw_virtualpath *vpath; 01260 struct vxge_hw_vpath_reg __iomem *vp_reg; 01261 01262 vxge_trace(); 01263 01264 vpath = &hldev->virtual_path; 01265 vp_reg = vpath->vp_reg; 01266 01267 val64 = readq(&vp_reg->prc_cfg1); 01268 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE; 01269 writeq(val64, &vp_reg->prc_cfg1); 01270 01271 val64 = readq(&vpath->vp_reg->prc_cfg6); 01272 val64 &= ~VXGE_HW_PRC_CFG6_RXD_CRXDT(0x1ff); 01273 val64 &= ~VXGE_HW_PRC_CFG6_RXD_SPAT(0x1ff); 01274 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN; 01275 val64 |= VXGE_HW_PRC_CFG6_RXD_CRXDT(0x3); 01276 val64 |= VXGE_HW_PRC_CFG6_RXD_SPAT(0xf); 01277 writeq(val64, &vpath->vp_reg->prc_cfg6); 01278 01279 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD( 01280 (u64)virt_to_bus(vpath->ringh.rxdl) >> 3), 01281 &vp_reg->prc_cfg5); 01282 01283 val64 = readq(&vp_reg->prc_cfg4); 01284 val64 |= VXGE_HW_PRC_CFG4_IN_SVC; 01285 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3); 01286 val64 |= VXGE_HW_PRC_CFG4_RING_MODE( 01287 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER); 01288 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE; 01289 01290 writeq(val64, &vp_reg->prc_cfg4); 01291 return; 01292 }
| enum vxge_hw_status __vxge_hw_vpath_kdfc_configure | ( | struct __vxge_hw_device * | devh, | |
| u32 | vp_id | |||
| ) |
Definition at line 1300 of file vxge_config.c.
References __vxge_hw_kdfc_swapper_set(), __vxge_hw_device::kdfc, vxge_hw_vpath_reg::kdfc_drbl_triplet_total, vxge_hw_vpath_reg::kdfc_fifo_trpl_ctrl, vxge_hw_vpath_reg::kdfc_fifo_trpl_partition, vxge_hw_vpath_reg::kdfc_trpl_fifo_0_ctrl, vxge_hw_vpath_reg::kdfc_trpl_fifo_0_wb_address, __vxge_hw_device::legacy_reg, __vxge_hw_virtualpath::max_kdfc_db, __vxge_hw_virtualpath::max_nofl_db, __vxge_hw_virtualpath::nofl_db, readq, vxge_hw_toc_reg::toc_kdfc_vpath_stride, __vxge_hw_device::toc_reg, u32, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE, VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE, VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN, VXGE_HW_OK, VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE, vxge_trace, wmb, and writeq.
Referenced by __vxge_hw_vpath_initialize().
01301 { 01302 u64 val64; 01303 u64 vpath_stride; 01304 enum vxge_hw_status status = VXGE_HW_OK; 01305 struct __vxge_hw_virtualpath *vpath; 01306 struct vxge_hw_vpath_reg __iomem *vp_reg; 01307 01308 vxge_trace(); 01309 01310 vpath = &hldev->virtual_path; 01311 vp_reg = vpath->vp_reg; 01312 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg); 01313 01314 if (status != VXGE_HW_OK) 01315 goto exit; 01316 01317 val64 = readq(&vp_reg->kdfc_drbl_triplet_total); 01318 01319 vpath->max_kdfc_db = 01320 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE( 01321 val64+1)/2; 01322 01323 vpath->max_nofl_db = vpath->max_kdfc_db; 01324 01325 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0( 01326 (vpath->max_nofl_db*2)-1); 01327 01328 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition); 01329 01330 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE, 01331 &vp_reg->kdfc_fifo_trpl_ctrl); 01332 01333 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl); 01334 01335 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) | 01336 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF)); 01337 01338 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE( 01339 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) | 01340 #if (__BYTE_ORDER != __BIG_ENDIAN) 01341 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN | 01342 #endif 01343 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0); 01344 01345 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl); 01346 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address); 01347 wmb(); 01348 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride); 01349 01350 vpath->nofl_db = 01351 (struct __vxge_hw_non_offload_db_wrapper __iomem *) 01352 (hldev->kdfc + (vp_id * 01353 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE( 01354 vpath_stride))); 01355 exit: 01356 return status; 01357 }
| enum vxge_hw_status __vxge_hw_vpath_mac_configure | ( | struct __vxge_hw_device * | devh | ) |
Definition at line 1364 of file vxge_config.c.
References readq, vxge_hw_vpath_reg::rxmac_vcfg1, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, __vxge_hw_virtualpath::vsport_number, VXGE_HW_OK, VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE, VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE, VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER, vxge_trace, writeq, and vxge_hw_vpath_reg::xmac_vsport_choice.
Referenced by __vxge_hw_vpath_initialize().
01365 { 01366 u64 val64; 01367 enum vxge_hw_status status = VXGE_HW_OK; 01368 struct __vxge_hw_virtualpath *vpath; 01369 struct vxge_hw_vpath_reg __iomem *vp_reg; 01370 01371 vxge_trace(); 01372 01373 vpath = &hldev->virtual_path; 01374 vp_reg = vpath->vp_reg; 01375 01376 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER( 01377 vpath->vsport_number), &vp_reg->xmac_vsport_choice); 01378 01379 val64 = readq(&vp_reg->rxmac_vcfg1); 01380 01381 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) | 01382 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE); 01383 01384 writeq(val64, &vp_reg->rxmac_vcfg1); 01385 return status; 01386 }
| enum vxge_hw_status __vxge_hw_vpath_tim_configure | ( | struct __vxge_hw_device * | devh, | |
| u32 | vp_id | |||
| ) |
Definition at line 1394 of file vxge_config.c.
References readq, RTI_RX_UFC_A, RTI_RX_UFC_B, RTI_RX_UFC_C, RTI_RX_UFC_D, RTI_RX_URANGE_A, RTI_RX_URANGE_B, RTI_RX_URANGE_C, vxge_hw_vpath_reg::tim_bitmap, vxge_hw_vpath_reg::tim_cfg1_int_num, vxge_hw_vpath_reg::tim_cfg2_int_num, vxge_hw_vpath_reg::tim_cfg3_int_num, vxge_hw_vpath_reg::tim_dest_addr, vxge_hw_vpath_reg::tim_pci_cfg, vxge_hw_vpath_reg::tim_remap, vxge_hw_vpath_reg::tim_ring_assn, vxge_hw_vpath_reg::tim_vpath_map, TTI_TX_UFC_A, TTI_TX_UFC_B, TTI_TX_UFC_C, TTI_TX_UFC_D, TTI_TX_URANGE_A, TTI_TX_URANGE_B, TTI_TX_URANGE_C, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_MAX_INTR_PER_VP, VXGE_HW_OK, VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL, VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC, VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI, VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN, VXGE_HW_TIM_CFG1_INT_NUM_URNG_A, VXGE_HW_TIM_CFG1_INT_NUM_URNG_B, VXGE_HW_TIM_CFG1_INT_NUM_URNG_C, VXGE_HW_TIM_CFG2_INT_NUM_UEC_A, VXGE_HW_TIM_CFG2_INT_NUM_UEC_B, VXGE_HW_TIM_CFG2_INT_NUM_UEC_C, VXGE_HW_TIM_CFG2_INT_NUM_UEC_D, VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL, VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL, VXGE_HW_TIM_PCI_CFG_ADD_PAD, VXGE_HW_TIM_RING_ASSN_INT_NUM, VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL, VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL, VXGE_HW_VPATH_INTR_BMAP, VXGE_HW_VPATH_INTR_EINTA, VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, VXGE_RTI_BTIMER_VAL, VXGE_RTI_LTIMER_VAL, vxge_trace, VXGE_TTI_BTIMER_VAL, VXGE_TTI_LTIMER_VAL, and writeq.
Referenced by __vxge_hw_vpath_initialize().
01395 { 01396 u64 val64; 01397 enum vxge_hw_status status = VXGE_HW_OK; 01398 struct __vxge_hw_virtualpath *vpath; 01399 struct vxge_hw_vpath_reg __iomem *vp_reg; 01400 01401 vxge_trace(); 01402 01403 vpath = &hldev->virtual_path; 01404 vp_reg = vpath->vp_reg; 01405 01406 writeq((u64)0, &vp_reg->tim_dest_addr); 01407 writeq((u64)0, &vp_reg->tim_vpath_map); 01408 writeq((u64)0, &vp_reg->tim_bitmap); 01409 writeq((u64)0, &vp_reg->tim_remap); 01410 01411 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM( 01412 (vp_id * VXGE_HW_MAX_INTR_PER_VP) + 01413 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn); 01414 01415 val64 = readq(&vp_reg->tim_pci_cfg); 01416 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD; 01417 writeq(val64, &vp_reg->tim_pci_cfg); 01418 01419 /* TX configuration */ 01420 val64 = VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( 01421 (VXGE_TTI_BTIMER_VAL * 1000) / 272); 01422 val64 |= (VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC | 01423 VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI | 01424 VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN); 01425 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(TTI_TX_URANGE_A) | 01426 VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(TTI_TX_URANGE_B) | 01427 VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(TTI_TX_URANGE_C); 01428 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); 01429 01430 val64 = VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(TTI_TX_UFC_A) | 01431 VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(TTI_TX_UFC_B) | 01432 VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(TTI_TX_UFC_C) | 01433 VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(TTI_TX_UFC_D); 01434 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]); 01435 01436 val64 = VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL( 01437 VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL); 01438 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( 01439 (VXGE_TTI_LTIMER_VAL * 1000) / 272); 01440 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); 01441 01442 /* RX configuration */ 01443 val64 = VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( 01444 (VXGE_RTI_BTIMER_VAL * 1000) / 272); 01445 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; 01446 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(RTI_RX_URANGE_A) | 01447 VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(RTI_RX_URANGE_B) | 01448 VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(RTI_RX_URANGE_C); 01449 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); 01450 01451 val64 = VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(RTI_RX_UFC_A) | 01452 VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(RTI_RX_UFC_B) | 01453 VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(RTI_RX_UFC_C) | 01454 VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(RTI_RX_UFC_D); 01455 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]); 01456 01457 val64 = VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL( 01458 VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL); 01459 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( 01460 (VXGE_RTI_LTIMER_VAL * 1000) / 272); 01461 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); 01462 01463 val64 = 0; 01464 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]); 01465 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]); 01466 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]); 01467 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]); 01468 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]); 01469 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]); 01470 01471 return status; 01472 }
| enum vxge_hw_status __vxge_hw_vpath_initialize | ( | struct __vxge_hw_device * | devh, | |
| u32 | vp_id | |||
| ) |
Definition at line 1480 of file vxge_config.c.
References __vxge_hw_legacy_swapper_set(), __vxge_hw_vpath_kdfc_configure(), __vxge_hw_vpath_mac_configure(), __vxge_hw_vpath_pci_read(), __vxge_hw_vpath_swapper_set(), __vxge_hw_vpath_tim_configure(), __vxge_hw_device::legacy_reg, readq, vxge_hw_vpath_reg::rtdma_rd_optimization_ctrl, u32, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, __vxge_hw_device::vpath_assignments, __vxge_hw_virtualpath::vpmgmt_reg, __vxge_hw_virtualpath::vsport_number, VXGE_HW_ERR_VPATH_NOT_AVAILABLE, VXGE_HW_MAX_PAYLOAD_SIZE_512, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, VXGE_HW_PCI_EXP_DEVCTL_READRQ, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE, vxge_mBIT, vxge_trace, writeq, and vxge_hw_vpmgmt_reg::xmac_vsport_choices_vp.
Referenced by __vxge_hw_vp_initialize(), and vxge_hw_vpath_recover_from_reset().
01481 { 01482 u64 val64; 01483 u32 val32; 01484 int i; 01485 enum vxge_hw_status status = VXGE_HW_OK; 01486 struct __vxge_hw_virtualpath *vpath; 01487 struct vxge_hw_vpath_reg *vp_reg; 01488 01489 vxge_trace(); 01490 01491 vpath = &hldev->virtual_path; 01492 01493 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) { 01494 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; 01495 goto exit; 01496 } 01497 vp_reg = vpath->vp_reg; 01498 status = __vxge_hw_legacy_swapper_set(hldev->legacy_reg); 01499 if (status != VXGE_HW_OK) 01500 goto exit; 01501 01502 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg); 01503 01504 if (status != VXGE_HW_OK) 01505 goto exit; 01506 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp); 01507 01508 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 01509 if (val64 & vxge_mBIT(i)) 01510 vpath->vsport_number = i; 01511 } 01512 01513 status = __vxge_hw_vpath_mac_configure(hldev); 01514 01515 if (status != VXGE_HW_OK) 01516 goto exit; 01517 01518 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id); 01519 01520 if (status != VXGE_HW_OK) 01521 goto exit; 01522 01523 status = __vxge_hw_vpath_tim_configure(hldev, vp_id); 01524 01525 if (status != VXGE_HW_OK) 01526 goto exit; 01527 01528 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl); 01529 01530 /* Get MRRS value from device control */ 01531 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32); 01532 01533 if (status == VXGE_HW_OK) { 01534 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12; 01535 val64 &= 01536 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7)); 01537 val64 |= 01538 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32); 01539 01540 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE; 01541 } 01542 01543 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7)); 01544 val64 |= 01545 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY( 01546 VXGE_HW_MAX_PAYLOAD_SIZE_512); 01547 01548 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN; 01549 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl); 01550 01551 exit: 01552 return status; 01553 }
| enum vxge_hw_status __vxge_hw_vp_initialize | ( | struct __vxge_hw_device * | hldev, | |
| u32 | vp_id, | |||
| struct __vxge_hw_virtualpath * | vpath | |||
| ) |
Definition at line 1561 of file vxge_config.c.
References __vxge_hw_vp_terminate(), __vxge_hw_vpath_initialize(), __vxge_hw_vpath_mgmt_read(), __vxge_hw_vpath_reset(), __vxge_hw_vpath_reset_check(), __vxge_hw_virtualpath::hldev, memset(), __vxge_hw_device::tim_int_mask0, __vxge_hw_device::tim_int_mask1, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, __vxge_hw_virtualpath::vp_reg, __vxge_hw_device::vpath_assignments, __vxge_hw_device::vpath_reg, __vxge_hw_device::vpmgmt_reg, __vxge_hw_virtualpath::vpmgmt_reg, VXGE_HW_DEVICE_TIM_INT_MASK_SET, VXGE_HW_ERR_VPATH_NOT_AVAILABLE, VXGE_HW_OK, VXGE_HW_VP_OPEN, vxge_mBIT, and vxge_trace.
Referenced by vxge_hw_vpath_open().
01563 { 01564 enum vxge_hw_status status = VXGE_HW_OK; 01565 01566 vxge_trace(); 01567 01568 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) { 01569 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; 01570 goto exit; 01571 } 01572 01573 vpath->vp_id = vp_id; 01574 vpath->vp_open = VXGE_HW_VP_OPEN; 01575 vpath->hldev = hldev; 01576 vpath->vp_reg = hldev->vpath_reg[vp_id]; 01577 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id]; 01578 01579 __vxge_hw_vpath_reset(hldev, vp_id); 01580 01581 status = __vxge_hw_vpath_reset_check(vpath); 01582 if (status != VXGE_HW_OK) { 01583 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); 01584 goto exit; 01585 } 01586 01587 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0, 01588 hldev->tim_int_mask1, vp_id); 01589 01590 status = __vxge_hw_vpath_initialize(hldev, vp_id); 01591 01592 if (status != VXGE_HW_OK) { 01593 __vxge_hw_vp_terminate(hldev, vpath); 01594 goto exit; 01595 } 01596 01597 status = __vxge_hw_vpath_mgmt_read(vpath); 01598 exit: 01599 return status; 01600 }
| void __vxge_hw_vp_terminate | ( | struct __vxge_hw_device * | hldev, | |
| struct __vxge_hw_virtualpath * | vpath | |||
| ) |
Definition at line 1607 of file vxge_config.c.
References memset(), __vxge_hw_device::tim_int_mask0, __vxge_hw_device::tim_int_mask1, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, VXGE_HW_DEVICE_TIM_INT_MASK_RESET, VXGE_HW_VP_NOT_OPEN, and vxge_trace.
Referenced by __vxge_hw_vp_initialize(), vxge_hw_vpath_close(), and vxge_hw_vpath_open().
01609 { 01610 vxge_trace(); 01611 01612 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) 01613 return; 01614 01615 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(hldev->tim_int_mask0, 01616 hldev->tim_int_mask1, vpath->vp_id); 01617 01618 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); 01619 }
| enum vxge_hw_status vxge_hw_device_begin_irq | ( | struct __vxge_hw_device * | hldev | ) |
vxge_hw_device_begin_irq - Begin IRQ processing.
: HW device handle.
The function performs two actions, It first checks whether (shared IRQ) the interrupt was raised by the device. Next, it masks the device interrupts.
Note: vxge_hw_device_begin_irq() does not flush MMIO writes through the bridge. Therefore, two back-to-back interrupts are potentially possible.
Returns: 0, if the interrupt is not "ours" (note that in this case the device remain enabled). Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter status.
Definition at line 558 of file vxge_traffic.c.
References __vxge_hw_vpath_alarm_process(), vxge_hw_common_reg::adapter_status, __vxge_hw_device::common_reg, net_device::name, __vxge_hw_device::ndev, readq, vxge_hw_common_reg::titan_general_int_status, __vxge_hw_device::virtual_path, __vxge_hw_device::vpaths_deployed, vxge_debug, VXGE_ERR, VXGE_HW_ALL_FOXES, vxge_hw_device_clear_tx_rx(), VXGE_HW_ERR_SLOT_FREEZE, VXGE_HW_ERR_WRONG_IRQ, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT, and VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT.
Referenced by vxge_poll().
00559 { 00560 u64 val64; 00561 u64 adapter_status; 00562 u64 vpath_mask; 00563 enum vxge_hw_status ret = VXGE_HW_OK; 00564 00565 val64 = readq(&hldev->common_reg->titan_general_int_status); 00566 00567 if (!val64) { 00568 ret = VXGE_HW_ERR_WRONG_IRQ; 00569 goto exit; 00570 } 00571 00572 if (val64 == VXGE_HW_ALL_FOXES) { 00573 00574 adapter_status = readq(&hldev->common_reg->adapter_status); 00575 00576 if (adapter_status == VXGE_HW_ALL_FOXES) { 00577 00578 vxge_debug(VXGE_ERR, "%s: %s:%d critical error " 00579 "occurred\n", hldev->ndev->name, 00580 __func__, __LINE__); 00581 ret = VXGE_HW_ERR_SLOT_FREEZE; 00582 goto exit; 00583 } 00584 } 00585 00586 vpath_mask = hldev->vpaths_deployed >> 00587 (64 - VXGE_HW_MAX_VIRTUAL_PATHS); 00588 if (val64 & VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT( 00589 vpath_mask)) 00590 vxge_hw_device_clear_tx_rx(hldev); 00591 00592 if (val64 & VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT) 00593 ret = __vxge_hw_vpath_alarm_process(&hldev->virtual_path); 00594 00595 exit: 00596 return ret; 00597 }
| void vxge_hw_device_intr_enable | ( | struct __vxge_hw_device * | hldev | ) |
vxge_hw_device_intr_enable - Enable interrupts.
: HW device handle.
Enable Titan interrupts. The function is to be executed the last in Titan initialization sequence.
See also: vxge_hw_device_intr_disable()
Definition at line 254 of file vxge_traffic.c.
References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, readq, vxge_hw_common_reg::tim_int_mask0, __vxge_hw_device::tim_int_mask0, vxge_hw_common_reg::tim_int_mask1, __vxge_hw_device::tim_int_mask1, vxge_hw_common_reg::tim_int_status0, vxge_hw_common_reg::tim_int_status1, vxge_hw_common_reg::titan_general_int_status, u32, __vxge_hw_device::virtual_path, vxge_hw_device_mask_all(), vxge_hw_vpath_intr_enable(), VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, and writeq.
Referenced by vxge_open().
00255 { 00256 u64 val64; 00257 u32 val32; 00258 00259 vxge_hw_device_mask_all(hldev); 00260 00261 vxge_hw_vpath_intr_enable(&hldev->virtual_path); 00262 00263 val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] | 00264 hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]; 00265 00266 if (val64 != 0) { 00267 writeq(val64, &hldev->common_reg->tim_int_status0); 00268 00269 writeq(~val64, &hldev->common_reg->tim_int_mask0); 00270 } 00271 00272 val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] | 00273 hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]; 00274 00275 if (val32 != 0) { 00276 __vxge_hw_pio_mem_write32_upper(val32, 00277 &hldev->common_reg->tim_int_status1); 00278 00279 __vxge_hw_pio_mem_write32_upper(~val32, 00280 &hldev->common_reg->tim_int_mask1); 00281 } 00282 00283 val64 = readq(&hldev->common_reg->titan_general_int_status); 00284 00285 /* We have not enabled the top level interrupt yet. 00286 * This will be controlled from vxge_irq() entry api. 00287 */ 00288 return; 00289 }
| void vxge_hw_device_intr_disable | ( | struct __vxge_hw_device * | hldev | ) |
vxge_hw_device_intr_disable - Disable Titan interrupts.
: HW device handle.
Disable Titan interrupts.
See also: vxge_hw_device_intr_enable()
Definition at line 299 of file vxge_traffic.c.
References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::tim_int_mask0, vxge_hw_common_reg::tim_int_mask1, __vxge_hw_device::virtual_path, VXGE_HW_DEFAULT_32, vxge_hw_device_mask_all(), VXGE_HW_INTR_MASK_ALL, vxge_hw_vpath_intr_disable(), and writeq.
Referenced by vxge_close().
00300 { 00301 vxge_hw_device_mask_all(hldev); 00302 00303 /* mask all the tim interrupts */ 00304 writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0); 00305 __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32, 00306 &hldev->common_reg->tim_int_mask1); 00307 00308 vxge_hw_vpath_intr_disable(&hldev->virtual_path); 00309 00310 return; 00311 }
| void vxge_hw_device_mask_all | ( | struct __vxge_hw_device * | hldev | ) |
vxge_hw_device_mask_all - Mask all device interrupts.
: HW device handle.
Mask all device interrupts.
See also: vxge_hw_device_unmask_all()
Definition at line 214 of file vxge_traffic.c.
References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::titan_mask_all_int, u32, vxge_bVALn, VXGE_HW_TITAN_MASK_ALL_INT_ALARM, and VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC.
Referenced by vxge_hw_device_intr_disable(), vxge_hw_device_intr_enable(), and vxge_irq().
00215 { 00216 u64 val64; 00217 00218 val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM | 00219 VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC; 00220 00221 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 00222 &hldev->common_reg->titan_mask_all_int); 00223 00224 return; 00225 }
| void vxge_hw_device_unmask_all | ( | struct __vxge_hw_device * | hldev | ) |
vxge_hw_device_unmask_all - Unmask all device interrupts.
: HW device handle.
Unmask all device interrupts.
See also: vxge_hw_device_mask_all()
Definition at line 235 of file vxge_traffic.c.
References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::titan_mask_all_int, u32, vxge_bVALn, and VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC.
Referenced by vxge_close(), and vxge_irq().
00236 { 00237 u64 val64 = VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC; 00238 00239 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 00240 &hldev->common_reg->titan_mask_all_int); 00241 00242 return; 00243 }
| void vxge_hw_vpath_doorbell_rx | ( | struct __vxge_hw_ring * | ring | ) |
vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted.
: Handle to the ring object used for receive
The function writes the number of qwords of rxds posted during replishment. Since the function is called frequently, a flush is not required to post the write transaction. At the very least, the previous write will be flushed once the subsequent write is made.
Returns: None.
Definition at line 611 of file vxge_traffic.c.
References __vxge_hw_ring::doorbell_cnt, vxge_hw_vpath_reg::prc_rxd_doorbell, __vxge_hw_ring::rxd_qword_limit, __vxge_hw_ring::total_db_cnt, u32, __vxge_hw_ring::vp_reg, VXGE_HW_MAX_RXDS_PER_BLOCK_1, VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT, VXGE_HW_RING_RXD_QWORDS_MODE_1, wmb, and writeq.
Referenced by vxge_hw_vpath_poll_rx().
00612 { 00613 u32 rxds_qw_per_block = VXGE_HW_MAX_RXDS_PER_BLOCK_1 * 00614 VXGE_HW_RING_RXD_QWORDS_MODE_1; 00615 00616 ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1; 00617 00618 ring->total_db_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1; 00619 00620 if (ring->total_db_cnt >= rxds_qw_per_block) { 00621 /* For each block add 4 more qwords */ 00622 ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1; 00623 00624 /* Reset total count */ 00625 ring->total_db_cnt -= rxds_qw_per_block; 00626 } 00627 00628 if (ring->doorbell_cnt >= ring->rxd_qword_limit) { 00629 wmb(); 00630 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT( 00631 ring->doorbell_cnt), 00632 &ring->vp_reg->prc_rxd_doorbell); 00633 ring->doorbell_cnt = 0; 00634 } 00635 }
| enum vxge_hw_status vxge_hw_vpath_poll_rx | ( | struct __vxge_hw_ring * | ringh | ) |
Definition at line 645 of file vxge_traffic.c.
References alloc_iob(), vxge_hw_ring_rxd_1::control_0, vxge_hw_ring_rxd_1::control_1, io_buffer::data, EINVAL, ENOMEM, ETH_FCS_LEN, __vxge_hw_virtualpath::hldev, vxge_hw_ring_rxd_1::host_control, iob_put, memcpy, net_device::name, __vxge_hw_device::ndev, netdev_rx(), netdev_rx_err(), NULL, __vxge_hw_ring_block::rxd, rxd, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, u16, __vxge_hw_device::vdev, __vxge_hw_ring::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_FAIL, VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS, VXGE_HW_OK, VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET, vxge_hw_ring_rxd_1b_set(), VXGE_HW_RING_RXD_LIST_OWN_ADAPTER, vxge_hw_ring_rxd_offset_up(), vxge_hw_ring_rxd_post(), VXGE_HW_RING_RXD_T_CODE_GET, VXGE_HW_RING_T_CODE_OK, vxge_hw_vpath_doorbell_rx(), VXGE_INFO, and VXGE_LL_MAX_FRAME_SIZE.
Referenced by vxge_poll().
00646 { 00647 struct __vxge_hw_device *hldev; 00648 enum vxge_hw_status status = VXGE_HW_OK; 00649 struct vxge_hw_ring_rxd_1 *rxd; 00650 unsigned int len; 00651 enum vxge_hw_ring_tcode tcode; 00652 struct io_buffer *rx_iob, *iobuf = NULL; 00653 u16 poll_count = 0; 00654 00655 hldev = ring->vpathh->hldev; 00656 00657 do { 00658 rxd = &ring->rxdl->rxd[ring->rxd_offset]; 00659 tcode = VXGE_HW_RING_RXD_T_CODE_GET(rxd->control_0); 00660 00661 /* if tcode is VXGE_HW_RING_T_CODE_FRM_DROP, it is 00662 * possible the ownership bit still set to adapter 00663 */ 00664 if ((rxd->control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER) 00665 && (tcode == VXGE_HW_RING_T_CODE_OK)) { 00666 00667 status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS; 00668 goto err0; 00669 } 00670 00671 vxge_debug(VXGE_INFO, "%s: rx frame received at offset %d\n", 00672 hldev->ndev->name, ring->rxd_offset); 00673 00674 if (tcode != VXGE_HW_RING_T_CODE_OK) { 00675 netdev_rx_err(hldev->ndev, NULL, -EINVAL); 00676 vxge_debug(VXGE_ERR, "%s:%d, rx error tcode %d\n", 00677 __func__, __LINE__, tcode); 00678 status = VXGE_HW_FAIL; 00679 goto err1; 00680 } 00681 00682 iobuf = (struct io_buffer *)(intptr_t)rxd->host_control; 00683 00684 len = VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxd->control_1); 00685 len -= ETH_FCS_LEN; 00686 00687 rx_iob = alloc_iob(len); 00688 if (!rx_iob) { 00689 netdev_rx_err(hldev->ndev, NULL, -ENOMEM); 00690 vxge_debug(VXGE_ERR, "%s:%d, alloc_iob error\n", 00691 __func__, __LINE__); 00692 status = VXGE_HW_ERR_OUT_OF_MEMORY; 00693 goto err1; 00694 } 00695 00696 memcpy(iob_put(rx_iob, len), iobuf->data, len); 00697 /* Add this packet to the receive queue. */ 00698 netdev_rx(hldev->ndev, rx_iob); 00699 00700 err1: 00701 /* repost the rxd */ 00702 rxd->control_0 = rxd->control_1 = 0; 00703 vxge_hw_ring_rxd_1b_set(rxd, iobuf, 00704 VXGE_LL_MAX_FRAME_SIZE(hldev->vdev)); 00705 vxge_hw_ring_rxd_post(ring, rxd); 00706 00707 /* repost the qword count for doorbell */ 00708 vxge_hw_vpath_doorbell_rx(ring); 00709 00710 /* increment the descriptor offset */ 00711 vxge_hw_ring_rxd_offset_up(&ring->rxd_offset); 00712 00713 } while (++poll_count < ring->rx_poll_weight); 00714 err0: 00715 return status; 00716 }
| enum vxge_hw_status vxge_hw_vpath_poll_tx | ( | struct __vxge_hw_fifo * | fifo | ) |
vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same.
: Handle to the fifo object used for non offload send
The function polls the Tx for the completed descriptors and calls the driver via supplied completion callback.
Definition at line 726 of file vxge_traffic.c.
References vxge_hw_fifo_txd::control_0, vxge_hw_fifo_txd::host_control, __vxge_hw_fifo::hw_offset, __vxge_hw_fifo::txdl, txdp, VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER, vxge_hw_fifo_txd_offset_up(), VXGE_HW_FIFO_TXD_T_CODE_GET, VXGE_HW_OK, and vxge_xmit_compl().
Referenced by vxge_poll().
00727 { 00728 enum vxge_hw_status status = VXGE_HW_OK; 00729 struct vxge_hw_fifo_txd *txdp; 00730 00731 txdp = fifo->txdl + fifo->hw_offset; 00732 if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER) 00733 && (txdp->host_control)) { 00734 00735 vxge_xmit_compl(fifo, txdp, 00736 VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0)); 00737 00738 vxge_hw_fifo_txd_offset_up(&fifo->hw_offset); 00739 } 00740 00741 return status; 00742 }
| struct vxge_hw_fifo_txd* vxge_hw_fifo_free_txdl_get | ( | struct __vxge_hw_fifo * | fifo | ) | [read] |
vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo
: tx channel handle
Definition at line 358 of file vxge_traffic.c.
References vxge_hw_fifo_txd::control_0, NULL, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::txdl, txdp, vxge_debug, VXGE_ERR, and VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER.
Referenced by vxge_xmit().
00359 { 00360 struct vxge_hw_fifo_txd *txdp; 00361 00362 txdp = fifo->txdl + fifo->sw_offset; 00363 if (txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER) { 00364 vxge_debug(VXGE_ERR, "%s:%d, error: txd(%d) owned by hw\n", 00365 __func__, __LINE__, fifo->sw_offset); 00366 return NULL; 00367 } 00368 00369 return txdp; 00370 }
1.5.7.1