vxge_traffic.c File Reference

#include <gpxe/netdevice.h>
#include <errno.h>
#include "vxge_traffic.h"
#include "vxge_config.h"
#include "vxge_main.h"

Go to the source code of this file.

Defines

#define ETH_FCS_LEN   4
 vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed descriptors and process the same.

Functions

 FILE_LICENCE (GPL2_ONLY)
enum vxge_hw_status vxge_hw_vpath_intr_enable (struct __vxge_hw_virtualpath *vpath)
enum vxge_hw_status vxge_hw_vpath_intr_disable (struct __vxge_hw_virtualpath *vpath)
void vxge_hw_device_mask_all (struct __vxge_hw_device *hldev)
 vxge_hw_device_mask_all - Mask all device interrupts.
void vxge_hw_device_unmask_all (struct __vxge_hw_device *hldev)
 vxge_hw_device_unmask_all - Unmask all device interrupts.
void vxge_hw_device_intr_enable (struct __vxge_hw_device *hldev)
 vxge_hw_device_intr_enable - Enable interrupts.
void vxge_hw_device_intr_disable (struct __vxge_hw_device *hldev)
 vxge_hw_device_intr_disable - Disable Titan interrupts.
void vxge_hw_ring_rxd_post (struct __vxge_hw_ring *ring __unused, struct vxge_hw_ring_rxd_1 *rxdp)
 vxge_hw_ring_rxd_post - Post descriptor on the ring.
static void __vxge_hw_non_offload_db_post (struct __vxge_hw_fifo *fifo, u64 txdl_ptr, u32 num_txds)
 __vxge_hw_non_offload_db_post - Post non offload doorbell
struct vxge_hw_fifo_txd * vxge_hw_fifo_free_txdl_get (struct __vxge_hw_fifo *fifo)
 vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo
void vxge_hw_fifo_txdl_buffer_set (struct __vxge_hw_fifo *fifo, struct vxge_hw_fifo_txd *txdp, struct io_buffer *iob)
 vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the descriptor.
void vxge_hw_fifo_txdl_post (struct __vxge_hw_fifo *fifo, struct vxge_hw_fifo_txd *txdp)
 vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
static enum vxge_hw_status __vxge_hw_vpath_alarm_process (struct __vxge_hw_virtualpath *vpath)
void vxge_hw_device_clear_tx_rx (struct __vxge_hw_device *hldev)
 vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the condition that has caused the Tx and RX interrupt.
enum vxge_hw_status vxge_hw_device_begin_irq (struct __vxge_hw_device *hldev)
 vxge_hw_device_begin_irq - Begin IRQ processing.
void vxge_hw_vpath_doorbell_rx (struct __vxge_hw_ring *ring)
 vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted.
enum vxge_hw_status vxge_hw_vpath_poll_rx (struct __vxge_hw_ring *ring)
enum vxge_hw_status vxge_hw_vpath_poll_tx (struct __vxge_hw_fifo *fifo)
 vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same.

Define Documentation

#define ETH_FCS_LEN   4

vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed descriptors and process the same.

: Handle to the ring object used for receive

The function polls the Rx for the completed descriptors.

Definition at line 644 of file vxge_traffic.c.

Function Documentation

FILE_LICENCE ( GPL2_ONLY   ) 

enum vxge_hw_status vxge_hw_vpath_intr_enable ( struct __vxge_hw_virtualpath *  vpath  ) 

Definition at line 34 of file vxge_traffic.c.

References __vxge_hw_pio_mem_write32_upper(), vxge_hw_vpath_reg::asic_ntwk_vp_err_mask, vxge_hw_vpath_reg::asic_ntwk_vp_err_reg, __vxge_hw_device::first_vp_id, vxge_hw_vpath_reg::general_errors_mask, vxge_hw_vpath_reg::general_errors_reg, __vxge_hw_virtualpath::hldev, vxge_hw_vpath_reg::kdfcctl_errors_mask, vxge_hw_vpath_reg::kdfcctl_errors_reg, vxge_hw_vpath_reg::mrpcim_to_vpath_alarm_mask, vxge_hw_vpath_reg::mrpcim_to_vpath_alarm_reg, vxge_hw_vpath_reg::pci_config_errors_mask, vxge_hw_vpath_reg::pci_config_errors_reg, vxge_hw_vpath_reg::prc_alarm_mask, vxge_hw_vpath_reg::prc_alarm_reg, readq, vxge_hw_vpath_reg::srpcim_msg_to_vpath_mask, vxge_hw_vpath_reg::srpcim_msg_to_vpath_reg, vxge_hw_vpath_reg::srpcim_to_vpath_alarm_mask, vxge_hw_vpath_reg::srpcim_to_vpath_alarm_reg, u32, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, __vxge_hw_virtualpath::vp_reg, vxge_hw_vpath_reg::vpath_general_int_mask, vxge_hw_vpath_reg::vpath_general_int_status, vxge_hw_vpath_reg::vpath_pcipif_int_mask, vxge_hw_vpath_reg::vpath_pcipif_int_status, vxge_hw_vpath_reg::vpath_ppif_int_mask, vxge_hw_vpath_reg::vpath_ppif_int_status, vxge_bVALn, VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT, VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK, VXGE_HW_ERR_VPATH_NOT_OPEN, VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW, VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW, VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ, VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR, VXGE_HW_INTR_MASK_ALL, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR, VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON, VXGE_HW_OK, VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, VXGE_HW_VP_NOT_OPEN, vxge_hw_vpath_reg::wrdma_alarm_mask, vxge_hw_vpath_reg::wrdma_alarm_status, writeq, vxge_hw_vpath_reg::xgmac_vp_int_mask, and vxge_hw_vpath_reg::xgmac_vp_int_status.

Referenced by vxge_hw_device_intr_enable().

00035 {
00036         u64 val64;
00037         struct vxge_hw_vpath_reg *vp_reg;
00038         enum vxge_hw_status status = VXGE_HW_OK;
00039 
00040         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
00041                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
00042         goto exit;
00043         }
00044 
00045         vp_reg = vpath->vp_reg;
00046 
00047         writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg);
00048 
00049         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00050                                 &vp_reg->general_errors_reg);
00051 
00052         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00053                                 &vp_reg->pci_config_errors_reg);
00054 
00055         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00056                                 &vp_reg->mrpcim_to_vpath_alarm_reg);
00057 
00058         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00059                                 &vp_reg->srpcim_to_vpath_alarm_reg);
00060 
00061         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00062                                 &vp_reg->vpath_ppif_int_status);
00063 
00064         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00065                                 &vp_reg->srpcim_msg_to_vpath_reg);
00066 
00067         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00068                                 &vp_reg->vpath_pcipif_int_status);
00069 
00070         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00071                                 &vp_reg->prc_alarm_reg);
00072 
00073         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00074                                 &vp_reg->wrdma_alarm_status);
00075 
00076         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00077                                 &vp_reg->asic_ntwk_vp_err_reg);
00078 
00079         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00080                                 &vp_reg->xgmac_vp_int_status);
00081 
00082         val64 = readq(&vp_reg->vpath_general_int_status);
00083 
00084         /* Mask unwanted interrupts */
00085         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00086                                 &vp_reg->vpath_pcipif_int_mask);
00087 
00088         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00089                                 &vp_reg->srpcim_msg_to_vpath_mask);
00090 
00091         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00092                                 &vp_reg->srpcim_to_vpath_alarm_mask);
00093 
00094         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00095                                 &vp_reg->mrpcim_to_vpath_alarm_mask);
00096 
00097         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00098                                 &vp_reg->pci_config_errors_mask);
00099 
00100         /* Unmask the individual interrupts */
00101         writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW|
00102                 VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW|
00103                 VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ|
00104                 VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR), 0, 32),
00105                 &vp_reg->general_errors_mask);
00106 
00107         __vxge_hw_pio_mem_write32_upper(
00108                 (u32)vxge_bVALn((VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR|
00109                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR|
00110                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON|
00111                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON|
00112                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR|
00113                 VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR), 0, 32),
00114                 &vp_reg->kdfcctl_errors_mask);
00115 
00116         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask);
00117 
00118         __vxge_hw_pio_mem_write32_upper(
00119                 (u32)vxge_bVALn(VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, 0, 32),
00120                 &vp_reg->prc_alarm_mask);
00121 
00122         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask);
00123         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask);
00124 
00125         if (vpath->hldev->first_vp_id != vpath->vp_id)
00126                 __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00127                                 &vp_reg->asic_ntwk_vp_err_mask);
00128         else
00129                 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn((
00130                 VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT|
00131                         VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK),
00132                         0, 32), &vp_reg->asic_ntwk_vp_err_mask);
00133 
00134         __vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_general_int_mask);
00135 exit:
00136         return status;
00137 
00138 }

enum vxge_hw_status vxge_hw_vpath_intr_disable ( struct __vxge_hw_virtualpath *  vpath  ) 

Definition at line 150 of file vxge_traffic.c.

References __vxge_hw_pio_mem_write32_upper(), vxge_hw_vpath_reg::asic_ntwk_vp_err_mask, vxge_hw_vpath_reg::general_errors_mask, vxge_hw_vpath_reg::kdfcctl_errors_mask, vxge_hw_vpath_reg::mrpcim_to_vpath_alarm_mask, vxge_hw_vpath_reg::pci_config_errors_mask, vxge_hw_vpath_reg::prc_alarm_mask, vxge_hw_vpath_reg::srpcim_msg_to_vpath_mask, vxge_hw_vpath_reg::srpcim_to_vpath_alarm_mask, u32, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, __vxge_hw_virtualpath::vp_reg, vxge_hw_vpath_reg::vpath_general_int_mask, vxge_hw_vpath_reg::vpath_pcipif_int_mask, vxge_hw_vpath_reg::vpath_ppif_int_mask, VXGE_HW_ERR_VPATH_NOT_OPEN, VXGE_HW_INTR_MASK_ALL, VXGE_HW_OK, VXGE_HW_TIM_CLR_INT_EN_VP, VXGE_HW_VP_NOT_OPEN, vxge_hw_vpath_reg::wrdma_alarm_mask, writeq, and vxge_hw_vpath_reg::xgmac_vp_int_mask.

Referenced by vxge_hw_device_intr_disable().

00151 {
00152         u64 val64;
00153         enum vxge_hw_status status = VXGE_HW_OK;
00154         struct vxge_hw_vpath_reg __iomem *vp_reg;
00155 
00156         if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
00157                 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
00158                 goto exit;
00159         }
00160         vp_reg = vpath->vp_reg;
00161 
00162         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00163                         &vp_reg->vpath_general_int_mask);
00164 
00165         val64 = VXGE_HW_TIM_CLR_INT_EN_VP(1 << (16 - vpath->vp_id));
00166 
00167         writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask);
00168 
00169         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00170                         &vp_reg->general_errors_mask);
00171 
00172         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00173                         &vp_reg->pci_config_errors_mask);
00174 
00175         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00176                         &vp_reg->mrpcim_to_vpath_alarm_mask);
00177 
00178         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00179                         &vp_reg->srpcim_to_vpath_alarm_mask);
00180 
00181         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00182                         &vp_reg->vpath_ppif_int_mask);
00183 
00184         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00185                         &vp_reg->srpcim_msg_to_vpath_mask);
00186 
00187         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00188                         &vp_reg->vpath_pcipif_int_mask);
00189 
00190         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00191                         &vp_reg->wrdma_alarm_mask);
00192 
00193         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00194                         &vp_reg->prc_alarm_mask);
00195 
00196         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00197                         &vp_reg->xgmac_vp_int_mask);
00198 
00199         __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
00200                         &vp_reg->asic_ntwk_vp_err_mask);
00201 
00202 exit:
00203         return status;
00204 }

void vxge_hw_device_mask_all ( struct __vxge_hw_device *  hldev  ) 

vxge_hw_device_mask_all - Mask all device interrupts.

: HW device handle.

Mask all device interrupts.

See also: vxge_hw_device_unmask_all()

Definition at line 214 of file vxge_traffic.c.

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::titan_mask_all_int, u32, vxge_bVALn, VXGE_HW_TITAN_MASK_ALL_INT_ALARM, and VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC.

Referenced by vxge_hw_device_intr_disable(), vxge_hw_device_intr_enable(), and vxge_irq().

00215 {
00216         u64 val64;
00217 
00218         val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM |
00219                         VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
00220 
00221         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
00222                         &hldev->common_reg->titan_mask_all_int);
00223 
00224         return;
00225 }

void vxge_hw_device_unmask_all ( struct __vxge_hw_device *  hldev  ) 

vxge_hw_device_unmask_all - Unmask all device interrupts.

: HW device handle.

Unmask all device interrupts.

See also: vxge_hw_device_mask_all()

Definition at line 235 of file vxge_traffic.c.

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::titan_mask_all_int, u32, vxge_bVALn, and VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC.

Referenced by vxge_close(), and vxge_irq().

00236 {
00237         u64 val64 = VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
00238 
00239         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
00240                         &hldev->common_reg->titan_mask_all_int);
00241 
00242         return;
00243 }

void vxge_hw_device_intr_enable ( struct __vxge_hw_device *  hldev  ) 

vxge_hw_device_intr_enable - Enable interrupts.

: HW device handle.

Enable Titan interrupts. The function is to be executed the last in Titan initialization sequence.

See also: vxge_hw_device_intr_disable()

Definition at line 254 of file vxge_traffic.c.

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, readq, vxge_hw_common_reg::tim_int_mask0, __vxge_hw_device::tim_int_mask0, vxge_hw_common_reg::tim_int_mask1, __vxge_hw_device::tim_int_mask1, vxge_hw_common_reg::tim_int_status0, vxge_hw_common_reg::tim_int_status1, vxge_hw_common_reg::titan_general_int_status, u32, __vxge_hw_device::virtual_path, vxge_hw_device_mask_all(), vxge_hw_vpath_intr_enable(), VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, and writeq.

Referenced by vxge_open().

00255 {
00256         u64 val64;
00257         u32 val32;
00258 
00259         vxge_hw_device_mask_all(hldev);
00260 
00261         vxge_hw_vpath_intr_enable(&hldev->virtual_path);
00262 
00263         val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
00264                         hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX];
00265 
00266         if (val64 != 0) {
00267                 writeq(val64, &hldev->common_reg->tim_int_status0);
00268 
00269                 writeq(~val64, &hldev->common_reg->tim_int_mask0);
00270         }
00271 
00272         val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
00273                         hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX];
00274 
00275         if (val32 != 0) {
00276                 __vxge_hw_pio_mem_write32_upper(val32,
00277                                 &hldev->common_reg->tim_int_status1);
00278 
00279                 __vxge_hw_pio_mem_write32_upper(~val32,
00280                                 &hldev->common_reg->tim_int_mask1);
00281         }
00282 
00283         val64 = readq(&hldev->common_reg->titan_general_int_status);
00284 
00285         /* We have not enabled the top level interrupt yet.
00286          * This will be controlled from vxge_irq() entry api.
00287          */
00288         return;
00289 }

void vxge_hw_device_intr_disable ( struct __vxge_hw_device *  hldev  ) 

vxge_hw_device_intr_disable - Disable Titan interrupts.

: HW device handle.

Disable Titan interrupts.

See also: vxge_hw_device_intr_enable()

Definition at line 299 of file vxge_traffic.c.

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, vxge_hw_common_reg::tim_int_mask0, vxge_hw_common_reg::tim_int_mask1, __vxge_hw_device::virtual_path, VXGE_HW_DEFAULT_32, vxge_hw_device_mask_all(), VXGE_HW_INTR_MASK_ALL, vxge_hw_vpath_intr_disable(), and writeq.

Referenced by vxge_close().

00300 {
00301         vxge_hw_device_mask_all(hldev);
00302 
00303         /* mask all the tim interrupts */
00304         writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);
00305         __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32,
00306                                 &hldev->common_reg->tim_int_mask1);
00307 
00308         vxge_hw_vpath_intr_disable(&hldev->virtual_path);
00309 
00310         return;
00311 }

void vxge_hw_ring_rxd_post ( struct __vxge_hw_ring *ring  __unused,
struct vxge_hw_ring_rxd_1 *  rxdp 
)

vxge_hw_ring_rxd_post - Post descriptor on the ring.

: Handle to the ring object used for receive : Descriptor obtained via vxge_hw_ring_rxd_reserve().

Post descriptor on the ring. Prior to posting the descriptor should be filled in accordance with Host/Titan interface specification for a given service (LL, etc.).

Definition at line 322 of file vxge_traffic.c.

References vxge_hw_ring_rxd_1::control_0, and VXGE_HW_RING_RXD_LIST_OWN_ADAPTER.

Referenced by vxge_hw_ring_replenish(), and vxge_hw_vpath_poll_rx().

00324 {
00325         rxdp->control_0 = VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
00326 }

static void __vxge_hw_non_offload_db_post ( struct __vxge_hw_fifo *  fifo,
u64  txdl_ptr,
u32  num_txds 
) [static]

__vxge_hw_non_offload_db_post - Post non offload doorbell

: fifohandle : The starting location of the TxDL in host memory : The highest TxD in this TxDL (0 to 255 means 1 to 256)

This function posts a non-offload doorbell to doorbell FIFO

Definition at line 338 of file vxge_traffic.c.

References __vxge_hw_non_offload_db_wrapper::control_0, __vxge_hw_fifo::nofl_db, __vxge_hw_non_offload_db_wrapper::txdl_ptr, VXGE_HW_NODBW_LAST_TXD_NUMBER, VXGE_HW_NODBW_TYPE, VXGE_HW_NODBW_TYPE_NODBW, wmb, and writeq.

Referenced by vxge_hw_fifo_txdl_post().

00340 {
00341         writeq(VXGE_HW_NODBW_TYPE(VXGE_HW_NODBW_TYPE_NODBW) |
00342                 VXGE_HW_NODBW_LAST_TXD_NUMBER(num_txds),
00343                 &fifo->nofl_db->control_0);
00344 
00345         wmb();
00346 
00347         writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr);
00348 
00349         wmb();
00350 }

struct vxge_hw_fifo_txd* vxge_hw_fifo_free_txdl_get ( struct __vxge_hw_fifo *  fifo  )  [read]

vxge_hw_fifo_free_txdl_get: fetch next available txd in the fifo

: tx channel handle

Definition at line 358 of file vxge_traffic.c.

References vxge_hw_fifo_txd::control_0, NULL, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::txdl, txdp, vxge_debug, VXGE_ERR, and VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER.

Referenced by vxge_xmit().

00359 {
00360         struct vxge_hw_fifo_txd *txdp;
00361 
00362         txdp = fifo->txdl + fifo->sw_offset;
00363         if (txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER) {
00364                 vxge_debug(VXGE_ERR, "%s:%d, error: txd(%d) owned by hw\n",
00365                                 __func__, __LINE__, fifo->sw_offset);
00366                 return NULL;
00367         }
00368 
00369         return txdp;
00370 }

void vxge_hw_fifo_txdl_buffer_set ( struct __vxge_hw_fifo *  fifo,
struct vxge_hw_fifo_txd *  txdp,
struct io_buffer *  iob 
)

vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the descriptor.

: Handle to the fifo object used for non offload send : Descriptor handle. : data buffer.

Definition at line 378 of file vxge_traffic.c.

References vxge_hw_fifo_txd::buffer_pointer, vxge_hw_fifo_txd::control_0, vxge_hw_fifo_txd::control_1, io_buffer::data, vxge_hw_fifo_txd::host_control, iob_len(), __vxge_hw_fifo::tx_intr_num, virt_to_bus(), VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST, VXGE_HW_FIFO_TXD_BUFFER_SIZE, VXGE_HW_FIFO_TXD_GATHER_CODE, VXGE_HW_FIFO_TXD_INT_NUMBER, and VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST.

Referenced by vxge_xmit().

00381 {
00382         txdp->control_0 = VXGE_HW_FIFO_TXD_GATHER_CODE(
00383                         VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST);
00384         txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(iob_len(iob));
00385 
00386         txdp->control_1 = VXGE_HW_FIFO_TXD_INT_NUMBER(fifo->tx_intr_num);
00387         txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
00388 
00389         txdp->host_control = (intptr_t)iob;
00390         txdp->buffer_pointer = virt_to_bus(iob->data);
00391 }

void vxge_hw_fifo_txdl_post ( struct __vxge_hw_fifo *  fifo,
struct vxge_hw_fifo_txd *  txdp 
)

vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.

: Handle to the fifo object used for non offload send : Tx Descriptor

Post descriptor on the 'fifo' type channel for transmission. Prior to posting the descriptor should be filled in accordance with Host/Titan interface specification for a given service (LL, etc.).

Definition at line 403 of file vxge_traffic.c.

References __vxge_hw_non_offload_db_post(), vxge_hw_fifo_txd::control_0, __vxge_hw_fifo::sw_offset, virt_to_bus(), VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER, and vxge_hw_fifo_txd_offset_up().

Referenced by vxge_xmit().

00405 {
00406         txdp->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER;
00407 
00408         __vxge_hw_non_offload_db_post(fifo, (u64) virt_to_bus(txdp), 0);
00409 
00410         vxge_hw_fifo_txd_offset_up(&fifo->sw_offset);
00411 }

static enum vxge_hw_status __vxge_hw_vpath_alarm_process ( struct __vxge_hw_virtualpath *  vpath  )  [static]

Definition at line 421 of file vxge_traffic.c.

References vxge_hw_vpath_reg::asic_ntwk_vp_err_mask, vxge_hw_vpath_reg::asic_ntwk_vp_err_reg, __vxge_hw_virtualpath::hldev, net_device::name, __vxge_hw_device::ndev, netdev_link_down(), netdev_link_up(), NULL, readq, __vxge_hw_virtualpath::vp_reg, vxge_hw_vpath_reg::vpath_general_int_status, vxge_debug, VXGE_ERR, VXGE_HW_ALL_FOXES, VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT, VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR, VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK, VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR, VXGE_HW_ERR_SLOT_FREEZE, VXGE_HW_FAIL, VXGE_HW_INTR_MASK_ALL, VXGE_HW_OK, VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT, VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT, VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT, VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT, VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT, VXGE_INFO, VXGE_INTR, writeq, and vxge_hw_vpath_reg::xgmac_vp_int_status.

Referenced by vxge_hw_device_begin_irq().

00423 {
00424         u64 val64;
00425         u64 alarm_status;
00426         enum vxge_hw_status status = VXGE_HW_OK;
00427         struct __vxge_hw_device *hldev = NULL;
00428         struct vxge_hw_vpath_reg *vp_reg;
00429 
00430         hldev = vpath->hldev;
00431         vp_reg = vpath->vp_reg;
00432         alarm_status = readq(&vp_reg->vpath_general_int_status);
00433 
00434         if (alarm_status == VXGE_HW_ALL_FOXES) {
00435 
00436                 vxge_debug(VXGE_ERR, "%s: %s:%d, slot freeze error\n",
00437                         hldev->ndev->name, __func__, __LINE__);
00438                 status = VXGE_HW_ERR_SLOT_FREEZE;
00439                 goto out;
00440         }
00441 
00442         if (alarm_status & ~(
00443                 VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT |
00444                 VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT |
00445                 VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
00446                 VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
00447 
00448                 vxge_debug(VXGE_ERR, "%s: %s:%d, Unknown vpath alarm\n",
00449                         hldev->ndev->name, __func__, __LINE__);
00450                 status = VXGE_HW_FAIL;
00451                 goto out;
00452         }
00453 
00454         if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
00455 
00456                 val64 = readq(&vp_reg->xgmac_vp_int_status);
00457 
00458                 if (val64 &
00459                 VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) {
00460 
00461                         val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
00462 
00463                         if (((val64 &
00464                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) &&
00465                             (!(val64 &
00466                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) ||
00467                             ((val64 &
00468                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
00469                                 && (!(val64 &
00470                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
00471                         ))) {
00472                                 writeq(VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT,
00473                                         &vp_reg->asic_ntwk_vp_err_mask);
00474 
00475                                 netdev_link_down(hldev->ndev);
00476                                 vxge_debug(VXGE_INTR, "%s: %s:%d link down\n",
00477                                         hldev->ndev->name, __func__, __LINE__);
00478                         }
00479 
00480                         if (((val64 &
00481                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) &&
00482                             (!(val64 &
00483                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) ||
00484                             ((val64 &
00485                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
00486                                 && (!(val64 &
00487                                 VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
00488                         ))) {
00489                                 writeq(VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK,
00490                                         &vp_reg->asic_ntwk_vp_err_mask);
00491 
00492                                 netdev_link_up(hldev->ndev);
00493                                 vxge_debug(VXGE_INTR, "%s: %s:%d link up\n",
00494                                         hldev->ndev->name, __func__, __LINE__);
00495                         }
00496 
00497                         writeq(VXGE_HW_INTR_MASK_ALL,
00498                                 &vp_reg->asic_ntwk_vp_err_reg);
00499                 }
00500         } else {
00501                 vxge_debug(VXGE_INFO, "%s: %s:%d unhandled alarm %llx\n",
00502                                 hldev->ndev->name, __func__, __LINE__,
00503                                 alarm_status);
00504         }
00505 out:
00506         return status;
00507 }

void vxge_hw_device_clear_tx_rx ( struct __vxge_hw_device *  hldev  ) 

vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the condition that has caused the Tx and RX interrupt.

: HW device.

Acknowledge (that is, clear) the condition that has caused the Tx and Rx interrupt. See also: vxge_hw_device_begin_irq(), vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx().

Definition at line 519 of file vxge_traffic.c.

References __vxge_hw_pio_mem_write32_upper(), __vxge_hw_device::common_reg, __vxge_hw_device::tim_int_mask0, __vxge_hw_device::tim_int_mask1, vxge_hw_common_reg::tim_int_status0, vxge_hw_common_reg::tim_int_status1, VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, and writeq.

Referenced by vxge_hw_device_begin_irq().

00520 {
00521 
00522         if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
00523                         (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
00524                 writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
00525                         hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]),
00526                         &hldev->common_reg->tim_int_status0);
00527         }
00528 
00529         if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
00530                         (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
00531                 __vxge_hw_pio_mem_write32_upper(
00532                         (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
00533                         hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]),
00534                         &hldev->common_reg->tim_int_status1);
00535         }
00536 
00537         return;
00538 }

enum vxge_hw_status vxge_hw_device_begin_irq ( struct __vxge_hw_device *  hldev  ) 

vxge_hw_device_begin_irq - Begin IRQ processing.

: HW device handle.

The function performs two actions, It first checks whether (shared IRQ) the interrupt was raised by the device. Next, it masks the device interrupts.

Note: vxge_hw_device_begin_irq() does not flush MMIO writes through the bridge. Therefore, two back-to-back interrupts are potentially possible.

Returns: 0, if the interrupt is not "ours" (note that in this case the device remain enabled). Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter status.

Definition at line 558 of file vxge_traffic.c.

References __vxge_hw_vpath_alarm_process(), vxge_hw_common_reg::adapter_status, __vxge_hw_device::common_reg, net_device::name, __vxge_hw_device::ndev, readq, vxge_hw_common_reg::titan_general_int_status, __vxge_hw_device::virtual_path, __vxge_hw_device::vpaths_deployed, vxge_debug, VXGE_ERR, VXGE_HW_ALL_FOXES, vxge_hw_device_clear_tx_rx(), VXGE_HW_ERR_SLOT_FREEZE, VXGE_HW_ERR_WRONG_IRQ, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT, and VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT.

Referenced by vxge_poll().

00559 {
00560         u64 val64;
00561         u64 adapter_status;
00562         u64 vpath_mask;
00563         enum vxge_hw_status ret = VXGE_HW_OK;
00564 
00565         val64 = readq(&hldev->common_reg->titan_general_int_status);
00566 
00567         if (!val64) {
00568                 ret = VXGE_HW_ERR_WRONG_IRQ;
00569                 goto exit;
00570         }
00571 
00572         if (val64 == VXGE_HW_ALL_FOXES) {
00573 
00574                 adapter_status = readq(&hldev->common_reg->adapter_status);
00575 
00576                 if (adapter_status == VXGE_HW_ALL_FOXES) {
00577 
00578                         vxge_debug(VXGE_ERR, "%s: %s:%d critical error "
00579                                 "occurred\n", hldev->ndev->name,
00580                                 __func__, __LINE__);
00581                         ret = VXGE_HW_ERR_SLOT_FREEZE;
00582                         goto exit;
00583                 }
00584         }
00585 
00586         vpath_mask = hldev->vpaths_deployed >>
00587                                 (64 - VXGE_HW_MAX_VIRTUAL_PATHS);
00588         if (val64 & VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(
00589                                 vpath_mask))
00590                 vxge_hw_device_clear_tx_rx(hldev);
00591 
00592         if (val64 & VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)
00593                 ret = __vxge_hw_vpath_alarm_process(&hldev->virtual_path);
00594 
00595 exit:
00596         return ret;
00597 }

void vxge_hw_vpath_doorbell_rx ( struct __vxge_hw_ring *  ring  ) 

vxge_hw_vpath_doorbell_rx - Indicates to hw the qwords of receive descriptors posted.

: Handle to the ring object used for receive

The function writes the number of qwords of rxds posted during replishment. Since the function is called frequently, a flush is not required to post the write transaction. At the very least, the previous write will be flushed once the subsequent write is made.

Returns: None.

Definition at line 611 of file vxge_traffic.c.

References __vxge_hw_ring::doorbell_cnt, vxge_hw_vpath_reg::prc_rxd_doorbell, __vxge_hw_ring::rxd_qword_limit, __vxge_hw_ring::total_db_cnt, u32, __vxge_hw_ring::vp_reg, VXGE_HW_MAX_RXDS_PER_BLOCK_1, VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT, VXGE_HW_RING_RXD_QWORDS_MODE_1, wmb, and writeq.

Referenced by vxge_hw_vpath_poll_rx().

00612 {
00613         u32 rxds_qw_per_block = VXGE_HW_MAX_RXDS_PER_BLOCK_1 *
00614                 VXGE_HW_RING_RXD_QWORDS_MODE_1;
00615 
00616         ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
00617 
00618         ring->total_db_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
00619 
00620         if (ring->total_db_cnt >= rxds_qw_per_block) {
00621                 /* For each block add 4 more qwords */
00622                 ring->doorbell_cnt += VXGE_HW_RING_RXD_QWORDS_MODE_1;
00623 
00624                 /* Reset total count */
00625                 ring->total_db_cnt -= rxds_qw_per_block;
00626         }
00627 
00628         if (ring->doorbell_cnt >= ring->rxd_qword_limit) {
00629                 wmb();
00630                 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(
00631                         ring->doorbell_cnt),
00632                         &ring->vp_reg->prc_rxd_doorbell);
00633                 ring->doorbell_cnt = 0;
00634         }
00635 }

enum vxge_hw_status vxge_hw_vpath_poll_rx ( struct __vxge_hw_ring *  ring  ) 

Definition at line 645 of file vxge_traffic.c.

References alloc_iob(), vxge_hw_ring_rxd_1::control_0, vxge_hw_ring_rxd_1::control_1, io_buffer::data, EINVAL, ENOMEM, ETH_FCS_LEN, __vxge_hw_virtualpath::hldev, vxge_hw_ring_rxd_1::host_control, iob_put, memcpy, net_device::name, __vxge_hw_device::ndev, netdev_rx(), netdev_rx_err(), NULL, __vxge_hw_ring_block::rxd, rxd, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, u16, __vxge_hw_device::vdev, __vxge_hw_ring::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_FAIL, VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS, VXGE_HW_OK, VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET, vxge_hw_ring_rxd_1b_set(), VXGE_HW_RING_RXD_LIST_OWN_ADAPTER, vxge_hw_ring_rxd_offset_up(), vxge_hw_ring_rxd_post(), VXGE_HW_RING_RXD_T_CODE_GET, VXGE_HW_RING_T_CODE_OK, vxge_hw_vpath_doorbell_rx(), VXGE_INFO, and VXGE_LL_MAX_FRAME_SIZE.

Referenced by vxge_poll().

00646 {
00647         struct __vxge_hw_device *hldev;
00648         enum vxge_hw_status status = VXGE_HW_OK;
00649         struct vxge_hw_ring_rxd_1 *rxd;
00650         unsigned int len;
00651         enum vxge_hw_ring_tcode tcode;
00652         struct io_buffer *rx_iob, *iobuf = NULL;
00653         u16 poll_count = 0;
00654 
00655         hldev = ring->vpathh->hldev;
00656 
00657         do {
00658                 rxd = &ring->rxdl->rxd[ring->rxd_offset];
00659                 tcode = VXGE_HW_RING_RXD_T_CODE_GET(rxd->control_0);
00660 
00661                 /* if tcode is VXGE_HW_RING_T_CODE_FRM_DROP, it is
00662                  * possible the ownership bit still set to adapter
00663                  */
00664                 if ((rxd->control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER)
00665                         && (tcode == VXGE_HW_RING_T_CODE_OK)) {
00666 
00667                         status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
00668                         goto err0;
00669                 }
00670 
00671                 vxge_debug(VXGE_INFO, "%s: rx frame received at offset %d\n",
00672                         hldev->ndev->name, ring->rxd_offset);
00673 
00674                 if (tcode != VXGE_HW_RING_T_CODE_OK) {
00675                         netdev_rx_err(hldev->ndev, NULL, -EINVAL);
00676                         vxge_debug(VXGE_ERR, "%s:%d, rx error tcode %d\n",
00677                                 __func__, __LINE__, tcode);
00678                         status = VXGE_HW_FAIL;
00679                         goto err1;
00680                 }
00681 
00682                 iobuf = (struct io_buffer *)(intptr_t)rxd->host_control;
00683 
00684                 len = VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxd->control_1);
00685                 len -= ETH_FCS_LEN;
00686 
00687                 rx_iob = alloc_iob(len);
00688                 if (!rx_iob) {
00689                         netdev_rx_err(hldev->ndev, NULL, -ENOMEM);
00690                         vxge_debug(VXGE_ERR, "%s:%d, alloc_iob error\n",
00691                                 __func__, __LINE__);
00692                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
00693                         goto err1;
00694                 }
00695 
00696                 memcpy(iob_put(rx_iob, len), iobuf->data, len);
00697                 /* Add this packet to the receive queue. */
00698                 netdev_rx(hldev->ndev, rx_iob);
00699 
00700 err1:
00701                 /* repost the rxd */
00702                 rxd->control_0 = rxd->control_1 = 0;
00703                 vxge_hw_ring_rxd_1b_set(rxd, iobuf,
00704                                 VXGE_LL_MAX_FRAME_SIZE(hldev->vdev));
00705                 vxge_hw_ring_rxd_post(ring, rxd);
00706 
00707                 /* repost the qword count for doorbell */
00708                 vxge_hw_vpath_doorbell_rx(ring);
00709 
00710                 /* increment the descriptor offset */
00711                 vxge_hw_ring_rxd_offset_up(&ring->rxd_offset);
00712 
00713         } while (++poll_count < ring->rx_poll_weight);
00714 err0:
00715         return status;
00716 }

enum vxge_hw_status vxge_hw_vpath_poll_tx ( struct __vxge_hw_fifo *  fifo  ) 

vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process the same.

: Handle to the fifo object used for non offload send

The function polls the Tx for the completed descriptors and calls the driver via supplied completion callback.

Definition at line 726 of file vxge_traffic.c.

References vxge_hw_fifo_txd::control_0, vxge_hw_fifo_txd::host_control, __vxge_hw_fifo::hw_offset, __vxge_hw_fifo::txdl, txdp, VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER, vxge_hw_fifo_txd_offset_up(), VXGE_HW_FIFO_TXD_T_CODE_GET, VXGE_HW_OK, and vxge_xmit_compl().

Referenced by vxge_poll().

00727 {
00728         enum vxge_hw_status status = VXGE_HW_OK;
00729         struct vxge_hw_fifo_txd *txdp;
00730 
00731         txdp = fifo->txdl + fifo->hw_offset;
00732         if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)
00733                 && (txdp->host_control)) {
00734 
00735                 vxge_xmit_compl(fifo, txdp,
00736                         VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0));
00737 
00738                 vxge_hw_fifo_txd_offset_up(&fifo->hw_offset);
00739         }
00740 
00741         return status;
00742 }

Generated on Tue Apr 6 20:01:46 2010 for gPXE by  doxygen 1.5.7.1