#include <stdlib.h>#include <stdio.h>#include <gpxe/malloc.h>#include <gpxe/iobuf.h>#include <byteswap.h>#include "vxge_traffic.h"#include "vxge_config.h"#include "vxge_main.h"Go to the source code of this file.
| FILE_LICENCE | ( | GPL2_ONLY | ) |
| void vxge_hw_vpath_set_zero_rx_frm_len | ( | struct __vxge_hw_device * | hldev | ) |
Definition at line 28 of file vxge_config.c.
References readq, vxge_hw_vpath_reg::rxmac_vcfg0, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN, and writeq.
Referenced by vxge_close().
00029 { 00030 u64 val64; 00031 struct __vxge_hw_virtualpath *vpath; 00032 struct vxge_hw_vpath_reg __iomem *vp_reg; 00033 00034 vpath = &hldev->virtual_path; 00035 vp_reg = vpath->vp_reg; 00036 00037 val64 = readq(&vp_reg->rxmac_vcfg0); 00038 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff); 00039 writeq(val64, &vp_reg->rxmac_vcfg0); 00040 val64 = readq(&vp_reg->rxmac_vcfg0); 00041 return; 00042 }
| enum vxge_hw_status vxge_hw_set_fw_api | ( | struct __vxge_hw_device * | hldev, | |
| u64 | vp_id, | |||
| u32 | action, | |||
| u32 | offset, | |||
| u64 | data0, | |||
| u64 | data1 | |||
| ) |
Definition at line 45 of file vxge_config.c.
References __vxge_hw_device_register_poll(), readq, vxge_hw_vpath_reg::rts_access_steer_ctrl, vxge_hw_vpath_reg::rts_access_steer_data0, vxge_hw_vpath_reg::rts_access_steer_data1, u32, __vxge_hw_device::vpath_reg, VXGE_HW_DEF_DEVICE_POLL_MILLIS, VXGE_HW_FAIL, VXGE_HW_OK, VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION, VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL, VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO, VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET, VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS, VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, WAIT_FACTOR, wmb, and writeq.
Referenced by vxge_hw_get_func_mode().
00051 { 00052 enum vxge_hw_status status = VXGE_HW_OK; 00053 u64 val64; 00054 u32 fw_memo = VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO; 00055 00056 struct vxge_hw_vpath_reg __iomem *vp_reg; 00057 00058 vp_reg = (struct vxge_hw_vpath_reg __iomem *)hldev->vpath_reg[vp_id]; 00059 00060 writeq(data0, &vp_reg->rts_access_steer_data0); 00061 writeq(data1, &vp_reg->rts_access_steer_data1); 00062 00063 wmb(); 00064 00065 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | 00066 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) | 00067 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) | 00068 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE; 00069 00070 writeq(val64, &vp_reg->rts_access_steer_ctrl); 00071 00072 wmb(); 00073 00074 status = __vxge_hw_device_register_poll( 00075 &vp_reg->rts_access_steer_ctrl, 00076 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, 00077 WAIT_FACTOR * 00078 VXGE_HW_DEF_DEVICE_POLL_MILLIS); 00079 00080 if (status != VXGE_HW_OK) 00081 return VXGE_HW_FAIL; 00082 00083 val64 = readq(&vp_reg->rts_access_steer_ctrl); 00084 00085 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) 00086 status = VXGE_HW_OK; 00087 else 00088 status = VXGE_HW_FAIL; 00089 00090 return status; 00091 }
| enum vxge_hw_status vxge_hw_get_func_mode | ( | struct __vxge_hw_device * | hldev, | |
| u32 * | func_mode | |||
| ) |
Definition at line 95 of file vxge_config.c.
References __vxge_hw_device::first_vp_id, readq, vxge_hw_vpath_reg::rts_access_steer_data0, __vxge_hw_device::vpath_reg, VXGE_HW_FW_API_GET_FUNC_MODE, VXGE_HW_GET_FUNC_MODE_VAL, VXGE_HW_OK, and vxge_hw_set_fw_api().
Referenced by vxge_probe().
00096 { 00097 enum vxge_hw_status status = VXGE_HW_OK; 00098 struct vxge_hw_vpath_reg __iomem *vp_reg; 00099 u64 val64; 00100 int vp_id; 00101 00102 /* get the first vpath number assigned to this function */ 00103 vp_id = hldev->first_vp_id; 00104 00105 vp_reg = (struct vxge_hw_vpath_reg __iomem *)hldev->vpath_reg[vp_id]; 00106 00107 status = vxge_hw_set_fw_api(hldev, vp_id, 00108 VXGE_HW_FW_API_GET_FUNC_MODE, 0, 0, 0); 00109 00110 if (status == VXGE_HW_OK) { 00111 val64 = readq(&vp_reg->rts_access_steer_data0); 00112 *func_mode = VXGE_HW_GET_FUNC_MODE_VAL(val64); 00113 } 00114 00115 return status; 00116 }
| void __vxge_hw_device_pci_e_init | ( | struct __vxge_hw_device * | hldev | ) |
Definition at line 124 of file vxge_config.c.
References PCI_COMMAND, pci_read_config_word(), pci_write_config_word(), __vxge_hw_device::pdev, u16, and vxge_trace.
Referenced by vxge_hw_device_initialize().
00125 { 00126 u16 cmd = 0; 00127 struct pci_device *pdev = hldev->pdev; 00128 00129 vxge_trace(); 00130 00131 /* Set the PErr Repconse bit and SERR in PCI command register. */ 00132 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 00133 cmd |= 0x140; 00134 pci_write_config_word(pdev, PCI_COMMAND, cmd); 00135 00136 return; 00137 }
| enum vxge_hw_status __vxge_hw_device_register_poll | ( | void __iomem * | reg, | |
| u64 | mask, | |||
| u32 | max_millis | |||
| ) |
Definition at line 145 of file vxge_config.c.
References readq, u32, udelay(), VXGE_HW_FAIL, and VXGE_HW_OK.
Referenced by __vxge_hw_device_vpath_reset_in_prog_check(), __vxge_hw_pio_mem_write64(), __vxge_hw_vpath_pci_read(), __vxge_hw_vpath_reset_check(), and vxge_hw_set_fw_api().
00146 { 00147 u64 val64; 00148 u32 i = 0; 00149 enum vxge_hw_status ret = VXGE_HW_FAIL; 00150 00151 udelay(10); 00152 00153 do { 00154 val64 = readq(reg); 00155 if (!(val64 & mask)) 00156 return VXGE_HW_OK; 00157 udelay(100); 00158 } while (++i <= 9); 00159 00160 i = 0; 00161 do { 00162 val64 = readq(reg); 00163 if (!(val64 & mask)) 00164 return VXGE_HW_OK; 00165 udelay(1000); 00166 } while (++i <= max_millis); 00167 00168 return ret; 00169 }
| enum vxge_hw_status __vxge_hw_device_vpath_reset_in_prog_check | ( | u64 __iomem * | vpath_rst_in_prog | ) |
Definition at line 176 of file vxge_config.c.
References __vxge_hw_device_register_poll(), VXGE_HW_DEF_DEVICE_POLL_MILLIS, VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG, and vxge_trace.
Referenced by __vxge_hw_device_reg_addr_get(), and vxge_hw_device_hw_info_get().
00177 { 00178 enum vxge_hw_status status; 00179 00180 vxge_trace(); 00181 00182 status = __vxge_hw_device_register_poll(vpath_rst_in_prog, 00183 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff), 00184 VXGE_HW_DEF_DEVICE_POLL_MILLIS); 00185 return status; 00186 }
| struct vxge_hw_toc_reg __iomem* __vxge_hw_device_toc_get | ( | void __iomem * | bar0 | ) | [read] |
Definition at line 194 of file vxge_config.c.
References __vxge_hw_legacy_swapper_set(), NULL, readq, vxge_hw_legacy_reg::toc_first_pointer, and VXGE_HW_OK.
Referenced by __vxge_hw_device_reg_addr_get(), and vxge_hw_device_hw_info_get().
00195 { 00196 u64 val64; 00197 struct vxge_hw_toc_reg __iomem *toc = NULL; 00198 enum vxge_hw_status status; 00199 00200 struct vxge_hw_legacy_reg __iomem *legacy_reg = 00201 (struct vxge_hw_legacy_reg __iomem *)bar0; 00202 00203 status = __vxge_hw_legacy_swapper_set(legacy_reg); 00204 if (status != VXGE_HW_OK) 00205 goto exit; 00206 00207 val64 = readq(&legacy_reg->toc_first_pointer); 00208 toc = (struct vxge_hw_toc_reg __iomem *)(bar0+val64); 00209 exit: 00210 return toc; 00211 }
| enum vxge_hw_status __vxge_hw_device_reg_addr_get | ( | struct __vxge_hw_device * | hldev | ) |
Definition at line 220 of file vxge_config.c.
References __vxge_hw_device_toc_get(), __vxge_hw_device_vpath_reset_in_prog_check(), __vxge_hw_device::bar0, __vxge_hw_device::common_reg, __vxge_hw_device::kdfc, __vxge_hw_device::legacy_reg, __vxge_hw_device::mrpcim_reg, NULL, readq, __vxge_hw_device::srpcim_reg, vxge_hw_toc_reg::toc_common_pointer, vxge_hw_toc_reg::toc_kdfc, vxge_hw_toc_reg::toc_mrpcim_pointer, __vxge_hw_device::toc_reg, vxge_hw_toc_reg::toc_srpcim_pointer, vxge_hw_toc_reg::toc_vpath_pointer, vxge_hw_toc_reg::toc_vpmgmt_pointer, u32, u8, __vxge_hw_device::vpath_reg, vxge_hw_common_reg::vpath_rst_in_prog, __vxge_hw_device::vpmgmt_reg, VXGE_HW_FAIL, VXGE_HW_OK, VXGE_HW_TITAN_SRPCIM_REG_SPACES, VXGE_HW_TITAN_VPATH_REG_SPACES, VXGE_HW_TITAN_VPMGMT_REG_SPACES, VXGE_HW_TOC_GET_KDFC_INITIAL_BIR, and VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET.
Referenced by vxge_hw_device_initialize().
00221 { 00222 u64 val64; 00223 u32 i; 00224 enum vxge_hw_status status = VXGE_HW_OK; 00225 00226 hldev->legacy_reg = (struct vxge_hw_legacy_reg __iomem *)hldev->bar0; 00227 00228 hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0); 00229 if (hldev->toc_reg == NULL) { 00230 status = VXGE_HW_FAIL; 00231 goto exit; 00232 } 00233 00234 val64 = readq(&hldev->toc_reg->toc_common_pointer); 00235 hldev->common_reg = 00236 (struct vxge_hw_common_reg __iomem *)(hldev->bar0 + val64); 00237 00238 val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer); 00239 hldev->mrpcim_reg = 00240 (struct vxge_hw_mrpcim_reg __iomem *)(hldev->bar0 + val64); 00241 00242 for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) { 00243 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]); 00244 hldev->srpcim_reg[i] = 00245 (struct vxge_hw_srpcim_reg __iomem *) 00246 (hldev->bar0 + val64); 00247 } 00248 00249 for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) { 00250 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]); 00251 hldev->vpmgmt_reg[i] = 00252 (struct vxge_hw_vpmgmt_reg __iomem *)(hldev->bar0 + val64); 00253 } 00254 00255 for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) { 00256 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]); 00257 hldev->vpath_reg[i] = 00258 (struct vxge_hw_vpath_reg __iomem *) 00259 (hldev->bar0 + val64); 00260 } 00261 00262 val64 = readq(&hldev->toc_reg->toc_kdfc); 00263 00264 switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) { 00265 case 0: 00266 hldev->kdfc = (u8 __iomem *)(hldev->bar0 + 00267 VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64)); 00268 break; 00269 default: 00270 break; 00271 } 00272 00273 status = __vxge_hw_device_vpath_reset_in_prog_check( 00274 (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog); 00275 exit: 00276 return status; 00277 }
Definition at line 284 of file vxge_config.c.
References u32, VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM, VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM, VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH, VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION, VXGE_HW_MR_SR_VH0_INVALID_CONFIG, VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION, VXGE_HW_NO_MR_SR_VH0_FUNCTION0, VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION, VXGE_HW_SR_VH_FUNCTION0, VXGE_HW_SR_VH_VIRTUAL_FUNCTION, and VXGE_HW_VH_NORMAL_FUNCTION.
Referenced by __vxge_hw_device_host_info_get(), and vxge_hw_device_hw_info_get().
00285 { 00286 u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH; 00287 00288 switch (host_type) { 00289 case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION: 00290 if (func_id == 0) { 00291 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | 00292 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; 00293 } 00294 break; 00295 case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION: 00296 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | 00297 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; 00298 break; 00299 case VXGE_HW_NO_MR_SR_VH0_FUNCTION0: 00300 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | 00301 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; 00302 break; 00303 case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION: 00304 case VXGE_HW_SR_VH_VIRTUAL_FUNCTION: 00305 case VXGE_HW_MR_SR_VH0_INVALID_CONFIG: 00306 break; 00307 case VXGE_HW_SR_VH_FUNCTION0: 00308 case VXGE_HW_VH_NORMAL_FUNCTION: 00309 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; 00310 break; 00311 } 00312 00313 return access_rights; 00314 }
| void __vxge_hw_device_host_info_get | ( | struct __vxge_hw_device * | hldev | ) |
Definition at line 320 of file vxge_config.c.
References __vxge_hw_device_access_rights_get(), __vxge_hw_vpath_func_id_get(), __vxge_hw_device::access_rights, __vxge_hw_device::common_reg, __vxge_hw_device::first_vp_id, __vxge_hw_device::func_id, __vxge_hw_device::host_type, vxge_hw_common_reg::host_type_assignments, readq, u32, vxge_hw_common_reg::vpath_assignments, __vxge_hw_device::vpath_assignments, __vxge_hw_device::vpmgmt_reg, VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS, VXGE_HW_MAX_VIRTUAL_PATHS, and vxge_mBIT.
Referenced by vxge_hw_device_initialize().
00321 { 00322 u64 val64; 00323 u32 i; 00324 00325 val64 = readq(&hldev->common_reg->host_type_assignments); 00326 00327 hldev->host_type = 00328 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64); 00329 00330 hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments); 00331 00332 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 00333 00334 if (!(hldev->vpath_assignments & vxge_mBIT(i))) 00335 continue; 00336 00337 hldev->func_id = 00338 __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]); 00339 00340 hldev->access_rights = __vxge_hw_device_access_rights_get( 00341 hldev->host_type, hldev->func_id); 00342 00343 hldev->first_vp_id = i; 00344 break; 00345 } 00346 00347 return; 00348 }
| enum vxge_hw_status vxge_hw_device_hw_info_get | ( | void __iomem * | bar0, | |
| struct vxge_hw_device_hw_info * | hw_info | |||
| ) |
vxge_hw_device_hw_info_get - Get the hw information Returns the vpath mask that has the bits set for each vpath allocated for the driver, FW version information and the first mac addresse for each vpath
Definition at line 357 of file vxge_config.c.
References __vxge_hw_device_access_rights_get(), __vxge_hw_device_toc_get(), __vxge_hw_device_vpath_reset_in_prog_check(), __vxge_hw_vpath_addr_get(), __vxge_hw_vpath_card_info_get(), __vxge_hw_vpath_func_id_get(), __vxge_hw_vpath_fw_ver_get(), vxge_hw_device_hw_info::func_id, vxge_hw_device_hw_info::host_type, vxge_hw_common_reg::host_type_assignments, memset(), NULL, readq, vxge_hw_toc_reg::toc_common_pointer, vxge_hw_toc_reg::toc_mrpcim_pointer, vxge_hw_toc_reg::toc_vpath_pointer, vxge_hw_toc_reg::toc_vpmgmt_pointer, u32, vxge_hw_common_reg::vpath_assignments, vxge_hw_device_hw_info::vpath_mask, vxge_hw_common_reg::vpath_rst_in_prog, VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM, VXGE_HW_ERR_CRITICAL, VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, vxge_mBIT, vxge_trace, wmb, writeq, and vxge_hw_mrpcim_reg::xgmac_gen_fw_memo_mask.
Referenced by vxge_probe().
00359 { 00360 u32 i; 00361 u64 val64; 00362 struct vxge_hw_toc_reg __iomem *toc; 00363 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg; 00364 struct vxge_hw_common_reg __iomem *common_reg; 00365 struct vxge_hw_vpath_reg __iomem *vpath_reg; 00366 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; 00367 enum vxge_hw_status status; 00368 00369 vxge_trace(); 00370 00371 memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info)); 00372 00373 toc = __vxge_hw_device_toc_get(bar0); 00374 if (toc == NULL) { 00375 status = VXGE_HW_ERR_CRITICAL; 00376 goto exit; 00377 } 00378 00379 val64 = readq(&toc->toc_common_pointer); 00380 common_reg = (struct vxge_hw_common_reg __iomem *)(bar0 + val64); 00381 00382 status = __vxge_hw_device_vpath_reset_in_prog_check( 00383 (u64 __iomem *)&common_reg->vpath_rst_in_prog); 00384 if (status != VXGE_HW_OK) 00385 goto exit; 00386 00387 hw_info->vpath_mask = readq(&common_reg->vpath_assignments); 00388 00389 val64 = readq(&common_reg->host_type_assignments); 00390 00391 hw_info->host_type = 00392 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64); 00393 00394 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 00395 00396 if (!((hw_info->vpath_mask) & vxge_mBIT(i))) 00397 continue; 00398 00399 val64 = readq(&toc->toc_vpmgmt_pointer[i]); 00400 00401 vpmgmt_reg = (struct vxge_hw_vpmgmt_reg __iomem *) 00402 (bar0 + val64); 00403 00404 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg); 00405 if (__vxge_hw_device_access_rights_get(hw_info->host_type, 00406 hw_info->func_id) & 00407 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) { 00408 00409 val64 = readq(&toc->toc_mrpcim_pointer); 00410 00411 mrpcim_reg = (struct vxge_hw_mrpcim_reg __iomem *) 00412 (bar0 + val64); 00413 00414 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask); 00415 wmb(); 00416 } 00417 00418 val64 = readq(&toc->toc_vpath_pointer[i]); 00419 00420 vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64); 00421 00422 status = __vxge_hw_vpath_fw_ver_get(vpath_reg, hw_info); 00423 if (status != VXGE_HW_OK) 00424 goto exit; 00425 00426 status = __vxge_hw_vpath_card_info_get(vpath_reg, hw_info); 00427 if (status != VXGE_HW_OK) 00428 goto exit; 00429 00430 break; 00431 } 00432 00433 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 00434 00435 if (!((hw_info->vpath_mask) & vxge_mBIT(i))) 00436 continue; 00437 00438 val64 = readq(&toc->toc_vpath_pointer[i]); 00439 vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64); 00440 00441 status = __vxge_hw_vpath_addr_get(vpath_reg, 00442 hw_info->mac_addrs[i], 00443 hw_info->mac_addr_masks[i]); 00444 if (status != VXGE_HW_OK) 00445 goto exit; 00446 } 00447 exit: 00448 return status; 00449 }
| enum vxge_hw_status vxge_hw_device_initialize | ( | struct __vxge_hw_device ** | devh, | |
| void * | bar0, | |||
| struct pci_device * | pdev, | |||
| u8 | titan1 | |||
| ) |
Definition at line 461 of file vxge_config.c.
References __vxge_hw_device_host_info_get(), __vxge_hw_device_pci_e_init(), __vxge_hw_device_reg_addr_get(), __vxge_hw_device::bar0, __vxge_hw_device::magic, NULL, __vxge_hw_device::pdev, __vxge_hw_device::titan1, vxge_debug, VXGE_ERR, VXGE_HW_DEVICE_MAGIC, vxge_hw_device_terminate(), VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_OK, vxge_trace, and zalloc().
Referenced by vxge_probe().
00466 { 00467 struct __vxge_hw_device *hldev = NULL; 00468 enum vxge_hw_status status = VXGE_HW_OK; 00469 00470 vxge_trace(); 00471 00472 hldev = (struct __vxge_hw_device *) 00473 zalloc(sizeof(struct __vxge_hw_device)); 00474 if (hldev == NULL) { 00475 vxge_debug(VXGE_ERR, "hldev allocation failed\n"); 00476 status = VXGE_HW_ERR_OUT_OF_MEMORY; 00477 goto exit; 00478 } 00479 00480 hldev->magic = VXGE_HW_DEVICE_MAGIC; 00481 00482 hldev->bar0 = bar0; 00483 hldev->pdev = pdev; 00484 hldev->titan1 = titan1; 00485 00486 __vxge_hw_device_pci_e_init(hldev); 00487 00488 status = __vxge_hw_device_reg_addr_get(hldev); 00489 if (status != VXGE_HW_OK) { 00490 vxge_debug(VXGE_ERR, "%s:%d __vxge_hw_device_reg_addr_get " 00491 "failed\n", __func__, __LINE__); 00492 vxge_hw_device_terminate(hldev); 00493 goto exit; 00494 } 00495 00496 __vxge_hw_device_host_info_get(hldev); 00497 00498 *devh = hldev; 00499 exit: 00500 return status; 00501 }
| void vxge_hw_device_terminate | ( | struct __vxge_hw_device * | hldev | ) |
Definition at line 508 of file vxge_config.c.
References assert, free(), __vxge_hw_device::magic, VXGE_HW_DEVICE_DEAD, VXGE_HW_DEVICE_MAGIC, and vxge_trace.
Referenced by vxge_hw_device_initialize(), vxge_probe(), and vxge_remove().
00509 { 00510 vxge_trace(); 00511 00512 assert(hldev->magic == VXGE_HW_DEVICE_MAGIC); 00513 00514 hldev->magic = VXGE_HW_DEVICE_DEAD; 00515 free(hldev); 00516 }
| enum vxge_hw_status vxge_hw_ring_replenish | ( | struct __vxge_hw_ring * | ring | ) |
Definition at line 523 of file vxge_config.c.
References alloc_iob(), ARRAY_SIZE, __vxge_hw_ring::buf_per_block, vxge_hw_ring_rxd_1::control_0, vxge_hw_ring_rxd_1::control_1, free_iob(), __vxge_hw_virtualpath::hldev, __vxge_hw_ring::iobuf, NULL, offset, __vxge_hw_ring_block::pNext_RxD_Blk_physical, __vxge_hw_ring_block::reserved_2_pNext_RxD_block, __vxge_hw_ring_block::rxd, rxd, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, u8, __vxge_hw_device::vdev, virt_to_bus(), __vxge_hw_ring::vpathh, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_MAX_RXDS_PER_BLOCK_1, VXGE_HW_OK, VXGE_HW_RING_BUF_PER_BLOCK, vxge_hw_ring_rxd_1b_set(), vxge_hw_ring_rxd_post(), VXGE_LL_MAX_FRAME_SIZE, and vxge_trace.
Referenced by __vxge_hw_ring_create().
00524 { 00525 struct __vxge_hw_device *hldev; 00526 struct vxge_hw_ring_rxd_1 *rxd; 00527 enum vxge_hw_status status = VXGE_HW_OK; 00528 u8 offset = 0; 00529 struct __vxge_hw_ring_block *block; 00530 u8 i, iob_off; 00531 00532 vxge_trace(); 00533 00534 hldev = ring->vpathh->hldev; 00535 /* 00536 * We allocate all the dma buffers first and then share the 00537 * these buffers among the all rx descriptors in the block. 00538 */ 00539 for (i = 0; i < ARRAY_SIZE(ring->iobuf); i++) { 00540 ring->iobuf[i] = alloc_iob(VXGE_LL_MAX_FRAME_SIZE(hldev->vdev)); 00541 if (!ring->iobuf[i]) { 00542 while (i) { 00543 free_iob(ring->iobuf[--i]); 00544 ring->iobuf[i] = NULL; 00545 } 00546 status = VXGE_HW_ERR_OUT_OF_MEMORY; 00547 goto iobuf_err; 00548 } 00549 } 00550 00551 for (offset = 0; offset < VXGE_HW_MAX_RXDS_PER_BLOCK_1; offset++) { 00552 00553 rxd = &ring->rxdl->rxd[offset]; 00554 if (offset == (VXGE_HW_MAX_RXDS_PER_BLOCK_1 - 1)) 00555 iob_off = VXGE_HW_RING_BUF_PER_BLOCK; 00556 else 00557 iob_off = offset % ring->buf_per_block; 00558 00559 rxd->control_0 = rxd->control_1 = 0; 00560 vxge_hw_ring_rxd_1b_set(rxd, ring->iobuf[iob_off], 00561 VXGE_LL_MAX_FRAME_SIZE(hldev->vdev)); 00562 00563 vxge_hw_ring_rxd_post(ring, rxd); 00564 } 00565 /* linking the block to itself as we use only one rx block*/ 00566 block = ring->rxdl; 00567 block->reserved_2_pNext_RxD_block = (unsigned long) block; 00568 block->pNext_RxD_Blk_physical = (u64)virt_to_bus(block); 00569 00570 ring->rxd_offset = 0; 00571 iobuf_err: 00572 return status; 00573 }
| enum vxge_hw_status __vxge_hw_ring_create | ( | struct __vxge_hw_virtualpath * | vpath, | |
| struct __vxge_hw_ring * | ring | |||
| ) |
Definition at line 581 of file vxge_config.c.
References __vxge_hw_ring_delete(), __vxge_hw_ring::buf_per_block, __vxge_hw_device::common_reg, __vxge_hw_ring::common_reg, __vxge_hw_virtualpath::hldev, malloc_dma(), __vxge_hw_ring::rx_poll_weight, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxd_qword_limit, __vxge_hw_ring::rxdl, u32, __vxge_hw_ring::vp_id, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_reg, __vxge_hw_ring::vp_reg, __vxge_hw_ring::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_OK, VXGE_HW_RING_BUF_PER_BLOCK, vxge_hw_ring_replenish(), VXGE_HW_RING_RX_POLL_WEIGHT, VXGE_HW_RING_RXD_QWORD_LIMIT, and vxge_trace.
Referenced by vxge_hw_vpath_open().
00583 { 00584 enum vxge_hw_status status = VXGE_HW_OK; 00585 struct __vxge_hw_device *hldev; 00586 u32 vp_id; 00587 00588 vxge_trace(); 00589 00590 hldev = vpath->hldev; 00591 vp_id = vpath->vp_id; 00592 00593 ring->rxdl = malloc_dma(sizeof(struct __vxge_hw_ring_block), 00594 sizeof(struct __vxge_hw_ring_block)); 00595 if (!ring->rxdl) { 00596 vxge_debug(VXGE_ERR, "%s:%d malloc_dma error\n", 00597 __func__, __LINE__); 00598 status = VXGE_HW_ERR_OUT_OF_MEMORY; 00599 goto exit; 00600 } 00601 ring->rxd_offset = 0; 00602 ring->vpathh = vpath; 00603 ring->buf_per_block = VXGE_HW_RING_BUF_PER_BLOCK; 00604 ring->rx_poll_weight = VXGE_HW_RING_RX_POLL_WEIGHT; 00605 ring->vp_id = vp_id; 00606 ring->vp_reg = vpath->vp_reg; 00607 ring->common_reg = hldev->common_reg; 00608 00609 ring->rxd_qword_limit = VXGE_HW_RING_RXD_QWORD_LIMIT; 00610 00611 status = vxge_hw_ring_replenish(ring); 00612 if (status != VXGE_HW_OK) { 00613 __vxge_hw_ring_delete(ring); 00614 goto exit; 00615 } 00616 exit: 00617 return status; 00618 }
| enum vxge_hw_status __vxge_hw_ring_delete | ( | struct __vxge_hw_ring * | ring | ) |
Definition at line 624 of file vxge_config.c.
References ARRAY_SIZE, free_dma(), free_iob(), __vxge_hw_ring::iobuf, NULL, __vxge_hw_ring::rxd_offset, __vxge_hw_ring::rxdl, u8, VXGE_HW_OK, and vxge_trace.
Referenced by __vxge_hw_ring_create(), and vxge_hw_vpath_close().
00625 { 00626 u8 i; 00627 00628 vxge_trace(); 00629 00630 for (i = 0; (i < ARRAY_SIZE(ring->iobuf)) && ring->iobuf[i]; i++) { 00631 free_iob(ring->iobuf[i]); 00632 ring->iobuf[i] = NULL; 00633 } 00634 00635 if (ring->rxdl) { 00636 free_dma(ring->rxdl, sizeof(struct __vxge_hw_ring_block)); 00637 ring->rxdl = NULL; 00638 } 00639 ring->rxd_offset = 0; 00640 00641 return VXGE_HW_OK; 00642 }
| enum vxge_hw_status __vxge_hw_legacy_swapper_set | ( | struct vxge_hw_legacy_reg __iomem * | legacy_reg | ) |
Definition at line 649 of file vxge_config.c.
References readq, VXGE_HW_ERR_SWAPPER_CTRL, VXGE_HW_OK, VXGE_HW_SWAPPER_BIT_FLIPPED, VXGE_HW_SWAPPER_BYTE_SWAPPED, VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED, VXGE_HW_SWAPPER_INITIAL_VALUE, VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, vxge_trace, wmb, and writeq.
Referenced by __vxge_hw_device_toc_get(), and __vxge_hw_vpath_initialize().
00650 { 00651 u64 val64; 00652 enum vxge_hw_status status = VXGE_HW_OK; 00653 00654 vxge_trace(); 00655 00656 val64 = readq(&legacy_reg->toc_swapper_fb); 00657 00658 wmb(); 00659 00660 switch (val64) { 00661 00662 case VXGE_HW_SWAPPER_INITIAL_VALUE: 00663 return status; 00664 00665 case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED: 00666 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, 00667 &legacy_reg->pifm_rd_swap_en); 00668 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, 00669 &legacy_reg->pifm_rd_flip_en); 00670 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, 00671 &legacy_reg->pifm_wr_swap_en); 00672 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, 00673 &legacy_reg->pifm_wr_flip_en); 00674 break; 00675 00676 case VXGE_HW_SWAPPER_BYTE_SWAPPED: 00677 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, 00678 &legacy_reg->pifm_rd_swap_en); 00679 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, 00680 &legacy_reg->pifm_wr_swap_en); 00681 break; 00682 00683 case VXGE_HW_SWAPPER_BIT_FLIPPED: 00684 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, 00685 &legacy_reg->pifm_rd_flip_en); 00686 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, 00687 &legacy_reg->pifm_wr_flip_en); 00688 break; 00689 } 00690 00691 wmb(); 00692 00693 val64 = readq(&legacy_reg->toc_swapper_fb); 00694 if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE) 00695 status = VXGE_HW_ERR_SWAPPER_CTRL; 00696 00697 return status; 00698 }
| enum vxge_hw_status __vxge_hw_vpath_swapper_set | ( | struct vxge_hw_vpath_reg __iomem * | vpath_reg | ) |
Definition at line 705 of file vxge_config.c.
References readq, VXGE_HW_OK, VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN, vxge_trace, wmb, and writeq.
Referenced by __vxge_hw_vpath_initialize().
00706 { 00707 vxge_trace(); 00708 00709 #if (__BYTE_ORDER != __BIG_ENDIAN) 00710 u64 val64; 00711 00712 val64 = readq(&vpath_reg->vpath_general_cfg1); 00713 wmb(); 00714 val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN; 00715 writeq(val64, &vpath_reg->vpath_general_cfg1); 00716 wmb(); 00717 #endif 00718 return VXGE_HW_OK; 00719 }
| enum vxge_hw_status __vxge_hw_kdfc_swapper_set | ( | struct vxge_hw_legacy_reg __iomem * | legacy_reg, | |
| struct vxge_hw_vpath_reg __iomem * | vpath_reg | |||
| ) |
Definition at line 726 of file vxge_config.c.
References readq, VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0, VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1, VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2, VXGE_HW_OK, VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, vxge_trace, wmb, and writeq.
Referenced by __vxge_hw_vpath_kdfc_configure().
00729 { 00730 u64 val64; 00731 00732 vxge_trace(); 00733 00734 val64 = readq(&legacy_reg->pifm_wr_swap_en); 00735 00736 if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) { 00737 val64 = readq(&vpath_reg->kdfcctl_cfg0); 00738 wmb(); 00739 00740 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 | 00741 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 | 00742 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2; 00743 00744 writeq(val64, &vpath_reg->kdfcctl_cfg0); 00745 wmb(); 00746 } 00747 00748 return VXGE_HW_OK; 00749 }
| enum vxge_hw_status vxge_hw_vpath_strip_fcs_check | ( | struct __vxge_hw_device * | hldev, | |
| u64 | vpath_mask | |||
| ) |
Definition at line 755 of file vxge_config.c.
References readq, vxge_hw_vpmgmt_reg::rxmac_cfg0_port_vpmgmt_clone, __vxge_hw_device::vpmgmt_reg, VXGE_HW_FAIL, VXGE_HW_MAC_MAX_MAC_PORT_ID, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS, and vxge_mBIT.
Referenced by vxge_probe().
00756 { 00757 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; 00758 enum vxge_hw_status status = VXGE_HW_OK; 00759 int i = 0, j = 0; 00760 00761 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 00762 if (!((vpath_mask) & vxge_mBIT(i))) 00763 continue; 00764 vpmgmt_reg = hldev->vpmgmt_reg[i]; 00765 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) { 00766 if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j]) 00767 & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS) 00768 return VXGE_HW_FAIL; 00769 } 00770 } 00771 return status; 00772 }
| enum vxge_hw_status __vxge_hw_fifo_create | ( | struct __vxge_hw_virtualpath * | vpath, | |
| struct __vxge_hw_fifo * | fifo | |||
| ) |
Definition at line 779 of file vxge_config.c.
References __vxge_hw_fifo::depth, __vxge_hw_fifo::hw_offset, malloc_dma(), memset(), __vxge_hw_virtualpath::nofl_db, __vxge_hw_fifo::nofl_db, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::tx_intr_num, __vxge_hw_fifo::txdl, __vxge_hw_virtualpath::vp_id, __vxge_hw_fifo::vp_id, __vxge_hw_virtualpath::vp_reg, __vxge_hw_fifo::vp_reg, __vxge_hw_fifo::vpathh, vxge_debug, VXGE_ERR, VXGE_HW_ERR_OUT_OF_MEMORY, VXGE_HW_FIFO_TXD_DEPTH, VXGE_HW_MAX_INTR_PER_VP, VXGE_HW_OK, VXGE_HW_VPATH_INTR_TX, and vxge_trace.
Referenced by vxge_hw_vpath_open().
00781 { 00782 enum vxge_hw_status status = VXGE_HW_OK; 00783 00784 vxge_trace(); 00785 00786 fifo->vpathh = vpath; 00787 fifo->depth = VXGE_HW_FIFO_TXD_DEPTH; 00788 fifo->hw_offset = fifo->sw_offset = 0; 00789 fifo->nofl_db = vpath->nofl_db; 00790 fifo->vp_id = vpath->vp_id; 00791 fifo->vp_reg = vpath->vp_reg; 00792 fifo->tx_intr_num = (vpath->vp_id * VXGE_HW_MAX_INTR_PER_VP) 00793 + VXGE_HW_VPATH_INTR_TX; 00794 00795 fifo->txdl = malloc_dma(sizeof(struct vxge_hw_fifo_txd) 00796 * fifo->depth, fifo->depth); 00797 if (!fifo->txdl) { 00798 vxge_debug(VXGE_ERR, "%s:%d malloc_dma error\n", 00799 __func__, __LINE__); 00800 return VXGE_HW_ERR_OUT_OF_MEMORY; 00801 } 00802 memset(fifo->txdl, 0, sizeof(struct vxge_hw_fifo_txd) * fifo->depth); 00803 return status; 00804 }
| enum vxge_hw_status __vxge_hw_fifo_delete | ( | struct __vxge_hw_fifo * | fifo | ) |
Definition at line 810 of file vxge_config.c.
References __vxge_hw_fifo::depth, free_dma(), __vxge_hw_fifo::hw_offset, NULL, __vxge_hw_fifo::sw_offset, __vxge_hw_fifo::txdl, VXGE_HW_OK, and vxge_trace.
Referenced by vxge_hw_vpath_close(), and vxge_hw_vpath_open().
00811 { 00812 vxge_trace(); 00813 00814 if (fifo->txdl) 00815 free_dma(fifo->txdl, 00816 sizeof(struct vxge_hw_fifo_txd) * fifo->depth); 00817 00818 fifo->txdl = NULL; 00819 fifo->hw_offset = fifo->sw_offset = 0; 00820 00821 return VXGE_HW_OK; 00822 }
| enum vxge_hw_status __vxge_hw_vpath_pci_read | ( | struct __vxge_hw_virtualpath * | vpath, | |
| u32 | phy_func_0, | |||
| u32 | offset, | |||
| u32 * | val | |||
| ) |
Definition at line 830 of file vxge_config.c.
References __vxge_hw_device_register_poll(), vxge_hw_vpath_reg::pci_config_access_cfg1, vxge_hw_vpath_reg::pci_config_access_cfg2, vxge_hw_vpath_reg::pci_config_access_status, readq, u32, __vxge_hw_virtualpath::vp_reg, vxge_bVALn, VXGE_HW_DEF_DEVICE_POLL_MILLIS, VXGE_HW_FAIL, VXGE_HW_INTR_MASK_ALL, VXGE_HW_OK, VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS, VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0, VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ, VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR, wmb, and writeq.
Referenced by __vxge_hw_vpath_initialize().
00832 { 00833 u64 val64; 00834 enum vxge_hw_status status = VXGE_HW_OK; 00835 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg; 00836 00837 val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset); 00838 00839 if (phy_func_0) 00840 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0; 00841 00842 writeq(val64, &vp_reg->pci_config_access_cfg1); 00843 wmb(); 00844 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ, 00845 &vp_reg->pci_config_access_cfg2); 00846 wmb(); 00847 00848 status = __vxge_hw_device_register_poll( 00849 &vp_reg->pci_config_access_cfg2, 00850 VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS); 00851 00852 if (status != VXGE_HW_OK) 00853 goto exit; 00854 00855 val64 = readq(&vp_reg->pci_config_access_status); 00856 00857 if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) { 00858 status = VXGE_HW_FAIL; 00859 *val = 0; 00860 } else 00861 *val = (u32)vxge_bVALn(val64, 32, 32); 00862 exit: 00863 return status; 00864 }
| u32 __vxge_hw_vpath_func_id_get | ( | struct vxge_hw_vpmgmt_reg __iomem * | vpmgmt_reg | ) |
Definition at line 871 of file vxge_config.c.
References readq, u32, and VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1.
Referenced by __vxge_hw_device_host_info_get(), and vxge_hw_device_hw_info_get().
00872 { 00873 u64 val64; 00874 00875 val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1); 00876 00877 return 00878 (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64); 00879 }
| static void __vxge_hw_read_rts_ds | ( | struct vxge_hw_vpath_reg __iomem * | vpath_reg, | |
| u64 | dta_struct_sel | |||
| ) | [inline, static] |
Definition at line 885 of file vxge_config.c.
Referenced by __vxge_hw_vpath_card_info_get().
00887 { 00888 writeq(0, &vpath_reg->rts_access_steer_ctrl); 00889 wmb(); 00890 writeq(dta_struct_sel, &vpath_reg->rts_access_steer_data0); 00891 writeq(0, &vpath_reg->rts_access_steer_data1); 00892 wmb(); 00893 return; 00894 }
| enum vxge_hw_status __vxge_hw_vpath_card_info_get | ( | struct vxge_hw_vpath_reg __iomem * | vpath_reg, | |
| struct vxge_hw_device_hw_info * | hw_info | |||
| ) |
Definition at line 901 of file vxge_config.c.
References __vxge_hw_pio_mem_write64(), __vxge_hw_read_rts_ds(), be64_to_cpu, data1, vxge_hw_device_hw_info::part_number, vxge_hw_device_hw_info::product_desc, readq, vxge_hw_device_hw_info::serial_number, u32, u8, VXGE_HW_DEF_DEVICE_POLL_MILLIS, VXGE_HW_OK, VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION, VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY, VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL, VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO, VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET, VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS, VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0, VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3, VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER, and VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER.
Referenced by vxge_hw_device_hw_info_get().
00904 { 00905 u32 i, j; 00906 u64 val64; 00907 u64 data1 = 0ULL; 00908 u64 data2 = 0ULL; 00909 enum vxge_hw_status status = VXGE_HW_OK; 00910 u8 *serial_number = hw_info->serial_number; 00911 u8 *part_number = hw_info->part_number; 00912 u8 *product_desc = hw_info->product_desc; 00913 00914 __vxge_hw_read_rts_ds(vpath_reg, 00915 VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER); 00916 00917 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( 00918 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | 00919 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( 00920 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | 00921 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | 00922 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); 00923 00924 status = __vxge_hw_pio_mem_write64(val64, 00925 &vpath_reg->rts_access_steer_ctrl, 00926 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, 00927 VXGE_HW_DEF_DEVICE_POLL_MILLIS); 00928 00929 if (status != VXGE_HW_OK) 00930 return status; 00931 00932 val64 = readq(&vpath_reg->rts_access_steer_ctrl); 00933 00934 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { 00935 data1 = readq(&vpath_reg->rts_access_steer_data0); 00936 ((u64 *)serial_number)[0] = be64_to_cpu(data1); 00937 00938 data2 = readq(&vpath_reg->rts_access_steer_data1); 00939 ((u64 *)serial_number)[1] = be64_to_cpu(data2); 00940 status = VXGE_HW_OK; 00941 } else 00942 *serial_number = 0; 00943 00944 __vxge_hw_read_rts_ds(vpath_reg, 00945 VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER); 00946 00947 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( 00948 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | 00949 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( 00950 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | 00951 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | 00952 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); 00953 00954 status = __vxge_hw_pio_mem_write64(val64, 00955 &vpath_reg->rts_access_steer_ctrl, 00956 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, 00957 VXGE_HW_DEF_DEVICE_POLL_MILLIS); 00958 00959 if (status != VXGE_HW_OK) 00960 return status; 00961 00962 val64 = readq(&vpath_reg->rts_access_steer_ctrl); 00963 00964 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { 00965 00966 data1 = readq(&vpath_reg->rts_access_steer_data0); 00967 ((u64 *)part_number)[0] = be64_to_cpu(data1); 00968 00969 data2 = readq(&vpath_reg->rts_access_steer_data1); 00970 ((u64 *)part_number)[1] = be64_to_cpu(data2); 00971 00972 status = VXGE_HW_OK; 00973 00974 } else 00975 *part_number = 0; 00976 00977 j = 0; 00978 00979 for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0; 00980 i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) { 00981 00982 __vxge_hw_read_rts_ds(vpath_reg, i); 00983 00984 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( 00985 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | 00986 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( 00987 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | 00988 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | 00989 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); 00990 00991 status = __vxge_hw_pio_mem_write64(val64, 00992 &vpath_reg->rts_access_steer_ctrl, 00993 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, 00994 VXGE_HW_DEF_DEVICE_POLL_MILLIS); 00995 00996 if (status != VXGE_HW_OK) 00997 return status; 00998 00999 val64 = readq(&vpath_reg->rts_access_steer_ctrl); 01000 01001 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { 01002 01003 data1 = readq(&vpath_reg->rts_access_steer_data0); 01004 ((u64 *)product_desc)[j++] = be64_to_cpu(data1); 01005 01006 data2 = readq(&vpath_reg->rts_access_steer_data1); 01007 ((u64 *)product_desc)[j++] = be64_to_cpu(data2); 01008 01009 status = VXGE_HW_OK; 01010 } else 01011 *product_desc = 0; 01012 } 01013 01014 return status; 01015 }
| enum vxge_hw_status __vxge_hw_vpath_fw_ver_get | ( | struct vxge_hw_vpath_reg __iomem * | vpath_reg, | |
| struct vxge_hw_device_hw_info * | hw_info | |||
| ) |
Definition at line 1022 of file vxge_config.c.
References __vxge_hw_pio_mem_write64(), vxge_hw_device_version::build, data1, vxge_hw_device_date::date, vxge_hw_device_date::day, vxge_hw_device_hw_info::flash_date, vxge_hw_device_hw_info::flash_version, vxge_hw_device_hw_info::fw_date, vxge_hw_device_hw_info::fw_version, vxge_hw_device_version::major, vxge_hw_device_version::minor, vxge_hw_device_date::month, readq, snprintf(), u32, vxge_hw_device_version::version, VXGE_HW_DEF_DEVICE_POLL_MILLIS, VXGE_HW_FAIL, VXGE_HW_FW_STRLEN, VXGE_HW_OK, VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION, VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY, VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL, VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO, VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET, VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS, VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD, VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY, VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR, VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR, VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH, VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR, VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD, VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY, VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR, VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR, VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH, VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR, and vxge_hw_device_date::year.
Referenced by vxge_hw_device_hw_info_get().
01025 { 01026 u64 val64; 01027 u64 data1 = 0ULL; 01028 u64 data2 = 0ULL; 01029 struct vxge_hw_device_version *fw_version = &hw_info->fw_version; 01030 struct vxge_hw_device_date *fw_date = &hw_info->fw_date; 01031 struct vxge_hw_device_version *flash_version = &hw_info->flash_version; 01032 struct vxge_hw_device_date *flash_date = &hw_info->flash_date; 01033 enum vxge_hw_status status = VXGE_HW_OK; 01034 01035 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( 01036 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY) | 01037 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( 01038 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | 01039 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | 01040 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); 01041 01042 status = __vxge_hw_pio_mem_write64(val64, 01043 &vpath_reg->rts_access_steer_ctrl, 01044 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, 01045 VXGE_HW_DEF_DEVICE_POLL_MILLIS); 01046 01047 if (status != VXGE_HW_OK) 01048 goto exit; 01049 01050 val64 = readq(&vpath_reg->rts_access_steer_ctrl); 01051 01052 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { 01053 01054 data1 = readq(&vpath_reg->rts_access_steer_data0); 01055 data2 = readq(&vpath_reg->rts_access_steer_data1); 01056 01057 fw_date->day = 01058 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY( 01059 data1); 01060 fw_date->month = 01061 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH( 01062 data1); 01063 fw_date->year = 01064 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR( 01065 data1); 01066 01067 snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%d/%d/%d", 01068 fw_date->month, fw_date->day, fw_date->year); 01069 01070 fw_version->major = 01071 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1); 01072 fw_version->minor = 01073 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1); 01074 fw_version->build = 01075 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1); 01076 01077 snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d", 01078 fw_version->major, fw_version->minor, fw_version->build); 01079 01080 flash_date->day = 01081 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data2); 01082 flash_date->month = 01083 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data2); 01084 flash_date->year = 01085 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data2); 01086 01087 snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%d/%d/%d", 01088 flash_date->month, flash_date->day, flash_date->year); 01089 01090 flash_version->major = 01091 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data2); 01092 flash_version->minor = 01093 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data2); 01094 flash_version->build = 01095 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data2); 01096 01097 snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d", 01098 flash_version->major, flash_version->minor, 01099 flash_version->build); 01100 01101 status = VXGE_HW_OK; 01102 01103 } else 01104 status = VXGE_HW_FAIL; 01105 exit: 01106 return status; 01107 }
| enum vxge_hw_status __vxge_hw_vpath_addr_get | ( | struct vxge_hw_vpath_reg * | vpath_reg, | |
| u8(macaddr) | [ETH_ALEN], | |||
| u8(macaddr_mask) | [ETH_ALEN] | |||
| ) |
Definition at line 1114 of file vxge_config.c.
References __vxge_hw_pio_mem_write64(), data1, is_valid_ether_addr(), readq, vxge_hw_vpath_reg::rts_access_steer_ctrl, vxge_hw_vpath_reg::rts_access_steer_data0, vxge_hw_vpath_reg::rts_access_steer_data1, u32, u8, VXGE_HW_DEF_DEVICE_POLL_MILLIS, VXGE_HW_FAIL, VXGE_HW_OK, VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION, VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY, VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY, VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL, VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA, VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET, VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS, VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR, and VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK.
Referenced by vxge_hw_device_hw_info_get().
01117 { 01118 u32 i; 01119 u64 val64; 01120 u64 data1 = 0ULL; 01121 u64 data2 = 0ULL; 01122 u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY; 01123 enum vxge_hw_status status = VXGE_HW_OK; 01124 01125 while (1) { 01126 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | 01127 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( 01128 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) | 01129 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | 01130 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); 01131 01132 status = __vxge_hw_pio_mem_write64(val64, 01133 &vpath_reg->rts_access_steer_ctrl, 01134 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, 01135 VXGE_HW_DEF_DEVICE_POLL_MILLIS); 01136 01137 if (status != VXGE_HW_OK) 01138 break; 01139 01140 val64 = readq(&vpath_reg->rts_access_steer_ctrl); 01141 01142 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { 01143 01144 data1 = readq(&vpath_reg->rts_access_steer_data0); 01145 data2 = readq(&vpath_reg->rts_access_steer_data1); 01146 01147 data1 = 01148 VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1); 01149 data2 = 01150 VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK( 01151 data2); 01152 01153 for (i = ETH_ALEN; i > 0; i--) { 01154 macaddr[i-1] = (u8)(data1 & 0xFF); 01155 data1 >>= 8; 01156 01157 macaddr_mask[i-1] = (u8)(data2 & 0xFF); 01158 data2 >>= 8; 01159 } 01160 if (is_valid_ether_addr(macaddr)) { 01161 status = VXGE_HW_OK; 01162 break; 01163 } 01164 action = 01165 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY; 01166 } else 01167 status = VXGE_HW_FAIL; 01168 } 01169 01170 return status; 01171 }
| static enum vxge_hw_status __vxge_hw_vpath_mgmt_read | ( | struct __vxge_hw_virtualpath * | vpath | ) | [static] |
Definition at line 1178 of file vxge_config.c.
References __vxge_hw_virtualpath::hldev, __vxge_hw_virtualpath::max_mtu, mtu, readq, u32, __vxge_hw_virtualpath::vpmgmt_reg, VXGE_HW_DEVICE_LINK_STATE_SET, VXGE_HW_LINK_DOWN, VXGE_HW_LINK_UP, VXGE_HW_MAC_HEADER_MAX_SIZE, VXGE_HW_MAC_MAX_MAC_PORT_ID, VXGE_HW_OK, VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN, VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK, and vxge_hw_vpmgmt_reg::xgmac_gen_status_vpmgmt_clone.
Referenced by __vxge_hw_vp_initialize().
01180 { 01181 u32 i, mtu = 0, max_pyld = 0; 01182 u64 val64; 01183 enum vxge_hw_status status = VXGE_HW_OK; 01184 01185 for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) { 01186 01187 val64 = readq(&vpath->vpmgmt_reg-> 01188 rxmac_cfg0_port_vpmgmt_clone[i]); 01189 max_pyld = 01190 (u32) 01191 VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN 01192 (val64); 01193 if (mtu < max_pyld) 01194 mtu = max_pyld; 01195 } 01196 01197 vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE; 01198 01199 val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone); 01200 01201 if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) 01202 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP); 01203 else 01204 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN); 01205 01206 return status; 01207 }
| enum vxge_hw_status __vxge_hw_vpath_reset_check | ( | struct __vxge_hw_virtualpath * | vpath | ) |
Definition at line 1215 of file vxge_config.c.
References __vxge_hw_device_register_poll(), __vxge_hw_device::common_reg, __vxge_hw_virtualpath::hldev, __vxge_hw_virtualpath::vp_id, vxge_hw_common_reg::vpath_rst_in_prog, VXGE_HW_DEF_DEVICE_POLL_MILLIS, VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG, and vxge_trace.
Referenced by __vxge_hw_vp_initialize(), vxge_hw_vpath_recover_from_reset(), and vxge_reset_all_vpaths().
01216 { 01217 enum vxge_hw_status status; 01218 01219 vxge_trace(); 01220 01221 status = __vxge_hw_device_register_poll( 01222 &vpath->hldev->common_reg->vpath_rst_in_prog, 01223 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG( 01224 1 << (16 - vpath->vp_id)), 01225 VXGE_HW_DEF_DEVICE_POLL_MILLIS); 01226 01227 return status; 01228 }
| enum vxge_hw_status __vxge_hw_vpath_reset | ( | struct __vxge_hw_device * | hldev, | |
| u32 | vp_id | |||
| ) |
Definition at line 1235 of file vxge_config.c.
References __vxge_hw_pio_mem_write32_upper(), vxge_hw_common_reg::cmn_rsthdlr_cfg0, __vxge_hw_device::common_reg, u32, vxge_bVALn, VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH, VXGE_HW_OK, and vxge_trace.
Referenced by __vxge_hw_vp_initialize(), and vxge_hw_vpath_reset().
01236 { 01237 u64 val64; 01238 enum vxge_hw_status status = VXGE_HW_OK; 01239 01240 vxge_trace(); 01241 01242 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id)); 01243 01244 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 01245 &hldev->common_reg->cmn_rsthdlr_cfg0); 01246 01247 return status; 01248 }
| void __vxge_hw_vpath_prc_configure | ( | struct __vxge_hw_device * | hldev | ) |
Definition at line 1256 of file vxge_config.c.
References vxge_hw_vpath_reg::prc_cfg1, vxge_hw_vpath_reg::prc_cfg4, vxge_hw_vpath_reg::prc_cfg5, vxge_hw_vpath_reg::prc_cfg6, readq, __vxge_hw_virtualpath::ringh, __vxge_hw_ring::rxdl, virt_to_bus(), __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE, VXGE_HW_PRC_CFG4_IN_SVC, VXGE_HW_PRC_CFG4_RING_MODE, VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER, VXGE_HW_PRC_CFG4_RTH_DISABLE, VXGE_HW_PRC_CFG5_RXD0_ADD, VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN, VXGE_HW_PRC_CFG6_RXD_CRXDT, VXGE_HW_PRC_CFG6_RXD_SPAT, vxge_trace, and writeq.
Referenced by vxge_hw_vpath_open(), and vxge_hw_vpath_recover_from_reset().
01257 { 01258 u64 val64; 01259 struct __vxge_hw_virtualpath *vpath; 01260 struct vxge_hw_vpath_reg __iomem *vp_reg; 01261 01262 vxge_trace(); 01263 01264 vpath = &hldev->virtual_path; 01265 vp_reg = vpath->vp_reg; 01266 01267 val64 = readq(&vp_reg->prc_cfg1); 01268 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE; 01269 writeq(val64, &vp_reg->prc_cfg1); 01270 01271 val64 = readq(&vpath->vp_reg->prc_cfg6); 01272 val64 &= ~VXGE_HW_PRC_CFG6_RXD_CRXDT(0x1ff); 01273 val64 &= ~VXGE_HW_PRC_CFG6_RXD_SPAT(0x1ff); 01274 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN; 01275 val64 |= VXGE_HW_PRC_CFG6_RXD_CRXDT(0x3); 01276 val64 |= VXGE_HW_PRC_CFG6_RXD_SPAT(0xf); 01277 writeq(val64, &vpath->vp_reg->prc_cfg6); 01278 01279 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD( 01280 (u64)virt_to_bus(vpath->ringh.rxdl) >> 3), 01281 &vp_reg->prc_cfg5); 01282 01283 val64 = readq(&vp_reg->prc_cfg4); 01284 val64 |= VXGE_HW_PRC_CFG4_IN_SVC; 01285 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3); 01286 val64 |= VXGE_HW_PRC_CFG4_RING_MODE( 01287 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER); 01288 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE; 01289 01290 writeq(val64, &vp_reg->prc_cfg4); 01291 return; 01292 }
| enum vxge_hw_status __vxge_hw_vpath_kdfc_configure | ( | struct __vxge_hw_device * | hldev, | |
| u32 | vp_id | |||
| ) |
Definition at line 1300 of file vxge_config.c.
References __vxge_hw_kdfc_swapper_set(), __vxge_hw_device::kdfc, vxge_hw_vpath_reg::kdfc_drbl_triplet_total, vxge_hw_vpath_reg::kdfc_fifo_trpl_ctrl, vxge_hw_vpath_reg::kdfc_fifo_trpl_partition, vxge_hw_vpath_reg::kdfc_trpl_fifo_0_ctrl, vxge_hw_vpath_reg::kdfc_trpl_fifo_0_wb_address, __vxge_hw_device::legacy_reg, __vxge_hw_virtualpath::max_kdfc_db, __vxge_hw_virtualpath::max_nofl_db, __vxge_hw_virtualpath::nofl_db, readq, vxge_hw_toc_reg::toc_kdfc_vpath_stride, __vxge_hw_device::toc_reg, u32, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE, VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE, VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT, VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN, VXGE_HW_OK, VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE, vxge_trace, wmb, and writeq.
Referenced by __vxge_hw_vpath_initialize().
01301 { 01302 u64 val64; 01303 u64 vpath_stride; 01304 enum vxge_hw_status status = VXGE_HW_OK; 01305 struct __vxge_hw_virtualpath *vpath; 01306 struct vxge_hw_vpath_reg __iomem *vp_reg; 01307 01308 vxge_trace(); 01309 01310 vpath = &hldev->virtual_path; 01311 vp_reg = vpath->vp_reg; 01312 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg); 01313 01314 if (status != VXGE_HW_OK) 01315 goto exit; 01316 01317 val64 = readq(&vp_reg->kdfc_drbl_triplet_total); 01318 01319 vpath->max_kdfc_db = 01320 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE( 01321 val64+1)/2; 01322 01323 vpath->max_nofl_db = vpath->max_kdfc_db; 01324 01325 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0( 01326 (vpath->max_nofl_db*2)-1); 01327 01328 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition); 01329 01330 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE, 01331 &vp_reg->kdfc_fifo_trpl_ctrl); 01332 01333 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl); 01334 01335 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) | 01336 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF)); 01337 01338 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE( 01339 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) | 01340 #if (__BYTE_ORDER != __BIG_ENDIAN) 01341 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN | 01342 #endif 01343 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0); 01344 01345 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl); 01346 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address); 01347 wmb(); 01348 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride); 01349 01350 vpath->nofl_db = 01351 (struct __vxge_hw_non_offload_db_wrapper __iomem *) 01352 (hldev->kdfc + (vp_id * 01353 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE( 01354 vpath_stride))); 01355 exit: 01356 return status; 01357 }
| enum vxge_hw_status __vxge_hw_vpath_mac_configure | ( | struct __vxge_hw_device * | hldev | ) |
Definition at line 1364 of file vxge_config.c.
References readq, vxge_hw_vpath_reg::rxmac_vcfg1, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, __vxge_hw_virtualpath::vsport_number, VXGE_HW_OK, VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE, VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE, VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER, vxge_trace, writeq, and vxge_hw_vpath_reg::xmac_vsport_choice.
Referenced by __vxge_hw_vpath_initialize().
01365 { 01366 u64 val64; 01367 enum vxge_hw_status status = VXGE_HW_OK; 01368 struct __vxge_hw_virtualpath *vpath; 01369 struct vxge_hw_vpath_reg __iomem *vp_reg; 01370 01371 vxge_trace(); 01372 01373 vpath = &hldev->virtual_path; 01374 vp_reg = vpath->vp_reg; 01375 01376 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER( 01377 vpath->vsport_number), &vp_reg->xmac_vsport_choice); 01378 01379 val64 = readq(&vp_reg->rxmac_vcfg1); 01380 01381 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) | 01382 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE); 01383 01384 writeq(val64, &vp_reg->rxmac_vcfg1); 01385 return status; 01386 }
| enum vxge_hw_status __vxge_hw_vpath_tim_configure | ( | struct __vxge_hw_device * | hldev, | |
| u32 | vp_id | |||
| ) |
Definition at line 1394 of file vxge_config.c.
References readq, RTI_RX_UFC_A, RTI_RX_UFC_B, RTI_RX_UFC_C, RTI_RX_UFC_D, RTI_RX_URANGE_A, RTI_RX_URANGE_B, RTI_RX_URANGE_C, vxge_hw_vpath_reg::tim_bitmap, vxge_hw_vpath_reg::tim_cfg1_int_num, vxge_hw_vpath_reg::tim_cfg2_int_num, vxge_hw_vpath_reg::tim_cfg3_int_num, vxge_hw_vpath_reg::tim_dest_addr, vxge_hw_vpath_reg::tim_pci_cfg, vxge_hw_vpath_reg::tim_remap, vxge_hw_vpath_reg::tim_ring_assn, vxge_hw_vpath_reg::tim_vpath_map, TTI_TX_UFC_A, TTI_TX_UFC_B, TTI_TX_UFC_C, TTI_TX_UFC_D, TTI_TX_URANGE_A, TTI_TX_URANGE_B, TTI_TX_URANGE_C, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, VXGE_HW_MAX_INTR_PER_VP, VXGE_HW_OK, VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL, VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC, VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI, VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN, VXGE_HW_TIM_CFG1_INT_NUM_URNG_A, VXGE_HW_TIM_CFG1_INT_NUM_URNG_B, VXGE_HW_TIM_CFG1_INT_NUM_URNG_C, VXGE_HW_TIM_CFG2_INT_NUM_UEC_A, VXGE_HW_TIM_CFG2_INT_NUM_UEC_B, VXGE_HW_TIM_CFG2_INT_NUM_UEC_C, VXGE_HW_TIM_CFG2_INT_NUM_UEC_D, VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL, VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL, VXGE_HW_TIM_PCI_CFG_ADD_PAD, VXGE_HW_TIM_RING_ASSN_INT_NUM, VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL, VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL, VXGE_HW_VPATH_INTR_BMAP, VXGE_HW_VPATH_INTR_EINTA, VXGE_HW_VPATH_INTR_RX, VXGE_HW_VPATH_INTR_TX, VXGE_RTI_BTIMER_VAL, VXGE_RTI_LTIMER_VAL, vxge_trace, VXGE_TTI_BTIMER_VAL, VXGE_TTI_LTIMER_VAL, and writeq.
Referenced by __vxge_hw_vpath_initialize().
01395 { 01396 u64 val64; 01397 enum vxge_hw_status status = VXGE_HW_OK; 01398 struct __vxge_hw_virtualpath *vpath; 01399 struct vxge_hw_vpath_reg __iomem *vp_reg; 01400 01401 vxge_trace(); 01402 01403 vpath = &hldev->virtual_path; 01404 vp_reg = vpath->vp_reg; 01405 01406 writeq((u64)0, &vp_reg->tim_dest_addr); 01407 writeq((u64)0, &vp_reg->tim_vpath_map); 01408 writeq((u64)0, &vp_reg->tim_bitmap); 01409 writeq((u64)0, &vp_reg->tim_remap); 01410 01411 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM( 01412 (vp_id * VXGE_HW_MAX_INTR_PER_VP) + 01413 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn); 01414 01415 val64 = readq(&vp_reg->tim_pci_cfg); 01416 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD; 01417 writeq(val64, &vp_reg->tim_pci_cfg); 01418 01419 /* TX configuration */ 01420 val64 = VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( 01421 (VXGE_TTI_BTIMER_VAL * 1000) / 272); 01422 val64 |= (VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC | 01423 VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI | 01424 VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN); 01425 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(TTI_TX_URANGE_A) | 01426 VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(TTI_TX_URANGE_B) | 01427 VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(TTI_TX_URANGE_C); 01428 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); 01429 01430 val64 = VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(TTI_TX_UFC_A) | 01431 VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(TTI_TX_UFC_B) | 01432 VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(TTI_TX_UFC_C) | 01433 VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(TTI_TX_UFC_D); 01434 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]); 01435 01436 val64 = VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL( 01437 VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL); 01438 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( 01439 (VXGE_TTI_LTIMER_VAL * 1000) / 272); 01440 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); 01441 01442 /* RX configuration */ 01443 val64 = VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( 01444 (VXGE_RTI_BTIMER_VAL * 1000) / 272); 01445 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; 01446 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(RTI_RX_URANGE_A) | 01447 VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(RTI_RX_URANGE_B) | 01448 VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(RTI_RX_URANGE_C); 01449 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); 01450 01451 val64 = VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(RTI_RX_UFC_A) | 01452 VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(RTI_RX_UFC_B) | 01453 VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(RTI_RX_UFC_C) | 01454 VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(RTI_RX_UFC_D); 01455 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]); 01456 01457 val64 = VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL( 01458 VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL); 01459 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( 01460 (VXGE_RTI_LTIMER_VAL * 1000) / 272); 01461 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); 01462 01463 val64 = 0; 01464 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]); 01465 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]); 01466 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]); 01467 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]); 01468 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]); 01469 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]); 01470 01471 return status; 01472 }
| enum vxge_hw_status __vxge_hw_vpath_initialize | ( | struct __vxge_hw_device * | hldev, | |
| u32 | vp_id | |||
| ) |
Definition at line 1480 of file vxge_config.c.
References __vxge_hw_legacy_swapper_set(), __vxge_hw_vpath_kdfc_configure(), __vxge_hw_vpath_mac_configure(), __vxge_hw_vpath_pci_read(), __vxge_hw_vpath_swapper_set(), __vxge_hw_vpath_tim_configure(), __vxge_hw_device::legacy_reg, readq, vxge_hw_vpath_reg::rtdma_rd_optimization_ctrl, u32, __vxge_hw_device::virtual_path, __vxge_hw_virtualpath::vp_reg, __vxge_hw_device::vpath_assignments, __vxge_hw_virtualpath::vpmgmt_reg, __vxge_hw_virtualpath::vsport_number, VXGE_HW_ERR_VPATH_NOT_AVAILABLE, VXGE_HW_MAX_PAYLOAD_SIZE_512, VXGE_HW_MAX_VIRTUAL_PATHS, VXGE_HW_OK, VXGE_HW_PCI_EXP_DEVCTL_READRQ, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH, VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE, vxge_mBIT, vxge_trace, writeq, and vxge_hw_vpmgmt_reg::xmac_vsport_choices_vp.
Referenced by __vxge_hw_vp_initialize(), and vxge_hw_vpath_recover_from_reset().
01481 { 01482 u64 val64; 01483 u32 val32; 01484 int i; 01485 enum vxge_hw_status status = VXGE_HW_OK; 01486 struct __vxge_hw_virtualpath *vpath; 01487 struct vxge_hw_vpath_reg *vp_reg; 01488 01489 vxge_trace(); 01490 01491 vpath = &hldev->virtual_path; 01492 01493 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) { 01494 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; 01495 goto exit; 01496 } 01497 vp_reg = vpath->vp_reg; 01498 status = __vxge_hw_legacy_swapper_set(hldev->legacy_reg); 01499 if (status != VXGE_HW_OK) 01500 goto exit; 01501 01502 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg); 01503 01504 if (status != VXGE_HW_OK) 01505 goto exit; 01506 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp); 01507 01508 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { 01509 if (val64 & vxge_mBIT(i)) 01510 vpath->vsport_number = i; 01511 } 01512 01513 status = __vxge_hw_vpath_mac_configure(hldev); 01514 01515 if (status != VXGE_HW_OK) 01516 goto exit; 01517 01518 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id); 01519 01520 if (status != VXGE_HW_OK) 01521 goto exit; 01522 01523 status = __vxge_hw_vpath_tim_configure(hldev, vp_id); 01524 01525 if (status != VXGE_HW_OK) 01526 goto exit; 01527 01528 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl); 01529 01530 /* Get MRRS value from device control */ 01531 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32); 01532 01533 if (status == VXGE_HW_OK) { 01534 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12; 01535 val64 &= 01536 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7)); 01537 val64 |= 01538 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32); 01539 01540 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE; 01541 } 01542 01543 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7)); 01544 val64 |= 01545 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY( 01546 VXGE_HW_MAX_PAYLOAD_SIZE_512); 01547 01548 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN; 01549 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl); 01550 01551 exit: 01552 return status; 01553 }
| enum vxge_hw_status __vxge_hw_vp_initialize | ( | struct __vxge_hw_device * | hldev, | |
| u32 | vp_id, | |||
| struct __vxge_hw_virtualpath * | vpath | |||
| ) |
Definition at line 1561 of file vxge_config.c.
References __vxge_hw_vp_terminate(), __vxge_hw_vpath_initialize(), __vxge_hw_vpath_mgmt_read(), __vxge_hw_vpath_reset(), __vxge_hw_vpath_reset_check(), __vxge_hw_virtualpath::hldev, memset(), __vxge_hw_device::tim_int_mask0, __vxge_hw_device::tim_int_mask1, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, __vxge_hw_virtualpath::vp_reg, __vxge_hw_device::vpath_assignments, __vxge_hw_device::vpath_reg, __vxge_hw_device::vpmgmt_reg, __vxge_hw_virtualpath::vpmgmt_reg, VXGE_HW_DEVICE_TIM_INT_MASK_SET, VXGE_HW_ERR_VPATH_NOT_AVAILABLE, VXGE_HW_OK, VXGE_HW_VP_OPEN, vxge_mBIT, and vxge_trace.
Referenced by vxge_hw_vpath_open().
01563 { 01564 enum vxge_hw_status status = VXGE_HW_OK; 01565 01566 vxge_trace(); 01567 01568 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) { 01569 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; 01570 goto exit; 01571 } 01572 01573 vpath->vp_id = vp_id; 01574 vpath->vp_open = VXGE_HW_VP_OPEN; 01575 vpath->hldev = hldev; 01576 vpath->vp_reg = hldev->vpath_reg[vp_id]; 01577 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id]; 01578 01579 __vxge_hw_vpath_reset(hldev, vp_id); 01580 01581 status = __vxge_hw_vpath_reset_check(vpath); 01582 if (status != VXGE_HW_OK) { 01583 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); 01584 goto exit; 01585 } 01586 01587 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0, 01588 hldev->tim_int_mask1, vp_id); 01589 01590 status = __vxge_hw_vpath_initialize(hldev, vp_id); 01591 01592 if (status != VXGE_HW_OK) { 01593 __vxge_hw_vp_terminate(hldev, vpath); 01594 goto exit; 01595 } 01596 01597 status = __vxge_hw_vpath_mgmt_read(vpath); 01598 exit: 01599 return status; 01600 }
| void __vxge_hw_vp_terminate | ( | struct __vxge_hw_device * | hldev, | |
| struct __vxge_hw_virtualpath * | vpath | |||
| ) |
Definition at line 1607 of file vxge_config.c.
References memset(), __vxge_hw_device::tim_int_mask0, __vxge_hw_device::tim_int_mask1, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, VXGE_HW_DEVICE_TIM_INT_MASK_RESET, VXGE_HW_VP_NOT_OPEN, and vxge_trace.
Referenced by __vxge_hw_vp_initialize(), vxge_hw_vpath_close(), and vxge_hw_vpath_open().
01609 { 01610 vxge_trace(); 01611 01612 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) 01613 return; 01614 01615 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(hldev->tim_int_mask0, 01616 hldev->tim_int_mask1, vpath->vp_id); 01617 01618 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); 01619 }
| enum vxge_hw_status vxge_hw_vpath_mtu_set | ( | struct __vxge_hw_virtualpath * | vpath, | |
| u32 | new_mtu | |||
| ) |
Definition at line 1627 of file vxge_config.c.
References __vxge_hw_virtualpath::max_mtu, readq, vxge_hw_vpath_reg::rxmac_vcfg0, __vxge_hw_virtualpath::vp_reg, VXGE_HW_ERR_INVALID_MTU_SIZE, VXGE_HW_MAC_HEADER_MAX_SIZE, VXGE_HW_MIN_MTU, VXGE_HW_OK, VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN, vxge_trace, and writeq.
Referenced by vxge_open().
01628 { 01629 u64 val64; 01630 enum vxge_hw_status status = VXGE_HW_OK; 01631 01632 vxge_trace(); 01633 01634 new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE; 01635 01636 if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu)) 01637 status = VXGE_HW_ERR_INVALID_MTU_SIZE; 01638 01639 val64 = readq(&vpath->vp_reg->rxmac_vcfg0); 01640 01641 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff); 01642 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu); 01643 01644 writeq(val64, &vpath->vp_reg->rxmac_vcfg0); 01645 01646 return status; 01647 }
| enum vxge_hw_status vxge_hw_vpath_open | ( | struct __vxge_hw_device * | hldev, | |
| struct vxge_vpath * | vpath | |||
| ) |
Definition at line 1656 of file vxge_config.c.
References __vxge_hw_fifo_create(), __vxge_hw_fifo_delete(), __vxge_hw_ring_create(), __vxge_hw_vp_initialize(), __vxge_hw_vp_terminate(), __vxge_hw_vpath_prc_configure(), __vxge_hw_virtualpath::fifoh, __vxge_hw_device::first_vp_id, __vxge_hw_virtualpath::ringh, __vxge_hw_device::virtual_path, vxge_vpath::vp_open, VXGE_HW_ERR_INVALID_STATE, VXGE_HW_OK, VXGE_HW_VP_OPEN, and vxge_trace.
Referenced by vxge_open_vpaths().
01657 { 01658 struct __vxge_hw_virtualpath *vpathh; 01659 enum vxge_hw_status status; 01660 01661 vxge_trace(); 01662 01663 vpathh = &hldev->virtual_path; 01664 01665 if (vpath->vp_open == VXGE_HW_VP_OPEN) { 01666 status = VXGE_HW_ERR_INVALID_STATE; 01667 goto vpath_open_exit1; 01668 } 01669 01670 status = __vxge_hw_vp_initialize(hldev, hldev->first_vp_id, vpathh); 01671 if (status != VXGE_HW_OK) 01672 goto vpath_open_exit1; 01673 01674 status = __vxge_hw_fifo_create(vpathh, &vpathh->fifoh); 01675 if (status != VXGE_HW_OK) 01676 goto vpath_open_exit2; 01677 01678 status = __vxge_hw_ring_create(vpathh, &vpathh->ringh); 01679 if (status != VXGE_HW_OK) 01680 goto vpath_open_exit3; 01681 01682 __vxge_hw_vpath_prc_configure(hldev); 01683 01684 return VXGE_HW_OK; 01685 01686 vpath_open_exit3: 01687 __vxge_hw_fifo_delete(&vpathh->fifoh); 01688 vpath_open_exit2: 01689 __vxge_hw_vp_terminate(hldev, vpathh); 01690 vpath_open_exit1: 01691 return status; 01692 }
| void vxge_hw_vpath_rx_doorbell_init | ( | struct __vxge_hw_virtualpath * | vpath | ) |
Definition at line 1703 of file vxge_config.c.
References __vxge_hw_virtualpath::hldev, vxge_hw_vpath_reg::prc_rxd_doorbell, readq, vxge_hw_vpath_reg::rxdmem_size, __vxge_hw_device::titan1, __vxge_hw_virtualpath::vp_reg, VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT, VXGE_HW_RING_RXD_QWORDS_MODE_1, VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE, vxge_trace, and writeq.
Referenced by vxge_open().
01704 { 01705 u64 new_count, val64; 01706 01707 vxge_trace(); 01708 01709 if (vpath->hldev->titan1) { 01710 new_count = readq(&vpath->vp_reg->rxdmem_size); 01711 new_count &= 0x1fff; 01712 } else 01713 new_count = VXGE_HW_RING_RXD_QWORDS_MODE_1 * 4; 01714 01715 val64 = (VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count)); 01716 01717 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val64), 01718 &vpath->vp_reg->prc_rxd_doorbell); 01719 }
| enum vxge_hw_status vxge_hw_vpath_close | ( | struct __vxge_hw_virtualpath * | vpath | ) |
Definition at line 1726 of file vxge_config.c.
References __vxge_hw_fifo_delete(), __vxge_hw_ring_delete(), __vxge_hw_vp_terminate(), __vxge_hw_virtualpath::fifoh, __vxge_hw_virtualpath::hldev, NULL, __vxge_hw_virtualpath::ringh, u32, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, __vxge_hw_device::vpaths_deployed, VXGE_HW_ERR_VPATH_NOT_OPEN, VXGE_HW_OK, VXGE_HW_VP_NOT_OPEN, vxge_mBIT, and vxge_trace.
Referenced by vxge_close_vpaths().
01727 { 01728 struct __vxge_hw_device *devh = NULL; 01729 u32 vp_id = vpath->vp_id; 01730 enum vxge_hw_status status = VXGE_HW_OK; 01731 01732 vxge_trace(); 01733 01734 devh = vpath->hldev; 01735 01736 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { 01737 status = VXGE_HW_ERR_VPATH_NOT_OPEN; 01738 goto vpath_close_exit; 01739 } 01740 01741 devh->vpaths_deployed &= ~vxge_mBIT(vp_id); 01742 01743 __vxge_hw_ring_delete(&vpath->ringh); 01744 01745 __vxge_hw_fifo_delete(&vpath->fifoh); 01746 01747 __vxge_hw_vp_terminate(devh, vpath); 01748 01749 vpath->vp_open = VXGE_HW_VP_NOT_OPEN; 01750 01751 vpath_close_exit: 01752 return status; 01753 }
| enum vxge_hw_status vxge_hw_vpath_reset | ( | struct __vxge_hw_virtualpath * | vpath | ) |
Definition at line 1759 of file vxge_config.c.
References __vxge_hw_vpath_reset(), __vxge_hw_virtualpath::hldev, u32, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, VXGE_HW_ERR_VPATH_NOT_OPEN, VXGE_HW_VP_NOT_OPEN, and vxge_trace.
Referenced by vxge_reset_all_vpaths().
01760 { 01761 enum vxge_hw_status status; 01762 u32 vp_id; 01763 01764 vxge_trace(); 01765 01766 vp_id = vpath->vp_id; 01767 01768 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { 01769 status = VXGE_HW_ERR_VPATH_NOT_OPEN; 01770 goto exit; 01771 } 01772 01773 status = __vxge_hw_vpath_reset(vpath->hldev, vp_id); 01774 exit: 01775 return status; 01776 }
| enum vxge_hw_status vxge_hw_vpath_recover_from_reset | ( | struct __vxge_hw_virtualpath * | vpath | ) |
Definition at line 1784 of file vxge_config.c.
References __vxge_hw_vpath_initialize(), __vxge_hw_vpath_prc_configure(), __vxge_hw_vpath_reset_check(), __vxge_hw_virtualpath::hldev, u32, __vxge_hw_virtualpath::vp_id, __vxge_hw_virtualpath::vp_open, VXGE_HW_ERR_VPATH_NOT_OPEN, VXGE_HW_OK, VXGE_HW_VP_NOT_OPEN, and vxge_trace.
Referenced by vxge_reset_all_vpaths().
01785 { 01786 enum vxge_hw_status status; 01787 struct __vxge_hw_device *hldev; 01788 u32 vp_id; 01789 01790 vxge_trace(); 01791 01792 vp_id = vpath->vp_id; 01793 hldev = vpath->hldev; 01794 01795 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { 01796 status = VXGE_HW_ERR_VPATH_NOT_OPEN; 01797 goto exit; 01798 } 01799 01800 status = __vxge_hw_vpath_reset_check(vpath); 01801 if (status != VXGE_HW_OK) 01802 goto exit; 01803 01804 status = __vxge_hw_vpath_initialize(hldev, vp_id); 01805 if (status != VXGE_HW_OK) 01806 goto exit; 01807 01808 __vxge_hw_vpath_prc_configure(hldev); 01809 01810 exit: 01811 return status; 01812 }
| void vxge_hw_vpath_enable | ( | struct __vxge_hw_virtualpath * | vpath | ) |
Definition at line 1820 of file vxge_config.c.
References __vxge_hw_pio_mem_write32_upper(), vxge_hw_common_reg::cmn_rsthdlr_cfg1, __vxge_hw_device::common_reg, __vxge_hw_virtualpath::hldev, u32, __vxge_hw_virtualpath::vp_id, vxge_bVALn, VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET, and vxge_trace.
Referenced by vxge_open().
01821 { 01822 struct __vxge_hw_device *hldev; 01823 u64 val64; 01824 01825 vxge_trace(); 01826 01827 hldev = vpath->hldev; 01828 01829 val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET( 01830 1 << (16 - vpath->vp_id)); 01831 01832 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), 01833 &hldev->common_reg->cmn_rsthdlr_cfg1); 01834 }
1.5.7.1