via-rhine.c File Reference

#include "etherboot.h"
#include "nic.h"
#include <gpxe/pci.h>
#include <gpxe/ethernet.h>

Go to the source code of this file.

Data Structures

struct rhine_tx_desc

union rhine_tx_desc::VTC_tx_status_tag

union rhine_tx_desc::VTC_tx_ctrl_tag

struct rhine_rx_desc

union rhine_rx_desc::VTC_rx_status_tag

union rhine_rx_desc::VTC_rx_ctrl_tag

struct rhine_private

Defines

#define W_MAX_TIMEOUT   0x0FFFU

#define RX_BUF_LEN_IDX   3

#define RX_BUF_LEN   (8192 << RX_BUF_LEN_IDX)

#define TX_BUF_SIZE   1536

#define RX_BUF_SIZE   1536

#define TX_FIFO_THRESH   256

#define RX_FIFO_THRESH   4

#define RX_DMA_BURST   4

#define TX_DMA_BURST   4

#define TX_TIMEOUT   ((2000*HZ)/1000)

#define byPAR0   ioaddr

#define byRCR   ioaddr + 6

#define byTCR   ioaddr + 7

#define byCR0   ioaddr + 8

#define byCR1   ioaddr + 9

#define byISR0   ioaddr + 0x0c

#define byISR1   ioaddr + 0x0d

#define byIMR0   ioaddr + 0x0e

#define byIMR1   ioaddr + 0x0f

#define byMAR0   ioaddr + 0x10

#define byMAR1   ioaddr + 0x11

#define byMAR2   ioaddr + 0x12

#define byMAR3   ioaddr + 0x13

#define byMAR4   ioaddr + 0x14

#define byMAR5   ioaddr + 0x15

#define byMAR6   ioaddr + 0x16

#define byMAR7   ioaddr + 0x17

#define dwCurrentRxDescAddr   ioaddr + 0x18

#define dwCurrentTxDescAddr   ioaddr + 0x1c

#define dwCurrentRDSE0   ioaddr + 0x20

#define dwCurrentRDSE1   ioaddr + 0x24

#define dwCurrentRDSE2   ioaddr + 0x28

#define dwCurrentRDSE3   ioaddr + 0x2c

#define dwNextRDSE0   ioaddr + 0x30

#define dwNextRDSE1   ioaddr + 0x34

#define dwNextRDSE2   ioaddr + 0x38

#define dwNextRDSE3   ioaddr + 0x3c

#define dwCurrentTDSE0   ioaddr + 0x40

#define dwCurrentTDSE1   ioaddr + 0x44

#define dwCurrentTDSE2   ioaddr + 0x48

#define dwCurrentTDSE3   ioaddr + 0x4c

#define dwNextTDSE0   ioaddr + 0x50

#define dwNextTDSE1   ioaddr + 0x54

#define dwNextTDSE2   ioaddr + 0x58

#define dwNextTDSE3   ioaddr + 0x5c

#define dwCurrRxDMAPtr   ioaddr + 0x60

#define dwCurrTxDMAPtr   ioaddr + 0x64

#define byMPHY   ioaddr + 0x6c

#define byMIISR   ioaddr + 0x6d

#define byBCR0   ioaddr + 0x6e

#define byBCR1   ioaddr + 0x6f

#define byMIICR   ioaddr + 0x70

#define byMIIAD   ioaddr + 0x71

#define wMIIDATA   ioaddr + 0x72

#define byEECSR   ioaddr + 0x74

#define byTEST   ioaddr + 0x75

#define byGPIO   ioaddr + 0x76

#define byCFGA   ioaddr + 0x78

#define byCFGB   ioaddr + 0x79

#define byCFGC   ioaddr + 0x7a

#define byCFGD   ioaddr + 0x7b

#define wTallyCntMPA   ioaddr + 0x7c

#define wTallyCntCRC   ioaddr + 0x7d

#define bySTICKHW   ioaddr + 0x83

#define byWOLcrClr   ioaddr + 0xA4

#define byWOLcgClr   ioaddr + 0xA7

#define byPwrcsrClr   ioaddr + 0xAC

#define RCR_RRFT2   0x80

#define RCR_RRFT1   0x40

#define RCR_RRFT0   0x20

#define RCR_PROM   0x10

#define RCR_AB   0x08

#define RCR_AM   0x04

#define RCR_AR   0x02

#define RCR_SEP   0x01

#define TCR_RTSF   0x80

#define TCR_RTFT1   0x40

#define TCR_RTFT0   0x20

#define TCR_OFSET   0x08

#define TCR_LB1   0x04

#define TCR_LB0   0x02

#define CR0_RDMD   0x40

#define CR0_TDMD   0x20

#define CR0_TXON   0x10

#define CR0_RXON   0x08

#define CR0_STOP   0x04

#define CR0_STRT   0x02

#define CR0_INIT   0x01

#define CR1_SFRST   0x80

#define CR1_RDMD1   0x40

#define CR1_TDMD1   0x20

#define CR1_KEYPAG   0x10

#define CR1_DPOLL   0x08

#define CR1_FDX   0x04

#define CR1_ETEN   0x02

#define CR1_EREN   0x01

#define CR_RDMD   0x0040

#define CR_TDMD   0x0020

#define CR_TXON   0x0010

#define CR_RXON   0x0008

#define CR_STOP   0x0004

#define CR_STRT   0x0002

#define CR_INIT   0x0001

#define CR_SFRST   0x8000

#define CR_RDMD1   0x4000

#define CR_TDMD1   0x2000

#define CR_KEYPAG   0x1000

#define CR_DPOLL   0x0800

#define CR_FDX   0x0400

#define CR_ETEN   0x0200

#define CR_EREN   0x0100

#define IMR0_CNTM   0x80

#define IMR0_BEM   0x40

#define IMR0_RUM   0x20

#define IMR0_TUM   0x10

#define IMR0_TXEM   0x08

#define IMR0_RXEM   0x04

#define IMR0_PTXM   0x02

#define IMR0_PRXM   0x01

#define IMRShadow   0x5AFF

#define IMR1_INITM   0x80

#define IMR1_SRCM   0x40

#define IMR1_NBFM   0x10

#define IMR1_PRAIM   0x08

#define IMR1_RES0M   0x04

#define IMR1_ETM   0x02

#define IMR1_ERM   0x01

#define ISR_INITI   0x8000

#define ISR_SRCI   0x4000

#define ISR_ABTI   0x2000

#define ISR_NORBF   0x1000

#define ISR_PKTRA   0x0800

#define ISR_RES0   0x0400

#define ISR_ETI   0x0200

#define ISR_ERI   0x0100

#define ISR_CNT   0x0080

#define ISR_BE   0x0040

#define ISR_RU   0x0020

#define ISR_TU   0x0010

#define ISR_TXE   0x0008

#define ISR_RXE   0x0004

#define ISR_PTX   0x0002

#define ISR_PRX   0x0001

#define ISR0_CNT   0x80

#define ISR0_BE   0x40

#define ISR0_RU   0x20

#define ISR0_TU   0x10

#define ISR0_TXE   0x08

#define ISR0_RXE   0x04

#define ISR0_PTX   0x02

#define ISR0_PRX   0x01

#define ISR1_INITI   0x80

#define ISR1_SRCI   0x40

#define ISR1_NORBF   0x10

#define ISR1_PKTRA   0x08

#define ISR1_ETI   0x02

#define ISR1_ERI   0x01

#define ISR_ABNORMAL   ISR_BE+ISR_RU+ISR_TU+ISR_CNT+ISR_NORBF+ISR_PKTRA

#define MIISR_MIIERR   0x08

#define MIISR_MRERR   0x04

#define MIISR_LNKFL   0x02

#define MIISR_SPEED   0x01

#define MIICR_MAUTO   0x80

#define MIICR_RCMD   0x40

#define MIICR_WCMD   0x20

#define MIICR_MDPM   0x10

#define MIICR_MOUT   0x08

#define MIICR_MDO   0x04

#define MIICR_MDI   0x02

#define MIICR_MDC   0x01

#define EECSR_EEPR   0x80

#define EECSR_EMBP   0x40

#define EECSR_AUTOLD   0x20

#define EECSR_DPM   0x10

#define EECSR_CS   0x08

#define EECSR_SK   0x04

#define EECSR_DI   0x02

#define EECSR_DO   0x01

#define BCR0_CRFT2   0x20

#define BCR0_CRFT1   0x10

#define BCR0_CRFT0   0x08

#define BCR0_DMAL2   0x04

#define BCR0_DMAL1   0x02

#define BCR0_DMAL0   0x01

#define BCR1_CTSF   0x20

#define BCR1_CTFT1   0x10

#define BCR1_CTFT0   0x08

#define BCR1_POT2   0x04

#define BCR1_POT1   0x02

#define BCR1_POT0   0x01

#define CFGA_EELOAD   0x80

#define CFGA_JUMPER   0x40

#define CFGA_MTGPIO   0x08

#define CFGA_T10EN   0x02

#define CFGA_AUTO   0x01

#define CFGB_PD   0x80

#define CFGB_POLEN   0x02

#define CFGB_LNKEN   0x01

#define CFGC_M10TIO   0x80

#define CFGC_M10POL   0x40

#define CFGC_PHY1   0x20

#define CFGC_PHY0   0x10

#define CFGC_BTSEL   0x08

#define CFGC_BPS2   0x04

#define CFGC_BPS1   0x02

#define CFGC_BPS0   0x01

#define CFGD_GPIOEN   0x80

#define CFGD_DIAG   0x40

#define CFGD_MAGIC   0x10

#define CFGD_RANDOM   0x08

#define CFGD_CFDX   0x04

#define CFGD_CEREN   0x02

#define CFGD_CETEN   0x01

#define RSR_RERR   0x00000001

#define RSR_CRC   0x00000002

#define RSR_FAE   0x00000004

#define RSR_FOV   0x00000008

#define RSR_LONG   0x00000010

#define RSR_RUNT   0x00000020

#define RSR_SERR   0x00000040

#define RSR_BUFF   0x00000080

#define RSR_EDP   0x00000100

#define RSR_STP   0x00000200

#define RSR_CHN   0x00000400

#define RSR_PHY   0x00000800

#define RSR_BAR   0x00001000

#define RSR_MAR   0x00002000

#define RSR_RXOK   0x00008000

#define RSR_ABNORMAL   RSR_RERR+RSR_LONG+RSR_RUNT

#define TSR_NCR0   0x00000001

#define TSR_NCR1   0x00000002

#define TSR_NCR2   0x00000004

#define TSR_NCR3   0x00000008

#define TSR_COLS   0x00000010

#define TSR_CDH   0x00000080

#define TSR_ABT   0x00000100

#define TSR_OWC   0x00000200

#define TSR_CRS   0x00000400

#define TSR_UDF   0x00000800

#define TSR_TBUFF   0x00001000

#define TSR_SERR   0x00002000

#define TSR_JAB   0x00004000

#define TSR_TERR   0x00008000

#define TSR_ABNORMAL   TSR_TERR+TSR_OWC+TSR_ABT+TSR_JAB+TSR_CRS

#define TSR_OWN_BIT   0x80000000

#define CB_DELAY_LOOP_WAIT   10

#define W_IMR_MASK_VALUE   0x1BFF

#define PKT_TYPE_DIRECTED   0x0001

#define PKT_TYPE_MULTICAST   0x0002

#define PKT_TYPE_ALL_MULTICAST   0x0004

#define PKT_TYPE_BROADCAST   0x0008

#define PKT_TYPE_PROMISCUOUS   0x0020

#define PKT_TYPE_LONG   0x2000

#define PKT_TYPE_RUNT   0x4000

#define PKT_TYPE_ERROR   0x8000

#define NIC_LB_NONE   0x00

#define NIC_LB_INTERNAL   0x01

#define NIC_LB_PHY   0x02

#define TX_RING_SIZE   2

#define RX_RING_SIZE   2

#define PKT_BUF_SZ   1536

#define PCI_REG_MODE3   0x53

#define MODE3_MIION   0x04

#define rhine_TOTAL_SIZE   0x80

#define NUM_TX_DESC   2

#define DEFAULT_INTR

#define IOSYNC   do { inb(nic->ioaddr + StationAddr); } while (0)

Enumerations

enum rhine_revs {
  VT86C100A = 0x00, VTunknown0 = 0x20, VT6102 = 0x40, VT8231 = 0x50,
  VT8233 = 0x60, VT8235 = 0x74, VT8237 = 0x78, VTunknown1 = 0x7C,
  VT6105 = 0x80, VT6105_B0 = 0x83, VT6105L = 0x8A, VT6107 = 0x8C,
  VTunknown2 = 0x8E, VT6105M = 0x90
}

enum register_offsets {
  ChipCmd = 0x00, ChipConfig = 0x04, EECtrl = 0x08, PCIBusCfg = 0x0C,
  IntrStatus = 0x10, IntrMask = 0x14, IntrEnable = 0x18, TxRingPtr = 0x20,
  TxConfig = 0x24, RxRingPtr = 0x30, RxConfig = 0x34, ClkRun = 0x3C,
  WOLCmd = 0x40, PauseCmd = 0x44, RxFilterAddr = 0x48, RxFilterData = 0x4C,
  BootRomAddr = 0x50, BootRomData = 0x54, SiliconRev = 0x58, StatsCtrl = 0x5C,
  StatsData = 0x60, RxPktErrs = 0x60, RxMissed = 0x68, RxCRCErrs = 0x64,
  PCIPM = 0x44, PhyStatus = 0xC0, MIntrCtrl = 0xC4, MIntrStatus = 0xC8,
  PGSEL = 0xCC, PMDCSR = 0xE4, TSTDAT = 0xFC, DSPCFG = 0xF4,
  SDCFG = 0x8C, BasicControl = 0x80, BasicStatus = 0x84, StationAddr = 0x00,
  RxConfig = 0x06, TxConfig = 0x07, ChipCmd = 0x08, IntrStatus = 0x0C,
  IntrEnable = 0x0E, MulticastFilter0 = 0x10, MulticastFilter1 = 0x14, RxRingPtr = 0x18,
  TxRingPtr = 0x1C, GFIFOTest = 0x54, MIIPhyAddr = 0x6C, MIIStatus = 0x6D,
  PCIBusConfig = 0x6E, MIICmd = 0x70, MIIRegAddr = 0x71, MIIData = 0x72,
  MACRegEEcsr = 0x74, ConfigA = 0x78, ConfigB = 0x79, ConfigC = 0x7A,
  ConfigD = 0x7B, RxMissed = 0x7C, RxCRCErrs = 0x7E, MiscCmd = 0x81,
  StickyHW = 0x83, IntrStatus2 = 0x84, WOLcrClr = 0xA4, WOLcgClr = 0xA7,
  PwrcsrClr = 0xAC
}

enum intr_status_bits {
  RFCON = 0x00020000, RFCOFF = 0x00010000, LSCStatus = 0x00008000, ANCStatus = 0x00004000,
  FBE = 0x00002000, FBEMask = 0x00001800, ParityErr = 0x00000000, TargetErr = 0x00001000,
  MasterErr = 0x00000800, TUNF = 0x00000400, ROVF = 0x00000200, ETI = 0x00000100,
  ERI = 0x00000080, CNTOVF = 0x00000040, RBU = 0x00000020, TBU = 0x00000010,
  TI = 0x00000008, RI = 0x00000004, RxErr = 0x00000002, IntrSummary = 0x0001,
  IntrPCIErr = 0x0002, IntrMACCtrl = 0x0008, IntrTxDone = 0x0004, IntrRxDone = 0x0010,
  IntrRxStart = 0x0020, IntrDrvRqst = 0x0040, StatsMax = 0x0080, LinkChange = 0x0100,
  IntrTxDMADone = 0x0200, IntrRxDMADone = 0x0400, IntrRxDone = 0x0001, IntrRxErr = 0x0004,
  IntrRxEmpty = 0x0020, IntrTxDone = 0x0002, IntrTxError = 0x0008, IntrTxUnderrun = 0x0210,
  IntrPCIErr = 0x0040, IntrStatsMax = 0x0080, IntrRxEarly = 0x0100, IntrRxOverflow = 0x0400,
  IntrRxDropped = 0x0800, IntrRxNoBuf = 0x1000, IntrTxAborted = 0x2000, IntrLinkChange = 0x4000,
  IntrRxWakeUp = 0x8000, IntrNormalSummary = 0x0003, IntrAbnormalSummary = 0xC260, IntrTxDescRace = 0x080000,
  IntrTxErrSummary = 0x082218, NormalIntr = 0x10000, AbnormalIntr = 0x8000, IntrPCIErr = 0x2000,
  TimerInt = 0x800, IntrRxDied = 0x100, RxNoBuf = 0x80, IntrRxDone = 0x40,
  TxFIFOUnderflow = 0x20, RxErrIntr = 0x10, TxIdle = 0x04, IntrTxStopped = 0x02,
  IntrTxDone = 0x01
}

Functions

static void rhine_probe1 (struct nic *nic, struct pci_device *pci, int ioaddr, int chip_id, int options)

static int QueryAuto (int)

static int ReadMII (int byMIIIndex, int)

static void WriteMII (char, char, char, int)

static void MIIDelay (void)

static void rhine_init_ring (struct nic *dev)

static void rhine_disable (struct nic *nic)

static void rhine_reset (struct nic *nic)

static int rhine_poll (struct nic *nic, int retreive)

static void rhine_transmit (struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)

static void reload_eeprom (int ioaddr)

void rhine_irq (struct nic *nic, irq_action_t action)

static int rhine_probe (struct nic *nic, struct pci_device *pci)

static void set_rx_mode (struct nic *nic __unused)

PCI_DRIVER (rhine_driver, rhine_nics, PCI_NO_CLASS)

DRIVER ("VIA 86C100", nic_driver, pci_driver, rhine_driver, rhine_probe, rhine_disable)

Variables

static const char * version = "rhine.c v1.0.2 2004-10-29\n"

struct {

   char   txbuf [TX_RING_SIZE *PKT_BUF_SZ+32]

   char   rxbuf [RX_RING_SIZE *PKT_BUF_SZ+32]

   char   txdesc [TX_RING_SIZE *sizeof(struct rhine_tx_desc)+32]

   char   rxdesc [RX_RING_SIZE *sizeof(struct rhine_rx_desc)+32]

} __shared

static int rhine_debug = 1

static struct rhine_private rhine

static struct nic_operations rhine_operations

static struct pci_device_id rhine_nics []

Define Documentation

#define W_MAX_TIMEOUT 0x0FFFU

Definition at line 26 of file via-rhine.c.

Referenced by enable_mii_autopoll(), rhine_probe1(), safe_disable_mii_autopoll(), velocity_mii_read(), velocity_mii_write(), and velocity_soft_reset().

#define RX_BUF_LEN_IDX 3

Definition at line 29 of file via-rhine.c.

#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)

Definition at line 30 of file via-rhine.c.

#define TX_BUF_SIZE 1536

Definition at line 33 of file via-rhine.c.

#define RX_BUF_SIZE 1536

Definition at line 34 of file via-rhine.c.

#define TX_FIFO_THRESH 256

Definition at line 38 of file via-rhine.c.

#define RX_FIFO_THRESH 4

Definition at line 41 of file via-rhine.c.

#define RX_DMA_BURST 4

Definition at line 42 of file via-rhine.c.

#define TX_DMA_BURST 4

Definition at line 43 of file via-rhine.c.

#define TX_TIMEOUT ((2000*HZ)/1000)

Definition at line 47 of file via-rhine.c.

#define byPAR0 ioaddr

Definition at line 56 of file via-rhine.c.

Referenced by rhine_probe1().

#define byRCR ioaddr + 6

Definition at line 57 of file via-rhine.c.

Referenced by rhine_reset(), and set_rx_mode().

#define byTCR ioaddr + 7

Definition at line 58 of file via-rhine.c.

Referenced by rhine_disable(), and rhine_reset().

#define byCR0 ioaddr + 8

Definition at line 59 of file via-rhine.c.

Referenced by rhine_disable(), rhine_probe1(), rhine_reset(), and rhine_transmit().

#define byCR1 ioaddr + 9

Definition at line 60 of file via-rhine.c.

Referenced by rhine_reset(), and rhine_transmit().

#define byISR0 ioaddr + 0x0c

Definition at line 61 of file via-rhine.c.

#define byISR1 ioaddr + 0x0d

Definition at line 62 of file via-rhine.c.

#define byIMR0 ioaddr + 0x0e

Definition at line 63 of file via-rhine.c.

Referenced by rhine_reset().

#define byIMR1 ioaddr + 0x0f

Definition at line 64 of file via-rhine.c.

#define byMAR0 ioaddr + 0x10

Definition at line 65 of file via-rhine.c.

Referenced by set_rx_mode().

#define byMAR1 ioaddr + 0x11

Definition at line 66 of file via-rhine.c.

#define byMAR2 ioaddr + 0x12

Definition at line 67 of file via-rhine.c.

#define byMAR3 ioaddr + 0x13

Definition at line 68 of file via-rhine.c.

#define byMAR4 ioaddr + 0x14

Definition at line 69 of file via-rhine.c.

Referenced by set_rx_mode().

#define byMAR5 ioaddr + 0x15

Definition at line 70 of file via-rhine.c.

#define byMAR6 ioaddr + 0x16

Definition at line 71 of file via-rhine.c.

#define byMAR7 ioaddr + 0x17

Definition at line 72 of file via-rhine.c.

#define dwCurrentRxDescAddr ioaddr + 0x18

Definition at line 73 of file via-rhine.c.

Referenced by rhine_reset().

#define dwCurrentTxDescAddr ioaddr + 0x1c

Definition at line 74 of file via-rhine.c.

Referenced by rhine_reset().

#define dwCurrentRDSE0 ioaddr + 0x20

Definition at line 75 of file via-rhine.c.

#define dwCurrentRDSE1 ioaddr + 0x24

Definition at line 76 of file via-rhine.c.

#define dwCurrentRDSE2 ioaddr + 0x28

Definition at line 77 of file via-rhine.c.

#define dwCurrentRDSE3 ioaddr + 0x2c

Definition at line 78 of file via-rhine.c.

#define dwNextRDSE0 ioaddr + 0x30

Definition at line 79 of file via-rhine.c.

#define dwNextRDSE1 ioaddr + 0x34

Definition at line 80 of file via-rhine.c.

#define dwNextRDSE2 ioaddr + 0x38

Definition at line 81 of file via-rhine.c.

#define dwNextRDSE3 ioaddr + 0x3c

Definition at line 82 of file via-rhine.c.

#define dwCurrentTDSE0 ioaddr + 0x40

Definition at line 83 of file via-rhine.c.

#define dwCurrentTDSE1 ioaddr + 0x44

Definition at line 84 of file via-rhine.c.

#define dwCurrentTDSE2 ioaddr + 0x48

Definition at line 85 of file via-rhine.c.

#define dwCurrentTDSE3 ioaddr + 0x4c

Definition at line 86 of file via-rhine.c.

#define dwNextTDSE0 ioaddr + 0x50

Definition at line 87 of file via-rhine.c.

#define dwNextTDSE1 ioaddr + 0x54

Definition at line 88 of file via-rhine.c.

#define dwNextTDSE2 ioaddr + 0x58

Definition at line 89 of file via-rhine.c.

#define dwNextTDSE3 ioaddr + 0x5c

Definition at line 90 of file via-rhine.c.

#define dwCurrRxDMAPtr ioaddr + 0x60

Definition at line 91 of file via-rhine.c.

#define dwCurrTxDMAPtr ioaddr + 0x64

Definition at line 92 of file via-rhine.c.

#define byMPHY ioaddr + 0x6c

Definition at line 93 of file via-rhine.c.

#define byMIISR ioaddr + 0x6d

Definition at line 94 of file via-rhine.c.

#define byBCR0 ioaddr + 0x6e

Definition at line 95 of file via-rhine.c.

Referenced by rhine_reset().

#define byBCR1 ioaddr + 0x6f

Definition at line 96 of file via-rhine.c.

Referenced by rhine_reset().

#define byMIICR ioaddr + 0x70

Definition at line 97 of file via-rhine.c.

Referenced by ReadMII(), rhine_probe1(), and WriteMII().

#define byMIIAD ioaddr + 0x71

Definition at line 98 of file via-rhine.c.

Referenced by ReadMII(), rhine_probe1(), and WriteMII().

#define wMIIDATA ioaddr + 0x72

Definition at line 99 of file via-rhine.c.

Referenced by ReadMII(), and WriteMII().

#define byEECSR ioaddr + 0x74

Definition at line 100 of file via-rhine.c.

Referenced by reload_eeprom(), and rhine_probe1().

#define byTEST ioaddr + 0x75

Definition at line 101 of file via-rhine.c.

#define byGPIO ioaddr + 0x76

Definition at line 102 of file via-rhine.c.

#define byCFGA ioaddr + 0x78

Definition at line 103 of file via-rhine.c.

Referenced by rhine_probe1().

#define byCFGB ioaddr + 0x79

Definition at line 104 of file via-rhine.c.

#define byCFGC ioaddr + 0x7a

Definition at line 105 of file via-rhine.c.

#define byCFGD ioaddr + 0x7b

Definition at line 106 of file via-rhine.c.

Referenced by rhine_probe1(), and rhine_reset().

#define wTallyCntMPA ioaddr + 0x7c

Definition at line 107 of file via-rhine.c.

#define wTallyCntCRC ioaddr + 0x7d

Definition at line 108 of file via-rhine.c.

#define bySTICKHW ioaddr + 0x83

Definition at line 109 of file via-rhine.c.

Referenced by rhine_probe1().

#define byWOLcrClr ioaddr + 0xA4

Definition at line 110 of file via-rhine.c.

Referenced by rhine_probe1().

#define byWOLcgClr ioaddr + 0xA7

Definition at line 111 of file via-rhine.c.

Referenced by rhine_probe1().

#define byPwrcsrClr ioaddr + 0xAC

Definition at line 112 of file via-rhine.c.

Referenced by rhine_probe1().

#define RCR_RRFT2 0x80

Definition at line 120 of file via-rhine.c.

#define RCR_RRFT1 0x40

Definition at line 121 of file via-rhine.c.

#define RCR_RRFT0 0x20

Definition at line 122 of file via-rhine.c.

#define RCR_PROM 0x10

Definition at line 123 of file via-rhine.c.

#define RCR_AB 0x08

Definition at line 124 of file via-rhine.c.

#define RCR_AM 0x04

Definition at line 125 of file via-rhine.c.

#define RCR_AR 0x02

Definition at line 126 of file via-rhine.c.

#define RCR_SEP 0x01

Definition at line 127 of file via-rhine.c.

#define TCR_RTSF 0x80

Definition at line 133 of file via-rhine.c.

#define TCR_RTFT1 0x40

Definition at line 134 of file via-rhine.c.

#define TCR_RTFT0 0x20

Definition at line 135 of file via-rhine.c.

#define TCR_OFSET 0x08

Definition at line 136 of file via-rhine.c.

#define TCR_LB1 0x04

Definition at line 137 of file via-rhine.c.

#define TCR_LB0 0x02

Definition at line 138 of file via-rhine.c.

#define CR0_RDMD 0x40

Definition at line 144 of file via-rhine.c.

#define CR0_TDMD 0x20

Definition at line 145 of file via-rhine.c.

#define CR0_TXON 0x10

Definition at line 146 of file via-rhine.c.

Referenced by velocity_init_registers().

#define CR0_RXON 0x08

Definition at line 147 of file via-rhine.c.

Referenced by velocity_init_registers().

#define CR0_STOP 0x04

Definition at line 148 of file via-rhine.c.

Referenced by velocity_disable(), and velocity_init_registers().

#define CR0_STRT 0x02

Definition at line 149 of file via-rhine.c.

Referenced by velocity_init_registers().

#define CR0_INIT 0x01

Definition at line 150 of file via-rhine.c.

#define CR1_SFRST 0x80

Definition at line 157 of file via-rhine.c.

Referenced by rhine_reset().

#define CR1_RDMD1 0x40

Definition at line 158 of file via-rhine.c.

#define CR1_TDMD1 0x20

Definition at line 159 of file via-rhine.c.

Referenced by rhine_transmit().

#define CR1_KEYPAG 0x10

Definition at line 160 of file via-rhine.c.

#define CR1_DPOLL 0x08

Definition at line 161 of file via-rhine.c.

#define CR1_FDX 0x04

Definition at line 162 of file via-rhine.c.

#define CR1_ETEN 0x02

Definition at line 163 of file via-rhine.c.

#define CR1_EREN 0x01

Definition at line 164 of file via-rhine.c.

#define CR_RDMD 0x0040

Definition at line 170 of file via-rhine.c.

#define CR_TDMD 0x0020

Definition at line 171 of file via-rhine.c.

#define CR_TXON 0x0010

Definition at line 172 of file via-rhine.c.

Referenced by rhine_reset(), and rhine_transmit().

#define CR_RXON 0x0008

Definition at line 173 of file via-rhine.c.

Referenced by rhine_reset().

#define CR_STOP 0x0004

Definition at line 174 of file via-rhine.c.

Referenced by rhine_disable().

#define CR_STRT 0x0002

Definition at line 175 of file via-rhine.c.

Referenced by rhine_reset().

#define CR_INIT 0x0001

Definition at line 176 of file via-rhine.c.

#define CR_SFRST 0x8000

Definition at line 177 of file via-rhine.c.

Referenced by rhine_probe1().

#define CR_RDMD1 0x4000

Definition at line 178 of file via-rhine.c.

#define CR_TDMD1 0x2000

Definition at line 179 of file via-rhine.c.

#define CR_KEYPAG 0x1000

Definition at line 180 of file via-rhine.c.

#define CR_DPOLL 0x0800

Definition at line 181 of file via-rhine.c.

Referenced by rhine_reset().

#define CR_FDX 0x0400

Definition at line 182 of file via-rhine.c.

Referenced by rhine_probe1(), and rhine_reset().

#define CR_ETEN 0x0200

Definition at line 183 of file via-rhine.c.

#define CR_EREN 0x0100

Definition at line 184 of file via-rhine.c.

#define IMR0_CNTM 0x80

Definition at line 190 of file via-rhine.c.

#define IMR0_BEM 0x40

Definition at line 191 of file via-rhine.c.

#define IMR0_RUM 0x20

Definition at line 192 of file via-rhine.c.

#define IMR0_TUM 0x10

Definition at line 193 of file via-rhine.c.

#define IMR0_TXEM 0x08

Definition at line 194 of file via-rhine.c.

#define IMR0_RXEM 0x04

Definition at line 195 of file via-rhine.c.

#define IMR0_PTXM 0x02

Definition at line 196 of file via-rhine.c.

#define IMR0_PRXM 0x01

Definition at line 197 of file via-rhine.c.

#define IMRShadow 0x5AFF

Definition at line 201 of file via-rhine.c.

#define IMR1_INITM 0x80

Definition at line 207 of file via-rhine.c.

#define IMR1_SRCM 0x40

Definition at line 208 of file via-rhine.c.

#define IMR1_NBFM 0x10

Definition at line 209 of file via-rhine.c.

#define IMR1_PRAIM 0x08

Definition at line 210 of file via-rhine.c.

#define IMR1_RES0M 0x04

Definition at line 211 of file via-rhine.c.

#define IMR1_ETM 0x02

Definition at line 212 of file via-rhine.c.

#define IMR1_ERM 0x01

Definition at line 213 of file via-rhine.c.

#define ISR_INITI 0x8000

Definition at line 219 of file via-rhine.c.

#define ISR_SRCI 0x4000

Definition at line 220 of file via-rhine.c.

#define ISR_ABTI 0x2000

Definition at line 221 of file via-rhine.c.

#define ISR_NORBF 0x1000

Definition at line 222 of file via-rhine.c.

#define ISR_PKTRA 0x0800

Definition at line 223 of file via-rhine.c.

#define ISR_RES0 0x0400

Definition at line 224 of file via-rhine.c.

#define ISR_ETI 0x0200

Definition at line 225 of file via-rhine.c.

#define ISR_ERI 0x0100

Definition at line 226 of file via-rhine.c.

#define ISR_CNT 0x0080

Definition at line 227 of file via-rhine.c.

#define ISR_BE 0x0040

Definition at line 228 of file via-rhine.c.

#define ISR_RU 0x0020

Definition at line 229 of file via-rhine.c.

#define ISR_TU 0x0010

Definition at line 230 of file via-rhine.c.

#define ISR_TXE 0x0008

Definition at line 231 of file via-rhine.c.

#define ISR_RXE 0x0004

Definition at line 232 of file via-rhine.c.

#define ISR_PTX 0x0002

Definition at line 233 of file via-rhine.c.

#define ISR_PRX 0x0001

Definition at line 234 of file via-rhine.c.

#define ISR0_CNT 0x80

Definition at line 240 of file via-rhine.c.

#define ISR0_BE 0x40

Definition at line 241 of file via-rhine.c.

#define ISR0_RU 0x20

Definition at line 242 of file via-rhine.c.

#define ISR0_TU 0x10

Definition at line 243 of file via-rhine.c.

#define ISR0_TXE 0x08

Definition at line 244 of file via-rhine.c.

#define ISR0_RXE 0x04

Definition at line 245 of file via-rhine.c.

#define ISR0_PTX 0x02

Definition at line 246 of file via-rhine.c.

#define ISR0_PRX 0x01

Definition at line 247 of file via-rhine.c.

#define ISR1_INITI 0x80

Definition at line 253 of file via-rhine.c.

#define ISR1_SRCI 0x40

Definition at line 254 of file via-rhine.c.

#define ISR1_NORBF 0x10

Definition at line 255 of file via-rhine.c.

#define ISR1_PKTRA 0x08

Definition at line 256 of file via-rhine.c.

#define ISR1_ETI 0x02

Definition at line 257 of file via-rhine.c.

#define ISR1_ERI 0x01

Definition at line 258 of file via-rhine.c.

#define ISR_ABNORMAL ISR_BE+ISR_RU+ISR_TU+ISR_CNT+ISR_NORBF+ISR_PKTRA

Definition at line 262 of file via-rhine.c.

#define MIISR_MIIERR 0x08

Definition at line 268 of file via-rhine.c.

#define MIISR_MRERR 0x04

Definition at line 269 of file via-rhine.c.

#define MIISR_LNKFL 0x02

Definition at line 270 of file via-rhine.c.

#define MIISR_SPEED 0x01

Definition at line 271 of file via-rhine.c.

Referenced by rhine_probe1().

#define MIICR_MAUTO 0x80

Definition at line 277 of file via-rhine.c.

Referenced by enable_mii_autopoll().

#define MIICR_RCMD 0x40

Definition at line 278 of file via-rhine.c.

Referenced by velocity_mii_read().

#define MIICR_WCMD 0x20

Definition at line 279 of file via-rhine.c.

Referenced by velocity_mii_write().

#define MIICR_MDPM 0x10

Definition at line 280 of file via-rhine.c.

#define MIICR_MOUT 0x08

Definition at line 281 of file via-rhine.c.

#define MIICR_MDO 0x04

Definition at line 282 of file via-rhine.c.

#define MIICR_MDI 0x02

Definition at line 283 of file via-rhine.c.

#define MIICR_MDC 0x01

Definition at line 284 of file via-rhine.c.

#define EECSR_EEPR 0x80

Definition at line 290 of file via-rhine.c.

#define EECSR_EMBP 0x40

Definition at line 291 of file via-rhine.c.

#define EECSR_AUTOLD 0x20

Definition at line 292 of file via-rhine.c.

#define EECSR_DPM 0x10

Definition at line 293 of file via-rhine.c.

#define EECSR_CS 0x08

Definition at line 294 of file via-rhine.c.

#define EECSR_SK 0x04

Definition at line 295 of file via-rhine.c.

#define EECSR_DI 0x02

Definition at line 296 of file via-rhine.c.

#define EECSR_DO 0x01

Definition at line 297 of file via-rhine.c.

#define BCR0_CRFT2 0x20

Definition at line 303 of file via-rhine.c.

#define BCR0_CRFT1 0x10

Definition at line 304 of file via-rhine.c.

#define BCR0_CRFT0 0x08

Definition at line 305 of file via-rhine.c.

#define BCR0_DMAL2 0x04

Definition at line 306 of file via-rhine.c.

#define BCR0_DMAL1 0x02

Definition at line 307 of file via-rhine.c.

#define BCR0_DMAL0 0x01

Definition at line 308 of file via-rhine.c.

#define BCR1_CTSF 0x20

Definition at line 314 of file via-rhine.c.

#define BCR1_CTFT1 0x10

Definition at line 315 of file via-rhine.c.

#define BCR1_CTFT0 0x08

Definition at line 316 of file via-rhine.c.

#define BCR1_POT2 0x04

Definition at line 317 of file via-rhine.c.

#define BCR1_POT1 0x02

Definition at line 318 of file via-rhine.c.

#define BCR1_POT0 0x01

Definition at line 319 of file via-rhine.c.

#define CFGA_EELOAD 0x80

Definition at line 325 of file via-rhine.c.

#define CFGA_JUMPER 0x40

Definition at line 326 of file via-rhine.c.

#define CFGA_MTGPIO 0x08

Definition at line 327 of file via-rhine.c.

#define CFGA_T10EN 0x02

Definition at line 328 of file via-rhine.c.

#define CFGA_AUTO 0x01

Definition at line 329 of file via-rhine.c.

#define CFGB_PD 0x80

Definition at line 335 of file via-rhine.c.

#define CFGB_POLEN 0x02

Definition at line 336 of file via-rhine.c.

#define CFGB_LNKEN 0x01

Definition at line 337 of file via-rhine.c.

#define CFGC_M10TIO 0x80

Definition at line 343 of file via-rhine.c.

#define CFGC_M10POL 0x40

Definition at line 344 of file via-rhine.c.

#define CFGC_PHY1 0x20

Definition at line 345 of file via-rhine.c.

#define CFGC_PHY0 0x10

Definition at line 346 of file via-rhine.c.

#define CFGC_BTSEL 0x08

Definition at line 347 of file via-rhine.c.

#define CFGC_BPS2 0x04

Definition at line 348 of file via-rhine.c.

#define CFGC_BPS1 0x02

Definition at line 349 of file via-rhine.c.

#define CFGC_BPS0 0x01

Definition at line 350 of file via-rhine.c.

#define CFGD_GPIOEN 0x80

Definition at line 356 of file via-rhine.c.

#define CFGD_DIAG 0x40

Definition at line 357 of file via-rhine.c.

#define CFGD_MAGIC 0x10

Definition at line 358 of file via-rhine.c.

#define CFGD_RANDOM 0x08

Definition at line 359 of file via-rhine.c.

Referenced by rhine_probe1().

#define CFGD_CFDX 0x04

Definition at line 360 of file via-rhine.c.

Referenced by rhine_probe1(), and rhine_reset().

#define CFGD_CEREN 0x02

Definition at line 361 of file via-rhine.c.

Referenced by rhine_probe1().

#define CFGD_CETEN 0x01

Definition at line 362 of file via-rhine.c.

Referenced by rhine_probe1().

#define RSR_RERR 0x00000001

Definition at line 365 of file via-rhine.c.

#define RSR_CRC 0x00000002

Definition at line 366 of file via-rhine.c.

#define RSR_FAE 0x00000004

Definition at line 367 of file via-rhine.c.

#define RSR_FOV 0x00000008

Definition at line 368 of file via-rhine.c.

#define RSR_LONG 0x00000010

Definition at line 369 of file via-rhine.c.

#define RSR_RUNT 0x00000020

Definition at line 370 of file via-rhine.c.

#define RSR_SERR 0x00000040

Definition at line 371 of file via-rhine.c.

#define RSR_BUFF 0x00000080

Definition at line 372 of file via-rhine.c.

#define RSR_EDP 0x00000100

Definition at line 373 of file via-rhine.c.

#define RSR_STP 0x00000200

Definition at line 374 of file via-rhine.c.

#define RSR_CHN 0x00000400

Definition at line 375 of file via-rhine.c.

#define RSR_PHY 0x00000800

Definition at line 376 of file via-rhine.c.

#define RSR_BAR 0x00001000

Definition at line 377 of file via-rhine.c.

#define RSR_MAR 0x00002000

Definition at line 378 of file via-rhine.c.

#define RSR_RXOK 0x00008000

Definition at line 379 of file via-rhine.c.

Referenced by velocity_poll().

#define RSR_ABNORMAL RSR_RERR+RSR_LONG+RSR_RUNT

Definition at line 380 of file via-rhine.c.

Referenced by rhine_poll().

#define TSR_NCR0 0x00000001

Definition at line 383 of file via-rhine.c.

#define TSR_NCR1 0x00000002

Definition at line 384 of file via-rhine.c.

#define TSR_NCR2 0x00000004

Definition at line 385 of file via-rhine.c.

#define TSR_NCR3 0x00000008

Definition at line 386 of file via-rhine.c.

#define TSR_COLS 0x00000010

Definition at line 387 of file via-rhine.c.

#define TSR_CDH 0x00000080

Definition at line 388 of file via-rhine.c.

#define TSR_ABT 0x00000100

Definition at line 389 of file via-rhine.c.

#define TSR_OWC 0x00000200

Definition at line 390 of file via-rhine.c.

#define TSR_CRS 0x00000400

Definition at line 391 of file via-rhine.c.

#define TSR_UDF 0x00000800

Definition at line 392 of file via-rhine.c.

#define TSR_TBUFF 0x00001000

Definition at line 393 of file via-rhine.c.

#define TSR_SERR 0x00002000

Definition at line 394 of file via-rhine.c.

#define TSR_JAB 0x00004000

Definition at line 395 of file via-rhine.c.

#define TSR_TERR 0x00008000

Definition at line 396 of file via-rhine.c.

#define TSR_ABNORMAL TSR_TERR+TSR_OWC+TSR_ABT+TSR_JAB+TSR_CRS

Definition at line 397 of file via-rhine.c.

#define TSR_OWN_BIT 0x80000000

Definition at line 398 of file via-rhine.c.

#define CB_DELAY_LOOP_WAIT 10

Definition at line 400 of file via-rhine.c.

#define W_IMR_MASK_VALUE 0x1BFF

Definition at line 403 of file via-rhine.c.

#define PKT_TYPE_DIRECTED 0x0001

Definition at line 406 of file via-rhine.c.

#define PKT_TYPE_MULTICAST 0x0002

Definition at line 407 of file via-rhine.c.

#define PKT_TYPE_ALL_MULTICAST 0x0004

Definition at line 408 of file via-rhine.c.

#define PKT_TYPE_BROADCAST 0x0008

Definition at line 409 of file via-rhine.c.

#define PKT_TYPE_PROMISCUOUS 0x0020

Definition at line 410 of file via-rhine.c.

#define PKT_TYPE_LONG 0x2000

Definition at line 411 of file via-rhine.c.

#define PKT_TYPE_RUNT 0x4000

Definition at line 412 of file via-rhine.c.

#define PKT_TYPE_ERROR 0x8000

Definition at line 413 of file via-rhine.c.

#define NIC_LB_NONE 0x00

Definition at line 417 of file via-rhine.c.

#define NIC_LB_INTERNAL 0x01

Definition at line 418 of file via-rhine.c.

#define NIC_LB_PHY 0x02

Definition at line 419 of file via-rhine.c.

#define TX_RING_SIZE 2

Definition at line 421 of file via-rhine.c.

#define RX_RING_SIZE 2

Definition at line 422 of file via-rhine.c.

#define PKT_BUF_SZ 1536

Definition at line 423 of file via-rhine.c.

#define PCI_REG_MODE3 0x53

Definition at line 425 of file via-rhine.c.

Referenced by rhine_probe1().

#define MODE3_MIION 0x04

Definition at line 426 of file via-rhine.c.

Referenced by rhine_probe1().

#define rhine_TOTAL_SIZE 0x80

Definition at line 557 of file via-rhine.c.

#define NUM_TX_DESC 2

Definition at line 656 of file via-rhine.c.

#define DEFAULT_INTR

Value:

(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | \
                   IntrRxDropped | IntrRxNoBuf)

Definition at line 928 of file via-rhine.c.

#define IOSYNC do { inb(nic->ioaddr + StationAddr); } while (0)

Definition at line 1286 of file via-rhine.c.

Referenced by rhine_poll().

Enumeration Type Documentation

enum rhine_revs

Enumerator:

VT86C100A
VTunknown0
VT6102
VT8231
VT8233
VT8235
VT8237
VTunknown1
VT6105
VT6105_B0
VT6105L
VT6107
VTunknown2
VT6105M

Definition at line 428 of file via-rhine.c.

00428                 {
00429     VT86C100A       = 0x00,
00430     VTunknown0      = 0x20,
00431     VT6102          = 0x40,
00432     VT8231          = 0x50, /* Integrated MAC */
00433     VT8233          = 0x60, /* Integrated MAC */
00434     VT8235          = 0x74, /* Integrated MAC */
00435     VT8237          = 0x78, /* Integrated MAC */
00436     VTunknown1      = 0x7C,
00437     VT6105          = 0x80,
00438     VT6105_B0       = 0x83,
00439     VT6105L         = 0x8A,
00440     VT6107          = 0x8C,
00441     VTunknown2      = 0x8E,
00442     VT6105M         = 0x90,
00443 };

enum register_offsets

Enumerator:

ChipCmd
ChipConfig
EECtrl
PCIBusCfg
IntrStatus
IntrMask
IntrEnable
TxRingPtr
TxConfig
RxRingPtr
RxConfig
ClkRun
WOLCmd
PauseCmd
RxFilterAddr
RxFilterData
BootRomAddr
BootRomData
SiliconRev
StatsCtrl
StatsData
RxPktErrs
RxMissed
RxCRCErrs
PCIPM
PhyStatus
MIntrCtrl
MIntrStatus
PGSEL
PMDCSR
TSTDAT
DSPCFG
SDCFG
BasicControl
BasicStatus
StationAddr
RxConfig
TxConfig
ChipCmd
IntrStatus
IntrEnable
MulticastFilter0
MulticastFilter1
RxRingPtr
TxRingPtr
GFIFOTest
MIIPhyAddr
MIIStatus
PCIBusConfig
MIICmd
MIIRegAddr
MIIData
MACRegEEcsr
ConfigA
ConfigB
ConfigC
ConfigD
RxMissed
RxCRCErrs
MiscCmd
StickyHW
IntrStatus2
WOLcrClr
WOLcgClr
PwrcsrClr

Definition at line 902 of file via-rhine.c.

00902                       {
00903         StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
00904         IntrStatus=0x0C, IntrEnable=0x0E,
00905         MulticastFilter0=0x10, MulticastFilter1=0x14,
00906         RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
00907         MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
00908         MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
00909         ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
00910         RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
00911         StickyHW=0x83, IntrStatus2=0x84, WOLcrClr=0xA4, WOLcgClr=0xA7,
00912         PwrcsrClr=0xAC,
00913 };

enum intr_status_bits

Enumerator:

RFCON
RFCOFF
LSCStatus
ANCStatus
FBE
FBEMask
ParityErr
TargetErr
MasterErr
TUNF
ROVF
ETI
ERI
CNTOVF
RBU
TBU
TI
RI
RxErr
IntrSummary
IntrPCIErr
IntrMACCtrl
IntrTxDone
IntrRxDone
IntrRxStart
IntrDrvRqst
StatsMax
LinkChange
IntrTxDMADone
IntrRxDMADone
IntrRxDone
IntrRxErr
IntrRxEmpty
IntrTxDone
IntrTxError
IntrTxUnderrun
IntrPCIErr
IntrStatsMax
IntrRxEarly
IntrRxOverflow
IntrRxDropped
IntrRxNoBuf
IntrTxAborted
IntrLinkChange
IntrRxWakeUp
IntrNormalSummary
IntrAbnormalSummary
IntrTxDescRace
IntrTxErrSummary
NormalIntr
AbnormalIntr
IntrPCIErr
TimerInt
IntrRxDied
RxNoBuf
IntrRxDone
TxFIFOUnderflow
RxErrIntr
TxIdle
IntrTxStopped
IntrTxDone

Definition at line 916 of file via-rhine.c.

00916                       {
00917         IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
00918         IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
00919         IntrPCIErr=0x0040,
00920         IntrStatsMax=0x0080, IntrRxEarly=0x0100,
00921         IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
00922         IntrTxAborted=0x2000, IntrLinkChange=0x4000,
00923         IntrRxWakeUp=0x8000,
00924         IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
00925         IntrTxDescRace=0x080000,        /* mapped from IntrStatus2 */
00926         IntrTxErrSummary=0x082218,
00927 };

Function Documentation

static void rhine_probe1	(	struct nic *	nic,
		struct pci_device *	pci,
		int	ioaddr,
		int	chip_id,
		int	options
	)			`[static]`

Definition at line 999 of file via-rhine.c.

References byCFGA, byCFGD, byCR0, byEECSR, byMIIAD, byMIICR, byPAR0, byPwrcsrClr, bySTICKHW, byWOLcgClr, byWOLcrClr, CFGD_CEREN, CFGD_CETEN, CFGD_CFDX, CFGD_RANDOM, rhine_private::chip_id, rhine_private::chip_revision, CR_FDX, CR_SFRST, currticks(), DBG, rhine_private::default_port, ETH_ALEN, eth_ntoa(), rhine_private::full_duplex, inb, inw, rhine_private::ioaddr, mdelay(), rhine_private::medialock, MIIDelay(), MIISR_SPEED, MODE3_MIION, nic::node_addr, outb, outw, pci_read_config_byte(), PCI_REG_MODE3, PCI_REVISION, pci_write_config_byte(), rhine_private::phys, printf(), nic::priv_data, QueryAuto(), ReadMII(), reload_eeprom(), rhine, rhine_debug, timeout(), tp, udelay(), version, W_MAX_TIMEOUT, and WriteMII().

Referenced by rhine_probe().

01000 {
01001     struct rhine_private *tp;
01002     static int did_version = 0; /* Already printed version info. */
01003     unsigned int i, ww;
01004     unsigned int timeout;
01005     int FDXFlag;
01006     int byMIIvalue, LineSpeed, MIICRbak;
01007     uint8_t revision_id;    
01008     unsigned char mode3_reg;
01009 
01010     if (rhine_debug > 0 && did_version++ == 0)
01011         printf ("%s",version);
01012 
01013     // get revision id.
01014     pci_read_config_byte(pci, PCI_REVISION, &revision_id);
01015 
01016     /* D-Link provided reset code (with comment additions) */
01017     if (revision_id >= 0x40) {
01018         unsigned char byOrgValue;
01019         
01020         if(rhine_debug > 0)
01021                 printf("Enabling Sticky Bit Workaround for Chip_id: 0x%hX\n"
01022                                 , chip_id);
01023         /* clear sticky bit before reset & read ethernet address */
01024         byOrgValue = inb(bySTICKHW);
01025         byOrgValue = byOrgValue & 0xFC;
01026         outb(byOrgValue, bySTICKHW);
01027 
01028         /* (bits written are cleared?) */
01029         /* disable force PME-enable */
01030         outb(0x80, byWOLcgClr);
01031         /* disable power-event config bit */
01032         outb(0xFF, byWOLcrClr);
01033         /* clear power status (undocumented in vt6102 docs?) */
01034         outb(0xFF, byPwrcsrClr);
01035         
01036     }
01037 
01038     /* Reset the chip to erase previous misconfiguration. */
01039     outw(CR_SFRST, byCR0);
01040     // if vt3043 delay after reset
01041     if (revision_id <0x40) {
01042        udelay(10000);
01043     }
01044     // polling till software reset complete
01045     // W_MAX_TIMEOUT is the timeout period
01046     for(ww = 0; ww < W_MAX_TIMEOUT; ww++) {
01047         if ((inw(byCR0) & CR_SFRST) == 0)
01048                 break;
01049         }
01050 
01051     // issue AUTOLoad in EECSR to reload eeprom
01052     outb(0x20, byEECSR );
01053 
01054     // if vt3065 delay after reset
01055     if (revision_id >=0x40) {
01056         // delay 8ms to let MAC stable
01057         mdelay(8);
01058         /*
01059          * for 3065D, EEPROM reloaded will cause bit 0 in MAC_REG_CFGA
01060          * turned on.  it makes MAC receive magic packet
01061          * automatically. So, we turn it off. (D-Link)
01062          */
01063          outb(inb(byCFGA) & 0xFE, byCFGA);
01064     }
01065 
01066     /* turn on bit2 in PCI configuration register 0x53 , only for 3065*/
01067     if (revision_id >= 0x40) {
01068         pci_read_config_byte(pci, PCI_REG_MODE3, &mode3_reg);
01069         pci_write_config_byte(pci, PCI_REG_MODE3, mode3_reg|MODE3_MIION);
01070     }
01071 
01072 
01073     /* back off algorithm ,disable the right-most 4-bit off CFGD*/
01074     outb(inb(byCFGD) & (~(CFGD_RANDOM | CFGD_CFDX | CFGD_CEREN | CFGD_CETEN)), byCFGD);
01075 
01076     /* reload eeprom */
01077     reload_eeprom(ioaddr);
01078 
01079     /* Perhaps this should be read from the EEPROM? */
01080     for (i = 0; i < ETH_ALEN; i++)
01081         nic->node_addr[i] = inb (byPAR0 + i);
01082 
01083     DBG ( "IO address %#hX Ethernet Address: %s\n", ioaddr, eth_ntoa ( nic->node_addr ) );
01084 
01085     /* restart MII auto-negotiation */
01086     WriteMII (0, 9, 1, ioaddr);
01087     printf ("Analyzing Media type,this may take several seconds... ");
01088     for (i = 0; i < 5; i++)
01089     {
01090         /* need to wait 1 millisecond - we will round it up to 50-100ms */
01091         timeout = currticks() + 2;
01092         for (timeout = currticks() + 2; currticks() < timeout;)
01093             /* nothing */;
01094         if (ReadMII (1, ioaddr) & 0x0020)
01095             break;
01096     }
01097     printf ("OK.\n");
01098 
01099 #if 0
01100         /* JJM : for Debug */
01101         printf("MII : Address %hhX ",inb(ioaddr+0x6c));
01102         {
01103          unsigned char st1,st2,adv1,adv2,l1,l2;
01104         
01105          st1=ReadMII(1,ioaddr)>>8;
01106          st2=ReadMII(1,ioaddr)&0xFF;
01107          adv1=ReadMII(4,ioaddr)>>8;
01108          adv2=ReadMII(4,ioaddr)&0xFF;
01109          l1=ReadMII(5,ioaddr)>>8;
01110          l2=ReadMII(5,ioaddr)&0xFF;
01111          printf(" status 0x%hhX%hhX, advertising 0x%hhX%hhX, link 0x%hhX%hhX\n", st1,st2,adv1,adv2,l1,l2);
01112         }
01113 #endif
01114 
01115     
01116     /* query MII to know LineSpeed,duplex mode */
01117     byMIIvalue = inb (ioaddr + 0x6d);
01118     LineSpeed = byMIIvalue & MIISR_SPEED;
01119     if (LineSpeed != 0)                                         //JJM
01120     {
01121         printf ("Linespeed=10Mbs");
01122     }
01123     else
01124     {
01125         printf ("Linespeed=100Mbs");
01126     }
01127         
01128     FDXFlag = QueryAuto (ioaddr);
01129     if (FDXFlag == 1)
01130     {
01131         printf (" Fullduplex\n");
01132         outw (CR_FDX, byCR0);
01133     }
01134     else
01135     {
01136         printf (" Halfduplex\n");
01137     }
01138 
01139 
01140     /* set MII 10 FULL ON, only apply in vt3043 */
01141     if(chip_id == 0x3043)
01142         WriteMII (0x17, 1, 1, ioaddr);
01143 
01144     /* turn on MII link change */
01145     MIICRbak = inb (byMIICR);
01146     outb (MIICRbak & 0x7F, byMIICR);
01147     MIIDelay ();
01148     outb (0x41, byMIIAD);
01149     MIIDelay ();
01150 
01151     /* while((inb(byMIIAD)&0x20)==0) ; */
01152     outb (MIICRbak | 0x80, byMIICR);
01153 
01154     nic->priv_data = &rhine;
01155     tp = &rhine;
01156     tp->chip_id = chip_id;
01157     tp->ioaddr = ioaddr;
01158     tp->phys[0] = -1;
01159     tp->chip_revision = revision_id;
01160 
01161     /* The lower four bits are the media type. */
01162     if (options > 0)
01163     {
01164         tp->full_duplex = (options & 16) ? 1 : 0;
01165         tp->default_port = options & 15;
01166         if (tp->default_port)
01167             tp->medialock = 1;
01168     }
01169     return;
01170 }

int QueryAuto ( int ioaddr ) [static]

Definition at line 755 of file via-rhine.c.

References ReadMII().

Referenced by rhine_probe1(), and rhine_reset().

00756 {
00757     int byMIIIndex;
00758     int MIIReturn;
00759 
00760         int advertising,mii_reg5;
00761         int negociated;
00762 
00763     byMIIIndex = 0x04;
00764     MIIReturn = ReadMII (byMIIIndex, ioaddr);
00765         advertising=MIIReturn;
00766 
00767     byMIIIndex = 0x05;
00768     MIIReturn = ReadMII (byMIIIndex, ioaddr);
00769         mii_reg5=MIIReturn;
00770 
00771         negociated=mii_reg5 & advertising;
00772 
00773         if ( (negociated & 0x100) || (negociated & 0x1C0) == 0x40 )
00774                 return 1;
00775         else
00776                 return 0;
00777 
00778 }

int ReadMII	(	int	byMIIIndex,
		int	ioaddr
	)			`[static]`

Definition at line 781 of file via-rhine.c.

References byMIIAD, byMIICR, currticks(), inb, inw, MIIDelay(), outb, and wMIIDATA.

Referenced by QueryAuto(), and rhine_probe1().

00782 {
00783     int ReturnMII;
00784     char byMIIAdrbak;
00785     char byMIICRbak;
00786     char byMIItemp;
00787     unsigned long ct;
00788 
00789     byMIIAdrbak = inb (byMIIAD);
00790     byMIICRbak = inb (byMIICR);
00791     outb (byMIICRbak & 0x7f, byMIICR);
00792     MIIDelay ();
00793 
00794     outb (byMIIIndex, byMIIAD);
00795     MIIDelay ();
00796 
00797     outb (inb (byMIICR) | 0x40, byMIICR);
00798 
00799     byMIItemp = inb (byMIICR);
00800     byMIItemp = byMIItemp & 0x40;
00801 
00802     ct = currticks();
00803     while (byMIItemp != 0 && ct + 2*1000 < currticks())
00804     {
00805         byMIItemp = inb (byMIICR);
00806         byMIItemp = byMIItemp & 0x40;
00807     }
00808     MIIDelay ();
00809 
00810     ReturnMII = inw (wMIIDATA);
00811 
00812     outb (byMIIAdrbak, byMIIAD);
00813     outb (byMIICRbak, byMIICR);
00814     MIIDelay ();
00815 
00816     return (ReturnMII);
00817 
00818 }

void WriteMII	(	char	byMIISetByte,
		char	byMIISetBit,
		char	byMIIOP,
		int	ioaddr
	)			`[static]`

Definition at line 821 of file via-rhine.c.

References byMIIAD, byMIICR, currticks(), inb, inw, MIIDelay(), outb, outw, and wMIIDATA.

Referenced by rhine_probe1().

00822 {
00823     int ReadMIItmp;
00824     int MIIMask;
00825     char byMIIAdrbak;
00826     char byMIICRbak;
00827     char byMIItemp;
00828     unsigned long ct;
00829 
00830 
00831     byMIIAdrbak = inb (byMIIAD);
00832 
00833     byMIICRbak = inb (byMIICR);
00834     outb (byMIICRbak & 0x7f, byMIICR);
00835     MIIDelay ();
00836     outb (byMIISetByte, byMIIAD);
00837     MIIDelay ();
00838 
00839     outb (inb (byMIICR) | 0x40, byMIICR);
00840 
00841     byMIItemp = inb (byMIICR);
00842     byMIItemp = byMIItemp & 0x40;
00843 
00844     ct = currticks();
00845     while (byMIItemp != 0 && ct + 2*1000 < currticks())
00846     {
00847         byMIItemp = inb (byMIICR);
00848         byMIItemp = byMIItemp & 0x40;
00849     }
00850     MIIDelay ();
00851 
00852     ReadMIItmp = inw (wMIIDATA);
00853     MIIMask = 0x0001;
00854     MIIMask = MIIMask << byMIISetBit;
00855 
00856 
00857     if (byMIIOP == 0)
00858     {
00859         MIIMask = ~MIIMask;
00860         ReadMIItmp = ReadMIItmp & MIIMask;
00861     }
00862     else
00863     {
00864         ReadMIItmp = ReadMIItmp | MIIMask;
00865 
00866     }
00867     outw (ReadMIItmp, wMIIDATA);
00868     MIIDelay ();
00869 
00870     outb (inb (byMIICR) | 0x20, byMIICR);
00871     byMIItemp = inb (byMIICR);
00872     byMIItemp = byMIItemp & 0x20;
00873 
00874     ct = currticks();
00875     while (byMIItemp != 0 && ct + 2*1000 < currticks())
00876     {
00877         byMIItemp = inb (byMIICR);
00878         byMIItemp = byMIItemp & 0x20;
00879     }
00880     MIIDelay ();
00881 
00882     outb (byMIIAdrbak & 0x7f, byMIIAD);
00883     outb (byMIICRbak, byMIICR);
00884     MIIDelay ();
00885 
00886 }

void MIIDelay ( void ) [static]

Definition at line 889 of file via-rhine.c.

References inb.

Referenced by ReadMII(), rhine_probe1(), rhine_reset(), and WriteMII().

00890 {
00891     int i;
00892     for (i = 0; i < 0x7fff; i++)
00893     {
00894         ( void ) inb (0x61);
00895         ( void ) inb (0x61);
00896         ( void ) inb (0x61);
00897         ( void ) inb (0x61);
00898     }
00899 }

static void rhine_init_ring ( struct nic * dev ) [static]

Definition at line 713 of file via-rhine.c.

References rhine_rx_desc::VTC_rx_ctrl_tag::bits, rhine_rx_desc::VTC_rx_status_tag::bits, rhine_tx_desc::buf_addr_1, rhine_rx_desc::buf_addr_1, rhine_tx_desc::buf_addr_2, rhine_rx_desc::buf_addr_2, rhine_private::cur_rx, rhine_private::cur_tx, rhine_private::dirty_rx, rhine_private::dirty_tx, rhine_tx_desc::VTC_tx_ctrl_tag::lw, rhine_tx_desc::VTC_tx_status_tag::lw, rhine_rx_desc::VTC_rx_status_tag::own_bit, nic::priv_data, rhine_rx_desc::VTC_rx_ctrl_tag::rx_buf_size, rhine_private::rx_buffs, rhine_rx_desc::rx_ctrl, rhine_private::rx_ring, RX_RING_SIZE, rhine_rx_desc::rx_status, tp, rhine_private::tx_buffs, rhine_tx_desc::tx_ctrl, rhine_private::tx_full, rhine_private::tx_ring, TX_RING_SIZE, rhine_tx_desc::tx_status, and virt_to_bus().

Referenced by rhine_reset().

00714 {
00715     struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
00716     int i;
00717 
00718     tp->tx_full = 0;
00719     tp->cur_rx = tp->cur_tx = 0;
00720     tp->dirty_rx = tp->dirty_tx = 0;
00721 
00722     for (i = 0; i < RX_RING_SIZE; i++)
00723     {
00724 
00725         tp->rx_ring[i].rx_status.bits.own_bit = 1;
00726         tp->rx_ring[i].rx_ctrl.bits.rx_buf_size = 1536;
00727 
00728         tp->rx_ring[i].buf_addr_1 = virt_to_bus (tp->rx_buffs[i]);
00729         tp->rx_ring[i].buf_addr_2 = virt_to_bus (&tp->rx_ring[i + 1]);
00730         /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->rx_ring[i].buf_addr_1,tp->rx_ring[i].buf_addr_2); */
00731     }
00732     /* Mark the last entry as wrapping the ring. */
00733     /* tp->rx_ring[i-1].rx_ctrl.bits.rx_buf_size =1518; */
00734     tp->rx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->rx_ring[0]);
00735     /*printf("[%d]buf1=%hX,buf2=%hX",i-1,tp->rx_ring[i-1].buf_addr_1,tp->rx_ring[i-1].buf_addr_2); */
00736 
00737     /* The Tx buffer descriptor is filled in as needed, but we
00738        do need to clear the ownership bit. */
00739 
00740     for (i = 0; i < TX_RING_SIZE; i++)
00741     {
00742 
00743         tp->tx_ring[i].tx_status.lw = 0;
00744         tp->tx_ring[i].tx_ctrl.lw = 0x00e08000;
00745         tp->tx_ring[i].buf_addr_1 = virt_to_bus (tp->tx_buffs[i]);
00746         tp->tx_ring[i].buf_addr_2 = virt_to_bus (&tp->tx_ring[i + 1]);
00747         /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i].buf_addr_1,tp->tx_ring[i].buf_addr_2); */
00748     }
00749 
00750     tp->tx_ring[i - 1].buf_addr_2 = virt_to_bus (&tp->tx_ring[0]);
00751     /* printf("[%d]buf1=%hX,buf2=%hX",i,tp->tx_ring[i-1].buf_addr_1,tp->tx_ring[i-1].buf_addr_2); */
00752 }

static void rhine_disable ( struct nic * nic ) [static]

Definition at line 1173 of file via-rhine.c.

References byCR0, byTCR, CR_STOP, rhine_private::ioaddr, ioaddr, outb, outw, printf(), nic::priv_data, rhine_reset(), and tp.

01173                                   {
01174 
01175     struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
01176     int ioaddr = tp->ioaddr;
01177 
01178     rhine_reset(nic);
01179 
01180     printf ("rhine disable\n");
01181     /* Switch to loopback mode to avoid hardware races. */
01182     outb(0x60 | 0x01, byTCR);
01183     /* Stop the chip's Tx and Rx processes. */
01184     outw(CR_STOP, byCR0);
01185 }

static void rhine_reset ( struct nic * nic ) [static]

Definition at line 1191 of file via-rhine.c.

References bus_to_virt(), byBCR0, byBCR1, byCFGD, byCR0, byCR1, byIMR0, byRCR, byTCR, CFGD_CFDX, CR1_SFRST, CR_DPOLL, CR_FDX, CR_RXON, CR_STRT, CR_TXON, dwCurrentRxDescAddr, dwCurrentTxDescAddr, inw, rhine_private::ioaddr, ioaddr, MIIDelay(), outb, outl, outw, nic::priv_data, QueryAuto(), rhine_init_ring(), rhine_private::rx_buffs, rhine_private::rx_ring, RX_RING_SIZE, set_rx_mode(), tp, rhine_private::tx_buffs, rhine_private::tx_ring, TX_RING_SIZE, and virt_to_bus().

Referenced by rhine_disable(), and rhine_probe().

01192 {
01193     struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
01194     int ioaddr = tp->ioaddr;
01195     int i, j;
01196     int FDXFlag, CRbak;
01197     void *rx_ring_tmp;
01198     void *tx_ring_tmp;
01199     void *rx_bufs_tmp;
01200     void *tx_bufs_tmp;
01201     unsigned long rx_ring_tmp1;
01202     unsigned long tx_ring_tmp1;
01203     unsigned long rx_bufs_tmp1;
01204     unsigned long tx_bufs_tmp1;
01205 
01206     /* printf ("rhine_reset\n"); */
01207     /* Soft reset the chip. */
01208     /*outb(CmdReset, ioaddr + ChipCmd); */
01209 
01210     tx_bufs_tmp = rhine_buffers.txbuf;
01211     tx_ring_tmp = rhine_buffers.txdesc;
01212     rx_bufs_tmp = rhine_buffers.rxbuf;
01213     rx_ring_tmp = rhine_buffers.rxdesc;
01214 
01215     /* tune RD TD 32 byte alignment */
01216     rx_ring_tmp1 = virt_to_bus ( rx_ring_tmp );
01217     j = (rx_ring_tmp1 + 32) & (~0x1f);
01218     /* printf ("txring[%d]", j); */
01219     tp->rx_ring = (struct rhine_rx_desc *) bus_to_virt (j);
01220 
01221     tx_ring_tmp1 = virt_to_bus ( tx_ring_tmp );
01222     j = (tx_ring_tmp1 + 32) & (~0x1f);
01223     tp->tx_ring = (struct rhine_tx_desc *) bus_to_virt (j);
01224     /* printf ("rxring[%X]", j); */
01225 
01226 
01227     tx_bufs_tmp1 = virt_to_bus ( tx_bufs_tmp );
01228     j = (int) (tx_bufs_tmp1 + 32) & (~0x1f);
01229     tx_bufs_tmp = bus_to_virt (j);
01230     /* printf ("txb[%X]", j); */
01231 
01232     rx_bufs_tmp1 = virt_to_bus ( rx_bufs_tmp );
01233     j = (int) (rx_bufs_tmp1 + 32) & (~0x1f);
01234     rx_bufs_tmp = bus_to_virt (j);
01235     /* printf ("rxb[%X][%X]", rx_bufs_tmp1, j); */
01236 
01237     for (i = 0; i < RX_RING_SIZE; i++)
01238     {
01239         tp->rx_buffs[i] = (char *) rx_bufs_tmp;
01240         /* printf("r[%X]",tp->rx_buffs[i]); */
01241         rx_bufs_tmp += 1536;
01242     }
01243 
01244     for (i = 0; i < TX_RING_SIZE; i++)
01245     {
01246         tp->tx_buffs[i] = (char *) tx_bufs_tmp;
01247         /* printf("t[%X]",tp->tx_buffs[i]);  */
01248         tx_bufs_tmp += 1536;
01249     }
01250 
01251     /* software reset */
01252     outb (CR1_SFRST, byCR1);
01253     MIIDelay ();
01254 
01255     /* printf ("init ring"); */
01256     rhine_init_ring (nic);
01257     /*write TD RD Descriptor to MAC */
01258     outl (virt_to_bus (tp->rx_ring), dwCurrentRxDescAddr);
01259     outl (virt_to_bus (tp->tx_ring), dwCurrentTxDescAddr);
01260 
01261     /* Setup Multicast */       
01262     set_rx_mode(nic);
01263 
01264     /* set TCR RCR threshold to store and forward*/
01265     outb (0x3e, byBCR0);
01266     outb (0x38, byBCR1);
01267     outb (0x2c, byRCR);
01268     outb (0x60, byTCR);
01269     /* Set Fulldupex */
01270     FDXFlag = QueryAuto (ioaddr);
01271     if (FDXFlag == 1)
01272     {
01273         outb (CFGD_CFDX, byCFGD);
01274         outw (CR_FDX, byCR0);
01275     }
01276 
01277     /* KICK NIC to WORK */
01278     CRbak = inw (byCR0);
01279     CRbak = CRbak & 0xFFFB;     /* not CR_STOP */
01280     outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0);
01281 
01282     /* disable all known interrupt */
01283     outw (0, byIMR0);
01284 }

static int rhine_poll	(	struct nic *	nic,
		int	retreive
	)			`[static]`

Definition at line 1289 of file via-rhine.c.

References rhine_rx_desc::VTC_rx_status_tag::bits, rhine_private::chip_id, rhine_private::cur_rx, DEFAULT_INTR, rhine_rx_desc::VTC_rx_status_tag::frame_length, inb, IntrRxDone, IntrStatus, IntrStatus2, IntrTxDescRace, inw, nic::ioaddr, IOSYNC, rhine_rx_desc::VTC_rx_status_tag::lw, memcpy, outb, outw, rhine_rx_desc::VTC_rx_status_tag::own_bit, nic::packet, nic::packetlen, printf(), nic::priv_data, RSR_ABNORMAL, rhine_private::rx_buffs, rhine_private::rx_ring, RX_RING_SIZE, rhine_rx_desc::rx_status, and tp.

01290 {
01291     struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
01292     int rxstatus, good = 0;;
01293 
01294     if (tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit == 0)
01295     {
01296         unsigned int intr_status;
01297         /* There is a packet ready */
01298         if(!retreive)
01299             return 1;
01300 
01301         intr_status = inw(nic->ioaddr + IntrStatus);
01302         /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
01303 #if 0
01304         if (tp->chip_id == 0x3065)
01305           intr_status |= inb(nic->ioaddr + IntrStatus2) << 16;
01306 #endif
01307         /* Acknowledge all of the current interrupt sources ASAP. */
01308         if (intr_status & IntrTxDescRace)
01309            outb(0x08, nic->ioaddr + IntrStatus2);
01310         outw(intr_status & 0xffff, nic->ioaddr + IntrStatus);
01311         IOSYNC;
01312 
01313         rxstatus = tp->rx_ring[tp->cur_rx].rx_status.lw;
01314         if ((rxstatus & 0x0300) != 0x0300)
01315         {
01316             printf("rhine_poll: bad status\n");
01317         }
01318         else if (rxstatus & (RSR_ABNORMAL))
01319         {
01320             printf ("rxerr[%X]\n", rxstatus);
01321         }
01322         else
01323             good = 1;
01324 
01325         if (good)
01326         {
01327             nic->packetlen = tp->rx_ring[tp->cur_rx].rx_status.bits.frame_length;
01328             memcpy (nic->packet, tp->rx_buffs[tp->cur_rx], nic->packetlen);
01329             /* printf ("Packet RXed\n"); */
01330         }
01331         tp->rx_ring[tp->cur_rx].rx_status.bits.own_bit = 1;
01332         tp->cur_rx++;
01333         tp->cur_rx = tp->cur_rx % RX_RING_SIZE;
01334     }
01335         /* Acknowledge all of the current interrupt sources ASAP. */
01336         outw(DEFAULT_INTR & ~IntrRxDone, nic->ioaddr + IntrStatus);
01337 
01338         IOSYNC;
01339 
01340     return good;
01341 }

static void rhine_transmit	(	struct nic *	nic,
		const char *	d,
		unsigned int	t,
		unsigned int	s,
		const char *	p
	)			`[static]`

Definition at line 1344 of file via-rhine.c.

References rhine_tx_desc::VTC_tx_status_tag::abt, rhine_tx_desc::VTC_tx_status_tag::bits, rhine_tx_desc::VTC_tx_ctrl_tag::bits, byCR0, byCR1, CR1_TDMD1, CR_TXON, rhine_private::cur_tx, currticks(), entry, ETH_ALEN, ETH_HLEN, ETH_ZLEN, htons, inb, rhine_private::ioaddr, ioaddr, memcpy, nic::node_addr, outb, rhine_tx_desc::VTC_tx_status_tag::own_bit, nic::priv_data, rhine_tx_desc::VTC_tx_status_tag::terr, tp, rhine_tx_desc::VTC_tx_ctrl_tag::tx_buf_size, rhine_private::tx_buffs, rhine_tx_desc::tx_ctrl, rhine_private::tx_ring, TX_RING_SIZE, and rhine_tx_desc::tx_status.

01346 {
01347     struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
01348     int ioaddr = tp->ioaddr;
01349     int entry;
01350     unsigned char CR1bak;
01351     unsigned char CR0bak;
01352     unsigned int nstype;
01353     unsigned long ct;
01354 
01355 
01356     /*printf ("rhine_transmit\n"); */
01357     /* setup ethernet header */
01358 
01359 
01360     /* Calculate the next Tx descriptor entry. */
01361     entry = tp->cur_tx % TX_RING_SIZE;
01362 
01363     memcpy (tp->tx_buffs[entry], d, ETH_ALEN);  /* dst */
01364     memcpy (tp->tx_buffs[entry] + ETH_ALEN, nic->node_addr, ETH_ALEN);  /* src */
01365     
01366     nstype=htons(t);
01367     memcpy(tp->tx_buffs[entry] + 2 * ETH_ALEN, (char*)&nstype, 2);
01368 
01369     memcpy (tp->tx_buffs[entry] + ETH_HLEN, p, s);
01370     s += ETH_HLEN;
01371     while (s < ETH_ZLEN)
01372         *((char *) tp->tx_buffs[entry] + (s++)) = 0;
01373 
01374     tp->tx_ring[entry].tx_ctrl.bits.tx_buf_size = s;
01375 
01376     tp->tx_ring[entry].tx_status.bits.own_bit = 1;
01377 
01378 
01379     CR1bak = inb (byCR1);
01380 
01381     CR1bak = CR1bak | CR1_TDMD1;
01382     /*printf("tdsw=[%X]",tp->tx_ring[entry].tx_status.lw); */
01383     /*printf("tdcw=[%X]",tp->tx_ring[entry].tx_ctrl.lw); */
01384     /*printf("tdbuf1=[%X]",tp->tx_ring[entry].buf_addr_1); */
01385     /*printf("tdbuf2=[%X]",tp->tx_ring[entry].buf_addr_2); */
01386     /*printf("td1=[%X]",inl(dwCurrentTDSE0)); */
01387     /*printf("td2=[%X]",inl(dwCurrentTDSE1)); */
01388     /*printf("td3=[%X]",inl(dwCurrentTDSE2)); */
01389     /*printf("td4=[%X]",inl(dwCurrentTDSE3)); */
01390 
01391     outb (CR1bak, byCR1);
01392     do
01393     {
01394         ct = currticks();
01395         /* Wait until transmit is finished or timeout*/
01396         while((tp->tx_ring[entry].tx_status.bits.own_bit !=0) &&
01397                 ct + 10*1000 < currticks())
01398         ;
01399 
01400         if(tp->tx_ring[entry].tx_status.bits.terr == 0)
01401             break;
01402 
01403         if(tp->tx_ring[entry].tx_status.bits.abt == 1)
01404         {
01405             // turn on TX
01406             CR0bak = inb(byCR0);
01407             CR0bak = CR0bak|CR_TXON;
01408             outb(CR0bak,byCR0);
01409         }
01410     }while(0);
01411     tp->cur_tx++;
01412 
01413     /*outw(IMRShadow,byIMR0); */
01414     /*dev_kfree_skb(tp->tx_skbuff[entry], FREE_WRITE); */
01415     /*tp->tx_skbuff[entry] = 0; */
01416 }

static void reload_eeprom ( int ioaddr ) [static]

Definition at line 702 of file via-rhine.c.

References byEECSR, inb, and outb.

Referenced by rhine_probe1().

00703 {
00704         int i;
00705         outb(0x20, byEECSR);
00706         /* Typically 2 cycles to reload. */
00707         for (i = 0; i < 150; i++)
00708                 if (! (inb(byEECSR) & 0x20))
00709                         break;
00710 }

void rhine_irq	(	struct nic *	nic,
		irq_action_t	action
	)

Definition at line 934 of file via-rhine.c.

References rhine_private::chip_revision, DEFAULT_INTR, DISABLE, ENABLE, FORCE, inb, IntrEnable, IntrStatus, IntrStatus2, inw, nic::ioaddr, outw, nic::priv_data, and tp.

00934                                                         {
00935     struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
00936     /* Enable interrupts by setting the interrupt mask. */
00937     unsigned int intr_status;
00938 
00939     switch ( action ) {
00940         case DISABLE :
00941         case ENABLE :
00942             intr_status = inw(nic->ioaddr + IntrStatus);
00943             /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
00944 
00945             /* added comment by guard */
00946             /* For supporting VT6107, please use revision id to recognize different chips in driver */
00947             // if (tp->chip_id == 0x3065)
00948             if( tp->chip_revision < 0x80 && tp->chip_revision >=0x40 )
00949                 intr_status |= inb(nic->ioaddr + IntrStatus2) << 16;
00950                 intr_status = (intr_status & ~DEFAULT_INTR);
00951                 if ( action == ENABLE ) 
00952                     intr_status = intr_status | DEFAULT_INTR;
00953                     outw(intr_status, nic->ioaddr + IntrEnable);
00954                 break;
00955         case FORCE :
00956             outw(0x0010, nic->ioaddr + 0x84);
00957            break;
00958         }
00959 }

static int rhine_probe	(	struct nic *	nic,
		struct pci_device *	pci
	)			`[static]`

Definition at line 964 of file via-rhine.c.

References adjust_pci_device(), pci_device::device, rhine_private::ioaddr, nic::ioaddr, pci_device::ioaddr, pci_device::irq, nic::irqno, nic::nic_op, nic::priv_data, rhine_operations, rhine_probe1(), rhine_reset(), and tp.

00964                                                         {
00965 
00966     struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
00967 
00968     if (!pci->ioaddr)
00969         return 0;
00970 
00971     rhine_probe1 (nic, pci, pci->ioaddr, pci->device, -1);
00972 
00973     adjust_pci_device ( pci );
00974 
00975     rhine_reset (nic);
00976 
00977     nic->nic_op = &rhine_operations;
00978 
00979     nic->irqno    = pci->irq;
00980     nic->ioaddr   = tp->ioaddr;
00981 
00982     return 1;
00983 }

static void set_rx_mode ( struct nic *nic __unused ) [static]

Definition at line 985 of file via-rhine.c.

References byMAR0, byMAR4, byRCR, rhine_private::ioaddr, ioaddr, outb, outl, and tp.

00985                                                   {
00986         struct rhine_private *tp = (struct rhine_private *) nic->priv_data;
00987         unsigned char rx_mode;
00988         int ioaddr = tp->ioaddr;
00989 
00990         /* ! IFF_PROMISC */
00991         outl(0xffffffff, byMAR0);
00992         outl(0xffffffff, byMAR4);
00993         rx_mode = 0x0C;
00994 
00995         outb(0x60 /* thresh */ | rx_mode, byRCR );
00996 }

PCI_DRIVER	(	rhine_driver	,
		rhine_nics	,
		PCI_NO_CLASS
	)

DRIVER	(	"VIA 86C100"	,
		nic_driver	,
		pci_driver	,
		rhine_driver	,
		rhine_probe	,
		rhine_disable
	)

Variable Documentation

const char* version = "rhine.c v1.0.2 2004-10-29\n" [static]

Definition at line 21 of file via-rhine.c.

Referenced by hermon_probe(), rhine_probe1(), tls_new_server_hello(), and tls_send_client_hello().

char txbuf[TX_RING_SIZE *PKT_BUF_SZ+32]

Definition at line 550 of file via-rhine.c.

char rxbuf[RX_RING_SIZE *PKT_BUF_SZ+32]

Definition at line 551 of file via-rhine.c.

char txdesc[TX_RING_SIZE *sizeof(struct rhine_tx_desc)+32]

Definition at line 552 of file via-rhine.c.

char rxdesc[RX_RING_SIZE *sizeof(struct rhine_rx_desc)+32]

Definition at line 553 of file via-rhine.c.

struct { ... } __shared

int rhine_debug = 1 [static]

Definition at line 564 of file via-rhine.c.

Referenced by rhine_probe1().

struct rhine_private rhine [static]

Referenced by rhine_probe1().

static struct nic_operations rhine_operations [static, read]

Initial value:

 {
        .connect        = dummy_connect,
        .poll           = rhine_poll,
        .transmit       = rhine_transmit,
        .irq            = rhine_irq,

}

Definition at line 961 of file via-rhine.c.

Referenced by rhine_probe().

struct pci_device_id rhine_nics[] [static]

Initial value:

 {
PCI_ROM(0x1106, 0x3065, "dlink-530tx",     "VIA 6102", 0),
PCI_ROM(0x1106, 0x3106, "via-rhine-6105",  "VIA 6105", 0),
PCI_ROM(0x1106, 0x3043, "dlink-530tx-old", "VIA 3043", 0),              
PCI_ROM(0x1106, 0x3053, "via6105m",        "VIA 6105M", 0),
PCI_ROM(0x1106, 0x6100, "via-rhine-old",   "VIA 86C100A", 0),   
}

Definition at line 1426 of file via-rhine.c.


Data Structures
struct	rhine_tx_desc
union	rhine_tx_desc::VTC_tx_status_tag
union	rhine_tx_desc::VTC_tx_ctrl_tag
struct	rhine_rx_desc
union	rhine_rx_desc::VTC_rx_status_tag
union	rhine_rx_desc::VTC_rx_ctrl_tag
struct	rhine_private
Defines
#define	W_MAX_TIMEOUT 0x0FFFU
#define	RX_BUF_LEN_IDX 3
#define	RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
#define	TX_BUF_SIZE 1536
#define	RX_BUF_SIZE 1536
#define	TX_FIFO_THRESH 256
#define	RX_FIFO_THRESH 4
#define	RX_DMA_BURST 4
#define	TX_DMA_BURST 4
#define	TX_TIMEOUT ((2000*HZ)/1000)
#define	byPAR0 ioaddr
#define	byRCR ioaddr + 6
#define	byTCR ioaddr + 7
#define	byCR0 ioaddr + 8
#define	byCR1 ioaddr + 9
#define	byISR0 ioaddr + 0x0c
#define	byISR1 ioaddr + 0x0d
#define	byIMR0 ioaddr + 0x0e
#define	byIMR1 ioaddr + 0x0f
#define	byMAR0 ioaddr + 0x10
#define	byMAR1 ioaddr + 0x11
#define	byMAR2 ioaddr + 0x12
#define	byMAR3 ioaddr + 0x13
#define	byMAR4 ioaddr + 0x14
#define	byMAR5 ioaddr + 0x15
#define	byMAR6 ioaddr + 0x16
#define	byMAR7 ioaddr + 0x17
#define	dwCurrentRxDescAddr ioaddr + 0x18
#define	dwCurrentTxDescAddr ioaddr + 0x1c
#define	dwCurrentRDSE0 ioaddr + 0x20
#define	dwCurrentRDSE1 ioaddr + 0x24
#define	dwCurrentRDSE2 ioaddr + 0x28
#define	dwCurrentRDSE3 ioaddr + 0x2c
#define	dwNextRDSE0 ioaddr + 0x30
#define	dwNextRDSE1 ioaddr + 0x34
#define	dwNextRDSE2 ioaddr + 0x38
#define	dwNextRDSE3 ioaddr + 0x3c
#define	dwCurrentTDSE0 ioaddr + 0x40
#define	dwCurrentTDSE1 ioaddr + 0x44
#define	dwCurrentTDSE2 ioaddr + 0x48
#define	dwCurrentTDSE3 ioaddr + 0x4c
#define	dwNextTDSE0 ioaddr + 0x50
#define	dwNextTDSE1 ioaddr + 0x54
#define	dwNextTDSE2 ioaddr + 0x58
#define	dwNextTDSE3 ioaddr + 0x5c
#define	dwCurrRxDMAPtr ioaddr + 0x60
#define	dwCurrTxDMAPtr ioaddr + 0x64
#define	byMPHY ioaddr + 0x6c
#define	byMIISR ioaddr + 0x6d
#define	byBCR0 ioaddr + 0x6e
#define	byBCR1 ioaddr + 0x6f
#define	byMIICR ioaddr + 0x70
#define	byMIIAD ioaddr + 0x71
#define	wMIIDATA ioaddr + 0x72
#define	byEECSR ioaddr + 0x74
#define	byTEST ioaddr + 0x75
#define	byGPIO ioaddr + 0x76
#define	byCFGA ioaddr + 0x78
#define	byCFGB ioaddr + 0x79
#define	byCFGC ioaddr + 0x7a
#define	byCFGD ioaddr + 0x7b
#define	wTallyCntMPA ioaddr + 0x7c
#define	wTallyCntCRC ioaddr + 0x7d
#define	bySTICKHW ioaddr + 0x83
#define	byWOLcrClr ioaddr + 0xA4
#define	byWOLcgClr ioaddr + 0xA7
#define	byPwrcsrClr ioaddr + 0xAC
#define	RCR_RRFT2 0x80
#define	RCR_RRFT1 0x40
#define	RCR_RRFT0 0x20
#define	RCR_PROM 0x10
#define	RCR_AB 0x08
#define	RCR_AM 0x04
#define	RCR_AR 0x02
#define	RCR_SEP 0x01
#define	TCR_RTSF 0x80
#define	TCR_RTFT1 0x40
#define	TCR_RTFT0 0x20
#define	TCR_OFSET 0x08
#define	TCR_LB1 0x04
#define	TCR_LB0 0x02
#define	CR0_RDMD 0x40
#define	CR0_TDMD 0x20
#define	CR0_TXON 0x10
#define	CR0_RXON 0x08
#define	CR0_STOP 0x04
#define	CR0_STRT 0x02
#define	CR0_INIT 0x01
#define	CR1_SFRST 0x80
#define	CR1_RDMD1 0x40
#define	CR1_TDMD1 0x20
#define	CR1_KEYPAG 0x10
#define	CR1_DPOLL 0x08
#define	CR1_FDX 0x04
#define	CR1_ETEN 0x02
#define	CR1_EREN 0x01
#define	CR_RDMD 0x0040
#define	CR_TDMD 0x0020
#define	CR_TXON 0x0010
#define	CR_RXON 0x0008
#define	CR_STOP 0x0004
#define	CR_STRT 0x0002
#define	CR_INIT 0x0001
#define	CR_SFRST 0x8000
#define	CR_RDMD1 0x4000
#define	CR_TDMD1 0x2000
#define	CR_KEYPAG 0x1000
#define	CR_DPOLL 0x0800
#define	CR_FDX 0x0400
#define	CR_ETEN 0x0200
#define	CR_EREN 0x0100
#define	IMR0_CNTM 0x80
#define	IMR0_BEM 0x40
#define	IMR0_RUM 0x20
#define	IMR0_TUM 0x10
#define	IMR0_TXEM 0x08
#define	IMR0_RXEM 0x04
#define	IMR0_PTXM 0x02
#define	IMR0_PRXM 0x01
#define	IMRShadow 0x5AFF
#define	IMR1_INITM 0x80
#define	IMR1_SRCM 0x40
#define	IMR1_NBFM 0x10
#define	IMR1_PRAIM 0x08
#define	IMR1_RES0M 0x04
#define	IMR1_ETM 0x02
#define	IMR1_ERM 0x01
#define	ISR_INITI 0x8000
#define	ISR_SRCI 0x4000
#define	ISR_ABTI 0x2000
#define	ISR_NORBF 0x1000
#define	ISR_PKTRA 0x0800
#define	ISR_RES0 0x0400
#define	ISR_ETI 0x0200
#define	ISR_ERI 0x0100
#define	ISR_CNT 0x0080
#define	ISR_BE 0x0040
#define	ISR_RU 0x0020
#define	ISR_TU 0x0010
#define	ISR_TXE 0x0008
#define	ISR_RXE 0x0004
#define	ISR_PTX 0x0002
#define	ISR_PRX 0x0001
#define	ISR0_CNT 0x80
#define	ISR0_BE 0x40
#define	ISR0_RU 0x20
#define	ISR0_TU 0x10
#define	ISR0_TXE 0x08
#define	ISR0_RXE 0x04
#define	ISR0_PTX 0x02
#define	ISR0_PRX 0x01
#define	ISR1_INITI 0x80
#define	ISR1_SRCI 0x40
#define	ISR1_NORBF 0x10
#define	ISR1_PKTRA 0x08
#define	ISR1_ETI 0x02
#define	ISR1_ERI 0x01
#define	ISR_ABNORMAL ISR_BE+ISR_RU+ISR_TU+ISR_CNT+ISR_NORBF+ISR_PKTRA
#define	MIISR_MIIERR 0x08
#define	MIISR_MRERR 0x04
#define	MIISR_LNKFL 0x02
#define	MIISR_SPEED 0x01
#define	MIICR_MAUTO 0x80
#define	MIICR_RCMD 0x40
#define	MIICR_WCMD 0x20
#define	MIICR_MDPM 0x10
#define	MIICR_MOUT 0x08
#define	MIICR_MDO 0x04
#define	MIICR_MDI 0x02
#define	MIICR_MDC 0x01
#define	EECSR_EEPR 0x80
#define	EECSR_EMBP 0x40
#define	EECSR_AUTOLD 0x20
#define	EECSR_DPM 0x10
#define	EECSR_CS 0x08
#define	EECSR_SK 0x04
#define	EECSR_DI 0x02
#define	EECSR_DO 0x01
#define	BCR0_CRFT2 0x20
#define	BCR0_CRFT1 0x10
#define	BCR0_CRFT0 0x08
#define	BCR0_DMAL2 0x04
#define	BCR0_DMAL1 0x02
#define	BCR0_DMAL0 0x01
#define	BCR1_CTSF 0x20
#define	BCR1_CTFT1 0x10
#define	BCR1_CTFT0 0x08
#define	BCR1_POT2 0x04
#define	BCR1_POT1 0x02
#define	BCR1_POT0 0x01
#define	CFGA_EELOAD 0x80
#define	CFGA_JUMPER 0x40
#define	CFGA_MTGPIO 0x08
#define	CFGA_T10EN 0x02
#define	CFGA_AUTO 0x01
#define	CFGB_PD 0x80
#define	CFGB_POLEN 0x02
#define	CFGB_LNKEN 0x01
#define	CFGC_M10TIO 0x80
#define	CFGC_M10POL 0x40
#define	CFGC_PHY1 0x20
#define	CFGC_PHY0 0x10
#define	CFGC_BTSEL 0x08
#define	CFGC_BPS2 0x04
#define	CFGC_BPS1 0x02
#define	CFGC_BPS0 0x01
#define	CFGD_GPIOEN 0x80
#define	CFGD_DIAG 0x40
#define	CFGD_MAGIC 0x10
#define	CFGD_RANDOM 0x08
#define	CFGD_CFDX 0x04
#define	CFGD_CEREN 0x02
#define	CFGD_CETEN 0x01
#define	RSR_RERR 0x00000001
#define	RSR_CRC 0x00000002
#define	RSR_FAE 0x00000004
#define	RSR_FOV 0x00000008
#define	RSR_LONG 0x00000010
#define	RSR_RUNT 0x00000020
#define	RSR_SERR 0x00000040
#define	RSR_BUFF 0x00000080
#define	RSR_EDP 0x00000100
#define	RSR_STP 0x00000200
#define	RSR_CHN 0x00000400
#define	RSR_PHY 0x00000800
#define	RSR_BAR 0x00001000
#define	RSR_MAR 0x00002000
#define	RSR_RXOK 0x00008000
#define	RSR_ABNORMAL RSR_RERR+RSR_LONG+RSR_RUNT
#define	TSR_NCR0 0x00000001
#define	TSR_NCR1 0x00000002
#define	TSR_NCR2 0x00000004
#define	TSR_NCR3 0x00000008
#define	TSR_COLS 0x00000010
#define	TSR_CDH 0x00000080
#define	TSR_ABT 0x00000100
#define	TSR_OWC 0x00000200
#define	TSR_CRS 0x00000400
#define	TSR_UDF 0x00000800
#define	TSR_TBUFF 0x00001000
#define	TSR_SERR 0x00002000
#define	TSR_JAB 0x00004000
#define	TSR_TERR 0x00008000
#define	TSR_ABNORMAL TSR_TERR+TSR_OWC+TSR_ABT+TSR_JAB+TSR_CRS
#define	TSR_OWN_BIT 0x80000000
#define	CB_DELAY_LOOP_WAIT 10
#define	W_IMR_MASK_VALUE 0x1BFF
#define	PKT_TYPE_DIRECTED 0x0001
#define	PKT_TYPE_MULTICAST 0x0002
#define	PKT_TYPE_ALL_MULTICAST 0x0004
#define	PKT_TYPE_BROADCAST 0x0008
#define	PKT_TYPE_PROMISCUOUS 0x0020
#define	PKT_TYPE_LONG 0x2000
#define	PKT_TYPE_RUNT 0x4000
#define	PKT_TYPE_ERROR 0x8000
#define	NIC_LB_NONE 0x00
#define	NIC_LB_INTERNAL 0x01
#define	NIC_LB_PHY 0x02
#define	TX_RING_SIZE 2
#define	RX_RING_SIZE 2
#define	PKT_BUF_SZ 1536
#define	PCI_REG_MODE3 0x53
#define	MODE3_MIION 0x04
#define	rhine_TOTAL_SIZE 0x80
#define	NUM_TX_DESC 2
#define	DEFAULT_INTR
#define	IOSYNC do { inb(nic->ioaddr + StationAddr); } while (0)
Enumerations
enum	rhine_revs { VT86C100A = 0x00, VTunknown0 = 0x20, VT6102 = 0x40, VT8231 = 0x50, VT8233 = 0x60, VT8235 = 0x74, VT8237 = 0x78, VTunknown1 = 0x7C, VT6105 = 0x80, VT6105_B0 = 0x83, VT6105L = 0x8A, VT6107 = 0x8C, VTunknown2 = 0x8E, VT6105M = 0x90 }
enum	register_offsets { ChipCmd = 0x00, ChipConfig = 0x04, EECtrl = 0x08, PCIBusCfg = 0x0C, IntrStatus = 0x10, IntrMask = 0x14, IntrEnable = 0x18, TxRingPtr = 0x20, TxConfig = 0x24, RxRingPtr = 0x30, RxConfig = 0x34, ClkRun = 0x3C, WOLCmd = 0x40, PauseCmd = 0x44, RxFilterAddr = 0x48, RxFilterData = 0x4C, BootRomAddr = 0x50, BootRomData = 0x54, SiliconRev = 0x58, StatsCtrl = 0x5C, StatsData = 0x60, RxPktErrs = 0x60, RxMissed = 0x68, RxCRCErrs = 0x64, PCIPM = 0x44, PhyStatus = 0xC0, MIntrCtrl = 0xC4, MIntrStatus = 0xC8, PGSEL = 0xCC, PMDCSR = 0xE4, TSTDAT = 0xFC, DSPCFG = 0xF4, SDCFG = 0x8C, BasicControl = 0x80, BasicStatus = 0x84, StationAddr = 0x00, RxConfig = 0x06, TxConfig = 0x07, ChipCmd = 0x08, IntrStatus = 0x0C, IntrEnable = 0x0E, MulticastFilter0 = 0x10, MulticastFilter1 = 0x14, RxRingPtr = 0x18, TxRingPtr = 0x1C, GFIFOTest = 0x54, MIIPhyAddr = 0x6C, MIIStatus = 0x6D, PCIBusConfig = 0x6E, MIICmd = 0x70, MIIRegAddr = 0x71, MIIData = 0x72, MACRegEEcsr = 0x74, ConfigA = 0x78, ConfigB = 0x79, ConfigC = 0x7A, ConfigD = 0x7B, RxMissed = 0x7C, RxCRCErrs = 0x7E, MiscCmd = 0x81, StickyHW = 0x83, IntrStatus2 = 0x84, WOLcrClr = 0xA4, WOLcgClr = 0xA7, PwrcsrClr = 0xAC }
enum	intr_status_bits { RFCON = 0x00020000, RFCOFF = 0x00010000, LSCStatus = 0x00008000, ANCStatus = 0x00004000, FBE = 0x00002000, FBEMask = 0x00001800, ParityErr = 0x00000000, TargetErr = 0x00001000, MasterErr = 0x00000800, TUNF = 0x00000400, ROVF = 0x00000200, ETI = 0x00000100, ERI = 0x00000080, CNTOVF = 0x00000040, RBU = 0x00000020, TBU = 0x00000010, TI = 0x00000008, RI = 0x00000004, RxErr = 0x00000002, IntrSummary = 0x0001, IntrPCIErr = 0x0002, IntrMACCtrl = 0x0008, IntrTxDone = 0x0004, IntrRxDone = 0x0010, IntrRxStart = 0x0020, IntrDrvRqst = 0x0040, StatsMax = 0x0080, LinkChange = 0x0100, IntrTxDMADone = 0x0200, IntrRxDMADone = 0x0400, IntrRxDone = 0x0001, IntrRxErr = 0x0004, IntrRxEmpty = 0x0020, IntrTxDone = 0x0002, IntrTxError = 0x0008, IntrTxUnderrun = 0x0210, IntrPCIErr = 0x0040, IntrStatsMax = 0x0080, IntrRxEarly = 0x0100, IntrRxOverflow = 0x0400, IntrRxDropped = 0x0800, IntrRxNoBuf = 0x1000, IntrTxAborted = 0x2000, IntrLinkChange = 0x4000, IntrRxWakeUp = 0x8000, IntrNormalSummary = 0x0003, IntrAbnormalSummary = 0xC260, IntrTxDescRace = 0x080000, IntrTxErrSummary = 0x082218, NormalIntr = 0x10000, AbnormalIntr = 0x8000, IntrPCIErr = 0x2000, TimerInt = 0x800, IntrRxDied = 0x100, RxNoBuf = 0x80, IntrRxDone = 0x40, TxFIFOUnderflow = 0x20, RxErrIntr = 0x10, TxIdle = 0x04, IntrTxStopped = 0x02, IntrTxDone = 0x01 }
Functions
static void	rhine_probe1 (struct nic nic, struct pci_device pci, int ioaddr, int chip_id, int options)
static int	QueryAuto (int)
static int	ReadMII (int byMIIIndex, int)
static void	WriteMII (char, char, char, int)
static void	MIIDelay (void)
static void	rhine_init_ring (struct nic *dev)
static void	rhine_disable (struct nic *nic)
static void	rhine_reset (struct nic *nic)
static int	rhine_poll (struct nic *nic, int retreive)
static void	rhine_transmit (struct nic nic, const char d, unsigned int t, unsigned int s, const char *p)
static void	reload_eeprom (int ioaddr)
void	rhine_irq (struct nic *nic, irq_action_t action)
static int	rhine_probe (struct nic nic, struct pci_device pci)
static void	set_rx_mode (struct nic *nic __unused)
	PCI_DRIVER (rhine_driver, rhine_nics, PCI_NO_CLASS)
	DRIVER ("VIA 86C100", nic_driver, pci_driver, rhine_driver, rhine_probe, rhine_disable)
Variables
static const char *	version = "rhine.c v1.0.2 2004-10-29\n"
struct {
char txbuf [TX_RING_SIZE *PKT_BUF_SZ+32]
char rxbuf [RX_RING_SIZE *PKT_BUF_SZ+32]
char txdesc [TX_RING_SIZE *sizeof(struct rhine_tx_desc)+32]
char rxdesc [RX_RING_SIZE *sizeof(struct rhine_rx_desc)+32]
}	__shared
static int	rhine_debug = 1
static struct rhine_private	rhine
static struct nic_operations	rhine_operations
static struct pci_device_id	rhine_nics []