tlan.c File Reference

#include "etherboot.h"
#include "nic.h"
#include <gpxe/pci.h>
#include <gpxe/ethernet.h>
#include <mii.h>
#include "tlan.h"

Go to the source code of this file.

Data Structures

struct  pci_id_info
struct  pci_id_info::match_info
struct  TLanList
struct  tlan_private

Defines

#define drv_version   "v1.4"
#define drv_date   "01-17-2004"
#define HZ   100
#define TX_TIME_OUT   (6*HZ)
#define virt_to_le32desc(addr)   cpu_to_le32(virt_to_bus(addr))
#define le32desc_to_virt(addr)   bus_to_virt(le32_to_cpu(addr))
#define tx_ring   tlan_buffers.tx_ring
#define txb   tlan_buffers.txb
#define rx_ring   tlan_buffers.rx_ring
#define rxb   tlan_buffers.rxb
#define board_found   1
#define valid_link   0

Typedefs

typedef u8 TLanBuffer [TLAN_MAX_FRAME_SIZE]

Enumerations

enum  tlan_nics {
  NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3,
  NETFLEX3B, NETEL100PI = 5, NETEL100D = 6, NETEL100I = 7,
  OC2183 = 8, OC2325 = 9, OC2326, NETELLIGENT_10_100_WS_5100 = 11,
  NETELLIGENT_10_T2 = 12
}

Functions

 FILE_LICENCE (GPL2_OR_LATER)
static void TLan_ResetLists (struct nic *nic __unused)
static void TLan_ResetAdapter (struct nic *nic __unused)
static void TLan_FinishReset (struct nic *nic __unused)
static void TLan_EeSendStart (u16)
static int TLan_EeSendByte (u16, u8, int)
static void TLan_EeReceiveByte (u16, u8 *, int)
static int TLan_EeReadByte (u16 io_base, u8, u8 *)
static void TLan_PhyDetect (struct nic *nic)
static void TLan_PhyPowerDown (struct nic *nic)
static void TLan_PhyPowerUp (struct nic *nic)
static void TLan_SetMac (struct nic *nic __unused, int areg, unsigned char *mac)
static void TLan_PhyReset (struct nic *nic)
static void TLan_PhyStartLink (struct nic *nic)
static void TLan_PhyFinishAutoNeg (struct nic *nic)
static void refill_rx (struct nic *nic __unused)
static int TLan_MiiReadReg (struct nic *nic __unused, u16, u16, u16 *)
static void TLan_MiiSendData (u16, u32, unsigned)
static void TLan_MiiSync (u16)
static void TLan_MiiWriteReg (struct nic *nic __unused, u16, u16, u16)
void TLan_FinishReset (struct nic *nic)
static int tlan_poll (struct nic *nic, int retrieve)
static void tlan_transmit (struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p)
static void tlan_disable (struct nic *nic __unused)
static void tlan_irq (struct nic *nic __unused, irq_action_t action __unused)
static void TLan_SetMulticastList (struct nic *nic)
static int tlan_probe (struct nic *nic, struct pci_device *pci)
 PCI_DRIVER (tlan_driver, tlan_nics, PCI_NO_CLASS)
 DRIVER ("TLAN/PCI", nic_driver, pci_driver, tlan_driver, tlan_probe, tlan_disable)

Variables

static const char * media []
static struct pci_id_info tlan_pci_tbl []
struct {
   struct TLanList   tx_ring [TLAN_NUM_TX_LISTS]
   unsigned char   txb [TLAN_MAX_FRAME_SIZE *TLAN_NUM_TX_LISTS]
   struct TLanList   rx_ring [TLAN_NUM_RX_LISTS]
   unsigned char   rxb [TLAN_MAX_FRAME_SIZE *TLAN_NUM_RX_LISTS]
} __shared
static int chip_idx
static struct tlan_private TLanPrivateInfo
static struct tlan_private * priv
static u32 BASE
static struct nic_operations tlan_operations
static struct pci_device_id tlan_nics []

Define Documentation

#define drv_version   "v1.4"

Definition at line 50 of file tlan.c.

#define drv_date   "01-17-2004"

Definition at line 51 of file tlan.c.

#define HZ   100

Definition at line 54 of file tlan.c.

#define TX_TIME_OUT   (6*HZ)

Definition at line 55 of file tlan.c.

#define virt_to_le32desc ( addr   )     cpu_to_le32(virt_to_bus(addr))

Definition at line 58 of file tlan.c.

#define le32desc_to_virt ( addr   )     bus_to_virt(le32_to_cpu(addr))

Definition at line 59 of file tlan.c.

#define tx_ring   tlan_buffers.tx_ring

Definition at line 187 of file tlan.c.

#define txb   tlan_buffers.txb

Definition at line 188 of file tlan.c.

#define rx_ring   tlan_buffers.rx_ring

Definition at line 189 of file tlan.c.

#define rxb   tlan_buffers.rxb

Definition at line 190 of file tlan.c.

#define board_found   1

Definition at line 777 of file tlan.c.

#define valid_link   0

Definition at line 778 of file tlan.c.

Typedef Documentation

typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE]

Definition at line 192 of file tlan.c.

Enumeration Type Documentation

enum tlan_nics

Enumerator:
NETEL10 
NETEL100 
NETFLEX3I 
THUNDER 
NETFLEX3B 
NETEL100PI 
NETEL100D 
NETEL100I 
OC2183 
OC2325 
OC2326 
NETELLIGENT_10_100_WS_5100 
NETELLIGENT_10_T2 

Definition at line 100 of file tlan.c.

00100                {
00101         NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
00102             4, NETEL100PI = 5,
00103         NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
00104             10, NETELLIGENT_10_100_WS_5100 = 11,
00105         NETELLIGENT_10_T2 = 12
00106 };

Function Documentation

FILE_LICENCE ( GPL2_OR_LATER   ) 

static void TLan_ResetLists ( struct nic *nic  __unused  )  [static]

Definition at line 241 of file tlan.c.

References TLanList::address, TLanList::buffer, TLanList::count, TLanList::cStat, tlan_private::cur_rx, tlan_private::dirty_rx, tlan_private::rx_buf_sz, rx_ring, rxb, TLAN_CSTAT_READY, TLAN_CSTAT_UNUSED, TLAN_LAST_BUFFER, TLAN_MAX_FRAME_SIZE, TLAN_NUM_RX_LISTS, TLAN_NUM_TX_LISTS, tx_ring, txb, tlan_private::txHead, tlan_private::txTail, virt_to_bus(), and virt_to_le32desc.

Referenced by tlan_probe().

00242 {
00243 
00244         int i;
00245         struct TLanList *list;
00246         priv->txHead = 0;
00247         priv->txTail = 0;
00248 
00249         for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
00250                 list = &tx_ring[i];
00251                 list->cStat = TLAN_CSTAT_UNUSED;
00252                 list->buffer[0].address = virt_to_bus(txb + 
00253                                 (i * TLAN_MAX_FRAME_SIZE)); 
00254                 list->buffer[2].count = 0;
00255                 list->buffer[2].address = 0;
00256                 list->buffer[9].address = 0;
00257         }
00258 
00259         priv->cur_rx = 0;
00260         priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
00261 //      priv->rx_head_desc = &rx_ring[0];
00262 
00263         /* Initialize all the Rx descriptors */
00264         for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
00265                 rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
00266                 rx_ring[i].cStat = TLAN_CSTAT_READY;
00267                 rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
00268                 rx_ring[i].buffer[0].count =
00269                     TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
00270                 rx_ring[i].buffer[0].address =
00271                     virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
00272                 rx_ring[i].buffer[1].count = 0;
00273                 rx_ring[i].buffer[1].address = 0;
00274         }
00275 
00276         /* Mark the last entry as wrapping the ring */
00277         rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
00278         priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
00279 
00280 } /* TLan_ResetLists */

void TLan_ResetAdapter ( struct nic *nic  __unused  )  [static]

Definition at line 299 of file tlan.c.

References tlan_private::aui, BASE, chip_idx, tlan_private::duplex, FALSE, inl, outl, outw, tlan_private::phyNum, tlan_private::phyOnline, TLAN_ACOMMIT, TLAN_ADAPTER_BIT_RATE_PHY, TLAN_ADAPTER_UNMANAGED_PHY, TLAN_AREG_0, TLAN_DIO_ADR, TLAN_DIO_DATA, TLan_DioWrite16(), TLan_DioWrite32(), TLan_DioWrite8(), TLAN_DUPLEX_FULL, TLan_FinishReset(), TLAN_HASH_2, TLAN_HC_AD_RST, TLAN_HC_INT_OFF, TLAN_HC_LD_THR, TLAN_HC_LD_TMR, TLAN_HOST_CMD, TLAN_ID_RX_EOC, TLAN_ID_TX_EOC, TLAN_INT_DIS, TLAN_NET_CFG_1CHAN, TLAN_NET_CFG_1FRAG, TLAN_NET_CFG_BIT, TLAN_NET_CFG_PHY_EN, TLAN_NET_CONFIG, TLAN_NET_SIO, TLAN_NET_SIO_NMRST, TLan_PhyDetect(), TLan_PhyPowerDown(), TLan_SetBit, tlan_private::tlanFullDuplex, tlan_private::tlanRev, TRUE, u16, u32, u8, and udelay().

Referenced by tlan_probe().

00300 {
00301         int i;
00302         u32 addr;
00303         u32 data;
00304         u8 data8;
00305 
00306         priv->tlanFullDuplex = FALSE;
00307         priv->phyOnline = 0;
00308 /*  1.  Assert reset bit. */
00309 
00310         data = inl(BASE + TLAN_HOST_CMD);
00311         data |= TLAN_HC_AD_RST;
00312         outl(data, BASE + TLAN_HOST_CMD);
00313 
00314         udelay(1000);
00315 
00316 /*  2.  Turn off interrupts. ( Probably isn't necessary ) */
00317 
00318         data = inl(BASE + TLAN_HOST_CMD);
00319         data |= TLAN_HC_INT_OFF;
00320         outl(data, BASE + TLAN_HOST_CMD);
00321 /*  3.  Clear AREGs and HASHs. */
00322 
00323         for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
00324                 TLan_DioWrite32(BASE, (u16) i, 0);
00325         }
00326 
00327 /*  4.  Setup NetConfig register. */
00328 
00329         data =
00330             TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
00331         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
00332 
00333 /*  5.  Load Ld_Tmr and Ld_Thr in HOST_CMD. */
00334 
00335         outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
00336         outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
00337 
00338 /*  6.  Unreset the MII by setting NMRST (in NetSio) to 1. */
00339 
00340         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
00341         addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
00342         TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
00343 
00344 /*  7.  Setup the remaining registers. */
00345 
00346         if (priv->tlanRev >= 0x30) {
00347                 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
00348                 TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
00349         }
00350         TLan_PhyDetect(nic);
00351         data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
00352 
00353         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
00354                 data |= TLAN_NET_CFG_BIT;
00355                 if (priv->aui == 1) {
00356                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
00357                 } else if (priv->duplex == TLAN_DUPLEX_FULL) {
00358                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
00359                         priv->tlanFullDuplex = TRUE;
00360                 } else {
00361                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
00362                 }
00363         }
00364 
00365         if (priv->phyNum == 0) {
00366                 data |= TLAN_NET_CFG_PHY_EN;
00367         }
00368         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
00369 
00370         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
00371                 TLan_FinishReset(nic);
00372         } else {
00373                 TLan_PhyPowerDown(nic);
00374         }
00375 
00376 }       /* TLan_ResetAdapter */

static void TLan_FinishReset ( struct nic *nic  __unused  )  [static]

Referenced by TLan_FinishReset(), TLan_PhyFinishAutoNeg(), TLan_PhyStartLink(), and TLan_ResetAdapter().

void TLan_EeSendStart ( u16  io_base  )  [static]

Definition at line 881 of file tlan.c.

References outw, TLan_ClearBit, TLAN_DIO_ADR, TLAN_DIO_DATA, TLAN_NET_SIO, TLAN_NET_SIO_ECLOK, TLAN_NET_SIO_EDATA, TLAN_NET_SIO_ETXEN, TLan_SetBit, and u16.

Referenced by TLan_EeReadByte().

00882 {
00883         u16 sio;
00884 
00885         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
00886         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
00887 
00888         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00889         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
00890         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
00891         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
00892         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00893 
00894 }       /* TLan_EeSendStart */

int TLan_EeSendByte ( u16  io_base,
u8  data,
int  stop 
) [static]

Definition at line 918 of file tlan.c.

References outw, TLan_ClearBit, TLAN_DIO_ADR, TLAN_DIO_DATA, TLan_GetBit, TLAN_NET_SIO, TLAN_NET_SIO_ECLOK, TLAN_NET_SIO_EDATA, TLAN_NET_SIO_ETXEN, TLan_SetBit, u16, and u8.

Referenced by TLan_EeReadByte().

00919 {
00920         int err;
00921         u8 place;
00922         u16 sio;
00923 
00924         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
00925         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
00926 
00927         /* Assume clock is low, tx is enabled; */
00928         for (place = 0x80; place != 0; place >>= 1) {
00929                 if (place & data)
00930                         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
00931                 else
00932                         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
00933                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00934                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00935         }
00936         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
00937         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00938         err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
00939         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00940         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
00941 
00942         if ((!err) && stop) {
00943                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
00944                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00945                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
00946         }
00947 
00948         return (err);
00949 
00950 }       /* TLan_EeSendByte */

void TLan_EeReceiveByte ( u16  io_base,
u8 *  data,
int  stop 
) [static]

Definition at line 976 of file tlan.c.

References outw, TLan_ClearBit, TLAN_DIO_ADR, TLAN_DIO_DATA, TLan_GetBit, TLAN_NET_SIO, TLAN_NET_SIO_ECLOK, TLAN_NET_SIO_EDATA, TLAN_NET_SIO_ETXEN, TLan_SetBit, u16, and u8.

Referenced by TLan_EeReadByte().

00977 {
00978         u8 place;
00979         u16 sio;
00980 
00981         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
00982         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
00983         *data = 0;
00984 
00985         /* Assume clock is low, tx is enabled; */
00986         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
00987         for (place = 0x80; place; place >>= 1) {
00988                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00989                 if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
00990                         *data |= place;
00991                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00992         }
00993 
00994         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
00995         if (!stop) {
00996                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */
00997                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
00998                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
00999         } else {
01000                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);   /* No ack = 1 (?) */
01001                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
01002                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
01003                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
01004                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
01005                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
01006         }
01007 
01008 }       /* TLan_EeReceiveByte */

int TLan_EeReadByte ( u16  io_base,
u8  ee_addr,
u8 *  data 
) [static]

Definition at line 1031 of file tlan.c.

References TLAN_EEPROM_ACK, TLAN_EEPROM_STOP, TLan_EeReceiveByte(), TLan_EeSendByte(), and TLan_EeSendStart().

Referenced by tlan_probe().

01032 {
01033         int err;
01034         int ret = 0;
01035 
01036 
01037         TLan_EeSendStart(io_base);
01038         err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
01039         if (err) {
01040                 ret = 1;
01041                 goto fail;
01042         }
01043         err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
01044         if (err) {
01045                 ret = 2;
01046                 goto fail;
01047         }
01048         TLan_EeSendStart(io_base);
01049         err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
01050         if (err) {
01051                 ret = 3;
01052                 goto fail;
01053         }
01054         TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
01055       fail:
01056 
01057         return ret;
01058 
01059 }       /* TLan_EeReadByte */

void TLan_PhyDetect ( struct nic *  nic  )  [static]

Definition at line 1338 of file tlan.c.

References chip_idx, MII_BMCR, MII_PHYSID1, MII_PHYSID2, tlan_private::phy, tlan_private::phyNum, printf(), TLAN_ADAPTER_UNMANAGED_PHY, TLan_MiiReadReg(), TLAN_PHY_MAX_ADDR, TLAN_PHY_NONE, u16, and u32.

Referenced by TLan_ResetAdapter().

01339 {
01340         u16 control;
01341         u16 hi;
01342         u16 lo;
01343         u32 phy;
01344 
01345         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
01346                 priv->phyNum = 0xFFFF;
01347                 return;
01348         }
01349 
01350         TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_PHYSID1, &hi);
01351 
01352         if (hi != 0xFFFF) {
01353                 priv->phy[0] = TLAN_PHY_MAX_ADDR;
01354         } else {
01355                 priv->phy[0] = TLAN_PHY_NONE;
01356         }
01357 
01358         priv->phy[1] = TLAN_PHY_NONE;
01359         for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
01360                 TLan_MiiReadReg(nic, phy, MII_BMCR, &control);
01361                 TLan_MiiReadReg(nic, phy, MII_PHYSID1, &hi);
01362                 TLan_MiiReadReg(nic, phy, MII_PHYSID2, &lo);
01363                 if ((control != 0xFFFF) || (hi != 0xFFFF)
01364                     || (lo != 0xFFFF)) {
01365                         printf("PHY found at %hX %hX %hX %hX\n", 
01366                                (unsigned int) phy, control, hi, lo);
01367                         if ((priv->phy[1] == TLAN_PHY_NONE)
01368                             && (phy != TLAN_PHY_MAX_ADDR)) {
01369                                 priv->phy[1] = phy;
01370                         }
01371                 }
01372         }
01373 
01374         if (priv->phy[1] != TLAN_PHY_NONE) {
01375                 priv->phyNum = 1;
01376         } else if (priv->phy[0] != TLAN_PHY_NONE) {
01377                 priv->phyNum = 0;
01378         } else {
01379                 printf
01380                     ("TLAN:  Cannot initialize device, no PHY was found!\n");
01381         }
01382 
01383 }                               /* TLan_PhyDetect */

void TLan_PhyPowerDown ( struct nic *  nic  )  [static]

Definition at line 1385 of file tlan.c.

References BASE, BMCR_ISOLATE, BMCR_LOOPBACK, BMCR_PDOWN, chip_idx, DBG, mdelay(), MII_BMCR, tlan_private::nic_name, tlan_private::phy, tlan_private::phyNum, TLAN_ADAPTER_USE_INTERN_10, TLan_MiiSync(), TLan_MiiWriteReg(), TLAN_PHY_NONE, TLan_PhyPowerUp(), and u16.

Referenced by TLan_PhyFinishAutoNeg(), TLan_PhyStartLink(), and TLan_ResetAdapter().

01386 {
01387 
01388         u16 value;
01389         DBG ( "%s: Powering down PHY(s).\n", priv->nic_name );
01390         value = BMCR_PDOWN | BMCR_LOOPBACK | BMCR_ISOLATE;
01391         TLan_MiiSync(BASE);
01392         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value);
01393         if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
01394             &&
01395             (!(tlan_pci_tbl[chip_idx].
01396                flags & TLAN_ADAPTER_USE_INTERN_10))) {
01397                 TLan_MiiSync(BASE);
01398                 TLan_MiiWriteReg(nic, priv->phy[1], MII_BMCR, value);
01399         }
01400 
01401         /* Wait for 50 ms and powerup
01402          * This is abitrary.  It is intended to make sure the
01403          * tranceiver settles.
01404          */
01405         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
01406         mdelay(50);
01407         TLan_PhyPowerUp(nic);
01408 
01409 }                               /* TLan_PhyPowerDown */

void TLan_PhyPowerUp ( struct nic *  nic  )  [static]

Definition at line 1412 of file tlan.c.

References BASE, BMCR_LOOPBACK, DBG, mdelay(), MII_BMCR, tlan_private::nic_name, tlan_private::phy, tlan_private::phyNum, TLan_MiiSync(), TLan_MiiWriteReg(), TLan_PhyReset(), and u16.

Referenced by TLan_PhyPowerDown().

01413 {
01414         u16 value;
01415 
01416         DBG ( "%s: Powering up PHY.\n", priv->nic_name );
01417         TLan_MiiSync(BASE);
01418         value = BMCR_LOOPBACK;
01419         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value);
01420         TLan_MiiSync(BASE);
01421         /* Wait for 500 ms and reset the
01422          * tranceiver.  The TLAN docs say both 50 ms and
01423          * 500 ms, so do the longer, just in case.
01424          */
01425         mdelay(500);
01426         TLan_PhyReset(nic);
01427         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
01428 
01429 }                               /* TLan_PhyPowerUp */

void TLan_SetMac ( struct nic *nic  __unused,
int  areg,
unsigned char *  mac 
) [static]

Definition at line 1304 of file tlan.c.

References BASE, NULL, TLAN_AREG_0, and TLan_DioWrite8().

Referenced by TLan_FinishReset(), and TLan_SetMulticastList().

01305 {
01306         int i;
01307 
01308         areg *= 6;
01309 
01310         if (mac != NULL) {
01311                 for (i = 0; i < 6; i++)
01312                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
01313                                        mac[i]);
01314         } else {
01315                 for (i = 0; i < 6; i++)
01316                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
01317         }
01318 
01319 }                               /* TLan_SetMac */

void TLan_PhyReset ( struct nic *  nic  )  [static]

Definition at line 1431 of file tlan.c.

References BASE, BMCR_LOOPBACK, BMCR_RESET, DBG, mdelay(), MII_BMCR, tlan_private::nic_name, tlan_private::phy, tlan_private::phyNum, TLan_MiiReadReg(), TLan_MiiSync(), TLan_MiiWriteReg(), TLan_PhyStartLink(), and u16.

Referenced by TLan_PhyPowerUp().

01432 {
01433         u16 phy;
01434         u16 value;
01435 
01436         phy = priv->phy[priv->phyNum];
01437 
01438         DBG ( "%s: Reseting PHY.\n", priv->nic_name );
01439         TLan_MiiSync(BASE);
01440         value = BMCR_LOOPBACK | BMCR_RESET;
01441         TLan_MiiWriteReg(nic, phy, MII_BMCR, value);
01442         TLan_MiiReadReg(nic, phy, MII_BMCR, &value);
01443         while (value & BMCR_RESET) {
01444                 TLan_MiiReadReg(nic, phy, MII_BMCR, &value);
01445         }
01446 
01447         /* Wait for 500 ms and initialize.
01448          * I don't remember why I wait this long.
01449          * I've changed this to 50ms, as it seems long enough.
01450          */
01451         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
01452         mdelay(50);
01453         TLan_PhyStartLink(nic);
01454 
01455 }                               /* TLan_PhyReset */

void TLan_PhyStartLink ( struct nic *  nic  )  [static]

Definition at line 1458 of file tlan.c.

References tlan_private::aui, BASE, BMCR_FULLDPLX, BMCR_SPEED100, BMSR_ANEGCAPABLE, DBG, tlan_private::duplex, mdelay(), MII_ADVERTISE, MII_BMCR, MII_BMSR, tlan_private::nic_name, tlan_private::phy, tlan_private::phyNum, tlan_private::speed, TLan_DioWrite16(), TLAN_DUPLEX_FULL, TLAN_DUPLEX_HALF, TLan_FinishReset(), TLan_MiiReadReg(), TLan_MiiWriteReg(), TLAN_NET_CFG_1CHAN, TLAN_NET_CFG_1FRAG, TLAN_NET_CFG_PHY_EN, TLAN_NET_CONFIG, TLan_PhyFinishAutoNeg(), TLan_PhyPowerDown(), TLAN_SPEED_10, TLAN_SPEED_100, TLAN_TC_AUISEL, TLAN_TLPHY_CTL, tlan_private::tlanFullDuplex, TRUE, and u16.

Referenced by TLan_PhyReset().

01459 {
01460 
01461         u16 ability;
01462         u16 control;
01463         u16 data;
01464         u16 phy;
01465         u16 status;
01466         u16 tctl;
01467 
01468         phy = priv->phy[priv->phyNum];
01469         DBG ( "%s: Trying to activate link.\n", priv->nic_name );
01470         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
01471         TLan_MiiReadReg(nic, phy, MII_BMSR, &ability);
01472 
01473         if ((status & BMSR_ANEGCAPABLE) && (!priv->aui)) {
01474                 ability = status >> 11;
01475                 if (priv->speed == TLAN_SPEED_10 &&
01476                     priv->duplex == TLAN_DUPLEX_HALF) {
01477                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0000);
01478                 } else if (priv->speed == TLAN_SPEED_10 &&
01479                            priv->duplex == TLAN_DUPLEX_FULL) {
01480                         priv->tlanFullDuplex = TRUE;
01481                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0100);
01482                 } else if (priv->speed == TLAN_SPEED_100 &&
01483                            priv->duplex == TLAN_DUPLEX_HALF) {
01484                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2000);
01485                 } else if (priv->speed == TLAN_SPEED_100 &&
01486                            priv->duplex == TLAN_DUPLEX_FULL) {
01487                         priv->tlanFullDuplex = TRUE;
01488                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2100);
01489                 } else {
01490 
01491                         /* Set Auto-Neg advertisement */
01492                         TLan_MiiWriteReg(nic, phy, MII_ADVERTISE,
01493                                          (ability << 5) | 1);
01494                         /* Enablee Auto-Neg */
01495                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1000);
01496                         /* Restart Auto-Neg */
01497                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1200);
01498                         /* Wait for 4 sec for autonegotiation
01499                          * to complete.  The max spec time is less than this
01500                          * but the card need additional time to start AN.
01501                          * .5 sec should be plenty extra.
01502                          */
01503                         DBG ( "TLAN: %s: Starting autonegotiation.\n",
01504                                priv->nic_name );
01505                         mdelay(4000);
01506                         TLan_PhyFinishAutoNeg(nic);
01507                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
01508                         return;
01509                 }
01510 
01511         }
01512 
01513         if ((priv->aui) && (priv->phyNum != 0)) {
01514                 priv->phyNum = 0;
01515                 data =
01516                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
01517                     TLAN_NET_CFG_PHY_EN;
01518                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
01519                 mdelay(50);
01520                 /* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
01521                 TLan_PhyPowerDown(nic);
01522                 return;
01523         } else if (priv->phyNum == 0) {
01524                 control = 0;
01525                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
01526                 if (priv->aui) {
01527                         tctl |= TLAN_TC_AUISEL;
01528                 } else {
01529                         tctl &= ~TLAN_TC_AUISEL;
01530                         if (priv->duplex == TLAN_DUPLEX_FULL) {
01531                                 control |= BMCR_FULLDPLX;
01532                                 priv->tlanFullDuplex = TRUE;
01533                         }
01534                         if (priv->speed == TLAN_SPEED_100) {
01535                                 control |= BMCR_SPEED100;
01536                         }
01537                 }
01538                 TLan_MiiWriteReg(nic, phy, MII_BMCR, control);
01539                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
01540         }
01541 
01542         /* Wait for 2 sec to give the tranceiver time
01543          * to establish link.
01544          */
01545         /* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */
01546         mdelay(2000);
01547         TLan_FinishReset(nic);
01548 
01549 }                               /* TLan_PhyStartLink */

void TLan_PhyFinishAutoNeg ( struct nic *  nic  )  [static]

Definition at line 1551 of file tlan.c.

References BASE, BMCR_ANENABLE, BMCR_FULLDPLX, BMSR_ANEGCOMPLETE, chip_idx, DBG, tlan_private::duplex, mdelay(), MII_ADVERTISE, MII_BMCR, MII_BMSR, MII_LPA, tlan_private::neg_be_verbose, tlan_private::nic_name, tlan_private::phy, tlan_private::phyNum, printf(), TLAN_ADAPTER_USE_INTERN_10, TLan_DioWrite16(), TLAN_DUPLEX_FULL, TLan_FinishReset(), TLan_MiiReadReg(), TLan_MiiWriteReg(), TLAN_NET_CFG_1CHAN, TLAN_NET_CFG_1FRAG, TLAN_NET_CFG_PHY_EN, TLAN_NET_CONFIG, TLan_PhyPowerDown(), tlan_private::tlanFullDuplex, TRUE, u16, and udelay().

Referenced by TLan_PhyStartLink().

01552 {
01553 
01554         u16 an_adv;
01555         u16 an_lpa;
01556         u16 data;
01557         u16 mode;
01558         u16 phy;
01559         u16 status;
01560 
01561         phy = priv->phy[priv->phyNum];
01562 
01563         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
01564         udelay(1000);
01565         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
01566 
01567         if (!(status & BMSR_ANEGCOMPLETE)) {
01568                 /* Wait for 8 sec to give the process
01569                  * more time.  Perhaps we should fail after a while.
01570                  */
01571                 if (!priv->neg_be_verbose++) {
01572                         printf
01573                             ("TLAN:  Giving autonegotiation more time.\n");
01574                         printf
01575                             ("TLAN:  Please check that your adapter has\n");
01576                         printf
01577                             ("TLAN:  been properly connected to a HUB or Switch.\n");
01578                         printf
01579                             ("TLAN:  Trying to establish link in the background...\n");
01580                 }
01581                 mdelay(8000);
01582                 TLan_PhyFinishAutoNeg(nic);
01583                 /* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
01584                 return;
01585         }
01586 
01587         DBG ( "TLAN: %s: Autonegotiation complete.\n", priv->nic_name );
01588         TLan_MiiReadReg(nic, phy, MII_ADVERTISE, &an_adv);
01589         TLan_MiiReadReg(nic, phy, MII_LPA, &an_lpa);
01590         mode = an_adv & an_lpa & 0x03E0;
01591         if (mode & 0x0100) {
01592                 printf("Full Duplex\n");
01593                 priv->tlanFullDuplex = TRUE;
01594         } else if (!(mode & 0x0080) && (mode & 0x0040)) {
01595                 priv->tlanFullDuplex = TRUE;
01596                 printf("Full Duplex\n");
01597         }
01598 
01599         if ((!(mode & 0x0180))
01600             && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
01601             && (priv->phyNum != 0)) {
01602                 priv->phyNum = 0;
01603                 data =
01604                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
01605                     TLAN_NET_CFG_PHY_EN;
01606                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
01607                 /* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
01608                 mdelay(400);
01609                 TLan_PhyPowerDown(nic);
01610                 return;
01611         }
01612 
01613         if (priv->phyNum == 0) {
01614                 if ((priv->duplex == TLAN_DUPLEX_FULL)
01615                     || (an_adv & an_lpa & 0x0040)) {
01616                         TLan_MiiWriteReg(nic, phy, MII_BMCR,
01617                                          BMCR_ANENABLE | BMCR_FULLDPLX);
01618                         DBG 
01619                             ( "TLAN:  Starting internal PHY with FULL-DUPLEX\n" );
01620                 } else {
01621                         TLan_MiiWriteReg(nic, phy, MII_BMCR,
01622                                          BMCR_ANENABLE);
01623                         DBG 
01624                             ( "TLAN:  Starting internal PHY with HALF-DUPLEX\n" );
01625                 }
01626         }
01627 
01628         /* Wait for 100 ms.  No reason in partiticular.
01629          */
01630         /* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
01631         mdelay(100);
01632         TLan_FinishReset(nic);
01633 
01634 }                               /* TLan_PhyFinishAutoNeg */

static void refill_rx ( struct nic *nic  __unused  )  [static]

Definition at line 549 of file tlan.c.

References tlan_private::cur_rx, tlan_private::dirty_rx, entry, rx_ring, TLAN_CSTAT_READY, TLAN_MAX_FRAME_SIZE, TLAN_NUM_RX_LISTS, and TLAN_NUM_TX_LISTS.

Referenced by alloc_rx(), and tlan_poll().

00550 {
00551         int entry = 0;
00552 
00553         for (;
00554              (priv->cur_rx - priv->dirty_rx +
00555               TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
00556              priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
00557                 entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
00558                 rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
00559                 rx_ring[entry].cStat = TLAN_CSTAT_READY;
00560         }
00561 
00562 }

int TLan_MiiReadReg ( struct nic *nic  __unused,
u16  phy,
u16  reg,
u16 *  val 
) [static]

Definition at line 1098 of file tlan.c.

References BASE, FALSE, outw, TLan_ClearBit, TLAN_DIO_ADR, TLAN_DIO_DATA, TLan_GetBit, TLan_MiiSendData(), TLan_MiiSync(), TLAN_NET_SIO, TLAN_NET_SIO_MCLK, TLAN_NET_SIO_MDATA, TLAN_NET_SIO_MINTEN, TLAN_NET_SIO_MTXEN, TLan_SetBit, TRUE, u16, u32, and u8.

Referenced by TLan_FinishReset(), TLan_PhyDetect(), TLan_PhyFinishAutoNeg(), TLan_PhyReset(), and TLan_PhyStartLink().

01099 {
01100         u8 nack;
01101         u16 sio, tmp;
01102         u32 i;
01103         int err;
01104         int minten;
01105 
01106         err = FALSE;
01107         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
01108         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
01109 
01110         TLan_MiiSync(BASE);
01111 
01112         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
01113         if (minten)
01114                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
01115 
01116         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
01117         TLan_MiiSendData(BASE, 0x2, 2); /* Read  ( 10b ) */
01118         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
01119         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
01120 
01121 
01122         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */
01123 
01124         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Clock Idle bit */
01125         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01126         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Wait 300ns */
01127 
01128         nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);    /* Check for ACK */
01129         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);    /* Finish ACK */
01130         if (nack) {             /* No ACK, so fake it */
01131                 for (i = 0; i < 16; i++) {
01132                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
01133                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01134                 }
01135                 tmp = 0xffff;
01136                 err = TRUE;
01137         } else {                /* ACK, so read data */
01138                 for (tmp = 0, i = 0x8000; i; i >>= 1) {
01139                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
01140                         if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
01141                                 tmp |= i;
01142                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01143                 }
01144         }
01145 
01146 
01147         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
01148         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01149 
01150         if (minten)
01151                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
01152 
01153         *val = tmp;
01154 
01155         return err;
01156 
01157 }                               /* TLan_MiiReadReg */

void TLan_MiiSendData ( u16  base_port,
u32  data,
unsigned  num_bits 
) [static]

Definition at line 1177 of file tlan.c.

References outw, TLan_ClearBit, TLAN_DIO_ADR, TLAN_DIO_DATA, TLan_GetBit, TLAN_NET_SIO, TLAN_NET_SIO_MCLK, TLAN_NET_SIO_MDATA, TLAN_NET_SIO_MTXEN, TLan_SetBit, u16, and u32.

Referenced by TLan_MiiReadReg(), and TLan_MiiWriteReg().

01178 {
01179         u16 sio;
01180         u32 i;
01181 
01182         if (num_bits == 0)
01183                 return;
01184 
01185         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
01186         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
01187         TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
01188 
01189         for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
01190                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
01191                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
01192                 if (data & i)
01193                         TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
01194                 else
01195                         TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
01196                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01197                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
01198         }
01199 
01200 }                               /* TLan_MiiSendData */

void TLan_MiiSync ( u16  base_port  )  [static]

Definition at line 1216 of file tlan.c.

References outw, TLan_ClearBit, TLAN_DIO_ADR, TLAN_DIO_DATA, TLAN_NET_SIO, TLAN_NET_SIO_MCLK, TLAN_NET_SIO_MTXEN, TLan_SetBit, and u16.

Referenced by TLan_MiiReadReg(), TLan_MiiWriteReg(), TLan_PhyPowerDown(), TLan_PhyPowerUp(), and TLan_PhyReset().

01217 {
01218         int i;
01219         u16 sio;
01220 
01221         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
01222         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
01223 
01224         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
01225         for (i = 0; i < 32; i++) {
01226                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
01227                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01228         }
01229 
01230 }                               /* TLan_MiiSync */

void TLan_MiiWriteReg ( struct nic *nic  __unused,
u16  phy,
u16  reg,
u16  val 
) [static]

Definition at line 1252 of file tlan.c.

References BASE, outw, TLan_ClearBit, TLAN_DIO_ADR, TLAN_DIO_DATA, TLan_GetBit, TLan_MiiSendData(), TLan_MiiSync(), TLAN_NET_SIO, TLAN_NET_SIO_MCLK, TLAN_NET_SIO_MINTEN, TLan_SetBit, and u16.

Referenced by TLan_FinishReset(), TLan_PhyFinishAutoNeg(), TLan_PhyPowerDown(), TLan_PhyPowerUp(), TLan_PhyReset(), and TLan_PhyStartLink().

01253 {
01254         u16 sio;
01255         int minten;
01256 
01257         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
01258         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
01259 
01260         TLan_MiiSync(BASE);
01261 
01262         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
01263         if (minten)
01264                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
01265 
01266         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
01267         TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
01268         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
01269         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
01270 
01271         TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
01272         TLan_MiiSendData(BASE, val, 16);        /* Send Data */
01273 
01274         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
01275         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
01276 
01277         if (minten)
01278                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
01279 
01280 
01281 }                               /* TLan_MiiWriteReg */

void TLan_FinishReset ( struct nic *  nic  ) 

Definition at line 378 of file tlan.c.

References tlan_private::aui, BASE, BMSR_LSTATUS, chip_idx, DBG, tlan_private::link, mdelay(), media, MII_BMSR, MII_LPA, MII_PHYSID1, MII_PHYSID2, NAT_SEM_ID1, NAT_SEM_ID2, tlan_private::nic_name, nic::node_addr, outb, outl, tlan_private::phy, tlan_private::phyNum, tlan_private::phyOnline, rx_ring, TLAN_ADAPTER_UNMANAGED_PHY, TLAN_CH_PARM, TLan_DioRead8(), TLan_DioWrite16(), TLan_DioWrite8(), TLan_FinishReset(), TLAN_HC_GO, TLAN_HC_INT_ON, TLAN_HC_RT, TLAN_HOST_CMD, TLAN_LED_LINK, TLAN_LED_REG, TLAN_MAX_RX, TLan_MiiReadReg(), TLan_MiiWriteReg(), TLAN_NET_CMD, TLAN_NET_CMD_DUPLEX, TLAN_NET_CMD_NRESET, TLAN_NET_CMD_NWRAP, TLAN_NET_MASK, TLAN_NET_MASK_MASK4, TLAN_NET_MASK_MASK5, TLAN_NET_MASK_MASK7, TLAN_NET_SIO, TLAN_NET_SIO_MINTEN, TLAN_PHY_AN_EN_STAT, TLAN_PHY_DUPLEX_FULL, TLAN_PHY_SPEED_100, TLan_SetMac(), TLAN_TC_INTEN, TLAN_TLPHY_CTL, TLAN_TLPHY_PAR, tlan_private::tlanFullDuplex, u16, u32, u8, udelay(), and virt_to_bus().

00379 {
00380 
00381         u8 data;
00382         u32 phy;
00383         u8 sio;
00384         u16 status;
00385         u16 partner;
00386         u16 tlphy_ctl;
00387         u16 tlphy_par;
00388         u16 tlphy_id1, tlphy_id2;
00389         int i;
00390 
00391         phy = priv->phy[priv->phyNum];
00392 
00393         data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
00394         if (priv->tlanFullDuplex) {
00395                 data |= TLAN_NET_CMD_DUPLEX;
00396         }
00397         TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
00398         data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
00399         if (priv->phyNum == 0) {
00400                 data |= TLAN_NET_MASK_MASK7;
00401         }
00402         TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
00403         TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
00404         TLan_MiiReadReg(nic, phy, MII_PHYSID1, &tlphy_id1);
00405         TLan_MiiReadReg(nic, phy, MII_PHYSID2, &tlphy_id2);
00406 
00407         if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
00408             || (priv->aui)) {
00409                 status = BMSR_LSTATUS;
00410                 DBG ( "TLAN:  %s: Link forced.\n", priv->nic_name );
00411         } else {
00412                 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
00413                 udelay(1000);
00414                 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
00415                 if ((status & BMSR_LSTATUS) &&  /* We only support link info on Nat.Sem. PHY's */
00416                     (tlphy_id1 == NAT_SEM_ID1)
00417                     && (tlphy_id2 == NAT_SEM_ID2)) {
00418                         TLan_MiiReadReg(nic, phy, MII_LPA, &partner);
00419                         TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
00420                                         &tlphy_par);
00421 
00422                         DBG ( "TLAN: %s: Link active with ",
00423                                priv->nic_name );
00424                         if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
00425                                 DBG ( "forced 10%sMbps %s-Duplex\n",
00426                                        tlphy_par & TLAN_PHY_SPEED_100 ? ""
00427                                        : "0",
00428                                        tlphy_par & TLAN_PHY_DUPLEX_FULL ?
00429                                        "Full" : "Half" );
00430                         } else {
00431                                 DBG 
00432                                     ( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
00433                                      tlphy_par & TLAN_PHY_SPEED_100 ? "" :
00434                                      "0",
00435                                      tlphy_par & TLAN_PHY_DUPLEX_FULL ?
00436                                      "Full" : "Half" );
00437                                 DBG ( "TLAN: Partner capability: " );
00438                                 for (i = 5; i <= 10; i++)
00439                                         if (partner & (1 << i)) {
00440                                                 DBG ( "%s", media[i - 5] );
00441                                         }
00442                                 DBG ( "\n" );
00443                         }
00444 
00445                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
00446 #ifdef MONITOR
00447                         /* We have link beat..for now anyway */
00448                         priv->link = 1;
00449                         /*Enabling link beat monitoring */
00450                         /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */
00451                         mdelay(10000);
00452                         TLan_PhyMonitor(nic);
00453 #endif
00454                 } else if (status & BMSR_LSTATUS) {
00455                         DBG ( "TLAN: %s: Link active\n", priv->nic_name );
00456                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
00457                 }
00458         }
00459 
00460         if (priv->phyNum == 0) {
00461                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
00462                 tlphy_ctl |= TLAN_TC_INTEN;
00463                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
00464                 sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
00465                 sio |= TLAN_NET_SIO_MINTEN;
00466                 TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
00467         }
00468 
00469         if (status & BMSR_LSTATUS) {
00470                 TLan_SetMac(nic, 0, nic->node_addr);
00471                 priv->phyOnline = 1;
00472                 outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
00473                 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
00474                 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
00475         } else {
00476                 DBG 
00477                     ( "TLAN: %s: Link inactive, will retry in 10 secs...\n",
00478                      priv->nic_name );
00479                 /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */
00480                 mdelay(10000);
00481                 TLan_FinishReset(nic);
00482                 return;
00483 
00484         }
00485 
00486 }       /* TLan_FinishReset */

static int tlan_poll ( struct nic *  nic,
int  retrieve 
) [static]

Definition at line 491 of file tlan.c.

References BASE, TLanList::cStat, tlan_private::cur_rx, DBG, entry, inw, le32_to_cpu, memcpy, outl, outw, nic::packet, nic::packetlen, refill_rx(), rx_ring, rxb, TLAN_CH_PARM, TLAN_CSTAT_EOC, TLAN_CSTAT_FRM_CMP, TLAN_CSTAT_READY, TLAN_HC_ACK, TLAN_HC_GO, TLAN_HC_RT, TLAN_HOST_CMD, TLAN_HOST_INT, TLAN_MAX_FRAME_SIZE, TLAN_NUM_RX_LISTS, u16, and u32.

00492 {
00493         /* return true if there's an ethernet packet ready to read */
00494         /* nic->packet should contain data on return */
00495         /* nic->packetlen should contain length of data */
00496         u32 framesize;
00497         u32 host_cmd = 0;
00498         u32 ack = 1;
00499         int eoc = 0;
00500         int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
00501         u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
00502         u16 host_int = inw(BASE + TLAN_HOST_INT);
00503 
00504         if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
00505           return 1;
00506 
00507         outw(host_int, BASE + TLAN_HOST_INT);
00508 
00509         if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
00510                 return 0;
00511 
00512         /* printf("PI-1: 0x%hX\n", host_int); */
00513         if (tmpCStat & TLAN_CSTAT_EOC)
00514                 eoc = 1;
00515 
00516         framesize = rx_ring[entry].frameSize;
00517 
00518         nic->packetlen = framesize;
00519 
00520         DBG ( ".%d.", (unsigned int) framesize ); 
00521      
00522         memcpy(nic->packet, rxb +
00523                (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
00524 
00525         rx_ring[entry].cStat = 0;
00526 
00527         DBG ( "%d", entry );  
00528 
00529         entry = (entry + 1) % TLAN_NUM_RX_LISTS;
00530         priv->cur_rx = entry;
00531         if (eoc) {
00532                 if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
00533                     TLAN_CSTAT_READY) {
00534                         ack |= TLAN_HC_GO | TLAN_HC_RT;
00535                         host_cmd = TLAN_HC_ACK | ack | 0x001C0000;
00536                         outl(host_cmd, BASE + TLAN_HOST_CMD);
00537                 }
00538         } else {
00539                 host_cmd = TLAN_HC_ACK | ack | (0x000C0000);
00540                 outl(host_cmd, BASE + TLAN_HOST_CMD);
00541                 
00542                 DBG ( "AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM) ); 
00543                 DBG ( "PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT) );
00544         }
00545         refill_rx(nic);
00546         return (1);             /* initially as this is called to flush the input */
00547 }

static void tlan_transmit ( struct nic *  nic,
const char *  d,
unsigned int  t,
unsigned int  s,
const char *  p 
) [static]

Definition at line 567 of file tlan.c.

References TLanList::address, BASE, TLanList::buffer, CIRC_INC, TLanList::count, TLanList::cStat, currticks(), DBG, entry, ETH_ALEN, ETH_HLEN, ETH_ZLEN, TLanList::forward, TLanList::frameSize, htons, inw, memcpy, tlan_private::nic_name, nic::node_addr, outl, tlan_private::phyOnline, printf(), TLAN_CH_PARM, TLAN_CSTAT_EOC, TLAN_CSTAT_FRM_CMP, TLAN_CSTAT_READY, TLAN_CSTAT_UNUSED, TLAN_HC_ACK, TLAN_HC_GO, TLAN_HOST_CMD, TLAN_HOST_INT, TLAN_LAST_BUFFER, TLAN_MAX_FRAME_SIZE, TLAN_NUM_TX_LISTS, tlan_private::tlanRev, tx_ring, TX_TIME_OUT, txb, tlan_private::txHead, tlan_private::txInProgress, tlan_private::txList, tlan_private::txTail, u16, u32, u8, and virt_to_le32desc.

00571 {                               /* Packet */
00572         u16 nstype;
00573         u32 to;
00574         struct TLanList *tail_list;
00575         struct TLanList *head_list;
00576         u8 *tail_buffer;
00577         u32 ack = 0;
00578         u32 host_cmd;
00579         int eoc = 0;
00580         u16 tmpCStat;
00581         u16 host_int = inw(BASE + TLAN_HOST_INT);
00582 
00583         int entry = 0;
00584 
00585         DBG ( "INT0-0x%hX\n", host_int );
00586 
00587         if (!priv->phyOnline) {
00588                 printf("TRANSMIT:  %s PHY is not ready\n", priv->nic_name);
00589                 return;
00590         }
00591 
00592         tail_list = priv->txList + priv->txTail;
00593 
00594         if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
00595                 printf("TRANSMIT: %s is busy (Head=%p Tail=%x)\n",
00596                        priv->nic_name, priv->txList, (unsigned int) priv->txTail);
00597                 tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
00598 //              priv->txBusyCount++;
00599                 return;
00600         }
00601 
00602         tail_list->forward = 0;
00603 
00604         tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
00605 
00606         /* send the packet to destination */
00607         memcpy(tail_buffer, d, ETH_ALEN);
00608         memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
00609         nstype = htons((u16) t);
00610         memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
00611         memcpy(tail_buffer + ETH_HLEN, p, s);
00612 
00613         s += ETH_HLEN;
00614         s &= 0x0FFF;
00615         while (s < ETH_ZLEN)
00616                 tail_buffer[s++] = '\0';
00617 
00618         /*=====================================================*/
00619         /* Receive
00620          * 0000 0000 0001 1100
00621          * 0000 0000 0000 1100
00622          * 0000 0000 0000 0011 = 0x0003
00623          *
00624          * 0000 0000 0000 0000 0000 0000 0000 0011
00625          * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
00626          *
00627          * Transmit
00628          * 0000 0000 0001 1100
00629          * 0000 0000 0000 0100
00630          * 0000 0000 0000 0001 = 0x0001
00631          *
00632          * 0000 0000 0000 0000 0000 0000 0000 0001
00633          * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
00634          * */
00635 
00636         /* Setup the transmit descriptor */
00637         tail_list->frameSize = (u16) s;
00638         tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s;
00639         tail_list->buffer[1].count = 0;
00640         tail_list->buffer[1].address = 0;
00641 
00642         tail_list->cStat = TLAN_CSTAT_READY;
00643 
00644         DBG ( "INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
00645 
00646         if (!priv->txInProgress) {
00647                 priv->txInProgress = 1;
00648                 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
00649                 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
00650         } else {
00651                 if (priv->txTail == 0) {
00652                         DBG ( "Out buffer\n" );
00653                         (priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
00654                             virt_to_le32desc(tail_list);
00655                 } else {
00656                         DBG ( "Fix this \n" );
00657                         (priv->txList + (priv->txTail - 1))->forward =
00658                             virt_to_le32desc(tail_list);
00659                 }
00660         }
00661         
00662         CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
00663 
00664         DBG ( "INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
00665 
00666         to = currticks() + TX_TIME_OUT;
00667         while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
00668 
00669         head_list = priv->txList + priv->txHead;
00670         while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP) 
00671                         && (ack < 255)) {
00672                 ack++;
00673                 if(tmpCStat & TLAN_CSTAT_EOC)
00674                         eoc =1;
00675                 head_list->cStat = TLAN_CSTAT_UNUSED;
00676                 CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
00677                 head_list = priv->txList + priv->txHead;
00678                 
00679         }
00680         if(!ack)
00681                 printf("Incomplete TX Frame\n");
00682 
00683         if(eoc) {
00684                 head_list = priv->txList + priv->txHead;
00685                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
00686                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
00687                         ack |= TLAN_HC_GO;
00688                 } else {
00689                         priv->txInProgress = 0;
00690                 }
00691         }
00692         if(ack) {
00693                 host_cmd = TLAN_HC_ACK | ack;
00694                 outl(host_cmd, BASE + TLAN_HOST_CMD);
00695         }
00696         
00697         if(priv->tlanRev < 0x30 ) {
00698                 ack = 1;
00699                 head_list = priv->txList + priv->txHead;
00700                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
00701                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
00702                         ack |= TLAN_HC_GO;
00703                 } else {
00704                         priv->txInProgress = 0;
00705                 }
00706                 host_cmd = TLAN_HC_ACK | ack | 0x00140000;
00707                 outl(host_cmd, BASE + TLAN_HOST_CMD);
00708                 
00709         }
00710                         
00711         if (currticks() >= to) {
00712                 printf("TX Time Out");
00713         }
00714 }

static void tlan_disable ( struct nic *nic  __unused  )  [static]

Definition at line 719 of file tlan.c.

References BASE, outl, TLAN_HC_AD_RST, and TLAN_HOST_CMD.

00719                                                       {
00720         /* put the card in its initial state */
00721         /* This function serves 3 purposes.
00722          * This disables DMA and interrupts so we don't receive
00723          *  unexpected packets or interrupts from the card after
00724          *  etherboot has finished.
00725          * This frees resources so etherboot may use
00726          *  this driver on another interface
00727          * This allows etherboot to reinitialize the interface
00728          *  if something is something goes wrong.
00729          *
00730          */
00731         outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
00732 }

static void tlan_irq ( struct nic *nic  __unused,
irq_action_t action  __unused 
) [static]

Definition at line 737 of file tlan.c.

References DISABLE, ENABLE, and FORCE.

00738 {
00739   switch ( action ) {
00740   case DISABLE :
00741     break;
00742   case ENABLE :
00743     break;
00744   case FORCE :
00745     break;
00746   }
00747 }

static void TLan_SetMulticastList ( struct nic *  nic  )  [static]

Definition at line 757 of file tlan.c.

References BASE, NULL, TLan_DioRead8(), TLan_DioWrite32(), TLan_DioWrite8(), TLAN_HASH_1, TLAN_HASH_2, TLAN_NET_CMD, TLAN_NET_CMD_CAF, TLan_SetMac(), and u8.

Referenced by tlan_probe().

00757                                                    {
00758         int i;
00759         u8 tmp;
00760 
00761         /* !IFF_PROMISC */
00762         tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
00763         TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
00764 
00765         /* IFF_ALLMULTI */
00766         for(i = 0; i< 3; i++)
00767                 TLan_SetMac(nic, i + 1, NULL);
00768         TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
00769         TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
00770 
00771         
00772 }

static int tlan_probe ( struct nic *  nic,
struct pci_device *  pci 
) [static]

Definition at line 779 of file tlan.c.

References adjust_pci_device(), BASE, chip_idx, DBG, tlan_private::dev_id, pci_device::device, pci_device::driver_name, tlan_private::eoc, eth_ntoa(), pci_id_info::id, inl, nic::ioaddr, pci_device::ioaddr, nic::irqno, name, tlan_private::nic_name, nic::nic_op, nic::node_addr, outw, pci_id_info::match_info::pci, printf(), TLAN_DEF_REVISION, TLan_DioRead8(), TLan_EeReadByte(), TLAN_HC_INT_OFF, TLAN_HOST_CMD, TLan_ResetAdapter(), TLan_ResetLists(), TLan_SetMulticastList(), TLanPrivateInfo, tlan_private::tlanRev, tx_ring, tlan_private::txList, u16, u32, u8, udelay(), pci_device::vendor, and tlan_private::vendor_id.

00779                                                                   {
00780 
00781         u16 data = 0;
00782         int err;
00783         int i;
00784 
00785         if (pci->ioaddr == 0)
00786                 return 0;
00787 
00788         nic->irqno  = 0;
00789         nic->ioaddr = pci->ioaddr;
00790 
00791         BASE = pci->ioaddr;
00792 
00793         /* Set nic as PCI bus master */
00794         adjust_pci_device(pci);
00795         
00796         /* Point to private storage */
00797         priv = &TLanPrivateInfo;
00798 
00799         /* Figure out which chip we're dealing with */
00800         i = 0;
00801         chip_idx = -1;
00802         while (tlan_pci_tbl[i].name) {
00803                 if ((((u32) pci->device << 16) | pci->vendor) ==
00804                     (tlan_pci_tbl[i].id.pci & 0xffffffff)) {
00805                         chip_idx = i;
00806                         break;
00807                 }
00808                 i++;
00809         }
00810 
00811         priv->vendor_id = pci->vendor;
00812         priv->dev_id = pci->device;
00813         priv->nic_name = pci->driver_name;
00814         priv->eoc = 0;
00815 
00816         err = 0;
00817         for (i = 0; i < 6; i++)
00818                 err |= TLan_EeReadByte(BASE,
00819                                        (u8) tlan_pci_tbl[chip_idx].
00820                                        addrOfs + i,
00821                                        (u8 *) & nic->node_addr[i]);
00822         if (err) {
00823             printf ( "TLAN: %s: Error reading MAC from eeprom: %d\n",
00824                     pci->driver_name, err);
00825         } else {
00826             DBG ( "%s: %s at ioaddr %#lX, ", 
00827                   pci->driver_name, eth_ntoa ( nic->node_addr ), pci->ioaddr );
00828         }
00829 
00830         priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
00831         printf("revision: 0x%hX\n", priv->tlanRev);
00832 
00833         TLan_ResetLists(nic);
00834         TLan_ResetAdapter(nic);
00835 
00836         data = inl(BASE + TLAN_HOST_CMD);
00837         data |= TLAN_HC_INT_OFF;
00838         outw(data, BASE + TLAN_HOST_CMD);
00839 
00840         TLan_SetMulticastList(nic);
00841         udelay(100); 
00842         priv->txList = tx_ring;
00843 
00844 /*      if (board_found && valid_link)
00845         {*/
00846         /* point to NIC specific routines */
00847         nic->nic_op     = &tlan_operations;
00848         return 1;
00849 }

PCI_DRIVER ( tlan_driver  ,
tlan_nics  ,
PCI_NO_CLASS   
)

DRIVER ( "TLAN/PCI"  ,
nic_driver  ,
pci_driver  ,
tlan_driver  ,
tlan_probe  ,
tlan_disable   
)

Variable Documentation

const char* media[] [static]

Initial value:

 {
        "10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
        "100baseTx-FD", "100baseT4", 0
}

Definition at line 94 of file tlan.c.

struct pci_id_info tlan_pci_tbl[] [static]

Definition at line 119 of file tlan.c.

struct TLanList tx_ring[TLAN_NUM_TX_LISTS]

Definition at line 182 of file tlan.c.

unsigned char txb[TLAN_MAX_FRAME_SIZE *TLAN_NUM_TX_LISTS]

Definition at line 183 of file tlan.c.

struct TLanList rx_ring[TLAN_NUM_RX_LISTS]

Definition at line 184 of file tlan.c.

unsigned char rxb[TLAN_MAX_FRAME_SIZE *TLAN_NUM_RX_LISTS]

Definition at line 185 of file tlan.c.

struct { ... } __shared

int chip_idx [static]

Definition at line 194 of file tlan.c.

Referenced by TLan_FinishReset(), TLan_PhyDetect(), TLan_PhyFinishAutoNeg(), TLan_PhyPowerDown(), tlan_probe(), TLan_ResetAdapter(), and tulip_probe().

struct tlan_private TLanPrivateInfo [static]

Referenced by tlan_probe().

struct tlan_private* priv [static]

Definition at line 223 of file tlan.c.

Referenced by grf5101_rf_init(), grf5101_rf_set_channel(), grf5101_rf_stop(), grf5101_write_phy_antenna(), ifec_check_ru_status(), ifec_free(), ifec_get_rx_desc(), ifec_init_eeprom(), ifec_link_check(), ifec_mdio_read(), ifec_mdio_setup(), ifec_mdio_write(), ifec_net_close(), ifec_net_irq(), ifec_net_open(), ifec_net_poll(), ifec_net_transmit(), ifec_pci_probe(), ifec_refill_rx_ring(), ifec_reprime_ru(), ifec_reset(), ifec_rx_process(), ifec_rx_setup(), ifec_scb_cmd(), ifec_scb_cmd_wait(), ifec_spi_read_bit(), ifec_spi_write_bit(), ifec_tx_process(), ifec_tx_setup(), ifec_tx_wake(), max2820_rf_init(), max2820_rf_set_channel(), max2820_write_phy_antenna(), mtnic_alloc_resources(), mtnic_close(), mtnic_disable(), mtnic_open(), mtnic_poll(), mtnic_probe(), mtnic_transmit(), myri10ge_interrupt_handler(), myri10ge_net_close(), myri10ge_net_open(), myri10ge_net_poll(), myri10ge_net_transmit(), myri10ge_pci_probe(), rtl818x_config(), rtl818x_free_rx_ring(), rtl818x_free_tx_ring(), rtl818x_handle_rx(), rtl818x_handle_tx(), rtl818x_init_hw(), rtl818x_init_rx_ring(), rtl818x_init_tx_ring(), rtl818x_irq(), rtl818x_poll(), rtl818x_probe(), rtl818x_set_hwaddr(), rtl818x_spi_read_bit(), rtl818x_spi_write_bit(), rtl818x_start(), rtl818x_stop(), rtl818x_tx(), rtl818x_write_phy(), rtl8225_read(), rtl8225_rf_conf_erp(), rtl8225_rf_init(), rtl8225_rf_set_channel(), rtl8225_rf_set_tx_power(), rtl8225_rf_stop(), rtl8225_write(), rtl8225x_rf_init(), rtl8225z2_rf_init(), rtl8225z2_rf_set_tx_power(), sa2400_rf_init(), sa2400_rf_set_channel(), sa2400_write_phy_antenna(), write_grf5101(), write_max2820(), and write_sa2400().

u32 BASE [static]

Definition at line 225 of file tlan.c.

struct nic_operations tlan_operations [static]

Initial value:

 {
        .connect        = dummy_connect,
        .poll           = tlan_poll,
        .transmit       = tlan_transmit,
        .irq            = tlan_irq,

}

Definition at line 749 of file tlan.c.

struct pci_device_id tlan_nics[] [static]

Initial value:

 {
        PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP", 0),
        PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP", 0),
        PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P", 0),
        PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P", 0),
        PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P", 0),
        PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP", 0),
        PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP", 0),
        PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP", 0),
        PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185", 0),
        PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325", 0),
        PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326", 0),
        PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP", 0),
        PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax", 0),
}

Definition at line 1696 of file tlan.c.

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