tg3.h File Reference

#include "stdint.h"

Go to the source code of this file.

Data Structures

struct tg3_tx_buffer_desc

struct tg3_rx_buffer_desc

struct tg3_ext_rx_buffer_desc

struct tg3_internal_buffer_desc

struct tg3_hw_status

struct tg3_stat64_t

struct tg3_hw_stats

struct tg3_config_info

struct tg3_link_config

struct tg3_bufmgr_config

struct tg3

Defines

#define ADVERTISED_10baseT_Half   (1 << 0)

#define ADVERTISED_10baseT_Full   (1 << 1)

#define ADVERTISED_100baseT_Half   (1 << 2)

#define ADVERTISED_100baseT_Full   (1 << 3)

#define ADVERTISED_1000baseT_Half   (1 << 4)

#define ADVERTISED_1000baseT_Full   (1 << 5)

#define ADVERTISED_Autoneg   (1 << 6)

#define ADVERTISED_TP   (1 << 7)

#define ADVERTISED_AUI   (1 << 8)

#define ADVERTISED_MII   (1 << 9)

#define ADVERTISED_FIBRE   (1 << 10)

#define ADVERTISED_BNC   (1 << 11)

#define SPEED_10   0

#define SPEED_100   1

#define SPEED_1000   2

#define SPEED_INVALID   3

#define DUPLEX_HALF   0x00

#define DUPLEX_FULL   0x01

#define DUPLEX_INVALID   0x02

#define PORT_TP   0x00

#define PORT_AUI   0x01

#define PORT_MII   0x02

#define PORT_FIBRE   0x03

#define PORT_BNC   0x04

#define XCVR_INTERNAL   0x00

#define XCVR_EXTERNAL   0x01

#define XCVR_DUMMY1   0x02

#define XCVR_DUMMY2   0x03

#define XCVR_DUMMY3   0x04

#define AUTONEG_DISABLE   0x00

#define AUTONEG_ENABLE   0x01

#define WAKE_PHY   (1 << 0)

#define WAKE_UCAST   (1 << 1)

#define WAKE_MCAST   (1 << 2)

#define WAKE_BCAST   (1 << 3)

#define WAKE_ARP   (1 << 4)

#define WAKE_MAGIC   (1 << 5)

#define WAKE_MAGICSECURE   (1 << 6)

#define TG3_64BIT_REG_HIGH   0x00UL

#define TG3_64BIT_REG_LOW   0x04UL

#define TG3_BDINFO_HOST_ADDR   0x0UL

#define TG3_BDINFO_MAXLEN_FLAGS   0x8UL

#define BDINFO_FLAGS_USE_EXT_RECV   0x00000001

#define BDINFO_FLAGS_DISABLED   0x00000002

#define BDINFO_FLAGS_MAXLEN_MASK   0xffff0000

#define BDINFO_FLAGS_MAXLEN_SHIFT   16

#define TG3_BDINFO_NIC_ADDR   0xcUL

#define TG3_BDINFO_SIZE   0x10UL

#define RX_COPY_THRESHOLD   256

#define RX_STD_MAX_SIZE   1536

#define RX_STD_MAX_SIZE_5705   512

#define RX_JUMBO_MAX_SIZE   0xdeadbeef

#define TG3PCI_VENDOR   0x00000000

#define TG3PCI_VENDOR_BROADCOM   0x14e4

#define TG3PCI_DEVICE   0x00000002

#define TG3PCI_DEVICE_TIGON3_1   0x1644

#define TG3PCI_DEVICE_TIGON3_2   0x1645

#define TG3PCI_DEVICE_TIGON3_3   0x1646

#define TG3PCI_DEVICE_TIGON3_4   0x1647

#define TG3PCI_COMMAND   0x00000004

#define TG3PCI_STATUS   0x00000006

#define TG3PCI_CCREVID   0x00000008

#define TG3PCI_CACHELINESZ   0x0000000c

#define TG3PCI_LATTIMER   0x0000000d

#define TG3PCI_HEADERTYPE   0x0000000e

#define TG3PCI_BIST   0x0000000f

#define TG3PCI_BASE0_LOW   0x00000010

#define TG3PCI_BASE0_HIGH   0x00000014

#define TG3PCI_SUBSYSVENID   0x0000002c

#define TG3PCI_SUBSYSID   0x0000002e

#define TG3PCI_ROMADDR   0x00000030

#define TG3PCI_CAPLIST   0x00000034

#define TG3PCI_IRQ_LINE   0x0000003c

#define TG3PCI_IRQ_PIN   0x0000003d

#define TG3PCI_MIN_GNT   0x0000003e

#define TG3PCI_MAX_LAT   0x0000003f

#define TG3PCI_X_CAPS   0x00000040

#define PCIX_CAPS_RELAXED_ORDERING   0x00020000

#define PCIX_CAPS_SPLIT_MASK   0x00700000

#define PCIX_CAPS_SPLIT_SHIFT   20

#define PCIX_CAPS_BURST_MASK   0x000c0000

#define PCIX_CAPS_BURST_SHIFT   18

#define PCIX_CAPS_MAX_BURST_CPIOB   2

#define TG3PCI_PM_CAP_PTR   0x00000041

#define TG3PCI_X_COMMAND   0x00000042

#define TG3PCI_X_STATUS   0x00000044

#define TG3PCI_PM_CAP_ID   0x00000048

#define TG3PCI_VPD_CAP_PTR   0x00000049

#define TG3PCI_PM_CAPS   0x0000004a

#define TG3PCI_PM_CTRL_STAT   0x0000004c

#define TG3PCI_BR_SUPP_EXT   0x0000004e

#define TG3PCI_PM_DATA   0x0000004f

#define TG3PCI_VPD_CAP_ID   0x00000050

#define TG3PCI_MSI_CAP_PTR   0x00000051

#define TG3PCI_VPD_ADDR_FLAG   0x00000052

#define VPD_ADDR_FLAG_WRITE   0x00008000

#define TG3PCI_VPD_DATA   0x00000054

#define TG3PCI_MSI_CAP_ID   0x00000058

#define TG3PCI_NXT_CAP_PTR   0x00000059

#define TG3PCI_MSI_CTRL   0x0000005a

#define TG3PCI_MSI_ADDR_LOW   0x0000005c

#define TG3PCI_MSI_ADDR_HIGH   0x00000060

#define TG3PCI_MSI_DATA   0x00000064

#define TG3PCI_MISC_HOST_CTRL   0x00000068

#define MISC_HOST_CTRL_CLEAR_INT   0x00000001

#define MISC_HOST_CTRL_MASK_PCI_INT   0x00000002

#define MISC_HOST_CTRL_BYTE_SWAP   0x00000004

#define MISC_HOST_CTRL_WORD_SWAP   0x00000008

#define MISC_HOST_CTRL_PCISTATE_RW   0x00000010

#define MISC_HOST_CTRL_CLKREG_RW   0x00000020

#define MISC_HOST_CTRL_REGWORD_SWAP   0x00000040

#define MISC_HOST_CTRL_INDIR_ACCESS   0x00000080

#define MISC_HOST_CTRL_IRQ_MASK_MODE   0x00000100

#define MISC_HOST_CTRL_TAGGED_STATUS   0x00000200

#define MISC_HOST_CTRL_CHIPREV   0xffff0000

#define MISC_HOST_CTRL_CHIPREV_SHIFT   16

#define GET_CHIP_REV_ID(MISC_HOST_CTRL)

#define CHIPREV_ID_5700_A0   0x7000

#define CHIPREV_ID_5700_A1   0x7001

#define CHIPREV_ID_5700_B0   0x7100

#define CHIPREV_ID_5700_B1   0x7101

#define CHIPREV_ID_5700_B3   0x7102

#define CHIPREV_ID_5700_ALTIMA   0x7104

#define CHIPREV_ID_5700_C0   0x7200

#define CHIPREV_ID_5701_A0   0x0000

#define CHIPREV_ID_5701_B0   0x0100

#define CHIPREV_ID_5701_B2   0x0102

#define CHIPREV_ID_5701_B5   0x0105

#define CHIPREV_ID_5703_A0   0x1000

#define CHIPREV_ID_5703_A1   0x1001

#define CHIPREV_ID_5703_A2   0x1002

#define CHIPREV_ID_5703_A3   0x1003

#define CHIPREV_ID_5704_A0   0x2000

#define CHIPREV_ID_5704_A1   0x2001

#define CHIPREV_ID_5704_A2   0x2002

#define CHIPREV_ID_5705_A0   0x3000

#define CHIPREV_ID_5705_A1   0x3001

#define CHIPREV_ID_5705_A2   0x3002

#define CHIPREV_ID_5705_A3   0x3003

#define CHIPREV_ID_5721   0x4101

#define CHIPREV_ID_5750_A0   0x4000

#define CHIPREV_ID_5750_A1   0x4001

#define CHIPREV_ID_5750_A3   0x4003

#define GET_ASIC_REV(CHIP_REV_ID)   ((CHIP_REV_ID) >> 12)

#define ASIC_REV_5700   0x07

#define ASIC_REV_5701   0x00

#define ASIC_REV_5703   0x01

#define ASIC_REV_5704   0x02

#define ASIC_REV_5705   0x03

#define ASIC_REV_5750   0x04

#define ASIC_REV_5787   0x0b

#define GET_CHIP_REV(CHIP_REV_ID)   ((CHIP_REV_ID) >> 8)

#define CHIPREV_5700_AX   0x70

#define CHIPREV_5700_BX   0x71

#define CHIPREV_5700_CX   0x72

#define CHIPREV_5701_AX   0x00

#define GET_METAL_REV(CHIP_REV_ID)   ((CHIP_REV_ID) & 0xff)

#define METAL_REV_A0   0x00

#define METAL_REV_A1   0x01

#define METAL_REV_B0   0x00

#define METAL_REV_B1   0x01

#define METAL_REV_B2   0x02

#define TG3PCI_DMA_RW_CTRL   0x0000006c

#define DMA_RWCTRL_MIN_DMA   0x000000ff

#define DMA_RWCTRL_MIN_DMA_SHIFT   0

#define DMA_RWCTRL_READ_BNDRY_MASK   0x00000700

#define DMA_RWCTRL_READ_BNDRY_DISAB   0x00000000

#define DMA_RWCTRL_READ_BNDRY_16   0x00000100

#define DMA_RWCTRL_READ_BNDRY_32   0x00000200

#define DMA_RWCTRL_READ_BNDRY_64   0x00000300

#define DMA_RWCTRL_READ_BNDRY_128   0x00000400

#define DMA_RWCTRL_READ_BNDRY_256   0x00000500

#define DMA_RWCTRL_READ_BNDRY_512   0x00000600

#define DMA_RWCTRL_READ_BNDRY_1024   0x00000700

#define DMA_RWCTRL_WRITE_BNDRY_MASK   0x00003800

#define DMA_RWCTRL_WRITE_BNDRY_DISAB   0x00000000

#define DMA_RWCTRL_WRITE_BNDRY_16   0x00000800

#define DMA_RWCTRL_WRITE_BNDRY_32   0x00001000

#define DMA_RWCTRL_WRITE_BNDRY_64   0x00001800

#define DMA_RWCTRL_WRITE_BNDRY_128   0x00002000

#define DMA_RWCTRL_WRITE_BNDRY_256   0x00002800

#define DMA_RWCTRL_WRITE_BNDRY_512   0x00003000

#define DMA_RWCTRL_WRITE_BNDRY_1024   0x00003800

#define DMA_RWCTRL_ONE_DMA   0x00004000

#define DMA_RWCTRL_READ_WATER   0x00070000

#define DMA_RWCTRL_READ_WATER_SHIFT   16

#define DMA_RWCTRL_WRITE_WATER   0x00380000

#define DMA_RWCTRL_WRITE_WATER_SHIFT   19

#define DMA_RWCTRL_USE_MEM_READ_MULT   0x00400000

#define DMA_RWCTRL_ASSERT_ALL_BE   0x00800000

#define DMA_RWCTRL_PCI_READ_CMD   0x0f000000

#define DMA_RWCTRL_PCI_READ_CMD_SHIFT   24

#define DMA_RWCTRL_PCI_WRITE_CMD   0xf0000000

#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT   28

#define TG3PCI_PCISTATE   0x00000070

#define PCISTATE_FORCE_RESET   0x00000001

#define PCISTATE_INT_NOT_ACTIVE   0x00000002

#define PCISTATE_CONV_PCI_MODE   0x00000004

#define PCISTATE_BUS_SPEED_HIGH   0x00000008

#define PCISTATE_BUS_32BIT   0x00000010

#define PCISTATE_ROM_ENABLE   0x00000020

#define PCISTATE_ROM_RETRY_ENABLE   0x00000040

#define PCISTATE_FLAT_VIEW   0x00000100

#define PCISTATE_RETRY_SAME_DMA   0x00002000

#define TG3PCI_CLOCK_CTRL   0x00000074

#define CLOCK_CTRL_CORECLK_DISABLE   0x00000200

#define CLOCK_CTRL_RXCLK_DISABLE   0x00000400

#define CLOCK_CTRL_TXCLK_DISABLE   0x00000800

#define CLOCK_CTRL_ALTCLK   0x00001000

#define CLOCK_CTRL_PWRDOWN_PLL133   0x00008000

#define CLOCK_CTRL_44MHZ_CORE   0x00040000

#define CLOCK_CTRL_625_CORE   0x00100000

#define CLOCK_CTRL_FORCE_CLKRUN   0x00200000

#define CLOCK_CTRL_CLKRUN_OENABLE   0x00400000

#define CLOCK_CTRL_DELAY_PCI_GRANT   0x80000000

#define TG3PCI_REG_BASE_ADDR   0x00000078

#define TG3PCI_MEM_WIN_BASE_ADDR   0x0000007c

#define TG3PCI_REG_DATA   0x00000080

#define TG3PCI_MEM_WIN_DATA   0x00000084

#define TG3PCI_MODE_CTRL   0x00000088

#define TG3PCI_MISC_CFG   0x0000008c

#define TG3PCI_MISC_LOCAL_CTRL   0x00000090

#define TG3PCI_STD_RING_PROD_IDX   0x00000098

#define TG3PCI_RCV_RET_RING_CON_IDX   0x000000a0

#define TG3PCI_SND_PROD_IDX   0x000000a8

#define MAILBOX_INTERRUPT_0   0x00000200

#define MAILBOX_INTERRUPT_1   0x00000208

#define MAILBOX_INTERRUPT_2   0x00000210

#define MAILBOX_INTERRUPT_3   0x00000218

#define MAILBOX_GENERAL_0   0x00000220

#define MAILBOX_GENERAL_1   0x00000228

#define MAILBOX_GENERAL_2   0x00000230

#define MAILBOX_GENERAL_3   0x00000238

#define MAILBOX_GENERAL_4   0x00000240

#define MAILBOX_GENERAL_5   0x00000248

#define MAILBOX_GENERAL_6   0x00000250

#define MAILBOX_GENERAL_7   0x00000258

#define MAILBOX_RELOAD_STAT   0x00000260

#define MAILBOX_RCV_STD_PROD_IDX   0x00000268

#define MAILBOX_RCV_JUMBO_PROD_IDX   0x00000270

#define MAILBOX_RCV_MINI_PROD_IDX   0x00000278

#define MAILBOX_RCVRET_CON_IDX_0   0x00000280

#define MAILBOX_RCVRET_CON_IDX_1   0x00000288

#define MAILBOX_RCVRET_CON_IDX_2   0x00000290

#define MAILBOX_RCVRET_CON_IDX_3   0x00000298

#define MAILBOX_RCVRET_CON_IDX_4   0x000002a0

#define MAILBOX_RCVRET_CON_IDX_5   0x000002a8

#define MAILBOX_RCVRET_CON_IDX_6   0x000002b0

#define MAILBOX_RCVRET_CON_IDX_7   0x000002b8

#define MAILBOX_RCVRET_CON_IDX_8   0x000002c0

#define MAILBOX_RCVRET_CON_IDX_9   0x000002c8

#define MAILBOX_RCVRET_CON_IDX_10   0x000002d0

#define MAILBOX_RCVRET_CON_IDX_11   0x000002d8

#define MAILBOX_RCVRET_CON_IDX_12   0x000002e0

#define MAILBOX_RCVRET_CON_IDX_13   0x000002e8

#define MAILBOX_RCVRET_CON_IDX_14   0x000002f0

#define MAILBOX_RCVRET_CON_IDX_15   0x000002f8

#define MAILBOX_SNDHOST_PROD_IDX_0   0x00000300

#define MAILBOX_SNDHOST_PROD_IDX_1   0x00000308

#define MAILBOX_SNDHOST_PROD_IDX_2   0x00000310

#define MAILBOX_SNDHOST_PROD_IDX_3   0x00000318

#define MAILBOX_SNDHOST_PROD_IDX_4   0x00000320

#define MAILBOX_SNDHOST_PROD_IDX_5   0x00000328

#define MAILBOX_SNDHOST_PROD_IDX_6   0x00000330

#define MAILBOX_SNDHOST_PROD_IDX_7   0x00000338

#define MAILBOX_SNDHOST_PROD_IDX_8   0x00000340

#define MAILBOX_SNDHOST_PROD_IDX_9   0x00000348

#define MAILBOX_SNDHOST_PROD_IDX_10   0x00000350

#define MAILBOX_SNDHOST_PROD_IDX_11   0x00000358

#define MAILBOX_SNDHOST_PROD_IDX_12   0x00000360

#define MAILBOX_SNDHOST_PROD_IDX_13   0x00000368

#define MAILBOX_SNDHOST_PROD_IDX_14   0x00000370

#define MAILBOX_SNDHOST_PROD_IDX_15   0x00000378

#define MAILBOX_SNDNIC_PROD_IDX_0   0x00000380

#define MAILBOX_SNDNIC_PROD_IDX_1   0x00000388

#define MAILBOX_SNDNIC_PROD_IDX_2   0x00000390

#define MAILBOX_SNDNIC_PROD_IDX_3   0x00000398

#define MAILBOX_SNDNIC_PROD_IDX_4   0x000003a0

#define MAILBOX_SNDNIC_PROD_IDX_5   0x000003a8

#define MAILBOX_SNDNIC_PROD_IDX_6   0x000003b0

#define MAILBOX_SNDNIC_PROD_IDX_7   0x000003b8

#define MAILBOX_SNDNIC_PROD_IDX_8   0x000003c0

#define MAILBOX_SNDNIC_PROD_IDX_9   0x000003c8

#define MAILBOX_SNDNIC_PROD_IDX_10   0x000003d0

#define MAILBOX_SNDNIC_PROD_IDX_11   0x000003d8

#define MAILBOX_SNDNIC_PROD_IDX_12   0x000003e0

#define MAILBOX_SNDNIC_PROD_IDX_13   0x000003e8

#define MAILBOX_SNDNIC_PROD_IDX_14   0x000003f0

#define MAILBOX_SNDNIC_PROD_IDX_15   0x000003f8

#define MAC_MODE   0x00000400

#define MAC_MODE_RESET   0x00000001

#define MAC_MODE_HALF_DUPLEX   0x00000002

#define MAC_MODE_PORT_MODE_MASK   0x0000000c

#define MAC_MODE_PORT_MODE_TBI   0x0000000c

#define MAC_MODE_PORT_MODE_GMII   0x00000008

#define MAC_MODE_PORT_MODE_MII   0x00000004

#define MAC_MODE_PORT_MODE_NONE   0x00000000

#define MAC_MODE_PORT_INT_LPBACK   0x00000010

#define MAC_MODE_TAGGED_MAC_CTRL   0x00000080

#define MAC_MODE_TX_BURSTING   0x00000100

#define MAC_MODE_MAX_DEFER   0x00000200

#define MAC_MODE_LINK_POLARITY   0x00000400

#define MAC_MODE_RXSTAT_ENABLE   0x00000800

#define MAC_MODE_RXSTAT_CLEAR   0x00001000

#define MAC_MODE_RXSTAT_FLUSH   0x00002000

#define MAC_MODE_TXSTAT_ENABLE   0x00004000

#define MAC_MODE_TXSTAT_CLEAR   0x00008000

#define MAC_MODE_TXSTAT_FLUSH   0x00010000

#define MAC_MODE_SEND_CONFIGS   0x00020000

#define MAC_MODE_MAGIC_PKT_ENABLE   0x00040000

#define MAC_MODE_ACPI_ENABLE   0x00080000

#define MAC_MODE_MIP_ENABLE   0x00100000

#define MAC_MODE_TDE_ENABLE   0x00200000

#define MAC_MODE_RDE_ENABLE   0x00400000

#define MAC_MODE_FHDE_ENABLE   0x00800000

#define MAC_STATUS   0x00000404

#define MAC_STATUS_PCS_SYNCED   0x00000001

#define MAC_STATUS_SIGNAL_DET   0x00000002

#define MAC_STATUS_RCVD_CFG   0x00000004

#define MAC_STATUS_CFG_CHANGED   0x00000008

#define MAC_STATUS_SYNC_CHANGED   0x00000010

#define MAC_STATUS_PORT_DEC_ERR   0x00000400

#define MAC_STATUS_LNKSTATE_CHANGED   0x00001000

#define MAC_STATUS_MI_COMPLETION   0x00400000

#define MAC_STATUS_MI_INTERRUPT   0x00800000

#define MAC_STATUS_AP_ERROR   0x01000000

#define MAC_STATUS_ODI_ERROR   0x02000000

#define MAC_STATUS_RXSTAT_OVERRUN   0x04000000

#define MAC_STATUS_TXSTAT_OVERRUN   0x08000000

#define MAC_EVENT   0x00000408

#define MAC_EVENT_PORT_DECODE_ERR   0x00000400

#define MAC_EVENT_LNKSTATE_CHANGED   0x00001000

#define MAC_EVENT_MI_COMPLETION   0x00400000

#define MAC_EVENT_MI_INTERRUPT   0x00800000

#define MAC_EVENT_AP_ERROR   0x01000000

#define MAC_EVENT_ODI_ERROR   0x02000000

#define MAC_EVENT_RXSTAT_OVERRUN   0x04000000

#define MAC_EVENT_TXSTAT_OVERRUN   0x08000000

#define MAC_LED_CTRL   0x0000040c

#define LED_CTRL_LNKLED_OVERRIDE   0x00000001

#define LED_CTRL_1000MBPS_ON   0x00000002

#define LED_CTRL_100MBPS_ON   0x00000004

#define LED_CTRL_10MBPS_ON   0x00000008

#define LED_CTRL_TRAFFIC_OVERRIDE   0x00000010

#define LED_CTRL_TRAFFIC_BLINK   0x00000020

#define LED_CTRL_TRAFFIC_LED   0x00000040

#define LED_CTRL_1000MBPS_STATUS   0x00000080

#define LED_CTRL_100MBPS_STATUS   0x00000100

#define LED_CTRL_10MBPS_STATUS   0x00000200

#define LED_CTRL_TRAFFIC_STATUS   0x00000400

#define LED_CTRL_MAC_MODE   0x00000000

#define LED_CTRL_PHY_MODE_1   0x00000800

#define LED_CTRL_PHY_MODE_2   0x00001000

#define LED_CTRL_BLINK_RATE_MASK   0x7ff80000

#define LED_CTRL_BLINK_RATE_SHIFT   19

#define LED_CTRL_BLINK_PER_OVERRIDE   0x00080000

#define LED_CTRL_BLINK_RATE_OVERRIDE   0x80000000

#define MAC_ADDR_0_HIGH   0x00000410

#define MAC_ADDR_0_LOW   0x00000414

#define MAC_ADDR_1_HIGH   0x00000418

#define MAC_ADDR_1_LOW   0x0000041c

#define MAC_ADDR_2_HIGH   0x00000420

#define MAC_ADDR_2_LOW   0x00000424

#define MAC_ADDR_3_HIGH   0x00000428

#define MAC_ADDR_3_LOW   0x0000042c

#define MAC_ACPI_MBUF_PTR   0x00000430

#define MAC_ACPI_LEN_OFFSET   0x00000434

#define ACPI_LENOFF_LEN_MASK   0x0000ffff

#define ACPI_LENOFF_LEN_SHIFT   0

#define ACPI_LENOFF_OFF_MASK   0x0fff0000

#define ACPI_LENOFF_OFF_SHIFT   16

#define MAC_TX_BACKOFF_SEED   0x00000438

#define TX_BACKOFF_SEED_MASK   0x000003ff

#define MAC_RX_MTU_SIZE   0x0000043c

#define RX_MTU_SIZE_MASK   0x0000ffff

#define MAC_PCS_TEST   0x00000440

#define PCS_TEST_PATTERN_MASK   0x000fffff

#define PCS_TEST_PATTERN_SHIFT   0

#define PCS_TEST_ENABLE   0x00100000

#define MAC_TX_AUTO_NEG   0x00000444

#define TX_AUTO_NEG_MASK   0x0000ffff

#define TX_AUTO_NEG_SHIFT   0

#define MAC_RX_AUTO_NEG   0x00000448

#define RX_AUTO_NEG_MASK   0x0000ffff

#define RX_AUTO_NEG_SHIFT   0

#define MAC_MI_COM   0x0000044c

#define MI_COM_CMD_MASK   0x0c000000

#define MI_COM_CMD_WRITE   0x04000000

#define MI_COM_CMD_READ   0x08000000

#define MI_COM_READ_FAILED   0x10000000

#define MI_COM_START   0x20000000

#define MI_COM_BUSY   0x20000000

#define MI_COM_PHY_ADDR_MASK   0x03e00000

#define MI_COM_PHY_ADDR_SHIFT   21

#define MI_COM_REG_ADDR_MASK   0x001f0000

#define MI_COM_REG_ADDR_SHIFT   16

#define MI_COM_DATA_MASK   0x0000ffff

#define MAC_MI_STAT   0x00000450

#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB   0x00000001

#define MAC_MI_MODE   0x00000454

#define MAC_MI_MODE_CLK_10MHZ   0x00000001

#define MAC_MI_MODE_SHORT_PREAMBLE   0x00000002

#define MAC_MI_MODE_AUTO_POLL   0x00000010

#define MAC_MI_MODE_CORE_CLK_62MHZ   0x00008000

#define MAC_MI_MODE_BASE   0x000c0000

#define MAC_AUTO_POLL_STATUS   0x00000458

#define MAC_AUTO_POLL_ERROR   0x00000001

#define MAC_TX_MODE   0x0000045c

#define TX_MODE_RESET   0x00000001

#define TX_MODE_ENABLE   0x00000002

#define TX_MODE_FLOW_CTRL_ENABLE   0x00000010

#define TX_MODE_BIG_BCKOFF_ENABLE   0x00000020

#define TX_MODE_LONG_PAUSE_ENABLE   0x00000040

#define MAC_TX_STATUS   0x00000460

#define TX_STATUS_XOFFED   0x00000001

#define TX_STATUS_SENT_XOFF   0x00000002

#define TX_STATUS_SENT_XON   0x00000004

#define TX_STATUS_LINK_UP   0x00000008

#define TX_STATUS_ODI_UNDERRUN   0x00000010

#define TX_STATUS_ODI_OVERRUN   0x00000020

#define MAC_TX_LENGTHS   0x00000464

#define TX_LENGTHS_SLOT_TIME_MASK   0x000000ff

#define TX_LENGTHS_SLOT_TIME_SHIFT   0

#define TX_LENGTHS_IPG_MASK   0x00000f00

#define TX_LENGTHS_IPG_SHIFT   8

#define TX_LENGTHS_IPG_CRS_MASK   0x00003000

#define TX_LENGTHS_IPG_CRS_SHIFT   12

#define MAC_RX_MODE   0x00000468

#define RX_MODE_RESET   0x00000001

#define RX_MODE_ENABLE   0x00000002

#define RX_MODE_FLOW_CTRL_ENABLE   0x00000004

#define RX_MODE_KEEP_MAC_CTRL   0x00000008

#define RX_MODE_KEEP_PAUSE   0x00000010

#define RX_MODE_ACCEPT_OVERSIZED   0x00000020

#define RX_MODE_ACCEPT_RUNTS   0x00000040

#define RX_MODE_LEN_CHECK   0x00000080

#define RX_MODE_PROMISC   0x00000100

#define RX_MODE_NO_CRC_CHECK   0x00000200

#define RX_MODE_KEEP_VLAN_TAG   0x00000400

#define MAC_RX_STATUS   0x0000046c

#define RX_STATUS_REMOTE_TX_XOFFED   0x00000001

#define RX_STATUS_XOFF_RCVD   0x00000002

#define RX_STATUS_XON_RCVD   0x00000004

#define MAC_HASH_REG_0   0x00000470

#define MAC_HASH_REG_1   0x00000474

#define MAC_HASH_REG_2   0x00000478

#define MAC_HASH_REG_3   0x0000047c

#define MAC_RCV_RULE_0   0x00000480

#define MAC_RCV_VALUE_0   0x00000484

#define MAC_RCV_RULE_1   0x00000488

#define MAC_RCV_VALUE_1   0x0000048c

#define MAC_RCV_RULE_2   0x00000490

#define MAC_RCV_VALUE_2   0x00000494

#define MAC_RCV_RULE_3   0x00000498

#define MAC_RCV_VALUE_3   0x0000049c

#define MAC_RCV_RULE_4   0x000004a0

#define MAC_RCV_VALUE_4   0x000004a4

#define MAC_RCV_RULE_5   0x000004a8

#define MAC_RCV_VALUE_5   0x000004ac

#define MAC_RCV_RULE_6   0x000004b0

#define MAC_RCV_VALUE_6   0x000004b4

#define MAC_RCV_RULE_7   0x000004b8

#define MAC_RCV_VALUE_7   0x000004bc

#define MAC_RCV_RULE_8   0x000004c0

#define MAC_RCV_VALUE_8   0x000004c4

#define MAC_RCV_RULE_9   0x000004c8

#define MAC_RCV_VALUE_9   0x000004cc

#define MAC_RCV_RULE_10   0x000004d0

#define MAC_RCV_VALUE_10   0x000004d4

#define MAC_RCV_RULE_11   0x000004d8

#define MAC_RCV_VALUE_11   0x000004dc

#define MAC_RCV_RULE_12   0x000004e0

#define MAC_RCV_VALUE_12   0x000004e4

#define MAC_RCV_RULE_13   0x000004e8

#define MAC_RCV_VALUE_13   0x000004ec

#define MAC_RCV_RULE_14   0x000004f0

#define MAC_RCV_VALUE_14   0x000004f4

#define MAC_RCV_RULE_15   0x000004f8

#define MAC_RCV_VALUE_15   0x000004fc

#define RCV_RULE_DISABLE_MASK   0x7fffffff

#define MAC_RCV_RULE_CFG   0x00000500

#define RCV_RULE_CFG_DEFAULT_CLASS   0x00000008

#define MAC_LOW_WMARK_MAX_RX_FRAME   0x00000504

#define MAC_HASHREGU_0   0x00000520

#define MAC_HASHREGU_1   0x00000524

#define MAC_HASHREGU_2   0x00000528

#define MAC_HASHREGU_3   0x0000052c

#define MAC_EXTADDR_0_HIGH   0x00000530

#define MAC_EXTADDR_0_LOW   0x00000534

#define MAC_EXTADDR_1_HIGH   0x00000538

#define MAC_EXTADDR_1_LOW   0x0000053c

#define MAC_EXTADDR_2_HIGH   0x00000540

#define MAC_EXTADDR_2_LOW   0x00000544

#define MAC_EXTADDR_3_HIGH   0x00000548

#define MAC_EXTADDR_3_LOW   0x0000054c

#define MAC_EXTADDR_4_HIGH   0x00000550

#define MAC_EXTADDR_4_LOW   0x00000554

#define MAC_EXTADDR_5_HIGH   0x00000558

#define MAC_EXTADDR_5_LOW   0x0000055c

#define MAC_EXTADDR_6_HIGH   0x00000560

#define MAC_EXTADDR_6_LOW   0x00000564

#define MAC_EXTADDR_7_HIGH   0x00000568

#define MAC_EXTADDR_7_LOW   0x0000056c

#define MAC_EXTADDR_8_HIGH   0x00000570

#define MAC_EXTADDR_8_LOW   0x00000574

#define MAC_EXTADDR_9_HIGH   0x00000578

#define MAC_EXTADDR_9_LOW   0x0000057c

#define MAC_EXTADDR_10_HIGH   0x00000580

#define MAC_EXTADDR_10_LOW   0x00000584

#define MAC_EXTADDR_11_HIGH   0x00000588

#define MAC_EXTADDR_11_LOW   0x0000058c

#define MAC_SERDES_CFG   0x00000590

#define MAC_SERDES_STAT   0x00000594

#define MAC_TX_MAC_STATE_BASE   0x00000600

#define MAC_RX_MAC_STATE_BASE   0x00000610

#define MAC_TX_STATS_OCTETS   0x00000800

#define MAC_TX_STATS_RESV1   0x00000804

#define MAC_TX_STATS_COLLISIONS   0x00000808

#define MAC_TX_STATS_XON_SENT   0x0000080c

#define MAC_TX_STATS_XOFF_SENT   0x00000810

#define MAC_TX_STATS_RESV2   0x00000814

#define MAC_TX_STATS_MAC_ERRORS   0x00000818

#define MAC_TX_STATS_SINGLE_COLLISIONS   0x0000081c

#define MAC_TX_STATS_MULT_COLLISIONS   0x00000820

#define MAC_TX_STATS_DEFERRED   0x00000824

#define MAC_TX_STATS_RESV3   0x00000828

#define MAC_TX_STATS_EXCESSIVE_COL   0x0000082c

#define MAC_TX_STATS_LATE_COL   0x00000830

#define MAC_TX_STATS_RESV4_1   0x00000834

#define MAC_TX_STATS_RESV4_2   0x00000838

#define MAC_TX_STATS_RESV4_3   0x0000083c

#define MAC_TX_STATS_RESV4_4   0x00000840

#define MAC_TX_STATS_RESV4_5   0x00000844

#define MAC_TX_STATS_RESV4_6   0x00000848

#define MAC_TX_STATS_RESV4_7   0x0000084c

#define MAC_TX_STATS_RESV4_8   0x00000850

#define MAC_TX_STATS_RESV4_9   0x00000854

#define MAC_TX_STATS_RESV4_10   0x00000858

#define MAC_TX_STATS_RESV4_11   0x0000085c

#define MAC_TX_STATS_RESV4_12   0x00000860

#define MAC_TX_STATS_RESV4_13   0x00000864

#define MAC_TX_STATS_RESV4_14   0x00000868

#define MAC_TX_STATS_UCAST   0x0000086c

#define MAC_TX_STATS_MCAST   0x00000870

#define MAC_TX_STATS_BCAST   0x00000874

#define MAC_TX_STATS_RESV5_1   0x00000878

#define MAC_TX_STATS_RESV5_2   0x0000087c

#define MAC_RX_STATS_OCTETS   0x00000880

#define MAC_RX_STATS_RESV1   0x00000884

#define MAC_RX_STATS_FRAGMENTS   0x00000888

#define MAC_RX_STATS_UCAST   0x0000088c

#define MAC_RX_STATS_MCAST   0x00000890

#define MAC_RX_STATS_BCAST   0x00000894

#define MAC_RX_STATS_FCS_ERRORS   0x00000898

#define MAC_RX_STATS_ALIGN_ERRORS   0x0000089c

#define MAC_RX_STATS_XON_PAUSE_RECVD   0x000008a0

#define MAC_RX_STATS_XOFF_PAUSE_RECVD   0x000008a4

#define MAC_RX_STATS_MAC_CTRL_RECVD   0x000008a8

#define MAC_RX_STATS_XOFF_ENTERED   0x000008ac

#define MAC_RX_STATS_FRAME_TOO_LONG   0x000008b0

#define MAC_RX_STATS_JABBERS   0x000008b4

#define MAC_RX_STATS_UNDERSIZE   0x000008b8

#define SNDDATAI_MODE   0x00000c00

#define SNDDATAI_MODE_RESET   0x00000001

#define SNDDATAI_MODE_ENABLE   0x00000002

#define SNDDATAI_MODE_STAT_OFLOW_ENAB   0x00000004

#define SNDDATAI_STATUS   0x00000c04

#define SNDDATAI_STATUS_STAT_OFLOW   0x00000004

#define SNDDATAI_STATSCTRL   0x00000c08

#define SNDDATAI_SCTRL_ENABLE   0x00000001

#define SNDDATAI_SCTRL_FASTUPD   0x00000002

#define SNDDATAI_SCTRL_CLEAR   0x00000004

#define SNDDATAI_SCTRL_FLUSH   0x00000008

#define SNDDATAI_SCTRL_FORCE_ZERO   0x00000010

#define SNDDATAI_STATSENAB   0x00000c0c

#define SNDDATAI_STATSINCMASK   0x00000c10

#define SNDDATAI_COS_CNT_0   0x00000c80

#define SNDDATAI_COS_CNT_1   0x00000c84

#define SNDDATAI_COS_CNT_2   0x00000c88

#define SNDDATAI_COS_CNT_3   0x00000c8c

#define SNDDATAI_COS_CNT_4   0x00000c90

#define SNDDATAI_COS_CNT_5   0x00000c94

#define SNDDATAI_COS_CNT_6   0x00000c98

#define SNDDATAI_COS_CNT_7   0x00000c9c

#define SNDDATAI_COS_CNT_8   0x00000ca0

#define SNDDATAI_COS_CNT_9   0x00000ca4

#define SNDDATAI_COS_CNT_10   0x00000ca8

#define SNDDATAI_COS_CNT_11   0x00000cac

#define SNDDATAI_COS_CNT_12   0x00000cb0

#define SNDDATAI_COS_CNT_13   0x00000cb4

#define SNDDATAI_COS_CNT_14   0x00000cb8

#define SNDDATAI_COS_CNT_15   0x00000cbc

#define SNDDATAI_DMA_RDQ_FULL_CNT   0x00000cc0

#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT   0x00000cc4

#define SNDDATAI_SDCQ_FULL_CNT   0x00000cc8

#define SNDDATAI_NICRNG_SSND_PIDX_CNT   0x00000ccc

#define SNDDATAI_STATS_UPDATED_CNT   0x00000cd0

#define SNDDATAI_INTERRUPTS_CNT   0x00000cd4

#define SNDDATAI_AVOID_INTERRUPTS_CNT   0x00000cd8

#define SNDDATAI_SND_THRESH_HIT_CNT   0x00000cdc

#define SNDDATAC_MODE   0x00001000

#define SNDDATAC_MODE_RESET   0x00000001

#define SNDDATAC_MODE_ENABLE   0x00000002

#define SNDBDS_MODE   0x00001400

#define SNDBDS_MODE_RESET   0x00000001

#define SNDBDS_MODE_ENABLE   0x00000002

#define SNDBDS_MODE_ATTN_ENABLE   0x00000004

#define SNDBDS_STATUS   0x00001404

#define SNDBDS_STATUS_ERROR_ATTN   0x00000004

#define SNDBDS_HWDIAG   0x00001408

#define SNDBDS_SEL_CON_IDX_0   0x00001440

#define SNDBDS_SEL_CON_IDX_1   0x00001444

#define SNDBDS_SEL_CON_IDX_2   0x00001448

#define SNDBDS_SEL_CON_IDX_3   0x0000144c

#define SNDBDS_SEL_CON_IDX_4   0x00001450

#define SNDBDS_SEL_CON_IDX_5   0x00001454

#define SNDBDS_SEL_CON_IDX_6   0x00001458

#define SNDBDS_SEL_CON_IDX_7   0x0000145c

#define SNDBDS_SEL_CON_IDX_8   0x00001460

#define SNDBDS_SEL_CON_IDX_9   0x00001464

#define SNDBDS_SEL_CON_IDX_10   0x00001468

#define SNDBDS_SEL_CON_IDX_11   0x0000146c

#define SNDBDS_SEL_CON_IDX_12   0x00001470

#define SNDBDS_SEL_CON_IDX_13   0x00001474

#define SNDBDS_SEL_CON_IDX_14   0x00001478

#define SNDBDS_SEL_CON_IDX_15   0x0000147c

#define SNDBDI_MODE   0x00001800

#define SNDBDI_MODE_RESET   0x00000001

#define SNDBDI_MODE_ENABLE   0x00000002

#define SNDBDI_MODE_ATTN_ENABLE   0x00000004

#define SNDBDI_STATUS   0x00001804

#define SNDBDI_STATUS_ERROR_ATTN   0x00000004

#define SNDBDI_IN_PROD_IDX_0   0x00001808

#define SNDBDI_IN_PROD_IDX_1   0x0000180c

#define SNDBDI_IN_PROD_IDX_2   0x00001810

#define SNDBDI_IN_PROD_IDX_3   0x00001814

#define SNDBDI_IN_PROD_IDX_4   0x00001818

#define SNDBDI_IN_PROD_IDX_5   0x0000181c

#define SNDBDI_IN_PROD_IDX_6   0x00001820

#define SNDBDI_IN_PROD_IDX_7   0x00001824

#define SNDBDI_IN_PROD_IDX_8   0x00001828

#define SNDBDI_IN_PROD_IDX_9   0x0000182c

#define SNDBDI_IN_PROD_IDX_10   0x00001830

#define SNDBDI_IN_PROD_IDX_11   0x00001834

#define SNDBDI_IN_PROD_IDX_12   0x00001838

#define SNDBDI_IN_PROD_IDX_13   0x0000183c

#define SNDBDI_IN_PROD_IDX_14   0x00001840

#define SNDBDI_IN_PROD_IDX_15   0x00001844

#define SNDBDC_MODE   0x00001c00

#define SNDBDC_MODE_RESET   0x00000001

#define SNDBDC_MODE_ENABLE   0x00000002

#define SNDBDC_MODE_ATTN_ENABLE   0x00000004

#define RCVLPC_MODE   0x00002000

#define RCVLPC_MODE_RESET   0x00000001

#define RCVLPC_MODE_ENABLE   0x00000002

#define RCVLPC_MODE_CLASS0_ATTN_ENAB   0x00000004

#define RCVLPC_MODE_MAPOOR_AATTN_ENAB   0x00000008

#define RCVLPC_MODE_STAT_OFLOW_ENAB   0x00000010

#define RCVLPC_STATUS   0x00002004

#define RCVLPC_STATUS_CLASS0   0x00000004

#define RCVLPC_STATUS_MAPOOR   0x00000008

#define RCVLPC_STATUS_STAT_OFLOW   0x00000010

#define RCVLPC_LOCK   0x00002008

#define RCVLPC_LOCK_REQ_MASK   0x0000ffff

#define RCVLPC_LOCK_REQ_SHIFT   0

#define RCVLPC_LOCK_GRANT_MASK   0xffff0000

#define RCVLPC_LOCK_GRANT_SHIFT   16

#define RCVLPC_NON_EMPTY_BITS   0x0000200c

#define RCVLPC_NON_EMPTY_BITS_MASK   0x0000ffff

#define RCVLPC_CONFIG   0x00002010

#define RCVLPC_STATSCTRL   0x00002014

#define RCVLPC_STATSCTRL_ENABLE   0x00000001

#define RCVLPC_STATSCTRL_FASTUPD   0x00000002

#define RCVLPC_STATS_ENABLE   0x00002018

#define RCVLPC_STATSENAB_LNGBRST_RFIX   0x00400000

#define RCVLPC_STATS_INCMASK   0x0000201c

#define RCVLPC_SELLST_BASE   0x00002100

#define SELLST_TAIL   0x00000004

#define SELLST_CONT   0x00000008

#define SELLST_UNUSED   0x0000000c

#define RCVLPC_COS_CNTL_BASE   0x00002200

#define RCVLPC_DROP_FILTER_CNT   0x00002240

#define RCVLPC_DMA_WQ_FULL_CNT   0x00002244

#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT   0x00002248

#define RCVLPC_NO_RCV_BD_CNT   0x0000224c

#define RCVLPC_IN_DISCARDS_CNT   0x00002250

#define RCVLPC_IN_ERRORS_CNT   0x00002254

#define RCVLPC_RCV_THRESH_HIT_CNT   0x00002258

#define RCVDBDI_MODE   0x00002400

#define RCVDBDI_MODE_RESET   0x00000001

#define RCVDBDI_MODE_ENABLE   0x00000002

#define RCVDBDI_MODE_JUMBOBD_NEEDED   0x00000004

#define RCVDBDI_MODE_FRM_TOO_BIG   0x00000008

#define RCVDBDI_MODE_INV_RING_SZ   0x00000010

#define RCVDBDI_STATUS   0x00002404

#define RCVDBDI_STATUS_JUMBOBD_NEEDED   0x00000004

#define RCVDBDI_STATUS_FRM_TOO_BIG   0x00000008

#define RCVDBDI_STATUS_INV_RING_SZ   0x00000010

#define RCVDBDI_SPLIT_FRAME_MINSZ   0x00002408

#define RCVDBDI_JUMBO_BD   0x00002440

#define RCVDBDI_STD_BD   0x00002450

#define RCVDBDI_MINI_BD   0x00002460

#define RCVDBDI_JUMBO_CON_IDX   0x00002470

#define RCVDBDI_STD_CON_IDX   0x00002474

#define RCVDBDI_MINI_CON_IDX   0x00002478

#define RCVDBDI_BD_PROD_IDX_0   0x00002480

#define RCVDBDI_BD_PROD_IDX_1   0x00002484

#define RCVDBDI_BD_PROD_IDX_2   0x00002488

#define RCVDBDI_BD_PROD_IDX_3   0x0000248c

#define RCVDBDI_BD_PROD_IDX_4   0x00002490

#define RCVDBDI_BD_PROD_IDX_5   0x00002494

#define RCVDBDI_BD_PROD_IDX_6   0x00002498

#define RCVDBDI_BD_PROD_IDX_7   0x0000249c

#define RCVDBDI_BD_PROD_IDX_8   0x000024a0

#define RCVDBDI_BD_PROD_IDX_9   0x000024a4

#define RCVDBDI_BD_PROD_IDX_10   0x000024a8

#define RCVDBDI_BD_PROD_IDX_11   0x000024ac

#define RCVDBDI_BD_PROD_IDX_12   0x000024b0

#define RCVDBDI_BD_PROD_IDX_13   0x000024b4

#define RCVDBDI_BD_PROD_IDX_14   0x000024b8

#define RCVDBDI_BD_PROD_IDX_15   0x000024bc

#define RCVDBDI_HWDIAG   0x000024c0

#define RCVDCC_MODE   0x00002800

#define RCVDCC_MODE_RESET   0x00000001

#define RCVDCC_MODE_ENABLE   0x00000002

#define RCVDCC_MODE_ATTN_ENABLE   0x00000004

#define RCVBDI_MODE   0x00002c00

#define RCVBDI_MODE_RESET   0x00000001

#define RCVBDI_MODE_ENABLE   0x00000002

#define RCVBDI_MODE_RCB_ATTN_ENAB   0x00000004

#define RCVBDI_STATUS   0x00002c04

#define RCVBDI_STATUS_RCB_ATTN   0x00000004

#define RCVBDI_JUMBO_PROD_IDX   0x00002c08

#define RCVBDI_STD_PROD_IDX   0x00002c0c

#define RCVBDI_MINI_PROD_IDX   0x00002c10

#define RCVBDI_MINI_THRESH   0x00002c14

#define RCVBDI_STD_THRESH   0x00002c18

#define RCVBDI_JUMBO_THRESH   0x00002c1c

#define RCVCC_MODE   0x00003000

#define RCVCC_MODE_RESET   0x00000001

#define RCVCC_MODE_ENABLE   0x00000002

#define RCVCC_MODE_ATTN_ENABLE   0x00000004

#define RCVCC_STATUS   0x00003004

#define RCVCC_STATUS_ERROR_ATTN   0x00000004

#define RCVCC_JUMP_PROD_IDX   0x00003008

#define RCVCC_STD_PROD_IDX   0x0000300c

#define RCVCC_MINI_PROD_IDX   0x00003010

#define RCVLSC_MODE   0x00003400

#define RCVLSC_MODE_RESET   0x00000001

#define RCVLSC_MODE_ENABLE   0x00000002

#define RCVLSC_MODE_ATTN_ENABLE   0x00000004

#define RCVLSC_STATUS   0x00003404

#define RCVLSC_STATUS_ERROR_ATTN   0x00000004

#define MBFREE_MODE   0x00003800

#define MBFREE_MODE_RESET   0x00000001

#define MBFREE_MODE_ENABLE   0x00000002

#define MBFREE_STATUS   0x00003804

#define HOSTCC_MODE   0x00003c00

#define HOSTCC_MODE_RESET   0x00000001

#define HOSTCC_MODE_ENABLE   0x00000002

#define HOSTCC_MODE_ATTN   0x00000004

#define HOSTCC_MODE_NOW   0x00000008

#define HOSTCC_MODE_FULL_STATUS   0x00000000

#define HOSTCC_MODE_64BYTE   0x00000080

#define HOSTCC_MODE_32BYTE   0x00000100

#define HOSTCC_MODE_CLRTICK_RXBD   0x00000200

#define HOSTCC_MODE_CLRTICK_TXBD   0x00000400

#define HOSTCC_MODE_NOINT_ON_NOW   0x00000800

#define HOSTCC_MODE_NOINT_ON_FORCE   0x00001000

#define HOSTCC_STATUS   0x00003c04

#define HOSTCC_STATUS_ERROR_ATTN   0x00000004

#define HOSTCC_RXCOL_TICKS   0x00003c08

#define LOW_RXCOL_TICKS   0x00000032

#define DEFAULT_RXCOL_TICKS   0x00000048

#define HIGH_RXCOL_TICKS   0x00000096

#define HOSTCC_TXCOL_TICKS   0x00003c0c

#define LOW_TXCOL_TICKS   0x00000096

#define DEFAULT_TXCOL_TICKS   0x0000012c

#define HIGH_TXCOL_TICKS   0x00000145

#define HOSTCC_RXMAX_FRAMES   0x00003c10

#define LOW_RXMAX_FRAMES   0x00000005

#define DEFAULT_RXMAX_FRAMES   0x00000008

#define HIGH_RXMAX_FRAMES   0x00000012

#define HOSTCC_TXMAX_FRAMES   0x00003c14

#define LOW_TXMAX_FRAMES   0x00000035

#define DEFAULT_TXMAX_FRAMES   0x0000004b

#define HIGH_TXMAX_FRAMES   0x00000052

#define HOSTCC_RXCOAL_TICK_INT   0x00003c18

#define DEFAULT_RXCOAL_TICK_INT   0x00000019

#define HOSTCC_TXCOAL_TICK_INT   0x00003c1c

#define DEFAULT_TXCOAL_TICK_INT   0x00000019

#define HOSTCC_RXCOAL_MAXF_INT   0x00003c20

#define DEFAULT_RXCOAL_MAXF_INT   0x00000005

#define HOSTCC_TXCOAL_MAXF_INT   0x00003c24

#define DEFAULT_TXCOAL_MAXF_INT   0x00000005

#define HOSTCC_STAT_COAL_TICKS   0x00003c28

#define DEFAULT_STAT_COAL_TICKS   0x000f4240

#define HOSTCC_STATS_BLK_HOST_ADDR   0x00003c30

#define HOSTCC_STATUS_BLK_HOST_ADDR   0x00003c38

#define HOSTCC_STATS_BLK_NIC_ADDR   0x00003c40

#define HOSTCC_STATUS_BLK_NIC_ADDR   0x00003c44

#define HOSTCC_FLOW_ATTN   0x00003c48

#define HOSTCC_JUMBO_CON_IDX   0x00003c50

#define HOSTCC_STD_CON_IDX   0x00003c54

#define HOSTCC_MINI_CON_IDX   0x00003c58

#define HOSTCC_RET_PROD_IDX_0   0x00003c80

#define HOSTCC_RET_PROD_IDX_1   0x00003c84

#define HOSTCC_RET_PROD_IDX_2   0x00003c88

#define HOSTCC_RET_PROD_IDX_3   0x00003c8c

#define HOSTCC_RET_PROD_IDX_4   0x00003c90

#define HOSTCC_RET_PROD_IDX_5   0x00003c94

#define HOSTCC_RET_PROD_IDX_6   0x00003c98

#define HOSTCC_RET_PROD_IDX_7   0x00003c9c

#define HOSTCC_RET_PROD_IDX_8   0x00003ca0

#define HOSTCC_RET_PROD_IDX_9   0x00003ca4

#define HOSTCC_RET_PROD_IDX_10   0x00003ca8

#define HOSTCC_RET_PROD_IDX_11   0x00003cac

#define HOSTCC_RET_PROD_IDX_12   0x00003cb0

#define HOSTCC_RET_PROD_IDX_13   0x00003cb4

#define HOSTCC_RET_PROD_IDX_14   0x00003cb8

#define HOSTCC_RET_PROD_IDX_15   0x00003cbc

#define HOSTCC_SND_CON_IDX_0   0x00003cc0

#define HOSTCC_SND_CON_IDX_1   0x00003cc4

#define HOSTCC_SND_CON_IDX_2   0x00003cc8

#define HOSTCC_SND_CON_IDX_3   0x00003ccc

#define HOSTCC_SND_CON_IDX_4   0x00003cd0

#define HOSTCC_SND_CON_IDX_5   0x00003cd4

#define HOSTCC_SND_CON_IDX_6   0x00003cd8

#define HOSTCC_SND_CON_IDX_7   0x00003cdc

#define HOSTCC_SND_CON_IDX_8   0x00003ce0

#define HOSTCC_SND_CON_IDX_9   0x00003ce4

#define HOSTCC_SND_CON_IDX_10   0x00003ce8

#define HOSTCC_SND_CON_IDX_11   0x00003cec

#define HOSTCC_SND_CON_IDX_12   0x00003cf0

#define HOSTCC_SND_CON_IDX_13   0x00003cf4

#define HOSTCC_SND_CON_IDX_14   0x00003cf8

#define HOSTCC_SND_CON_IDX_15   0x00003cfc

#define MEMARB_MODE   0x00004000

#define MEMARB_MODE_RESET   0x00000001

#define MEMARB_MODE_ENABLE   0x00000002

#define MEMARB_STATUS   0x00004004

#define MEMARB_TRAP_ADDR_LOW   0x00004008

#define MEMARB_TRAP_ADDR_HIGH   0x0000400c

#define BUFMGR_MODE   0x00004400

#define BUFMGR_MODE_RESET   0x00000001

#define BUFMGR_MODE_ENABLE   0x00000002

#define BUFMGR_MODE_ATTN_ENABLE   0x00000004

#define BUFMGR_MODE_BM_TEST   0x00000008

#define BUFMGR_MODE_MBLOW_ATTN_ENAB   0x00000010

#define BUFMGR_STATUS   0x00004404

#define BUFMGR_STATUS_ERROR   0x00000004

#define BUFMGR_STATUS_MBLOW   0x00000010

#define BUFMGR_MB_POOL_ADDR   0x00004408

#define BUFMGR_MB_POOL_SIZE   0x0000440c

#define BUFMGR_MB_RDMA_LOW_WATER   0x00004410

#define DEFAULT_MB_RDMA_LOW_WATER   0x00000050

#define DEFAULT_MB_RDMA_LOW_WATER_5705   0x00000000

#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO   0x00000130

#define BUFMGR_MB_MACRX_LOW_WATER   0x00004414

#define DEFAULT_MB_MACRX_LOW_WATER   0x00000020

#define DEFAULT_MB_MACRX_LOW_WATER_5705   0x00000010

#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO   0x00000098

#define BUFMGR_MB_HIGH_WATER   0x00004418

#define DEFAULT_MB_HIGH_WATER   0x00000060

#define DEFAULT_MB_HIGH_WATER_5705   0x00000060

#define DEFAULT_MB_HIGH_WATER_JUMBO   0x0000017c

#define BUFMGR_RX_MB_ALLOC_REQ   0x0000441c

#define BUFMGR_MB_ALLOC_BIT   0x10000000

#define BUFMGR_RX_MB_ALLOC_RESP   0x00004420

#define BUFMGR_TX_MB_ALLOC_REQ   0x00004424

#define BUFMGR_TX_MB_ALLOC_RESP   0x00004428

#define BUFMGR_DMA_DESC_POOL_ADDR   0x0000442c

#define BUFMGR_DMA_DESC_POOL_SIZE   0x00004430

#define BUFMGR_DMA_LOW_WATER   0x00004434

#define DEFAULT_DMA_LOW_WATER   0x00000005

#define BUFMGR_DMA_HIGH_WATER   0x00004438

#define DEFAULT_DMA_HIGH_WATER   0x0000000a

#define BUFMGR_RX_DMA_ALLOC_REQ   0x0000443c

#define BUFMGR_RX_DMA_ALLOC_RESP   0x00004440

#define BUFMGR_TX_DMA_ALLOC_REQ   0x00004444

#define BUFMGR_TX_DMA_ALLOC_RESP   0x00004448

#define BUFMGR_HWDIAG_0   0x0000444c

#define BUFMGR_HWDIAG_1   0x00004450

#define BUFMGR_HWDIAG_2   0x00004454

#define RDMAC_MODE   0x00004800

#define RDMAC_MODE_RESET   0x00000001

#define RDMAC_MODE_ENABLE   0x00000002

#define RDMAC_MODE_TGTABORT_ENAB   0x00000004

#define RDMAC_MODE_MSTABORT_ENAB   0x00000008

#define RDMAC_MODE_PARITYERR_ENAB   0x00000010

#define RDMAC_MODE_ADDROFLOW_ENAB   0x00000020

#define RDMAC_MODE_FIFOOFLOW_ENAB   0x00000040

#define RDMAC_MODE_FIFOURUN_ENAB   0x00000080

#define RDMAC_MODE_FIFOOREAD_ENAB   0x00000100

#define RDMAC_MODE_LNGREAD_ENAB   0x00000200

#define RDMAC_MODE_SPLIT_ENABLE   0x00000800

#define RDMAC_MODE_SPLIT_RESET   0x00001000

#define RDMAC_MODE_FIFO_SIZE_128   0x00020000

#define RDMAC_MODE_FIFO_LONG_BURST   0x00030000

#define RDMAC_STATUS   0x00004804

#define RDMAC_STATUS_TGTABORT   0x00000004

#define RDMAC_STATUS_MSTABORT   0x00000008

#define RDMAC_STATUS_PARITYERR   0x00000010

#define RDMAC_STATUS_ADDROFLOW   0x00000020

#define RDMAC_STATUS_FIFOOFLOW   0x00000040

#define RDMAC_STATUS_FIFOURUN   0x00000080

#define RDMAC_STATUS_FIFOOREAD   0x00000100

#define RDMAC_STATUS_LNGREAD   0x00000200

#define WDMAC_MODE   0x00004c00

#define WDMAC_MODE_RESET   0x00000001

#define WDMAC_MODE_ENABLE   0x00000002

#define WDMAC_MODE_TGTABORT_ENAB   0x00000004

#define WDMAC_MODE_MSTABORT_ENAB   0x00000008

#define WDMAC_MODE_PARITYERR_ENAB   0x00000010

#define WDMAC_MODE_ADDROFLOW_ENAB   0x00000020

#define WDMAC_MODE_FIFOOFLOW_ENAB   0x00000040

#define WDMAC_MODE_FIFOURUN_ENAB   0x00000080

#define WDMAC_MODE_FIFOOREAD_ENAB   0x00000100

#define WDMAC_MODE_LNGREAD_ENAB   0x00000200

#define WDMAC_MODE_RX_ACCEL   0x00000400

#define WDMAC_STATUS   0x00004c04

#define WDMAC_STATUS_TGTABORT   0x00000004

#define WDMAC_STATUS_MSTABORT   0x00000008

#define WDMAC_STATUS_PARITYERR   0x00000010

#define WDMAC_STATUS_ADDROFLOW   0x00000020

#define WDMAC_STATUS_FIFOOFLOW   0x00000040

#define WDMAC_STATUS_FIFOURUN   0x00000080

#define WDMAC_STATUS_FIFOOREAD   0x00000100

#define WDMAC_STATUS_LNGREAD   0x00000200

#define CPU_MODE   0x00000000

#define CPU_MODE_RESET   0x00000001

#define CPU_MODE_HALT   0x00000400

#define CPU_STATE   0x00000004

#define CPU_EVTMASK   0x00000008

#define CPU_PC   0x0000001c

#define CPU_INSN   0x00000020

#define CPU_SPAD_UFLOW   0x00000024

#define CPU_WDOG_CLEAR   0x00000028

#define CPU_WDOG_VECTOR   0x0000002c

#define CPU_WDOG_PC   0x00000030

#define CPU_HW_BP   0x00000034

#define CPU_WDOG_SAVED_STATE   0x00000044

#define CPU_LAST_BRANCH_ADDR   0x00000048

#define CPU_SPAD_UFLOW_SET   0x0000004c

#define CPU_R0   0x00000200

#define CPU_R1   0x00000204

#define CPU_R2   0x00000208

#define CPU_R3   0x0000020c

#define CPU_R4   0x00000210

#define CPU_R5   0x00000214

#define CPU_R6   0x00000218

#define CPU_R7   0x0000021c

#define CPU_R8   0x00000220

#define CPU_R9   0x00000224

#define CPU_R10   0x00000228

#define CPU_R11   0x0000022c

#define CPU_R12   0x00000230

#define CPU_R13   0x00000234

#define CPU_R14   0x00000238

#define CPU_R15   0x0000023c

#define CPU_R16   0x00000240

#define CPU_R17   0x00000244

#define CPU_R18   0x00000248

#define CPU_R19   0x0000024c

#define CPU_R20   0x00000250

#define CPU_R21   0x00000254

#define CPU_R22   0x00000258

#define CPU_R23   0x0000025c

#define CPU_R24   0x00000260

#define CPU_R25   0x00000264

#define CPU_R26   0x00000268

#define CPU_R27   0x0000026c

#define CPU_R28   0x00000270

#define CPU_R29   0x00000274

#define CPU_R30   0x00000278

#define CPU_R31   0x0000027c

#define RX_CPU_BASE   0x00005000

#define TX_CPU_BASE   0x00005400

#define GRCMBOX_INTERRUPT_0   0x00005800

#define GRCMBOX_INTERRUPT_1   0x00005808

#define GRCMBOX_INTERRUPT_2   0x00005810

#define GRCMBOX_INTERRUPT_3   0x00005818

#define GRCMBOX_GENERAL_0   0x00005820

#define GRCMBOX_GENERAL_1   0x00005828

#define GRCMBOX_GENERAL_2   0x00005830

#define GRCMBOX_GENERAL_3   0x00005838

#define GRCMBOX_GENERAL_4   0x00005840

#define GRCMBOX_GENERAL_5   0x00005848

#define GRCMBOX_GENERAL_6   0x00005850

#define GRCMBOX_GENERAL_7   0x00005858

#define GRCMBOX_RELOAD_STAT   0x00005860

#define GRCMBOX_RCVSTD_PROD_IDX   0x00005868

#define GRCMBOX_RCVJUMBO_PROD_IDX   0x00005870

#define GRCMBOX_RCVMINI_PROD_IDX   0x00005878

#define GRCMBOX_RCVRET_CON_IDX_0   0x00005880

#define GRCMBOX_RCVRET_CON_IDX_1   0x00005888

#define GRCMBOX_RCVRET_CON_IDX_2   0x00005890

#define GRCMBOX_RCVRET_CON_IDX_3   0x00005898

#define GRCMBOX_RCVRET_CON_IDX_4   0x000058a0

#define GRCMBOX_RCVRET_CON_IDX_5   0x000058a8

#define GRCMBOX_RCVRET_CON_IDX_6   0x000058b0

#define GRCMBOX_RCVRET_CON_IDX_7   0x000058b8

#define GRCMBOX_RCVRET_CON_IDX_8   0x000058c0

#define GRCMBOX_RCVRET_CON_IDX_9   0x000058c8

#define GRCMBOX_RCVRET_CON_IDX_10   0x000058d0

#define GRCMBOX_RCVRET_CON_IDX_11   0x000058d8

#define GRCMBOX_RCVRET_CON_IDX_12   0x000058e0

#define GRCMBOX_RCVRET_CON_IDX_13   0x000058e8

#define GRCMBOX_RCVRET_CON_IDX_14   0x000058f0

#define GRCMBOX_RCVRET_CON_IDX_15   0x000058f8

#define GRCMBOX_SNDHOST_PROD_IDX_0   0x00005900

#define GRCMBOX_SNDHOST_PROD_IDX_1   0x00005908

#define GRCMBOX_SNDHOST_PROD_IDX_2   0x00005910

#define GRCMBOX_SNDHOST_PROD_IDX_3   0x00005918

#define GRCMBOX_SNDHOST_PROD_IDX_4   0x00005920

#define GRCMBOX_SNDHOST_PROD_IDX_5   0x00005928

#define GRCMBOX_SNDHOST_PROD_IDX_6   0x00005930

#define GRCMBOX_SNDHOST_PROD_IDX_7   0x00005938

#define GRCMBOX_SNDHOST_PROD_IDX_8   0x00005940

#define GRCMBOX_SNDHOST_PROD_IDX_9   0x00005948

#define GRCMBOX_SNDHOST_PROD_IDX_10   0x00005950

#define GRCMBOX_SNDHOST_PROD_IDX_11   0x00005958

#define GRCMBOX_SNDHOST_PROD_IDX_12   0x00005960

#define GRCMBOX_SNDHOST_PROD_IDX_13   0x00005968

#define GRCMBOX_SNDHOST_PROD_IDX_14   0x00005970

#define GRCMBOX_SNDHOST_PROD_IDX_15   0x00005978

#define GRCMBOX_SNDNIC_PROD_IDX_0   0x00005980

#define GRCMBOX_SNDNIC_PROD_IDX_1   0x00005988

#define GRCMBOX_SNDNIC_PROD_IDX_2   0x00005990

#define GRCMBOX_SNDNIC_PROD_IDX_3   0x00005998

#define GRCMBOX_SNDNIC_PROD_IDX_4   0x000059a0

#define GRCMBOX_SNDNIC_PROD_IDX_5   0x000059a8

#define GRCMBOX_SNDNIC_PROD_IDX_6   0x000059b0

#define GRCMBOX_SNDNIC_PROD_IDX_7   0x000059b8

#define GRCMBOX_SNDNIC_PROD_IDX_8   0x000059c0

#define GRCMBOX_SNDNIC_PROD_IDX_9   0x000059c8

#define GRCMBOX_SNDNIC_PROD_IDX_10   0x000059d0

#define GRCMBOX_SNDNIC_PROD_IDX_11   0x000059d8

#define GRCMBOX_SNDNIC_PROD_IDX_12   0x000059e0

#define GRCMBOX_SNDNIC_PROD_IDX_13   0x000059e8

#define GRCMBOX_SNDNIC_PROD_IDX_14   0x000059f0

#define GRCMBOX_SNDNIC_PROD_IDX_15   0x000059f8

#define GRCMBOX_HIGH_PRIO_EV_VECTOR   0x00005a00

#define GRCMBOX_HIGH_PRIO_EV_MASK   0x00005a04

#define GRCMBOX_LOW_PRIO_EV_VEC   0x00005a08

#define GRCMBOX_LOW_PRIO_EV_MASK   0x00005a0c

#define FTQ_RESET   0x00005c00

#define FTQ_RESET_DMA_READ_QUEUE   (1 << 1)

#define FTQ_RESET_DMA_HIGH_PRI_READ   (1 << 2)

#define FTQ_RESET_SEND_BD_COMPLETION   (1 << 4)

#define FTQ_RESET_DMA_WRITE   (1 << 6)

#define FTQ_RESET_DMA_HIGH_PRI_WRITE   (1 << 7)

#define FTQ_RESET_SEND_DATA_COMPLETION   (1 << 9)

#define FTQ_RESET_HOST_COALESCING   (1 << 10)

#define FTQ_RESET_MAC_TX   (1 << 11)

#define FTQ_RESET_RX_BD_COMPLETE   (1 << 13)

#define FTQ_RESET_RX_LIST_PLCMT   (1 << 14)

#define FTQ_RESET_RX_DATA_COMPLETION   (1 << 16)

#define FTQ_DMA_NORM_READ_CTL   0x00005c10

#define FTQ_DMA_NORM_READ_FULL_CNT   0x00005c14

#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ   0x00005c18

#define FTQ_DMA_NORM_READ_WRITE_PEEK   0x00005c1c

#define FTQ_DMA_HIGH_READ_CTL   0x00005c20

#define FTQ_DMA_HIGH_READ_FULL_CNT   0x00005c24

#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ   0x00005c28

#define FTQ_DMA_HIGH_READ_WRITE_PEEK   0x00005c2c

#define FTQ_DMA_COMP_DISC_CTL   0x00005c30

#define FTQ_DMA_COMP_DISC_FULL_CNT   0x00005c34

#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ   0x00005c38

#define FTQ_DMA_COMP_DISC_WRITE_PEEK   0x00005c3c

#define FTQ_SEND_BD_COMP_CTL   0x00005c40

#define FTQ_SEND_BD_COMP_FULL_CNT   0x00005c44

#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ   0x00005c48

#define FTQ_SEND_BD_COMP_WRITE_PEEK   0x00005c4c

#define FTQ_SEND_DATA_INIT_CTL   0x00005c50

#define FTQ_SEND_DATA_INIT_FULL_CNT   0x00005c54

#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ   0x00005c58

#define FTQ_SEND_DATA_INIT_WRITE_PEEK   0x00005c5c

#define FTQ_DMA_NORM_WRITE_CTL   0x00005c60

#define FTQ_DMA_NORM_WRITE_FULL_CNT   0x00005c64

#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ   0x00005c68

#define FTQ_DMA_NORM_WRITE_WRITE_PEEK   0x00005c6c

#define FTQ_DMA_HIGH_WRITE_CTL   0x00005c70

#define FTQ_DMA_HIGH_WRITE_FULL_CNT   0x00005c74

#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ   0x00005c78

#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK   0x00005c7c

#define FTQ_SWTYPE1_CTL   0x00005c80

#define FTQ_SWTYPE1_FULL_CNT   0x00005c84

#define FTQ_SWTYPE1_FIFO_ENQDEQ   0x00005c88

#define FTQ_SWTYPE1_WRITE_PEEK   0x00005c8c

#define FTQ_SEND_DATA_COMP_CTL   0x00005c90

#define FTQ_SEND_DATA_COMP_FULL_CNT   0x00005c94

#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ   0x00005c98

#define FTQ_SEND_DATA_COMP_WRITE_PEEK   0x00005c9c

#define FTQ_HOST_COAL_CTL   0x00005ca0

#define FTQ_HOST_COAL_FULL_CNT   0x00005ca4

#define FTQ_HOST_COAL_FIFO_ENQDEQ   0x00005ca8

#define FTQ_HOST_COAL_WRITE_PEEK   0x00005cac

#define FTQ_MAC_TX_CTL   0x00005cb0

#define FTQ_MAC_TX_FULL_CNT   0x00005cb4

#define FTQ_MAC_TX_FIFO_ENQDEQ   0x00005cb8

#define FTQ_MAC_TX_WRITE_PEEK   0x00005cbc

#define FTQ_MB_FREE_CTL   0x00005cc0

#define FTQ_MB_FREE_FULL_CNT   0x00005cc4

#define FTQ_MB_FREE_FIFO_ENQDEQ   0x00005cc8

#define FTQ_MB_FREE_WRITE_PEEK   0x00005ccc

#define FTQ_RCVBD_COMP_CTL   0x00005cd0

#define FTQ_RCVBD_COMP_FULL_CNT   0x00005cd4

#define FTQ_RCVBD_COMP_FIFO_ENQDEQ   0x00005cd8

#define FTQ_RCVBD_COMP_WRITE_PEEK   0x00005cdc

#define FTQ_RCVLST_PLMT_CTL   0x00005ce0

#define FTQ_RCVLST_PLMT_FULL_CNT   0x00005ce4

#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ   0x00005ce8

#define FTQ_RCVLST_PLMT_WRITE_PEEK   0x00005cec

#define FTQ_RCVDATA_INI_CTL   0x00005cf0

#define FTQ_RCVDATA_INI_FULL_CNT   0x00005cf4

#define FTQ_RCVDATA_INI_FIFO_ENQDEQ   0x00005cf8

#define FTQ_RCVDATA_INI_WRITE_PEEK   0x00005cfc

#define FTQ_RCVDATA_COMP_CTL   0x00005d00

#define FTQ_RCVDATA_COMP_FULL_CNT   0x00005d04

#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ   0x00005d08

#define FTQ_RCVDATA_COMP_WRITE_PEEK   0x00005d0c

#define FTQ_SWTYPE2_CTL   0x00005d10

#define FTQ_SWTYPE2_FULL_CNT   0x00005d14

#define FTQ_SWTYPE2_FIFO_ENQDEQ   0x00005d18

#define FTQ_SWTYPE2_WRITE_PEEK   0x00005d1c

#define MSGINT_MODE   0x00006000

#define MSGINT_MODE_RESET   0x00000001

#define MSGINT_MODE_ENABLE   0x00000002

#define MSGINT_STATUS   0x00006004

#define MSGINT_FIFO   0x00006008

#define DMAC_MODE   0x00006400

#define DMAC_MODE_RESET   0x00000001

#define DMAC_MODE_ENABLE   0x00000002

#define GRC_MODE   0x00006800

#define GRC_MODE_UPD_ON_COAL   0x00000001

#define GRC_MODE_BSWAP_NONFRM_DATA   0x00000002

#define GRC_MODE_WSWAP_NONFRM_DATA   0x00000004

#define GRC_MODE_BSWAP_DATA   0x00000010

#define GRC_MODE_WSWAP_DATA   0x00000020

#define GRC_MODE_SPLITHDR   0x00000100

#define GRC_MODE_NOFRM_CRACKING   0x00000200

#define GRC_MODE_INCL_CRC   0x00000400

#define GRC_MODE_ALLOW_BAD_FRMS   0x00000800

#define GRC_MODE_NOIRQ_ON_SENDS   0x00002000

#define GRC_MODE_NOIRQ_ON_RCV   0x00004000

#define GRC_MODE_FORCE_PCI32BIT   0x00008000

#define GRC_MODE_HOST_STACKUP   0x00010000

#define GRC_MODE_HOST_SENDBDS   0x00020000

#define GRC_MODE_NO_TX_PHDR_CSUM   0x00100000

#define GRC_MODE_NO_RX_PHDR_CSUM   0x00800000

#define GRC_MODE_IRQ_ON_TX_CPU_ATTN   0x01000000

#define GRC_MODE_IRQ_ON_RX_CPU_ATTN   0x02000000

#define GRC_MODE_IRQ_ON_MAC_ATTN   0x04000000

#define GRC_MODE_IRQ_ON_DMA_ATTN   0x08000000

#define GRC_MODE_IRQ_ON_FLOW_ATTN   0x10000000

#define GRC_MODE_4X_NIC_SEND_RINGS   0x20000000

#define GRC_MODE_MCAST_FRM_ENABLE   0x40000000

#define GRC_MISC_CFG   0x00006804

#define GRC_MISC_CFG_CORECLK_RESET   0x00000001

#define GRC_MISC_CFG_PRESCALAR_MASK   0x000000fe

#define GRC_MISC_CFG_PRESCALAR_SHIFT   1

#define GRC_MISC_CFG_BOARD_ID_MASK   0x0001e000

#define GRC_MISC_CFG_BOARD_ID_5700   0x0001e000

#define GRC_MISC_CFG_BOARD_ID_5701   0x00000000

#define GRC_MISC_CFG_BOARD_ID_5702FE   0x00004000

#define GRC_MISC_CFG_BOARD_ID_5703   0x00000000

#define GRC_MISC_CFG_BOARD_ID_5703S   0x00002000

#define GRC_MISC_CFG_BOARD_ID_5704   0x00000000

#define GRC_MISC_CFG_BOARD_ID_5704CIOBE   0x00004000

#define GRC_MISC_CFG_BOARD_ID_5704_A2   0x00008000

#define GRC_MISC_CFG_BOARD_ID_5788   0x00010000

#define GRC_MISC_CFG_BOARD_ID_5788M   0x00018000

#define GRC_MISC_CFG_BOARD_ID_AC91002A1   0x00018000

#define GRC_MISC_CFG_KEEP_GPHY_POWER   0x04000000

#define GRC_LOCAL_CTRL   0x00006808

#define GRC_LCLCTRL_INT_ACTIVE   0x00000001

#define GRC_LCLCTRL_CLEARINT   0x00000002

#define GRC_LCLCTRL_SETINT   0x00000004

#define GRC_LCLCTRL_INT_ON_ATTN   0x00000008

#define GRC_LCLCTRL_GPIO_INPUT0   0x00000100

#define GRC_LCLCTRL_GPIO_INPUT1   0x00000200

#define GRC_LCLCTRL_GPIO_INPUT2   0x00000400

#define GRC_LCLCTRL_GPIO_OE0   0x00000800

#define GRC_LCLCTRL_GPIO_OE1   0x00001000

#define GRC_LCLCTRL_GPIO_OE2   0x00002000

#define GRC_LCLCTRL_GPIO_OUTPUT0   0x00004000

#define GRC_LCLCTRL_GPIO_OUTPUT1   0x00008000

#define GRC_LCLCTRL_GPIO_OUTPUT2   0x00010000

#define GRC_LCLCTRL_EXTMEM_ENABLE   0x00020000

#define GRC_LCLCTRL_MEMSZ_MASK   0x001c0000

#define GRC_LCLCTRL_MEMSZ_256K   0x00000000

#define GRC_LCLCTRL_MEMSZ_512K   0x00040000

#define GRC_LCLCTRL_MEMSZ_1M   0x00080000

#define GRC_LCLCTRL_MEMSZ_2M   0x000c0000

#define GRC_LCLCTRL_MEMSZ_4M   0x00100000

#define GRC_LCLCTRL_MEMSZ_8M   0x00140000

#define GRC_LCLCTRL_MEMSZ_16M   0x00180000

#define GRC_LCLCTRL_BANK_SELECT   0x00200000

#define GRC_LCLCTRL_SSRAM_TYPE   0x00400000

#define GRC_LCLCTRL_AUTO_SEEPROM   0x01000000

#define GRC_TIMER   0x0000680c

#define GRC_RX_CPU_EVENT   0x00006810

#define GRC_RX_TIMER_REF   0x00006814

#define GRC_RX_CPU_SEM   0x00006818

#define GRC_REMOTE_RX_CPU_ATTN   0x0000681c

#define GRC_TX_CPU_EVENT   0x00006820

#define GRC_TX_TIMER_REF   0x00006824

#define GRC_TX_CPU_SEM   0x00006828

#define GRC_REMOTE_TX_CPU_ATTN   0x0000682c

#define GRC_MEM_POWER_UP   0x00006830

#define GRC_EEPROM_ADDR   0x00006838

#define EEPROM_ADDR_WRITE   0x00000000

#define EEPROM_ADDR_READ   0x80000000

#define EEPROM_ADDR_COMPLETE   0x40000000

#define EEPROM_ADDR_FSM_RESET   0x20000000

#define EEPROM_ADDR_DEVID_MASK   0x1c000000

#define EEPROM_ADDR_DEVID_SHIFT   26

#define EEPROM_ADDR_START   0x02000000

#define EEPROM_ADDR_CLKPERD_SHIFT   16

#define EEPROM_ADDR_ADDR_MASK   0x0000ffff

#define EEPROM_ADDR_ADDR_SHIFT   0

#define EEPROM_DEFAULT_CLOCK_PERIOD   0x60

#define EEPROM_CHIP_SIZE   (64 * 1024)

#define GRC_EEPROM_DATA   0x0000683c

#define GRC_EEPROM_CTRL   0x00006840

#define GRC_MDI_CTRL   0x00006844

#define GRC_SEEPROM_DELAY   0x00006848

#define NVRAM_CMD   0x00007000

#define NVRAM_CMD_RESET   0x00000001

#define NVRAM_CMD_DONE   0x00000008

#define NVRAM_CMD_GO   0x00000010

#define NVRAM_CMD_WR   0x00000020

#define NVRAM_CMD_RD   0x00000000

#define NVRAM_CMD_ERASE   0x00000040

#define NVRAM_CMD_FIRST   0x00000080

#define NVRAM_CMD_LAST   0x00000100

#define NVRAM_STAT   0x00007004

#define NVRAM_WRDATA   0x00007008

#define NVRAM_ADDR   0x0000700c

#define NVRAM_ADDR_MSK   0x00ffffff

#define NVRAM_RDDATA   0x00007010

#define NVRAM_CFG1   0x00007014

#define NVRAM_CFG1_FLASHIF_ENAB   0x00000001

#define NVRAM_CFG1_BUFFERED_MODE   0x00000002

#define NVRAM_CFG1_PASS_THRU   0x00000004

#define NVRAM_CFG1_BIT_BANG   0x00000008

#define NVRAM_CFG1_COMPAT_BYPASS   0x80000000

#define NVRAM_CFG2   0x00007018

#define NVRAM_CFG3   0x0000701c

#define NVRAM_SWARB   0x00007020

#define SWARB_REQ_SET0   0x00000001

#define SWARB_REQ_SET1   0x00000002

#define SWARB_REQ_SET2   0x00000004

#define SWARB_REQ_SET3   0x00000008

#define SWARB_REQ_CLR0   0x00000010

#define SWARB_REQ_CLR1   0x00000020

#define SWARB_REQ_CLR2   0x00000040

#define SWARB_REQ_CLR3   0x00000080

#define SWARB_GNT0   0x00000100

#define SWARB_GNT1   0x00000200

#define SWARB_GNT2   0x00000400

#define SWARB_GNT3   0x00000800

#define SWARB_REQ0   0x00001000

#define SWARB_REQ1   0x00002000

#define SWARB_REQ2   0x00004000

#define SWARB_REQ3   0x00008000

#define NVRAM_BUFFERED_PAGE_SIZE   264

#define NVRAM_BUFFERED_PAGE_POS   9

#define NIC_SRAM_WIN_BASE   0x00008000

#define NIC_SRAM_PAGE_ZERO   0x00000000

#define NIC_SRAM_SEND_RCB   0x00000100

#define NIC_SRAM_RCV_RET_RCB   0x00000200

#define NIC_SRAM_STATS_BLK   0x00000300

#define NIC_SRAM_STATUS_BLK   0x00000b00

#define NIC_SRAM_FIRMWARE_MBOX   0x00000b50

#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1   0x4B657654

#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2   0x4861764b

#define NIC_SRAM_DATA_SIG   0x00000b54

#define NIC_SRAM_DATA_SIG_MAGIC   0x4b657654

#define NIC_SRAM_DATA_CFG   0x00000b58

#define NIC_SRAM_DATA_CFG_LED_MODE_MASK   0x0000000c

#define NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN   0x00000000

#define NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD   0x00000004

#define NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN   0x00000004

#define NIC_SRAM_DATA_CFG_LED_LINK_SPD   0x00000008

#define NIC_SRAM_DATA_CFG_LED_OUTPUT   0x00000008

#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK   0x00000030

#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN   0x00000000

#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER   0x00000010

#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER   0x00000020

#define NIC_SRAM_DATA_CFG_WOL_ENABLE   0x00000040

#define NIC_SRAM_DATA_CFG_ASF_ENABLE   0x00000080

#define NIC_SRAM_DATA_CFG_EEPROM_WP   0x00000100

#define NIC_SRAM_DATA_CFG_MINI_PCI   0x00001000

#define NIC_SRAM_DATA_CFG_FIBER_WOL   0x00004000

#define NIC_SRAM_DATA_PHY_ID   0x00000b74

#define NIC_SRAM_DATA_PHY_ID1_MASK   0xffff0000

#define NIC_SRAM_DATA_PHY_ID2_MASK   0x0000ffff

#define NIC_SRAM_FW_CMD_MBOX   0x00000b78

#define FWCMD_NICDRV_ALIVE   0x00000001

#define FWCMD_NICDRV_PAUSE_FW   0x00000002

#define FWCMD_NICDRV_IPV4ADDR_CHG   0x00000003

#define FWCMD_NICDRV_IPV6ADDR_CHG   0x00000004

#define FWCMD_NICDRV_FIX_DMAR   0x00000005

#define FWCMD_NICDRV_FIX_DMAW   0x00000006

#define NIC_SRAM_FW_CMD_LEN_MBOX   0x00000b7c

#define NIC_SRAM_FW_CMD_DATA_MBOX   0x00000b80

#define NIC_SRAM_FW_ASF_STATUS_MBOX   0x00000c00

#define NIC_SRAM_FW_DRV_STATE_MBOX   0x00000c04

#define DRV_STATE_START   0x00000001

#define DRV_STATE_UNLOAD   0x00000002

#define DRV_STATE_WOL   0x00000003

#define DRV_STATE_SUSPEND   0x00000004

#define NIC_SRAM_FW_RESET_TYPE_MBOX   0x00000c08

#define NIC_SRAM_MAC_ADDR_HIGH_MBOX   0x00000c14

#define NIC_SRAM_MAC_ADDR_LOW_MBOX   0x00000c18

#define NIC_SRAM_RX_MINI_BUFFER_DESC   0x00001000

#define NIC_SRAM_DMA_DESC_POOL_BASE   0x00002000

#define NIC_SRAM_DMA_DESC_POOL_SIZE   0x00002000

#define NIC_SRAM_TX_BUFFER_DESC   0x00004000

#define NIC_SRAM_RX_BUFFER_DESC   0x00006000

#define NIC_SRAM_RX_JUMBO_BUFFER_DESC   0x00007000

#define NIC_SRAM_MBUF_POOL_BASE   0x00008000

#define NIC_SRAM_MBUF_POOL_SIZE96   0x00018000

#define NIC_SRAM_MBUF_POOL_SIZE64   0x00010000

#define NIC_SRAM_MBUF_POOL_BASE5705   0x00010000

#define NIC_SRAM_MBUF_POOL_SIZE5705   0x0000e000

#define PHY_ADDR   0x01

#define TG3_BMCR_SPEED1000   0x0040

#define MII_TG3_CTRL   0x09

#define MII_TG3_CTRL_ADV_1000_HALF   0x0100

#define MII_TG3_CTRL_ADV_1000_FULL   0x0200

#define MII_TG3_CTRL_AS_MASTER   0x0800

#define MII_TG3_CTRL_ENABLE_AS_MASTER   0x1000

#define MII_TG3_EXT_CTRL   0x10

#define MII_TG3_EXT_CTRL_LNK3_LED_MODE   0x0002

#define MII_TG3_EXT_CTRL_TBI   0x8000

#define MII_TG3_EXT_STAT   0x11

#define MII_TG3_EXT_STAT_LPASS   0x0100

#define MII_TG3_DSP_RW_PORT   0x15

#define MII_TG3_DSP_ADDRESS   0x17

#define MII_TG3_AUX_CTRL   0x18

#define MII_TG3_AUX_STAT   0x19

#define MII_TG3_AUX_STAT_LPASS   0x0004

#define MII_TG3_AUX_STAT_SPDMASK   0x0700

#define MII_TG3_AUX_STAT_10HALF   0x0100

#define MII_TG3_AUX_STAT_10FULL   0x0200

#define MII_TG3_AUX_STAT_100HALF   0x0300

#define MII_TG3_AUX_STAT_100_4   0x0400

#define MII_TG3_AUX_STAT_100FULL   0x0500

#define MII_TG3_AUX_STAT_1000HALF   0x0600

#define MII_TG3_AUX_STAT_1000FULL   0x0700

#define MII_TG3_ISTAT   0x1a

#define MII_TG3_IMASK   0x1b

#define MII_TG3_INT_LINKCHG   0x0002

#define MII_TG3_INT_SPEEDCHG   0x0004

#define MII_TG3_INT_DUPLEXCHG   0x0008

#define MII_TG3_INT_ANEG_PAGE_RX   0x0400

#define TXD_FLAG_TCPUDP_CSUM   0x0001

#define TXD_FLAG_IP_CSUM   0x0002

#define TXD_FLAG_END   0x0004

#define TXD_FLAG_IP_FRAG   0x0008

#define TXD_FLAG_IP_FRAG_END   0x0010

#define TXD_FLAG_VLAN   0x0040

#define TXD_FLAG_COAL_NOW   0x0080

#define TXD_FLAG_CPU_PRE_DMA   0x0100

#define TXD_FLAG_CPU_POST_DMA   0x0200

#define TXD_FLAG_ADD_SRC_ADDR   0x1000

#define TXD_FLAG_CHOOSE_SRC_ADDR   0x6000

#define TXD_FLAG_NO_CRC   0x8000

#define TXD_LEN_SHIFT   16

#define TXD_VLAN_TAG_SHIFT   0

#define TXD_MSS_SHIFT   16

#define TXD_ADDR   0x00UL

#define TXD_LEN_FLAGS   0x08UL

#define TXD_VLAN_TAG   0x0cUL

#define TXD_SIZE   0x10UL

#define RXD_IDX_MASK   0xffff0000

#define RXD_IDX_SHIFT   16

#define RXD_LEN_MASK   0x0000ffff

#define RXD_LEN_SHIFT   0

#define RXD_TYPE_SHIFT   16

#define RXD_FLAGS_SHIFT   0

#define RXD_FLAG_END   0x0004

#define RXD_FLAG_MINI   0x0800

#define RXD_FLAG_JUMBO   0x0020

#define RXD_FLAG_VLAN   0x0040

#define RXD_FLAG_ERROR   0x0400

#define RXD_FLAG_IP_CSUM   0x1000

#define RXD_FLAG_TCPUDP_CSUM   0x2000

#define RXD_FLAG_IS_TCP   0x4000

#define RXD_IPCSUM_MASK   0xffff0000

#define RXD_IPCSUM_SHIFT   16

#define RXD_TCPCSUM_MASK   0x0000ffff

#define RXD_TCPCSUM_SHIFT   0

#define RXD_VLAN_MASK   0x0000ffff

#define RXD_ERR_BAD_CRC   0x00010000

#define RXD_ERR_COLLISION   0x00020000

#define RXD_ERR_LINK_LOST   0x00040000

#define RXD_ERR_PHY_DECODE   0x00080000

#define RXD_ERR_ODD_NIBBLE_RCVD_MII   0x00100000

#define RXD_ERR_MAC_ABRT   0x00200000

#define RXD_ERR_TOO_SMALL   0x00400000

#define RXD_ERR_NO_RESOURCES   0x00800000

#define RXD_ERR_HUGE_FRAME   0x01000000

#define RXD_ERR_MASK   0xffff0000

#define RXD_OPAQUE_INDEX_MASK   0x0000ffff

#define RXD_OPAQUE_INDEX_SHIFT   0

#define RXD_OPAQUE_RING_STD   0x00010000

#define RXD_OPAQUE_RING_JUMBO   0x00020000

#define RXD_OPAQUE_RING_MINI   0x00040000

#define RXD_OPAQUE_RING_MASK   0x00070000

#define TG3_HW_STATUS_SIZE   0x50

#define SD_STATUS_UPDATED   0x00000001

#define SD_STATUS_LINK_CHG   0x00000002

#define SD_STATUS_ERROR   0x00000004

#define TG3_FLAG_TXD_MBOX_HWBUG   0x00000002

#define TG3_FLAG_RX_CHECKSUMS   0x00000004

#define TG3_FLAG_USE_LINKCHG_REG   0x00000008

#define TG3_FLAG_USE_MI_INTERRUPT   0x00000010

#define TG3_FLAG_ENABLE_ASF   0x00000020

#define TG3_FLAG_5701_REG_WRITE_BUG   0x00000040

#define TG3_FLAG_POLL_SERDES   0x00000080

#define TG3_FLAG_MBOX_WRITE_REORDER   0x00000100

#define TG3_FLAG_PCIX_TARGET_HWBUG   0x00000200

#define TG3_FLAG_WOL_SPEED_100MB   0x00000400

#define TG3_FLAG_WOL_ENABLE   0x00000800

#define TG3_FLAG_EEPROM_WRITE_PROT   0x00001000

#define TG3_FLAG_NVRAM   0x00002000

#define TG3_FLAG_NVRAM_BUFFERED   0x00004000

#define TG3_FLAG_RX_PAUSE   0x00008000

#define TG3_FLAG_TX_PAUSE   0x00010000

#define TG3_FLAG_PCIX_MODE   0x00020000

#define TG3_FLAG_PCI_HIGH_SPEED   0x00040000

#define TG3_FLAG_PCI_32BIT   0x00080000

#define TG3_FLAG_NO_TX_PSEUDO_CSUM   0x00100000

#define TG3_FLAG_NO_RX_PSEUDO_CSUM   0x00200000

#define TG3_FLAG_SERDES_WOL_CAP   0x00400000

#define TG3_FLAG_JUMBO_ENABLE   0x00800000

#define TG3_FLAG_10_100_ONLY   0x01000000

#define TG3_FLAG_PAUSE_AUTONEG   0x02000000

#define TG3_FLAG_PAUSE_RX   0x04000000

#define TG3_FLAG_PAUSE_TX   0x08000000

#define TG3_FLAG_BROKEN_CHECKSUMS   0x10000000

#define TG3_FLAG_GOT_SERDES_FLOWCTL   0x20000000

#define TG3_FLAG_SPLIT_MODE   0x40000000

#define TG3_FLAG_INIT_COMPLETE   0x80000000

#define TG3_FLG2_RESTART_TIMER   0x00000001

#define TG3_FLG2_SUN_5704   0x00000002

#define TG3_FLG2_NO_ETH_WIRE_SPEED   0x00000004

#define TG3_FLG2_IS_5788   0x00000008

#define TG3_FLG2_MAX_RXPEND_64   0x00000010

#define TG3_FLG2_TSO_CAPABLE   0x00000020

#define TG3_FLG2_PCI_EXPRESS   0x00000040

#define SPLIT_MODE_5704_MAX_REQ   3

#define PHY_ID_MASK   0xfffffff0

#define PHY_ID_BCM5400   0x60008040

#define PHY_ID_BCM5401   0x60008050

#define PHY_ID_BCM5411   0x60008070

#define PHY_ID_BCM5701   0x60008110

#define PHY_ID_BCM5703   0x60008160

#define PHY_ID_BCM5704   0x60008190

#define PHY_ID_BCM5705   0x600081a0

#define PHY_ID_BCM5750   0x60008180

#define PHY_ID_BCM5787   0xbc050ce0

#define PHY_ID_BCM8002   0x60010140

#define PHY_ID_BCM5751   0x00206180

#define PHY_ID_SERDES   0xfeedbee0

#define PHY_ID_INVALID   0xffffffff

#define PHY_ID_REV_MASK   0x0000000f

#define PHY_REV_BCM5401_B0   0x1

#define PHY_REV_BCM5401_B2   0x3

#define PHY_REV_BCM5401_C0   0x6

#define PHY_REV_BCM5411_X0   0x1

#define KNOWN_PHY_ID(X)

Typedefs

typedef unsigned long dma_addr_t

Enumerations

enum phy_led_mode { led_mode_auto, led_mode_three_link, led_mode_link10 }

Functions

FILE_LICENCE (GPL2_ONLY)

Define Documentation

#define ADVERTISED_10baseT_Half (1 << 0)

Definition at line 20 of file tg3.h.

#define ADVERTISED_10baseT_Full (1 << 1)

Definition at line 21 of file tg3.h.

#define ADVERTISED_100baseT_Half (1 << 2)

Definition at line 22 of file tg3.h.

#define ADVERTISED_100baseT_Full (1 << 3)

Definition at line 23 of file tg3.h.

#define ADVERTISED_1000baseT_Half (1 << 4)

Definition at line 24 of file tg3.h.

#define ADVERTISED_1000baseT_Full (1 << 5)

Definition at line 25 of file tg3.h.

#define ADVERTISED_Autoneg (1 << 6)

Definition at line 26 of file tg3.h.

#define ADVERTISED_TP (1 << 7)

Definition at line 27 of file tg3.h.

#define ADVERTISED_AUI (1 << 8)

Definition at line 28 of file tg3.h.

#define ADVERTISED_MII (1 << 9)

Definition at line 29 of file tg3.h.

#define ADVERTISED_FIBRE (1 << 10)

Definition at line 30 of file tg3.h.

#define ADVERTISED_BNC (1 << 11)

Definition at line 31 of file tg3.h.

#define SPEED_10 0

Definition at line 40 of file tg3.h.

#define SPEED_100 1

Definition at line 41 of file tg3.h.

#define SPEED_1000 2

Definition at line 42 of file tg3.h.

#define SPEED_INVALID 3

Definition at line 43 of file tg3.h.

#define DUPLEX_HALF 0x00

Definition at line 47 of file tg3.h.

#define DUPLEX_FULL 0x01

Definition at line 48 of file tg3.h.

#define DUPLEX_INVALID 0x02

Definition at line 49 of file tg3.h.

#define PORT_TP 0x00

Definition at line 52 of file tg3.h.

#define PORT_AUI 0x01

Definition at line 53 of file tg3.h.

#define PORT_MII 0x02

Definition at line 54 of file tg3.h.

#define PORT_FIBRE 0x03

Definition at line 55 of file tg3.h.

#define PORT_BNC 0x04

Definition at line 56 of file tg3.h.

#define XCVR_INTERNAL 0x00

Definition at line 59 of file tg3.h.

#define XCVR_EXTERNAL 0x01

Definition at line 60 of file tg3.h.

#define XCVR_DUMMY1 0x02

Definition at line 61 of file tg3.h.

#define XCVR_DUMMY2 0x03

Definition at line 62 of file tg3.h.

#define XCVR_DUMMY3 0x04

Definition at line 63 of file tg3.h.

#define AUTONEG_DISABLE 0x00

Definition at line 68 of file tg3.h.

#define AUTONEG_ENABLE 0x01

Definition at line 69 of file tg3.h.

#define WAKE_PHY (1 << 0)

Definition at line 72 of file tg3.h.

#define WAKE_UCAST (1 << 1)

Definition at line 73 of file tg3.h.

#define WAKE_MCAST (1 << 2)

Definition at line 74 of file tg3.h.

#define WAKE_BCAST (1 << 3)

Definition at line 75 of file tg3.h.

#define WAKE_ARP (1 << 4)

Definition at line 76 of file tg3.h.

#define WAKE_MAGIC (1 << 5)

Definition at line 77 of file tg3.h.

#define WAKE_MAGICSECURE (1 << 6)

Definition at line 78 of file tg3.h.

#define TG3_64BIT_REG_HIGH 0x00UL

Definition at line 82 of file tg3.h.

Referenced by tg3_set_bdinfo(), and tg3_setup_hw().

#define TG3_64BIT_REG_LOW 0x04UL

Definition at line 83 of file tg3.h.

Referenced by tg3_ack_irqs(), tg3_disable_ints(), tg3_poll(), tg3_set_bdinfo(), tg3_setup_hw(), and tg3_transmit().

#define TG3_BDINFO_HOST_ADDR 0x0UL

Definition at line 86 of file tg3.h.

Referenced by tg3_set_bdinfo(), and tg3_setup_hw().

#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL

Definition at line 87 of file tg3.h.

Referenced by tg3_set_bdinfo(), and tg3_setup_hw().

#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001

Definition at line 88 of file tg3.h.

#define BDINFO_FLAGS_DISABLED 0x00000002

Definition at line 89 of file tg3.h.

Referenced by tg3_setup_hw().

#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000

Definition at line 90 of file tg3.h.

#define BDINFO_FLAGS_MAXLEN_SHIFT 16

Definition at line 91 of file tg3.h.

Referenced by tg3_setup_hw().

#define TG3_BDINFO_NIC_ADDR 0xcUL

Definition at line 92 of file tg3.h.

Referenced by tg3_set_bdinfo(), and tg3_setup_hw().

#define TG3_BDINFO_SIZE 0x10UL

Definition at line 93 of file tg3.h.

Referenced by tg3_setup_hw().

#define RX_COPY_THRESHOLD 256

Definition at line 95 of file tg3.h.

#define RX_STD_MAX_SIZE 1536

Definition at line 97 of file tg3.h.

Referenced by tg3_setup_hw().

#define RX_STD_MAX_SIZE_5705 512

Definition at line 98 of file tg3.h.

Referenced by tg3_setup_hw().

#define RX_JUMBO_MAX_SIZE 0xdeadbeef

Definition at line 99 of file tg3.h.

#define TG3PCI_VENDOR 0x00000000

Definition at line 102 of file tg3.h.

#define TG3PCI_VENDOR_BROADCOM 0x14e4

Definition at line 103 of file tg3.h.

#define TG3PCI_DEVICE 0x00000002

Definition at line 104 of file tg3.h.

#define TG3PCI_DEVICE_TIGON3_1 0x1644

Definition at line 105 of file tg3.h.

#define TG3PCI_DEVICE_TIGON3_2 0x1645

Definition at line 106 of file tg3.h.

#define TG3PCI_DEVICE_TIGON3_3 0x1646

Definition at line 107 of file tg3.h.

#define TG3PCI_DEVICE_TIGON3_4 0x1647

Definition at line 108 of file tg3.h.

#define TG3PCI_COMMAND 0x00000004

Definition at line 109 of file tg3.h.

#define TG3PCI_STATUS 0x00000006

Definition at line 110 of file tg3.h.

#define TG3PCI_CCREVID 0x00000008

Definition at line 111 of file tg3.h.

#define TG3PCI_CACHELINESZ 0x0000000c

Definition at line 112 of file tg3.h.

#define TG3PCI_LATTIMER 0x0000000d

Definition at line 113 of file tg3.h.

#define TG3PCI_HEADERTYPE 0x0000000e

Definition at line 114 of file tg3.h.

#define TG3PCI_BIST 0x0000000f

Definition at line 115 of file tg3.h.

#define TG3PCI_BASE0_LOW 0x00000010

Definition at line 116 of file tg3.h.

#define TG3PCI_BASE0_HIGH 0x00000014

Definition at line 117 of file tg3.h.

#define TG3PCI_SUBSYSVENID 0x0000002c

Definition at line 119 of file tg3.h.

#define TG3PCI_SUBSYSID 0x0000002e

Definition at line 120 of file tg3.h.

#define TG3PCI_ROMADDR 0x00000030

Definition at line 121 of file tg3.h.

#define TG3PCI_CAPLIST 0x00000034

Definition at line 122 of file tg3.h.

#define TG3PCI_IRQ_LINE 0x0000003c

Definition at line 124 of file tg3.h.

#define TG3PCI_IRQ_PIN 0x0000003d

Definition at line 125 of file tg3.h.

#define TG3PCI_MIN_GNT 0x0000003e

Definition at line 126 of file tg3.h.

#define TG3PCI_MAX_LAT 0x0000003f

Definition at line 127 of file tg3.h.

#define TG3PCI_X_CAPS 0x00000040

Definition at line 128 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_setup_hw().

#define PCIX_CAPS_RELAXED_ORDERING 0x00020000

Definition at line 129 of file tg3.h.

Referenced by tg3_chip_reset().

#define PCIX_CAPS_SPLIT_MASK 0x00700000

Definition at line 130 of file tg3.h.

Referenced by tg3_setup_hw().

#define PCIX_CAPS_SPLIT_SHIFT 20

Definition at line 131 of file tg3.h.

Referenced by tg3_setup_hw().

#define PCIX_CAPS_BURST_MASK 0x000c0000

Definition at line 132 of file tg3.h.

Referenced by tg3_setup_hw().

#define PCIX_CAPS_BURST_SHIFT 18

Definition at line 133 of file tg3.h.

Referenced by tg3_setup_hw().

#define PCIX_CAPS_MAX_BURST_CPIOB 2

Definition at line 134 of file tg3.h.

Referenced by tg3_setup_hw().

#define TG3PCI_PM_CAP_PTR 0x00000041

Definition at line 135 of file tg3.h.

#define TG3PCI_X_COMMAND 0x00000042

Definition at line 136 of file tg3.h.

#define TG3PCI_X_STATUS 0x00000044

Definition at line 137 of file tg3.h.

#define TG3PCI_PM_CAP_ID 0x00000048

Definition at line 138 of file tg3.h.

#define TG3PCI_VPD_CAP_PTR 0x00000049

Definition at line 139 of file tg3.h.

#define TG3PCI_PM_CAPS 0x0000004a

Definition at line 140 of file tg3.h.

#define TG3PCI_PM_CTRL_STAT 0x0000004c

Definition at line 141 of file tg3.h.

#define TG3PCI_BR_SUPP_EXT 0x0000004e

Definition at line 142 of file tg3.h.

#define TG3PCI_PM_DATA 0x0000004f

Definition at line 143 of file tg3.h.

#define TG3PCI_VPD_CAP_ID 0x00000050

Definition at line 144 of file tg3.h.

#define TG3PCI_MSI_CAP_PTR 0x00000051

Definition at line 145 of file tg3.h.

#define TG3PCI_VPD_ADDR_FLAG 0x00000052

Definition at line 146 of file tg3.h.

#define VPD_ADDR_FLAG_WRITE 0x00008000

Definition at line 147 of file tg3.h.

#define TG3PCI_VPD_DATA 0x00000054

Definition at line 148 of file tg3.h.

#define TG3PCI_MSI_CAP_ID 0x00000058

Definition at line 149 of file tg3.h.

#define TG3PCI_NXT_CAP_PTR 0x00000059

Definition at line 150 of file tg3.h.

#define TG3PCI_MSI_CTRL 0x0000005a

Definition at line 151 of file tg3.h.

#define TG3PCI_MSI_ADDR_LOW 0x0000005c

Definition at line 152 of file tg3.h.

#define TG3PCI_MSI_ADDR_HIGH 0x00000060

Definition at line 153 of file tg3.h.

#define TG3PCI_MSI_DATA 0x00000064

Definition at line 154 of file tg3.h.

#define TG3PCI_MISC_HOST_CTRL 0x00000068

Definition at line 156 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_disable_ints(), tg3_get_invariants(), and tg3_set_power_state_0().

#define MISC_HOST_CTRL_CLEAR_INT 0x00000001

Definition at line 157 of file tg3.h.

#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002

Definition at line 158 of file tg3.h.

Referenced by tg3_disable_ints(), and tg3_probe().

#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004

Definition at line 159 of file tg3.h.

#define MISC_HOST_CTRL_WORD_SWAP 0x00000008

Definition at line 160 of file tg3.h.

Referenced by tg3_probe().

#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010

Definition at line 161 of file tg3.h.

Referenced by tg3_probe().

#define MISC_HOST_CTRL_CLKREG_RW 0x00000020

Definition at line 162 of file tg3.h.

#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040

Definition at line 163 of file tg3.h.

#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080

Definition at line 164 of file tg3.h.

Referenced by tg3_probe().

#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100

Definition at line 165 of file tg3.h.

#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200

Definition at line 166 of file tg3.h.

#define MISC_HOST_CTRL_CHIPREV 0xffff0000

Definition at line 167 of file tg3.h.

Referenced by tg3_get_invariants().

#define MISC_HOST_CTRL_CHIPREV_SHIFT 16

Definition at line 168 of file tg3.h.

Referenced by tg3_get_invariants().

#define GET_CHIP_REV_ID ( MISC_HOST_CTRL )

Value:

(((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
          MISC_HOST_CTRL_CHIPREV_SHIFT)

Definition at line 169 of file tg3.h.

#define CHIPREV_ID_5700_A0 0x7000

Definition at line 172 of file tg3.h.

#define CHIPREV_ID_5700_A1 0x7001

Definition at line 173 of file tg3.h.

#define CHIPREV_ID_5700_B0 0x7100

Definition at line 174 of file tg3.h.

#define CHIPREV_ID_5700_B1 0x7101

Definition at line 175 of file tg3.h.

#define CHIPREV_ID_5700_B3 0x7102

Definition at line 176 of file tg3.h.

#define CHIPREV_ID_5700_ALTIMA 0x7104

Definition at line 177 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define CHIPREV_ID_5700_C0 0x7200

Definition at line 178 of file tg3.h.

#define CHIPREV_ID_5701_A0 0x0000

Definition at line 179 of file tg3.h.

Referenced by tg3_phy_copper_begin(), tg3_phy_probe(), tg3_setup_copper_phy(), and tg3_setup_hw().

#define CHIPREV_ID_5701_B0 0x0100

Definition at line 180 of file tg3.h.

Referenced by tg3_phy_copper_begin(), tg3_phy_probe(), and tg3_setup_copper_phy().

#define CHIPREV_ID_5701_B2 0x0102

Definition at line 181 of file tg3.h.

#define CHIPREV_ID_5701_B5 0x0105

Definition at line 182 of file tg3.h.

#define CHIPREV_ID_5703_A0 0x1000

Definition at line 183 of file tg3.h.

#define CHIPREV_ID_5703_A1 0x1001

Definition at line 184 of file tg3.h.

Referenced by tg3_setup_hw().

#define CHIPREV_ID_5703_A2 0x1002

Definition at line 185 of file tg3.h.

#define CHIPREV_ID_5703_A3 0x1003

Definition at line 186 of file tg3.h.

#define CHIPREV_ID_5704_A0 0x2000

Definition at line 187 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), and tg3_setup_hw().

#define CHIPREV_ID_5704_A1 0x2001

Definition at line 188 of file tg3.h.

#define CHIPREV_ID_5704_A2 0x2002

Definition at line 189 of file tg3.h.

#define CHIPREV_ID_5705_A0 0x3000

Definition at line 190 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_setup_copper_phy(), and tg3_setup_hw().

#define CHIPREV_ID_5705_A1 0x3001

Definition at line 191 of file tg3.h.

Referenced by tg3_get_invariants().

#define CHIPREV_ID_5705_A2 0x3002

Definition at line 192 of file tg3.h.

#define CHIPREV_ID_5705_A3 0x3003

Definition at line 193 of file tg3.h.

#define CHIPREV_ID_5721 0x4101

Definition at line 194 of file tg3.h.

Referenced by tg3_setup_hw().

#define CHIPREV_ID_5750_A0 0x4000

Definition at line 195 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_restart_fw().

#define CHIPREV_ID_5750_A1 0x4001

Definition at line 196 of file tg3.h.

#define CHIPREV_ID_5750_A3 0x4003

Definition at line 197 of file tg3.h.

#define GET_ASIC_REV ( CHIP_REV_ID ) ((CHIP_REV_ID) >> 12)

Definition at line 198 of file tg3.h.

Referenced by __tg3_set_mac_addr(), tg3_chip_reset(), tg3_get_invariants(), tg3_nvram_init(), tg3_phy_probe(), tg3_phy_reset(), tg3_restart_fw(), tg3_set_bdinfo(), tg3_setup_copper_phy(), tg3_setup_dma(), tg3_setup_hw(), tg3_stop_block(), and tg3_switch_clocks().

#define ASIC_REV_5700 0x07

Definition at line 199 of file tg3.h.

Referenced by __tg3_set_mac_addr(), tg3_get_invariants(), tg3_nvram_init(), tg3_setup_copper_phy(), and tg3_setup_hw().

#define ASIC_REV_5701 0x00

Definition at line 200 of file tg3.h.

Referenced by __tg3_set_mac_addr(), and tg3_nvram_init().

#define ASIC_REV_5703 0x01

Definition at line 201 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_phy_probe(), tg3_phy_reset(), tg3_setup_copper_phy(), tg3_setup_dma(), and tg3_setup_hw().

#define ASIC_REV_5704 0x02

Definition at line 202 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_phy_probe(), tg3_phy_reset(), tg3_setup_copper_phy(), tg3_setup_dma(), and tg3_setup_hw().

#define ASIC_REV_5705 0x03

Definition at line 203 of file tg3.h.

Referenced by __tg3_set_mac_addr(), tg3_chip_reset(), tg3_get_invariants(), tg3_phy_probe(), tg3_phy_reset(), tg3_set_bdinfo(), tg3_setup_dma(), tg3_setup_hw(), tg3_stop_block(), and tg3_switch_clocks().

#define ASIC_REV_5750 0x04

Definition at line 204 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), tg3_phy_reset(), tg3_setup_hw(), and tg3_switch_clocks().

#define ASIC_REV_5787 0x0b

Definition at line 205 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_restart_fw(), tg3_setup_hw(), and tg3_stop_block().

#define GET_CHIP_REV ( CHIP_REV_ID ) ((CHIP_REV_ID) >> 8)

Definition at line 206 of file tg3.h.

#define CHIPREV_5700_AX 0x70

Definition at line 207 of file tg3.h.

#define CHIPREV_5700_BX 0x71

Definition at line 208 of file tg3.h.

#define CHIPREV_5700_CX 0x72

Definition at line 209 of file tg3.h.

#define CHIPREV_5701_AX 0x00

Definition at line 210 of file tg3.h.

#define GET_METAL_REV ( CHIP_REV_ID ) ((CHIP_REV_ID) & 0xff)

Definition at line 211 of file tg3.h.

#define METAL_REV_A0 0x00

Definition at line 212 of file tg3.h.

#define METAL_REV_A1 0x01

Definition at line 213 of file tg3.h.

#define METAL_REV_B0 0x00

Definition at line 214 of file tg3.h.

#define METAL_REV_B1 0x01

Definition at line 215 of file tg3.h.

#define METAL_REV_B2 0x02

Definition at line 216 of file tg3.h.

#define TG3PCI_DMA_RW_CTRL 0x0000006c

Definition at line 217 of file tg3.h.

Referenced by tg3_setup_dma(), and tg3_setup_hw().

#define DMA_RWCTRL_MIN_DMA 0x000000ff

Definition at line 218 of file tg3.h.

Referenced by tg3_setup_dma().

#define DMA_RWCTRL_MIN_DMA_SHIFT 0

Definition at line 219 of file tg3.h.

Referenced by tg3_setup_dma().

#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700

Definition at line 220 of file tg3.h.

#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000

Definition at line 221 of file tg3.h.

#define DMA_RWCTRL_READ_BNDRY_16 0x00000100

Definition at line 222 of file tg3.h.

#define DMA_RWCTRL_READ_BNDRY_32 0x00000200

Definition at line 223 of file tg3.h.

#define DMA_RWCTRL_READ_BNDRY_64 0x00000300

Definition at line 224 of file tg3.h.

#define DMA_RWCTRL_READ_BNDRY_128 0x00000400

Definition at line 225 of file tg3.h.

#define DMA_RWCTRL_READ_BNDRY_256 0x00000500

Definition at line 226 of file tg3.h.

#define DMA_RWCTRL_READ_BNDRY_512 0x00000600

Definition at line 227 of file tg3.h.

#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700

Definition at line 228 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800

Definition at line 229 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000

Definition at line 230 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800

Definition at line 231 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000

Definition at line 232 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800

Definition at line 233 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000

Definition at line 234 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800

Definition at line 235 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000

Definition at line 236 of file tg3.h.

#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800

Definition at line 237 of file tg3.h.

#define DMA_RWCTRL_ONE_DMA 0x00004000

Definition at line 238 of file tg3.h.

Referenced by tg3_setup_dma().

#define DMA_RWCTRL_READ_WATER 0x00070000

Definition at line 239 of file tg3.h.

#define DMA_RWCTRL_READ_WATER_SHIFT 16

Definition at line 240 of file tg3.h.

Referenced by tg3_setup_dma().

#define DMA_RWCTRL_WRITE_WATER 0x00380000

Definition at line 241 of file tg3.h.

#define DMA_RWCTRL_WRITE_WATER_SHIFT 19

Definition at line 242 of file tg3.h.

Referenced by tg3_setup_dma().

#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000

Definition at line 243 of file tg3.h.

#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000

Definition at line 244 of file tg3.h.

Referenced by tg3_setup_dma().

#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000

Definition at line 245 of file tg3.h.

#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24

Definition at line 246 of file tg3.h.

Referenced by tg3_setup_dma().

#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000

Definition at line 247 of file tg3.h.

#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28

Definition at line 248 of file tg3.h.

Referenced by tg3_setup_dma().

#define TG3PCI_PCISTATE 0x00000070

Definition at line 249 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), and tg3_setup_hw().

#define PCISTATE_FORCE_RESET 0x00000001

Definition at line 250 of file tg3.h.

#define PCISTATE_INT_NOT_ACTIVE 0x00000002

Definition at line 251 of file tg3.h.

#define PCISTATE_CONV_PCI_MODE 0x00000004

Definition at line 252 of file tg3.h.

Referenced by tg3_get_invariants().

#define PCISTATE_BUS_SPEED_HIGH 0x00000008

Definition at line 253 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_setup_hw().

#define PCISTATE_BUS_32BIT 0x00000010

Definition at line 254 of file tg3.h.

Referenced by tg3_get_invariants().

#define PCISTATE_ROM_ENABLE 0x00000020

Definition at line 255 of file tg3.h.

Referenced by tg3_chip_reset().

#define PCISTATE_ROM_RETRY_ENABLE 0x00000040

Definition at line 256 of file tg3.h.

Referenced by tg3_chip_reset().

#define PCISTATE_FLAT_VIEW 0x00000100

Definition at line 257 of file tg3.h.

#define PCISTATE_RETRY_SAME_DMA 0x00002000

Definition at line 258 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), and tg3_setup_hw().

#define TG3PCI_CLOCK_CTRL 0x00000074

Definition at line 259 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_setup_dma(), tg3_setup_hw(), and tg3_switch_clocks().

#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200

Definition at line 260 of file tg3.h.

#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400

Definition at line 261 of file tg3.h.

#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800

Definition at line 262 of file tg3.h.

#define CLOCK_CTRL_ALTCLK 0x00001000

Definition at line 263 of file tg3.h.

Referenced by tg3_switch_clocks().

#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000

Definition at line 264 of file tg3.h.

#define CLOCK_CTRL_44MHZ_CORE 0x00040000

Definition at line 265 of file tg3.h.

Referenced by tg3_switch_clocks().

#define CLOCK_CTRL_625_CORE 0x00100000

Definition at line 266 of file tg3.h.

#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000

Definition at line 267 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_switch_clocks().

#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000

Definition at line 268 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_switch_clocks().

#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000

Definition at line 269 of file tg3.h.

Referenced by tg3_setup_hw().

#define TG3PCI_REG_BASE_ADDR 0x00000078

Definition at line 270 of file tg3.h.

Referenced by tg3_write_indirect_reg32().

#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c

Definition at line 271 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_read_mem(), tg3_setup_hw(), and tg3_write_mem().

#define TG3PCI_REG_DATA 0x00000080

Definition at line 272 of file tg3.h.

Referenced by tg3_write_indirect_reg32().

#define TG3PCI_MEM_WIN_DATA 0x00000084

Definition at line 273 of file tg3.h.

Referenced by tg3_read_mem(), and tg3_write_mem().

#define TG3PCI_MODE_CTRL 0x00000088

Definition at line 274 of file tg3.h.

#define TG3PCI_MISC_CFG 0x0000008c

Definition at line 275 of file tg3.h.

#define TG3PCI_MISC_LOCAL_CTRL 0x00000090

Definition at line 276 of file tg3.h.

#define TG3PCI_STD_RING_PROD_IDX 0x00000098

Definition at line 278 of file tg3.h.

#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0

Definition at line 279 of file tg3.h.

#define TG3PCI_SND_PROD_IDX 0x000000a8

Definition at line 280 of file tg3.h.

#define MAILBOX_INTERRUPT_0 0x00000200

Definition at line 286 of file tg3.h.

Referenced by tg3_ack_irqs(), tg3_disable_ints(), and tg3_setup_hw().

#define MAILBOX_INTERRUPT_1 0x00000208

Definition at line 287 of file tg3.h.

#define MAILBOX_INTERRUPT_2 0x00000210

Definition at line 288 of file tg3.h.

#define MAILBOX_INTERRUPT_3 0x00000218

Definition at line 289 of file tg3.h.

#define MAILBOX_GENERAL_0 0x00000220

Definition at line 290 of file tg3.h.

#define MAILBOX_GENERAL_1 0x00000228

Definition at line 291 of file tg3.h.

#define MAILBOX_GENERAL_2 0x00000230

Definition at line 292 of file tg3.h.

#define MAILBOX_GENERAL_3 0x00000238

Definition at line 293 of file tg3.h.

#define MAILBOX_GENERAL_4 0x00000240

Definition at line 294 of file tg3.h.

#define MAILBOX_GENERAL_5 0x00000248

Definition at line 295 of file tg3.h.

#define MAILBOX_GENERAL_6 0x00000250

Definition at line 296 of file tg3.h.

#define MAILBOX_GENERAL_7 0x00000258

Definition at line 297 of file tg3.h.

#define MAILBOX_RELOAD_STAT 0x00000260

Definition at line 298 of file tg3.h.

#define MAILBOX_RCV_STD_PROD_IDX 0x00000268

Definition at line 299 of file tg3.h.

Referenced by tg3_poll(), and tg3_setup_hw().

#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270

Definition at line 300 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278

Definition at line 301 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_0 0x00000280

Definition at line 302 of file tg3.h.

Referenced by tg3_poll(), and tg3_setup_hw().

#define MAILBOX_RCVRET_CON_IDX_1 0x00000288

Definition at line 303 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_2 0x00000290

Definition at line 304 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_3 0x00000298

Definition at line 305 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0

Definition at line 306 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8

Definition at line 307 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0

Definition at line 308 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8

Definition at line 309 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0

Definition at line 310 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8

Definition at line 311 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0

Definition at line 312 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8

Definition at line 313 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0

Definition at line 314 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8

Definition at line 315 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0

Definition at line 316 of file tg3.h.

#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8

Definition at line 317 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300

Definition at line 318 of file tg3.h.

Referenced by tg3_setup_hw(), and tg3_transmit().

#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308

Definition at line 319 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310

Definition at line 320 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318

Definition at line 321 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320

Definition at line 322 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328

Definition at line 323 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330

Definition at line 324 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338

Definition at line 325 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340

Definition at line 326 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348

Definition at line 327 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350

Definition at line 328 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358

Definition at line 329 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360

Definition at line 330 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368

Definition at line 331 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370

Definition at line 332 of file tg3.h.

#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378

Definition at line 333 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380

Definition at line 334 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388

Definition at line 335 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390

Definition at line 336 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398

Definition at line 337 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0

Definition at line 338 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8

Definition at line 339 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0

Definition at line 340 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8

Definition at line 341 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0

Definition at line 342 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8

Definition at line 343 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0

Definition at line 344 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8

Definition at line 345 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0

Definition at line 346 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8

Definition at line 347 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0

Definition at line 348 of file tg3.h.

#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8

Definition at line 349 of file tg3.h.

#define MAC_MODE 0x00000400

Definition at line 352 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_fiber_aneg_smachine(), tg3_poll_link(), tg3_setup_copper_phy(), tg3_setup_fiber_phy(), and tg3_setup_hw().

#define MAC_MODE_RESET 0x00000001

Definition at line 353 of file tg3.h.

#define MAC_MODE_HALF_DUPLEX 0x00000002

Definition at line 354 of file tg3.h.

Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define MAC_MODE_PORT_MODE_MASK 0x0000000c

Definition at line 355 of file tg3.h.

Referenced by tg3_poll_link(), tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define MAC_MODE_PORT_MODE_TBI 0x0000000c

Definition at line 356 of file tg3.h.

Referenced by tg3_setup_fiber_phy(), and tg3_setup_hw().

#define MAC_MODE_PORT_MODE_GMII 0x00000008

Definition at line 357 of file tg3.h.

Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define MAC_MODE_PORT_MODE_MII 0x00000004

Definition at line 358 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define MAC_MODE_PORT_MODE_NONE 0x00000000

Definition at line 359 of file tg3.h.

#define MAC_MODE_PORT_INT_LPBACK 0x00000010

Definition at line 360 of file tg3.h.

#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080

Definition at line 361 of file tg3.h.

#define MAC_MODE_TX_BURSTING 0x00000100

Definition at line 362 of file tg3.h.

#define MAC_MODE_MAX_DEFER 0x00000200

Definition at line 363 of file tg3.h.

#define MAC_MODE_LINK_POLARITY 0x00000400

Definition at line 364 of file tg3.h.

Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define MAC_MODE_RXSTAT_ENABLE 0x00000800

Definition at line 365 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_MODE_RXSTAT_CLEAR 0x00001000

Definition at line 366 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_MODE_RXSTAT_FLUSH 0x00002000

Definition at line 367 of file tg3.h.

#define MAC_MODE_TXSTAT_ENABLE 0x00004000

Definition at line 368 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_MODE_TXSTAT_CLEAR 0x00008000

Definition at line 369 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_MODE_TXSTAT_FLUSH 0x00010000

Definition at line 370 of file tg3.h.

#define MAC_MODE_SEND_CONFIGS 0x00020000

Definition at line 371 of file tg3.h.

Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().

#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000

Definition at line 372 of file tg3.h.

#define MAC_MODE_ACPI_ENABLE 0x00080000

Definition at line 373 of file tg3.h.

#define MAC_MODE_MIP_ENABLE 0x00100000

Definition at line 374 of file tg3.h.

#define MAC_MODE_TDE_ENABLE 0x00200000

Definition at line 375 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define MAC_MODE_RDE_ENABLE 0x00400000

Definition at line 376 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_MODE_FHDE_ENABLE 0x00800000

Definition at line 377 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_STATUS 0x00000404

Definition at line 378 of file tg3.h.

Referenced by tg3_fiber_aneg_smachine(), tg3_poll_link(), tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define MAC_STATUS_PCS_SYNCED 0x00000001

Definition at line 379 of file tg3.h.

Referenced by tg3_poll_link(), and tg3_setup_fiber_phy().

#define MAC_STATUS_SIGNAL_DET 0x00000002

Definition at line 380 of file tg3.h.

#define MAC_STATUS_RCVD_CFG 0x00000004

Definition at line 381 of file tg3.h.

Referenced by tg3_fiber_aneg_smachine().

#define MAC_STATUS_CFG_CHANGED 0x00000008

Definition at line 382 of file tg3.h.

Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define MAC_STATUS_SYNC_CHANGED 0x00000010

Definition at line 383 of file tg3.h.

Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define MAC_STATUS_PORT_DEC_ERR 0x00000400

Definition at line 384 of file tg3.h.

#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000

Definition at line 385 of file tg3.h.

Referenced by tg3_poll_link(), and tg3_setup_copper_phy().

#define MAC_STATUS_MI_COMPLETION 0x00400000

Definition at line 386 of file tg3.h.

#define MAC_STATUS_MI_INTERRUPT 0x00800000

Definition at line 387 of file tg3.h.

#define MAC_STATUS_AP_ERROR 0x01000000

Definition at line 388 of file tg3.h.

#define MAC_STATUS_ODI_ERROR 0x02000000

Definition at line 389 of file tg3.h.

#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000

Definition at line 390 of file tg3.h.

#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000

Definition at line 391 of file tg3.h.

#define MAC_EVENT 0x00000408

Definition at line 392 of file tg3.h.

Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define MAC_EVENT_PORT_DECODE_ERR 0x00000400

Definition at line 393 of file tg3.h.

#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000

Definition at line 394 of file tg3.h.

#define MAC_EVENT_MI_COMPLETION 0x00400000

Definition at line 395 of file tg3.h.

#define MAC_EVENT_MI_INTERRUPT 0x00800000

Definition at line 396 of file tg3.h.

#define MAC_EVENT_AP_ERROR 0x01000000

Definition at line 397 of file tg3.h.

#define MAC_EVENT_ODI_ERROR 0x02000000

Definition at line 398 of file tg3.h.

#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000

Definition at line 399 of file tg3.h.

#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000

Definition at line 400 of file tg3.h.

#define MAC_LED_CTRL 0x0000040c

Definition at line 401 of file tg3.h.

Referenced by tg3_setup_copper_phy(), and tg3_setup_hw().

#define LED_CTRL_LNKLED_OVERRIDE 0x00000001

Definition at line 402 of file tg3.h.

#define LED_CTRL_1000MBPS_ON 0x00000002

Definition at line 403 of file tg3.h.

#define LED_CTRL_100MBPS_ON 0x00000004

Definition at line 404 of file tg3.h.

#define LED_CTRL_10MBPS_ON 0x00000008

Definition at line 405 of file tg3.h.

#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010

Definition at line 406 of file tg3.h.

#define LED_CTRL_TRAFFIC_BLINK 0x00000020

Definition at line 407 of file tg3.h.

#define LED_CTRL_TRAFFIC_LED 0x00000040

Definition at line 408 of file tg3.h.

#define LED_CTRL_1000MBPS_STATUS 0x00000080

Definition at line 409 of file tg3.h.

#define LED_CTRL_100MBPS_STATUS 0x00000100

Definition at line 410 of file tg3.h.

#define LED_CTRL_10MBPS_STATUS 0x00000200

Definition at line 411 of file tg3.h.

#define LED_CTRL_TRAFFIC_STATUS 0x00000400

Definition at line 412 of file tg3.h.

#define LED_CTRL_MAC_MODE 0x00000000

Definition at line 413 of file tg3.h.

#define LED_CTRL_PHY_MODE_1 0x00000800

Definition at line 414 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define LED_CTRL_PHY_MODE_2 0x00001000

Definition at line 415 of file tg3.h.

#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000

Definition at line 416 of file tg3.h.

#define LED_CTRL_BLINK_RATE_SHIFT 19

Definition at line 417 of file tg3.h.

#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000

Definition at line 418 of file tg3.h.

#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000

Definition at line 419 of file tg3.h.

#define MAC_ADDR_0_HIGH 0x00000410

Definition at line 420 of file tg3.h.

Referenced by __tg3_set_mac_addr(), and tg3_get_device_address().

#define MAC_ADDR_0_LOW 0x00000414

Definition at line 421 of file tg3.h.

Referenced by __tg3_set_mac_addr(), and tg3_get_device_address().

#define MAC_ADDR_1_HIGH 0x00000418

Definition at line 422 of file tg3.h.

#define MAC_ADDR_1_LOW 0x0000041c

Definition at line 423 of file tg3.h.

#define MAC_ADDR_2_HIGH 0x00000420

Definition at line 424 of file tg3.h.

#define MAC_ADDR_2_LOW 0x00000424

Definition at line 425 of file tg3.h.

#define MAC_ADDR_3_HIGH 0x00000428

Definition at line 426 of file tg3.h.

#define MAC_ADDR_3_LOW 0x0000042c

Definition at line 427 of file tg3.h.

#define MAC_ACPI_MBUF_PTR 0x00000430

Definition at line 428 of file tg3.h.

#define MAC_ACPI_LEN_OFFSET 0x00000434

Definition at line 429 of file tg3.h.

#define ACPI_LENOFF_LEN_MASK 0x0000ffff

Definition at line 430 of file tg3.h.

#define ACPI_LENOFF_LEN_SHIFT 0

Definition at line 431 of file tg3.h.

#define ACPI_LENOFF_OFF_MASK 0x0fff0000

Definition at line 432 of file tg3.h.

#define ACPI_LENOFF_OFF_SHIFT 16

Definition at line 433 of file tg3.h.

#define MAC_TX_BACKOFF_SEED 0x00000438

Definition at line 434 of file tg3.h.

Referenced by __tg3_set_mac_addr().

#define TX_BACKOFF_SEED_MASK 0x000003ff

Definition at line 435 of file tg3.h.

Referenced by __tg3_set_mac_addr().

#define MAC_RX_MTU_SIZE 0x0000043c

Definition at line 436 of file tg3.h.

Referenced by tg3_setup_hw().

#define RX_MTU_SIZE_MASK 0x0000ffff

Definition at line 437 of file tg3.h.

#define MAC_PCS_TEST 0x00000440

Definition at line 438 of file tg3.h.

#define PCS_TEST_PATTERN_MASK 0x000fffff

Definition at line 439 of file tg3.h.

#define PCS_TEST_PATTERN_SHIFT 0

Definition at line 440 of file tg3.h.

#define PCS_TEST_ENABLE 0x00100000

Definition at line 441 of file tg3.h.

#define MAC_TX_AUTO_NEG 0x00000444

Definition at line 442 of file tg3.h.

Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().

#define TX_AUTO_NEG_MASK 0x0000ffff

Definition at line 443 of file tg3.h.

#define TX_AUTO_NEG_SHIFT 0

Definition at line 444 of file tg3.h.

#define MAC_RX_AUTO_NEG 0x00000448

Definition at line 445 of file tg3.h.

Referenced by tg3_fiber_aneg_smachine().

#define RX_AUTO_NEG_MASK 0x0000ffff

Definition at line 446 of file tg3.h.

#define RX_AUTO_NEG_SHIFT 0

Definition at line 447 of file tg3.h.

#define MAC_MI_COM 0x0000044c

Definition at line 448 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define MI_COM_CMD_MASK 0x0c000000

Definition at line 449 of file tg3.h.

#define MI_COM_CMD_WRITE 0x04000000

Definition at line 450 of file tg3.h.

Referenced by tg3_writephy().

#define MI_COM_CMD_READ 0x08000000

Definition at line 451 of file tg3.h.

Referenced by tg3_readphy().

#define MI_COM_READ_FAILED 0x10000000

Definition at line 452 of file tg3.h.

#define MI_COM_START 0x20000000

Definition at line 453 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define MI_COM_BUSY 0x20000000

Definition at line 454 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define MI_COM_PHY_ADDR_MASK 0x03e00000

Definition at line 455 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define MI_COM_PHY_ADDR_SHIFT 21

Definition at line 456 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define MI_COM_REG_ADDR_MASK 0x001f0000

Definition at line 457 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define MI_COM_REG_ADDR_SHIFT 16

Definition at line 458 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define MI_COM_DATA_MASK 0x0000ffff

Definition at line 459 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define MAC_MI_STAT 0x00000450

Definition at line 460 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001

Definition at line 461 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_MI_MODE 0x00000454

Definition at line 462 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_readphy(), tg3_setup_copper_phy(), tg3_setup_hw(), and tg3_writephy().

#define MAC_MI_MODE_CLK_10MHZ 0x00000001

Definition at line 463 of file tg3.h.

#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002

Definition at line 464 of file tg3.h.

#define MAC_MI_MODE_AUTO_POLL 0x00000010

Definition at line 465 of file tg3.h.

Referenced by tg3_readphy(), tg3_setup_copper_phy(), and tg3_writephy().

#define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000

Definition at line 466 of file tg3.h.

#define MAC_MI_MODE_BASE 0x000c0000

Definition at line 467 of file tg3.h.

Referenced by tg3_probe(), tg3_setup_copper_phy(), and tg3_setup_hw().

#define MAC_AUTO_POLL_STATUS 0x00000458

Definition at line 468 of file tg3.h.

#define MAC_AUTO_POLL_ERROR 0x00000001

Definition at line 469 of file tg3.h.

#define MAC_TX_MODE 0x0000045c

Definition at line 470 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define TX_MODE_RESET 0x00000001

Definition at line 471 of file tg3.h.

#define TX_MODE_ENABLE 0x00000002

Definition at line 472 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010

Definition at line 473 of file tg3.h.

Referenced by tg3_setup_flow_control().

#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020

Definition at line 474 of file tg3.h.

#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040

Definition at line 475 of file tg3.h.

#define MAC_TX_STATUS 0x00000460

Definition at line 476 of file tg3.h.

#define TX_STATUS_XOFFED 0x00000001

Definition at line 477 of file tg3.h.

#define TX_STATUS_SENT_XOFF 0x00000002

Definition at line 478 of file tg3.h.

#define TX_STATUS_SENT_XON 0x00000004

Definition at line 479 of file tg3.h.

#define TX_STATUS_LINK_UP 0x00000008

Definition at line 480 of file tg3.h.

#define TX_STATUS_ODI_UNDERRUN 0x00000010

Definition at line 481 of file tg3.h.

#define TX_STATUS_ODI_OVERRUN 0x00000020

Definition at line 482 of file tg3.h.

#define MAC_TX_LENGTHS 0x00000464

Definition at line 483 of file tg3.h.

Referenced by tg3_setup_hw(), and tg3_setup_phy().

#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff

Definition at line 484 of file tg3.h.

#define TX_LENGTHS_SLOT_TIME_SHIFT 0

Definition at line 485 of file tg3.h.

Referenced by tg3_setup_hw(), and tg3_setup_phy().

#define TX_LENGTHS_IPG_MASK 0x00000f00

Definition at line 486 of file tg3.h.

#define TX_LENGTHS_IPG_SHIFT 8

Definition at line 487 of file tg3.h.

Referenced by tg3_setup_hw(), and tg3_setup_phy().

#define TX_LENGTHS_IPG_CRS_MASK 0x00003000

Definition at line 488 of file tg3.h.

#define TX_LENGTHS_IPG_CRS_SHIFT 12

Definition at line 489 of file tg3.h.

Referenced by tg3_setup_hw(), and tg3_setup_phy().

#define MAC_RX_MODE 0x00000468

Definition at line 490 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RX_MODE_RESET 0x00000001

Definition at line 491 of file tg3.h.

Referenced by tg3_setup_hw().

#define RX_MODE_ENABLE 0x00000002

Definition at line 492 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004

Definition at line 493 of file tg3.h.

Referenced by tg3_setup_flow_control().

#define RX_MODE_KEEP_MAC_CTRL 0x00000008

Definition at line 494 of file tg3.h.

#define RX_MODE_KEEP_PAUSE 0x00000010

Definition at line 495 of file tg3.h.

#define RX_MODE_ACCEPT_OVERSIZED 0x00000020

Definition at line 496 of file tg3.h.

#define RX_MODE_ACCEPT_RUNTS 0x00000040

Definition at line 497 of file tg3.h.

#define RX_MODE_LEN_CHECK 0x00000080

Definition at line 498 of file tg3.h.

#define RX_MODE_PROMISC 0x00000100

Definition at line 499 of file tg3.h.

#define RX_MODE_NO_CRC_CHECK 0x00000200

Definition at line 500 of file tg3.h.

#define RX_MODE_KEEP_VLAN_TAG 0x00000400

Definition at line 501 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RX_STATUS 0x0000046c

Definition at line 502 of file tg3.h.

#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001

Definition at line 503 of file tg3.h.

#define RX_STATUS_XOFF_RCVD 0x00000002

Definition at line 504 of file tg3.h.

#define RX_STATUS_XON_RCVD 0x00000004

Definition at line 505 of file tg3.h.

#define MAC_HASH_REG_0 0x00000470

Definition at line 506 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_HASH_REG_1 0x00000474

Definition at line 507 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_HASH_REG_2 0x00000478

Definition at line 508 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_HASH_REG_3 0x0000047c

Definition at line 509 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_0 0x00000480

Definition at line 510 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_0 0x00000484

Definition at line 511 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_1 0x00000488

Definition at line 512 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_1 0x0000048c

Definition at line 513 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_2 0x00000490

Definition at line 514 of file tg3.h.

#define MAC_RCV_VALUE_2 0x00000494

Definition at line 515 of file tg3.h.

#define MAC_RCV_RULE_3 0x00000498

Definition at line 516 of file tg3.h.

#define MAC_RCV_VALUE_3 0x0000049c

Definition at line 517 of file tg3.h.

#define MAC_RCV_RULE_4 0x000004a0

Definition at line 518 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_4 0x000004a4

Definition at line 519 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_5 0x000004a8

Definition at line 520 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_5 0x000004ac

Definition at line 521 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_6 0x000004b0

Definition at line 522 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_6 0x000004b4

Definition at line 523 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_7 0x000004b8

Definition at line 524 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_7 0x000004bc

Definition at line 525 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_8 0x000004c0

Definition at line 526 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_8 0x000004c4

Definition at line 527 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_9 0x000004c8

Definition at line 528 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_9 0x000004cc

Definition at line 529 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_10 0x000004d0

Definition at line 530 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_10 0x000004d4

Definition at line 531 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_11 0x000004d8

Definition at line 532 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_11 0x000004dc

Definition at line 533 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_12 0x000004e0

Definition at line 534 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_12 0x000004e4

Definition at line 535 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_13 0x000004e8

Definition at line 536 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_13 0x000004ec

Definition at line 537 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_14 0x000004f0

Definition at line 538 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_14 0x000004f4

Definition at line 539 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_15 0x000004f8

Definition at line 540 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_VALUE_15 0x000004fc

Definition at line 541 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCV_RULE_DISABLE_MASK 0x7fffffff

Definition at line 542 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_RCV_RULE_CFG 0x00000500

Definition at line 543 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008

Definition at line 544 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504

Definition at line 545 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_HASHREGU_0 0x00000520

Definition at line 547 of file tg3.h.

#define MAC_HASHREGU_1 0x00000524

Definition at line 548 of file tg3.h.

#define MAC_HASHREGU_2 0x00000528

Definition at line 549 of file tg3.h.

#define MAC_HASHREGU_3 0x0000052c

Definition at line 550 of file tg3.h.

#define MAC_EXTADDR_0_HIGH 0x00000530

Definition at line 551 of file tg3.h.

Referenced by __tg3_set_mac_addr().

#define MAC_EXTADDR_0_LOW 0x00000534

Definition at line 552 of file tg3.h.

Referenced by __tg3_set_mac_addr().

#define MAC_EXTADDR_1_HIGH 0x00000538

Definition at line 553 of file tg3.h.

#define MAC_EXTADDR_1_LOW 0x0000053c

Definition at line 554 of file tg3.h.

#define MAC_EXTADDR_2_HIGH 0x00000540

Definition at line 555 of file tg3.h.

#define MAC_EXTADDR_2_LOW 0x00000544

Definition at line 556 of file tg3.h.

#define MAC_EXTADDR_3_HIGH 0x00000548

Definition at line 557 of file tg3.h.

#define MAC_EXTADDR_3_LOW 0x0000054c

Definition at line 558 of file tg3.h.

#define MAC_EXTADDR_4_HIGH 0x00000550

Definition at line 559 of file tg3.h.

#define MAC_EXTADDR_4_LOW 0x00000554

Definition at line 560 of file tg3.h.

#define MAC_EXTADDR_5_HIGH 0x00000558

Definition at line 561 of file tg3.h.

#define MAC_EXTADDR_5_LOW 0x0000055c

Definition at line 562 of file tg3.h.

#define MAC_EXTADDR_6_HIGH 0x00000560

Definition at line 563 of file tg3.h.

#define MAC_EXTADDR_6_LOW 0x00000564

Definition at line 564 of file tg3.h.

#define MAC_EXTADDR_7_HIGH 0x00000568

Definition at line 565 of file tg3.h.

#define MAC_EXTADDR_7_LOW 0x0000056c

Definition at line 566 of file tg3.h.

#define MAC_EXTADDR_8_HIGH 0x00000570

Definition at line 567 of file tg3.h.

#define MAC_EXTADDR_8_LOW 0x00000574

Definition at line 568 of file tg3.h.

#define MAC_EXTADDR_9_HIGH 0x00000578

Definition at line 569 of file tg3.h.

#define MAC_EXTADDR_9_LOW 0x0000057c

Definition at line 570 of file tg3.h.

#define MAC_EXTADDR_10_HIGH 0x00000580

Definition at line 571 of file tg3.h.

#define MAC_EXTADDR_10_LOW 0x00000584

Definition at line 572 of file tg3.h.

#define MAC_EXTADDR_11_HIGH 0x00000588

Definition at line 573 of file tg3.h.

#define MAC_EXTADDR_11_LOW 0x0000058c

Definition at line 574 of file tg3.h.

#define MAC_SERDES_CFG 0x00000590

Definition at line 575 of file tg3.h.

Referenced by tg3_setup_hw().

#define MAC_SERDES_STAT 0x00000594

Definition at line 576 of file tg3.h.

#define MAC_TX_MAC_STATE_BASE 0x00000600

Definition at line 578 of file tg3.h.

#define MAC_RX_MAC_STATE_BASE 0x00000610

Definition at line 579 of file tg3.h.

#define MAC_TX_STATS_OCTETS 0x00000800

Definition at line 581 of file tg3.h.

#define MAC_TX_STATS_RESV1 0x00000804

Definition at line 582 of file tg3.h.

#define MAC_TX_STATS_COLLISIONS 0x00000808

Definition at line 583 of file tg3.h.

#define MAC_TX_STATS_XON_SENT 0x0000080c

Definition at line 584 of file tg3.h.

#define MAC_TX_STATS_XOFF_SENT 0x00000810

Definition at line 585 of file tg3.h.

#define MAC_TX_STATS_RESV2 0x00000814

Definition at line 586 of file tg3.h.

#define MAC_TX_STATS_MAC_ERRORS 0x00000818

Definition at line 587 of file tg3.h.

#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c

Definition at line 588 of file tg3.h.

#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820

Definition at line 589 of file tg3.h.

#define MAC_TX_STATS_DEFERRED 0x00000824

Definition at line 590 of file tg3.h.

#define MAC_TX_STATS_RESV3 0x00000828

Definition at line 591 of file tg3.h.

#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c

Definition at line 592 of file tg3.h.

#define MAC_TX_STATS_LATE_COL 0x00000830

Definition at line 593 of file tg3.h.

#define MAC_TX_STATS_RESV4_1 0x00000834

Definition at line 594 of file tg3.h.

#define MAC_TX_STATS_RESV4_2 0x00000838

Definition at line 595 of file tg3.h.

#define MAC_TX_STATS_RESV4_3 0x0000083c

Definition at line 596 of file tg3.h.

#define MAC_TX_STATS_RESV4_4 0x00000840

Definition at line 597 of file tg3.h.

#define MAC_TX_STATS_RESV4_5 0x00000844

Definition at line 598 of file tg3.h.

#define MAC_TX_STATS_RESV4_6 0x00000848

Definition at line 599 of file tg3.h.

#define MAC_TX_STATS_RESV4_7 0x0000084c

Definition at line 600 of file tg3.h.

#define MAC_TX_STATS_RESV4_8 0x00000850

Definition at line 601 of file tg3.h.

#define MAC_TX_STATS_RESV4_9 0x00000854

Definition at line 602 of file tg3.h.

#define MAC_TX_STATS_RESV4_10 0x00000858

Definition at line 603 of file tg3.h.

#define MAC_TX_STATS_RESV4_11 0x0000085c

Definition at line 604 of file tg3.h.

#define MAC_TX_STATS_RESV4_12 0x00000860

Definition at line 605 of file tg3.h.

#define MAC_TX_STATS_RESV4_13 0x00000864

Definition at line 606 of file tg3.h.

#define MAC_TX_STATS_RESV4_14 0x00000868

Definition at line 607 of file tg3.h.

#define MAC_TX_STATS_UCAST 0x0000086c

Definition at line 608 of file tg3.h.

#define MAC_TX_STATS_MCAST 0x00000870

Definition at line 609 of file tg3.h.

#define MAC_TX_STATS_BCAST 0x00000874

Definition at line 610 of file tg3.h.

#define MAC_TX_STATS_RESV5_1 0x00000878

Definition at line 611 of file tg3.h.

#define MAC_TX_STATS_RESV5_2 0x0000087c

Definition at line 612 of file tg3.h.

#define MAC_RX_STATS_OCTETS 0x00000880

Definition at line 613 of file tg3.h.

#define MAC_RX_STATS_RESV1 0x00000884

Definition at line 614 of file tg3.h.

#define MAC_RX_STATS_FRAGMENTS 0x00000888

Definition at line 615 of file tg3.h.

#define MAC_RX_STATS_UCAST 0x0000088c

Definition at line 616 of file tg3.h.

#define MAC_RX_STATS_MCAST 0x00000890

Definition at line 617 of file tg3.h.

#define MAC_RX_STATS_BCAST 0x00000894

Definition at line 618 of file tg3.h.

#define MAC_RX_STATS_FCS_ERRORS 0x00000898

Definition at line 619 of file tg3.h.

#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c

Definition at line 620 of file tg3.h.

#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0

Definition at line 621 of file tg3.h.

#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4

Definition at line 622 of file tg3.h.

#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8

Definition at line 623 of file tg3.h.

#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac

Definition at line 624 of file tg3.h.

#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0

Definition at line 625 of file tg3.h.

#define MAC_RX_STATS_JABBERS 0x000008b4

Definition at line 626 of file tg3.h.

#define MAC_RX_STATS_UNDERSIZE 0x000008b8

Definition at line 627 of file tg3.h.

#define SNDDATAI_MODE 0x00000c00

Definition at line 631 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDDATAI_MODE_RESET 0x00000001

Definition at line 632 of file tg3.h.

#define SNDDATAI_MODE_ENABLE 0x00000002

Definition at line 633 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004

Definition at line 634 of file tg3.h.

#define SNDDATAI_STATUS 0x00000c04

Definition at line 635 of file tg3.h.

#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004

Definition at line 636 of file tg3.h.

#define SNDDATAI_STATSCTRL 0x00000c08

Definition at line 637 of file tg3.h.

Referenced by tg3_setup_hw().

#define SNDDATAI_SCTRL_ENABLE 0x00000001

Definition at line 638 of file tg3.h.

Referenced by tg3_setup_hw().

#define SNDDATAI_SCTRL_FASTUPD 0x00000002

Definition at line 639 of file tg3.h.

Referenced by tg3_setup_hw().

#define SNDDATAI_SCTRL_CLEAR 0x00000004

Definition at line 640 of file tg3.h.

#define SNDDATAI_SCTRL_FLUSH 0x00000008

Definition at line 641 of file tg3.h.

#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010

Definition at line 642 of file tg3.h.

#define SNDDATAI_STATSENAB 0x00000c0c

Definition at line 643 of file tg3.h.

Referenced by tg3_setup_hw().

#define SNDDATAI_STATSINCMASK 0x00000c10

Definition at line 644 of file tg3.h.

#define SNDDATAI_COS_CNT_0 0x00000c80

Definition at line 646 of file tg3.h.

#define SNDDATAI_COS_CNT_1 0x00000c84

Definition at line 647 of file tg3.h.

#define SNDDATAI_COS_CNT_2 0x00000c88

Definition at line 648 of file tg3.h.

#define SNDDATAI_COS_CNT_3 0x00000c8c

Definition at line 649 of file tg3.h.

#define SNDDATAI_COS_CNT_4 0x00000c90

Definition at line 650 of file tg3.h.

#define SNDDATAI_COS_CNT_5 0x00000c94

Definition at line 651 of file tg3.h.

#define SNDDATAI_COS_CNT_6 0x00000c98

Definition at line 652 of file tg3.h.

#define SNDDATAI_COS_CNT_7 0x00000c9c

Definition at line 653 of file tg3.h.

#define SNDDATAI_COS_CNT_8 0x00000ca0

Definition at line 654 of file tg3.h.

#define SNDDATAI_COS_CNT_9 0x00000ca4

Definition at line 655 of file tg3.h.

#define SNDDATAI_COS_CNT_10 0x00000ca8

Definition at line 656 of file tg3.h.

#define SNDDATAI_COS_CNT_11 0x00000cac

Definition at line 657 of file tg3.h.

#define SNDDATAI_COS_CNT_12 0x00000cb0

Definition at line 658 of file tg3.h.

#define SNDDATAI_COS_CNT_13 0x00000cb4

Definition at line 659 of file tg3.h.

#define SNDDATAI_COS_CNT_14 0x00000cb8

Definition at line 660 of file tg3.h.

#define SNDDATAI_COS_CNT_15 0x00000cbc

Definition at line 661 of file tg3.h.

#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0

Definition at line 662 of file tg3.h.

#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4

Definition at line 663 of file tg3.h.

#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8

Definition at line 664 of file tg3.h.

#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc

Definition at line 665 of file tg3.h.

#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0

Definition at line 666 of file tg3.h.

#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4

Definition at line 667 of file tg3.h.

#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8

Definition at line 668 of file tg3.h.

#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc

Definition at line 669 of file tg3.h.

#define SNDDATAC_MODE 0x00001000

Definition at line 673 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDDATAC_MODE_RESET 0x00000001

Definition at line 674 of file tg3.h.

#define SNDDATAC_MODE_ENABLE 0x00000002

Definition at line 675 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDBDS_MODE 0x00001400

Definition at line 679 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDBDS_MODE_RESET 0x00000001

Definition at line 680 of file tg3.h.

#define SNDBDS_MODE_ENABLE 0x00000002

Definition at line 681 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDBDS_MODE_ATTN_ENABLE 0x00000004

Definition at line 682 of file tg3.h.

Referenced by tg3_setup_hw().

#define SNDBDS_STATUS 0x00001404

Definition at line 683 of file tg3.h.

#define SNDBDS_STATUS_ERROR_ATTN 0x00000004

Definition at line 684 of file tg3.h.

#define SNDBDS_HWDIAG 0x00001408

Definition at line 685 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_0 0x00001440

Definition at line 687 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_1 0x00001444

Definition at line 688 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_2 0x00001448

Definition at line 689 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_3 0x0000144c

Definition at line 690 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_4 0x00001450

Definition at line 691 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_5 0x00001454

Definition at line 692 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_6 0x00001458

Definition at line 693 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_7 0x0000145c

Definition at line 694 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_8 0x00001460

Definition at line 695 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_9 0x00001464

Definition at line 696 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_10 0x00001468

Definition at line 697 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_11 0x0000146c

Definition at line 698 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_12 0x00001470

Definition at line 699 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_13 0x00001474

Definition at line 700 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_14 0x00001478

Definition at line 701 of file tg3.h.

#define SNDBDS_SEL_CON_IDX_15 0x0000147c

Definition at line 702 of file tg3.h.

#define SNDBDI_MODE 0x00001800

Definition at line 706 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDBDI_MODE_RESET 0x00000001

Definition at line 707 of file tg3.h.

#define SNDBDI_MODE_ENABLE 0x00000002

Definition at line 708 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDBDI_MODE_ATTN_ENABLE 0x00000004

Definition at line 709 of file tg3.h.

Referenced by tg3_setup_hw().

#define SNDBDI_STATUS 0x00001804

Definition at line 710 of file tg3.h.

#define SNDBDI_STATUS_ERROR_ATTN 0x00000004

Definition at line 711 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_0 0x00001808

Definition at line 712 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_1 0x0000180c

Definition at line 713 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_2 0x00001810

Definition at line 714 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_3 0x00001814

Definition at line 715 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_4 0x00001818

Definition at line 716 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_5 0x0000181c

Definition at line 717 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_6 0x00001820

Definition at line 718 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_7 0x00001824

Definition at line 719 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_8 0x00001828

Definition at line 720 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_9 0x0000182c

Definition at line 721 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_10 0x00001830

Definition at line 722 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_11 0x00001834

Definition at line 723 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_12 0x00001838

Definition at line 724 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_13 0x0000183c

Definition at line 725 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_14 0x00001840

Definition at line 726 of file tg3.h.

#define SNDBDI_IN_PROD_IDX_15 0x00001844

Definition at line 727 of file tg3.h.

#define SNDBDC_MODE 0x00001c00

Definition at line 731 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDBDC_MODE_RESET 0x00000001

Definition at line 732 of file tg3.h.

#define SNDBDC_MODE_ENABLE 0x00000002

Definition at line 733 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SNDBDC_MODE_ATTN_ENABLE 0x00000004

Definition at line 734 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVLPC_MODE 0x00002000

Definition at line 738 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVLPC_MODE_RESET 0x00000001

Definition at line 739 of file tg3.h.

#define RCVLPC_MODE_ENABLE 0x00000002

Definition at line 740 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004

Definition at line 741 of file tg3.h.

#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008

Definition at line 742 of file tg3.h.

#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010

Definition at line 743 of file tg3.h.

#define RCVLPC_STATUS 0x00002004

Definition at line 744 of file tg3.h.

#define RCVLPC_STATUS_CLASS0 0x00000004

Definition at line 745 of file tg3.h.

#define RCVLPC_STATUS_MAPOOR 0x00000008

Definition at line 746 of file tg3.h.

#define RCVLPC_STATUS_STAT_OFLOW 0x00000010

Definition at line 747 of file tg3.h.

#define RCVLPC_LOCK 0x00002008

Definition at line 748 of file tg3.h.

#define RCVLPC_LOCK_REQ_MASK 0x0000ffff

Definition at line 749 of file tg3.h.

#define RCVLPC_LOCK_REQ_SHIFT 0

Definition at line 750 of file tg3.h.

#define RCVLPC_LOCK_GRANT_MASK 0xffff0000

Definition at line 751 of file tg3.h.

#define RCVLPC_LOCK_GRANT_SHIFT 16

Definition at line 752 of file tg3.h.

#define RCVLPC_NON_EMPTY_BITS 0x0000200c

Definition at line 753 of file tg3.h.

#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff

Definition at line 754 of file tg3.h.

#define RCVLPC_CONFIG 0x00002010

Definition at line 755 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVLPC_STATSCTRL 0x00002014

Definition at line 756 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVLPC_STATSCTRL_ENABLE 0x00000001

Definition at line 757 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVLPC_STATSCTRL_FASTUPD 0x00000002

Definition at line 758 of file tg3.h.

#define RCVLPC_STATS_ENABLE 0x00002018

Definition at line 759 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000

Definition at line 760 of file tg3.h.

#define RCVLPC_STATS_INCMASK 0x0000201c

Definition at line 761 of file tg3.h.

#define RCVLPC_SELLST_BASE 0x00002100

Definition at line 763 of file tg3.h.

#define SELLST_TAIL 0x00000004

Definition at line 764 of file tg3.h.

#define SELLST_CONT 0x00000008

Definition at line 765 of file tg3.h.

#define SELLST_UNUSED 0x0000000c

Definition at line 766 of file tg3.h.

#define RCVLPC_COS_CNTL_BASE 0x00002200

Definition at line 767 of file tg3.h.

#define RCVLPC_DROP_FILTER_CNT 0x00002240

Definition at line 768 of file tg3.h.

#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244

Definition at line 769 of file tg3.h.

#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248

Definition at line 770 of file tg3.h.

#define RCVLPC_NO_RCV_BD_CNT 0x0000224c

Definition at line 771 of file tg3.h.

#define RCVLPC_IN_DISCARDS_CNT 0x00002250

Definition at line 772 of file tg3.h.

#define RCVLPC_IN_ERRORS_CNT 0x00002254

Definition at line 773 of file tg3.h.

#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258

Definition at line 774 of file tg3.h.

#define RCVDBDI_MODE 0x00002400

Definition at line 778 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVDBDI_MODE_RESET 0x00000001

Definition at line 779 of file tg3.h.

#define RCVDBDI_MODE_ENABLE 0x00000002

Definition at line 780 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004

Definition at line 781 of file tg3.h.

#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008

Definition at line 782 of file tg3.h.

#define RCVDBDI_MODE_INV_RING_SZ 0x00000010

Definition at line 783 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVDBDI_STATUS 0x00002404

Definition at line 784 of file tg3.h.

#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004

Definition at line 785 of file tg3.h.

#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008

Definition at line 786 of file tg3.h.

#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010

Definition at line 787 of file tg3.h.

#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408

Definition at line 788 of file tg3.h.

#define RCVDBDI_JUMBO_BD 0x00002440

Definition at line 790 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVDBDI_STD_BD 0x00002450

Definition at line 791 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVDBDI_MINI_BD 0x00002460

Definition at line 792 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVDBDI_JUMBO_CON_IDX 0x00002470

Definition at line 793 of file tg3.h.

#define RCVDBDI_STD_CON_IDX 0x00002474

Definition at line 794 of file tg3.h.

#define RCVDBDI_MINI_CON_IDX 0x00002478

Definition at line 795 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_0 0x00002480

Definition at line 797 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_1 0x00002484

Definition at line 798 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_2 0x00002488

Definition at line 799 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_3 0x0000248c

Definition at line 800 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_4 0x00002490

Definition at line 801 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_5 0x00002494

Definition at line 802 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_6 0x00002498

Definition at line 803 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_7 0x0000249c

Definition at line 804 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_8 0x000024a0

Definition at line 805 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_9 0x000024a4

Definition at line 806 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_10 0x000024a8

Definition at line 807 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_11 0x000024ac

Definition at line 808 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_12 0x000024b0

Definition at line 809 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_13 0x000024b4

Definition at line 810 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_14 0x000024b8

Definition at line 811 of file tg3.h.

#define RCVDBDI_BD_PROD_IDX_15 0x000024bc

Definition at line 812 of file tg3.h.

#define RCVDBDI_HWDIAG 0x000024c0

Definition at line 813 of file tg3.h.

#define RCVDCC_MODE 0x00002800

Definition at line 817 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVDCC_MODE_RESET 0x00000001

Definition at line 818 of file tg3.h.

#define RCVDCC_MODE_ENABLE 0x00000002

Definition at line 819 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVDCC_MODE_ATTN_ENABLE 0x00000004

Definition at line 820 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVBDI_MODE 0x00002c00

Definition at line 824 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVBDI_MODE_RESET 0x00000001

Definition at line 825 of file tg3.h.

#define RCVBDI_MODE_ENABLE 0x00000002

Definition at line 826 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004

Definition at line 827 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVBDI_STATUS 0x00002c04

Definition at line 828 of file tg3.h.

#define RCVBDI_STATUS_RCB_ATTN 0x00000004

Definition at line 829 of file tg3.h.

#define RCVBDI_JUMBO_PROD_IDX 0x00002c08

Definition at line 830 of file tg3.h.

#define RCVBDI_STD_PROD_IDX 0x00002c0c

Definition at line 831 of file tg3.h.

#define RCVBDI_MINI_PROD_IDX 0x00002c10

Definition at line 832 of file tg3.h.

#define RCVBDI_MINI_THRESH 0x00002c14

Definition at line 833 of file tg3.h.

#define RCVBDI_STD_THRESH 0x00002c18

Definition at line 834 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVBDI_JUMBO_THRESH 0x00002c1c

Definition at line 835 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVCC_MODE 0x00003000

Definition at line 839 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVCC_MODE_RESET 0x00000001

Definition at line 840 of file tg3.h.

#define RCVCC_MODE_ENABLE 0x00000002

Definition at line 841 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVCC_MODE_ATTN_ENABLE 0x00000004

Definition at line 842 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVCC_STATUS 0x00003004

Definition at line 843 of file tg3.h.

#define RCVCC_STATUS_ERROR_ATTN 0x00000004

Definition at line 844 of file tg3.h.

#define RCVCC_JUMP_PROD_IDX 0x00003008

Definition at line 845 of file tg3.h.

#define RCVCC_STD_PROD_IDX 0x0000300c

Definition at line 846 of file tg3.h.

#define RCVCC_MINI_PROD_IDX 0x00003010

Definition at line 847 of file tg3.h.

#define RCVLSC_MODE 0x00003400

Definition at line 851 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_setup_hw(), and tg3_stop_block().

#define RCVLSC_MODE_RESET 0x00000001

Definition at line 852 of file tg3.h.

#define RCVLSC_MODE_ENABLE 0x00000002

Definition at line 853 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RCVLSC_MODE_ATTN_ENABLE 0x00000004

Definition at line 854 of file tg3.h.

Referenced by tg3_setup_hw().

#define RCVLSC_STATUS 0x00003404

Definition at line 855 of file tg3.h.

#define RCVLSC_STATUS_ERROR_ATTN 0x00000004

Definition at line 856 of file tg3.h.

#define MBFREE_MODE 0x00003800

Definition at line 860 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_setup_hw(), and tg3_stop_block().

#define MBFREE_MODE_RESET 0x00000001

Definition at line 861 of file tg3.h.

#define MBFREE_MODE_ENABLE 0x00000002

Definition at line 862 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define MBFREE_STATUS 0x00003804

Definition at line 863 of file tg3.h.

#define HOSTCC_MODE 0x00003c00

Definition at line 867 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define HOSTCC_MODE_RESET 0x00000001

Definition at line 868 of file tg3.h.

#define HOSTCC_MODE_ENABLE 0x00000002

Definition at line 869 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define HOSTCC_MODE_ATTN 0x00000004

Definition at line 870 of file tg3.h.

#define HOSTCC_MODE_NOW 0x00000008

Definition at line 871 of file tg3.h.

#define HOSTCC_MODE_FULL_STATUS 0x00000000

Definition at line 872 of file tg3.h.

#define HOSTCC_MODE_64BYTE 0x00000080

Definition at line 873 of file tg3.h.

#define HOSTCC_MODE_32BYTE 0x00000100

Definition at line 874 of file tg3.h.

#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200

Definition at line 875 of file tg3.h.

#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400

Definition at line 876 of file tg3.h.

#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800

Definition at line 877 of file tg3.h.

#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000

Definition at line 878 of file tg3.h.

#define HOSTCC_STATUS 0x00003c04

Definition at line 879 of file tg3.h.

#define HOSTCC_STATUS_ERROR_ATTN 0x00000004

Definition at line 880 of file tg3.h.

#define HOSTCC_RXCOL_TICKS 0x00003c08

Definition at line 881 of file tg3.h.

Referenced by tg3_setup_hw().

#define LOW_RXCOL_TICKS 0x00000032

Definition at line 882 of file tg3.h.

#define DEFAULT_RXCOL_TICKS 0x00000048

Definition at line 883 of file tg3.h.

#define HIGH_RXCOL_TICKS 0x00000096

Definition at line 884 of file tg3.h.

#define HOSTCC_TXCOL_TICKS 0x00003c0c

Definition at line 885 of file tg3.h.

Referenced by tg3_setup_hw().

#define LOW_TXCOL_TICKS 0x00000096

Definition at line 886 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_TXCOL_TICKS 0x0000012c

Definition at line 887 of file tg3.h.

#define HIGH_TXCOL_TICKS 0x00000145

Definition at line 888 of file tg3.h.

#define HOSTCC_RXMAX_FRAMES 0x00003c10

Definition at line 889 of file tg3.h.

Referenced by tg3_setup_hw().

#define LOW_RXMAX_FRAMES 0x00000005

Definition at line 890 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_RXMAX_FRAMES 0x00000008

Definition at line 891 of file tg3.h.

#define HIGH_RXMAX_FRAMES 0x00000012

Definition at line 892 of file tg3.h.

#define HOSTCC_TXMAX_FRAMES 0x00003c14

Definition at line 893 of file tg3.h.

Referenced by tg3_setup_hw().

#define LOW_TXMAX_FRAMES 0x00000035

Definition at line 894 of file tg3.h.

#define DEFAULT_TXMAX_FRAMES 0x0000004b

Definition at line 895 of file tg3.h.

#define HIGH_TXMAX_FRAMES 0x00000052

Definition at line 896 of file tg3.h.

#define HOSTCC_RXCOAL_TICK_INT 0x00003c18

Definition at line 897 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_RXCOAL_TICK_INT 0x00000019

Definition at line 898 of file tg3.h.

#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c

Definition at line 899 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_TXCOAL_TICK_INT 0x00000019

Definition at line 900 of file tg3.h.

#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20

Definition at line 901 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_RXCOAL_MAXF_INT 0x00000005

Definition at line 902 of file tg3.h.

#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24

Definition at line 903 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_TXCOAL_MAXF_INT 0x00000005

Definition at line 904 of file tg3.h.

#define HOSTCC_STAT_COAL_TICKS 0x00003c28

Definition at line 905 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_STAT_COAL_TICKS 0x000f4240

Definition at line 906 of file tg3.h.

Referenced by tg3_setup_hw().

#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30

Definition at line 908 of file tg3.h.

Referenced by tg3_setup_hw().

#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38

Definition at line 909 of file tg3.h.

Referenced by tg3_setup_hw().

#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40

Definition at line 910 of file tg3.h.

Referenced by tg3_setup_hw().

#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44

Definition at line 911 of file tg3.h.

Referenced by tg3_setup_hw().

#define HOSTCC_FLOW_ATTN 0x00003c48

Definition at line 912 of file tg3.h.

#define HOSTCC_JUMBO_CON_IDX 0x00003c50

Definition at line 914 of file tg3.h.

#define HOSTCC_STD_CON_IDX 0x00003c54

Definition at line 915 of file tg3.h.

#define HOSTCC_MINI_CON_IDX 0x00003c58

Definition at line 916 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_0 0x00003c80

Definition at line 918 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_1 0x00003c84

Definition at line 919 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_2 0x00003c88

Definition at line 920 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_3 0x00003c8c

Definition at line 921 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_4 0x00003c90

Definition at line 922 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_5 0x00003c94

Definition at line 923 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_6 0x00003c98

Definition at line 924 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_7 0x00003c9c

Definition at line 925 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_8 0x00003ca0

Definition at line 926 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_9 0x00003ca4

Definition at line 927 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_10 0x00003ca8

Definition at line 928 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_11 0x00003cac

Definition at line 929 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_12 0x00003cb0

Definition at line 930 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_13 0x00003cb4

Definition at line 931 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_14 0x00003cb8

Definition at line 932 of file tg3.h.

#define HOSTCC_RET_PROD_IDX_15 0x00003cbc

Definition at line 933 of file tg3.h.

#define HOSTCC_SND_CON_IDX_0 0x00003cc0

Definition at line 934 of file tg3.h.

#define HOSTCC_SND_CON_IDX_1 0x00003cc4

Definition at line 935 of file tg3.h.

#define HOSTCC_SND_CON_IDX_2 0x00003cc8

Definition at line 936 of file tg3.h.

#define HOSTCC_SND_CON_IDX_3 0x00003ccc

Definition at line 937 of file tg3.h.

#define HOSTCC_SND_CON_IDX_4 0x00003cd0

Definition at line 938 of file tg3.h.

#define HOSTCC_SND_CON_IDX_5 0x00003cd4

Definition at line 939 of file tg3.h.

#define HOSTCC_SND_CON_IDX_6 0x00003cd8

Definition at line 940 of file tg3.h.

#define HOSTCC_SND_CON_IDX_7 0x00003cdc

Definition at line 941 of file tg3.h.

#define HOSTCC_SND_CON_IDX_8 0x00003ce0

Definition at line 942 of file tg3.h.

#define HOSTCC_SND_CON_IDX_9 0x00003ce4

Definition at line 943 of file tg3.h.

#define HOSTCC_SND_CON_IDX_10 0x00003ce8

Definition at line 944 of file tg3.h.

#define HOSTCC_SND_CON_IDX_11 0x00003cec

Definition at line 945 of file tg3.h.

#define HOSTCC_SND_CON_IDX_12 0x00003cf0

Definition at line 946 of file tg3.h.

#define HOSTCC_SND_CON_IDX_13 0x00003cf4

Definition at line 947 of file tg3.h.

#define HOSTCC_SND_CON_IDX_14 0x00003cf8

Definition at line 948 of file tg3.h.

#define HOSTCC_SND_CON_IDX_15 0x00003cfc

Definition at line 949 of file tg3.h.

#define MEMARB_MODE 0x00004000

Definition at line 953 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_chip_reset(), and tg3_stop_block().

#define MEMARB_MODE_RESET 0x00000001

Definition at line 954 of file tg3.h.

#define MEMARB_MODE_ENABLE 0x00000002

Definition at line 955 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_chip_reset().

#define MEMARB_STATUS 0x00004004

Definition at line 956 of file tg3.h.

#define MEMARB_TRAP_ADDR_LOW 0x00004008

Definition at line 957 of file tg3.h.

#define MEMARB_TRAP_ADDR_HIGH 0x0000400c

Definition at line 958 of file tg3.h.

#define BUFMGR_MODE 0x00004400

Definition at line 962 of file tg3.h.

Referenced by tg3_abort_hw(), tg3_setup_hw(), and tg3_stop_block().

#define BUFMGR_MODE_RESET 0x00000001

Definition at line 963 of file tg3.h.

#define BUFMGR_MODE_ENABLE 0x00000002

Definition at line 964 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define BUFMGR_MODE_ATTN_ENABLE 0x00000004

Definition at line 965 of file tg3.h.

Referenced by tg3_setup_hw().

#define BUFMGR_MODE_BM_TEST 0x00000008

Definition at line 966 of file tg3.h.

#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010

Definition at line 967 of file tg3.h.

#define BUFMGR_STATUS 0x00004404

Definition at line 968 of file tg3.h.

#define BUFMGR_STATUS_ERROR 0x00000004

Definition at line 969 of file tg3.h.

#define BUFMGR_STATUS_MBLOW 0x00000010

Definition at line 970 of file tg3.h.

#define BUFMGR_MB_POOL_ADDR 0x00004408

Definition at line 971 of file tg3.h.

Referenced by tg3_setup_hw().

#define BUFMGR_MB_POOL_SIZE 0x0000440c

Definition at line 972 of file tg3.h.

Referenced by tg3_setup_hw().

#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410

Definition at line 973 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050

Definition at line 974 of file tg3.h.

#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000

Definition at line 975 of file tg3.h.

#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130

Definition at line 976 of file tg3.h.

#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414

Definition at line 977 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020

Definition at line 978 of file tg3.h.

#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010

Definition at line 979 of file tg3.h.

#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098

Definition at line 980 of file tg3.h.

#define BUFMGR_MB_HIGH_WATER 0x00004418

Definition at line 981 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_MB_HIGH_WATER 0x00000060

Definition at line 982 of file tg3.h.

#define DEFAULT_MB_HIGH_WATER_5705 0x00000060

Definition at line 983 of file tg3.h.

#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c

Definition at line 984 of file tg3.h.

#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c

Definition at line 985 of file tg3.h.

#define BUFMGR_MB_ALLOC_BIT 0x10000000

Definition at line 986 of file tg3.h.

#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420

Definition at line 987 of file tg3.h.

#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424

Definition at line 988 of file tg3.h.

#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428

Definition at line 989 of file tg3.h.

#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c

Definition at line 990 of file tg3.h.

Referenced by tg3_setup_hw().

#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430

Definition at line 991 of file tg3.h.

Referenced by tg3_setup_hw().

#define BUFMGR_DMA_LOW_WATER 0x00004434

Definition at line 992 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_DMA_LOW_WATER 0x00000005

Definition at line 993 of file tg3.h.

#define BUFMGR_DMA_HIGH_WATER 0x00004438

Definition at line 994 of file tg3.h.

Referenced by tg3_setup_hw().

#define DEFAULT_DMA_HIGH_WATER 0x0000000a

Definition at line 995 of file tg3.h.

#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c

Definition at line 996 of file tg3.h.

#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440

Definition at line 997 of file tg3.h.

#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444

Definition at line 998 of file tg3.h.

#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448

Definition at line 999 of file tg3.h.

#define BUFMGR_HWDIAG_0 0x0000444c

Definition at line 1000 of file tg3.h.

#define BUFMGR_HWDIAG_1 0x00004450

Definition at line 1001 of file tg3.h.

#define BUFMGR_HWDIAG_2 0x00004454

Definition at line 1002 of file tg3.h.

#define RDMAC_MODE 0x00004800

Definition at line 1006 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RDMAC_MODE_RESET 0x00000001

Definition at line 1007 of file tg3.h.

#define RDMAC_MODE_ENABLE 0x00000002

Definition at line 1008 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define RDMAC_MODE_TGTABORT_ENAB 0x00000004

Definition at line 1009 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_MSTABORT_ENAB 0x00000008

Definition at line 1010 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_PARITYERR_ENAB 0x00000010

Definition at line 1011 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020

Definition at line 1012 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040

Definition at line 1013 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080

Definition at line 1014 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100

Definition at line 1015 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_LNGREAD_ENAB 0x00000200

Definition at line 1016 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_SPLIT_ENABLE 0x00000800

Definition at line 1017 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_MODE_SPLIT_RESET 0x00001000

Definition at line 1018 of file tg3.h.

#define RDMAC_MODE_FIFO_SIZE_128 0x00020000

Definition at line 1019 of file tg3.h.

#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000

Definition at line 1020 of file tg3.h.

Referenced by tg3_setup_hw().

#define RDMAC_STATUS 0x00004804

Definition at line 1021 of file tg3.h.

#define RDMAC_STATUS_TGTABORT 0x00000004

Definition at line 1022 of file tg3.h.

#define RDMAC_STATUS_MSTABORT 0x00000008

Definition at line 1023 of file tg3.h.

#define RDMAC_STATUS_PARITYERR 0x00000010

Definition at line 1024 of file tg3.h.

#define RDMAC_STATUS_ADDROFLOW 0x00000020

Definition at line 1025 of file tg3.h.

#define RDMAC_STATUS_FIFOOFLOW 0x00000040

Definition at line 1026 of file tg3.h.

#define RDMAC_STATUS_FIFOURUN 0x00000080

Definition at line 1027 of file tg3.h.

#define RDMAC_STATUS_FIFOOREAD 0x00000100

Definition at line 1028 of file tg3.h.

#define RDMAC_STATUS_LNGREAD 0x00000200

Definition at line 1029 of file tg3.h.

#define WDMAC_MODE 0x00004c00

Definition at line 1033 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define WDMAC_MODE_RESET 0x00000001

Definition at line 1034 of file tg3.h.

#define WDMAC_MODE_ENABLE 0x00000002

Definition at line 1035 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define WDMAC_MODE_TGTABORT_ENAB 0x00000004

Definition at line 1036 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_MODE_MSTABORT_ENAB 0x00000008

Definition at line 1037 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_MODE_PARITYERR_ENAB 0x00000010

Definition at line 1038 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020

Definition at line 1039 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040

Definition at line 1040 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080

Definition at line 1041 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100

Definition at line 1042 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_MODE_LNGREAD_ENAB 0x00000200

Definition at line 1043 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_MODE_RX_ACCEL 0x00000400

Definition at line 1044 of file tg3.h.

Referenced by tg3_setup_hw().

#define WDMAC_STATUS 0x00004c04

Definition at line 1045 of file tg3.h.

#define WDMAC_STATUS_TGTABORT 0x00000004

Definition at line 1046 of file tg3.h.

#define WDMAC_STATUS_MSTABORT 0x00000008

Definition at line 1047 of file tg3.h.

#define WDMAC_STATUS_PARITYERR 0x00000010

Definition at line 1048 of file tg3.h.

#define WDMAC_STATUS_ADDROFLOW 0x00000020

Definition at line 1049 of file tg3.h.

#define WDMAC_STATUS_FIFOOFLOW 0x00000040

Definition at line 1050 of file tg3.h.

#define WDMAC_STATUS_FIFOURUN 0x00000080

Definition at line 1051 of file tg3.h.

#define WDMAC_STATUS_FIFOOREAD 0x00000100

Definition at line 1052 of file tg3.h.

#define WDMAC_STATUS_LNGREAD 0x00000200

Definition at line 1053 of file tg3.h.

#define CPU_MODE 0x00000000

Definition at line 1057 of file tg3.h.

#define CPU_MODE_RESET 0x00000001

Definition at line 1058 of file tg3.h.

#define CPU_MODE_HALT 0x00000400

Definition at line 1059 of file tg3.h.

#define CPU_STATE 0x00000004

Definition at line 1060 of file tg3.h.

#define CPU_EVTMASK 0x00000008

Definition at line 1061 of file tg3.h.

#define CPU_PC 0x0000001c

Definition at line 1063 of file tg3.h.

#define CPU_INSN 0x00000020

Definition at line 1064 of file tg3.h.

#define CPU_SPAD_UFLOW 0x00000024

Definition at line 1065 of file tg3.h.

#define CPU_WDOG_CLEAR 0x00000028

Definition at line 1066 of file tg3.h.

#define CPU_WDOG_VECTOR 0x0000002c

Definition at line 1067 of file tg3.h.

#define CPU_WDOG_PC 0x00000030

Definition at line 1068 of file tg3.h.

#define CPU_HW_BP 0x00000034

Definition at line 1069 of file tg3.h.

#define CPU_WDOG_SAVED_STATE 0x00000044

Definition at line 1071 of file tg3.h.

#define CPU_LAST_BRANCH_ADDR 0x00000048

Definition at line 1072 of file tg3.h.

#define CPU_SPAD_UFLOW_SET 0x0000004c

Definition at line 1073 of file tg3.h.

#define CPU_R0 0x00000200

Definition at line 1075 of file tg3.h.

#define CPU_R1 0x00000204

Definition at line 1076 of file tg3.h.

#define CPU_R2 0x00000208

Definition at line 1077 of file tg3.h.

#define CPU_R3 0x0000020c

Definition at line 1078 of file tg3.h.

#define CPU_R4 0x00000210

Definition at line 1079 of file tg3.h.

#define CPU_R5 0x00000214

Definition at line 1080 of file tg3.h.

#define CPU_R6 0x00000218

Definition at line 1081 of file tg3.h.

#define CPU_R7 0x0000021c

Definition at line 1082 of file tg3.h.

#define CPU_R8 0x00000220

Definition at line 1083 of file tg3.h.

#define CPU_R9 0x00000224

Definition at line 1084 of file tg3.h.

#define CPU_R10 0x00000228

Definition at line 1085 of file tg3.h.

#define CPU_R11 0x0000022c

Definition at line 1086 of file tg3.h.

#define CPU_R12 0x00000230

Definition at line 1087 of file tg3.h.

#define CPU_R13 0x00000234

Definition at line 1088 of file tg3.h.

#define CPU_R14 0x00000238

Definition at line 1089 of file tg3.h.

#define CPU_R15 0x0000023c

Definition at line 1090 of file tg3.h.

#define CPU_R16 0x00000240

Definition at line 1091 of file tg3.h.

#define CPU_R17 0x00000244

Definition at line 1092 of file tg3.h.

#define CPU_R18 0x00000248

Definition at line 1093 of file tg3.h.

#define CPU_R19 0x0000024c

Definition at line 1094 of file tg3.h.

#define CPU_R20 0x00000250

Definition at line 1095 of file tg3.h.

#define CPU_R21 0x00000254

Definition at line 1096 of file tg3.h.

#define CPU_R22 0x00000258

Definition at line 1097 of file tg3.h.

#define CPU_R23 0x0000025c

Definition at line 1098 of file tg3.h.

#define CPU_R24 0x00000260

Definition at line 1099 of file tg3.h.

#define CPU_R25 0x00000264

Definition at line 1100 of file tg3.h.

#define CPU_R26 0x00000268

Definition at line 1101 of file tg3.h.

#define CPU_R27 0x0000026c

Definition at line 1102 of file tg3.h.

#define CPU_R28 0x00000270

Definition at line 1103 of file tg3.h.

#define CPU_R29 0x00000274

Definition at line 1104 of file tg3.h.

#define CPU_R30 0x00000278

Definition at line 1105 of file tg3.h.

#define CPU_R31 0x0000027c

Definition at line 1106 of file tg3.h.

#define RX_CPU_BASE 0x00005000

Definition at line 1109 of file tg3.h.

#define TX_CPU_BASE 0x00005400

Definition at line 1110 of file tg3.h.

#define GRCMBOX_INTERRUPT_0 0x00005800

Definition at line 1113 of file tg3.h.

#define GRCMBOX_INTERRUPT_1 0x00005808

Definition at line 1114 of file tg3.h.

#define GRCMBOX_INTERRUPT_2 0x00005810

Definition at line 1115 of file tg3.h.

#define GRCMBOX_INTERRUPT_3 0x00005818

Definition at line 1116 of file tg3.h.

#define GRCMBOX_GENERAL_0 0x00005820

Definition at line 1117 of file tg3.h.

#define GRCMBOX_GENERAL_1 0x00005828

Definition at line 1118 of file tg3.h.

#define GRCMBOX_GENERAL_2 0x00005830

Definition at line 1119 of file tg3.h.

#define GRCMBOX_GENERAL_3 0x00005838

Definition at line 1120 of file tg3.h.

#define GRCMBOX_GENERAL_4 0x00005840

Definition at line 1121 of file tg3.h.

#define GRCMBOX_GENERAL_5 0x00005848

Definition at line 1122 of file tg3.h.

#define GRCMBOX_GENERAL_6 0x00005850

Definition at line 1123 of file tg3.h.

#define GRCMBOX_GENERAL_7 0x00005858

Definition at line 1124 of file tg3.h.

#define GRCMBOX_RELOAD_STAT 0x00005860

Definition at line 1125 of file tg3.h.

#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868

Definition at line 1126 of file tg3.h.

#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870

Definition at line 1127 of file tg3.h.

#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878

Definition at line 1128 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880

Definition at line 1129 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888

Definition at line 1130 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890

Definition at line 1131 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898

Definition at line 1132 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0

Definition at line 1133 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8

Definition at line 1134 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0

Definition at line 1135 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8

Definition at line 1136 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0

Definition at line 1137 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8

Definition at line 1138 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0

Definition at line 1139 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8

Definition at line 1140 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0

Definition at line 1141 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8

Definition at line 1142 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0

Definition at line 1143 of file tg3.h.

#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8

Definition at line 1144 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900

Definition at line 1145 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908

Definition at line 1146 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910

Definition at line 1147 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918

Definition at line 1148 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920

Definition at line 1149 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928

Definition at line 1150 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930

Definition at line 1151 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938

Definition at line 1152 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940

Definition at line 1153 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948

Definition at line 1154 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950

Definition at line 1155 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958

Definition at line 1156 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960

Definition at line 1157 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968

Definition at line 1158 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970

Definition at line 1159 of file tg3.h.

#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978

Definition at line 1160 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980

Definition at line 1161 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988

Definition at line 1162 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990

Definition at line 1163 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998

Definition at line 1164 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0

Definition at line 1165 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8

Definition at line 1166 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0

Definition at line 1167 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8

Definition at line 1168 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0

Definition at line 1169 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8

Definition at line 1170 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0

Definition at line 1171 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8

Definition at line 1172 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0

Definition at line 1173 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8

Definition at line 1174 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0

Definition at line 1175 of file tg3.h.

#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8

Definition at line 1176 of file tg3.h.

#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00

Definition at line 1177 of file tg3.h.

#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04

Definition at line 1178 of file tg3.h.

#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08

Definition at line 1179 of file tg3.h.

#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c

Definition at line 1180 of file tg3.h.

#define FTQ_RESET 0x00005c00

Definition at line 1184 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define FTQ_RESET_DMA_READ_QUEUE (1 << 1)

Definition at line 1185 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_DMA_HIGH_PRI_READ (1 << 2)

Definition at line 1186 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_SEND_BD_COMPLETION (1 << 4)

Definition at line 1187 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_DMA_WRITE (1 << 6)

Definition at line 1188 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_DMA_HIGH_PRI_WRITE (1 << 7)

Definition at line 1189 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_SEND_DATA_COMPLETION (1 << 9)

Definition at line 1190 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_HOST_COALESCING (1 << 10)

Definition at line 1191 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_MAC_TX (1 << 11)

Definition at line 1192 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_RX_BD_COMPLETE (1 << 13)

Definition at line 1193 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_RX_LIST_PLCMT (1 << 14)

Definition at line 1194 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_RESET_RX_DATA_COMPLETION (1 << 16)

Definition at line 1195 of file tg3.h.

Referenced by tg3_abort_hw().

#define FTQ_DMA_NORM_READ_CTL 0x00005c10

Definition at line 1197 of file tg3.h.

#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14

Definition at line 1198 of file tg3.h.

#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18

Definition at line 1199 of file tg3.h.

#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c

Definition at line 1200 of file tg3.h.

#define FTQ_DMA_HIGH_READ_CTL 0x00005c20

Definition at line 1201 of file tg3.h.

#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24

Definition at line 1202 of file tg3.h.

#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28

Definition at line 1203 of file tg3.h.

#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c

Definition at line 1204 of file tg3.h.

#define FTQ_DMA_COMP_DISC_CTL 0x00005c30

Definition at line 1205 of file tg3.h.

#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34

Definition at line 1206 of file tg3.h.

#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38

Definition at line 1207 of file tg3.h.

#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c

Definition at line 1208 of file tg3.h.

#define FTQ_SEND_BD_COMP_CTL 0x00005c40

Definition at line 1209 of file tg3.h.

#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44

Definition at line 1210 of file tg3.h.

#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48

Definition at line 1211 of file tg3.h.

#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c

Definition at line 1212 of file tg3.h.

#define FTQ_SEND_DATA_INIT_CTL 0x00005c50

Definition at line 1213 of file tg3.h.

#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54

Definition at line 1214 of file tg3.h.

#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58

Definition at line 1215 of file tg3.h.

#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c

Definition at line 1216 of file tg3.h.

#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60

Definition at line 1217 of file tg3.h.

#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64

Definition at line 1218 of file tg3.h.

#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68

Definition at line 1219 of file tg3.h.

#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c

Definition at line 1220 of file tg3.h.

#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70

Definition at line 1221 of file tg3.h.

#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74

Definition at line 1222 of file tg3.h.

#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78

Definition at line 1223 of file tg3.h.

#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c

Definition at line 1224 of file tg3.h.

#define FTQ_SWTYPE1_CTL 0x00005c80

Definition at line 1225 of file tg3.h.

#define FTQ_SWTYPE1_FULL_CNT 0x00005c84

Definition at line 1226 of file tg3.h.

#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88

Definition at line 1227 of file tg3.h.

#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c

Definition at line 1228 of file tg3.h.

#define FTQ_SEND_DATA_COMP_CTL 0x00005c90

Definition at line 1229 of file tg3.h.

#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94

Definition at line 1230 of file tg3.h.

#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98

Definition at line 1231 of file tg3.h.

#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c

Definition at line 1232 of file tg3.h.

#define FTQ_HOST_COAL_CTL 0x00005ca0

Definition at line 1233 of file tg3.h.

#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4

Definition at line 1234 of file tg3.h.

#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8

Definition at line 1235 of file tg3.h.

#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac

Definition at line 1236 of file tg3.h.

#define FTQ_MAC_TX_CTL 0x00005cb0

Definition at line 1237 of file tg3.h.

#define FTQ_MAC_TX_FULL_CNT 0x00005cb4

Definition at line 1238 of file tg3.h.

#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8

Definition at line 1239 of file tg3.h.

#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc

Definition at line 1240 of file tg3.h.

#define FTQ_MB_FREE_CTL 0x00005cc0

Definition at line 1241 of file tg3.h.

#define FTQ_MB_FREE_FULL_CNT 0x00005cc4

Definition at line 1242 of file tg3.h.

#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8

Definition at line 1243 of file tg3.h.

#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc

Definition at line 1244 of file tg3.h.

#define FTQ_RCVBD_COMP_CTL 0x00005cd0

Definition at line 1245 of file tg3.h.

#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4

Definition at line 1246 of file tg3.h.

#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8

Definition at line 1247 of file tg3.h.

#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc

Definition at line 1248 of file tg3.h.

#define FTQ_RCVLST_PLMT_CTL 0x00005ce0

Definition at line 1249 of file tg3.h.

#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4

Definition at line 1250 of file tg3.h.

#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8

Definition at line 1251 of file tg3.h.

#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec

Definition at line 1252 of file tg3.h.

#define FTQ_RCVDATA_INI_CTL 0x00005cf0

Definition at line 1253 of file tg3.h.

#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4

Definition at line 1254 of file tg3.h.

#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8

Definition at line 1255 of file tg3.h.

#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc

Definition at line 1256 of file tg3.h.

#define FTQ_RCVDATA_COMP_CTL 0x00005d00

Definition at line 1257 of file tg3.h.

#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04

Definition at line 1258 of file tg3.h.

#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08

Definition at line 1259 of file tg3.h.

#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c

Definition at line 1260 of file tg3.h.

#define FTQ_SWTYPE2_CTL 0x00005d10

Definition at line 1261 of file tg3.h.

#define FTQ_SWTYPE2_FULL_CNT 0x00005d14

Definition at line 1262 of file tg3.h.

#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18

Definition at line 1263 of file tg3.h.

#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c

Definition at line 1264 of file tg3.h.

#define MSGINT_MODE 0x00006000

Definition at line 1268 of file tg3.h.

#define MSGINT_MODE_RESET 0x00000001

Definition at line 1269 of file tg3.h.

#define MSGINT_MODE_ENABLE 0x00000002

Definition at line 1270 of file tg3.h.

#define MSGINT_STATUS 0x00006004

Definition at line 1271 of file tg3.h.

#define MSGINT_FIFO 0x00006008

Definition at line 1272 of file tg3.h.

#define DMAC_MODE 0x00006400

Definition at line 1276 of file tg3.h.

Referenced by tg3_setup_hw(), and tg3_stop_block().

#define DMAC_MODE_RESET 0x00000001

Definition at line 1277 of file tg3.h.

#define DMAC_MODE_ENABLE 0x00000002

Definition at line 1278 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_MODE 0x00006800

Definition at line 1282 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_setup_hw().

#define GRC_MODE_UPD_ON_COAL 0x00000001

Definition at line 1283 of file tg3.h.

#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002

Definition at line 1284 of file tg3.h.

Referenced by tg3_probe().

#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004

Definition at line 1285 of file tg3.h.

Referenced by tg3_probe().

#define GRC_MODE_BSWAP_DATA 0x00000010

Definition at line 1286 of file tg3.h.

Referenced by tg3_probe().

#define GRC_MODE_WSWAP_DATA 0x00000020

Definition at line 1287 of file tg3.h.

Referenced by tg3_probe().

#define GRC_MODE_SPLITHDR 0x00000100

Definition at line 1288 of file tg3.h.

#define GRC_MODE_NOFRM_CRACKING 0x00000200

Definition at line 1289 of file tg3.h.

#define GRC_MODE_INCL_CRC 0x00000400

Definition at line 1290 of file tg3.h.

#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800

Definition at line 1291 of file tg3.h.

#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000

Definition at line 1292 of file tg3.h.

#define GRC_MODE_NOIRQ_ON_RCV 0x00004000

Definition at line 1293 of file tg3.h.

#define GRC_MODE_FORCE_PCI32BIT 0x00008000

Definition at line 1294 of file tg3.h.

#define GRC_MODE_HOST_STACKUP 0x00010000

Definition at line 1295 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_MODE_HOST_SENDBDS 0x00020000

Definition at line 1296 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000

Definition at line 1297 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000

Definition at line 1298 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000

Definition at line 1299 of file tg3.h.

#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000

Definition at line 1300 of file tg3.h.

#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000

Definition at line 1301 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000

Definition at line 1302 of file tg3.h.

#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000

Definition at line 1303 of file tg3.h.

#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000

Definition at line 1304 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000

Definition at line 1305 of file tg3.h.

#define GRC_MISC_CFG 0x00006804

Definition at line 1306 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), and tg3_setup_hw().

#define GRC_MISC_CFG_CORECLK_RESET 0x00000001

Definition at line 1307 of file tg3.h.

Referenced by tg3_chip_reset().

#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe

Definition at line 1308 of file tg3.h.

#define GRC_MISC_CFG_PRESCALAR_SHIFT 1

Definition at line 1309 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000

Definition at line 1310 of file tg3.h.

Referenced by tg3_get_invariants().

#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000

Definition at line 1311 of file tg3.h.

#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000

Definition at line 1312 of file tg3.h.

#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000

Definition at line 1313 of file tg3.h.

#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000

Definition at line 1314 of file tg3.h.

#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000

Definition at line 1315 of file tg3.h.

#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000

Definition at line 1316 of file tg3.h.

#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000

Definition at line 1317 of file tg3.h.

Referenced by tg3_get_invariants().

#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000

Definition at line 1318 of file tg3.h.

#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000

Definition at line 1319 of file tg3.h.

Referenced by tg3_get_invariants().

#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000

Definition at line 1320 of file tg3.h.

Referenced by tg3_get_invariants().

#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000

Definition at line 1321 of file tg3.h.

#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000

Definition at line 1322 of file tg3.h.

Referenced by tg3_chip_reset().

#define GRC_LOCAL_CTRL 0x00006808

Definition at line 1323 of file tg3.h.

Referenced by tg3_nvram_init(), tg3_set_power_state_0(), and tg3_setup_hw().

#define GRC_LCLCTRL_INT_ACTIVE 0x00000001

Definition at line 1324 of file tg3.h.

#define GRC_LCLCTRL_CLEARINT 0x00000002

Definition at line 1325 of file tg3.h.

#define GRC_LCLCTRL_SETINT 0x00000004

Definition at line 1326 of file tg3.h.

#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008

Definition at line 1327 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100

Definition at line 1328 of file tg3.h.

#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200

Definition at line 1329 of file tg3.h.

#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400

Definition at line 1330 of file tg3.h.

#define GRC_LCLCTRL_GPIO_OE0 0x00000800

Definition at line 1331 of file tg3.h.

#define GRC_LCLCTRL_GPIO_OE1 0x00001000

Definition at line 1332 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_LCLCTRL_GPIO_OE2 0x00002000

Definition at line 1333 of file tg3.h.

#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000

Definition at line 1334 of file tg3.h.

#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000

Definition at line 1335 of file tg3.h.

Referenced by tg3_setup_hw().

#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000

Definition at line 1336 of file tg3.h.

#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000

Definition at line 1337 of file tg3.h.

#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000

Definition at line 1338 of file tg3.h.

#define GRC_LCLCTRL_MEMSZ_256K 0x00000000

Definition at line 1339 of file tg3.h.

#define GRC_LCLCTRL_MEMSZ_512K 0x00040000

Definition at line 1340 of file tg3.h.

#define GRC_LCLCTRL_MEMSZ_1M 0x00080000

Definition at line 1341 of file tg3.h.

#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000

Definition at line 1342 of file tg3.h.

#define GRC_LCLCTRL_MEMSZ_4M 0x00100000

Definition at line 1343 of file tg3.h.

#define GRC_LCLCTRL_MEMSZ_8M 0x00140000

Definition at line 1344 of file tg3.h.

#define GRC_LCLCTRL_MEMSZ_16M 0x00180000

Definition at line 1345 of file tg3.h.

#define GRC_LCLCTRL_BANK_SELECT 0x00200000

Definition at line 1346 of file tg3.h.

#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000

Definition at line 1347 of file tg3.h.

#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000

Definition at line 1348 of file tg3.h.

Referenced by tg3_nvram_init(), and tg3_setup_hw().

#define GRC_TIMER 0x0000680c

Definition at line 1349 of file tg3.h.

#define GRC_RX_CPU_EVENT 0x00006810

Definition at line 1350 of file tg3.h.

Referenced by tg3_stop_fw().

#define GRC_RX_TIMER_REF 0x00006814

Definition at line 1351 of file tg3.h.

#define GRC_RX_CPU_SEM 0x00006818

Definition at line 1352 of file tg3.h.

#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c

Definition at line 1353 of file tg3.h.

#define GRC_TX_CPU_EVENT 0x00006820

Definition at line 1354 of file tg3.h.

#define GRC_TX_TIMER_REF 0x00006824

Definition at line 1355 of file tg3.h.

#define GRC_TX_CPU_SEM 0x00006828

Definition at line 1356 of file tg3.h.

#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c

Definition at line 1357 of file tg3.h.

#define GRC_MEM_POWER_UP 0x00006830

Definition at line 1358 of file tg3.h.

#define GRC_EEPROM_ADDR 0x00006838

Definition at line 1359 of file tg3.h.

Referenced by tg3_nvram_init(), and tg3_nvram_read_using_eeprom().

#define EEPROM_ADDR_WRITE 0x00000000

Definition at line 1360 of file tg3.h.

#define EEPROM_ADDR_READ 0x80000000

Definition at line 1361 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

#define EEPROM_ADDR_COMPLETE 0x40000000

Definition at line 1362 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

#define EEPROM_ADDR_FSM_RESET 0x20000000

Definition at line 1363 of file tg3.h.

Referenced by tg3_nvram_init().

#define EEPROM_ADDR_DEVID_MASK 0x1c000000

Definition at line 1364 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

#define EEPROM_ADDR_DEVID_SHIFT 26

Definition at line 1365 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

#define EEPROM_ADDR_START 0x02000000

Definition at line 1366 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

#define EEPROM_ADDR_CLKPERD_SHIFT 16

Definition at line 1367 of file tg3.h.

Referenced by tg3_nvram_init().

#define EEPROM_ADDR_ADDR_MASK 0x0000ffff

Definition at line 1368 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

#define EEPROM_ADDR_ADDR_SHIFT 0

Definition at line 1369 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60

Definition at line 1370 of file tg3.h.

Referenced by tg3_nvram_init().

#define EEPROM_CHIP_SIZE (64 * 1024)

Definition at line 1371 of file tg3.h.

#define GRC_EEPROM_DATA 0x0000683c

Definition at line 1372 of file tg3.h.

Referenced by tg3_nvram_read_using_eeprom().

#define GRC_EEPROM_CTRL 0x00006840

Definition at line 1373 of file tg3.h.

#define GRC_MDI_CTRL 0x00006844

Definition at line 1374 of file tg3.h.

#define GRC_SEEPROM_DELAY 0x00006848

Definition at line 1375 of file tg3.h.

#define NVRAM_CMD 0x00007000

Definition at line 1381 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_CMD_RESET 0x00000001

Definition at line 1382 of file tg3.h.

#define NVRAM_CMD_DONE 0x00000008

Definition at line 1383 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_CMD_GO 0x00000010

Definition at line 1384 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_CMD_WR 0x00000020

Definition at line 1385 of file tg3.h.

#define NVRAM_CMD_RD 0x00000000

Definition at line 1386 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_CMD_ERASE 0x00000040

Definition at line 1387 of file tg3.h.

#define NVRAM_CMD_FIRST 0x00000080

Definition at line 1388 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_CMD_LAST 0x00000100

Definition at line 1389 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_STAT 0x00007004

Definition at line 1390 of file tg3.h.

#define NVRAM_WRDATA 0x00007008

Definition at line 1391 of file tg3.h.

#define NVRAM_ADDR 0x0000700c

Definition at line 1392 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_ADDR_MSK 0x00ffffff

Definition at line 1393 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_RDDATA 0x00007010

Definition at line 1394 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_CFG1 0x00007014

Definition at line 1395 of file tg3.h.

Referenced by tg3_nvram_init().

#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001

Definition at line 1396 of file tg3.h.

Referenced by tg3_nvram_init().

#define NVRAM_CFG1_BUFFERED_MODE 0x00000002

Definition at line 1397 of file tg3.h.

Referenced by tg3_nvram_init().

#define NVRAM_CFG1_PASS_THRU 0x00000004

Definition at line 1398 of file tg3.h.

#define NVRAM_CFG1_BIT_BANG 0x00000008

Definition at line 1399 of file tg3.h.

#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000

Definition at line 1400 of file tg3.h.

Referenced by tg3_nvram_init().

#define NVRAM_CFG2 0x00007018

Definition at line 1401 of file tg3.h.

#define NVRAM_CFG3 0x0000701c

Definition at line 1402 of file tg3.h.

#define NVRAM_SWARB 0x00007020

Definition at line 1403 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_nvram_read().

#define SWARB_REQ_SET0 0x00000001

Definition at line 1404 of file tg3.h.

#define SWARB_REQ_SET1 0x00000002

Definition at line 1405 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_nvram_read().

#define SWARB_REQ_SET2 0x00000004

Definition at line 1406 of file tg3.h.

#define SWARB_REQ_SET3 0x00000008

Definition at line 1407 of file tg3.h.

#define SWARB_REQ_CLR0 0x00000010

Definition at line 1408 of file tg3.h.

#define SWARB_REQ_CLR1 0x00000020

Definition at line 1409 of file tg3.h.

Referenced by tg3_nvram_read().

#define SWARB_REQ_CLR2 0x00000040

Definition at line 1410 of file tg3.h.

#define SWARB_REQ_CLR3 0x00000080

Definition at line 1411 of file tg3.h.

#define SWARB_GNT0 0x00000100

Definition at line 1412 of file tg3.h.

#define SWARB_GNT1 0x00000200

Definition at line 1413 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_nvram_read().

#define SWARB_GNT2 0x00000400

Definition at line 1414 of file tg3.h.

#define SWARB_GNT3 0x00000800

Definition at line 1415 of file tg3.h.

#define SWARB_REQ0 0x00001000

Definition at line 1416 of file tg3.h.

#define SWARB_REQ1 0x00002000

Definition at line 1417 of file tg3.h.

#define SWARB_REQ2 0x00004000

Definition at line 1418 of file tg3.h.

#define SWARB_REQ3 0x00008000

Definition at line 1419 of file tg3.h.

#define NVRAM_BUFFERED_PAGE_SIZE 264

Definition at line 1420 of file tg3.h.

Referenced by tg3_nvram_read().

#define NVRAM_BUFFERED_PAGE_POS 9

Definition at line 1421 of file tg3.h.

Referenced by tg3_nvram_read().

#define NIC_SRAM_WIN_BASE 0x00008000

Definition at line 1427 of file tg3.h.

#define NIC_SRAM_PAGE_ZERO 0x00000000

Definition at line 1430 of file tg3.h.

#define NIC_SRAM_SEND_RCB 0x00000100

Definition at line 1431 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_RCV_RET_RCB 0x00000200

Definition at line 1432 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_STATS_BLK 0x00000300

Definition at line 1433 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_STATUS_BLK 0x00000b00

Definition at line 1434 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50

Definition at line 1436 of file tg3.h.

Referenced by tg3_restart_fw(), and tg3_setup_copper_phy().

#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654

Definition at line 1437 of file tg3.h.

Referenced by tg3_restart_fw().

#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b

Definition at line 1438 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define NIC_SRAM_DATA_SIG 0x00000b54

Definition at line 1440 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654

Definition at line 1441 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG 0x00000b58

Definition at line 1443 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c

Definition at line 1444 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN 0x00000000

Definition at line 1445 of file tg3.h.

#define NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD 0x00000004

Definition at line 1446 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN 0x00000004

Definition at line 1447 of file tg3.h.

#define NIC_SRAM_DATA_CFG_LED_LINK_SPD 0x00000008

Definition at line 1448 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG_LED_OUTPUT 0x00000008

Definition at line 1449 of file tg3.h.

#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030

Definition at line 1450 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000

Definition at line 1451 of file tg3.h.

#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010

Definition at line 1452 of file tg3.h.

#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020

Definition at line 1453 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040

Definition at line 1454 of file tg3.h.

#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080

Definition at line 1455 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100

Definition at line 1456 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000

Definition at line 1457 of file tg3.h.

Referenced by tg3_chip_reset().

#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000

Definition at line 1458 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_PHY_ID 0x00000b74

Definition at line 1460 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000

Definition at line 1461 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff

Definition at line 1462 of file tg3.h.

Referenced by tg3_phy_probe().

#define NIC_SRAM_FW_CMD_MBOX 0x00000b78

Definition at line 1464 of file tg3.h.

Referenced by tg3_stop_fw().

#define FWCMD_NICDRV_ALIVE 0x00000001

Definition at line 1465 of file tg3.h.

#define FWCMD_NICDRV_PAUSE_FW 0x00000002

Definition at line 1466 of file tg3.h.

Referenced by tg3_stop_fw().

#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003

Definition at line 1467 of file tg3.h.

#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004

Definition at line 1468 of file tg3.h.

#define FWCMD_NICDRV_FIX_DMAR 0x00000005

Definition at line 1469 of file tg3.h.

#define FWCMD_NICDRV_FIX_DMAW 0x00000006

Definition at line 1470 of file tg3.h.

#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c

Definition at line 1471 of file tg3.h.

#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80

Definition at line 1472 of file tg3.h.

#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00

Definition at line 1473 of file tg3.h.

#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04

Definition at line 1474 of file tg3.h.

Referenced by tg3_restart_fw().

#define DRV_STATE_START 0x00000001

Definition at line 1475 of file tg3.h.

Referenced by tg3_setup_hw().

#define DRV_STATE_UNLOAD 0x00000002

Definition at line 1476 of file tg3.h.

Referenced by tg3_halt().

#define DRV_STATE_WOL 0x00000003

Definition at line 1477 of file tg3.h.

#define DRV_STATE_SUSPEND 0x00000004

Definition at line 1478 of file tg3.h.

Referenced by tg3_restart_fw().

#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08

Definition at line 1480 of file tg3.h.

#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14

Definition at line 1482 of file tg3.h.

Referenced by tg3_get_device_address().

#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18

Definition at line 1483 of file tg3.h.

Referenced by tg3_get_device_address().

#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000

Definition at line 1485 of file tg3.h.

#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000

Definition at line 1487 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000

Definition at line 1488 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_TX_BUFFER_DESC 0x00004000

Definition at line 1489 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_RX_BUFFER_DESC 0x00006000

Definition at line 1490 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000

Definition at line 1491 of file tg3.h.

#define NIC_SRAM_MBUF_POOL_BASE 0x00008000

Definition at line 1492 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000

Definition at line 1493 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000

Definition at line 1494 of file tg3.h.

Referenced by tg3_setup_hw().

#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000

Definition at line 1495 of file tg3.h.

#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000

Definition at line 1496 of file tg3.h.

#define PHY_ADDR 0x01

Definition at line 1499 of file tg3.h.

Referenced by tg3_readphy(), and tg3_writephy().

#define TG3_BMCR_SPEED1000 0x0040

Definition at line 1502 of file tg3.h.

Referenced by tg3_phy_reset_5703_4_5().

#define MII_TG3_CTRL 0x09

Definition at line 1504 of file tg3.h.

Referenced by tg3_phy_copper_begin(), tg3_phy_probe(), tg3_phy_reset_5703_4_5(), and tg3_setup_copper_phy().

#define MII_TG3_CTRL_ADV_1000_HALF 0x0100

Definition at line 1505 of file tg3.h.

Referenced by tg3_phy_copper_begin(), tg3_phy_probe(), and tg3_setup_copper_phy().

#define MII_TG3_CTRL_ADV_1000_FULL 0x0200

Definition at line 1506 of file tg3.h.

Referenced by tg3_phy_copper_begin(), tg3_phy_probe(), and tg3_setup_copper_phy().

#define MII_TG3_CTRL_AS_MASTER 0x0800

Definition at line 1507 of file tg3.h.

Referenced by tg3_phy_copper_begin(), tg3_phy_probe(), and tg3_phy_reset_5703_4_5().

#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000

Definition at line 1508 of file tg3.h.

Referenced by tg3_phy_copper_begin(), tg3_phy_probe(), and tg3_phy_reset_5703_4_5().

#define MII_TG3_EXT_CTRL 0x10

Definition at line 1510 of file tg3.h.

Referenced by tg3_phy_reset_5703_4_5(), and tg3_setup_copper_phy().

#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002

Definition at line 1511 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define MII_TG3_EXT_CTRL_TBI 0x8000

Definition at line 1512 of file tg3.h.

#define MII_TG3_EXT_STAT 0x11

Definition at line 1514 of file tg3.h.

#define MII_TG3_EXT_STAT_LPASS 0x0100

Definition at line 1515 of file tg3.h.

#define MII_TG3_DSP_RW_PORT 0x15

Definition at line 1517 of file tg3.h.

Referenced by tg3_phy_probe(), tg3_phy_reset_5703_4_5(), tg3_phy_reset_chanpat(), tg3_phy_write_and_check_testpat(), and tg3_writedsp().

#define MII_TG3_DSP_ADDRESS 0x17

Definition at line 1519 of file tg3.h.

Referenced by tg3_phy_probe(), tg3_phy_reset_5703_4_5(), tg3_phy_reset_chanpat(), tg3_phy_write_and_check_testpat(), and tg3_writedsp().

#define MII_TG3_AUX_CTRL 0x18

Definition at line 1521 of file tg3.h.

Referenced by tg3_init_5401phy_dsp(), tg3_phy_probe(), tg3_phy_reset_5703_4_5(), tg3_phy_set_wirespeed(), and tg3_setup_copper_phy().

#define MII_TG3_AUX_STAT 0x19

Definition at line 1523 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define MII_TG3_AUX_STAT_LPASS 0x0004

Definition at line 1524 of file tg3.h.

#define MII_TG3_AUX_STAT_SPDMASK 0x0700

Definition at line 1525 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

#define MII_TG3_AUX_STAT_10HALF 0x0100

Definition at line 1526 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

#define MII_TG3_AUX_STAT_10FULL 0x0200

Definition at line 1527 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

#define MII_TG3_AUX_STAT_100HALF 0x0300

Definition at line 1528 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

#define MII_TG3_AUX_STAT_100_4 0x0400

Definition at line 1529 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

#define MII_TG3_AUX_STAT_100FULL 0x0500

Definition at line 1530 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

#define MII_TG3_AUX_STAT_1000HALF 0x0600

Definition at line 1531 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

#define MII_TG3_AUX_STAT_1000FULL 0x0700

Definition at line 1532 of file tg3.h.

Referenced by tg3_aux_stat_to_speed_duplex().

#define MII_TG3_ISTAT 0x1a

Definition at line 1534 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define MII_TG3_IMASK 0x1b

Definition at line 1535 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define MII_TG3_INT_LINKCHG 0x0002

Definition at line 1538 of file tg3.h.

#define MII_TG3_INT_SPEEDCHG 0x0004

Definition at line 1539 of file tg3.h.

#define MII_TG3_INT_DUPLEXCHG 0x0008

Definition at line 1540 of file tg3.h.

#define MII_TG3_INT_ANEG_PAGE_RX 0x0400

Definition at line 1541 of file tg3.h.

#define TXD_FLAG_TCPUDP_CSUM 0x0001

Definition at line 1585 of file tg3.h.

#define TXD_FLAG_IP_CSUM 0x0002

Definition at line 1586 of file tg3.h.

#define TXD_FLAG_END 0x0004

Definition at line 1587 of file tg3.h.

Referenced by tg3_transmit().

#define TXD_FLAG_IP_FRAG 0x0008

Definition at line 1588 of file tg3.h.

#define TXD_FLAG_IP_FRAG_END 0x0010

Definition at line 1589 of file tg3.h.

#define TXD_FLAG_VLAN 0x0040

Definition at line 1590 of file tg3.h.

#define TXD_FLAG_COAL_NOW 0x0080

Definition at line 1591 of file tg3.h.

#define TXD_FLAG_CPU_PRE_DMA 0x0100

Definition at line 1592 of file tg3.h.

#define TXD_FLAG_CPU_POST_DMA 0x0200

Definition at line 1593 of file tg3.h.

#define TXD_FLAG_ADD_SRC_ADDR 0x1000

Definition at line 1594 of file tg3.h.

#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000

Definition at line 1595 of file tg3.h.

#define TXD_FLAG_NO_CRC 0x8000

Definition at line 1596 of file tg3.h.

#define TXD_LEN_SHIFT 16

Definition at line 1597 of file tg3.h.

Referenced by tg3_transmit().

#define TXD_VLAN_TAG_SHIFT 0

Definition at line 1600 of file tg3.h.

Referenced by tg3_transmit().

#define TXD_MSS_SHIFT 16

Definition at line 1601 of file tg3.h.

#define TXD_ADDR 0x00UL

Definition at line 1604 of file tg3.h.

#define TXD_LEN_FLAGS 0x08UL

Definition at line 1605 of file tg3.h.

#define TXD_VLAN_TAG 0x0cUL

Definition at line 1606 of file tg3.h.

#define TXD_SIZE 0x10UL

Definition at line 1607 of file tg3.h.

#define RXD_IDX_MASK 0xffff0000

Definition at line 1614 of file tg3.h.

#define RXD_IDX_SHIFT 16

Definition at line 1615 of file tg3.h.

#define RXD_LEN_MASK 0x0000ffff

Definition at line 1616 of file tg3.h.

Referenced by tg3_poll().

#define RXD_LEN_SHIFT 0

Definition at line 1617 of file tg3.h.

Referenced by tg3_init_rings(), and tg3_poll().

#define RXD_TYPE_SHIFT 16

Definition at line 1620 of file tg3.h.

#define RXD_FLAGS_SHIFT 0

Definition at line 1621 of file tg3.h.

Referenced by tg3_init_rings().

#define RXD_FLAG_END 0x0004

Definition at line 1623 of file tg3.h.

Referenced by tg3_init_rings().

#define RXD_FLAG_MINI 0x0800

Definition at line 1624 of file tg3.h.

#define RXD_FLAG_JUMBO 0x0020

Definition at line 1625 of file tg3.h.

#define RXD_FLAG_VLAN 0x0040

Definition at line 1626 of file tg3.h.

#define RXD_FLAG_ERROR 0x0400

Definition at line 1627 of file tg3.h.

#define RXD_FLAG_IP_CSUM 0x1000

Definition at line 1628 of file tg3.h.

#define RXD_FLAG_TCPUDP_CSUM 0x2000

Definition at line 1629 of file tg3.h.

#define RXD_FLAG_IS_TCP 0x4000

Definition at line 1630 of file tg3.h.

#define RXD_IPCSUM_MASK 0xffff0000

Definition at line 1633 of file tg3.h.

#define RXD_IPCSUM_SHIFT 16

Definition at line 1634 of file tg3.h.

#define RXD_TCPCSUM_MASK 0x0000ffff

Definition at line 1635 of file tg3.h.

#define RXD_TCPCSUM_SHIFT 0

Definition at line 1636 of file tg3.h.

#define RXD_VLAN_MASK 0x0000ffff

Definition at line 1640 of file tg3.h.

#define RXD_ERR_BAD_CRC 0x00010000

Definition at line 1642 of file tg3.h.

#define RXD_ERR_COLLISION 0x00020000

Definition at line 1643 of file tg3.h.

#define RXD_ERR_LINK_LOST 0x00040000

Definition at line 1644 of file tg3.h.

#define RXD_ERR_PHY_DECODE 0x00080000

Definition at line 1645 of file tg3.h.

#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000

Definition at line 1646 of file tg3.h.

#define RXD_ERR_MAC_ABRT 0x00200000

Definition at line 1647 of file tg3.h.

#define RXD_ERR_TOO_SMALL 0x00400000

Definition at line 1648 of file tg3.h.

#define RXD_ERR_NO_RESOURCES 0x00800000

Definition at line 1649 of file tg3.h.

#define RXD_ERR_HUGE_FRAME 0x01000000

Definition at line 1650 of file tg3.h.

#define RXD_ERR_MASK 0xffff0000

Definition at line 1651 of file tg3.h.

#define RXD_OPAQUE_INDEX_MASK 0x0000ffff

Definition at line 1655 of file tg3.h.

#define RXD_OPAQUE_INDEX_SHIFT 0

Definition at line 1656 of file tg3.h.

Referenced by tg3_init_rings().

#define RXD_OPAQUE_RING_STD 0x00010000

Definition at line 1657 of file tg3.h.

Referenced by tg3_init_rings(), and tg3_poll().

#define RXD_OPAQUE_RING_JUMBO 0x00020000

Definition at line 1658 of file tg3.h.

#define RXD_OPAQUE_RING_MINI 0x00040000

Definition at line 1659 of file tg3.h.

#define RXD_OPAQUE_RING_MASK 0x00070000

Definition at line 1660 of file tg3.h.

Referenced by tg3_poll().

#define TG3_HW_STATUS_SIZE 0x50

Definition at line 1695 of file tg3.h.

Referenced by tg3_abort_hw(), and tg3_setup_hw().

#define SD_STATUS_UPDATED 0x00000001

Definition at line 1698 of file tg3.h.

Referenced by tg3_ack_irqs(), and tg3_setup_fiber_phy().

#define SD_STATUS_LINK_CHG 0x00000002

Definition at line 1699 of file tg3.h.

Referenced by tg3_setup_fiber_phy().

#define SD_STATUS_ERROR 0x00000004

Definition at line 1700 of file tg3.h.

#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002

Definition at line 1940 of file tg3.h.

#define TG3_FLAG_RX_CHECKSUMS 0x00000004

Definition at line 1941 of file tg3.h.

#define TG3_FLAG_USE_LINKCHG_REG 0x00000008

Definition at line 1942 of file tg3.h.

#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010

Definition at line 1943 of file tg3.h.

#define TG3_FLAG_ENABLE_ASF 0x00000020

Definition at line 1944 of file tg3.h.

Referenced by tg3_phy_probe(), tg3_restart_fw(), tg3_setup_hw(), tg3_stop_fw(), and tg3_switch_clocks().

#define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040

Definition at line 1945 of file tg3.h.

#define TG3_FLAG_POLL_SERDES 0x00000080

Definition at line 1946 of file tg3.h.

#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100

Definition at line 1947 of file tg3.h.

#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200

Definition at line 1948 of file tg3.h.

#define TG3_FLAG_WOL_SPEED_100MB 0x00000400

Definition at line 1949 of file tg3.h.

#define TG3_FLAG_WOL_ENABLE 0x00000800

Definition at line 1950 of file tg3.h.

#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000

Definition at line 1951 of file tg3.h.

Referenced by tg3_phy_probe().

#define TG3_FLAG_NVRAM 0x00002000

Definition at line 1952 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_nvram_init(), and tg3_nvram_read().

#define TG3_FLAG_NVRAM_BUFFERED 0x00004000

Definition at line 1953 of file tg3.h.

Referenced by tg3_nvram_init(), and tg3_nvram_read().

#define TG3_FLAG_RX_PAUSE 0x00008000

Definition at line 1954 of file tg3.h.

Referenced by tg3_link_report(), tg3_setup_fiber_phy(), and tg3_setup_flow_control().

#define TG3_FLAG_TX_PAUSE 0x00010000

Definition at line 1955 of file tg3.h.

Referenced by tg3_link_report(), tg3_setup_fiber_phy(), and tg3_setup_flow_control().

#define TG3_FLAG_PCIX_MODE 0x00020000

Definition at line 1956 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), tg3_probe(), tg3_setup_copper_phy(), tg3_setup_dma(), and tg3_setup_hw().

#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000

Definition at line 1957 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_probe(), and tg3_setup_copper_phy().

#define TG3_FLAG_PCI_32BIT 0x00080000

Definition at line 1958 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_probe().

#define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000

Definition at line 1959 of file tg3.h.

#define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000

Definition at line 1960 of file tg3.h.

#define TG3_FLAG_SERDES_WOL_CAP 0x00400000

Definition at line 1961 of file tg3.h.

Referenced by tg3_phy_probe().

#define TG3_FLAG_JUMBO_ENABLE 0x00800000

Definition at line 1962 of file tg3.h.

Referenced by tg3_setup_hw().

#define TG3_FLAG_10_100_ONLY 0x01000000

Definition at line 1963 of file tg3.h.

Referenced by tg3_get_invariants(), tg3_phy_copper_begin(), and tg3_phy_probe().

#define TG3_FLAG_PAUSE_AUTONEG 0x02000000

Definition at line 1964 of file tg3.h.

#define TG3_FLAG_PAUSE_RX 0x04000000

Definition at line 1965 of file tg3.h.

#define TG3_FLAG_PAUSE_TX 0x08000000

Definition at line 1966 of file tg3.h.

#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000

Definition at line 1967 of file tg3.h.

#define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000

Definition at line 1968 of file tg3.h.

Referenced by tg3_disable(), and tg3_setup_fiber_phy().

#define TG3_FLAG_SPLIT_MODE 0x40000000

Definition at line 1969 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_setup_hw().

#define TG3_FLAG_INIT_COMPLETE 0x80000000

Definition at line 1970 of file tg3.h.

Referenced by tg3_disable(), tg3_probe(), tg3_setup_copper_phy(), and tg3_setup_fiber_phy().

#define TG3_FLG2_RESTART_TIMER 0x00000001

Definition at line 1973 of file tg3.h.

#define TG3_FLG2_SUN_5704 0x00000002

Definition at line 1974 of file tg3.h.

Referenced by tg3_chip_reset(), and tg3_restart_fw().

#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004

Definition at line 1975 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_phy_set_wirespeed().

#define TG3_FLG2_IS_5788 0x00000008

Definition at line 1976 of file tg3.h.

Referenced by tg3_get_invariants(), and tg3_setup_hw().

#define TG3_FLG2_MAX_RXPEND_64 0x00000010

Definition at line 1977 of file tg3.h.

#define TG3_FLG2_TSO_CAPABLE 0x00000020

Definition at line 1978 of file tg3.h.

#define TG3_FLG2_PCI_EXPRESS 0x00000040

Definition at line 1980 of file tg3.h.

Referenced by tg3_chip_reset(), tg3_get_invariants(), tg3_restart_fw(), and tg3_setup_hw().

#define SPLIT_MODE_5704_MAX_REQ 3

Definition at line 1985 of file tg3.h.

Referenced by tg3_get_invariants().

#define PHY_ID_MASK 0xfffffff0

Definition at line 2032 of file tg3.h.

Referenced by tg3_phy_probe(), tg3_phy_string(), and tg3_setup_copper_phy().

#define PHY_ID_BCM5400 0x60008040

Definition at line 2033 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_BCM5401 0x60008050

Definition at line 2034 of file tg3.h.

Referenced by tg3_phy_probe(), tg3_phy_string(), and tg3_setup_copper_phy().

#define PHY_ID_BCM5411 0x60008070

Definition at line 2035 of file tg3.h.

Referenced by tg3_phy_string(), and tg3_setup_copper_phy().

#define PHY_ID_BCM5701 0x60008110

Definition at line 2036 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_BCM5703 0x60008160

Definition at line 2037 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_BCM5704 0x60008190

Definition at line 2038 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_BCM5705 0x600081a0

Definition at line 2039 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_BCM5750 0x60008180

Definition at line 2040 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_BCM5787 0xbc050ce0

Definition at line 2041 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_BCM8002 0x60010140

Definition at line 2042 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_BCM5751 0x00206180

Definition at line 2043 of file tg3.h.

Referenced by tg3_phy_string().

#define PHY_ID_SERDES 0xfeedbee0

Definition at line 2044 of file tg3.h.

Referenced by tg3_phy_probe(), tg3_phy_string(), tg3_poll_link(), tg3_setup_hw(), and tg3_setup_phy().

#define PHY_ID_INVALID 0xffffffff

Definition at line 2045 of file tg3.h.

Referenced by tg3_phy_probe().

#define PHY_ID_REV_MASK 0x0000000f

Definition at line 2046 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define PHY_REV_BCM5401_B0 0x1

Definition at line 2047 of file tg3.h.

Referenced by tg3_setup_copper_phy().

#define PHY_REV_BCM5401_B2 0x3

Definition at line 2048 of file tg3.h.

#define PHY_REV_BCM5401_C0 0x6

Definition at line 2049 of file tg3.h.

#define PHY_REV_BCM5411_X0 0x1

Definition at line 2050 of file tg3.h.

#define KNOWN_PHY_ID ( X )

Value:

((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
         (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
         (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
         (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
         (X) == PHY_ID_BCM5751 || (X) == PHY_ID_BCM5787 || \
         (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)

Definition at line 2064 of file tg3.h.

Referenced by tg3_phy_probe().

Typedef Documentation

typedef unsigned long dma_addr_t

Definition at line 15 of file tg3.h.

Enumeration Type Documentation

enum phy_led_mode

Enumerator:

led_mode_auto
led_mode_three_link
led_mode_link10

Definition at line 1833 of file tg3.h.

01833                   {
01834         led_mode_auto,
01835         led_mode_three_link,
01836         led_mode_link10
01837 };

Function Documentation

FILE_LICENCE ( GPL2_ONLY )