#include "etherboot.h"#include "nic.h"#include <errno.h>#include <gpxe/pci.h>#include <gpxe/ethernet.h>#include "string.h"#include <mii.h>#include "tg3.h"Go to the source code of this file.
Data Structures | |
| struct | eth_frame |
| struct | bss |
| struct | tg3_fiber_aneginfo |
| struct | subsys_tbl_ent |
Defines | |
| #define | SUPPORT_COPPER_PHY 1 |
| #define | SUPPORT_FIBER_PHY 1 |
| #define | SUPPORT_LINK_REPORT 1 |
| #define | SUPPORT_PARTNO_STR 1 |
| #define | SUPPORT_PHY_STR 1 |
| #define | TG3_RX_RING_SIZE 512 |
| #define | TG3_DEF_RX_RING_PENDING 20 |
| #define | TG3_RX_RCB_RING_SIZE 1024 |
| #define | TG3_TX_RING_SIZE 512 |
| #define | TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) |
| #define | TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE) |
| #define | TG3_RX_RCB_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE) |
| #define | TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE) |
| #define | NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
| #define | PREV_TX(N) (((N) - 1) & (TG3_TX_RING_SIZE - 1)) |
| #define | RX_PKT_BUF_SZ (1536 + 2 + 64) |
| #define | tw32(reg, val) tg3_write_indirect_reg32((reg),(val)) |
| #define | tw32_mailbox(reg, val) writel(((val) & 0xffffffff), tg3.regs + (reg)) |
| #define | tw16(reg, val) writew(((val) & 0xffff), tg3.regs + (reg)) |
| #define | tw8(reg, val) writeb(((val) & 0xff), tg3.regs + (reg)) |
| #define | tr32(reg) readl(tg3.regs + (reg)) |
| #define | tr16(reg) readw(tg3.regs + (reg)) |
| #define | tr8(reg) readb(tg3.regs + (reg)) |
| #define | PHY_BUSY_LOOPS 5000 |
| #define | ANEG_STATE_UNKNOWN 0 |
| #define | ANEG_STATE_AN_ENABLE 1 |
| #define | ANEG_STATE_RESTART_INIT 2 |
| #define | ANEG_STATE_RESTART 3 |
| #define | ANEG_STATE_DISABLE_LINK_OK 4 |
| #define | ANEG_STATE_ABILITY_DETECT_INIT 5 |
| #define | ANEG_STATE_ABILITY_DETECT 6 |
| #define | ANEG_STATE_ACK_DETECT_INIT 7 |
| #define | ANEG_STATE_ACK_DETECT 8 |
| #define | ANEG_STATE_COMPLETE_ACK_INIT 9 |
| #define | ANEG_STATE_COMPLETE_ACK 10 |
| #define | ANEG_STATE_IDLE_DETECT_INIT 11 |
| #define | ANEG_STATE_IDLE_DETECT 12 |
| #define | ANEG_STATE_LINK_OK 13 |
| #define | ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 |
| #define | ANEG_STATE_NEXT_PAGE_WAIT 15 |
| #define | MR_AN_ENABLE 0x00000001 |
| #define | MR_RESTART_AN 0x00000002 |
| #define | MR_AN_COMPLETE 0x00000004 |
| #define | MR_PAGE_RX 0x00000008 |
| #define | MR_NP_LOADED 0x00000010 |
| #define | MR_TOGGLE_TX 0x00000020 |
| #define | MR_LP_ADV_FULL_DUPLEX 0x00000040 |
| #define | MR_LP_ADV_HALF_DUPLEX 0x00000080 |
| #define | MR_LP_ADV_SYM_PAUSE 0x00000100 |
| #define | MR_LP_ADV_ASYM_PAUSE 0x00000200 |
| #define | MR_LP_ADV_REMOTE_FAULT1 0x00000400 |
| #define | MR_LP_ADV_REMOTE_FAULT2 0x00000800 |
| #define | MR_LP_ADV_NEXT_PAGE 0x00001000 |
| #define | MR_TOGGLE_RX 0x00002000 |
| #define | MR_NP_RX 0x00004000 |
| #define | MR_LINK_OK 0x80000000 |
| #define | ANEG_CFG_NP 0x00000080 |
| #define | ANEG_CFG_ACK 0x00000040 |
| #define | ANEG_CFG_RF2 0x00000020 |
| #define | ANEG_CFG_RF1 0x00000010 |
| #define | ANEG_CFG_PS2 0x00000001 |
| #define | ANEG_CFG_PS1 0x00008000 |
| #define | ANEG_CFG_HD 0x00004000 |
| #define | ANEG_CFG_FD 0x00002000 |
| #define | ANEG_CFG_INVAL 0x00001f06 |
| #define | ANEG_OK 0 |
| #define | ANEG_DONE 1 |
| #define | ANEG_TIMER_ENAB 2 |
| #define | ANEG_FAILED -1 |
| #define | ANEG_STATE_SETTLE_TIME 10000 |
| #define | MAX_WAIT_CNT 1000 |
| #define | TG3_WRITE_SETTINGS(TABLE) |
| #define | T3_PCIE_CAPABILITY_ID_REG 0xD0 |
| #define | T3_PCIE_CAPABILITY_ID 0x10 |
| #define | T3_PCIE_CAPABILITY_REG 0xD2 |
| #define | PCI_DEVICE_ID_TIGON3_5901 0x170d |
| #define | PCI_DEVICE_ID_TIGON3_5901_2 0x170e |
Functions | |
| FILE_LICENCE (GPL2_ONLY) | |
| static int | pci_save_state (struct pci_device *dev, uint32_t *buffer) |
| pci_save_state - save the PCI configuration space of a device before suspending : - PCI device that we're dealing with : - buffer to hold config space context | |
| static int | pci_restore_state (struct pci_device *dev, uint32_t *buffer) |
| pci_restore_state - Restore the saved state of a PCI device : - PCI device that we're dealing with : - saved PCI config space | |
| static void | tg3_write_indirect_reg32 (uint32_t off, uint32_t val) |
| static void | tw32_carefully (uint32_t reg, uint32_t val) |
| static void | tw32_mailbox2 (uint32_t reg, uint32_t val) |
| static void | tg3_write_mem (uint32_t off, uint32_t val) |
| static void | tg3_read_mem (uint32_t off, uint32_t *val) |
| static void | tg3_disable_ints (struct tg3 *tp) |
| static void | tg3_switch_clocks (struct tg3 *tp) |
| static int | tg3_readphy (struct tg3 *tp, int reg, uint32_t *val) |
| static int | tg3_writephy (struct tg3 *tp, int reg, uint32_t val) |
| static int | tg3_writedsp (struct tg3 *tp, uint16_t addr, uint16_t val) |
| static void | tg3_phy_set_wirespeed (struct tg3 *tp) |
| static int | tg3_bmcr_reset (struct tg3 *tp) |
| static int | tg3_wait_macro_done (struct tg3 *tp) |
| static int | tg3_phy_write_and_check_testpat (struct tg3 *tp, int *resetp) |
| static int | tg3_phy_reset_chanpat (struct tg3 *tp) |
| static int | tg3_phy_reset_5703_4_5 (struct tg3 *tp) |
| static int | tg3_phy_reset (struct tg3 *tp) |
| static void | tg3_set_power_state_0 (struct tg3 *tp) |
| static void | tg3_link_report (struct tg3 *tp) |
| static void | tg3_setup_flow_control (struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv) |
| static void | tg3_aux_stat_to_speed_duplex (struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex) |
| static int | tg3_phy_copper_begin (struct tg3 *tp) |
| static int | tg3_init_5401phy_dsp (struct tg3 *tp) |
| static int | tg3_setup_copper_phy (struct tg3 *tp) |
| static int | tg3_fiber_aneg_smachine (struct tg3 *tp, struct tg3_fiber_aneginfo *ap) |
| static int | tg3_setup_fiber_phy (struct tg3 *tp) |
| static int | tg3_setup_phy (struct tg3 *tp) |
| static int | tg3_stop_block (struct tg3 *tp, unsigned long ofs, uint32_t enable_bit) |
| static int | tg3_abort_hw (struct tg3 *tp) |
| static void | tg3_chip_reset (struct tg3 *tp) |
| static void | tg3_stop_fw (struct tg3 *tp) |
| static int | tg3_restart_fw (struct tg3 *tp, uint32_t state) |
| static int | tg3_halt (struct tg3 *tp) |
| static void | __tg3_set_mac_addr (struct tg3 *tp) |
| static void | tg3_set_bdinfo (struct tg3 *tp, uint32_t bdinfo_addr, dma_addr_t mapping, uint32_t maxlen_flags, uint32_t nic_addr) |
| static void | tg3_init_rings (struct tg3 *tp) |
| static int | tg3_setup_hw (struct tg3 *tp) |
| static void | tg3_nvram_init (struct tg3 *tp) |
| static int | tg3_nvram_read_using_eeprom (struct tg3 *tp __unused, uint32_t offset, uint32_t *val) |
| static int | tg3_nvram_read (struct tg3 *tp, uint32_t offset, uint32_t *val) |
| static int | tg3_phy_probe (struct tg3 *tp) |
| static void | tg3_read_partno (struct tg3 *tp) |
| static int | tg3_get_invariants (struct tg3 *tp) |
| static int | tg3_get_device_address (struct tg3 *tp) |
| static int | tg3_setup_dma (struct tg3 *tp) |
| static void | tg3_init_link_config (struct tg3 *tp) |
| static const char * | tg3_phy_string (struct tg3 *tp) |
| static void | tg3_poll_link (struct tg3 *tp) |
| static void | tg3_ack_irqs (struct tg3 *tp) |
| static int | tg3_poll (struct nic *nic, int retrieve) |
| static void | tg3_transmit (struct nic *nic, const char *dst_addr, unsigned int type, unsigned int size, const char *packet) |
| static void | tg3_disable (struct nic *nic __unused) |
| static void | tg3_irq (struct nic *nic __unused, irq_action_t action __unused) |
| static int | tg3_probe (struct nic *nic, struct pci_device *pdev) |
| PCI_DRIVER (tg3_driver, tg3_nics, PCI_NO_CLASS) | |
| DRIVER ("TG3", nic_driver, pci_driver, tg3_driver, tg3_probe, tg3_disable) | |
Variables | |
| static struct tg3 | tg3 |
| struct bss | __shared |
| static struct subsys_tbl_ent | subsys_id_to_phy_id [] |
| static struct nic_operations | tg3_operations |
| static struct pci_device_id | tg3_nics [] |
| #define TG3_RX_RING_SIZE 512 |
| #define TG3_DEF_RX_RING_PENDING 20 |
| #define TG3_RX_RCB_RING_SIZE 1024 |
| #define TG3_TX_RING_SIZE 512 |
| #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE) |
| #define TG3_RX_RCB_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE) |
| #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE) |
| #define NEXT_TX | ( | N | ) | (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
| #define PREV_TX | ( | N | ) | (((N) - 1) & (TG3_TX_RING_SIZE - 1)) |
| #define tw32 | ( | reg, | |||
| val | ) | tg3_write_indirect_reg32((reg),(val)) |
Definition at line 110 of file tg3.c.
Referenced by __tg3_set_mac_addr(), tg3_abort_hw(), tg3_chip_reset(), tg3_disable_ints(), tg3_fiber_aneg_smachine(), tg3_get_invariants(), tg3_nvram_init(), tg3_nvram_read(), tg3_nvram_read_using_eeprom(), tg3_setup_copper_phy(), tg3_setup_dma(), tg3_setup_fiber_phy(), tg3_setup_hw(), tg3_setup_phy(), tg3_stop_block(), tg3_stop_fw(), and tw32_carefully().
| #define tw32_mailbox | ( | reg, | |||
| val | ) | writel(((val) & 0xffffffff), tg3.regs + (reg)) |
Definition at line 111 of file tg3.c.
Referenced by tg3_ack_irqs(), tg3_setup_hw(), tg3_transmit(), and tw32_mailbox2().
| #define tw16 | ( | reg, | |||
| val | ) | writew(((val) & 0xffff), tg3.regs + (reg)) |
| #define tw8 | ( | reg, | |||
| val | ) | writeb(((val) & 0xff), tg3.regs + (reg)) |
| #define tr32 | ( | reg | ) | readl(tg3.regs + (reg)) |
Definition at line 114 of file tg3.c.
Referenced by tg3_abort_hw(), tg3_ack_irqs(), tg3_chip_reset(), tg3_fiber_aneg_smachine(), tg3_get_device_address(), tg3_get_invariants(), tg3_nvram_init(), tg3_nvram_read(), tg3_nvram_read_using_eeprom(), tg3_poll_link(), tg3_readphy(), tg3_setup_dma(), tg3_setup_fiber_phy(), tg3_setup_hw(), tg3_stop_block(), tg3_stop_fw(), tg3_switch_clocks(), tg3_writephy(), tw32_carefully(), and tw32_mailbox2().
| #define PHY_BUSY_LOOPS 5000 |
| #define ANEG_STATE_UNKNOWN 0 |
Definition at line 910 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define ANEG_STATE_AN_ENABLE 1 |
| #define ANEG_STATE_RESTART_INIT 2 |
| #define ANEG_STATE_RESTART 3 |
| #define ANEG_STATE_DISABLE_LINK_OK 4 |
| #define ANEG_STATE_ABILITY_DETECT_INIT 5 |
| #define ANEG_STATE_ABILITY_DETECT 6 |
| #define ANEG_STATE_ACK_DETECT_INIT 7 |
| #define ANEG_STATE_ACK_DETECT 8 |
| #define ANEG_STATE_COMPLETE_ACK_INIT 9 |
| #define ANEG_STATE_COMPLETE_ACK 10 |
| #define ANEG_STATE_IDLE_DETECT_INIT 11 |
| #define ANEG_STATE_IDLE_DETECT 12 |
| #define ANEG_STATE_LINK_OK 13 |
| #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 |
| #define ANEG_STATE_NEXT_PAGE_WAIT 15 |
| #define MR_AN_ENABLE 0x00000001 |
Definition at line 928 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define MR_RESTART_AN 0x00000002 |
| #define MR_AN_COMPLETE 0x00000004 |
Definition at line 930 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define MR_PAGE_RX 0x00000008 |
| #define MR_NP_LOADED 0x00000010 |
| #define MR_TOGGLE_TX 0x00000020 |
| #define MR_LP_ADV_FULL_DUPLEX 0x00000040 |
Definition at line 934 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define MR_LP_ADV_HALF_DUPLEX 0x00000080 |
| #define MR_LP_ADV_SYM_PAUSE 0x00000100 |
Definition at line 936 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define MR_LP_ADV_ASYM_PAUSE 0x00000200 |
Definition at line 937 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 |
| #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 |
| #define MR_LP_ADV_NEXT_PAGE 0x00001000 |
| #define MR_TOGGLE_RX 0x00002000 |
| #define MR_NP_RX 0x00004000 |
| #define MR_LINK_OK 0x80000000 |
Definition at line 944 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define ANEG_CFG_NP 0x00000080 |
| #define ANEG_CFG_ACK 0x00000040 |
| #define ANEG_CFG_RF2 0x00000020 |
| #define ANEG_CFG_RF1 0x00000010 |
| #define ANEG_CFG_PS2 0x00000001 |
| #define ANEG_CFG_PS1 0x00008000 |
| #define ANEG_CFG_HD 0x00004000 |
| #define ANEG_CFG_FD 0x00002000 |
| #define ANEG_CFG_INVAL 0x00001f06 |
| #define ANEG_OK 0 |
| #define ANEG_DONE 1 |
Definition at line 966 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define ANEG_TIMER_ENAB 2 |
| #define ANEG_FAILED -1 |
Definition at line 968 of file tg3.c.
Referenced by tg3_fiber_aneg_smachine(), and tg3_setup_fiber_phy().
| #define ANEG_STATE_SETTLE_TIME 10000 |
| #define MAX_WAIT_CNT 1000 |
| #define TG3_WRITE_SETTINGS | ( | TABLE | ) |
Value:
do { \ const uint32_t *_table, *_end; \ _table = TABLE; \ _end = _table + sizeof(TABLE)/sizeof(TABLE[0]); \ for(; _table < _end; _table += 2) { \ tw32(_table[0], _table[1]); \ } \ } while(0)
Definition at line 1790 of file tg3.c.
Referenced by tg3_setup_hw().
| #define T3_PCIE_CAPABILITY_ID_REG 0xD0 |
| #define T3_PCIE_CAPABILITY_ID 0x10 |
| #define T3_PCIE_CAPABILITY_REG 0xD2 |
| #define PCI_DEVICE_ID_TIGON3_5901 0x170d |
Referenced by tg3_get_invariants().
| #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e |
Referenced by tg3_get_invariants().
| FILE_LICENCE | ( | GPL2_ONLY | ) |
| static int pci_save_state | ( | struct pci_device * | dev, | |
| uint32_t * | buffer | |||
| ) | [static] |
pci_save_state - save the PCI configuration space of a device before suspending : - PCI device that we're dealing with : - buffer to hold config space context
must be large enough to hold the entire PCI 2.2 config space (>= 64 bytes).
Definition at line 81 of file tg3.c.
References pci_read_config_dword().
Referenced by tg3_probe().
00082 { 00083 int i; 00084 for (i = 0; i < 16; i++) 00085 pci_read_config_dword(dev, i * 4,&buffer[i]); 00086 return 0; 00087 }
| static int pci_restore_state | ( | struct pci_device * | dev, | |
| uint32_t * | buffer | |||
| ) | [static] |
pci_restore_state - Restore the saved state of a PCI device : - PCI device that we're dealing with : - saved PCI config space
Definition at line 95 of file tg3.c.
References pci_write_config_dword().
Referenced by tg3_chip_reset().
00096 { 00097 int i; 00098 00099 for (i = 0; i < 16; i++) 00100 pci_write_config_dword(dev,i * 4, buffer[i]); 00101 return 0; 00102 }
Definition at line 104 of file tg3.c.
References pci_write_config_dword(), TG3PCI_REG_BASE_ADDR, and TG3PCI_REG_DATA.
00105 { 00106 pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off); 00107 pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val); 00108 }
Definition at line 118 of file tg3.c.
References tr32, tw32, and udelay().
Referenced by tg3_abort_hw(), tg3_fiber_aneg_smachine(), tg3_get_invariants(), tg3_nvram_init(), tg3_poll_link(), tg3_readphy(), tg3_set_power_state_0(), tg3_setup_copper_phy(), tg3_setup_fiber_phy(), tg3_setup_hw(), tg3_switch_clocks(), and tg3_writephy().
Definition at line 125 of file tg3.c.
References tr32, and tw32_mailbox.
Referenced by tg3_disable_ints(), tg3_poll(), tg3_setup_hw(), and tg3_transmit().
00126 { 00127 tw32_mailbox(reg, val); 00128 tr32(reg); 00129 }
Definition at line 131 of file tg3.c.
References pci_write_config_dword(), TG3PCI_MEM_WIN_BASE_ADDR, and TG3PCI_MEM_WIN_DATA.
Referenced by tg3_restart_fw(), tg3_set_bdinfo(), tg3_setup_copper_phy(), tg3_setup_hw(), and tg3_stop_fw().
00132 { 00133 pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); 00134 pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val); 00135 00136 /* Always leave this as zero. */ 00137 pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); 00138 }
Definition at line 140 of file tg3.c.
References pci_read_config_dword(), pci_write_config_dword(), TG3PCI_MEM_WIN_BASE_ADDR, and TG3PCI_MEM_WIN_DATA.
Referenced by tg3_get_device_address(), tg3_phy_probe(), and tg3_restart_fw().
00141 { 00142 pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); 00143 pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val); 00144 00145 /* Always leave this as zero. */ 00146 pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); 00147 }
| static void tg3_disable_ints | ( | struct tg3 * | tp | ) | [static] |
Definition at line 149 of file tg3.c.
References MAILBOX_INTERRUPT_0, tg3::misc_host_ctrl, MISC_HOST_CTRL_MASK_PCI_INT, TG3_64BIT_REG_LOW, TG3PCI_MISC_HOST_CTRL, tw32, and tw32_mailbox2().
Referenced by tg3_abort_hw(), and tg3_setup_hw().
00150 { 00151 tw32(TG3PCI_MISC_HOST_CTRL, 00152 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); 00153 tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); 00154 }
| static void tg3_switch_clocks | ( | struct tg3 * | tp | ) | [static] |
Definition at line 156 of file tg3.c.
References ASIC_REV_5705, ASIC_REV_5750, CLOCK_CTRL_44MHZ_CORE, CLOCK_CTRL_ALTCLK, CLOCK_CTRL_CLKRUN_OENABLE, CLOCK_CTRL_FORCE_CLKRUN, GET_ASIC_REV, tg3::pci_chip_rev_id, tg3::pci_clock_ctrl, TG3_FLAG_ENABLE_ASF, tg3::tg3_flags, TG3PCI_CLOCK_CTRL, tr32, and tw32_carefully().
Referenced by tg3_get_invariants(), and tg3_setup_hw().
00157 { 00158 uint32_t orig_clock_ctrl, clock_ctrl; 00159 00160 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); 00161 00162 orig_clock_ctrl = clock_ctrl; 00163 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE | 0x1f); 00164 tp->pci_clock_ctrl = clock_ctrl; 00165 00166 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) && 00167 (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) 00168 && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) && 00169 (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) { 00170 tw32_carefully(TG3PCI_CLOCK_CTRL, 00171 clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK)); 00172 tw32_carefully(TG3PCI_CLOCK_CTRL, 00173 clock_ctrl | (CLOCK_CTRL_ALTCLK)); 00174 } 00175 tw32_carefully(TG3PCI_CLOCK_CTRL, clock_ctrl); 00176 }
Definition at line 180 of file tg3.c.
References EBUSY, MAC_MI_COM, MAC_MI_MODE, MAC_MI_MODE_AUTO_POLL, MI_COM_BUSY, MI_COM_CMD_READ, MI_COM_DATA_MASK, MI_COM_PHY_ADDR_MASK, MI_COM_PHY_ADDR_SHIFT, MI_COM_REG_ADDR_MASK, MI_COM_REG_ADDR_SHIFT, MI_COM_START, tg3::mi_mode, PHY_ADDR, PHY_BUSY_LOOPS, tr32, tw32_carefully(), and udelay().
Referenced by tg3_bmcr_reset(), tg3_phy_probe(), tg3_phy_reset(), tg3_phy_reset_5703_4_5(), tg3_phy_set_wirespeed(), tg3_phy_write_and_check_testpat(), tg3_setup_copper_phy(), and tg3_wait_macro_done().
00181 { 00182 uint32_t frame_val; 00183 int loops, ret; 00184 00185 tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL); 00186 00187 *val = 0xffffffff; 00188 00189 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & 00190 MI_COM_PHY_ADDR_MASK); 00191 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & 00192 MI_COM_REG_ADDR_MASK); 00193 frame_val |= (MI_COM_CMD_READ | MI_COM_START); 00194 00195 tw32_carefully(MAC_MI_COM, frame_val); 00196 00197 loops = PHY_BUSY_LOOPS; 00198 while (loops-- > 0) { 00199 udelay(10); 00200 frame_val = tr32(MAC_MI_COM); 00201 00202 if ((frame_val & MI_COM_BUSY) == 0) { 00203 udelay(5); 00204 frame_val = tr32(MAC_MI_COM); 00205 break; 00206 } 00207 } 00208 00209 ret = -EBUSY; 00210 if (loops > 0) { 00211 *val = frame_val & MI_COM_DATA_MASK; 00212 ret = 0; 00213 } 00214 00215 tw32_carefully(MAC_MI_MODE, tp->mi_mode); 00216 00217 return ret; 00218 }
Definition at line 220 of file tg3.c.
References EBUSY, MAC_MI_COM, MAC_MI_MODE, MAC_MI_MODE_AUTO_POLL, MI_COM_BUSY, MI_COM_CMD_WRITE, MI_COM_DATA_MASK, MI_COM_PHY_ADDR_MASK, MI_COM_PHY_ADDR_SHIFT, MI_COM_REG_ADDR_MASK, MI_COM_REG_ADDR_SHIFT, MI_COM_START, tg3::mi_mode, PHY_ADDR, PHY_BUSY_LOOPS, tr32, tw32_carefully(), and udelay().
Referenced by tg3_bmcr_reset(), tg3_init_5401phy_dsp(), tg3_phy_copper_begin(), tg3_phy_probe(), tg3_phy_reset(), tg3_phy_reset_5703_4_5(), tg3_phy_reset_chanpat(), tg3_phy_set_wirespeed(), tg3_phy_write_and_check_testpat(), tg3_setup_copper_phy(), tg3_setup_fiber_phy(), and tg3_writedsp().
00221 { 00222 uint32_t frame_val; 00223 int loops, ret; 00224 00225 tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL); 00226 00227 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) & 00228 MI_COM_PHY_ADDR_MASK); 00229 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & 00230 MI_COM_REG_ADDR_MASK); 00231 frame_val |= (val & MI_COM_DATA_MASK); 00232 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); 00233 00234 tw32_carefully(MAC_MI_COM, frame_val); 00235 00236 loops = PHY_BUSY_LOOPS; 00237 while (loops-- > 0) { 00238 udelay(10); 00239 frame_val = tr32(MAC_MI_COM); 00240 if ((frame_val & MI_COM_BUSY) == 0) { 00241 udelay(5); 00242 frame_val = tr32(MAC_MI_COM); 00243 break; 00244 } 00245 } 00246 00247 ret = -EBUSY; 00248 if (loops > 0) 00249 ret = 0; 00250 00251 tw32_carefully(MAC_MI_MODE, tp->mi_mode); 00252 00253 return ret; 00254 }
Definition at line 256 of file tg3.c.
References MII_TG3_DSP_ADDRESS, MII_TG3_DSP_RW_PORT, and tg3_writephy().
Referenced by tg3_init_5401phy_dsp(), and tg3_phy_probe().
00257 { 00258 int err; 00259 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr); 00260 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); 00261 return err; 00262 }
| static void tg3_phy_set_wirespeed | ( | struct tg3 * | tp | ) | [static] |
Definition at line 265 of file tg3.c.
References MII_TG3_AUX_CTRL, tg3::tg3_flags2, TG3_FLG2_NO_ETH_WIRE_SPEED, tg3_readphy(), and tg3_writephy().
Referenced by tg3_phy_probe(), and tg3_phy_reset().
00266 { 00267 uint32_t val; 00268 00269 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) 00270 return; 00271 00272 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007); 00273 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); 00274 tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4))); 00275 }
| static int tg3_bmcr_reset | ( | struct tg3 * | tp | ) | [static] |
Definition at line 277 of file tg3.c.
References BMCR_RESET, EBUSY, MII_BMCR, tg3_readphy(), tg3_writephy(), and udelay().
Referenced by tg3_phy_reset(), and tg3_phy_reset_5703_4_5().
00278 { 00279 uint32_t phy_control; 00280 int limit, err; 00281 00282 /* OK, reset it, and poll the BMCR_RESET bit until it 00283 * clears or we time out. 00284 */ 00285 phy_control = BMCR_RESET; 00286 err = tg3_writephy(tp, MII_BMCR, phy_control); 00287 if (err != 0) 00288 return -EBUSY; 00289 00290 limit = 5000; 00291 while (limit--) { 00292 err = tg3_readphy(tp, MII_BMCR, &phy_control); 00293 if (err != 0) 00294 return -EBUSY; 00295 00296 if ((phy_control & BMCR_RESET) == 0) { 00297 udelay(40); 00298 break; 00299 } 00300 udelay(10); 00301 } 00302 if (limit <= 0) 00303 return -EBUSY; 00304 00305 return 0; 00306 }
| static int tg3_wait_macro_done | ( | struct tg3 * | tp | ) | [static] |
Definition at line 308 of file tg3.c.
References EBUSY, and tg3_readphy().
Referenced by tg3_phy_reset_chanpat(), and tg3_phy_write_and_check_testpat().
00309 { 00310 int limit = 100; 00311 00312 while (limit--) { 00313 uint32_t tmp32; 00314 00315 tg3_readphy(tp, 0x16, &tmp32); 00316 if ((tmp32 & 0x1000) == 0) 00317 break; 00318 } 00319 if (limit <= 0) 00320 return -EBUSY; 00321 00322 return 0; 00323 }
| static int tg3_phy_write_and_check_testpat | ( | struct tg3 * | tp, | |
| int * | resetp | |||
| ) | [static] |
Definition at line 325 of file tg3.c.
References EBUSY, MII_TG3_DSP_ADDRESS, MII_TG3_DSP_RW_PORT, tg3_readphy(), tg3_wait_macro_done(), and tg3_writephy().
Referenced by tg3_phy_reset_5703_4_5().
00326 { 00327 static const uint32_t test_pat[4][6] = { 00328 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, 00329 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, 00330 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, 00331 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } 00332 }; 00333 int chan; 00334 00335 for (chan = 0; chan < 4; chan++) { 00336 int i; 00337 00338 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 00339 (chan * 0x2000) | 0x0200); 00340 tg3_writephy(tp, 0x16, 0x0002); 00341 00342 for (i = 0; i < 6; i++) 00343 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 00344 test_pat[chan][i]); 00345 00346 tg3_writephy(tp, 0x16, 0x0202); 00347 if (tg3_wait_macro_done(tp)) { 00348 *resetp = 1; 00349 return -EBUSY; 00350 } 00351 00352 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 00353 (chan * 0x2000) | 0x0200); 00354 tg3_writephy(tp, 0x16, 0x0082); 00355 if (tg3_wait_macro_done(tp)) { 00356 *resetp = 1; 00357 return -EBUSY; 00358 } 00359 00360 tg3_writephy(tp, 0x16, 0x0802); 00361 if (tg3_wait_macro_done(tp)) { 00362 *resetp = 1; 00363 return -EBUSY; 00364 } 00365 00366 for (i = 0; i < 6; i += 2) { 00367 uint32_t low, high; 00368 00369 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low); 00370 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high); 00371 if (tg3_wait_macro_done(tp)) { 00372 *resetp = 1; 00373 return -EBUSY; 00374 } 00375 low &= 0x7fff; 00376 high &= 0x000f; 00377 if (low != test_pat[chan][i] || 00378 high != test_pat[chan][i+1]) { 00379 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); 00380 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); 00381 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); 00382 00383 return -EBUSY; 00384 } 00385 } 00386 } 00387 00388 return 0; 00389 }
| static int tg3_phy_reset_chanpat | ( | struct tg3 * | tp | ) | [static] |
Definition at line 391 of file tg3.c.
References EBUSY, MII_TG3_DSP_ADDRESS, MII_TG3_DSP_RW_PORT, tg3_wait_macro_done(), and tg3_writephy().
Referenced by tg3_phy_reset_5703_4_5().
00392 { 00393 int chan; 00394 00395 for (chan = 0; chan < 4; chan++) { 00396 int i; 00397 00398 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 00399 (chan * 0x2000) | 0x0200); 00400 tg3_writephy(tp, 0x16, 0x0002); 00401 for (i = 0; i < 6; i++) 00402 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); 00403 tg3_writephy(tp, 0x16, 0x0202); 00404 if (tg3_wait_macro_done(tp)) 00405 return -EBUSY; 00406 } 00407 00408 return 0; 00409 }
| static int tg3_phy_reset_5703_4_5 | ( | struct tg3 * | tp | ) | [static] |
Definition at line 411 of file tg3.c.
References BMCR_FULLDPLX, MII_BMCR, MII_TG3_AUX_CTRL, MII_TG3_CTRL, MII_TG3_CTRL_AS_MASTER, MII_TG3_CTRL_ENABLE_AS_MASTER, MII_TG3_DSP_ADDRESS, MII_TG3_DSP_RW_PORT, MII_TG3_EXT_CTRL, tg3_bmcr_reset(), TG3_BMCR_SPEED1000, tg3_phy_reset_chanpat(), tg3_phy_write_and_check_testpat(), tg3_readphy(), and tg3_writephy().
Referenced by tg3_phy_reset().
00412 { 00413 uint32_t reg32, phy9_orig; 00414 int retries, do_phy_reset, err; 00415 00416 retries = 10; 00417 do_phy_reset = 1; 00418 do { 00419 if (do_phy_reset) { 00420 err = tg3_bmcr_reset(tp); 00421 if (err) 00422 return err; 00423 do_phy_reset = 0; 00424 } 00425 00426 /* Disable transmitter and interrupt. */ 00427 tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); 00428 reg32 |= 0x3000; 00429 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); 00430 00431 /* Set full-duplex, 1000 mbps. */ 00432 tg3_writephy(tp, MII_BMCR, 00433 BMCR_FULLDPLX | TG3_BMCR_SPEED1000); 00434 00435 /* Set to master mode. */ 00436 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig); 00437 tg3_writephy(tp, MII_TG3_CTRL, 00438 (MII_TG3_CTRL_AS_MASTER | 00439 MII_TG3_CTRL_ENABLE_AS_MASTER)); 00440 00441 /* Enable SM_DSP_CLOCK and 6dB. */ 00442 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); 00443 00444 /* Block the PHY control access. */ 00445 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); 00446 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800); 00447 00448 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); 00449 if (!err) 00450 break; 00451 } while (--retries); 00452 00453 err = tg3_phy_reset_chanpat(tp); 00454 if (err) 00455 return err; 00456 00457 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); 00458 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000); 00459 00460 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); 00461 tg3_writephy(tp, 0x16, 0x0000); 00462 00463 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 00464 00465 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); 00466 00467 tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); 00468 reg32 &= ~0x3000; 00469 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); 00470 00471 return err; 00472 }
| static int tg3_phy_reset | ( | struct tg3 * | tp | ) | [static] |
Definition at line 477 of file tg3.c.
References ASIC_REV_5703, ASIC_REV_5704, ASIC_REV_5705, ASIC_REV_5750, EBUSY, GET_ASIC_REV, MII_BMSR, tg3::pci_chip_rev_id, tg3_bmcr_reset(), tg3_phy_reset_5703_4_5(), tg3_phy_set_wirespeed(), tg3_readphy(), and tg3_writephy().
Referenced by tg3_phy_probe(), and tg3_setup_copper_phy().
00478 { 00479 uint32_t phy_status; 00480 int err; 00481 00482 err = tg3_readphy(tp, MII_BMSR, &phy_status); 00483 err |= tg3_readphy(tp, MII_BMSR, &phy_status); 00484 if (err != 0) 00485 return -EBUSY; 00486 00487 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || 00488 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || 00489 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) { 00490 err = tg3_phy_reset_5703_4_5(tp); 00491 if (err) 00492 return err; 00493 goto out; 00494 } 00495 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 00496 // Taken from Broadcom's source code 00497 tg3_writephy(tp, 0x18, 0x0c00); 00498 tg3_writephy(tp, 0x17, 0x000a); 00499 tg3_writephy(tp, 0x15, 0x310b); 00500 tg3_writephy(tp, 0x17, 0x201f); 00501 tg3_writephy(tp, 0x15, 0x9506); 00502 tg3_writephy(tp, 0x17, 0x401f); 00503 tg3_writephy(tp, 0x15, 0x14e2); 00504 tg3_writephy(tp, 0x18, 0x0400); 00505 } 00506 err = tg3_bmcr_reset(tp); 00507 if (err) 00508 return err; 00509 out: 00510 tg3_phy_set_wirespeed(tp); 00511 return 0; 00512 }
| static void tg3_set_power_state_0 | ( | struct tg3 * | tp | ) | [static] |
Definition at line 514 of file tg3.c.
References tg3::grc_local_ctrl, GRC_LOCAL_CTRL, tg3::misc_host_ctrl, PCI_PM_CTRL, PCI_PM_CTRL_PME_STATUS, PCI_PM_CTRL_STATE_MASK, pci_read_config_word(), pci_write_config_dword(), pci_write_config_word(), tg3::pdev, tg3::pm_cap, TG3PCI_MISC_HOST_CTRL, and tw32_carefully().
Referenced by tg3_get_invariants(), and tg3_setup_hw().
00515 { 00516 uint16_t power_control; 00517 int pm = tp->pm_cap; 00518 00519 /* Make sure register accesses (indirect or otherwise) 00520 * will function correctly. 00521 */ 00522 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); 00523 00524 pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control); 00525 00526 power_control |= PCI_PM_CTRL_PME_STATUS; 00527 power_control &= ~(PCI_PM_CTRL_STATE_MASK); 00528 power_control |= 0; 00529 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control); 00530 00531 tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 00532 00533 return; 00534 }
| static void tg3_link_report | ( | struct tg3 * | tp | ) | [static] |
Definition at line 538 of file tg3.c.
References tg3_link_config::active_duplex, tg3_link_config::active_speed, tg3::carrier_ok, DUPLEX_FULL, tg3::link_config, printf(), SPEED_100, SPEED_1000, TG3_FLAG_RX_PAUSE, TG3_FLAG_TX_PAUSE, and tg3::tg3_flags.
Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_phy().
00539 { 00540 if (!tp->carrier_ok) { 00541 printf("Link is down.\n"); 00542 } else { 00543 printf("Link is up at %d Mbps, %s duplex. %s %s %s\n", 00544 (tp->link_config.active_speed == SPEED_1000 ? 00545 1000 : 00546 (tp->link_config.active_speed == SPEED_100 ? 00547 100 : 10)), 00548 (tp->link_config.active_duplex == DUPLEX_FULL ? 00549 "full" : "half"), 00550 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "", 00551 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "", 00552 (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : ""); 00553 } 00554 }
| static void tg3_setup_flow_control | ( | struct tg3 * | tp, | |
| uint32_t | local_adv, | |||
| uint32_t | remote_adv | |||
| ) | [static] |
Definition at line 559 of file tg3.c.
References ADVERTISE_PAUSE_ASYM, ADVERTISE_PAUSE_CAP, LPA_PAUSE_ASYM, LPA_PAUSE_CAP, tg3::rx_mode, RX_MODE_FLOW_CTRL_ENABLE, TG3_FLAG_RX_PAUSE, TG3_FLAG_TX_PAUSE, tg3::tg3_flags, tg3::tx_mode, and TX_MODE_FLOW_CTRL_ENABLE.
Referenced by tg3_setup_copper_phy(), and tg3_setup_fiber_phy().
00560 { 00561 uint32_t new_tg3_flags = 0; 00562 00563 if (local_adv & ADVERTISE_PAUSE_CAP) { 00564 if (local_adv & ADVERTISE_PAUSE_ASYM) { 00565 if (remote_adv & LPA_PAUSE_CAP) 00566 new_tg3_flags |= 00567 (TG3_FLAG_RX_PAUSE | 00568 TG3_FLAG_TX_PAUSE); 00569 else if (remote_adv & LPA_PAUSE_ASYM) 00570 new_tg3_flags |= 00571 (TG3_FLAG_RX_PAUSE); 00572 } else { 00573 if (remote_adv & LPA_PAUSE_CAP) 00574 new_tg3_flags |= 00575 (TG3_FLAG_RX_PAUSE | 00576 TG3_FLAG_TX_PAUSE); 00577 } 00578 } else if (local_adv & ADVERTISE_PAUSE_ASYM) { 00579 if ((remote_adv & LPA_PAUSE_CAP) && 00580 (remote_adv & LPA_PAUSE_ASYM)) 00581 new_tg3_flags |= TG3_FLAG_TX_PAUSE; 00582 } 00583 00584 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE); 00585 tp->tg3_flags |= new_tg3_flags; 00586 00587 if (new_tg3_flags & TG3_FLAG_RX_PAUSE) 00588 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; 00589 else 00590 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; 00591 00592 if (new_tg3_flags & TG3_FLAG_TX_PAUSE) 00593 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; 00594 else 00595 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; 00596 }
| static void tg3_aux_stat_to_speed_duplex | ( | struct tg3 *tp | __unused, | |
| uint32_t | val, | |||
| uint8_t * | speed, | |||
| uint8_t * | duplex | |||
| ) | [static] |
Definition at line 599 of file tg3.c.
References DUPLEX_FULL, DUPLEX_HALF, DUPLEX_INVALID, MII_TG3_AUX_STAT_1000FULL, MII_TG3_AUX_STAT_1000HALF, MII_TG3_AUX_STAT_100_4, MII_TG3_AUX_STAT_100FULL, MII_TG3_AUX_STAT_100HALF, MII_TG3_AUX_STAT_10FULL, MII_TG3_AUX_STAT_10HALF, MII_TG3_AUX_STAT_SPDMASK, SPEED_10, SPEED_100, SPEED_1000, and SPEED_INVALID.
Referenced by tg3_setup_copper_phy().
00601 { 00602 static const uint8_t map[] = { 00603 [0] = (SPEED_INVALID << 2) | DUPLEX_INVALID, 00604 [MII_TG3_AUX_STAT_10HALF >> 8] = (SPEED_10 << 2) | DUPLEX_HALF, 00605 [MII_TG3_AUX_STAT_10FULL >> 8] = (SPEED_10 << 2) | DUPLEX_FULL, 00606 [MII_TG3_AUX_STAT_100HALF >> 8] = (SPEED_100 << 2) | DUPLEX_HALF, 00607 [MII_TG3_AUX_STAT_100_4 >> 8] = (SPEED_INVALID << 2) | DUPLEX_INVALID, 00608 [MII_TG3_AUX_STAT_100FULL >> 8] = (SPEED_100 << 2) | DUPLEX_FULL, 00609 [MII_TG3_AUX_STAT_1000HALF >> 8] = (SPEED_1000 << 2) | DUPLEX_HALF, 00610 [MII_TG3_AUX_STAT_1000FULL >> 8] = (SPEED_1000 << 2) | DUPLEX_FULL, 00611 }; 00612 uint8_t result; 00613 result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8]; 00614 *speed = result >> 2; 00615 *duplex = result & 3; 00616 }
| static int tg3_phy_copper_begin | ( | struct tg3 * | tp | ) | [static] |
Definition at line 618 of file tg3.c.
References ADVERTISE_100FULL, ADVERTISE_100HALF, ADVERTISE_10FULL, ADVERTISE_10HALF, ADVERTISE_CSMA, ADVERTISE_PAUSE_CAP, ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_100baseT_Full, ADVERTISED_100baseT_Half, ADVERTISED_10baseT_Full, ADVERTISED_10baseT_Half, ADVERTISED_Autoneg, ADVERTISED_MII, tg3_link_config::advertising, BMCR_ANENABLE, BMCR_ANRESTART, CHIPREV_ID_5701_A0, CHIPREV_ID_5701_B0, tg3::link_config, MII_ADVERTISE, MII_BMCR, MII_TG3_CTRL, MII_TG3_CTRL_ADV_1000_FULL, MII_TG3_CTRL_ADV_1000_HALF, MII_TG3_CTRL_AS_MASTER, MII_TG3_CTRL_ENABLE_AS_MASTER, tg3::pci_chip_rev_id, TG3_FLAG_10_100_ONLY, tg3::tg3_flags, and tg3_writephy().
Referenced by tg3_setup_copper_phy().
00619 { 00620 uint32_t new_adv; 00621 00622 tp->link_config.advertising = 00623 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | 00624 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | 00625 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | 00626 ADVERTISED_Autoneg | ADVERTISED_MII); 00627 00628 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) { 00629 tp->link_config.advertising &= 00630 ~(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); 00631 } 00632 00633 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); 00634 if (tp->link_config.advertising & ADVERTISED_10baseT_Half) { 00635 new_adv |= ADVERTISE_10HALF; 00636 } 00637 if (tp->link_config.advertising & ADVERTISED_10baseT_Full) { 00638 new_adv |= ADVERTISE_10FULL; 00639 } 00640 if (tp->link_config.advertising & ADVERTISED_100baseT_Half) { 00641 new_adv |= ADVERTISE_100HALF; 00642 } 00643 if (tp->link_config.advertising & ADVERTISED_100baseT_Full) { 00644 new_adv |= ADVERTISE_100FULL; 00645 } 00646 tg3_writephy(tp, MII_ADVERTISE, new_adv); 00647 00648 if (tp->link_config.advertising & 00649 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { 00650 new_adv = 0; 00651 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) { 00652 new_adv |= MII_TG3_CTRL_ADV_1000_HALF; 00653 } 00654 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) { 00655 new_adv |= MII_TG3_CTRL_ADV_1000_FULL; 00656 } 00657 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) && 00658 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || 00659 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) { 00660 new_adv |= (MII_TG3_CTRL_AS_MASTER | 00661 MII_TG3_CTRL_ENABLE_AS_MASTER); 00662 } 00663 tg3_writephy(tp, MII_TG3_CTRL, new_adv); 00664 } else { 00665 tg3_writephy(tp, MII_TG3_CTRL, 0); 00666 } 00667 00668 tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); 00669 00670 return 0; 00671 }
| static int tg3_init_5401phy_dsp | ( | struct tg3 * | tp | ) | [static] |
Definition at line 673 of file tg3.c.
References MII_TG3_AUX_CTRL, tg3_writedsp(), tg3_writephy(), and udelay().
Referenced by tg3_phy_probe(), and tg3_setup_copper_phy().
00674 { 00675 int err; 00676 00677 /* Turn off tap power management. */ 00678 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20); 00679 00680 err |= tg3_writedsp(tp, 0x0012, 0x1804); 00681 err |= tg3_writedsp(tp, 0x0013, 0x1204); 00682 err |= tg3_writedsp(tp, 0x8006, 0x0132); 00683 err |= tg3_writedsp(tp, 0x8006, 0x0232); 00684 err |= tg3_writedsp(tp, 0x201f, 0x0a20); 00685 00686 udelay(40); 00687 00688 return err; 00689 }
| static int tg3_setup_copper_phy | ( | struct tg3 * | tp | ) | [static] |
Definition at line 691 of file tg3.c.
References tg3_link_config::active_duplex, tg3_link_config::active_speed, ADVERTISE_PAUSE_ASYM, ADVERTISE_PAUSE_CAP, ASIC_REV_5700, ASIC_REV_5703, ASIC_REV_5704, BMCR_ANENABLE, BMSR_LSTATUS, tg3::carrier_ok, CHIPREV_ID_5700_ALTIMA, CHIPREV_ID_5701_A0, CHIPREV_ID_5701_B0, CHIPREV_ID_5705_A0, DUPLEX_FULL, DUPLEX_HALF, GET_ASIC_REV, LED_CTRL_PHY_MODE_1, tg3::led_mode, led_mode_link10, led_mode_three_link, tg3::link_config, LPA_PAUSE_ASYM, LPA_PAUSE_CAP, MAC_EVENT, MAC_LED_CTRL, MAC_MI_MODE, MAC_MI_MODE_AUTO_POLL, MAC_MI_MODE_BASE, MAC_MODE, tg3::mac_mode, MAC_MODE_HALF_DUPLEX, MAC_MODE_LINK_POLARITY, MAC_MODE_PORT_MODE_GMII, MAC_MODE_PORT_MODE_MASK, MAC_MODE_PORT_MODE_MII, MAC_STATUS, MAC_STATUS_CFG_CHANGED, MAC_STATUS_LNKSTATE_CHANGED, MAC_STATUS_SYNC_CHANGED, tg3::mi_mode, MII_ADVERTISE, MII_BMCR, MII_BMSR, MII_LPA, MII_TG3_AUX_CTRL, MII_TG3_AUX_STAT, MII_TG3_CTRL, MII_TG3_CTRL_ADV_1000_FULL, MII_TG3_CTRL_ADV_1000_HALF, MII_TG3_EXT_CTRL, MII_TG3_EXT_CTRL_LNK3_LED_MODE, MII_TG3_IMASK, MII_TG3_ISTAT, NIC_SRAM_FIRMWARE_MBOX, NIC_SRAM_FIRMWARE_MBOX_MAGIC2, tg3::pci_chip_rev_id, tg3::phy_id, PHY_ID_BCM5401, PHY_ID_BCM5411, PHY_ID_MASK, PHY_ID_REV_MASK, PHY_REV_BCM5401_B0, SPEED_10, SPEED_100, SPEED_1000, tg3_aux_stat_to_speed_duplex(), TG3_FLAG_INIT_COMPLETE, TG3_FLAG_PCI_HIGH_SPEED, TG3_FLAG_PCIX_MODE, tg3::tg3_flags, tg3_init_5401phy_dsp(), tg3_link_report(), tg3_phy_copper_begin(), tg3_phy_reset(), tg3_readphy(), tg3_setup_flow_control(), tg3_write_mem(), tg3_writephy(), tw32, tw32_carefully(), and udelay().
Referenced by tg3_setup_phy().
00692 { 00693 int current_link_up; 00694 uint32_t bmsr, dummy; 00695 int i, err; 00696 00697 tw32_carefully(MAC_STATUS, 00698 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED 00699 | MAC_STATUS_LNKSTATE_CHANGED)); 00700 00701 tp->mi_mode = MAC_MI_MODE_BASE; 00702 tw32_carefully(MAC_MI_MODE, tp->mi_mode); 00703 00704 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); 00705 00706 /* Some third-party PHYs need to be reset on link going 00707 * down. 00708 */ 00709 if ( ( (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || 00710 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || 00711 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) && 00712 (tp->carrier_ok)) { 00713 tg3_readphy(tp, MII_BMSR, &bmsr); 00714 tg3_readphy(tp, MII_BMSR, &bmsr); 00715 if (!(bmsr & BMSR_LSTATUS)) 00716 tg3_phy_reset(tp); 00717 } 00718 00719 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 00720 tg3_readphy(tp, MII_BMSR, &bmsr); 00721 tg3_readphy(tp, MII_BMSR, &bmsr); 00722 00723 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) 00724 bmsr = 0; 00725 00726 if (!(bmsr & BMSR_LSTATUS)) { 00727 err = tg3_init_5401phy_dsp(tp); 00728 if (err) 00729 return err; 00730 00731 tg3_readphy(tp, MII_BMSR, &bmsr); 00732 for (i = 0; i < 1000; i++) { 00733 udelay(10); 00734 tg3_readphy(tp, MII_BMSR, &bmsr); 00735 if (bmsr & BMSR_LSTATUS) { 00736 udelay(40); 00737 break; 00738 } 00739 } 00740 00741 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 && 00742 !(bmsr & BMSR_LSTATUS) && 00743 tp->link_config.active_speed == SPEED_1000) { 00744 err = tg3_phy_reset(tp); 00745 if (!err) 00746 err = tg3_init_5401phy_dsp(tp); 00747 if (err) 00748 return err; 00749 } 00750 } 00751 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || 00752 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { 00753 /* 5701 {A0,B0} CRC bug workaround */ 00754 tg3_writephy(tp, 0x15, 0x0a75); 00755 tg3_writephy(tp, 0x1c, 0x8c68); 00756 tg3_writephy(tp, 0x1c, 0x8d68); 00757 tg3_writephy(tp, 0x1c, 0x8c68); 00758 } 00759 00760 /* Clear pending interrupts... */ 00761 tg3_readphy(tp, MII_TG3_ISTAT, &dummy); 00762 tg3_readphy(tp, MII_TG3_ISTAT, &dummy); 00763 00764 tg3_writephy(tp, MII_TG3_IMASK, ~0); 00765 00766 if (tp->led_mode == led_mode_three_link) 00767 tg3_writephy(tp, MII_TG3_EXT_CTRL, 00768 MII_TG3_EXT_CTRL_LNK3_LED_MODE); 00769 else 00770 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); 00771 00772 current_link_up = 0; 00773 00774 tg3_readphy(tp, MII_BMSR, &bmsr); 00775 tg3_readphy(tp, MII_BMSR, &bmsr); 00776 00777 if (bmsr & BMSR_LSTATUS) { 00778 uint32_t aux_stat, bmcr; 00779 00780 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); 00781 for (i = 0; i < 2000; i++) { 00782 udelay(10); 00783 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); 00784 if (aux_stat) 00785 break; 00786 } 00787 00788 tg3_aux_stat_to_speed_duplex(tp, aux_stat, 00789 &tp->link_config.active_speed, 00790 &tp->link_config.active_duplex); 00791 tg3_readphy(tp, MII_BMCR, &bmcr); 00792 tg3_readphy(tp, MII_BMCR, &bmcr); 00793 if (bmcr & BMCR_ANENABLE) { 00794 uint32_t gig_ctrl; 00795 00796 current_link_up = 1; 00797 00798 /* Force autoneg restart if we are exiting 00799 * low power mode. 00800 */ 00801 tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl); 00802 if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF | 00803 MII_TG3_CTRL_ADV_1000_FULL))) { 00804 current_link_up = 0; 00805 } 00806 } else { 00807 current_link_up = 0; 00808 } 00809 } 00810 00811 if (current_link_up == 1 && 00812 (tp->link_config.active_duplex == DUPLEX_FULL)) { 00813 uint32_t local_adv, remote_adv; 00814 00815 tg3_readphy(tp, MII_ADVERTISE, &local_adv); 00816 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); 00817 00818 tg3_readphy(tp, MII_LPA, &remote_adv); 00819 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM); 00820 00821 /* If we are not advertising full pause capability, 00822 * something is wrong. Bring the link down and reconfigure. 00823 */ 00824 if (local_adv != ADVERTISE_PAUSE_CAP) { 00825 current_link_up = 0; 00826 } else { 00827 tg3_setup_flow_control(tp, local_adv, remote_adv); 00828 } 00829 } 00830 00831 if (current_link_up == 0) { 00832 uint32_t tmp; 00833 00834 tg3_phy_copper_begin(tp); 00835 00836 tg3_readphy(tp, MII_BMSR, &tmp); 00837 tg3_readphy(tp, MII_BMSR, &tmp); 00838 if (tmp & BMSR_LSTATUS) 00839 current_link_up = 1; 00840 } 00841 00842 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; 00843 if (current_link_up == 1) { 00844 if (tp->link_config.active_speed == SPEED_100 || 00845 tp->link_config.active_speed == SPEED_10) 00846 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; 00847 else 00848 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; 00849 } else 00850 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; 00851 00852 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; 00853 if (tp->link_config.active_duplex == DUPLEX_HALF) 00854 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; 00855 00856 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; 00857 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { 00858 if ((tp->led_mode == led_mode_link10) || 00859 (current_link_up == 1 && 00860 tp->link_config.active_speed == SPEED_10)) 00861 tp->mac_mode |= MAC_MODE_LINK_POLARITY; 00862 } else { 00863 if (current_link_up == 1) 00864 tp->mac_mode |= MAC_MODE_LINK_POLARITY; 00865 tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1); 00866 } 00867 00868 /* ??? Without this setting Netgear GA302T PHY does not 00869 * ??? send/receive packets... 00870 * With this other PHYs cannot bring up the link 00871 */ 00872 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 && 00873 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { 00874 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; 00875 tw32_carefully(MAC_MI_MODE, tp->mi_mode); 00876 } 00877 00878 tw32_carefully(MAC_MODE, tp->mac_mode); 00879 00880 /* Link change polled. */ 00881 tw32_carefully(MAC_EVENT, 0); 00882 00883 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && 00884 current_link_up == 1 && 00885 tp->link_config.active_speed == SPEED_1000 && 00886 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || 00887 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { 00888 udelay(120); 00889 tw32_carefully(MAC_STATUS, 00890 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)); 00891 tg3_write_mem( 00892 NIC_SRAM_FIRMWARE_MBOX, 00893 NIC_SRAM_FIRMWARE_MBOX_MAGIC2); 00894 } 00895 00896 if (current_link_up != tp->carrier_ok) { 00897 tp->carrier_ok = current_link_up; 00898 tg3_link_report(tp); 00899 } 00900 00901 return 0; 00902 }
| static int tg3_fiber_aneg_smachine | ( | struct tg3 * | tp, | |
| struct tg3_fiber_aneginfo * | ap | |||
| ) | [static] |
Definition at line 972 of file tg3.c.
References tg3_fiber_aneginfo::ability_match, tg3_fiber_aneginfo::ability_match_cfg, tg3_fiber_aneginfo::ability_match_count, tg3_fiber_aneginfo::ack_match, ANEG_CFG_ACK, ANEG_CFG_FD, ANEG_CFG_HD, ANEG_CFG_INVAL, ANEG_CFG_NP, ANEG_CFG_PS1, ANEG_CFG_PS2, ANEG_CFG_RF1, ANEG_CFG_RF2, ANEG_DONE, ANEG_FAILED, ANEG_OK, ANEG_STATE_ABILITY_DETECT, ANEG_STATE_ABILITY_DETECT_INIT, ANEG_STATE_ACK_DETECT, ANEG_STATE_ACK_DETECT_INIT, ANEG_STATE_AN_ENABLE, ANEG_STATE_COMPLETE_ACK, ANEG_STATE_COMPLETE_ACK_INIT, ANEG_STATE_DISABLE_LINK_OK, ANEG_STATE_IDLE_DETECT, ANEG_STATE_IDLE_DETECT_INIT, ANEG_STATE_LINK_OK, ANEG_STATE_NEXT_PAGE_WAIT, ANEG_STATE_NEXT_PAGE_WAIT_INIT, ANEG_STATE_RESTART, ANEG_STATE_RESTART_INIT, ANEG_STATE_SETTLE_TIME, ANEG_STATE_UNKNOWN, ANEG_TIMER_ENAB, tg3_fiber_aneginfo::cur_time, tg3_fiber_aneginfo::flags, tg3_fiber_aneginfo::idle_match, tg3_fiber_aneginfo::link_time, MAC_MODE, tg3::mac_mode, MAC_MODE_SEND_CONFIGS, MAC_RX_AUTO_NEG, MAC_STATUS, MAC_STATUS_RCVD_CFG, MAC_TX_AUTO_NEG, MR_AN_COMPLETE, MR_AN_ENABLE, MR_LINK_OK, MR_LP_ADV_ASYM_PAUSE, MR_LP_ADV_FULL_DUPLEX, MR_LP_ADV_HALF_DUPLEX, MR_LP_ADV_NEXT_PAGE, MR_LP_ADV_REMOTE_FAULT1, MR_LP_ADV_REMOTE_FAULT2, MR_LP_ADV_SYM_PAUSE, MR_NP_LOADED, MR_NP_RX, MR_PAGE_RX, MR_RESTART_AN, MR_TOGGLE_RX, MR_TOGGLE_TX, tg3_fiber_aneginfo::rxconfig, tg3_fiber_aneginfo::state, tr32, tw32, tw32_carefully(), and tg3_fiber_aneginfo::txconfig.
Referenced by tg3_setup_fiber_phy().
00974 { 00975 unsigned long delta; 00976 uint32_t rx_cfg_reg; 00977 int ret; 00978 00979 if (ap->state == ANEG_STATE_UNKNOWN) { 00980 ap->rxconfig = 0; 00981 ap->link_time = 0; 00982 ap->cur_time = 0; 00983 ap->ability_match_cfg = 0; 00984 ap->ability_match_count = 0; 00985 ap->ability_match = 0; 00986 ap->idle_match = 0; 00987 ap->ack_match = 0; 00988 } 00989 ap->cur_time++; 00990 00991 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { 00992 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); 00993 00994 if (rx_cfg_reg != ap->ability_match_cfg) { 00995 ap->ability_match_cfg = rx_cfg_reg; 00996 ap->ability_match = 0; 00997 ap->ability_match_count = 0; 00998 } else { 00999 if (++ap->ability_match_count > 1) { 01000 ap->ability_match = 1; 01001 ap->ability_match_cfg = rx_cfg_reg; 01002 } 01003 } 01004 if (rx_cfg_reg & ANEG_CFG_ACK) 01005 ap->ack_match = 1; 01006 else 01007 ap->ack_match = 0; 01008 01009 ap->idle_match = 0; 01010 } else { 01011 ap->idle_match = 1; 01012 ap->ability_match_cfg = 0; 01013 ap->ability_match_count = 0; 01014 ap->ability_match = 0; 01015 ap->ack_match = 0; 01016 01017 rx_cfg_reg = 0; 01018 } 01019 01020 ap->rxconfig = rx_cfg_reg; 01021 ret = ANEG_OK; 01022 01023 switch(ap->state) { 01024 case ANEG_STATE_UNKNOWN: 01025 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) 01026 ap->state = ANEG_STATE_AN_ENABLE; 01027 01028 /* fallthru */ 01029 case ANEG_STATE_AN_ENABLE: 01030 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); 01031 if (ap->flags & MR_AN_ENABLE) { 01032 ap->link_time = 0; 01033 ap->cur_time = 0; 01034 ap->ability_match_cfg = 0; 01035 ap->ability_match_count = 0; 01036 ap->ability_match = 0; 01037 ap->idle_match = 0; 01038 ap->ack_match = 0; 01039 01040 ap->state = ANEG_STATE_RESTART_INIT; 01041 } else { 01042 ap->state = ANEG_STATE_DISABLE_LINK_OK; 01043 } 01044 break; 01045 01046 case ANEG_STATE_RESTART_INIT: 01047 ap->link_time = ap->cur_time; 01048 ap->flags &= ~(MR_NP_LOADED); 01049 ap->txconfig = 0; 01050 tw32(MAC_TX_AUTO_NEG, 0); 01051 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; 01052 tw32_carefully(MAC_MODE, tp->mac_mode); 01053 01054 ret = ANEG_TIMER_ENAB; 01055 ap->state = ANEG_STATE_RESTART; 01056 01057 /* fallthru */ 01058 case ANEG_STATE_RESTART: 01059 delta = ap->cur_time - ap->link_time; 01060 if (delta > ANEG_STATE_SETTLE_TIME) { 01061 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; 01062 } else { 01063 ret = ANEG_TIMER_ENAB; 01064 } 01065 break; 01066 01067 case ANEG_STATE_DISABLE_LINK_OK: 01068 ret = ANEG_DONE; 01069 break; 01070 01071 case ANEG_STATE_ABILITY_DETECT_INIT: 01072 ap->flags &= ~(MR_TOGGLE_TX); 01073 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1); 01074 tw32(MAC_TX_AUTO_NEG, ap->txconfig); 01075 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; 01076 tw32_carefully(MAC_MODE, tp->mac_mode); 01077 01078 ap->state = ANEG_STATE_ABILITY_DETECT; 01079 break; 01080 01081 case ANEG_STATE_ABILITY_DETECT: 01082 if (ap->ability_match != 0 && ap->rxconfig != 0) { 01083 ap->state = ANEG_STATE_ACK_DETECT_INIT; 01084 } 01085 break; 01086 01087 case ANEG_STATE_ACK_DETECT_INIT: 01088 ap->txconfig |= ANEG_CFG_ACK; 01089 tw32(MAC_TX_AUTO_NEG, ap->txconfig); 01090 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; 01091 tw32_carefully(MAC_MODE, tp->mac_mode); 01092 01093 ap->state = ANEG_STATE_ACK_DETECT; 01094 01095 /* fallthru */ 01096 case ANEG_STATE_ACK_DETECT: 01097 if (ap->ack_match != 0) { 01098 if ((ap->rxconfig & ~ANEG_CFG_ACK) == 01099 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { 01100 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; 01101 } else { 01102 ap->state = ANEG_STATE_AN_ENABLE; 01103 } 01104 } else if (ap->ability_match != 0 && 01105 ap->rxconfig == 0) { 01106 ap->state = ANEG_STATE_AN_ENABLE; 01107 } 01108 break; 01109 01110 case ANEG_STATE_COMPLETE_ACK_INIT: 01111 if (ap->rxconfig & ANEG_CFG_INVAL) { 01112 ret = ANEG_FAILED; 01113 break; 01114 } 01115 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | 01116 MR_LP_ADV_HALF_DUPLEX | 01117 MR_LP_ADV_SYM_PAUSE | 01118 MR_LP_ADV_ASYM_PAUSE | 01119 MR_LP_ADV_REMOTE_FAULT1 | 01120 MR_LP_ADV_REMOTE_FAULT2 | 01121 MR_LP_ADV_NEXT_PAGE | 01122 MR_TOGGLE_RX | 01123 MR_NP_RX); 01124 if (ap->rxconfig & ANEG_CFG_FD) 01125 ap->flags |= MR_LP_ADV_FULL_DUPLEX; 01126 if (ap->rxconfig & ANEG_CFG_HD) 01127 ap->flags |= MR_LP_ADV_HALF_DUPLEX; 01128 if (ap->rxconfig & ANEG_CFG_PS1) 01129 ap->flags |= MR_LP_ADV_SYM_PAUSE; 01130 if (ap->rxconfig & ANEG_CFG_PS2) 01131 ap->flags |= MR_LP_ADV_ASYM_PAUSE; 01132 if (ap->rxconfig & ANEG_CFG_RF1) 01133 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; 01134 if (ap->rxconfig & ANEG_CFG_RF2) 01135 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; 01136 if (ap->rxconfig & ANEG_CFG_NP) 01137 ap->flags |= MR_LP_ADV_NEXT_PAGE; 01138 01139 ap->link_time = ap->cur_time; 01140 01141 ap->flags ^= (MR_TOGGLE_TX); 01142 if (ap->rxconfig & 0x0008) 01143 ap->flags |= MR_TOGGLE_RX; 01144 if (ap->rxconfig & ANEG_CFG_NP) 01145 ap->flags |= MR_NP_RX; 01146 ap->flags |= MR_PAGE_RX; 01147 01148 ap->state = ANEG_STATE_COMPLETE_ACK; 01149 ret = ANEG_TIMER_ENAB; 01150 break; 01151 01152 case ANEG_STATE_COMPLETE_ACK: 01153 if (ap->ability_match != 0 && 01154 ap->rxconfig == 0) { 01155 ap->state = ANEG_STATE_AN_ENABLE; 01156 break; 01157 } 01158 delta = ap->cur_time - ap->link_time; 01159 if (delta > ANEG_STATE_SETTLE_TIME) { 01160 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { 01161 ap->state = ANEG_STATE_IDLE_DETECT_INIT; 01162 } else { 01163 if ((ap->txconfig & ANEG_CFG_NP) == 0 && 01164 !(ap->flags & MR_NP_RX)) { 01165 ap->state = ANEG_STATE_IDLE_DETECT_INIT; 01166 } else { 01167 ret = ANEG_FAILED; 01168 } 01169 } 01170 } 01171 break; 01172 01173 case ANEG_STATE_IDLE_DETECT_INIT: 01174 ap->link_time = ap->cur_time; 01175 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; 01176 tw32_carefully(MAC_MODE, tp->mac_mode); 01177 01178 ap->state = ANEG_STATE_IDLE_DETECT; 01179 ret = ANEG_TIMER_ENAB; 01180 break; 01181 01182 case ANEG_STATE_IDLE_DETECT: 01183 if (ap->ability_match != 0 && 01184 ap->rxconfig == 0) { 01185 ap->state = ANEG_STATE_AN_ENABLE; 01186 break; 01187 } 01188 delta = ap->cur_time - ap->link_time; 01189 if (delta > ANEG_STATE_SETTLE_TIME) { 01190 /* XXX another gem from the Broadcom driver :( */ 01191 ap->state = ANEG_STATE_LINK_OK; 01192 } 01193 break; 01194 01195 case ANEG_STATE_LINK_OK: 01196 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); 01197 ret = ANEG_DONE; 01198 break; 01199 01200 case ANEG_STATE_NEXT_PAGE_WAIT_INIT: 01201 /* ??? unimplemented */ 01202 break; 01203 01204 case ANEG_STATE_NEXT_PAGE_WAIT: 01205 /* ??? unimplemented */ 01206 break; 01207 01208 default: 01209 ret = ANEG_FAILED; 01210 break; 01211 }; 01212 01213 return ret; 01214 }
| static int tg3_setup_fiber_phy | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1216 of file tg3.c.
References tg3_link_config::active_duplex, tg3_link_config::active_speed, ADVERTISE_PAUSE_CAP, ANEG_DONE, ANEG_FAILED, ANEG_STATE_UNKNOWN, BMCR_RESET, tg3::carrier_ok, tg3_fiber_aneginfo::cur_time, DUPLEX_FULL, DUPLEX_INVALID, tg3_fiber_aneginfo::flags, tg3::hw_status, tg3::link_config, LPA_PAUSE_ASYM, LPA_PAUSE_CAP, MAC_EVENT, MAC_MODE, tg3::mac_mode, MAC_MODE_HALF_DUPLEX, MAC_MODE_LINK_POLARITY, MAC_MODE_PORT_MODE_GMII, MAC_MODE_PORT_MODE_MASK, MAC_MODE_PORT_MODE_TBI, MAC_MODE_SEND_CONFIGS, MAC_STATUS, MAC_STATUS_CFG_CHANGED, MAC_STATUS_PCS_SYNCED, MAC_STATUS_SYNC_CHANGED, MAC_TX_AUTO_NEG, mdelay(), memset(), MII_BMCR, MR_AN_COMPLETE, MR_AN_ENABLE, MR_LINK_OK, MR_LP_ADV_ASYM_PAUSE, MR_LP_ADV_FULL_DUPLEX, MR_LP_ADV_SYM_PAUSE, SD_STATUS_LINK_CHG, SD_STATUS_UPDATED, SPEED_1000, SPEED_INVALID, tg3_fiber_aneginfo::state, tg3_hw_status::status, tg3_fiber_aneg_smachine(), TG3_FLAG_GOT_SERDES_FLOWCTL, TG3_FLAG_INIT_COMPLETE, TG3_FLAG_RX_PAUSE, TG3_FLAG_TX_PAUSE, tg3::tg3_flags, tg3_link_report(), tg3_setup_flow_control(), tg3_writephy(), tr32, tw32, tw32_carefully(), and udelay().
Referenced by tg3_setup_phy().
01217 { 01218 uint32_t orig_pause_cfg; 01219 uint16_t orig_active_speed; 01220 uint8_t orig_active_duplex; 01221 int current_link_up; 01222 int i; 01223 01224 orig_pause_cfg = 01225 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE | 01226 TG3_FLAG_TX_PAUSE)); 01227 orig_active_speed = tp->link_config.active_speed; 01228 orig_active_duplex = tp->link_config.active_duplex; 01229 01230 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); 01231 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; 01232 tw32_carefully(MAC_MODE, tp->mac_mode); 01233 01234 /* Reset when initting first time or we have a link. */ 01235 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) || 01236 (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) { 01237 /* Set PLL lock range. */ 01238 tg3_writephy(tp, 0x16, 0x8007); 01239 01240 /* SW reset */ 01241 tg3_writephy(tp, MII_BMCR, BMCR_RESET); 01242 01243 /* Wait for reset to complete. */ 01244 mdelay(5); 01245 01246 /* Config mode; select PMA/Ch 1 regs. */ 01247 tg3_writephy(tp, 0x10, 0x8411); 01248 01249 /* Enable auto-lock and comdet, select txclk for tx. */ 01250 tg3_writephy(tp, 0x11, 0x0a10); 01251 01252 tg3_writephy(tp, 0x18, 0x00a0); 01253 tg3_writephy(tp, 0x16, 0x41ff); 01254 01255 /* Assert and deassert POR. */ 01256 tg3_writephy(tp, 0x13, 0x0400); 01257 udelay(40); 01258 tg3_writephy(tp, 0x13, 0x0000); 01259 01260 tg3_writephy(tp, 0x11, 0x0a50); 01261 udelay(40); 01262 tg3_writephy(tp, 0x11, 0x0a10); 01263 01264 /* Wait for signal to stabilize */ 01265 mdelay(150); 01266 01267 /* Deselect the channel register so we can read the PHYID 01268 * later. 01269 */ 01270 tg3_writephy(tp, 0x10, 0x8011); 01271 } 01272 01273 /* Disable link change interrupt. */ 01274 tw32_carefully(MAC_EVENT, 0); 01275 01276 current_link_up = 0; 01277 if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) { 01278 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) { 01279 struct tg3_fiber_aneginfo aninfo; 01280 int status = ANEG_FAILED; 01281 unsigned int tick; 01282 uint32_t tmp; 01283 01284 memset(&aninfo, 0, sizeof(aninfo)); 01285 aninfo.flags |= (MR_AN_ENABLE); 01286 01287 tw32(MAC_TX_AUTO_NEG, 0); 01288 01289 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; 01290 tw32_carefully(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); 01291 01292 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); 01293 01294 aninfo.state = ANEG_STATE_UNKNOWN; 01295 aninfo.cur_time = 0; 01296 tick = 0; 01297 while (++tick < 195000) { 01298 status = tg3_fiber_aneg_smachine(tp, &aninfo); 01299 if (status == ANEG_DONE || 01300 status == ANEG_FAILED) 01301 break; 01302 01303 udelay(1); 01304 } 01305 01306 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; 01307 tw32_carefully(MAC_MODE, tp->mac_mode); 01308 01309 if (status == ANEG_DONE && 01310 (aninfo.flags & 01311 (MR_AN_COMPLETE | MR_LINK_OK | 01312 MR_LP_ADV_FULL_DUPLEX))) { 01313 uint32_t local_adv, remote_adv; 01314 01315 local_adv = ADVERTISE_PAUSE_CAP; 01316 remote_adv = 0; 01317 if (aninfo.flags & MR_LP_ADV_SYM_PAUSE) 01318 remote_adv |= LPA_PAUSE_CAP; 01319 if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE) 01320 remote_adv |= LPA_PAUSE_ASYM; 01321 01322 tg3_setup_flow_control(tp, local_adv, remote_adv); 01323 01324 tp->tg3_flags |= 01325 TG3_FLAG_GOT_SERDES_FLOWCTL; 01326 current_link_up = 1; 01327 } 01328 for (i = 0; i < 60; i++) { 01329 udelay(20); 01330 tw32_carefully(MAC_STATUS, 01331 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)); 01332 if ((tr32(MAC_STATUS) & 01333 (MAC_STATUS_SYNC_CHANGED | 01334 MAC_STATUS_CFG_CHANGED)) == 0) 01335 break; 01336 } 01337 if (current_link_up == 0 && 01338 (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) { 01339 current_link_up = 1; 01340 } 01341 } else { 01342 /* Forcing 1000FD link up. */ 01343 current_link_up = 1; 01344 } 01345 } 01346 01347 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; 01348 tw32_carefully(MAC_MODE, tp->mac_mode); 01349 01350 tp->hw_status->status = 01351 (SD_STATUS_UPDATED | 01352 (tp->hw_status->status & ~SD_STATUS_LINK_CHG)); 01353 01354 for (i = 0; i < 100; i++) { 01355 udelay(20); 01356 tw32_carefully(MAC_STATUS, 01357 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)); 01358 if ((tr32(MAC_STATUS) & 01359 (MAC_STATUS_SYNC_CHANGED | 01360 MAC_STATUS_CFG_CHANGED)) == 0) 01361 break; 01362 } 01363 01364 if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) 01365 current_link_up = 0; 01366 01367 if (current_link_up == 1) { 01368 tp->link_config.active_speed = SPEED_1000; 01369 tp->link_config.active_duplex = DUPLEX_FULL; 01370 } else { 01371 tp->link_config.active_speed = SPEED_INVALID; 01372 tp->link_config.active_duplex = DUPLEX_INVALID; 01373 } 01374 01375 if (current_link_up != tp->carrier_ok) { 01376 tp->carrier_ok = current_link_up; 01377 tg3_link_report(tp); 01378 } else { 01379 uint32_t now_pause_cfg = 01380 tp->tg3_flags & (TG3_FLAG_RX_PAUSE | 01381 TG3_FLAG_TX_PAUSE); 01382 if (orig_pause_cfg != now_pause_cfg || 01383 orig_active_speed != tp->link_config.active_speed || 01384 orig_active_duplex != tp->link_config.active_duplex) 01385 tg3_link_report(tp); 01386 } 01387 01388 if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) { 01389 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY); 01390 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) { 01391 tw32_carefully(MAC_MODE, tp->mac_mode); 01392 } 01393 } 01394 01395 return 0; 01396 }
| static int tg3_setup_phy | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1401 of file tg3.c.
References tg3_link_config::active_duplex, tg3_link_config::active_speed, DUPLEX_HALF, tg3::link_config, MAC_TX_LENGTHS, tg3::phy_id, PHY_ID_SERDES, SPEED_1000, tg3_setup_copper_phy(), tg3_setup_fiber_phy(), tw32, TX_LENGTHS_IPG_CRS_SHIFT, TX_LENGTHS_IPG_SHIFT, and TX_LENGTHS_SLOT_TIME_SHIFT.
Referenced by tg3_poll_link(), and tg3_setup_hw().
01402 { 01403 int err; 01404 01405 if (tp->phy_id == PHY_ID_SERDES) { 01406 err = tg3_setup_fiber_phy(tp); 01407 } else { 01408 err = tg3_setup_copper_phy(tp); 01409 } 01410 01411 if (tp->link_config.active_speed == SPEED_1000 && 01412 tp->link_config.active_duplex == DUPLEX_HALF) 01413 tw32(MAC_TX_LENGTHS, 01414 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | 01415 (6 << TX_LENGTHS_IPG_SHIFT) | 01416 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); 01417 else 01418 tw32(MAC_TX_LENGTHS, 01419 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | 01420 (6 << TX_LENGTHS_IPG_SHIFT) | 01421 (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); 01422 01423 return err; 01424 }
Definition at line 1432 of file tg3.c.
References ASIC_REV_5705, ASIC_REV_5787, BUFMGR_MODE, DMAC_MODE, ENODEV, GET_ASIC_REV, MAX_WAIT_CNT, MBFREE_MODE, MEMARB_MODE, tg3::pci_chip_rev_id, printf(), RCVLSC_MODE, tr32, tw32, and udelay().
Referenced by tg3_abort_hw().
01433 { 01434 unsigned int i; 01435 uint32_t val; 01436 01437 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || 01438 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) { 01439 switch(ofs) { 01440 case RCVLSC_MODE: 01441 case DMAC_MODE: 01442 case MBFREE_MODE: 01443 case BUFMGR_MODE: 01444 case MEMARB_MODE: 01445 /* We can't enable/disable these bits of the 01446 * 5705 or 5787, just say success. 01447 */ 01448 return 0; 01449 default: 01450 break; 01451 } 01452 } 01453 val = tr32(ofs); 01454 val &= ~enable_bit; 01455 tw32(ofs, val); 01456 tr32(ofs); 01457 01458 for (i = 0; i < MAX_WAIT_CNT; i++) { 01459 udelay(100); 01460 val = tr32(ofs); 01461 if ((val & enable_bit) == 0) 01462 break; 01463 } 01464 01465 if (i == MAX_WAIT_CNT) { 01466 printf( "tg3_stop_block timed out, ofs=%#lx enable_bit=%3x\n", 01467 ofs, enable_bit ); 01468 return -ENODEV; 01469 } 01470 01471 return 0; 01472 }
| static int tg3_abort_hw | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1474 of file tg3.c.
References BUFMGR_MODE, BUFMGR_MODE_ENABLE, ENODEV, FTQ_RESET, FTQ_RESET_DMA_HIGH_PRI_READ, FTQ_RESET_DMA_HIGH_PRI_WRITE, FTQ_RESET_DMA_READ_QUEUE, FTQ_RESET_DMA_WRITE, FTQ_RESET_HOST_COALESCING, FTQ_RESET_MAC_TX, FTQ_RESET_RX_BD_COMPLETE, FTQ_RESET_RX_DATA_COMPLETION, FTQ_RESET_RX_LIST_PLCMT, FTQ_RESET_SEND_BD_COMPLETION, FTQ_RESET_SEND_DATA_COMPLETION, HOSTCC_MODE, HOSTCC_MODE_ENABLE, tg3::hw_status, MAC_MODE, tg3::mac_mode, MAC_MODE_TDE_ENABLE, MAC_RX_MODE, MAC_TX_MODE, MAX_WAIT_CNT, MBFREE_MODE, MBFREE_MODE_ENABLE, MEMARB_MODE, MEMARB_MODE_ENABLE, memset(), printf(), RCVBDI_MODE, RCVBDI_MODE_ENABLE, RCVCC_MODE, RCVCC_MODE_ENABLE, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, RCVDCC_MODE, RCVDCC_MODE_ENABLE, RCVLPC_MODE, RCVLPC_MODE_ENABLE, RCVLSC_MODE, RCVLSC_MODE_ENABLE, RDMAC_MODE, RDMAC_MODE_ENABLE, tg3::rx_mode, RX_MODE_ENABLE, SNDBDC_MODE, SNDBDC_MODE_ENABLE, SNDBDI_MODE, SNDBDI_MODE_ENABLE, SNDBDS_MODE, SNDBDS_MODE_ENABLE, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, tg3_disable_ints(), TG3_HW_STATUS_SIZE, tg3_stop_block(), tr32, tw32, tw32_carefully(), tg3::tx_mode, TX_MODE_ENABLE, udelay(), WDMAC_MODE, and WDMAC_MODE_ENABLE.
Referenced by tg3_halt().
01475 { 01476 int i, err; 01477 uint32_t val; 01478 01479 tg3_disable_ints(tp); 01480 01481 tp->rx_mode &= ~RX_MODE_ENABLE; 01482 tw32_carefully(MAC_RX_MODE, tp->rx_mode); 01483 01484 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE); 01485 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE); 01486 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE); 01487 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE); 01488 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE); 01489 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE); 01490 01491 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE); 01492 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE); 01493 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); 01494 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE); 01495 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); 01496 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE); 01497 if (err) 01498 goto out; 01499 01500 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; 01501 tw32_carefully(MAC_MODE, tp->mac_mode); 01502 01503 tp->tx_mode &= ~TX_MODE_ENABLE; 01504 tw32_carefully(MAC_TX_MODE, tp->tx_mode); 01505 01506 for (i = 0; i < MAX_WAIT_CNT; i++) { 01507 udelay(100); 01508 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) 01509 break; 01510 } 01511 if (i >= MAX_WAIT_CNT) { 01512 printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n", 01513 (unsigned int) tr32(MAC_TX_MODE)); 01514 return -ENODEV; 01515 } 01516 01517 err = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE); 01518 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE); 01519 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE); 01520 01521 val = tr32(FTQ_RESET); 01522 val |= FTQ_RESET_DMA_READ_QUEUE | FTQ_RESET_DMA_HIGH_PRI_READ | 01523 FTQ_RESET_SEND_BD_COMPLETION | FTQ_RESET_DMA_WRITE | 01524 FTQ_RESET_DMA_HIGH_PRI_WRITE | FTQ_RESET_SEND_DATA_COMPLETION | 01525 FTQ_RESET_HOST_COALESCING | FTQ_RESET_MAC_TX | 01526 FTQ_RESET_RX_BD_COMPLETE | FTQ_RESET_RX_LIST_PLCMT | 01527 FTQ_RESET_RX_DATA_COMPLETION; 01528 tw32(FTQ_RESET, val); 01529 01530 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE); 01531 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE); 01532 if (err) 01533 goto out; 01534 01535 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); 01536 01537 out: 01538 return err; 01539 }
| static void tg3_chip_reset | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1541 of file tg3.c.
References ASIC_REV_5705, ASIC_REV_5750, ASIC_REV_5787, CHIPREV_ID_5704_A0, CHIPREV_ID_5750_A0, CLOCK_CTRL_CLKRUN_OENABLE, CLOCK_CTRL_FORCE_CLKRUN, GET_ASIC_REV, GRC_MISC_CFG, GRC_MISC_CFG_CORECLK_RESET, GRC_MISC_CFG_KEEP_GPHY_POWER, MEMARB_MODE, MEMARB_MODE_ENABLE, tg3::misc_host_ctrl, tg3::nic_sram_data_cfg, NIC_SRAM_DATA_CFG_MINI_PCI, NVRAM_SWARB, tg3::pci_cfg_state, tg3::pci_chip_rev_id, tg3::pci_clock_ctrl, PCI_COMMAND, pci_read_config_dword(), pci_restore_state(), pci_write_config_dword(), PCISTATE_RETRY_SAME_DMA, PCISTATE_ROM_ENABLE, PCISTATE_ROM_RETRY_ENABLE, PCIX_CAPS_RELAXED_ORDERING, tg3::pdev, SWARB_GNT1, SWARB_REQ_SET1, TG3_FLAG_NVRAM, TG3_FLAG_PCIX_MODE, tg3::tg3_flags, tg3::tg3_flags2, TG3_FLG2_PCI_EXPRESS, TG3_FLG2_SUN_5704, TG3PCI_CLOCK_CTRL, TG3PCI_MISC_HOST_CTRL, TG3PCI_PCISTATE, TG3PCI_X_CAPS, tr32, tw32, and udelay().
Referenced by tg3_halt(), and tg3_setup_hw().
01542 { 01543 uint32_t val; 01544 01545 if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) { 01546 /* Force NVRAM to settle. 01547 * This deals with a chip bug which can result in EEPROM 01548 * corruption. 01549 */ 01550 if (tp->tg3_flags & TG3_FLAG_NVRAM) { 01551 int i; 01552 01553 tw32(NVRAM_SWARB, SWARB_REQ_SET1); 01554 for (i = 0; i < 100000; i++) { 01555 if (tr32(NVRAM_SWARB) & SWARB_GNT1) 01556 break; 01557 udelay(10); 01558 } 01559 } 01560 } 01561 /* In Etherboot we don't need to worry about the 5701 01562 * REG_WRITE_BUG because we do all register writes indirectly. 01563 */ 01564 01565 // Alf: here patched 01566 /* do the reset */ 01567 val = GRC_MISC_CFG_CORECLK_RESET; 01568 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 01569 if (tr32(0x7e2c) == 0x60) { 01570 tw32(0x7e2c, 0x20); 01571 } 01572 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { 01573 tw32(GRC_MISC_CFG, (1 << 29)); 01574 val |= (1 << 29); 01575 } 01576 } 01577 01578 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) 01579 || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) 01580 || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)) { 01581 val |= GRC_MISC_CFG_KEEP_GPHY_POWER; 01582 } 01583 01584 // Alf : Please VALIDATE THIS. 01585 // It is necessary in my case (5751) to prevent a reboot, but 01586 // I have no idea about a side effect on any other version. 01587 // It appears to be what's done in tigon3.c from Broadcom 01588 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { 01589 tw32(GRC_MISC_CFG, 0x20000000) ; 01590 val |= 0x20000000 ; 01591 } 01592 01593 tw32(GRC_MISC_CFG, val); 01594 01595 /* Flush PCI posted writes. The normal MMIO registers 01596 * are inaccessible at this time so this is the only 01597 * way to make this reliably. I tried to use indirect 01598 * register read/write but this upset some 5701 variants. 01599 */ 01600 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); 01601 01602 udelay(120); 01603 01604 /* Re-enable indirect register accesses. */ 01605 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, 01606 tp->misc_host_ctrl); 01607 01608 /* Set MAX PCI retry to zero. */ 01609 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); 01610 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && 01611 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) 01612 val |= PCISTATE_RETRY_SAME_DMA; 01613 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); 01614 01615 pci_restore_state(tp->pdev, tp->pci_cfg_state); 01616 01617 /* Make sure PCI-X relaxed ordering bit is clear. */ 01618 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val); 01619 val &= ~PCIX_CAPS_RELAXED_ORDERING; 01620 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val); 01621 01622 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); 01623 01624 if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) && 01625 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) { 01626 tp->pci_clock_ctrl |= 01627 (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE); 01628 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); 01629 } 01630 01631 tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); 01632 }
| static void tg3_stop_fw | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1634 of file tg3.c.
References FWCMD_NICDRV_PAUSE_FW, GRC_RX_CPU_EVENT, NIC_SRAM_FW_CMD_MBOX, TG3_FLAG_ENABLE_ASF, tg3::tg3_flags, tg3_write_mem(), tr32, tw32, and udelay().
Referenced by tg3_halt(), and tg3_setup_hw().
01635 { 01636 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { 01637 uint32_t val; 01638 int i; 01639 01640 tg3_write_mem(NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); 01641 val = tr32(GRC_RX_CPU_EVENT); 01642 val |= (1 << 14); 01643 tw32(GRC_RX_CPU_EVENT, val); 01644 01645 /* Wait for RX cpu to ACK the event. */ 01646 for (i = 0; i < 100; i++) { 01647 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14))) 01648 break; 01649 udelay(1); 01650 } 01651 } 01652 }
Definition at line 1654 of file tg3.c.
References ASIC_REV_5787, CHIPREV_ID_5750_A0, DRV_STATE_SUSPEND, ENODEV, GET_ASIC_REV, NIC_SRAM_FIRMWARE_MBOX, NIC_SRAM_FIRMWARE_MBOX_MAGIC1, NIC_SRAM_FW_DRV_STATE_MBOX, tg3::pci_chip_rev_id, printf(), TG3_FLAG_ENABLE_ASF, tg3::tg3_flags, tg3::tg3_flags2, TG3_FLG2_PCI_EXPRESS, TG3_FLG2_SUN_5704, tg3_read_mem(), tg3_write_mem(), and udelay().
Referenced by tg3_halt(), and tg3_setup_hw().
01655 { 01656 uint32_t val; 01657 int i; 01658 01659 tg3_write_mem(NIC_SRAM_FIRMWARE_MBOX, 01660 NIC_SRAM_FIRMWARE_MBOX_MAGIC1); 01661 /* Wait for firmware initialization to complete. */ 01662 for (i = 0; i < 100000; i++) { 01663 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val); 01664 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) 01665 break; 01666 udelay(10); 01667 } 01668 if (i >= 100000 && 01669 !(tp->tg3_flags2 & TG3_FLG2_SUN_5704) && 01670 !(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)) { 01671 printf ( "Firmware will not restart magic=%#x\n", 01672 val ); 01673 return -ENODEV; 01674 } 01675 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { 01676 state = DRV_STATE_SUSPEND; 01677 } 01678 01679 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && 01680 (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) { 01681 // Enable PCIE bug fix 01682 tg3_read_mem(0x7c00, &val); 01683 tg3_write_mem(0x7c00, val | 0x02000000); 01684 } 01685 tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state); 01686 return 0; 01687 }
| static int tg3_halt | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1689 of file tg3.c.
References DRV_STATE_UNLOAD, tg3_abort_hw(), tg3_chip_reset(), tg3_restart_fw(), and tg3_stop_fw().
Referenced by tg3_disable(), and tg3_transmit().
01690 { 01691 tg3_stop_fw(tp); 01692 tg3_abort_hw(tp); 01693 tg3_chip_reset(tp); 01694 return tg3_restart_fw(tp, DRV_STATE_UNLOAD); 01695 }
| static void __tg3_set_mac_addr | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1697 of file tg3.c.
References ASIC_REV_5700, ASIC_REV_5701, ASIC_REV_5705, GET_ASIC_REV, MAC_ADDR_0_HIGH, MAC_ADDR_0_LOW, MAC_EXTADDR_0_HIGH, MAC_EXTADDR_0_LOW, MAC_TX_BACKOFF_SEED, tg3::nic, nic::node_addr, tg3::pci_chip_rev_id, tw32, and TX_BACKOFF_SEED_MASK.
Referenced by tg3_setup_hw().
01698 { 01699 uint32_t addr_high, addr_low; 01700 int i; 01701 01702 addr_high = ((tp->nic->node_addr[0] << 8) | 01703 tp->nic->node_addr[1]); 01704 addr_low = ((tp->nic->node_addr[2] << 24) | 01705 (tp->nic->node_addr[3] << 16) | 01706 (tp->nic->node_addr[4] << 8) | 01707 (tp->nic->node_addr[5] << 0)); 01708 for (i = 0; i < 4; i++) { 01709 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); 01710 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); 01711 } 01712 01713 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && 01714 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && 01715 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) { 01716 for(i = 0; i < 12; i++) { 01717 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); 01718 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); 01719 } 01720 } 01721 addr_high = (tp->nic->node_addr[0] + 01722 tp->nic->node_addr[1] + 01723 tp->nic->node_addr[2] + 01724 tp->nic->node_addr[3] + 01725 tp->nic->node_addr[4] + 01726 tp->nic->node_addr[5]) & 01727 TX_BACKOFF_SEED_MASK; 01728 tw32(MAC_TX_BACKOFF_SEED, addr_high); 01729 }
| static void tg3_set_bdinfo | ( | struct tg3 * | tp, | |
| uint32_t | bdinfo_addr, | |||
| dma_addr_t | mapping, | |||
| uint32_t | maxlen_flags, | |||
| uint32_t | nic_addr | |||
| ) | [static] |
Definition at line 1731 of file tg3.c.
References ASIC_REV_5705, GET_ASIC_REV, tg3::pci_chip_rev_id, TG3_64BIT_REG_HIGH, TG3_64BIT_REG_LOW, TG3_BDINFO_HOST_ADDR, TG3_BDINFO_MAXLEN_FLAGS, TG3_BDINFO_NIC_ADDR, and tg3_write_mem().
Referenced by tg3_setup_hw().
01734 { 01735 tg3_write_mem((bdinfo_addr + 01736 TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), 01737 ((uint64_t) mapping >> 32)); 01738 tg3_write_mem((bdinfo_addr + 01739 TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), 01740 ((uint64_t) mapping & 0xffffffff)); 01741 tg3_write_mem((bdinfo_addr + 01742 TG3_BDINFO_MAXLEN_FLAGS), 01743 maxlen_flags); 01744 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { 01745 tg3_write_mem((bdinfo_addr + TG3_BDINFO_NIC_ADDR), nic_addr); 01746 } 01747 }
| static void tg3_init_rings | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1750 of file tg3.c.
References tg3_rx_buffer_desc::addr_hi, tg3_rx_buffer_desc::addr_lo, tg3::hw_stats, tg3::hw_status, tg3_rx_buffer_desc::idx_len, tg3::mac_mode, memset(), tg3_rx_buffer_desc::opaque, RX_PKT_BUF_SZ, tg3::rx_rcb, tg3::rx_std, rxd, RXD_FLAG_END, RXD_FLAGS_SHIFT, RXD_LEN_SHIFT, RXD_OPAQUE_INDEX_SHIFT, RXD_OPAQUE_RING_STD, TG3_DEF_RX_RING_PENDING, TG3_RX_RING_SIZE, tg3::tx_ring, tg3_rx_buffer_desc::type_flags, and virt_to_bus().
Referenced by tg3_setup_hw().
01751 { 01752 unsigned i; 01753 01754 /* Zero out the tg3 variables */ 01755 memset(&tg3_bss, 0, sizeof(tg3_bss)); 01756 tp->rx_std = &tg3_bss.rx_std[0]; 01757 tp->rx_rcb = &tg3_bss.rx_rcb[0]; 01758 tp->tx_ring = &tg3_bss.tx_ring[0]; 01759 tp->hw_status = &tg3_bss.hw_status; 01760 tp->hw_stats = &tg3_bss.hw_stats; 01761 tp->mac_mode = 0; 01762 01763 01764 /* Initialize tx/rx rings for packet processing. 01765 * 01766 * The chip has been shut down and the driver detached from 01767 * the networking, so no interrupts or new tx packets will 01768 * end up in the driver. 01769 */ 01770 01771 /* Initialize invariants of the rings, we only set this 01772 * stuff once. This works because the card does not 01773 * write into the rx buffer posting rings. 01774 */ 01775 for (i = 0; i < TG3_RX_RING_SIZE; i++) { 01776 struct tg3_rx_buffer_desc *rxd; 01777 01778 rxd = &tp->rx_std[i]; 01779 rxd->idx_len = (RX_PKT_BUF_SZ - 2 - 64) << RXD_LEN_SHIFT; 01780 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); 01781 rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT)); 01782 01783 /* Note where the receive buffer for the ring is placed */ 01784 rxd->addr_hi = 0; 01785 rxd->addr_lo = virt_to_bus( 01786 &tg3_bss.rx_bufs[i%TG3_DEF_RX_RING_PENDING][2]); 01787 } 01788 }
| static int tg3_setup_hw | ( | struct tg3 * | tp | ) | [static] |
Definition at line 1802 of file tg3.c.
References __tg3_set_mac_addr(), ASIC_REV_5700, ASIC_REV_5703, ASIC_REV_5704, ASIC_REV_5705, ASIC_REV_5750, ASIC_REV_5787, BDINFO_FLAGS_DISABLED, BDINFO_FLAGS_MAXLEN_SHIFT, tg3::bufmgr_config, BUFMGR_DMA_DESC_POOL_ADDR, BUFMGR_DMA_DESC_POOL_SIZE, BUFMGR_DMA_HIGH_WATER, BUFMGR_DMA_LOW_WATER, BUFMGR_MB_HIGH_WATER, BUFMGR_MB_MACRX_LOW_WATER, BUFMGR_MB_POOL_ADDR, BUFMGR_MB_POOL_SIZE, BUFMGR_MB_RDMA_LOW_WATER, BUFMGR_MODE, BUFMGR_MODE_ATTN_ENABLE, BUFMGR_MODE_ENABLE, CHIPREV_ID_5701_A0, CHIPREV_ID_5703_A1, CHIPREV_ID_5704_A0, CHIPREV_ID_5705_A0, CHIPREV_ID_5721, CLOCK_CTRL_DELAY_PCI_GRANT, DEFAULT_STAT_COAL_TICKS, tg3_bufmgr_config::dma_high_water, tg3_bufmgr_config::dma_low_water, tg3::dma_rwctrl, DMAC_MODE, DMAC_MODE_ENABLE, DRV_STATE_START, EINVAL, ENODEV, ETH_HLEN, ETH_MAX_MTU, FTQ_RESET, GET_ASIC_REV, GRC_LCLCTRL_AUTO_SEEPROM, GRC_LCLCTRL_GPIO_OE1, GRC_LCLCTRL_GPIO_OUTPUT1, GRC_LCLCTRL_INT_ON_ATTN, GRC_LOCAL_CTRL, tg3::grc_local_ctrl, GRC_MISC_CFG, GRC_MISC_CFG_PRESCALAR_SHIFT, tg3::grc_mode, GRC_MODE, GRC_MODE_4X_NIC_SEND_RINGS, GRC_MODE_HOST_SENDBDS, GRC_MODE_HOST_STACKUP, GRC_MODE_IRQ_ON_MAC_ATTN, GRC_MODE_NO_RX_PHDR_CSUM, GRC_MODE_NO_TX_PHDR_CSUM, HOSTCC_MODE, HOSTCC_MODE_ENABLE, HOSTCC_RXCOAL_MAXF_INT, HOSTCC_RXCOAL_TICK_INT, HOSTCC_RXCOL_TICKS, HOSTCC_RXMAX_FRAMES, HOSTCC_STAT_COAL_TICKS, HOSTCC_STATS_BLK_HOST_ADDR, HOSTCC_STATS_BLK_NIC_ADDR, HOSTCC_STATUS_BLK_HOST_ADDR, HOSTCC_STATUS_BLK_NIC_ADDR, HOSTCC_TXCOAL_MAXF_INT, HOSTCC_TXCOAL_TICK_INT, HOSTCC_TXCOL_TICKS, HOSTCC_TXMAX_FRAMES, tg3::hw_stats, tg3::hw_status, LOW_RXMAX_FRAMES, LOW_TXCOL_TICKS, MAC_HASH_REG_0, MAC_HASH_REG_1, MAC_HASH_REG_2, MAC_HASH_REG_3, MAC_LED_CTRL, MAC_LOW_WMARK_MAX_RX_FRAME, MAC_MI_MODE, MAC_MI_MODE_BASE, MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB, MAC_MODE, tg3::mac_mode, MAC_MODE_FHDE_ENABLE, MAC_MODE_PORT_MODE_TBI, MAC_MODE_RDE_ENABLE, MAC_MODE_RXSTAT_CLEAR, MAC_MODE_RXSTAT_ENABLE, MAC_MODE_TDE_ENABLE, MAC_MODE_TXSTAT_CLEAR, MAC_MODE_TXSTAT_ENABLE, MAC_RCV_RULE_0, MAC_RCV_RULE_1, MAC_RCV_RULE_10, MAC_RCV_RULE_11, MAC_RCV_RULE_12, MAC_RCV_RULE_13, MAC_RCV_RULE_14, MAC_RCV_RULE_15, MAC_RCV_RULE_4, MAC_RCV_RULE_5, MAC_RCV_RULE_6, MAC_RCV_RULE_7, MAC_RCV_RULE_8, MAC_RCV_RULE_9, MAC_RCV_RULE_CFG, MAC_RCV_VALUE_0, MAC_RCV_VALUE_1, MAC_RCV_VALUE_10, MAC_RCV_VALUE_11, MAC_RCV_VALUE_12, MAC_RCV_VALUE_13, MAC_RCV_VALUE_14, MAC_RCV_VALUE_15, MAC_RCV_VALUE_4, MAC_RCV_VALUE_5, MAC_RCV_VALUE_6, MAC_RCV_VALUE_7, MAC_RCV_VALUE_8, MAC_RCV_VALUE_9, MAC_RX_MODE, MAC_RX_MTU_SIZE, MAC_SERDES_CFG, MAC_TX_LENGTHS, MAC_TX_MODE, MAILBOX_INTERRUPT_0, MAILBOX_RCV_JUMBO_PROD_IDX, MAILBOX_RCV_STD_PROD_IDX, MAILBOX_RCVRET_CON_IDX_0, MAILBOX_SNDHOST_PROD_IDX_0, MAILBOX_SNDNIC_PROD_IDX_0, MBFREE_MODE, MBFREE_MODE_ENABLE, tg3_bufmgr_config::mbuf_high_water, tg3_bufmgr_config::mbuf_high_water_jumbo, tg3_bufmgr_config::mbuf_mac_rx_low_water, tg3_bufmgr_config::mbuf_mac_rx_low_water_jumbo, tg3_bufmgr_config::mbuf_read_dma_low_water, tg3_bufmgr_config::mbuf_read_dma_low_water_jumbo, tg3::mi_mode, NIC_SRAM_DMA_DESC_POOL_BASE, NIC_SRAM_DMA_DESC_POOL_SIZE, NIC_SRAM_MBUF_POOL_BASE, NIC_SRAM_MBUF_POOL_SIZE64, NIC_SRAM_MBUF_POOL_SIZE96, NIC_SRAM_RCV_RET_RCB, NIC_SRAM_RX_BUFFER_DESC, NIC_SRAM_SEND_RCB, NIC_SRAM_STATS_BLK, NIC_SRAM_STATUS_BLK, NIC_SRAM_TX_BUFFER_DESC, tg3::pci_chip_rev_id, tg3::pci_clock_ctrl, PCISTATE_BUS_SPEED_HIGH, PCISTATE_RETRY_SAME_DMA, PCIX_CAPS_BURST_MASK, PCIX_CAPS_BURST_SHIFT, PCIX_CAPS_MAX_BURST_CPIOB, PCIX_CAPS_SPLIT_MASK, PCIX_CAPS_SPLIT_SHIFT, tg3::phy_id, PHY_ID_SERDES, printf(), RCV_RULE_CFG_DEFAULT_CLASS, RCV_RULE_DISABLE_MASK, RCVBDI_JUMBO_THRESH, RCVBDI_MODE, RCVBDI_MODE_ENABLE, RCVBDI_MODE_RCB_ATTN_ENAB, RCVBDI_STD_THRESH, RCVCC_MODE, RCVCC_MODE_ATTN_ENABLE, RCVCC_MODE_ENABLE, RCVDBDI_JUMBO_BD, RCVDBDI_MINI_BD, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, RCVDBDI_MODE_INV_RING_SZ, RCVDBDI_STD_BD, RCVDCC_MODE, RCVDCC_MODE_ATTN_ENABLE, RCVDCC_MODE_ENABLE, RCVLPC_CONFIG, RCVLPC_MODE, RCVLPC_MODE_ENABLE, RCVLPC_STATS_ENABLE, RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE, RCVLSC_MODE, RCVLSC_MODE_ATTN_ENABLE, RCVLSC_MODE_ENABLE, RDMAC_MODE, RDMAC_MODE_ADDROFLOW_ENAB, RDMAC_MODE_ENABLE, RDMAC_MODE_FIFO_LONG_BURST, RDMAC_MODE_FIFOOFLOW_ENAB, RDMAC_MODE_FIFOOREAD_ENAB, RDMAC_MODE_FIFOURUN_ENAB, RDMAC_MODE_LNGREAD_ENAB, RDMAC_MODE_MSTABORT_ENAB, RDMAC_MODE_PARITYERR_ENAB, RDMAC_MODE_SPLIT_ENABLE, RDMAC_MODE_TGTABORT_ENAB, tg3::rx_mode, RX_MODE_ENABLE, RX_MODE_KEEP_VLAN_TAG, RX_MODE_RESET, tg3::rx_rcb, tg3::rx_rcb_ptr, tg3::rx_std, RX_STD_MAX_SIZE, RX_STD_MAX_SIZE_5705, tg3::rx_std_ptr, SNDBDC_MODE, SNDBDC_MODE_ATTN_ENABLE, SNDBDC_MODE_ENABLE, SNDBDI_MODE, SNDBDI_MODE_ATTN_ENABLE, SNDBDI_MODE_ENABLE, SNDBDS_MODE, SNDBDS_MODE_ATTN_ENABLE, SNDBDS_MODE_ENABLE, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, SNDDATAI_SCTRL_ENABLE, SNDDATAI_SCTRL_FASTUPD, SNDDATAI_STATSCTRL, SNDDATAI_STATSENAB, tg3::split_mode_max_reqs, TG3_64BIT_REG_HIGH, TG3_64BIT_REG_LOW, TG3_BDINFO_HOST_ADDR, TG3_BDINFO_MAXLEN_FLAGS, TG3_BDINFO_NIC_ADDR, TG3_BDINFO_SIZE, tg3_chip_reset(), TG3_DEF_RX_RING_PENDING, tg3_disable_ints(), TG3_FLAG_ENABLE_ASF, TG3_FLAG_JUMBO_ENABLE, TG3_FLAG_PCIX_MODE, TG3_FLAG_SPLIT_MODE, tg3::tg3_flags, tg3::tg3_flags2, TG3_FLG2_IS_5788, TG3_FLG2_PCI_EXPRESS, TG3_HW_STATUS_SIZE, tg3_init_rings(), tg3_restart_fw(), TG3_RX_RCB_RING_SIZE, tg3_set_bdinfo(), tg3_set_power_state_0(), tg3_setup_phy(), tg3_stop_fw(), tg3_switch_clocks(), TG3_TX_RING_SIZE, tg3_write_mem(), TG3_WRITE_SETTINGS, TG3PCI_CLOCK_CTRL, TG3PCI_DMA_RW_CTRL, TG3PCI_MEM_WIN_BASE_ADDR, TG3PCI_PCISTATE, TG3PCI_X_CAPS, tr32, tw32, tw32_carefully(), tw32_mailbox, tw32_mailbox2(), TX_LENGTHS_IPG_CRS_SHIFT, TX_LENGTHS_IPG_SHIFT, TX_LENGTHS_SLOT_TIME_SHIFT, tg3::tx_mode, TX_MODE_ENABLE, tg3::tx_prod, tg3::tx_ring, udelay(), virt_to_bus(), WDMAC_MODE, WDMAC_MODE_ADDROFLOW_ENAB, WDMAC_MODE_ENABLE, WDMAC_MODE_FIFOOFLOW_ENAB, WDMAC_MODE_FIFOOREAD_ENAB, WDMAC_MODE_FIFOURUN_ENAB, WDMAC_MODE_LNGREAD_ENAB, WDMAC_MODE_MSTABORT_ENAB, WDMAC_MODE_PARITYERR_ENAB, WDMAC_MODE_RX_ACCEL, and WDMAC_MODE_TGTABORT_ENAB.
Referenced by tg3_probe(), and tg3_transmit().
01803 { 01804 uint32_t val, rdmac_mode; 01805 int i, err, limit; 01806 01807 /* Simply don't support setups with extremly buggy firmware in etherboot */ 01808 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { 01809 printf("Error 5701_A0 firmware bug detected\n"); 01810 return -EINVAL; 01811 } 01812 01813 tg3_disable_ints(tp); 01814 01815 /* Originally this was all in tg3_init_hw */ 01816 01817 /* Force the chip into D0. */ 01818 tg3_set_power_state_0(tp); 01819 01820 tg3_switch_clocks(tp); 01821 01822 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); 01823 01824 // This should go somewhere else 01825 #define T3_PCIE_CAPABILITY_ID_REG 0xD0 01826 #define T3_PCIE_CAPABILITY_ID 0x10 01827 #define T3_PCIE_CAPABILITY_REG 0xD2 01828 01829 /* Originally this was all in tg3_reset_hw */ 01830 01831 tg3_stop_fw(tp); 01832 01833 /* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */ 01834 01835 tg3_chip_reset(tp); 01836 01837 tw32(GRC_MODE, tp->grc_mode); /* Redundant? */ 01838 01839 err = tg3_restart_fw(tp, DRV_STATE_START); 01840 if (err) 01841 return err; 01842 01843 if (tp->phy_id == PHY_ID_SERDES) { 01844 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; 01845 } 01846 tw32_carefully(MAC_MODE, tp->mac_mode); 01847 01848 01849 /* This works around an issue with Athlon chipsets on 01850 * B3 tigon3 silicon. This bit has no effect on any 01851 * other revision. 01852 * Alf: Except 5750 ! (which reboots) 01853 */ 01854 01855 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) 01856 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; 01857 tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); 01858 01859 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && 01860 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { 01861 val = tr32(TG3PCI_PCISTATE); 01862 val |= PCISTATE_RETRY_SAME_DMA; 01863 tw32(TG3PCI_PCISTATE, val); 01864 } 01865 01866 /* Descriptor ring init may make accesses to the 01867 * NIC SRAM area to setup the TX descriptors, so we 01868 * can only do this after the hardware has been 01869 * successfully reset. 01870 */ 01871 tg3_init_rings(tp); 01872 01873 /* Clear statistics/status block in chip */ 01874 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { 01875 for (i = NIC_SRAM_STATS_BLK; 01876 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; 01877 i += sizeof(uint32_t)) { 01878 tg3_write_mem(i, 0); 01879 udelay(40); 01880 } 01881 } 01882 01883 /* This value is determined during the probe time DMA 01884 * engine test, tg3_setup_dma. 01885 */ 01886 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); 01887 01888 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | 01889 GRC_MODE_4X_NIC_SEND_RINGS | 01890 GRC_MODE_NO_TX_PHDR_CSUM | 01891 GRC_MODE_NO_RX_PHDR_CSUM); 01892 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; 01893 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; 01894 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM; 01895 01896 tw32(GRC_MODE, 01897 tp->grc_mode | 01898 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); 01899 01900 /* Setup the timer prescalar register. Clock is always 66Mhz. */ 01901 tw32(GRC_MISC_CFG, 01902 (65 << GRC_MISC_CFG_PRESCALAR_SHIFT)); 01903 01904 /* Initialize MBUF/DESC pool. */ 01905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) { 01906 /* Do nothing. */ 01907 } else if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) && 01908 (tp->pci_chip_rev_id != CHIPREV_ID_5721)) { 01909 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); 01910 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) 01911 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); 01912 else 01913 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); 01914 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); 01915 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); 01916 } 01917 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) { 01918 tw32(BUFMGR_MB_RDMA_LOW_WATER, 01919 tp->bufmgr_config.mbuf_read_dma_low_water); 01920 tw32(BUFMGR_MB_MACRX_LOW_WATER, 01921 tp->bufmgr_config.mbuf_mac_rx_low_water); 01922 tw32(BUFMGR_MB_HIGH_WATER, 01923 tp->bufmgr_config.mbuf_high_water); 01924 } else { 01925 tw32(BUFMGR_MB_RDMA_LOW_WATER, 01926 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); 01927 tw32(BUFMGR_MB_MACRX_LOW_WATER, 01928 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); 01929 tw32(BUFMGR_MB_HIGH_WATER, 01930 tp->bufmgr_config.mbuf_high_water_jumbo); 01931 } 01932 tw32(BUFMGR_DMA_LOW_WATER, 01933 tp->bufmgr_config.dma_low_water); 01934 tw32(BUFMGR_DMA_HIGH_WATER, 01935 tp->bufmgr_config.dma_high_water); 01936 01937 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); 01938 for (i = 0; i < 2000; i++) { 01939 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) 01940 break; 01941 udelay(10); 01942 } 01943 if (i >= 2000) { 01944 printf("tg3_setup_hw cannot enable BUFMGR\n"); 01945 return -ENODEV; 01946 } 01947 01948 tw32(FTQ_RESET, 0xffffffff); 01949 tw32(FTQ_RESET, 0x00000000); 01950 for (i = 0; i < 2000; i++) { 01951 if (tr32(FTQ_RESET) == 0x00000000) 01952 break; 01953 udelay(10); 01954 } 01955 if (i >= 2000) { 01956 printf("tg3_setup_hw cannot reset FTQ\n"); 01957 return -ENODEV; 01958 } 01959 01960 /* Initialize TG3_BDINFO's at: 01961 * RCVDBDI_STD_BD: standard eth size rx ring 01962 * RCVDBDI_JUMBO_BD: jumbo frame rx ring 01963 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) 01964 * 01965 * like so: 01966 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring 01967 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | 01968 * ring attribute flags 01969 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM 01970 * 01971 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. 01972 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. 01973 * 01974 * ??? No space allocated for mini receive ring? :( 01975 * 01976 * The size of each ring is fixed in the firmware, but the location is 01977 * configurable. 01978 */ 01979 { 01980 static const uint32_t table_all[] = { 01981 /* Setup replenish thresholds. */ 01982 RCVBDI_STD_THRESH, TG3_DEF_RX_RING_PENDING / 8, 01983 01984 /* Etherboot lives below 4GB */ 01985 RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 0, 01986 RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC, 01987 }; 01988 static const uint32_t table_not_5705[] = { 01989 /* Buffer maximum length */ 01990 RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT, 01991 01992 /* Disable the mini frame rx ring */ 01993 RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED, 01994 01995 /* Disable the jumbo frame rx ring */ 01996 RCVBDI_JUMBO_THRESH, 0, 01997 RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED, 01998 01999 02000 }; 02001 TG3_WRITE_SETTINGS(table_all); 02002 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 02003 virt_to_bus(tp->rx_std)); 02004 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || 02005 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) { 02006 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, 02007 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT); 02008 } else { 02009 TG3_WRITE_SETTINGS(table_not_5705); 02010 } 02011 } 02012 02013 02014 /* There is only one send ring on 5705 and 5787, no need to explicitly 02015 * disable the others. 02016 */ 02017 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && 02018 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) { 02019 /* Clear out send RCB ring in SRAM. */ 02020 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE) 02021 tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED); 02022 } 02023 02024 tp->tx_prod = 0; 02025 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0); 02026 tw32_mailbox2(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0); 02027 02028 tg3_set_bdinfo(tp, 02029 NIC_SRAM_SEND_RCB, 02030 virt_to_bus(tp->tx_ring), 02031 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT), 02032 NIC_SRAM_TX_BUFFER_DESC); 02033 02034 /* There is only one receive return ring on 5705 and 5787, no need to 02035 * explicitly disable the others. 02036 */ 02037 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && 02038 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) { 02039 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) { 02040 tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, 02041 BDINFO_FLAGS_DISABLED); 02042 } 02043 } 02044 02045 tp->rx_rcb_ptr = 0; 02046 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0); 02047 02048 tg3_set_bdinfo(tp, 02049 NIC_SRAM_RCV_RET_RCB, 02050 virt_to_bus(tp->rx_rcb), 02051 (TG3_RX_RCB_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT), 02052 0); 02053 02054 tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING; 02055 tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, 02056 tp->rx_std_ptr); 02057 02058 tw32_mailbox2(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 0); 02059 02060 /* Initialize MAC address and backoff seed. */ 02061 __tg3_set_mac_addr(tp); 02062 02063 /* Calculate RDMAC_MODE setting early, we need it to determine 02064 * the RCVLPC_STATE_ENABLE mask. 02065 */ 02066 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | 02067 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | 02068 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | 02069 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | 02070 RDMAC_MODE_LNGREAD_ENAB); 02071 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) 02072 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE; 02073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { 02074 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { 02075 if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && 02076 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { 02077 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; 02078 } 02079 } 02080 } 02081 02082 /* Setup host coalescing engine. */ 02083 tw32(HOSTCC_MODE, 0); 02084 for (i = 0; i < 2000; i++) { 02085 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) 02086 break; 02087 udelay(10); 02088 } 02089 02090 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | 02091 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; 02092 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); 02093 02094 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; 02095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) 02096 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | 02097 GRC_LCLCTRL_GPIO_OUTPUT1); 02098 tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl); 02099 02100 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0); 02101 tr32(MAILBOX_INTERRUPT_0); 02102 02103 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { 02104 tw32_carefully(DMAC_MODE, DMAC_MODE_ENABLE); 02105 } 02106 02107 val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | 02108 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | 02109 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | 02110 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | 02111 WDMAC_MODE_LNGREAD_ENAB); 02112 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) && 02113 ((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) && 02114 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { 02115 val |= WDMAC_MODE_RX_ACCEL; 02116 } 02117 02118 /* Host coalescing bug fix */ 02119 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) 02120 val |= (1 << 29); 02121 02122 tw32_carefully(WDMAC_MODE, val); 02123 02124 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { 02125 val = tr32(TG3PCI_X_CAPS); 02126 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { 02127 val &= PCIX_CAPS_BURST_MASK; 02128 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT); 02129 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { 02130 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK); 02131 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT); 02132 if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) 02133 val |= (tp->split_mode_max_reqs << 02134 PCIX_CAPS_SPLIT_SHIFT); 02135 } 02136 tw32(TG3PCI_X_CAPS, val); 02137 } 02138 02139 tw32_carefully(RDMAC_MODE, rdmac_mode); 02140 { 02141 static const uint32_t table_all[] = { 02142 /* MTU + ethernet header + FCS + optional VLAN tag */ 02143 MAC_RX_MTU_SIZE, ETH_MAX_MTU + ETH_HLEN + 8, 02144 02145 /* The slot time is changed by tg3_setup_phy if we 02146 * run at gigabit with half duplex. 02147 */ 02148 MAC_TX_LENGTHS, 02149 (2 << TX_LENGTHS_IPG_CRS_SHIFT) | 02150 (6 << TX_LENGTHS_IPG_SHIFT) | 02151 (32 << TX_LENGTHS_SLOT_TIME_SHIFT), 02152 02153 /* Receive rules. */ 02154 MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS, 02155 RCVLPC_CONFIG, 0x0181, 02156 02157 /* Receive/send statistics. */ 02158 RCVLPC_STATS_ENABLE, 0xffffff, 02159 RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE, 02160 SNDDATAI_STATSENAB, 0xffffff, 02161 SNDDATAI_STATSCTRL, (SNDDATAI_SCTRL_ENABLE |SNDDATAI_SCTRL_FASTUPD), 02162 02163 /* Host coalescing engine */ 02164 HOSTCC_RXCOL_TICKS, 0, 02165 HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS, 02166 HOSTCC_RXMAX_FRAMES, 1, 02167 HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES, 02168 HOSTCC_RXCOAL_MAXF_INT, 1, 02169 HOSTCC_TXCOAL_MAXF_INT, 0, 02170 02171 /* Status/statistics block address. */ 02172 /* Etherboot lives below 4GB, so HIGH == 0 */ 02173 HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0, 02174 02175 /* No need to enable 32byte coalesce mode. */ 02176 HOSTCC_MODE, HOSTCC_MODE_ENABLE | 0, 02177 02178 RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE, 02179 RCVLPC_MODE, RCVLPC_MODE_ENABLE, 02180 02181 RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE, 02182 02183 SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, 02184 SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE, 02185 RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB, 02186 RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ, 02187 SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, 02188 SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE, 02189 SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE, 02190 02191 /* Accept all multicast frames. */ 02192 MAC_HASH_REG_0, 0xffffffff, 02193 MAC_HASH_REG_1, 0xffffffff, 02194 MAC_HASH_REG_2, 0xffffffff, 02195 MAC_HASH_REG_3, 0xffffffff, 02196 }; 02197 static const uint32_t table_not_5705[] = { 02198 /* Host coalescing engine */ 02199 HOSTCC_RXCOAL_TICK_INT, 0, 02200 HOSTCC_TXCOAL_TICK_INT, 0, 02201 02202 /* Status/statistics block address. */ 02203 /* Etherboot lives below 4GB, so HIGH == 0 */ 02204 HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS, 02205 HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0, 02206 HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK, 02207 HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK, 02208 02209 RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE, 02210 02211 MBFREE_MODE, MBFREE_MODE_ENABLE, 02212 }; 02213 TG3_WRITE_SETTINGS(table_all); 02214 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, 02215 virt_to_bus(tp->hw_stats)); 02216 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, 02217 virt_to_bus(tp->hw_status)); 02218 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && 02219 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) { 02220 TG3_WRITE_SETTINGS(table_not_5705); 02221 } 02222 } 02223 02224 tp->tx_mode = TX_MODE_ENABLE; 02225 tw32_carefully(MAC_TX_MODE, tp->tx_mode); 02226 02227 tp->rx_mode = RX_MODE_ENABLE; 02228 tw32_carefully(MAC_RX_MODE, tp->rx_mode); 02229 02230 tp->mi_mode = MAC_MI_MODE_BASE; 02231 tw32_carefully(MAC_MI_MODE, tp->mi_mode); 02232 02233 tw32(MAC_LED_CTRL, 0); 02234 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); 02235 if (tp->phy_id == PHY_ID_SERDES) { 02236 tw32_carefully(MAC_RX_MODE, RX_MODE_RESET); 02237 } 02238 tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */ 02239 tw32_carefully(MAC_RX_MODE, tp->rx_mode); 02240 02241 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) 02242 tw32(MAC_SERDES_CFG, 0x616000); 02243 02244 /* Prevent chip from dropping frames when flow control 02245 * is enabled. 02246 */ 02247 tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2); 02248 tr32(MAC_LOW_WMARK_MAX_RX_FRAME); 02249 02250 err = tg3_setup_phy(tp); 02251 02252 /* Ignore CRC stats */ 02253 02254 /* Initialize receive rules. */ 02255 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); 02256 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); 02257 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); 02258 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); 02259 02260 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) 02261 || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) 02262 limit = 8; 02263 else 02264 limit = 16; 02265 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) 02266 limit -= 4; 02267 switch (limit) { 02268 case 16: tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); 02269 case 15: tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); 02270 case 14: tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); 02271 case 13: tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); 02272 case 12: tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); 02273 case 11: tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); 02274 case 10: tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); 02275 case 9: tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); 02276 case 8: tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); 02277 case 7: tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); 02278 case 6: tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); 02279 case 5: tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); 02280 case 4: /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ 02281 case 3: /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ 02282 case 2: 02283 case 1: 02284 default: 02285 break; 02286 }; 02287 02288 return err; 02289 }
| static void tg3_nvram_init | ( | struct tg3 * | tp | ) | [static] |
Definition at line 2294 of file tg3.c.
References ASIC_REV_5700, ASIC_REV_5701, EEPROM_ADDR_CLKPERD_SHIFT, EEPROM_ADDR_FSM_RESET, EEPROM_DEFAULT_CLOCK_PERIOD, GET_ASIC_REV, GRC_EEPROM_ADDR, GRC_LCLCTRL_AUTO_SEEPROM, GRC_LOCAL_CTRL, mdelay(), NVRAM_CFG1, NVRAM_CFG1_BUFFERED_MODE, NVRAM_CFG1_COMPAT_BYPASS, NVRAM_CFG1_FLASHIF_ENAB, tg3::pci_chip_rev_id, TG3_FLAG_NVRAM, TG3_FLAG_NVRAM_BUFFERED, tg3::tg3_flags, tr32, tw32, and tw32_carefully().
Referenced by tg3_get_invariants().
02295 { 02296 tw32(GRC_EEPROM_ADDR, 02297 (EEPROM_ADDR_FSM_RESET | 02298 (EEPROM_DEFAULT_CLOCK_PERIOD << 02299 EEPROM_ADDR_CLKPERD_SHIFT))); 02300 02301 mdelay(1); 02302 02303 /* Enable seeprom accesses. */ 02304 tw32_carefully(GRC_LOCAL_CTRL, 02305 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); 02306 02307 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && 02308 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { 02309 uint32_t nvcfg1 = tr32(NVRAM_CFG1); 02310 02311 tp->tg3_flags |= TG3_FLAG_NVRAM; 02312 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { 02313 if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE) 02314 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; 02315 } else { 02316 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; 02317 tw32(NVRAM_CFG1, nvcfg1); 02318 } 02319 02320 } else { 02321 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); 02322 } 02323 }
| static int tg3_nvram_read_using_eeprom | ( | struct tg3 *tp | __unused, | |
| uint32_t | offset, | |||
| uint32_t * | val | |||
| ) | [static] |
Definition at line 2326 of file tg3.c.
References EBUSY, EEPROM_ADDR_ADDR_MASK, EEPROM_ADDR_ADDR_SHIFT, EEPROM_ADDR_COMPLETE, EEPROM_ADDR_DEVID_MASK, EEPROM_ADDR_DEVID_SHIFT, EEPROM_ADDR_READ, EEPROM_ADDR_START, EINVAL, GRC_EEPROM_ADDR, GRC_EEPROM_DATA, tr32, tw32, and udelay().
Referenced by tg3_nvram_read().
02328 { 02329 uint32_t tmp; 02330 int i; 02331 02332 if (offset > EEPROM_ADDR_ADDR_MASK || 02333 (offset % 4) != 0) { 02334 return -EINVAL; 02335 } 02336 02337 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | 02338 EEPROM_ADDR_DEVID_MASK | 02339 EEPROM_ADDR_READ); 02340 tw32(GRC_EEPROM_ADDR, 02341 tmp | 02342 (0 << EEPROM_ADDR_DEVID_SHIFT) | 02343 ((offset << EEPROM_ADDR_ADDR_SHIFT) & 02344 EEPROM_ADDR_ADDR_MASK) | 02345 EEPROM_ADDR_READ | EEPROM_ADDR_START); 02346 02347 for (i = 0; i < 10000; i++) { 02348 tmp = tr32(GRC_EEPROM_ADDR); 02349 02350 if (tmp & EEPROM_ADDR_COMPLETE) 02351 break; 02352 udelay(100); 02353 } 02354 if (!(tmp & EEPROM_ADDR_COMPLETE)) { 02355 return -EBUSY; 02356 } 02357 02358 *val = tr32(GRC_EEPROM_DATA); 02359 return 0; 02360 }
Definition at line 2362 of file tg3.c.
References bswap_32, EBUSY, EINVAL, NVRAM_ADDR, NVRAM_ADDR_MSK, NVRAM_BUFFERED_PAGE_POS, NVRAM_BUFFERED_PAGE_SIZE, NVRAM_CMD, NVRAM_CMD_DONE, NVRAM_CMD_FIRST, NVRAM_CMD_GO, NVRAM_CMD_LAST, NVRAM_CMD_RD, NVRAM_RDDATA, NVRAM_SWARB, SWARB_GNT1, SWARB_REQ_CLR1, SWARB_REQ_SET1, TG3_FLAG_NVRAM, TG3_FLAG_NVRAM_BUFFERED, tg3::tg3_flags, tg3_nvram_read_using_eeprom(), tr32, tw32, and udelay().
Referenced by tg3_get_device_address(), and tg3_read_partno().
02363 { 02364 int i, saw_done_clear; 02365 02366 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) 02367 return tg3_nvram_read_using_eeprom(tp, offset, val); 02368 02369 if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) 02370 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) << 02371 NVRAM_BUFFERED_PAGE_POS) + 02372 (offset % NVRAM_BUFFERED_PAGE_SIZE); 02373 02374 if (offset > NVRAM_ADDR_MSK) 02375 return -EINVAL; 02376 02377 tw32(NVRAM_SWARB, SWARB_REQ_SET1); 02378 for (i = 0; i < 1000; i++) { 02379 if (tr32(NVRAM_SWARB) & SWARB_GNT1) 02380 break; 02381 udelay(20); 02382 } 02383 02384 tw32(NVRAM_ADDR, offset); 02385 tw32(NVRAM_CMD, 02386 NVRAM_CMD_RD | NVRAM_CMD_GO | 02387 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); 02388 02389 /* Wait for done bit to clear then set again. */ 02390 saw_done_clear = 0; 02391 for (i = 0; i < 1000; i++) { 02392 udelay(10); 02393 if (!saw_done_clear && 02394 !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE)) 02395 saw_done_clear = 1; 02396 else if (saw_done_clear && 02397 (tr32(NVRAM_CMD) & NVRAM_CMD_DONE)) 02398 break; 02399 } 02400 if (i >= 1000) { 02401 tw32(NVRAM_SWARB, SWARB_REQ_CLR1); 02402 return -EBUSY; 02403 } 02404 02405 *val = bswap_32(tr32(NVRAM_RDDATA)); 02406 tw32(NVRAM_SWARB, 0x20); 02407 02408 return 0; 02409 }
| static int tg3_phy_probe | ( | struct tg3 * | tp | ) | [static] |
Definition at line 2458 of file tg3.c.
References ADVERTISE_100FULL, ADVERTISE_100HALF, ADVERTISE_10FULL, ADVERTISE_10HALF, ADVERTISE_CSMA, ADVERTISE_PAUSE_CAP, ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_Autoneg, ADVERTISED_FIBRE, tg3_link_config::advertising, ASIC_REV_5703, ASIC_REV_5704, ASIC_REV_5705, BMCR_ANENABLE, BMCR_ANRESTART, CHIPREV_ID_5701_A0, CHIPREV_ID_5701_B0, ENODEV, GET_ASIC_REV, KNOWN_PHY_ID, tg3::led_mode, led_mode_auto, led_mode_link10, led_mode_three_link, tg3::link_config, MII_ADVERTISE, MII_BMCR, MII_PHYSID1, MII_PHYSID2, MII_TG3_AUX_CTRL, MII_TG3_CTRL, MII_TG3_CTRL_ADV_1000_FULL, MII_TG3_CTRL_ADV_1000_HALF, MII_TG3_CTRL_AS_MASTER, MII_TG3_CTRL_ENABLE_AS_MASTER, MII_TG3_DSP_ADDRESS, MII_TG3_DSP_RW_PORT, tg3::nic_sram_data_cfg, NIC_SRAM_DATA_CFG, NIC_SRAM_DATA_CFG_ASF_ENABLE, NIC_SRAM_DATA_CFG_EEPROM_WP, NIC_SRAM_DATA_CFG_FIBER_WOL, NIC_SRAM_DATA_CFG_LED_LINK_SPD, NIC_SRAM_DATA_CFG_LED_MODE_MASK, NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD, NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER, NIC_SRAM_DATA_CFG_PHY_TYPE_MASK, NIC_SRAM_DATA_PHY_ID, NIC_SRAM_DATA_PHY_ID1_MASK, NIC_SRAM_DATA_PHY_ID2_MASK, NIC_SRAM_DATA_SIG, NIC_SRAM_DATA_SIG_MAGIC, tg3::pci_chip_rev_id, PCI_VENDOR_ID_DELL, subsys_tbl_ent::phy_id, tg3::phy_id, PHY_ID_BCM5401, PHY_ID_INVALID, PHY_ID_MASK, PHY_ID_SERDES, subsys_tbl_ent::subsys_devid, subsys_tbl_ent::subsys_vendor, tg3::subsystem_device, tg3::subsystem_vendor, TG3_FLAG_10_100_ONLY, TG3_FLAG_EEPROM_WRITE_PROT, TG3_FLAG_ENABLE_ASF, TG3_FLAG_SERDES_WOL_CAP, tg3::tg3_flags, tg3_init_5401phy_dsp(), tg3_phy_reset(), tg3_phy_set_wirespeed(), tg3_read_mem(), tg3_readphy(), tg3_writedsp(), and tg3_writephy().
Referenced by tg3_get_invariants().
02459 { 02460 uint32_t eeprom_phy_id, hw_phy_id_1, hw_phy_id_2; 02461 uint32_t hw_phy_id, hw_phy_id_masked; 02462 enum phy_led_mode eeprom_led_mode; 02463 uint32_t val; 02464 unsigned i; 02465 int eeprom_signature_found, err; 02466 02467 tp->phy_id = PHY_ID_INVALID; 02468 02469 for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) { 02470 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) && 02471 (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) { 02472 tp->phy_id = subsys_id_to_phy_id[i].phy_id; 02473 break; 02474 } 02475 } 02476 02477 eeprom_phy_id = PHY_ID_INVALID; 02478 eeprom_led_mode = led_mode_auto; 02479 eeprom_signature_found = 0; 02480 tg3_read_mem(NIC_SRAM_DATA_SIG, &val); 02481 if (val == NIC_SRAM_DATA_SIG_MAGIC) { 02482 uint32_t nic_cfg; 02483 02484 tg3_read_mem(NIC_SRAM_DATA_CFG, &nic_cfg); 02485 tp->nic_sram_data_cfg = nic_cfg; 02486 02487 eeprom_signature_found = 1; 02488 02489 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == 02490 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) { 02491 eeprom_phy_id = PHY_ID_SERDES; 02492 } else { 02493 uint32_t nic_phy_id; 02494 02495 tg3_read_mem(NIC_SRAM_DATA_PHY_ID, &nic_phy_id); 02496 if (nic_phy_id != 0) { 02497 uint32_t id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; 02498 uint32_t id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; 02499 02500 eeprom_phy_id = (id1 >> 16) << 10; 02501 eeprom_phy_id |= (id2 & 0xfc00) << 16; 02502 eeprom_phy_id |= (id2 & 0x03ff) << 0; 02503 } 02504 } 02505 02506 switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) { 02507 case NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD: 02508 eeprom_led_mode = led_mode_three_link; 02509 break; 02510 02511 case NIC_SRAM_DATA_CFG_LED_LINK_SPD: 02512 eeprom_led_mode = led_mode_link10; 02513 break; 02514 02515 default: 02516 eeprom_led_mode = led_mode_auto; 02517 break; 02518 }; 02519 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || 02520 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || 02521 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) && 02522 (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)) { 02523 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; 02524 } 02525 02526 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) 02527 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 02528 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL) 02529 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP; 02530 } 02531 02532 /* Now read the physical PHY_ID from the chip and verify 02533 * that it is sane. If it doesn't look good, we fall back 02534 * to either the hard-coded table based PHY_ID and failing 02535 * that the value found in the eeprom area. 02536 */ 02537 err = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); 02538 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); 02539 02540 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; 02541 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; 02542 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; 02543 02544 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK; 02545 02546 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) { 02547 tp->phy_id = hw_phy_id; 02548 } else { 02549 /* phy_id currently holds the value found in the 02550 * subsys_id_to_phy_id[] table or PHY_ID_INVALID 02551 * if a match was not found there. 02552 */ 02553 if (tp->phy_id == PHY_ID_INVALID) { 02554 if (!eeprom_signature_found || 02555 !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK)) 02556 return -ENODEV; 02557 tp->phy_id = eeprom_phy_id; 02558 } 02559 } 02560 02561 err = tg3_phy_reset(tp); 02562 if (err) 02563 return err; 02564 02565 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || 02566 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { 02567 uint32_t mii_tg3_ctrl; 02568 02569 /* These chips, when reset, only advertise 10Mb 02570 * capabilities. Fix that. 02571 */ 02572 err = tg3_writephy(tp, MII_ADVERTISE, 02573 (ADVERTISE_CSMA | 02574 ADVERTISE_PAUSE_CAP | 02575 ADVERTISE_10HALF | 02576 ADVERTISE_10FULL | 02577 ADVERTISE_100HALF | 02578 ADVERTISE_100FULL)); 02579 mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | 02580 MII_TG3_CTRL_ADV_1000_FULL | 02581 MII_TG3_CTRL_AS_MASTER | 02582 MII_TG3_CTRL_ENABLE_AS_MASTER); 02583 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) 02584 mii_tg3_ctrl = 0; 02585 02586 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl); 02587 err |= tg3_writephy(tp, MII_BMCR, 02588 (BMCR_ANRESTART | BMCR_ANENABLE)); 02589 } 02590 02591 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { 02592 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); 02593 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); 02594 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); 02595 } 02596 02597 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { 02598 tg3_writephy(tp, 0x1c, 0x8d68); 02599 tg3_writephy(tp, 0x1c, 0x8d68); 02600 } 02601 02602 /* Enable Ethernet@WireSpeed */ 02603 tg3_phy_set_wirespeed(tp); 02604 02605 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) { 02606 err = tg3_init_5401phy_dsp(tp); 02607 } 02608 02609 /* Determine the PHY led mode. 02610 * Be careful if this gets set wrong it can result in an inability to 02611 * establish a link. 02612 */ 02613 if (tp->phy_id == PHY_ID_SERDES) { 02614 tp->led_mode = led_mode_three_link; 02615 } 02616 else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) { 02617 tp->led_mode = led_mode_link10; 02618 } else { 02619 tp->led_mode = led_mode_three_link; 02620 if (eeprom_signature_found && 02621 eeprom_led_mode != led_mode_auto) 02622 tp->led_mode = eeprom_led_mode; 02623 } 02624 02625 if (tp->phy_id == PHY_ID_SERDES) 02626 tp->link_config.advertising = 02627 (ADVERTISED_1000baseT_Half | 02628 ADVERTISED_1000baseT_Full | 02629 ADVERTISED_Autoneg | 02630 ADVERTISED_FIBRE); 02631 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) 02632 tp->link_config.advertising &= 02633 ~(ADVERTISED_1000baseT_Half | 02634 ADVERTISED_1000baseT_Full); 02635 02636 return err; 02637 }
| static void tg3_read_partno | ( | struct tg3 * | tp | ) | [static] |
Definition at line 2640 of file tg3.c.
References tg3::board_part_number, memcpy, and tg3_nvram_read().
Referenced by tg3_get_invariants().
02641 { 02642 unsigned char vpd_data[256]; 02643 int i; 02644 02645 for (i = 0; i < 256; i += 4) { 02646 uint32_t tmp; 02647 02648 if (tg3_nvram_read(tp, 0x100 + i, &tmp)) 02649 goto out_not_found; 02650 02651 vpd_data[i + 0] = ((tmp >> 0) & 0xff); 02652 vpd_data[i + 1] = ((tmp >> 8) & 0xff); 02653 vpd_data[i + 2] = ((tmp >> 16) & 0xff); 02654 vpd_data[i + 3] = ((tmp >> 24) & 0xff); 02655 } 02656 02657 /* Now parse and find the part number. */ 02658 for (i = 0; i < 256; ) { 02659 unsigned char val = vpd_data[i]; 02660 int block_end; 02661 02662 if (val == 0x82 || val == 0x91) { 02663 i = (i + 3 + 02664 (vpd_data[i + 1] + 02665 (vpd_data[i + 2] << 8))); 02666 continue; 02667 } 02668 02669 if (val != 0x90) 02670 goto out_not_found; 02671 02672 block_end = (i + 3 + 02673 (vpd_data[i + 1] + 02674 (vpd_data[i + 2] << 8))); 02675 i += 3; 02676 while (i < block_end) { 02677 if (vpd_data[i + 0] == 'P' && 02678 vpd_data[i + 1] == 'N') { 02679 int partno_len = vpd_data[i + 2]; 02680 02681 if (partno_len > 24) 02682 goto out_not_found; 02683 02684 memcpy(tp->board_part_number, 02685 &vpd_data[i + 3], 02686 partno_len); 02687 02688 /* Success. */ 02689 return; 02690 } 02691 } 02692 02693 /* Part number not found. */ 02694 goto out_not_found; 02695 } 02696 02697 out_not_found: 02698 memcpy(tp->board_part_number, "none", sizeof("none")); 02699 }
| static int tg3_get_invariants | ( | struct tg3 * | tp | ) | [static] |
Definition at line 2704 of file tg3.c.
References ASIC_REV_5700, ASIC_REV_5703, ASIC_REV_5704, ASIC_REV_5705, ASIC_REV_5750, CHIPREV_ID_5704_A0, CHIPREV_ID_5705_A0, CHIPREV_ID_5705_A1, pci_device::device, GET_ASIC_REV, GRC_MISC_CFG, GRC_MISC_CFG_BOARD_ID_5704CIOBE, GRC_MISC_CFG_BOARD_ID_5788, GRC_MISC_CFG_BOARD_ID_5788M, GRC_MISC_CFG_BOARD_ID_MASK, tg3::grc_mode, GRC_MODE, MAC_MI_MODE, tg3::mi_mode, tg3::misc_host_ctrl, MISC_HOST_CTRL_CHIPREV, MISC_HOST_CTRL_CHIPREV_SHIFT, PCI_CAP_ID_EXP, tg3::pci_chip_rev_id, PCI_COMMAND, PCI_COMMAND_INVALIDATE, PCI_COMMAND_PARITY, PCI_COMMAND_SERR, PCI_DEVICE_ID_TIGON3_5901, PCI_DEVICE_ID_TIGON3_5901_2, pci_find_capability(), PCI_LATENCY_TIMER, pci_read_config_byte(), pci_read_config_dword(), pci_read_config_word(), PCI_SUBSYSTEM_ID, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_BROADCOM, pci_write_config_byte(), pci_write_config_dword(), pci_write_config_word(), PCISTATE_BUS_32BIT, PCISTATE_BUS_SPEED_HIGH, PCISTATE_CONV_PCI_MODE, PCISTATE_RETRY_SAME_DMA, tg3::pdev, printf(), SPLIT_MODE_5704_MAX_REQ, tg3::split_mode_max_reqs, tg3::subsystem_device, tg3::subsystem_vendor, TG3_FLAG_10_100_ONLY, TG3_FLAG_PCI_32BIT, TG3_FLAG_PCI_HIGH_SPEED, TG3_FLAG_PCIX_MODE, TG3_FLAG_SPLIT_MODE, tg3::tg3_flags, tg3::tg3_flags2, TG3_FLG2_IS_5788, TG3_FLG2_NO_ETH_WIRE_SPEED, TG3_FLG2_PCI_EXPRESS, tg3_nvram_init(), tg3_phy_probe(), tg3_read_partno(), tg3_set_power_state_0(), tg3_switch_clocks(), TG3PCI_MEM_WIN_BASE_ADDR, TG3PCI_MISC_HOST_CTRL, TG3PCI_PCISTATE, tr32, tw32, tw32_carefully(), udelay(), and pci_device::vendor.
Referenced by tg3_probe().
02705 { 02706 uint32_t misc_ctrl_reg; 02707 uint32_t pci_state_reg, grc_misc_cfg; 02708 uint16_t pci_cmd; 02709 uint8_t pci_latency; 02710 uint32_t val ; 02711 int err; 02712 02713 /* Read the subsystem vendor and device ids */ 02714 pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor); 02715 pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device); 02716 02717 /* The sun_5704 code needs infrastructure etherboot does have 02718 * ignore it for now. 02719 */ 02720 02721 /* If we have an AMD 762 or Intel ICH/ICH0 chipset, write 02722 * reordering to the mailbox registers done by the host 02723 * controller can cause major troubles. We read back from 02724 * every mailbox register write to force the writes to be 02725 * posted to the chip in order. 02726 * 02727 * TG3_FLAG_MBOX_WRITE_REORDER has been forced on. 02728 */ 02729 02730 /* Force memory write invalidate off. If we leave it on, 02731 * then on 5700_BX chips we have to enable a workaround. 02732 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry 02733 * to match the cacheline size. The Broadcom driver have this 02734 * workaround but turns MWI off all the times so never uses 02735 * it. This seems to suggest that the workaround is insufficient. 02736 */ 02737 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); 02738 pci_cmd &= ~PCI_COMMAND_INVALIDATE; 02739 /* Also, force SERR#/PERR# in PCI command. */ 02740 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; 02741 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); 02742 02743 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL 02744 * has the register indirect write enable bit set before 02745 * we try to access any of the MMIO registers. It is also 02746 * critical that the PCI-X hw workaround situation is decided 02747 * before that as well. 02748 */ 02749 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg); 02750 02751 tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT); 02752 02753 /* Initialize misc host control in PCI block. */ 02754 tp->misc_host_ctrl |= (misc_ctrl_reg & 02755 MISC_HOST_CTRL_CHIPREV); 02756 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, 02757 tp->misc_host_ctrl); 02758 02759 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency); 02760 if (pci_latency < 64) { 02761 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64); 02762 } 02763 02764 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg); 02765 02766 /* If this is a 5700 BX chipset, and we are in PCI-X 02767 * mode, enable register write workaround. 02768 * 02769 * The workaround is to use indirect register accesses 02770 * for all chip writes not to mailbox registers. 02771 * 02772 * In etherboot to simplify things we just always use this work around. 02773 */ 02774 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) { 02775 tp->tg3_flags |= TG3_FLAG_PCIX_MODE; 02776 } 02777 /* Back to back register writes can cause problems on the 5701, 02778 * the workaround is to read back all reg writes except those to 02779 * mailbox regs. 02780 * In etherboot we always use indirect register accesses so 02781 * we don't see this. 02782 */ 02783 02784 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) 02785 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; 02786 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) 02787 tp->tg3_flags |= TG3_FLAG_PCI_32BIT; 02788 02789 /* Chip-specific fixup from Broadcom driver */ 02790 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && 02791 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { 02792 pci_state_reg |= PCISTATE_RETRY_SAME_DMA; 02793 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); 02794 } 02795 02796 /* determine if it is PCIE system */ 02797 // Alf : I have no idea what this is about... 02798 // But it's definitely usefull 02799 val = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); 02800 if (val) 02801 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; 02802 02803 /* Force the chip into D0. */ 02804 tg3_set_power_state_0(tp); 02805 02806 /* Etherboot does not ask the tg3 to do checksums */ 02807 /* Etherboot does not ask the tg3 to do jumbo frames */ 02808 /* Ehterboot does not ask the tg3 to use WakeOnLan. */ 02809 02810 /* A few boards don't want Ethernet@WireSpeed phy feature */ 02811 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || 02812 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || 02813 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && 02814 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && 02815 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) { 02816 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; 02817 } 02818 02819 /* Avoid tagged irq status etherboot does not use irqs */ 02820 02821 /* Only 5701 and later support tagged irq status mode. 02822 * Also, 5788 chips cannot use tagged irq status. 02823 * 02824 * However, since etherboot does not use irqs avoid tagged irqs 02825 * status because the interrupt condition is more difficult to 02826 * fully clear in that mode. 02827 */ 02828 02829 /* Since some 5700_AX && 5700_BX have problems with 32BYTE 02830 * coalesce_mode, and the rest work fine anything set. 02831 * Don't enable HOST_CC_MODE_32BYTE in etherboot. 02832 */ 02833 02834 /* Initialize MAC MI mode, polling disabled. */ 02835 tw32_carefully(MAC_MI_MODE, tp->mi_mode); 02836 02837 /* Initialize data/descriptor byte/word swapping. */ 02838 tw32(GRC_MODE, tp->grc_mode); 02839 02840 tg3_switch_clocks(tp); 02841 02842 /* Clear this out for sanity. */ 02843 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); 02844 02845 /* Etherboot does not need to check if the PCIX_TARGET_HWBUG 02846 * is needed. It always uses it. 02847 */ 02848 02849 udelay(50); 02850 tg3_nvram_init(tp); 02851 02852 /* The TX descriptors will reside in main memory. 02853 */ 02854 02855 /* See which board we are using. 02856 */ 02857 grc_misc_cfg = tr32(GRC_MISC_CFG); 02858 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; 02859 02860 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && 02861 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) { 02862 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE; 02863 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ; 02864 } 02865 02866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && 02867 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || 02868 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) 02869 tp->tg3_flags2 |= TG3_FLG2_IS_5788; 02870 02871 #define PCI_DEVICE_ID_TIGON3_5901 0x170d 02872 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e 02873 02874 /* these are limited to 10/100 only */ 02875 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) && 02876 ((grc_misc_cfg == 0x8000) || (grc_misc_cfg == 0x4000))) || 02877 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && 02878 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) && 02879 ((tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901) || 02880 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2)))) { 02881 tp->tg3_flags |= TG3_FLAG_10_100_ONLY; 02882 } 02883 02884 err = tg3_phy_probe(tp); 02885 if (err) { 02886 printf("phy probe failed, err %d\n", err); 02887 } 02888 02889 tg3_read_partno(tp); 02890 02891 02892 /* 5700 BX chips need to have their TX producer index mailboxes 02893 * written twice to workaround a bug. 02894 * In etherboot we do this unconditionally to simplify things. 02895 */ 02896 02897 /* 5700 chips can get confused if TX buffers straddle the 02898 * 4GB address boundary in some cases. 02899 * 02900 * In etherboot we can ignore the problem as etherboot lives below 4GB. 02901 */ 02902 02903 /* In etherboot wake-on-lan is unconditionally disabled */ 02904 return err; 02905 }
| static int tg3_get_device_address | ( | struct tg3 * | tp | ) | [static] |
Definition at line 2907 of file tg3.c.
References pci_device::devfn, MAC_ADDR_0_HIGH, MAC_ADDR_0_LOW, tg3::nic, NIC_SRAM_MAC_ADDR_HIGH_MBOX, NIC_SRAM_MAC_ADDR_LOW_MBOX, nic::node_addr, PCI_FUNC, tg3::pdev, tg3_nvram_read(), tg3_read_mem(), and tr32.
Referenced by tg3_probe().
02908 { 02909 struct nic *nic = tp->nic; 02910 uint32_t hi, lo, mac_offset; 02911 02912 if (PCI_FUNC(tp->pdev->devfn) == 0) 02913 mac_offset = 0x7c; 02914 else 02915 mac_offset = 0xcc; 02916 02917 /* First try to get it from MAC address mailbox. */ 02918 tg3_read_mem(NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); 02919 if ((hi >> 16) == 0x484b) { 02920 nic->node_addr[0] = (hi >> 8) & 0xff; 02921 nic->node_addr[1] = (hi >> 0) & 0xff; 02922 02923 tg3_read_mem(NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); 02924 nic->node_addr[2] = (lo >> 24) & 0xff; 02925 nic->node_addr[3] = (lo >> 16) & 0xff; 02926 nic->node_addr[4] = (lo >> 8) & 0xff; 02927 nic->node_addr[5] = (lo >> 0) & 0xff; 02928 } 02929 /* Next, try NVRAM. */ 02930 else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) && 02931 !tg3_nvram_read(tp, mac_offset + 4, &lo)) { 02932 nic->node_addr[0] = ((hi >> 16) & 0xff); 02933 nic->node_addr[1] = ((hi >> 24) & 0xff); 02934 nic->node_addr[2] = ((lo >> 0) & 0xff); 02935 nic->node_addr[3] = ((lo >> 8) & 0xff); 02936 nic->node_addr[4] = ((lo >> 16) & 0xff); 02937 nic->node_addr[5] = ((lo >> 24) & 0xff); 02938 } 02939 /* Finally just fetch it out of the MAC control regs. */ 02940 else { 02941 hi = tr32(MAC_ADDR_0_HIGH); 02942 lo = tr32(MAC_ADDR_0_LOW); 02943 02944 nic->node_addr[5] = lo & 0xff; 02945 nic->node_addr[4] = (lo >> 8) & 0xff; 02946 nic->node_addr[3] = (lo >> 16) & 0xff; 02947 nic->node_addr[2] = (lo >> 24) & 0xff; 02948 nic->node_addr[1] = hi & 0xff; 02949 nic->node_addr[0] = (hi >> 8) & 0xff; 02950 } 02951 02952 return 0; 02953 }
| static int tg3_setup_dma | ( | struct tg3 * | tp | ) | [static] |
Definition at line 2956 of file tg3.c.
References ASIC_REV_5703, ASIC_REV_5704, ASIC_REV_5705, tg3::dma_rwctrl, DMA_RWCTRL_ASSERT_ALL_BE, DMA_RWCTRL_MIN_DMA, DMA_RWCTRL_MIN_DMA_SHIFT, DMA_RWCTRL_ONE_DMA, DMA_RWCTRL_PCI_READ_CMD_SHIFT, DMA_RWCTRL_PCI_WRITE_CMD_SHIFT, DMA_RWCTRL_READ_WATER_SHIFT, DMA_RWCTRL_WRITE_WATER_SHIFT, GET_ASIC_REV, tg3::pci_chip_rev_id, TG3_FLAG_PCIX_MODE, tg3::tg3_flags, TG3PCI_CLOCK_CTRL, TG3PCI_DMA_RW_CTRL, tr32, and tw32.
Referenced by tg3_probe().
02957 { 02958 tw32(TG3PCI_CLOCK_CTRL, 0); 02959 02960 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) { 02961 tp->dma_rwctrl = 02962 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | 02963 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) | 02964 (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) | 02965 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) | 02966 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT); 02967 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { 02968 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT); 02969 } 02970 } else { 02971 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) 02972 tp->dma_rwctrl = 02973 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | 02974 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) | 02975 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | 02976 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) | 02977 (0x00 << DMA_RWCTRL_MIN_DMA_SHIFT); 02978 else 02979 tp->dma_rwctrl = 02980 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | 02981 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) | 02982 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | 02983 (0x3 << DMA_RWCTRL_READ_WATER_SHIFT) | 02984 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT); 02985 02986 /* Wheee, some more chip bugs... */ 02987 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || 02988 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) { 02989 uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; 02990 02991 if ((ccval == 0x6) || (ccval == 0x7)) { 02992 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; 02993 } 02994 } 02995 } 02996 02997 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) || 02998 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) { 02999 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT); 03000 } 03001 03002 /* 03003 Alf : Tried that, but it does not work. Should be this way though :-( 03004 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { 03005 tp->dma_rwctrl |= 0x001f0000; 03006 } 03007 */ 03008 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; 03009 03010 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); 03011 03012 return 0; 03013 }
| static void tg3_init_link_config | ( | struct tg3 * | tp | ) | [static] |
Definition at line 3015 of file tg3.c.
References tg3_link_config::active_duplex, tg3_link_config::active_speed, ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_100baseT_Full, ADVERTISED_100baseT_Half, ADVERTISED_10baseT_Full, ADVERTISED_10baseT_Half, ADVERTISED_Autoneg, ADVERTISED_MII, tg3_link_config::advertising, tg3::carrier_ok, DUPLEX_INVALID, tg3::link_config, and SPEED_INVALID.
Referenced by tg3_probe().
03016 { 03017 tp->link_config.advertising = 03018 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | 03019 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | 03020 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | 03021 ADVERTISED_Autoneg | ADVERTISED_MII); 03022 tp->carrier_ok = 0; 03023 tp->link_config.active_speed = SPEED_INVALID; 03024 tp->link_config.active_duplex = DUPLEX_INVALID; 03025 }
| static const char* tg3_phy_string | ( | struct tg3 * | tp | ) | [static] |
Definition at line 3029 of file tg3.c.
References tg3::phy_id, PHY_ID_BCM5400, PHY_ID_BCM5401, PHY_ID_BCM5411, PHY_ID_BCM5701, PHY_ID_BCM5703, PHY_ID_BCM5704, PHY_ID_BCM5705, PHY_ID_BCM5750, PHY_ID_BCM5751, PHY_ID_BCM5787, PHY_ID_BCM8002, PHY_ID_MASK, and PHY_ID_SERDES.
Referenced by tg3_probe().
03030 { 03031 switch (tp->phy_id & PHY_ID_MASK) { 03032 case PHY_ID_BCM5400: return "5400"; 03033 case PHY_ID_BCM5401: return "5401"; 03034 case PHY_ID_BCM5411: return "5411"; 03035 case PHY_ID_BCM5701: return "5701"; 03036 case PHY_ID_BCM5703: return "5703"; 03037 case PHY_ID_BCM5704: return "5704"; 03038 case PHY_ID_BCM5705: return "5705"; 03039 case PHY_ID_BCM5750: return "5750"; 03040 case PHY_ID_BCM5751: return "5751"; 03041 case PHY_ID_BCM5787: return "5787"; 03042 case PHY_ID_BCM8002: return "8002/serdes"; 03043 case PHY_ID_SERDES: return "serdes"; 03044 default: return "unknown"; 03045 }; 03046 }
| static void tg3_poll_link | ( | struct tg3 * | tp | ) | [static] |
Definition at line 3052 of file tg3.c.
References tg3::carrier_ok, tg3::mac_mode, MAC_MODE, MAC_MODE_PORT_MODE_MASK, MAC_STATUS, MAC_STATUS_LNKSTATE_CHANGED, MAC_STATUS_PCS_SYNCED, tg3::phy_id, PHY_ID_SERDES, tg3_setup_phy(), tr32, and tw32_carefully().
Referenced by tg3_poll(), and tg3_probe().
03053 { 03054 uint32_t mac_stat; 03055 03056 mac_stat = tr32(MAC_STATUS); 03057 if (tp->phy_id == PHY_ID_SERDES) { 03058 if (tp->carrier_ok? 03059 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED): 03060 (mac_stat & MAC_STATUS_PCS_SYNCED)) { 03061 tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK); 03062 tw32_carefully(MAC_MODE, tp->mac_mode); 03063 03064 tg3_setup_phy(tp); 03065 } 03066 } 03067 else { 03068 if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) { 03069 tg3_setup_phy(tp); 03070 } 03071 } 03072 }
| static void tg3_ack_irqs | ( | struct tg3 * | tp | ) | [static] |
Definition at line 3077 of file tg3.c.
References tg3::hw_status, MAILBOX_INTERRUPT_0, SD_STATUS_UPDATED, tg3_hw_status::status, TG3_64BIT_REG_LOW, tr32, and tw32_mailbox.
Referenced by tg3_poll().
03078 { 03079 if (tp->hw_status->status & SD_STATUS_UPDATED) { 03080 /* 03081 * writing any value to intr-mbox-0 clears PCI INTA# and 03082 * chip-internal interrupt pending events. 03083 * writing non-zero to intr-mbox-0 additional tells the 03084 * NIC to stop sending us irqs, engaging "in-intr-handler" 03085 * event coalescing. 03086 */ 03087 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 03088 0x00000001); 03089 /* 03090 * Flush PCI write. This also guarantees that our 03091 * status block has been flushed to host memory. 03092 */ 03093 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW); 03094 tp->hw_status->status &= ~SD_STATUS_UPDATED; 03095 } 03096 }
| static int tg3_poll | ( | struct nic * | nic, | |
| int | retrieve | |||
| ) | [static] |
Definition at line 3098 of file tg3.c.
References tg3_rx_buffer_desc::addr_lo, bus_to_virt(), tg3::hw_status, tg3_hw_status::idx, tg3_rx_buffer_desc::idx_len, MAILBOX_RCV_STD_PROD_IDX, MAILBOX_RCVRET_CON_IDX_0, memcpy, tg3_rx_buffer_desc::opaque, nic::packet, nic::packetlen, tg3_hw_status::rx_producer, tg3::rx_rcb, tg3::rx_rcb_ptr, tg3::rx_std_ptr, RXD_LEN_MASK, RXD_LEN_SHIFT, RXD_OPAQUE_RING_MASK, RXD_OPAQUE_RING_STD, TG3_64BIT_REG_LOW, tg3_ack_irqs(), tg3_poll_link(), TG3_RX_RCB_RING_SIZE, TG3_RX_RING_SIZE, tp, and tw32_mailbox2().
03099 { 03100 /* return true if there's an ethernet packet ready to read */ 03101 /* nic->packet should contain data on return */ 03102 /* nic->packetlen should contain length of data */ 03103 03104 struct tg3 *tp = &tg3; 03105 int result; 03106 03107 result = 0; 03108 03109 if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve ) 03110 return 1; 03111 03112 tg3_ack_irqs(tp); 03113 03114 if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) { 03115 struct tg3_rx_buffer_desc *desc; 03116 unsigned int len; 03117 desc = &tp->rx_rcb[tp->rx_rcb_ptr]; 03118 if ((desc->opaque & RXD_OPAQUE_RING_MASK) == RXD_OPAQUE_RING_STD) { 03119 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */ 03120 03121 nic->packetlen = len; 03122 memcpy(nic->packet, bus_to_virt(desc->addr_lo), len); 03123 result = 1; 03124 } 03125 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE; 03126 03127 /* ACK the status ring */ 03128 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr); 03129 03130 /* Refill RX ring. */ 03131 if (result) { 03132 tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE; 03133 tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr); 03134 } 03135 } 03136 tg3_poll_link(tp); 03137 return result; 03138 }
| static void tg3_transmit | ( | struct nic * | nic, | |
| const char * | dst_addr, | |||
| unsigned int | type, | |||
| unsigned int | size, | |||
| const char * | packet | |||
| ) | [static] |
Definition at line 3161 of file tg3.c.
References tg3_tx_buffer_desc::addr_hi, tg3_tx_buffer_desc::addr_lo, eth_frame::data, eth_frame::dst_addr, ETH_ALEN, ETH_HLEN, htons, tg3::hw_status, tg3_hw_status::idx, tg3_tx_buffer_desc::len_flags, MAILBOX_SNDHOST_PROD_IDX_0, mdelay(), memcpy, memset(), NEXT_TX, nic::node_addr, PREV_TX, printf(), eth_frame::src_addr, TG3_64BIT_REG_LOW, tg3_halt(), tg3_setup_hw(), tw32_mailbox, tw32_mailbox2(), tg3_hw_status::tx_consumer, tg3::tx_prod, tg3::tx_ring, TXD_FLAG_END, TXD_LEN_SHIFT, TXD_VLAN_TAG_SHIFT, eth_frame::type, virt_to_bus(), and tg3_tx_buffer_desc::vlan_tag.
03163 { 03164 static int frame_idx; 03165 struct eth_frame *frame; 03166 03167 /* send the packet to destination */ 03168 struct tg3_tx_buffer_desc *txd; 03169 struct tg3 *tp; 03170 uint32_t entry; 03171 int i; 03172 03173 /* Wait until there is a free packet frame */ 03174 tp = &tg3; 03175 i = 0; 03176 entry = tp->tx_prod; 03177 while((tp->hw_status->idx[0].tx_consumer != entry) && 03178 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) { 03179 mdelay(10); /* give the nick a chance */ 03180 if (++i > 500) { /* timeout 5s for transmit */ 03181 printf("transmit timed out\n"); 03182 tg3_halt(tp); 03183 tg3_setup_hw(tp); 03184 return; 03185 } 03186 } 03187 if (i != 0) { 03188 printf("#"); 03189 } 03190 03191 /* Copy the packet to the our local buffer */ 03192 frame = &tg3_bss.tx_frame[frame_idx]; 03193 memcpy(frame->dst_addr, dst_addr, ETH_ALEN); 03194 memcpy(frame->src_addr, nic->node_addr, ETH_ALEN); 03195 frame->type = htons(type); 03196 memset(frame->data, 0, sizeof(frame->data)); 03197 memcpy(frame->data, packet, size); 03198 03199 /* Setup the ring buffer entry to transmit */ 03200 txd = &tp->tx_ring[entry]; 03201 txd->addr_hi = 0; /* Etherboot runs under 4GB */ 03202 txd->addr_lo = virt_to_bus(frame); 03203 txd->len_flags = ((size + ETH_HLEN) << TXD_LEN_SHIFT) | TXD_FLAG_END; 03204 txd->vlan_tag = 0 << TXD_VLAN_TAG_SHIFT; 03205 03206 /* Advance to the next entry */ 03207 entry = NEXT_TX(entry); 03208 frame_idx ^= 1; 03209 03210 /* Packets are ready, update Tx producer idx local and on card */ 03211 tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry); 03212 tw32_mailbox2((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry); 03213 tp->tx_prod = entry; 03214 }
Definition at line 3219 of file tg3.c.
References tg3::carrier_ok, iounmap(), tg3::regs, TG3_FLAG_GOT_SERDES_FLOWCTL, TG3_FLAG_INIT_COMPLETE, tg3::tg3_flags, and tg3_halt().
Referenced by tg3_probe().
03219 { 03220 struct tg3 *tp = &tg3; 03221 /* put the card in its initial state */ 03222 /* This function serves 3 purposes. 03223 * This disables DMA and interrupts so we don't receive 03224 * unexpected packets or interrupts from the card after 03225 * etherboot has finished. 03226 * This frees resources so etherboot may use 03227 * this driver on another interface 03228 * This allows etherboot to reinitialize the interface 03229 * if something is something goes wrong. 03230 */ 03231 tg3_halt(tp); 03232 tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL); 03233 tp->carrier_ok = 0; 03234 iounmap((void *)tp->regs); 03235 }
| static void tg3_irq | ( | struct nic *nic | __unused, | |
| irq_action_t action | __unused | |||
| ) | [static] |
| static int tg3_probe | ( | struct nic * | nic, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 3264 of file tg3.c.
References adjust_pci_device(), tg3::board_part_number, tg3::carrier_ok, DBG, eth_ntoa(), tg3::grc_mode, GRC_MODE_BSWAP_DATA, GRC_MODE_BSWAP_NONFRM_DATA, GRC_MODE_WSWAP_DATA, GRC_MODE_WSWAP_NONFRM_DATA, pci_device::ioaddr, nic::ioaddr, ioremap(), iounmap(), nic::irqno, MAC_MI_MODE_BASE, mdelay(), memset(), tg3::mi_mode, tg3::misc_host_ctrl, MISC_HOST_CTRL_INDIR_ACCESS, MISC_HOST_CTRL_MASK_PCI_INT, MISC_HOST_CTRL_PCISTATE_RW, MISC_HOST_CTRL_WORD_SWAP, tg3::nic, nic::nic_op, nic::node_addr, pci_bar_size(), pci_bar_start(), PCI_BASE_ADDRESS_0, PCI_CAP_ID_PM, tg3::pci_cfg_state, tg3::pci_chip_rev_id, pci_find_capability(), pci_save_state(), tg3::pdev, tg3::pm_cap, printf(), tg3::regs, tg3::rx_mode, tg3_disable(), TG3_FLAG_INIT_COMPLETE, TG3_FLAG_PCI_32BIT, TG3_FLAG_PCI_HIGH_SPEED, TG3_FLAG_PCIX_MODE, tg3::tg3_flags, tg3_get_device_address(), tg3_get_invariants(), tg3_init_link_config(), tg3_phy_string(), tg3_poll_link(), tg3_setup_dma(), tg3_setup_hw(), tg3::tx_mode, and VALID_LINK_TIMEOUT.
03264 { 03265 03266 struct tg3 *tp = &tg3; 03267 unsigned long tg3reg_base, tg3reg_len; 03268 int i, err, pm_cap; 03269 03270 memset(tp, 0, sizeof(*tp)); 03271 03272 adjust_pci_device(pdev); 03273 03274 nic->irqno = 0; 03275 nic->ioaddr = pdev->ioaddr; 03276 03277 /* Find power-management capability. */ 03278 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); 03279 if (pm_cap == 0) { 03280 printf("Cannot find PowerManagement capability, aborting.\n"); 03281 return 0; 03282 } 03283 tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0); 03284 if (tg3reg_base == -1UL) { 03285 printf("Unuseable bar\n"); 03286 return 0; 03287 } 03288 tg3reg_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_0); 03289 03290 tp->pdev = pdev; 03291 tp->nic = nic; 03292 tp->pm_cap = pm_cap; 03293 tp->rx_mode = 0; 03294 tp->tx_mode = 0; 03295 tp->mi_mode = MAC_MI_MODE_BASE; 03296 tp->tg3_flags = 0 & ~TG3_FLAG_INIT_COMPLETE; 03297 03298 /* The word/byte swap controls here control register access byte 03299 * swapping. DMA data byte swapping is controlled in the GRC_MODE 03300 * setting below. 03301 */ 03302 tp->misc_host_ctrl = 03303 MISC_HOST_CTRL_MASK_PCI_INT | 03304 MISC_HOST_CTRL_WORD_SWAP | 03305 MISC_HOST_CTRL_INDIR_ACCESS | 03306 MISC_HOST_CTRL_PCISTATE_RW; 03307 03308 /* The NONFRM (non-frame) byte/word swap controls take effect 03309 * on descriptor entries, anything which isn't packet data. 03310 * 03311 * The StrongARM chips on the board (one for tx, one for rx) 03312 * are running in big-endian mode. 03313 */ 03314 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | 03315 GRC_MODE_WSWAP_NONFRM_DATA); 03316 #if __BYTE_ORDER == __BIG_ENDIAN 03317 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; 03318 #endif 03319 tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len); 03320 if (tp->regs == 0UL) { 03321 printf("Cannot map device registers, aborting\n"); 03322 return 0; 03323 } 03324 03325 tg3_init_link_config(tp); 03326 03327 err = tg3_get_invariants(tp); 03328 if (err) { 03329 printf("Problem fetching invariants of chip, aborting.\n"); 03330 goto err_out_iounmap; 03331 } 03332 03333 err = tg3_get_device_address(tp); 03334 if (err) { 03335 printf("Could not obtain valid ethernet address, aborting.\n"); 03336 goto err_out_iounmap; 03337 } 03338 03339 DBG ( "Ethernet addr: %s\n", eth_ntoa ( nic->node_addr ) ); 03340 03341 tg3_setup_dma(tp); 03342 03343 /* Now that we have fully setup the chip, save away a snapshot 03344 * of the PCI config space. We need to restore this after 03345 * GRC_MISC_CFG core clock resets and some resume events. 03346 */ 03347 pci_save_state(tp->pdev, tp->pci_cfg_state); 03348 03349 printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n", 03350 tp->board_part_number, 03351 tp->pci_chip_rev_id, 03352 tg3_phy_string(tp), 03353 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""), 03354 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ? 03355 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") : 03356 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")), 03357 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit")); 03358 03359 03360 err = tg3_setup_hw(tp); 03361 if (err) { 03362 goto err_out_disable; 03363 } 03364 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; 03365 03366 /* Wait for a reasonable time for the link to come up */ 03367 tg3_poll_link(tp); 03368 for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) { 03369 mdelay(1); 03370 tg3_poll_link(tp); 03371 } 03372 if (!tp->carrier_ok){ 03373 printf("Valid link not established\n"); 03374 goto err_out_disable; 03375 } 03376 03377 nic->nic_op = &tg3_operations; 03378 return 1; 03379 03380 err_out_iounmap: 03381 iounmap((void *)tp->regs); 03382 return 0; 03383 err_out_disable: 03384 tg3_disable(nic); 03385 return 0; 03386 }
| PCI_DRIVER | ( | tg3_driver | , | |
| tg3_nics | , | |||
| PCI_NO_CLASS | ||||
| ) |
| DRIVER | ( | "TG3" | , | |
| nic_driver | , | |||
| pci_driver | , | |||
| tg3_driver | , | |||
| tg3_probe | , | |||
| tg3_disable | ||||
| ) |
struct subsys_tbl_ent subsys_id_to_phy_id[] [static] |
struct nic_operations tg3_operations [static] |
Initial value:
{
.connect = dummy_connect,
.poll = tg3_poll,
.transmit = tg3_transmit,
.irq = tg3_irq,
}
struct pci_device_id tg3_nics[] [static] |
1.5.7.1