Go to the source code of this file.
Defines | |
| #define | BANK_SELECT 14 |
| #define | TCR 0 |
| #define | TCR_ENABLE 0x0001 |
| #define | TCR_FDUPLX 0x0800 |
| #define | TCR_STP_SQET 0x1000 |
| #define | TCR_MON_CNS 0x0400 |
| #define | TCR_PAD_ENABLE 0x0080 |
| #define | TCR_CLEAR 0 |
| #define | TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE) |
| #define | EPH_STATUS 2 |
| #define | ES_LINK_OK 0x4000 |
| #define | RCR 4 |
| #define | RCR_SOFTRESET 0x8000 |
| #define | RCR_STRIP_CRC 0x200 |
| #define | RCR_ENABLE 0x100 |
| #define | RCR_ALMUL 0x4 |
| #define | RCR_PROMISC 0x2 |
| #define | RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) |
| #define | RCR_CLEAR 0x0 |
| #define | COUNTER 6 |
| #define | MIR 8 |
| #define | MCR 10 |
| #define | RPC_REG 0x000A |
| #define | RPC_SPEED 0x2000 |
| #define | RPC_DPLX 0x1000 |
| #define | RPC_ANEG 0x0800 |
| #define | RPC_LSXA_SHFT 5 |
| #define | RPC_LSXB_SHFT 2 |
| #define | RPC_LED_100_10 (0x00) |
| #define | RPC_LED_RES (0x01) |
| #define | RPC_LED_10 (0x02) |
| #define | RPC_LED_FD (0x03) |
| #define | RPC_LED_TX_RX (0x04) |
| #define | RPC_LED_100 (0x05) |
| #define | RPC_LED_TX (0x06) |
| #define | RPC_LED_RX (0x07) |
| #define | RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
| #define | RPC_REG 0x000A |
| #define | RPC_SPEED 0x2000 |
| #define | RPC_DPLX 0x1000 |
| #define | RPC_ANEG 0x0800 |
| #define | RPC_LSXA_SHFT 5 |
| #define | RPC_LSXB_SHFT 2 |
| #define | RPC_LED_100_10 (0x00) |
| #define | RPC_LED_RES (0x01) |
| #define | RPC_LED_10 (0x02) |
| #define | RPC_LED_FD (0x03) |
| #define | RPC_LED_TX_RX (0x04) |
| #define | RPC_LED_100 (0x05) |
| #define | RPC_LED_TX (0x06) |
| #define | RPC_LED_RX (0x07) |
| #define | RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
| #define | CONFIG 0 |
| #define | CFG_AUI_SELECT 0x100 |
| #define | BASE 2 |
| #define | ADDR0 4 |
| #define | ADDR1 6 |
| #define | ADDR2 8 |
| #define | GENERAL 10 |
| #define | CONTROL 12 |
| #define | CTL_POWERDOWN 0x2000 |
| #define | CTL_LE_ENABLE 0x80 |
| #define | CTL_CR_ENABLE 0x40 |
| #define | CTL_TE_ENABLE 0x0020 |
| #define | CTL_AUTO_RELEASE 0x0800 |
| #define | CTL_EPROM_ACCESS 0x0003 |
| #define | MMU_CMD 0 |
| #define | MC_BUSY 1 |
| #define | MC_NOP 0 |
| #define | MC_ALLOC 0x20 |
| #define | MC_RESET 0x40 |
| #define | MC_REMOVE 0x60 |
| #define | MC_RELEASE 0x80 |
| #define | MC_FREEPKT 0xA0 |
| #define | MC_ENQUEUE 0xC0 |
| #define | PNR_ARR 2 |
| #define | FIFO_PORTS 4 |
| #define | FP_RXEMPTY 0x8000 |
| #define | FP_TXEMPTY 0x80 |
| #define | POINTER 6 |
| #define | PTR_READ 0x2000 |
| #define | PTR_RCV 0x8000 |
| #define | PTR_AUTOINC 0x4000 |
| #define | PTR_AUTO_INC 0x0040 |
| #define | DATA_1 8 |
| #define | DATA_2 10 |
| #define | INTERRUPT 12 |
| #define | INT_MASK 13 |
| #define | IM_RCV_INT 0x1 |
| #define | IM_TX_INT 0x2 |
| #define | IM_TX_EMPTY_INT 0x4 |
| #define | IM_ALLOC_INT 0x8 |
| #define | IM_RX_OVRN_INT 0x10 |
| #define | IM_EPH_INT 0x20 |
| #define | IM_ERCV_INT 0x40 |
| #define | MULTICAST1 0 |
| #define | MULTICAST2 2 |
| #define | MULTICAST3 4 |
| #define | MULTICAST4 6 |
| #define | MGMT 8 |
| #define | REVISION 10 |
| #define | MII_REG 0x0008 |
| #define | MII_MSK_CRS100 0x4000 |
| #define | MII_MDOE 0x0008 |
| #define | MII_MCLK 0x0004 |
| #define | MII_MDI 0x0002 |
| #define | MII_MDO 0x0001 |
| #define | ERCV 12 |
| #define | CHIP_9190 3 |
| #define | CHIP_9194 4 |
| #define | CHIP_9195 5 |
| #define | CHIP_9196 4 |
| #define | CHIP_91100 7 |
| #define | CHIP_91100FD 8 |
| #define | REV_9196 6 |
| #define | TS_SUCCESS 0x0001 |
| #define | TS_LOSTCAR 0x0400 |
| #define | TS_LATCOL 0x0200 |
| #define | TS_16COL 0x0010 |
| #define | RS_ALGNERR 0x8000 |
| #define | RS_BADCRC 0x2000 |
| #define | RS_ODDFRAME 0x1000 |
| #define | RS_TOOLONG 0x0800 |
| #define | RS_TOOSHORT 0x0400 |
| #define | RS_MULTICAST 0x0001 |
| #define | RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
| #define | PHY_CNTL_REG 0x00 |
| #define | PHY_CNTL_RST 0x8000 |
| #define | PHY_CNTL_LPBK 0x4000 |
| #define | PHY_CNTL_SPEED 0x2000 |
| #define | PHY_CNTL_ANEG_EN 0x1000 |
| #define | PHY_CNTL_PDN 0x0800 |
| #define | PHY_CNTL_MII_DIS 0x0400 |
| #define | PHY_CNTL_ANEG_RST 0x0200 |
| #define | PHY_CNTL_DPLX 0x0100 |
| #define | PHY_CNTL_COLTST 0x0080 |
| #define | PHY_STAT_REG 0x01 |
| #define | PHY_STAT_CAP_T4 0x8000 |
| #define | PHY_STAT_CAP_TXF 0x4000 |
| #define | PHY_STAT_CAP_TXH 0x2000 |
| #define | PHY_STAT_CAP_TF 0x1000 |
| #define | PHY_STAT_CAP_TH 0x0800 |
| #define | PHY_STAT_CAP_SUPR 0x0040 |
| #define | PHY_STAT_ANEG_ACK 0x0020 |
| #define | PHY_STAT_REM_FLT 0x0010 |
| #define | PHY_STAT_CAP_ANEG 0x0008 |
| #define | PHY_STAT_LINK 0x0004 |
| #define | PHY_STAT_JAB 0x0002 |
| #define | PHY_STAT_EXREG 0x0001 |
| #define | PHY_ID1_REG 0x02 |
| #define | PHY_ID2_REG 0x03 |
| #define | PHY_AD_REG 0x04 |
| #define | PHY_AD_NP 0x8000 |
| #define | PHY_AD_ACK 0x4000 |
| #define | PHY_AD_RF 0x2000 |
| #define | PHY_AD_T4 0x0200 |
| #define | PHY_AD_TX_FDX 0x0100 |
| #define | PHY_AD_TX_HDX 0x0080 |
| #define | PHY_AD_10_FDX 0x0040 |
| #define | PHY_AD_10_HDX 0x0020 |
| #define | PHY_AD_CSMA 0x0001 |
| #define | PHY_RMT_REG 0x05 |
| #define | PHY_CFG1_REG 0x10 |
| #define | PHY_CFG1_LNKDIS 0x8000 |
| #define | PHY_CFG1_XMTDIS 0x4000 |
| #define | PHY_CFG1_XMTPDN 0x2000 |
| #define | PHY_CFG1_BYPSCR 0x0400 |
| #define | PHY_CFG1_UNSCDS 0x0200 |
| #define | PHY_CFG1_EQLZR 0x0100 |
| #define | PHY_CFG1_CABLE 0x0080 |
| #define | PHY_CFG1_RLVL0 0x0040 |
| #define | PHY_CFG1_TLVL_SHIFT 2 |
| #define | PHY_CFG1_TLVL_MASK 0x003C |
| #define | PHY_CFG1_TRF_MASK 0x0003 |
| #define | PHY_CFG2_REG 0x11 |
| #define | PHY_CFG2_APOLDIS 0x0020 |
| #define | PHY_CFG2_JABDIS 0x0010 |
| #define | PHY_CFG2_MREG 0x0008 |
| #define | PHY_CFG2_INTMDIO 0x0004 |
| #define | PHY_INT_REG 0x12 |
| #define | PHY_INT_INT 0x8000 |
| #define | PHY_INT_LNKFAIL 0x4000 |
| #define | PHY_INT_LOSSSYNC 0x2000 |
| #define | PHY_INT_CWRD 0x1000 |
| #define | PHY_INT_SSD 0x0800 |
| #define | PHY_INT_ESD 0x0400 |
| #define | PHY_INT_RPOL 0x0200 |
| #define | PHY_INT_JAB 0x0100 |
| #define | PHY_INT_SPDDET 0x0080 |
| #define | PHY_INT_DPLXDET 0x0040 |
| #define | PHY_MASK_REG 0x13 |
| #define | PHY_CNTL_REG 0x00 |
| #define | PHY_CNTL_RST 0x8000 |
| #define | PHY_CNTL_LPBK 0x4000 |
| #define | PHY_CNTL_SPEED 0x2000 |
| #define | PHY_CNTL_ANEG_EN 0x1000 |
| #define | PHY_CNTL_PDN 0x0800 |
| #define | PHY_CNTL_MII_DIS 0x0400 |
| #define | PHY_CNTL_ANEG_RST 0x0200 |
| #define | PHY_CNTL_DPLX 0x0100 |
| #define | PHY_CNTL_COLTST 0x0080 |
| #define | PHY_STAT_REG 0x01 |
| #define | PHY_STAT_CAP_T4 0x8000 |
| #define | PHY_STAT_CAP_TXF 0x4000 |
| #define | PHY_STAT_CAP_TXH 0x2000 |
| #define | PHY_STAT_CAP_TF 0x1000 |
| #define | PHY_STAT_CAP_TH 0x0800 |
| #define | PHY_STAT_CAP_SUPR 0x0040 |
| #define | PHY_STAT_ANEG_ACK 0x0020 |
| #define | PHY_STAT_REM_FLT 0x0010 |
| #define | PHY_STAT_CAP_ANEG 0x0008 |
| #define | PHY_STAT_LINK 0x0004 |
| #define | PHY_STAT_JAB 0x0002 |
| #define | PHY_STAT_EXREG 0x0001 |
| #define | PHY_ID1_REG 0x02 |
| #define | PHY_ID2_REG 0x03 |
| #define | PHY_AD_REG 0x04 |
| #define | PHY_AD_NP 0x8000 |
| #define | PHY_AD_ACK 0x4000 |
| #define | PHY_AD_RF 0x2000 |
| #define | PHY_AD_T4 0x0200 |
| #define | PHY_AD_TX_FDX 0x0100 |
| #define | PHY_AD_TX_HDX 0x0080 |
| #define | PHY_AD_10_FDX 0x0040 |
| #define | PHY_AD_10_HDX 0x0020 |
| #define | PHY_AD_CSMA 0x0001 |
| #define | PHY_RMT_REG 0x05 |
| #define | PHY_CFG1_REG 0x10 |
| #define | PHY_CFG1_LNKDIS 0x8000 |
| #define | PHY_CFG1_XMTDIS 0x4000 |
| #define | PHY_CFG1_XMTPDN 0x2000 |
| #define | PHY_CFG1_BYPSCR 0x0400 |
| #define | PHY_CFG1_UNSCDS 0x0200 |
| #define | PHY_CFG1_EQLZR 0x0100 |
| #define | PHY_CFG1_CABLE 0x0080 |
| #define | PHY_CFG1_RLVL0 0x0040 |
| #define | PHY_CFG1_TLVL_SHIFT 2 |
| #define | PHY_CFG1_TLVL_MASK 0x003C |
| #define | PHY_CFG1_TRF_MASK 0x0003 |
| #define | PHY_CFG2_REG 0x11 |
| #define | PHY_CFG2_APOLDIS 0x0020 |
| #define | PHY_CFG2_JABDIS 0x0010 |
| #define | PHY_CFG2_MREG 0x0008 |
| #define | PHY_CFG2_INTMDIO 0x0004 |
| #define | PHY_INT_REG 0x12 |
| #define | PHY_INT_INT 0x8000 |
| #define | PHY_INT_LNKFAIL 0x4000 |
| #define | PHY_INT_LOSSSYNC 0x2000 |
| #define | PHY_INT_CWRD 0x1000 |
| #define | PHY_INT_SSD 0x0800 |
| #define | PHY_INT_ESD 0x0400 |
| #define | PHY_INT_RPOL 0x0200 |
| #define | PHY_INT_JAB 0x0100 |
| #define | PHY_INT_SPDDET 0x0080 |
| #define | PHY_INT_DPLXDET 0x0040 |
| #define | PHY_MASK_REG 0x13 |
| #define | SMC_SELECT_BANK(x, y) { _outw( y, x + BANK_SELECT ); } |
| #define | SMC_DELAY(x) |
Typedefs | |
| typedef unsigned char | byte |
| typedef unsigned short | word |
| typedef unsigned long int | dword |
Functions | |
| FILE_LICENCE (GPL_ANY) | |
| #define BANK_SELECT 14 |
Definition at line 62 of file smc9000.h.
Referenced by smc9000_probe_addr(), smc_read_phy_register(), and smc_write_phy_register().
| #define TCR 0 |
Definition at line 66 of file smc9000.h.
Referenced by smc9000_disable(), smc9000_probe(), smc9000_transmit(), and smc_reset().
| #define TCR_ENABLE 0x0001 |
| #define TCR_CLEAR 0 |
| #define TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE) |
| #define RCR 4 |
Definition at line 81 of file smc9000.h.
Referenced by smc9000_disable(), smc9000_probe(), and smc_reset().
| #define RCR_SOFTRESET 0x8000 |
| #define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) |
| #define RCR_CLEAR 0x0 |
| #define MIR 8 |
| #define MCR 10 |
| #define RPC_REG 0x000A |
| #define RPC_SPEED 0x2000 |
| #define RPC_DPLX 0x1000 |
| #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
| #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) |
| #define CONFIG 0 |
| #define CFG_AUI_SELECT 0x100 |
| #define ADDR0 4 |
| #define MMU_CMD 0 |
Definition at line 150 of file smc9000.h.
Referenced by smc9000_poll(), smc9000_transmit(), and smc_reset().
| #define MC_ALLOC 0x20 |
| #define MC_RESET 0x40 |
| #define MC_RELEASE 0x80 |
| #define MC_FREEPKT 0xA0 |
| #define MC_ENQUEUE 0xC0 |
| #define PNR_ARR 2 |
| #define FIFO_PORTS 4 |
| #define FP_RXEMPTY 0x8000 |
| #define POINTER 6 |
| #define PTR_READ 0x2000 |
| #define PTR_RCV 0x8000 |
| #define PTR_AUTOINC 0x4000 |
| #define DATA_1 8 |
| #define INTERRUPT 12 |
| #define INT_MASK 13 |
| #define IM_TX_INT 0x2 |
| #define IM_ALLOC_INT 0x8 |
| #define REVISION 10 |
| #define MII_REG 0x0008 |
Definition at line 194 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
| #define MII_MDOE 0x0008 |
Definition at line 196 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
| #define MII_MCLK 0x0004 |
Definition at line 197 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
| #define MII_MDI 0x0002 |
Definition at line 198 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
| #define MII_MDO 0x0001 |
Definition at line 199 of file smc9000.h.
Referenced by smc_read_phy_register(), and smc_write_phy_register().
| #define CHIP_9196 4 |
| #define REV_9196 6 |
| #define TS_SUCCESS 0x0001 |
| #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
| #define PHY_CNTL_REG 0x00 |
| #define PHY_CNTL_RST 0x8000 |
| #define PHY_CNTL_SPEED 0x2000 |
| #define PHY_CNTL_ANEG_EN 0x1000 |
| #define PHY_CNTL_ANEG_RST 0x0200 |
| #define PHY_CNTL_DPLX 0x0100 |
| #define PHY_STAT_REG 0x01 |
| #define PHY_STAT_CAP_T4 0x8000 |
| #define PHY_STAT_CAP_TXF 0x4000 |
| #define PHY_STAT_CAP_TXH 0x2000 |
| #define PHY_STAT_CAP_TF 0x1000 |
| #define PHY_STAT_CAP_TH 0x0800 |
| #define PHY_STAT_ANEG_ACK 0x0020 |
| #define PHY_STAT_REM_FLT 0x0010 |
| #define PHY_ID1_REG 0x02 |
| #define PHY_ID2_REG 0x03 |
| #define PHY_AD_REG 0x04 |
| #define PHY_AD_T4 0x0200 |
| #define PHY_AD_TX_FDX 0x0100 |
| #define PHY_AD_TX_HDX 0x0080 |
| #define PHY_AD_10_FDX 0x0040 |
| #define PHY_AD_10_HDX 0x0020 |
| #define PHY_AD_CSMA 0x0001 |
| #define PHY_INT_REG 0x12 |
| #define PHY_INT_LOSSSYNC 0x2000 |
| #define PHY_INT_CWRD 0x1000 |
| #define PHY_INT_SSD 0x0800 |
| #define PHY_INT_ESD 0x0400 |
| #define PHY_INT_RPOL 0x0200 |
| #define PHY_INT_JAB 0x0100 |
| #define PHY_INT_SPDDET 0x0080 |
| #define PHY_INT_DPLXDET 0x0040 |
| #define PHY_MASK_REG 0x13 |
| #define SMC_SELECT_BANK | ( | x, | |||
| y | ) | { _outw( y, x + BANK_SELECT ); } |
Definition at line 419 of file smc9000.h.
Referenced by smc9000_disable(), smc9000_poll(), smc9000_probe(), smc9000_probe_addr(), smc9000_transmit(), smc_phy_configure(), smc_read_phy_register(), smc_reset(), and smc_write_phy_register().
| #define SMC_DELAY | ( | x | ) |
| FILE_LICENCE | ( | GPL_ANY | ) |
1.5.7.1