sky2.h File Reference

Go to the source code of this file.

Data Structures

struct  sky2_tx_le
struct  sky2_rx_le
struct  sky2_status_le
struct  tx_ring_info
struct  rx_ring_info
struct  sky2_port
struct  sky2_hw

Defines

#define AUTONEG_DISABLE   0x00
#define AUTONEG_ENABLE   0x01
#define DUPLEX_HALF   0x00
#define DUPLEX_FULL   0x01
#define SPEED_10   10
#define SPEED_100   100
#define SPEED_1000   1000
#define ADVERTISED_10baseT_Half   (1 << 0)
#define ADVERTISED_10baseT_Full   (1 << 1)
#define ADVERTISED_100baseT_Half   (1 << 2)
#define ADVERTISED_100baseT_Full   (1 << 3)
#define ADVERTISED_1000baseT_Half   (1 << 4)
#define ADVERTISED_1000baseT_Full   (1 << 5)
#define SUPPORTED_10baseT_Half   (1 << 0)
#define SUPPORTED_10baseT_Full   (1 << 1)
#define SUPPORTED_100baseT_Half   (1 << 2)
#define SUPPORTED_100baseT_Full   (1 << 3)
#define SUPPORTED_1000baseT_Half   (1 << 4)
#define SUPPORTED_1000baseT_Full   (1 << 5)
#define SUPPORTED_Autoneg   (1 << 6)
#define SUPPORTED_TP   (1 << 7)
#define SUPPORTED_FIBRE   (1 << 10)
#define P_PEX_LTSSM_STAT(x)   ((x << 25) & P_PEX_LTSSM_STAT_MSK)
#define PCI_STATUS_ERROR_BITS
#define RAM_BUFFER(port, reg)   (reg | (port <<6))
#define CFG_LED_MODE(x)   (((x) & CFG_LED_MODE_MSK) >> 2)
#define CFG_DUAL_MAC_MSK   (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
#define Y2_CLK_DIV_VAL(x)   (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
#define Y2_CLK_DIV_VAL_2(x)   (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
#define Y2_CLK_SEL_VAL_2(x)   (((x)<<16) & Y2_CLK_SELECT2_MSK)
#define RAM_ADR_RAN   0x0007ffffL
#define SK_RI_TO_53   36
#define SK_REG(port, reg)   (((port)<<7)+(reg))
#define TXA_MAX_VAL   0x00ffffffUL
#define Q_ADDR(reg, offs)   (B8_Q_REGS + (reg) + (offs))
#define Y2_QADDR(q, reg)   (Y2_B8_PREF_REGS + (q) + (reg))
#define RB_ADDR(offs, queue)   ((u16) B16_RAM_REGS + (queue) + (offs))
#define RB_MSK   0x0007ffff
#define WOL_REGS(port, x)   (x + (port)*0x80)
#define WOL_PATT_RAM_BASE(port)   (WOL_PATT_RAM_1 + (port)*0x400)
#define PHY_M_PC_MDI_XMODE(x)   (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
#define PHY_M_PS_PAUSE_MSK   (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
#define PHY_M_EC_M_DSC(x)   ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
#define PHY_M_EC_S_DSC(x)   ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
#define PHY_M_EC_DSC_2(x)   ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
#define PHY_M_EC_MAC_S(x)   ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
#define PHY_M_PC_DSC(x)   (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
#define PHY_M_LED_PULS_DUR(x)   (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
#define PHY_M_POLC_LS1_P_MIX(x)   (((x)<<12) & PHY_M_POLC_LS1M_MSK)
#define PHY_M_POLC_IS0_P_MIX(x)   (((x)<<8) & PHY_M_POLC_IS0M_MSK)
#define PHY_M_POLC_LOS_CTRL(x)   (((x)<<6) & PHY_M_POLC_LOS_MSK)
#define PHY_M_POLC_INIT_CTRL(x)   (((x)<<4) & PHY_M_POLC_INIT_MSK)
#define PHY_M_POLC_STA1_CTRL(x)   (((x)<<2) & PHY_M_POLC_STA1_MSK)
#define PHY_M_POLC_STA0_CTRL(x)   (((x)<<0) & PHY_M_POLC_STA0_MSK)
#define PHY_M_LED_BLINK_RT(x)   (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
#define PHY_M_LED_MO_SGMII(x)   ((x)<<14)
#define PHY_M_LED_MO_DUP(x)   ((x)<<10)
#define PHY_M_LED_MO_10(x)   ((x)<<8)
#define PHY_M_LED_MO_100(x)   ((x)<<6)
#define PHY_M_LED_MO_1000(x)   ((x)<<4)
#define PHY_M_LED_MO_RX(x)   ((x)<<2)
#define PHY_M_LED_MO_TX(x)   ((x)<<0)
#define PHY_M_FELP_LED2_CTRL(x)   (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
#define PHY_M_FELP_LED1_CTRL(x)   (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
#define PHY_M_FELP_LED0_CTRL(x)   (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
#define PHY_M_MAC_MODE_SEL(x)   (((x)<<7) & PHY_M_MAC_MD_MSK)
#define PHY_M_LEDC_LOS_CTRL(x)   (((x)<<12) & PHY_M_LEDC_LOS_MSK)
#define PHY_M_LEDC_INIT_CTRL(x)   (((x)<<8) & PHY_M_LEDC_INIT_MSK)
#define PHY_M_LEDC_STA1_CTRL(x)   (((x)<<4) & PHY_M_LEDC_STA1_MSK)
#define PHY_M_LEDC_STA0_CTRL(x)   (((x)<<0) & PHY_M_LEDC_STA0_MSK)
#define GM_GPCR_SPEED_1000   (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
#define GM_GPCR_AU_ALL_DIS   (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
#define TX_COL_THR(x)   (((x)<<10) & GM_TXCR_COL_THR_MSK)
#define TX_COL_DEF   0x04
#define TX_JAM_LEN_VAL(x)   (((x)<<14) & GM_TXPA_JAMLEN_MSK)
#define TX_JAM_IPG_VAL(x)   (((x)<<9) & GM_TXPA_JAMIPG_MSK)
#define TX_IPG_JAM_DATA(x)   (((x)<<4) & GM_TXPA_JAMDAT_MSK)
#define TX_BACK_OFF_LIM(x)   ((x) & GM_TXPA_BO_LIM_MSK)
#define DATA_BLIND_VAL(x)   (((x)<<11) & GM_SMOD_DATABL_MSK)
#define DATA_BLIND_DEF   0x04
#define IPG_DATA_VAL(x)   (x & GM_SMOD_IPG_MSK)
#define IPG_DATA_DEF   0x1e
#define GM_SMI_CT_PHY_AD(x)   (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
#define GM_SMI_CT_REG_AD(x)   (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
#define GMAC_DEF_MSK   GM_IS_TX_FF_UR
#define SKY2_HW_USE_MSI   0x00000001
#define SKY2_HW_FIBRE_PHY   0x00000002
#define SKY2_HW_GIGABIT   0x00000004
#define SKY2_HW_NEWER_PHY   0x00000008
#define SKY2_HW_RAM_BUFFER   0x00000010
#define SKY2_HW_NEW_LE   0x00000020
#define SKY2_HW_AUTO_TX_SUM   0x00000040
#define SKY2_HW_ADV_POWER_CTL   0x00000080
#define SK_GMAC_REG(port, reg)   (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
#define GM_PHY_RETRIES   100

Enumerations

enum  {
  PCI_DEV_REG1 = 0x40, PCI_DEV_REG2 = 0x44, PCI_DEV_STATUS = 0x7c, PCI_DEV_REG3 = 0x80,
  PCI_DEV_REG4 = 0x84, PCI_DEV_REG5 = 0x88, PCI_CFG_REG_0 = 0x90, PCI_CFG_REG_1 = 0x94
}
enum  pci_dev_reg_1 {
  PCI_Y2_PIG_ENA = 1<<31, PCI_Y2_DLL_DIS = 1<<30, PCI_SW_PWR_ON_RST = 1<<30, PCI_Y2_PHY2_COMA = 1<<29,
  PCI_Y2_PHY1_COMA = 1<<28, PCI_Y2_PHY2_POWD = 1<<27, PCI_Y2_PHY1_POWD = 1<<26, PCI_Y2_PME_LEGACY = 1<<15,
  PCI_PHY_LNK_TIM_MSK = 3L<<8, PCI_ENA_L1_EVENT = 1<<7, PCI_ENA_GPHY_LNK = 1<<6, PCI_FORCE_PEX_L1 = 1<<5
}
enum  pci_dev_reg_2 {
  PCI_VPD_WR_THR = 0xffL<<24, PCI_DEV_SEL = 0x7fL<<17, PCI_VPD_ROM_SZ = 7L<<14, PCI_PATCH_DIR = 0xfL<<8,
  PCI_EXT_PATCHS = 0xfL<<4, PCI_EN_DUMMY_RD = 1<<3, PCI_REV_DESC = 1<<2, PCI_USEDATA64 = 1<<0
}
enum  pci_dev_reg_4 {
  P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, P_PEX_LTSSM_STAT, P_PEX_LTSSM_DET_STAT = 0x01, P_TIMER_VALUE_MSK = 0xffL<<16,
  P_FORCE_ASPM_REQUEST = 1<<15, P_ASPM_GPHY_LINK_DOWN = 1<<14, P_ASPM_INT_FIFO_EMPTY = 1<<13, P_ASPM_CLKRUN_REQUEST = 1<<12,
  P_ASPM_FORCE_CLKREQ_ENA = 1<<4, P_ASPM_CLKREQ_PAD_CTL = 1<<3, P_ASPM_A1_MODE_SELECT = 1<<2, P_CLK_GATE_PEX_UNIT_ENA = 1<<1,
  P_CLK_GATE_ROOT_COR_ENA = 1<<0, P_ASPM_CONTROL_MSK
}
enum  pci_dev_reg_5 {
  P_CTL_DIV_CORE_CLK_ENA = 1<<31, P_CTL_SRESET_VMAIN_AV = 1<<30, P_CTL_BYPASS_VMAIN_AV = 1<<29, P_CTL_TIM_VMAIN_AV_MSK = 3<<27,
  P_REL_PCIE_RST_DE_ASS = 1<<26, P_REL_GPHY_REC_PACKET = 1<<25, P_REL_INT_FIFO_N_EMPTY = 1<<24, P_REL_MAIN_PWR_AVAIL = 1<<23,
  P_REL_CLKRUN_REQ_REL = 1<<22, P_REL_PCIE_RESET_ASS = 1<<21, P_REL_PME_ASSERTED = 1<<20, P_REL_PCIE_EXIT_L1_ST = 1<<19,
  P_REL_LOADER_NOT_FIN = 1<<18, P_REL_PCIE_RX_EX_IDLE = 1<<17, P_REL_GPHY_LINK_UP = 1<<16, P_GAT_PCIE_RST_ASSERTED = 1<<10,
  P_GAT_GPHY_N_REC_PACKET = 1<<9, P_GAT_INT_FIFO_EMPTY = 1<<8, P_GAT_MAIN_PWR_N_AVAIL = 1<<7, P_GAT_CLKRUN_REQ_REL = 1<<6,
  P_GAT_PCIE_RESET_ASS = 1<<5, P_GAT_PME_DE_ASSERTED = 1<<4, P_GAT_PCIE_ENTER_L1_ST = 1<<3, P_GAT_LOADER_FINISHED = 1<<2,
  P_GAT_PCIE_RX_EL_IDLE = 1<<1, P_GAT_GPHY_LINK_DOWN = 1<<0, PCIE_OUR5_EVENT_CLK_D3_SET
}
enum  pci_cfg_reg1 {
  P_CF1_DIS_REL_EVT_RST = 1<<24, P_CF1_REL_LDR_NOT_FIN = 1<<23, P_CF1_REL_VMAIN_AVLBL = 1<<22, P_CF1_REL_PCIE_RESET = 1<<21,
  P_CF1_GAT_LDR_NOT_FIN = 1<<20, P_CF1_GAT_PCIE_RX_IDLE = 1<<19, P_CF1_GAT_PCIE_RESET = 1<<18, P_CF1_PRST_PHY_CLKREQ = 1<<17,
  P_CF1_PCIE_RST_CLKREQ = 1<<16, P_CF1_ENA_CFG_LDR_DONE = 1<<8, P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, P_CF1_ENA_TXBMU_WR_IDLE = 1<<0,
  PCIE_CFG1_EVENT_CLK_D3_SET
}
enum  csr_regs {
  B0_RAP = 0x0000, B0_CTST = 0x0004, B0_LED = 0x0006, B0_POWER_CTRL = 0x0007,
  B0_ISRC = 0x0008, B0_IMSK = 0x000c, B0_HWE_ISRC = 0x0010, B0_HWE_IMSK = 0x0014,
  B0_SP_ISRC = 0x0018, B0_XM1_IMSK = 0x0020, B0_XM1_ISRC = 0x0028, B0_XM1_PHY_ADDR = 0x0030,
  B0_XM1_PHY_DATA = 0x0034, B0_XM2_IMSK = 0x0040, B0_XM2_ISRC = 0x0048, B0_XM2_PHY_ADDR = 0x0050,
  B0_XM2_PHY_DATA = 0x0054, B0_R1_CSR = 0x0060, B0_R2_CSR = 0x0064, B0_XS1_CSR = 0x0068,
  B0_XA1_CSR = 0x006c, B0_XS2_CSR = 0x0070, B0_XA2_CSR = 0x0074, B2_MAC_1 = 0x0100,
  B2_MAC_2 = 0x0108, B2_MAC_3 = 0x0110, B2_CONN_TYP = 0x0118, B2_PMD_TYP = 0x0119,
  B2_MAC_CFG = 0x011a, B2_CHIP_ID = 0x011b, B2_E_0 = 0x011c, B2_E_1 = 0x011d,
  B2_E_2 = 0x011e, B2_E_3 = 0x011f, B2_FAR = 0x0120, B2_FDP = 0x0124,
  B2_LD_CTRL = 0x0128, B2_LD_TEST = 0x0129, B2_TI_INI = 0x0130, B2_TI_VAL = 0x0134,
  B2_TI_CTRL = 0x0138, B2_TI_TEST = 0x0139, B2_IRQM_INI = 0x0140, B2_IRQM_VAL = 0x0144,
  B2_IRQM_CTRL = 0x0148, B2_IRQM_TEST = 0x0149, B2_IRQM_MSK = 0x014c, B2_IRQM_HWE_MSK = 0x0150,
  B2_TST_CTRL1 = 0x0158, B2_TST_CTRL2 = 0x0159, B2_GP_IO = 0x015c, B2_I2C_CTRL = 0x0160,
  B2_I2C_DATA = 0x0164, B2_I2C_IRQ = 0x0168, B2_I2C_SW = 0x016c, B2_BSC_INI = 0x0170,
  B2_BSC_VAL = 0x0174, B2_BSC_CTRL = 0x0178, B2_BSC_STAT = 0x0179, B2_BSC_TST = 0x017a,
  B3_RAM_ADDR = 0x0180, B3_RAM_DATA_LO = 0x0184, B3_RAM_DATA_HI = 0x0188, B3_RI_WTO_R1 = 0x0190,
  B3_RI_WTO_XA1 = 0x0191, B3_RI_WTO_XS1 = 0x0192, B3_RI_RTO_R1 = 0x0193, B3_RI_RTO_XA1 = 0x0194,
  B3_RI_RTO_XS1 = 0x0195, B3_RI_WTO_R2 = 0x0196, B3_RI_WTO_XA2 = 0x0197, B3_RI_WTO_XS2 = 0x0198,
  B3_RI_RTO_R2 = 0x0199, B3_RI_RTO_XA2 = 0x019a, B3_RI_RTO_XS2 = 0x019b, B3_RI_TO_VAL = 0x019c,
  B3_RI_CTRL = 0x01a0, B3_RI_TEST = 0x01a2, B3_MA_TOINI_RX1 = 0x01b0, B3_MA_TOINI_RX2 = 0x01b1,
  B3_MA_TOINI_TX1 = 0x01b2, B3_MA_TOINI_TX2 = 0x01b3, B3_MA_TOVAL_RX1 = 0x01b4, B3_MA_TOVAL_RX2 = 0x01b5,
  B3_MA_TOVAL_TX1 = 0x01b6, B3_MA_TOVAL_TX2 = 0x01b7, B3_MA_TO_CTRL = 0x01b8, B3_MA_TO_TEST = 0x01ba,
  B3_MA_RCINI_RX1 = 0x01c0, B3_MA_RCINI_RX2 = 0x01c1, B3_MA_RCINI_TX1 = 0x01c2, B3_MA_RCINI_TX2 = 0x01c3,
  B3_MA_RCVAL_RX1 = 0x01c4, B3_MA_RCVAL_RX2 = 0x01c5, B3_MA_RCVAL_TX1 = 0x01c6, B3_MA_RCVAL_TX2 = 0x01c7,
  B3_MA_RC_CTRL = 0x01c8, B3_MA_RC_TEST = 0x01ca, B3_PA_TOINI_RX1 = 0x01d0, B3_PA_TOINI_RX2 = 0x01d4,
  B3_PA_TOINI_TX1 = 0x01d8, B3_PA_TOINI_TX2 = 0x01dc, B3_PA_TOVAL_RX1 = 0x01e0, B3_PA_TOVAL_RX2 = 0x01e4,
  B3_PA_TOVAL_TX1 = 0x01e8, B3_PA_TOVAL_TX2 = 0x01ec, B3_PA_CTRL = 0x01f0, B3_PA_TEST = 0x01f2,
  B0_RAP = 0x0000, B0_CTST = 0x0004, B0_Y2LED = 0x0005, B0_POWER_CTRL = 0x0007,
  B0_ISRC = 0x0008, B0_IMSK = 0x000c, B0_HWE_ISRC = 0x0010, B0_HWE_IMSK = 0x0014,
  B0_Y2_SP_ISRC2 = 0x001c, B0_Y2_SP_ISRC3 = 0x0020, B0_Y2_SP_EISR = 0x0024, B0_Y2_SP_LISR = 0x0028,
  B0_Y2_SP_ICR = 0x002c, B2_MAC_1 = 0x0100, B2_MAC_2 = 0x0108, B2_MAC_3 = 0x0110,
  B2_CONN_TYP = 0x0118, B2_PMD_TYP = 0x0119, B2_MAC_CFG = 0x011a, B2_CHIP_ID = 0x011b,
  B2_E_0 = 0x011c, B2_Y2_CLK_GATE = 0x011d, B2_Y2_HW_RES = 0x011e, B2_E_3 = 0x011f,
  B2_Y2_CLK_CTRL = 0x0120, B2_TI_INI = 0x0130, B2_TI_VAL = 0x0134, B2_TI_CTRL = 0x0138,
  B2_TI_TEST = 0x0139, B2_TST_CTRL1 = 0x0158, B2_TST_CTRL2 = 0x0159, B2_GP_IO = 0x015c,
  B2_I2C_CTRL = 0x0160, B2_I2C_DATA = 0x0164, B2_I2C_IRQ = 0x0168, B2_I2C_SW = 0x016c,
  B3_RAM_ADDR = 0x0180, B3_RAM_DATA_LO = 0x0184, B3_RAM_DATA_HI = 0x0188, RAM_BUFFER,
  B3_RI_WTO_XA1 = 0x0191, B3_RI_WTO_XS1 = 0x0192, B3_RI_RTO_R1 = 0x0193, B3_RI_RTO_XA1 = 0x0194,
  B3_RI_RTO_XS1 = 0x0195, B3_RI_WTO_R2 = 0x0196, B3_RI_WTO_XA2 = 0x0197, B3_RI_WTO_XS2 = 0x0198,
  B3_RI_RTO_R2 = 0x0199, B3_RI_RTO_XA2 = 0x019a, B3_RI_RTO_XS2 = 0x019b, B3_RI_TO_VAL = 0x019c,
  B3_RI_CTRL = 0x01a0, B3_RI_TEST = 0x01a2, B3_MA_TOINI_RX1 = 0x01b0, B3_MA_TOINI_RX2 = 0x01b1,
  B3_MA_TOINI_TX1 = 0x01b2, B3_MA_TOINI_TX2 = 0x01b3, B3_MA_TOVAL_RX1 = 0x01b4, B3_MA_TOVAL_RX2 = 0x01b5,
  B3_MA_TOVAL_TX1 = 0x01b6, B3_MA_TOVAL_TX2 = 0x01b7, B3_MA_TO_CTRL = 0x01b8, B3_MA_TO_TEST = 0x01ba,
  B3_MA_RCINI_RX1 = 0x01c0, B3_MA_RCINI_RX2 = 0x01c1, B3_MA_RCINI_TX1 = 0x01c2, B3_MA_RCINI_TX2 = 0x01c3,
  B3_MA_RCVAL_RX1 = 0x01c4, B3_MA_RCVAL_RX2 = 0x01c5, B3_MA_RCVAL_TX1 = 0x01c6, B3_MA_RCVAL_TX2 = 0x01c7,
  B3_MA_RC_CTRL = 0x01c8, B3_MA_RC_TEST = 0x01ca, B3_PA_TOINI_RX1 = 0x01d0, B3_PA_TOINI_RX2 = 0x01d4,
  B3_PA_TOINI_TX1 = 0x01d8, B3_PA_TOINI_TX2 = 0x01dc, B3_PA_TOVAL_RX1 = 0x01e0, B3_PA_TOVAL_RX2 = 0x01e4,
  B3_PA_TOVAL_TX1 = 0x01e8, B3_PA_TOVAL_TX2 = 0x01ec, B3_PA_CTRL = 0x01f0, B3_PA_TEST = 0x01f2,
  Y2_CFG_SPC = 0x1c00, Y2_CFG_AER = 0x1d00
}
enum  {
  Y2_VMAIN_AVAIL = 1<<17, Y2_VAUX_AVAIL = 1<<16, Y2_HW_WOL_ON = 1<<15, Y2_HW_WOL_OFF = 1<<14,
  Y2_ASF_ENABLE = 1<<13, Y2_ASF_DISABLE = 1<<12, Y2_CLK_RUN_ENA = 1<<11, Y2_CLK_RUN_DIS = 1<<10,
  Y2_LED_STAT_ON = 1<<9, Y2_LED_STAT_OFF = 1<<8, CS_ST_SW_IRQ = 1<<7, CS_CL_SW_IRQ = 1<<6,
  CS_STOP_DONE = 1<<5, CS_STOP_MAST = 1<<4, CS_MRST_CLR = 1<<3, CS_MRST_SET = 1<<2,
  CS_RST_CLR = 1<<1, CS_RST_SET = 1
}
enum  { LED_STAT_ON = 1<<1, LED_STAT_OFF = 1 }
enum  {
  PC_VAUX_ENA = 1<<7, PC_VAUX_DIS = 1<<6, PC_VCC_ENA = 1<<5, PC_VCC_DIS = 1<<4,
  PC_VAUX_ON = 1<<3, PC_VAUX_OFF = 1<<2, PC_VCC_ON = 1<<1, PC_VCC_OFF = 1<<0
}
enum  {
  Y2_IS_HW_ERR = 1<<31, Y2_IS_STAT_BMU = 1<<30, Y2_IS_ASF = 1<<29, Y2_IS_POLL_CHK = 1<<27,
  Y2_IS_TWSI_RDY = 1<<26, Y2_IS_IRQ_SW = 1<<25, Y2_IS_TIMINT = 1<<24, Y2_IS_IRQ_PHY2 = 1<<12,
  Y2_IS_IRQ_MAC2 = 1<<11, Y2_IS_CHK_RX2 = 1<<10, Y2_IS_CHK_TXS2 = 1<<9, Y2_IS_CHK_TXA2 = 1<<8,
  Y2_IS_IRQ_PHY1 = 1<<4, Y2_IS_IRQ_MAC1 = 1<<3, Y2_IS_CHK_RX1 = 1<<2, Y2_IS_CHK_TXS1 = 1<<1,
  Y2_IS_CHK_TXA1 = 1<<0, Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU, Y2_IS_PORT_1, Y2_IS_PORT_2,
  Y2_IS_ERROR
}
enum  {
  IS_ERR_MSK = 0x00003fff, IS_IRQ_TIST_OV = 1<<13, IS_IRQ_SENSOR = 1<<12, IS_IRQ_MST_ERR = 1<<11,
  IS_IRQ_STAT = 1<<10, IS_NO_STAT_M1 = 1<<9, IS_NO_STAT_M2 = 1<<8, IS_NO_TIST_M1 = 1<<7,
  IS_NO_TIST_M2 = 1<<6, IS_RAM_RD_PAR = 1<<5, IS_RAM_WR_PAR = 1<<4, IS_M1_PAR_ERR = 1<<3,
  IS_M2_PAR_ERR = 1<<2, IS_R1_PAR_ERR = 1<<1, IS_R2_PAR_ERR = 1<<0
}
enum  {
  Y2_IS_TIST_OV = 1<<29, Y2_IS_SENSOR = 1<<28, Y2_IS_MST_ERR = 1<<27, Y2_IS_IRQ_STAT = 1<<26,
  Y2_IS_PCI_EXP = 1<<25, Y2_IS_PCI_NEXP = 1<<24, Y2_IS_PAR_RD2 = 1<<13, Y2_IS_PAR_WR2 = 1<<12,
  Y2_IS_PAR_MAC2 = 1<<11, Y2_IS_PAR_RX2 = 1<<10, Y2_IS_TCP_TXS2 = 1<<9, Y2_IS_TCP_TXA2 = 1<<8,
  Y2_IS_PAR_RD1 = 1<<5, Y2_IS_PAR_WR1 = 1<<4, Y2_IS_PAR_MAC1 = 1<<3, Y2_IS_PAR_RX1 = 1<<2,
  Y2_IS_TCP_TXS1 = 1<<1, Y2_IS_TCP_TXA1 = 1<<0, Y2_HWE_L1_MASK, Y2_HWE_L2_MASK,
  Y2_HWE_ALL_MASK
}
enum  { DPT_START = 1<<1, DPT_STOP = 1<<0 }
enum  {
  TST_FRC_DPERR_MR = 1<<7, TST_FRC_DPERR_MW = 1<<6, TST_FRC_DPERR_TR = 1<<5, TST_FRC_DPERR_TW = 1<<4,
  TST_FRC_APERR_M = 1<<3, TST_FRC_APERR_T = 1<<2, TST_CFG_WRITE_ON = 1<<1, TST_CFG_WRITE_OFF = 1<<0
}
enum  {
  GLB_GPIO_CLK_DEB_ENA = 1<<31, GLB_GPIO_CLK_DBG_MSK = 0xf<<26, GLB_GPIO_INT_RST_D3_DIS = 1<<15, GLB_GPIO_LED_PAD_SPEED_UP = 1<<14,
  GLB_GPIO_STAT_RACE_DIS = 1<<13, GLB_GPIO_TEST_SEL_MSK = 3<<11, GLB_GPIO_TEST_SEL_BASE = 1<<11, GLB_GPIO_RAND_ENA = 1<<10,
  GLB_GPIO_RAND_BIT_1 = 1<<9
}
enum  { CFG_CHIP_R_MSK = 0xf<<4, CFG_DIS_M2_CLK = 1<<1, CFG_SNG_MAC = 1<<0 }
enum  {
  CHIP_ID_YUKON_XL = 0xb3, CHIP_ID_YUKON_EC_U = 0xb4, CHIP_ID_YUKON_EX = 0xb5, CHIP_ID_YUKON_EC = 0xb6,
  CHIP_ID_YUKON_FE = 0xb7, CHIP_ID_YUKON_FE_P = 0xb8, CHIP_ID_YUKON_SUPR = 0xb9, CHIP_ID_YUKON_UL_2 = 0xba
}
enum  yukon_ec_rev { CHIP_REV_YU_EC_A1 = 0, CHIP_REV_YU_EC_A2 = 1, CHIP_REV_YU_EC_A3 = 2 }
enum  yukon_ec_u_rev { CHIP_REV_YU_EC_U_A0 = 1, CHIP_REV_YU_EC_U_A1 = 2, CHIP_REV_YU_EC_U_B0 = 3 }
enum  yukon_fe_rev { CHIP_REV_YU_FE_A1 = 1, CHIP_REV_YU_FE_A2 = 2 }
enum  yukon_fe_p_rev { CHIP_REV_YU_FE2_A0 = 0 }
enum  yukon_ex_rev { CHIP_REV_YU_EX_A0 = 1, CHIP_REV_YU_EX_B0 = 2 }
enum  yukon_supr_rev { CHIP_REV_YU_SU_A0 = 0 }
enum  {
  Y2_STATUS_LNK2_INAC = 1<<7, Y2_CLK_GAT_LNK2_DIS = 1<<6, Y2_COR_CLK_LNK2_DIS = 1<<5, Y2_PCI_CLK_LNK2_DIS = 1<<4,
  Y2_STATUS_LNK1_INAC = 1<<3, Y2_CLK_GAT_LNK1_DIS = 1<<2, Y2_COR_CLK_LNK1_DIS = 1<<1, Y2_PCI_CLK_LNK1_DIS = 1<<0
}
enum  { CFG_LED_MODE_MSK = 7<<2, CFG_LINK_2_AVAIL = 1<<1, CFG_LINK_1_AVAIL = 1<<0 }
enum  {
  Y2_CLK_DIV_VAL_MSK = 0xff<<16, Y2_CLK_DIV_VAL, Y2_CLK_SELECT2_MSK = 0x1f<<16, Y2_CLK_DIV_VAL_2,
  Y2_CLK_DIV_DIS = 1<<0
}
enum  { TIM_START = 1<<2, TIM_STOP = 1<<1, TIM_CLR_IRQ = 1<<0 }
enum  { TIM_T_ON = 1<<2, TIM_T_OFF = 1<<1, TIM_T_STEP = 1<<0 }
enum  { RI_CLR_RD_PERR = 1<<9, RI_CLR_WR_PERR = 1<<8, RI_RST_CLR = 1<<1, RI_RST_SET = 1<<0 }
enum  {
  TXA_ENA_FSYNC = 1<<7, TXA_DIS_FSYNC = 1<<6, TXA_ENA_ALLOC = 1<<5, TXA_DIS_ALLOC = 1<<4,
  TXA_START_RC = 1<<3, TXA_STOP_RC = 1<<2, TXA_ENA_ARB = 1<<1, TXA_DIS_ARB = 1<<0
}
enum  {
  TXA_ITI_INI = 0x0200, TXA_ITI_VAL = 0x0204, TXA_LIM_INI = 0x0208, TXA_LIM_VAL = 0x020c,
  TXA_CTRL = 0x0210, TXA_TEST = 0x0211, TXA_STAT = 0x0212
}
enum  {
  B6_EXT_REG = 0x0300, B7_CFG_SPC = 0x0380, B8_RQ1_REGS = 0x0400, B8_RQ2_REGS = 0x0480,
  B8_TS1_REGS = 0x0600, B8_TA1_REGS = 0x0680, B8_TS2_REGS = 0x0700, B8_TA2_REGS = 0x0780,
  B16_RAM_REGS = 0x0800
}
enum  {
  B8_Q_REGS = 0x0400, Q_D = 0x00, Q_VLAN = 0x20, Q_DONE = 0x24,
  Q_AC_L = 0x28, Q_AC_H = 0x2c, Q_BC = 0x30, Q_CSR = 0x34,
  Q_TEST = 0x38, Q_WM = 0x40, Q_AL = 0x42, Q_RSP = 0x44,
  Q_RSL = 0x46, Q_RP = 0x48, Q_RL = 0x4a, Q_WP = 0x4c,
  Q_WSP = 0x4d, Q_WL = 0x4e, Q_WSL = 0x4f
}
enum  { F_TX_CHK_AUTO_OFF = 1<<31, F_TX_CHK_AUTO_ON = 1<<30, F_M_RX_RAM_DIS = 1<<24 }
enum  {
  Y2_B8_PREF_REGS = 0x0450, PREF_UNIT_CTRL = 0x00, PREF_UNIT_LAST_IDX = 0x04, PREF_UNIT_ADDR_LO = 0x08,
  PREF_UNIT_ADDR_HI = 0x0c, PREF_UNIT_GET_IDX = 0x10, PREF_UNIT_PUT_IDX = 0x14, PREF_UNIT_FIFO_WP = 0x20,
  PREF_UNIT_FIFO_RP = 0x24, PREF_UNIT_FIFO_WM = 0x28, PREF_UNIT_FIFO_LEV = 0x2c, PREF_UNIT_MASK_IDX = 0x0fff
}
enum  {
  RB_START = 0x00, RB_END = 0x04, RB_WP = 0x08, RB_RP = 0x0c,
  RB_RX_UTPP = 0x10, RB_RX_LTPP = 0x14, RB_RX_UTHP = 0x18, RB_RX_LTHP = 0x1c,
  RB_PC = 0x20, RB_LEV = 0x24, RB_CTRL = 0x28, RB_TST1 = 0x29,
  RB_TST2 = 0x2a
}
enum  {
  Q_R1 = 0x0000, Q_R2 = 0x0080, Q_XS1 = 0x0200, Q_XA1 = 0x0280,
  Q_XS2 = 0x0300, Q_XA2 = 0x0380
}
enum  { PHY_ADDR_MARV = 0 }
enum  {
  LNK_SYNC_INI = 0x0c30, LNK_SYNC_VAL = 0x0c34, LNK_SYNC_CTRL = 0x0c38, LNK_SYNC_TST = 0x0c39,
  LNK_LED_REG = 0x0c3c, RX_GMF_EA = 0x0c40, RX_GMF_AF_THR = 0x0c44, RX_GMF_CTRL_T = 0x0c48,
  RX_GMF_FL_MSK = 0x0c4c, RX_GMF_FL_THR = 0x0c50, RX_GMF_TR_THR = 0x0c54, RX_GMF_UP_THR = 0x0c58,
  RX_GMF_LP_THR = 0x0c5a, RX_GMF_VLAN = 0x0c5c, RX_GMF_WP = 0x0c60, RX_GMF_WLEV = 0x0c68,
  RX_GMF_RP = 0x0c70, RX_GMF_RLEV = 0x0c78
}
enum  {
  BMU_IDLE = 1<<31, BMU_RX_TCP_PKT = 1<<30, BMU_RX_IP_PKT = 1<<29, BMU_ENA_RX_RSS_HASH = 1<<15,
  BMU_DIS_RX_RSS_HASH = 1<<14, BMU_ENA_RX_CHKSUM = 1<<13, BMU_DIS_RX_CHKSUM = 1<<12, BMU_CLR_IRQ_PAR = 1<<11,
  BMU_CLR_IRQ_TCP = 1<<11, BMU_CLR_IRQ_CHK = 1<<10, BMU_STOP = 1<<9, BMU_START = 1<<8,
  BMU_FIFO_OP_ON = 1<<7, BMU_FIFO_OP_OFF = 1<<6, BMU_FIFO_ENA = 1<<5, BMU_FIFO_RST = 1<<4,
  BMU_OP_ON = 1<<3, BMU_OP_OFF = 1<<2, BMU_RST_CLR = 1<<1, BMU_RST_SET = 1<<0,
  BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR, BMU_OPER_INIT, BMU_WM_DEFAULT = 0x600, BMU_WM_PEX = 0x80
}
enum  { BMU_TX_IPIDINCR_ON = 1<<13, BMU_TX_IPIDINCR_OFF = 1<<12, BMU_TX_CLR_IRQ_TCP = 1<<11 }
enum  { PREF_UNIT_OP_ON = 1<<3, PREF_UNIT_OP_OFF = 1<<2, PREF_UNIT_RST_CLR = 1<<1, PREF_UNIT_RST_SET = 1<<0 }
enum  {
  RB_ENA_STFWD = 1<<5, RB_DIS_STFWD = 1<<4, RB_ENA_OP_MD = 1<<3, RB_DIS_OP_MD = 1<<2,
  RB_RST_CLR = 1<<1, RB_RST_SET = 1<<0
}
enum  {
  TX_GMF_EA = 0x0d40, TX_GMF_AE_THR = 0x0d44, TX_GMF_CTRL_T = 0x0d48, TX_GMF_WP = 0x0d60,
  TX_GMF_WSP = 0x0d64, TX_GMF_WLEV = 0x0d68, TX_GMF_RP = 0x0d70, TX_GMF_RSTP = 0x0d74,
  TX_GMF_RLEV = 0x0d78, ECU_AE_THR = 0x0070, ECU_TXFF_LEV = 0x01a0, ECU_JUMBO_WM = 0x0080
}
enum  { B28_DPT_INI = 0x0e00, B28_DPT_VAL = 0x0e04, B28_DPT_CTRL = 0x0e08, B28_DPT_TST = 0x0e0a }
enum  { GMAC_TI_ST_VAL = 0x0e14, GMAC_TI_ST_CTRL = 0x0e18, GMAC_TI_ST_TST = 0x0e1a }
enum  { POLL_CTRL = 0x0e20, POLL_LAST_IDX = 0x0e24, POLL_LIST_ADDR_LO = 0x0e28, POLL_LIST_ADDR_HI = 0x0e2c }
enum  { SMB_CFG = 0x0e40, SMB_CSR = 0x0e44 }
enum  {
  CPU_WDOG = 0x0e48, CPU_CNTR = 0x0e4C, CPU_TIM = 0x0e50, CPU_AHB_ADDR = 0x0e54,
  CPU_AHB_WDATA = 0x0e58, CPU_AHB_RDATA = 0x0e5C, HCU_MAP_BASE = 0x0e60, CPU_AHB_CTRL = 0x0e64,
  HCU_CCSR = 0x0e68, HCU_HCSR = 0x0e6C
}
enum  {
  B28_Y2_SMB_CONFIG = 0x0e40, B28_Y2_SMB_CSD_REG = 0x0e44, B28_Y2_ASF_IRQ_V_BASE = 0x0e60, B28_Y2_ASF_STAT_CMD = 0x0e68,
  B28_Y2_ASF_HOST_COM = 0x0e6c, B28_Y2_DATA_REG_1 = 0x0e70, B28_Y2_DATA_REG_2 = 0x0e74, B28_Y2_DATA_REG_3 = 0x0e78,
  B28_Y2_DATA_REG_4 = 0x0e7c
}
enum  {
  STAT_CTRL = 0x0e80, STAT_LAST_IDX = 0x0e84, STAT_LIST_ADDR_LO = 0x0e88, STAT_LIST_ADDR_HI = 0x0e8c,
  STAT_TXA1_RIDX = 0x0e90, STAT_TXS1_RIDX = 0x0e92, STAT_TXA2_RIDX = 0x0e94, STAT_TXS2_RIDX = 0x0e96,
  STAT_TX_IDX_TH = 0x0e98, STAT_PUT_IDX = 0x0e9c, STAT_FIFO_WP = 0x0ea0, STAT_FIFO_RP = 0x0ea4,
  STAT_FIFO_RSP = 0x0ea6, STAT_FIFO_LEVEL = 0x0ea8, STAT_FIFO_SHLVL = 0x0eaa, STAT_FIFO_WM = 0x0eac,
  STAT_FIFO_ISR_WM = 0x0ead, STAT_LEV_TIMER_INI = 0x0eb0, STAT_LEV_TIMER_CNT = 0x0eb4, STAT_LEV_TIMER_CTRL = 0x0eb8,
  STAT_LEV_TIMER_TEST = 0x0eb9, STAT_TX_TIMER_INI = 0x0ec0, STAT_TX_TIMER_CNT = 0x0ec4, STAT_TX_TIMER_CTRL = 0x0ec8,
  STAT_TX_TIMER_TEST = 0x0ec9, STAT_ISR_TIMER_INI = 0x0ed0, STAT_ISR_TIMER_CNT = 0x0ed4, STAT_ISR_TIMER_CTRL = 0x0ed8,
  STAT_ISR_TIMER_TEST = 0x0ed9
}
enum  {
  LINKLED_OFF = 0x01, LINKLED_ON = 0x02, LINKLED_LINKSYNC_OFF = 0x04, LINKLED_LINKSYNC_ON = 0x08,
  LINKLED_BLINK_OFF = 0x10, LINKLED_BLINK_ON = 0x20
}
enum  {
  GMAC_CTRL = 0x0f00, GPHY_CTRL = 0x0f04, GMAC_IRQ_SRC = 0x0f08, GMAC_IRQ_MSK = 0x0f0c,
  GMAC_LINK_CTRL = 0x0f10, WOL_CTRL_STAT = 0x0f20, WOL_MATCH_CTL = 0x0f22, WOL_MATCH_RES = 0x0f23,
  WOL_MAC_ADDR = 0x0f24, WOL_PATT_RPTR = 0x0f2c, WOL_PATT_LEN_LO = 0x0f30, WOL_PATT_LEN_HI = 0x0f34,
  WOL_PATT_CNT_0 = 0x0f38, WOL_PATT_CNT_4 = 0x0f3c
}
enum  { WOL_PATT_RAM_1 = 0x1000, WOL_PATT_RAM_2 = 0x1400 }
enum  { BASE_GMAC_1 = 0x2800, BASE_GMAC_2 = 0x3800 }
enum  {
  PHY_MARV_CTRL = 0x00, PHY_MARV_STAT = 0x01, PHY_MARV_ID0 = 0x02, PHY_MARV_ID1 = 0x03,
  PHY_MARV_AUNE_ADV = 0x04, PHY_MARV_AUNE_LP = 0x05, PHY_MARV_AUNE_EXP = 0x06, PHY_MARV_NEPG = 0x07,
  PHY_MARV_NEPG_LP = 0x08, PHY_MARV_1000T_CTRL = 0x09, PHY_MARV_1000T_STAT = 0x0a, PHY_MARV_EXT_STAT = 0x0f,
  PHY_MARV_PHY_CTRL = 0x10, PHY_MARV_PHY_STAT = 0x11, PHY_MARV_INT_MASK = 0x12, PHY_MARV_INT_STAT = 0x13,
  PHY_MARV_EXT_CTRL = 0x14, PHY_MARV_RXE_CNT = 0x15, PHY_MARV_EXT_ADR = 0x16, PHY_MARV_PORT_IRQ = 0x17,
  PHY_MARV_LED_CTRL = 0x18, PHY_MARV_LED_OVER = 0x19, PHY_MARV_EXT_CTRL_2 = 0x1a, PHY_MARV_EXT_P_STAT = 0x1b,
  PHY_MARV_CABLE_DIAG = 0x1c, PHY_MARV_PAGE_ADDR = 0x1d, PHY_MARV_PAGE_DATA = 0x1e, PHY_MARV_FE_LED_PAR = 0x16,
  PHY_MARV_FE_LED_SER = 0x17, PHY_MARV_FE_VCT_TX = 0x1a, PHY_MARV_FE_VCT_RX = 0x1b, PHY_MARV_FE_SPEC_2 = 0x1c
}
enum  {
  PHY_CT_RESET = 1<<15, PHY_CT_LOOP = 1<<14, PHY_CT_SPS_LSB = 1<<13, PHY_CT_ANE = 1<<12,
  PHY_CT_PDOWN = 1<<11, PHY_CT_ISOL = 1<<10, PHY_CT_RE_CFG = 1<<9, PHY_CT_DUP_MD = 1<<8,
  PHY_CT_COL_TST = 1<<7, PHY_CT_SPS_MSB = 1<<6
}
enum  { PHY_CT_SP1000 = PHY_CT_SPS_MSB, PHY_CT_SP100 = PHY_CT_SPS_LSB, PHY_CT_SP10 = 0 }
enum  {
  PHY_ST_EXT_ST = 1<<8, PHY_ST_PRE_SUP = 1<<6, PHY_ST_AN_OVER = 1<<5, PHY_ST_REM_FLT = 1<<4,
  PHY_ST_AN_CAP = 1<<3, PHY_ST_LSYNC = 1<<2, PHY_ST_JAB_DET = 1<<1, PHY_ST_EXT_REG = 1<<0
}
enum  { PHY_I1_OUI_MSK = 0x3f<<10, PHY_I1_MOD_NUM = 0x3f<<4, PHY_I1_REV_MSK = 0xf }
enum  {
  PHY_MARV_ID0_VAL = 0x0141, PHY_BCOM_ID1_A1 = 0x6041, PHY_BCOM_ID1_B2 = 0x6043, PHY_BCOM_ID1_C0 = 0x6044,
  PHY_BCOM_ID1_C5 = 0x6047, PHY_MARV_ID1_B0 = 0x0C23, PHY_MARV_ID1_B2 = 0x0C25, PHY_MARV_ID1_C2 = 0x0CC2,
  PHY_MARV_ID1_Y2 = 0x0C91, PHY_MARV_ID1_FE = 0x0C83, PHY_MARV_ID1_ECU = 0x0CB0
}
enum  {
  PHY_AN_NXT_PG = 1<<15, PHY_AN_ACK = 1<<14, PHY_AN_RF = 1<<13, PHY_AN_PAUSE_ASYM = 1<<11,
  PHY_AN_PAUSE_CAP = 1<<10, PHY_AN_100BASE4 = 1<<9, PHY_AN_100FULL = 1<<8, PHY_AN_100HALF = 1<<7,
  PHY_AN_10FULL = 1<<6, PHY_AN_10HALF = 1<<5, PHY_AN_CSMA = 1<<0, PHY_AN_SEL = 0x1f,
  PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA, PHY_AN_ALL
}
enum  {
  PHY_B_1000S_MSF = 1<<15, PHY_B_1000S_MSR = 1<<14, PHY_B_1000S_LRS = 1<<13, PHY_B_1000S_RRS = 1<<12,
  PHY_B_1000S_LP_FD = 1<<11, PHY_B_1000S_LP_HD = 1<<10, PHY_B_1000S_IEC = 0xff
}
enum  {
  PHY_M_AN_NXT_PG = 1<<15, PHY_M_AN_ACK = 1<<14, PHY_M_AN_RF = 1<<13, PHY_M_AN_ASP = 1<<11,
  PHY_M_AN_PC = 1<<10, PHY_M_AN_100_T4 = 1<<9, PHY_M_AN_100_FD = 1<<8, PHY_M_AN_100_HD = 1<<7,
  PHY_M_AN_10_FD = 1<<6, PHY_M_AN_10_HD = 1<<5, PHY_M_AN_SEL_MSK = 0x1f<<4
}
 Marvell-Specific. More...
enum  { PHY_M_AN_ASP_X = 1<<8, PHY_M_AN_PC_X = 1<<7, PHY_M_AN_1000X_AHD = 1<<6, PHY_M_AN_1000X_AFD = 1<<5 }
enum  { PHY_M_P_NO_PAUSE_X = 0<<7, PHY_M_P_SYM_MD_X = 1<<7, PHY_M_P_ASYM_MD_X = 2<<7, PHY_M_P_BOTH_MD_X = 3<<7 }
enum  {
  PHY_M_1000C_TEST = 7<<13, PHY_M_1000C_MSE = 1<<12, PHY_M_1000C_MSC = 1<<11, PHY_M_1000C_MPD = 1<<10,
  PHY_M_1000C_AFD = 1<<9, PHY_M_1000C_AHD = 1<<8
}
enum  {
  PHY_M_PC_TX_FFD_MSK = 3<<14, PHY_M_PC_RX_FFD_MSK = 3<<12, PHY_M_PC_ASS_CRS_TX = 1<<11, PHY_M_PC_FL_GOOD = 1<<10,
  PHY_M_PC_EN_DET_MSK = 3<<8, PHY_M_PC_ENA_EXT_D = 1<<7, PHY_M_PC_MDIX_MSK = 3<<5, PHY_M_PC_DIS_125CLK = 1<<4,
  PHY_M_PC_MAC_POW_UP = 1<<3, PHY_M_PC_SQE_T_ENA = 1<<2, PHY_M_PC_POL_R_DIS = 1<<1, PHY_M_PC_DIS_JABBER = 1<<0
}
enum  { PHY_M_PC_EN_DET = 2<<8, PHY_M_PC_EN_DET_PLUS = 3<<8 }
enum  { PHY_M_PC_MAN_MDI = 0, PHY_M_PC_MAN_MDIX = 1, PHY_M_PC_ENA_AUTO = 3 }
enum  { PHY_M_PC_COP_TX_DIS = 1<<3, PHY_M_PC_POW_D_ENA = 1<<2 }
enum  {
  PHY_M_PC_ENA_DTE_DT = 1<<15, PHY_M_PC_ENA_ENE_DT = 1<<14, PHY_M_PC_DIS_NLP_CK = 1<<13, PHY_M_PC_ENA_LIP_NP = 1<<12,
  PHY_M_PC_DIS_NLP_GN = 1<<11, PHY_M_PC_DIS_SCRAMB = 1<<9, PHY_M_PC_DIS_FEFI = 1<<8, PHY_M_PC_SH_TP_SEL = 1<<6,
  PHY_M_PC_RX_FD_MSK = 3<<2
}
enum  {
  PHY_M_PS_SPEED_MSK = 3<<14, PHY_M_PS_SPEED_1000 = 1<<15, PHY_M_PS_SPEED_100 = 1<<14, PHY_M_PS_SPEED_10 = 0,
  PHY_M_PS_FULL_DUP = 1<<13, PHY_M_PS_PAGE_REC = 1<<12, PHY_M_PS_SPDUP_RES = 1<<11, PHY_M_PS_LINK_UP = 1<<10,
  PHY_M_PS_CABLE_MSK = 7<<7, PHY_M_PS_MDI_X_STAT = 1<<6, PHY_M_PS_DOWNS_STAT = 1<<5, PHY_M_PS_ENDET_STAT = 1<<4,
  PHY_M_PS_TX_P_EN = 1<<3, PHY_M_PS_RX_P_EN = 1<<2, PHY_M_PS_POL_REV = 1<<1, PHY_M_PS_JABBER = 1<<0
}
enum  { PHY_M_PS_DTE_DETECT = 1<<15, PHY_M_PS_RES_SPEED = 1<<14 }
enum  {
  PHY_M_IS_AN_ERROR = 1<<15, PHY_M_IS_LSP_CHANGE = 1<<14, PHY_M_IS_DUP_CHANGE = 1<<13, PHY_M_IS_AN_PR = 1<<12,
  PHY_M_IS_AN_COMPL = 1<<11, PHY_M_IS_LST_CHANGE = 1<<10, PHY_M_IS_SYMB_ERROR = 1<<9, PHY_M_IS_FALSE_CARR = 1<<8,
  PHY_M_IS_FIFO_ERROR = 1<<7, PHY_M_IS_MDI_CHANGE = 1<<6, PHY_M_IS_DOWNSH_DET = 1<<5, PHY_M_IS_END_CHANGE = 1<<4,
  PHY_M_IS_DTE_CHANGE = 1<<2, PHY_M_IS_POL_CHANGE = 1<<1, PHY_M_IS_JABBER = 1<<0, PHY_M_DEF_MSK,
  PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL
}
enum  {
  PHY_M_EC_ENA_BC_EXT = 1<<15, PHY_M_EC_ENA_LIN_LB = 1<<14, PHY_M_EC_DIS_LINK_P = 1<<12, PHY_M_EC_M_DSC_MSK = 3<<10,
  PHY_M_EC_S_DSC_MSK = 3<<8, PHY_M_EC_M_DSC_MSK2 = 7<<9, PHY_M_EC_DOWN_S_ENA = 1<<8, PHY_M_EC_RX_TIM_CT = 1<<7,
  PHY_M_EC_MAC_S_MSK = 7<<4, PHY_M_EC_FIB_AN_ENA = 1<<3, PHY_M_EC_DTE_D_ENA = 1<<2, PHY_M_EC_TX_TIM_CT = 1<<1,
  PHY_M_EC_TRANS_DIS = 1<<0
}
enum  { PHY_M_PC_DIS_LINK_Pa = 1<<15, PHY_M_PC_DSC_MSK = 7<<12, PHY_M_PC_DOWN_S_ENA = 1<<11 }
enum  { MAC_TX_CLK_0_MHZ = 2, MAC_TX_CLK_2_5_MHZ = 6, MAC_TX_CLK_25_MHZ = 7 }
enum  {
  PHY_M_LEDC_DIS_LED = 1<<15, PHY_M_LEDC_PULS_MSK = 7<<12, PHY_M_LEDC_F_INT = 1<<11, PHY_M_LEDC_BL_R_MSK = 7<<8,
  PHY_M_LEDC_DP_C_LSB = 1<<7, PHY_M_LEDC_TX_C_LSB = 1<<6, PHY_M_LEDC_LK_C_MSK = 7<<3
}
enum  {
  PHY_M_LEDC_LINK_MSK = 3<<3, PHY_M_LEDC_DP_CTRL = 1<<2, PHY_M_LEDC_DP_C_MSB = 1<<2, PHY_M_LEDC_RX_CTRL = 1<<1,
  PHY_M_LEDC_TX_CTRL = 1<<0, PHY_M_LEDC_TX_C_MSB = 1<<0
}
enum  {
  PHY_M_POLC_LS1M_MSK = 0xf<<12, PHY_M_POLC_IS0M_MSK = 0xf<<8, PHY_M_POLC_LOS_MSK = 0x3<<6, PHY_M_POLC_INIT_MSK = 0x3<<4,
  PHY_M_POLC_STA1_MSK = 0x3<<2, PHY_M_POLC_STA0_MSK = 0x3
}
enum  {
  PULS_NO_STR = 0, PULS_21MS = 1, PULS_42MS = 2, PULS_84MS = 3,
  PULS_170MS = 4, PULS_340MS = 5, PULS_670MS = 6, PULS_1300MS = 7
}
enum  {
  BLINK_42MS = 0, BLINK_84MS = 1, BLINK_170MS = 2, BLINK_340MS = 3,
  BLINK_670MS = 4
}
enum  led_mode {
  LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST, MO_LED_NORM = 0,
  MO_LED_BLINK = 1, MO_LED_OFF = 2, MO_LED_ON = 3
}
enum  {
  PHY_M_EC2_FI_IMPED = 1<<6, PHY_M_EC2_FO_IMPED = 1<<5, PHY_M_EC2_FO_M_CLK = 1<<4, PHY_M_EC2_FO_BOOST = 1<<3,
  PHY_M_EC2_FO_AM_MSK = 7
}
enum  {
  PHY_M_FC_AUTO_SEL = 1<<15, PHY_M_FC_AN_REG_ACC = 1<<14, PHY_M_FC_RESOLUTION = 1<<13, PHY_M_SER_IF_AN_BP = 1<<12,
  PHY_M_SER_IF_BP_ST = 1<<11, PHY_M_IRQ_POLARITY = 1<<10, PHY_M_DIS_AUT_MED = 1<<9, PHY_M_UNDOC1 = 1<<7,
  PHY_M_DTE_POW_STAT = 1<<4, PHY_M_MODE_MASK = 0xf
}
enum  { PHY_M_FELP_LED2_MSK = 0xf<<8, PHY_M_FELP_LED1_MSK = 0xf<<4, PHY_M_FELP_LED0_MSK = 0xf }
enum  {
  LED_PAR_CTRL_COLX = 0x00, LED_PAR_CTRL_ERROR = 0x01, LED_PAR_CTRL_DUPLEX = 0x02, LED_PAR_CTRL_DP_COL = 0x03,
  LED_PAR_CTRL_SPEED = 0x04, LED_PAR_CTRL_LINK = 0x05, LED_PAR_CTRL_TX = 0x06, LED_PAR_CTRL_RX = 0x07,
  LED_PAR_CTRL_ACT = 0x08, LED_PAR_CTRL_LNK_RX = 0x09, LED_PAR_CTRL_LNK_AC = 0x0a, LED_PAR_CTRL_ACT_BL = 0x0b,
  LED_PAR_CTRL_TX_BL = 0x0c, LED_PAR_CTRL_RX_BL = 0x0d, LED_PAR_CTRL_COL_BL = 0x0e, LED_PAR_CTRL_INACT = 0x0f
}
enum  { PHY_M_FESC_DIS_WAIT = 1<<2, PHY_M_FESC_ENA_MCLK = 1<<1, PHY_M_FESC_SEL_CL_A = 1<<0 }
enum  { PHY_M_FIB_FORCE_LNK = 1<<10, PHY_M_FIB_SIGD_POL = 1<<9, PHY_M_FIB_TX_DIS = 1<<3 }
enum  {
  PHY_M_MAC_MD_MSK = 7<<7, PHY_M_MAC_GMIF_PUP = 1<<3, PHY_M_MAC_MD_AUTO = 3, PHY_M_MAC_MD_COPPER = 5,
  PHY_M_MAC_MD_1000BX = 7
}
enum  { PHY_M_LEDC_LOS_MSK = 0xf<<12, PHY_M_LEDC_INIT_MSK = 0xf<<8, PHY_M_LEDC_STA1_MSK = 0xf<<4, PHY_M_LEDC_STA0_MSK = 0xf }
enum  {
  GM_GP_STAT = 0x0000, GM_GP_CTRL = 0x0004, GM_TX_CTRL = 0x0008, GM_RX_CTRL = 0x000c,
  GM_TX_FLOW_CTRL = 0x0010, GM_TX_PARAM = 0x0014, GM_SERIAL_MODE = 0x0018, GM_SRC_ADDR_1L = 0x001c,
  GM_SRC_ADDR_1M = 0x0020, GM_SRC_ADDR_1H = 0x0024, GM_SRC_ADDR_2L = 0x0028, GM_SRC_ADDR_2M = 0x002c,
  GM_SRC_ADDR_2H = 0x0030, GM_MC_ADDR_H1 = 0x0034, GM_MC_ADDR_H2 = 0x0038, GM_MC_ADDR_H3 = 0x003c,
  GM_MC_ADDR_H4 = 0x0040, GM_TX_IRQ_SRC = 0x0044, GM_RX_IRQ_SRC = 0x0048, GM_TR_IRQ_SRC = 0x004c,
  GM_TX_IRQ_MSK = 0x0050, GM_RX_IRQ_MSK = 0x0054, GM_TR_IRQ_MSK = 0x0058, GM_SMI_CTRL = 0x0080,
  GM_SMI_DATA = 0x0084, GM_PHY_ADDR = 0x0088, GM_MIB_CNT_BASE = 0x0100, GM_MIB_CNT_END = 0x025C
}
enum  {
  GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24,
  GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64,
  GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, GM_RXF_SHT = GM_MIB_CNT_BASE + 80, GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, GM_RXF_64B = GM_MIB_CNT_BASE + 96,
  GM_RXF_127B = GM_MIB_CNT_BASE + 104, GM_RXF_255B = GM_MIB_CNT_BASE + 112, GM_RXF_511B = GM_MIB_CNT_BASE + 120, GM_RXF_1023B = GM_MIB_CNT_BASE + 128,
  GM_RXF_1518B = GM_MIB_CNT_BASE + 136, GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,
  GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,
  GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, GM_TXF_64B = GM_MIB_CNT_BASE + 240,
  GM_TXF_127B = GM_MIB_CNT_BASE + 248, GM_TXF_255B = GM_MIB_CNT_BASE + 256, GM_TXF_511B = GM_MIB_CNT_BASE + 264, GM_TXF_1023B = GM_MIB_CNT_BASE + 272,
  GM_TXF_1518B = GM_MIB_CNT_BASE + 280, GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, GM_TXF_COL = GM_MIB_CNT_BASE + 304, GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,
  GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344
}
enum  {
  GM_GPSR_SPEED = 1<<15, GM_GPSR_DUPLEX = 1<<14, GM_GPSR_FC_TX_DIS = 1<<13, GM_GPSR_LINK_UP = 1<<12,
  GM_GPSR_PAUSE = 1<<11, GM_GPSR_TX_ACTIVE = 1<<10, GM_GPSR_EXC_COL = 1<<9, GM_GPSR_LAT_COL = 1<<8,
  GM_GPSR_PHY_ST_CH = 1<<5, GM_GPSR_GIG_SPEED = 1<<4, GM_GPSR_PART_MODE = 1<<3, GM_GPSR_FC_RX_DIS = 1<<2,
  GM_GPSR_PROM_EN = 1<<1
}
enum  {
  GM_GPCR_PROM_ENA = 1<<14, GM_GPCR_FC_TX_DIS = 1<<13, GM_GPCR_TX_ENA = 1<<12, GM_GPCR_RX_ENA = 1<<11,
  GM_GPCR_BURST_ENA = 1<<10, GM_GPCR_LOOP_ENA = 1<<9, GM_GPCR_PART_ENA = 1<<8, GM_GPCR_GIGS_ENA = 1<<7,
  GM_GPCR_FL_PASS = 1<<6, GM_GPCR_DUP_FULL = 1<<5, GM_GPCR_FC_RX_DIS = 1<<4, GM_GPCR_SPEED_100 = 1<<3,
  GM_GPCR_AU_DUP_DIS = 1<<2, GM_GPCR_AU_FCT_DIS = 1<<1, GM_GPCR_AU_SPD_DIS = 1<<0
}
enum  { GM_TXCR_FORCE_JAM = 1<<15, GM_TXCR_CRC_DIS = 1<<14, GM_TXCR_PAD_DIS = 1<<13, GM_TXCR_COL_THR_MSK = 7<<10 }
enum  { GM_RXCR_UCF_ENA = 1<<15, GM_RXCR_MCF_ENA = 1<<14, GM_RXCR_CRC_DIS = 1<<13, GM_RXCR_PASS_FC = 1<<12 }
enum  {
  GM_TXPA_JAMLEN_MSK = 0x03<<14, GM_TXPA_JAMIPG_MSK = 0x1f<<9, GM_TXPA_JAMDAT_MSK = 0x1f<<4, GM_TXPA_BO_LIM_MSK = 0x0f,
  TX_JAM_LEN_DEF = 0x03, TX_JAM_IPG_DEF = 0x0b, TX_IPG_JAM_DEF = 0x1c, TX_BOF_LIM_DEF = 0x04
}
enum  {
  GM_SMOD_DATABL_MSK = 0x1f<<11, GM_SMOD_LIMIT_4 = 1<<10, GM_SMOD_VLAN_ENA = 1<<9, GM_SMOD_JUMBO_ENA = 1<<8,
  GM_SMOD_IPG_MSK = 0x1f
}
enum  {
  GM_SMI_CT_PHY_A_MSK = 0x1f<<11, GM_SMI_CT_REG_A_MSK = 0x1f<<6, GM_SMI_CT_OP_RD = 1<<5, GM_SMI_CT_RD_VAL = 1<<4,
  GM_SMI_CT_BUSY = 1<<3
}
enum  { GM_PAR_MIB_CLR = 1<<5, GM_PAR_MIB_TST = 1<<4 }
enum  {
  GMR_FS_LEN = 0x7fff<<16, GMR_FS_VLAN = 1<<13, GMR_FS_JABBER = 1<<12, GMR_FS_UN_SIZE = 1<<11,
  GMR_FS_MC = 1<<10, GMR_FS_BC = 1<<9, GMR_FS_RX_OK = 1<<8, GMR_FS_GOOD_FC = 1<<7,
  GMR_FS_BAD_FC = 1<<6, GMR_FS_MII_ERR = 1<<5, GMR_FS_LONG_ERR = 1<<4, GMR_FS_FRAGMENT = 1<<3,
  GMR_FS_CRC_ERR = 1<<1, GMR_FS_RX_FF_OV = 1<<0, GMR_FS_ANY_ERR
}
enum  {
  RX_TRUNC_ON = 1<<27, RX_TRUNC_OFF = 1<<26, RX_VLAN_STRIP_ON = 1<<25, RX_VLAN_STRIP_OFF = 1<<24,
  RX_MACSEC_FLUSH_ON = 1<<23, RX_MACSEC_FLUSH_OFF = 1<<22, RX_MACSEC_ASF_FLUSH_ON = 1<<21, RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
  GMF_RX_OVER_ON = 1<<19, GMF_RX_OVER_OFF = 1<<18, GMF_ASF_RX_OVER_ON = 1<<17, GMF_ASF_RX_OVER_OFF = 1<<16,
  GMF_WP_TST_ON = 1<<14, GMF_WP_TST_OFF = 1<<13, GMF_WP_STEP = 1<<12, GMF_RP_TST_ON = 1<<10,
  GMF_RP_TST_OFF = 1<<9, GMF_RP_STEP = 1<<8, GMF_RX_F_FL_ON = 1<<7, GMF_RX_F_FL_OFF = 1<<6,
  GMF_CLI_RX_FO = 1<<5, GMF_CLI_RX_C = 1<<4, GMF_OPER_ON = 1<<3, GMF_OPER_OFF = 1<<2,
  GMF_RST_CLR = 1<<1, GMF_RST_SET = 1<<0, RX_GMF_FL_THR_DEF = 0xa, GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON
}
enum  { TX_DYN_WM_ENA = 3 }
enum  {
  TX_STFW_DIS = 1<<31, TX_STFW_ENA = 1<<30, TX_VLAN_TAG_ON = 1<<25, TX_VLAN_TAG_OFF = 1<<24,
  TX_JUMBO_ENA = 1<<23, TX_JUMBO_DIS = 1<<22, GMF_WSP_TST_ON = 1<<18, GMF_WSP_TST_OFF = 1<<17,
  GMF_WSP_STEP = 1<<16, GMF_CLI_TX_FU = 1<<6, GMF_CLI_TX_FC = 1<<5, GMF_CLI_TX_PE = 1<<4
}
enum  { GMT_ST_START = 1<<2, GMT_ST_STOP = 1<<1, GMT_ST_CLR_IRQ = 1<<0 }
enum  {
  Y2_ASF_OS_PRES = 1<<4, Y2_ASF_RESET = 1<<3, Y2_ASF_RUNNING = 1<<2, Y2_ASF_CLR_HSTI = 1<<1,
  Y2_ASF_IRQ = 1<<0, Y2_ASF_UC_STATE = 3<<2, Y2_ASF_CLK_HALT = 0
}
enum  { Y2_ASF_CLR_ASFI = 1<<1, Y2_ASF_HOST_IRQ = 1<<0 }
enum  {
  HCU_CCSR_SMBALERT_MONITOR = 1<<27, HCU_CCSR_CPU_SLEEP = 1<<26, HCU_CCSR_CS_TO = 1<<25, HCU_CCSR_WDOG = 1<<24,
  HCU_CCSR_CLR_IRQ_HOST = 1<<17, HCU_CCSR_SET_IRQ_HCU = 1<<16, HCU_CCSR_AHB_RST = 1<<9, HCU_CCSR_CPU_RST_MODE = 1<<8,
  HCU_CCSR_SET_SYNC_CPU = 1<<5, HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3, HCU_CCSR_CPU_CLK_DIVIDE_BASE = 1<<3, HCU_CCSR_OS_PRSNT = 1<<2,
  HCU_CCSR_UC_STATE_MSK = 3, HCU_CCSR_UC_STATE_BASE = 1<<0, HCU_CCSR_ASF_RESET = 0, HCU_CCSR_ASF_HALTED = 1<<1,
  HCU_CCSR_ASF_RUNNING = 1<<0
}
enum  { HCU_HCSR_SET_IRQ_CPU = 1<<16, HCU_HCSR_CLR_IRQ_HCU = 1<<1, HCU_HCSR_SET_IRQ_HOST = 1<<0 }
enum  {
  SC_STAT_CLR_IRQ = 1<<4, SC_STAT_OP_ON = 1<<3, SC_STAT_OP_OFF = 1<<2, SC_STAT_RST_CLR = 1<<1,
  SC_STAT_RST_SET = 1<<0
}
enum  {
  GMC_SET_RST = 1<<15, GMC_SEC_RST_OFF = 1<<14, GMC_BYP_MACSECRX_ON = 1<<13, GMC_BYP_MACSECRX_OFF = 1<<12,
  GMC_BYP_MACSECTX_ON = 1<<11, GMC_BYP_MACSECTX_OFF = 1<<10, GMC_BYP_RETR_ON = 1<<9, GMC_BYP_RETR_OFF = 1<<8,
  GMC_H_BURST_ON = 1<<7, GMC_H_BURST_OFF = 1<<6, GMC_F_LOOPB_ON = 1<<5, GMC_F_LOOPB_OFF = 1<<4,
  GMC_PAUSE_ON = 1<<3, GMC_PAUSE_OFF = 1<<2, GMC_RST_CLR = 1<<1, GMC_RST_SET = 1<<0
}
enum  {
  GPC_TX_PAUSE = 1<<30, GPC_RX_PAUSE = 1<<29, GPC_SPEED = 3<<27, GPC_LINK = 1<<26,
  GPC_DUPLEX = 1<<25, GPC_CLOCK = 1<<24, GPC_PDOWN = 1<<23, GPC_TSTMODE = 1<<22,
  GPC_REG18 = 1<<21, GPC_REG12SEL = 3<<19, GPC_REG18SEL = 3<<17, GPC_SPILOCK = 1<<16,
  GPC_LEDMUX = 3<<14, GPC_INTPOL = 1<<13, GPC_DETECT = 1<<12, GPC_1000HD = 1<<11,
  GPC_SLAVE = 1<<10, GPC_PAUSE = 1<<9, GPC_LEDCTL = 3<<6, GPC_RST_CLR = 1<<1,
  GPC_RST_SET = 1<<0
}
enum  {
  GM_IS_TX_CO_OV = 1<<5, GM_IS_RX_CO_OV = 1<<4, GM_IS_TX_FF_UR = 1<<3, GM_IS_TX_COMPL = 1<<2,
  GM_IS_RX_FF_OR = 1<<1, GM_IS_RX_COMPL = 1<<0, GMAC_DEF_MSK
}
enum  { GMLC_RST_CLR = 1<<1, GMLC_RST_SET = 1<<0 }
enum  {
  WOL_CTL_LINK_CHG_OCC = 1<<15, WOL_CTL_MAGIC_PKT_OCC = 1<<14, WOL_CTL_PATTERN_OCC = 1<<13, WOL_CTL_CLEAR_RESULT = 1<<12,
  WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11, WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10, WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9, WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
  WOL_CTL_ENA_PME_ON_PATTERN = 1<<7, WOL_CTL_DIS_PME_ON_PATTERN = 1<<6, WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5, WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
  WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3, WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2, WOL_CTL_ENA_PATTERN_UNIT = 1<<1, WOL_CTL_DIS_PATTERN_UNIT = 1<<0
}
enum  {
  UDPTCP = 1<<0, CALSUM = 1<<1, WR_SUM = 1<<2, INIT_SUM = 1<<3,
  LOCK_SUM = 1<<4, INS_VLAN = 1<<5, EOP = 1<<7
}
enum  {
  HW_OWNER = 1<<7, OP_TCPWRITE = 0x11, OP_TCPSTART = 0x12, OP_TCPINIT = 0x14,
  OP_TCPLCK = 0x18, OP_TCPCHKSUM = OP_TCPSTART, OP_TCPIS = OP_TCPINIT | OP_TCPSTART, OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
  OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE, OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE, OP_ADDR64 = 0x21, OP_VLAN = 0x22,
  OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN, OP_LRGLEN = 0x24, OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN, OP_MSS = 0x28,
  OP_MSSVLAN = OP_MSS | OP_VLAN, OP_BUFFER = 0x40, OP_PACKET = 0x41, OP_LARGESEND = 0x43,
  OP_LSOV2 = 0x45, OP_RXSTAT = 0x60, OP_RXTIMESTAMP = 0x61, OP_RXVLAN = 0x62,
  OP_RXCHKS = 0x64, OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN, OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN, OP_RSS_HASH = 0x65,
  OP_TXINDEXLE = 0x68, OP_MACSEC = 0x6c, OP_PUTIDX = 0x70
}
enum  status_css {
  CSS_TCPUDPCSOK = 1<<7, CSS_ISUDP = 1<<6, CSS_ISTCP = 1<<5, CSS_ISIPFRAG = 1<<4,
  CSS_ISIPV6 = 1<<3, CSS_IPV4CSUMOK = 1<<2, CSS_ISIPV4 = 1<<1, CSS_LINK_BIT = 1<<0
}
enum  flow_control { FC_NONE = 0, FC_TX = 1, FC_RX = 2, FC_BOTH = 3 }

Functions

 FILE_LICENCE (GPL2_ONLY)
static int sky2_is_copper (const struct sky2_hw *hw)
static u32 sky2_read32 (const struct sky2_hw *hw, unsigned reg)
static u16 sky2_read16 (const struct sky2_hw *hw, unsigned reg)
static u8 sky2_read8 (const struct sky2_hw *hw, unsigned reg)
static void sky2_write32 (const struct sky2_hw *hw, unsigned reg, u32 val)
static void sky2_write16 (const struct sky2_hw *hw, unsigned reg, u16 val)
static void sky2_write8 (const struct sky2_hw *hw, unsigned reg, u8 val)
static u16 gma_read16 (const struct sky2_hw *hw, unsigned port, unsigned reg)
static u32 gma_read32 (struct sky2_hw *hw, unsigned port, unsigned reg)
static void gma_write16 (const struct sky2_hw *hw, unsigned port, int r, u16 v)
static void gma_set_addr (struct sky2_hw *hw, unsigned port, unsigned reg, const u8 *addr)
static u32 sky2_pci_read32 (const struct sky2_hw *hw, unsigned reg)
static u16 sky2_pci_read16 (const struct sky2_hw *hw, unsigned reg)
static void sky2_pci_write32 (struct sky2_hw *hw, unsigned reg, u32 val)
static void sky2_pci_write16 (struct sky2_hw *hw, unsigned reg, u16 val)

Variables

struct sky2_tx_le packed

Define Documentation

#define AUTONEG_DISABLE   0x00

Definition at line 14 of file sky2.h.

#define AUTONEG_ENABLE   0x01

Definition at line 15 of file sky2.h.

#define DUPLEX_HALF   0x00

Definition at line 17 of file sky2.h.

#define DUPLEX_FULL   0x01

Definition at line 18 of file sky2.h.

#define SPEED_10   10

Definition at line 20 of file sky2.h.

#define SPEED_100   100

Definition at line 21 of file sky2.h.

#define SPEED_1000   1000

Definition at line 22 of file sky2.h.

#define ADVERTISED_10baseT_Half   (1 << 0)

Definition at line 24 of file sky2.h.

#define ADVERTISED_10baseT_Full   (1 << 1)

Definition at line 25 of file sky2.h.

#define ADVERTISED_100baseT_Half   (1 << 2)

Definition at line 26 of file sky2.h.

#define ADVERTISED_100baseT_Full   (1 << 3)

Definition at line 27 of file sky2.h.

#define ADVERTISED_1000baseT_Half   (1 << 4)

Definition at line 28 of file sky2.h.

#define ADVERTISED_1000baseT_Full   (1 << 5)

Definition at line 29 of file sky2.h.

#define SUPPORTED_10baseT_Half   (1 << 0)

Definition at line 31 of file sky2.h.

#define SUPPORTED_10baseT_Full   (1 << 1)

Definition at line 32 of file sky2.h.

#define SUPPORTED_100baseT_Half   (1 << 2)

Definition at line 33 of file sky2.h.

#define SUPPORTED_100baseT_Full   (1 << 3)

Definition at line 34 of file sky2.h.

#define SUPPORTED_1000baseT_Half   (1 << 4)

Definition at line 35 of file sky2.h.

#define SUPPORTED_1000baseT_Full   (1 << 5)

Definition at line 36 of file sky2.h.

#define SUPPORTED_Autoneg   (1 << 6)

Definition at line 37 of file sky2.h.

#define SUPPORTED_TP   (1 << 7)

Definition at line 38 of file sky2.h.

#define SUPPORTED_FIBRE   (1 << 10)

Definition at line 39 of file sky2.h.

#define P_PEX_LTSSM_STAT ( x   )     ((x << 25) & P_PEX_LTSSM_STAT_MSK)

#define PCI_STATUS_ERROR_BITS

Value:

(PCI_STATUS_DETECTED_PARITY | \
                               PCI_STATUS_SIG_SYSTEM_ERROR | \
                               PCI_STATUS_REC_MASTER_ABORT | \
                               PCI_STATUS_REC_TARGET_ABORT | \
                               PCI_STATUS_PARITY)

Definition at line 183 of file sky2.h.

#define RAM_BUFFER ( port,
reg   )     (reg | (port <<6))

Referenced by sky2_hw_error(), and sky2_reset().

#define CFG_LED_MODE ( x   )     (((x) & CFG_LED_MODE_MSK) >> 2)

Definition at line 524 of file sky2.h.

#define CFG_DUAL_MAC_MSK   (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)

Definition at line 525 of file sky2.h.

Referenced by sky2_init().

#define Y2_CLK_DIV_VAL ( x   )     (((x)<<16) & Y2_CLK_DIV_VAL_MSK)

#define Y2_CLK_DIV_VAL_2 ( x   )     (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)

#define Y2_CLK_SEL_VAL_2 ( x   )     (((x)<<16) & Y2_CLK_SELECT2_MSK)

#define RAM_ADR_RAN   0x0007ffffL

Definition at line 559 of file sky2.h.

#define SK_RI_TO_53   36

Definition at line 571 of file sky2.h.

#define SK_REG ( port,
reg   )     (((port)<<7)+(reg))

Definition at line 575 of file sky2.h.

#define TXA_MAX_VAL   0x00ffffffUL

Definition at line 583 of file sky2.h.

#define Q_ADDR ( reg,
offs   )     (B8_Q_REGS + (reg) + (offs))

Definition at line 648 of file sky2.h.

#define Y2_QADDR ( q,
reg   )     (Y2_B8_PREF_REGS + (q) + (reg))

Definition at line 679 of file sky2.h.

Referenced by sky2_down(), sky2_le_error(), sky2_prefetch_init(), sky2_put_idx(), and sky2_rx_stop().

#define RB_ADDR ( offs,
queue   )     ((u16) B16_RAM_REGS + (queue) + (offs))

Definition at line 715 of file sky2.h.

#define RB_MSK   0x0007ffff

Definition at line 819 of file sky2.h.

#define WOL_REGS ( port,
x   )     (x + (port)*0x80)

Definition at line 981 of file sky2.h.

#define WOL_PATT_RAM_BASE ( port   )     (WOL_PATT_RAM_1 + (port)*0x400)

Definition at line 987 of file sky2.h.

#define PHY_M_PC_MDI_XMODE ( x   )     (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)

Definition at line 1185 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_PS_PAUSE_MSK   (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)

Definition at line 1234 of file sky2.h.

#define PHY_M_EC_M_DSC ( x   )     ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)

Definition at line 1287 of file sky2.h.

#define PHY_M_EC_S_DSC ( x   )     ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)

Definition at line 1289 of file sky2.h.

#define PHY_M_EC_DSC_2 ( x   )     ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)

Definition at line 1291 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_EC_MAC_S ( x   )     ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)

Definition at line 1293 of file sky2.h.

#define PHY_M_PC_DSC ( x   )     (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)

Definition at line 1304 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_LED_PULS_DUR ( x   )     (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)

Definition at line 1334 of file sky2.h.

#define PHY_M_POLC_LS1_P_MIX ( x   )     (((x)<<12) & PHY_M_POLC_LS1M_MSK)

Definition at line 1346 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_POLC_IS0_P_MIX ( x   )     (((x)<<8) & PHY_M_POLC_IS0M_MSK)

Definition at line 1347 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_POLC_LOS_CTRL ( x   )     (((x)<<6) & PHY_M_POLC_LOS_MSK)

Definition at line 1348 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_POLC_INIT_CTRL ( x   )     (((x)<<4) & PHY_M_POLC_INIT_MSK)

Definition at line 1349 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_POLC_STA1_CTRL ( x   )     (((x)<<2) & PHY_M_POLC_STA1_MSK)

Definition at line 1350 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_POLC_STA0_CTRL ( x   )     (((x)<<0) & PHY_M_POLC_STA0_MSK)

Definition at line 1351 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_LED_BLINK_RT ( x   )     (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)

Definition at line 1364 of file sky2.h.

#define PHY_M_LED_MO_SGMII ( x   )     ((x)<<14)

Definition at line 1375 of file sky2.h.

#define PHY_M_LED_MO_DUP ( x   )     ((x)<<10)

Definition at line 1377 of file sky2.h.

#define PHY_M_LED_MO_10 ( x   )     ((x)<<8)

Definition at line 1378 of file sky2.h.

#define PHY_M_LED_MO_100 ( x   )     ((x)<<6)

Definition at line 1379 of file sky2.h.

#define PHY_M_LED_MO_1000 ( x   )     ((x)<<4)

Definition at line 1380 of file sky2.h.

#define PHY_M_LED_MO_RX ( x   )     ((x)<<2)

Definition at line 1381 of file sky2.h.

#define PHY_M_LED_MO_TX ( x   )     ((x)<<0)

Definition at line 1382 of file sky2.h.

#define PHY_M_FELP_LED2_CTRL ( x   )     (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)

Definition at line 1425 of file sky2.h.

#define PHY_M_FELP_LED1_CTRL ( x   )     (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)

Definition at line 1426 of file sky2.h.

#define PHY_M_FELP_LED0_CTRL ( x   )     (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)

Definition at line 1427 of file sky2.h.

#define PHY_M_MAC_MODE_SEL ( x   )     (((x)<<7) & PHY_M_MAC_MD_MSK)

Definition at line 1472 of file sky2.h.

Referenced by sky2_phy_init().

#define PHY_M_LEDC_LOS_CTRL ( x   )     (((x)<<12) & PHY_M_LEDC_LOS_MSK)

Definition at line 1482 of file sky2.h.

#define PHY_M_LEDC_INIT_CTRL ( x   )     (((x)<<8) & PHY_M_LEDC_INIT_MSK)

Definition at line 1483 of file sky2.h.

#define PHY_M_LEDC_STA1_CTRL ( x   )     (((x)<<4) & PHY_M_LEDC_STA1_MSK)

Definition at line 1484 of file sky2.h.

#define PHY_M_LEDC_STA0_CTRL ( x   )     (((x)<<0) & PHY_M_LEDC_STA0_MSK)

Definition at line 1485 of file sky2.h.

#define GM_GPCR_SPEED_1000   (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)

Definition at line 1619 of file sky2.h.

#define GM_GPCR_AU_ALL_DIS   (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)

Definition at line 1620 of file sky2.h.

#define TX_COL_THR ( x   )     (((x)<<10) & GM_TXCR_COL_THR_MSK)

Definition at line 1630 of file sky2.h.

#define TX_COL_DEF   0x04

Definition at line 1631 of file sky2.h.

#define TX_JAM_LEN_VAL ( x   )     (((x)<<14) & GM_TXPA_JAMLEN_MSK)

Definition at line 1654 of file sky2.h.

#define TX_JAM_IPG_VAL ( x   )     (((x)<<9) & GM_TXPA_JAMIPG_MSK)

Definition at line 1655 of file sky2.h.

#define TX_IPG_JAM_DATA ( x   )     (((x)<<4) & GM_TXPA_JAMDAT_MSK)

Definition at line 1656 of file sky2.h.

#define TX_BACK_OFF_LIM ( x   )     ((x) & GM_TXPA_BO_LIM_MSK)

Definition at line 1657 of file sky2.h.

Referenced by sky2_mac_init().

#define DATA_BLIND_VAL ( x   )     (((x)<<11) & GM_SMOD_DATABL_MSK)

Definition at line 1669 of file sky2.h.

#define DATA_BLIND_DEF   0x04

Definition at line 1670 of file sky2.h.

#define IPG_DATA_VAL ( x   )     (x & GM_SMOD_IPG_MSK)

Definition at line 1672 of file sky2.h.

#define IPG_DATA_DEF   0x1e

Definition at line 1673 of file sky2.h.

#define GM_SMI_CT_PHY_AD ( x   )     (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)

Definition at line 1684 of file sky2.h.

#define GM_SMI_CT_REG_AD ( x   )     (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)

Definition at line 1685 of file sky2.h.

#define GMAC_DEF_MSK   GM_IS_TX_FF_UR

#define SKY2_HW_USE_MSI   0x00000001

Definition at line 2071 of file sky2.h.

#define SKY2_HW_FIBRE_PHY   0x00000002

Definition at line 2072 of file sky2.h.

Referenced by sky2_init(), sky2_is_copper(), sky2_phy_init(), and sky2_phy_speed().

#define SKY2_HW_GIGABIT   0x00000004

Definition at line 2073 of file sky2.h.

Referenced by sky2_init(), sky2_phy_init(), sky2_phy_speed(), and sky2_supported_modes().

#define SKY2_HW_NEWER_PHY   0x00000008

Definition at line 2074 of file sky2.h.

Referenced by sky2_init(), sky2_phy_init(), and sky2_phy_power_down().

#define SKY2_HW_RAM_BUFFER   0x00000010

Definition at line 2075 of file sky2.h.

Referenced by sky2_mac_init(), sky2_rx_alloc(), and sky2_up().

#define SKY2_HW_NEW_LE   0x00000020

Definition at line 2076 of file sky2.h.

Referenced by sky2_init(), and sky2_rx_start().

#define SKY2_HW_AUTO_TX_SUM   0x00000040

Definition at line 2077 of file sky2.h.

Referenced by sky2_init().

#define SKY2_HW_ADV_POWER_CTL   0x00000080

Definition at line 2078 of file sky2.h.

Referenced by sky2_init(), sky2_phy_power_up(), and sky2_power_on().

#define SK_GMAC_REG ( port,
reg   )     (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))

Definition at line 2127 of file sky2.h.

#define GM_PHY_RETRIES   100

Definition at line 2129 of file sky2.h.

Enumeration Type Documentation

anonymous enum

Enumerator:
PCI_DEV_REG1 
PCI_DEV_REG2 
PCI_DEV_STATUS 
PCI_DEV_REG3 
PCI_DEV_REG4 
PCI_DEV_REG5 
PCI_CFG_REG_0 
PCI_CFG_REG_1 

Definition at line 44 of file sky2.h.

00044      {
00045         PCI_DEV_REG1    = 0x40,
00046         PCI_DEV_REG2    = 0x44,
00047         PCI_DEV_STATUS  = 0x7c,
00048         PCI_DEV_REG3    = 0x80,
00049         PCI_DEV_REG4    = 0x84,
00050         PCI_DEV_REG5    = 0x88,
00051         PCI_CFG_REG_0   = 0x90,
00052         PCI_CFG_REG_1   = 0x94,
00053 };

enum pci_dev_reg_1

Enumerator:
PCI_Y2_PIG_ENA 
PCI_Y2_DLL_DIS 
PCI_SW_PWR_ON_RST 
PCI_Y2_PHY2_COMA 
PCI_Y2_PHY1_COMA 
PCI_Y2_PHY2_POWD 
PCI_Y2_PHY1_POWD 
PCI_Y2_PME_LEGACY 
PCI_PHY_LNK_TIM_MSK 
PCI_ENA_L1_EVENT 
PCI_ENA_GPHY_LNK 
PCI_FORCE_PEX_L1 

Definition at line 56 of file sky2.h.

00056                    {
00057         PCI_Y2_PIG_ENA   = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
00058         PCI_Y2_DLL_DIS   = 1<<30, /* Disable PCI DLL (YUKON-2) */
00059         PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
00060         PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
00061         PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
00062         PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
00063         PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
00064         PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
00065 
00066         PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit  9.. 8:       GPHY Link Trigger Timer */
00067         PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
00068         PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
00069         PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
00070 };

enum pci_dev_reg_2

Enumerator:
PCI_VPD_WR_THR 
PCI_DEV_SEL 
PCI_VPD_ROM_SZ 
PCI_PATCH_DIR 
PCI_EXT_PATCHS 
PCI_EN_DUMMY_RD 
PCI_REV_DESC 
PCI_USEDATA64 

Definition at line 72 of file sky2.h.

00072                    {
00073         PCI_VPD_WR_THR  = 0xffL<<24,    /* Bit 31..24:  VPD Write Threshold */
00074         PCI_DEV_SEL     = 0x7fL<<17,    /* Bit 23..17:  EEPROM Device Select */
00075         PCI_VPD_ROM_SZ  = 7L<<14,       /* Bit 16..14:  VPD ROM Size    */
00076 
00077         PCI_PATCH_DIR   = 0xfL<<8,      /* Bit 11.. 8:  Ext Patches dir 3..0 */
00078         PCI_EXT_PATCHS  = 0xfL<<4,      /* Bit  7.. 4:  Extended Patches 3..0 */
00079         PCI_EN_DUMMY_RD = 1<<3,         /* Enable Dummy Read */
00080         PCI_REV_DESC    = 1<<2,         /* Reverse Desc. Bytes */
00081 
00082         PCI_USEDATA64   = 1<<0,         /* Use 64Bit Data bus ext */
00083 };

enum pci_dev_reg_4

Enumerator:
P_PEX_LTSSM_STAT_MSK 
P_PEX_LTSSM_STAT 
P_PEX_LTSSM_DET_STAT 
P_TIMER_VALUE_MSK 
P_FORCE_ASPM_REQUEST 
P_ASPM_GPHY_LINK_DOWN 
P_ASPM_INT_FIFO_EMPTY 
P_ASPM_CLKRUN_REQUEST 
P_ASPM_FORCE_CLKREQ_ENA 
P_ASPM_CLKREQ_PAD_CTL 
P_ASPM_A1_MODE_SELECT 
P_CLK_GATE_PEX_UNIT_ENA 
P_CLK_GATE_ROOT_COR_ENA 
P_ASPM_CONTROL_MSK 

Definition at line 86 of file sky2.h.

00086                    {
00087                                 /* (Link Training & Status State Machine) */
00088         P_PEX_LTSSM_STAT_MSK    = 0x7fL<<25,    /* Bit 31..25:  PEX LTSSM Mask */
00089 #define P_PEX_LTSSM_STAT(x)     ((x << 25) & P_PEX_LTSSM_STAT_MSK)
00090         P_PEX_LTSSM_L1_STAT     = 0x34,
00091         P_PEX_LTSSM_DET_STAT    = 0x01,
00092         P_TIMER_VALUE_MSK       = 0xffL<<16,    /* Bit 23..16:  Timer Value Mask */
00093                                         /* (Active State Power Management) */
00094         P_FORCE_ASPM_REQUEST    = 1<<15, /* Force ASPM Request (A1 only) */
00095         P_ASPM_GPHY_LINK_DOWN   = 1<<14, /* GPHY Link Down (A1 only) */
00096         P_ASPM_INT_FIFO_EMPTY   = 1<<13, /* Internal FIFO Empty (A1 only) */
00097         P_ASPM_CLKRUN_REQUEST   = 1<<12, /* CLKRUN Request (A1 only) */
00098 
00099         P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
00100         P_ASPM_CLKREQ_PAD_CTL   = 1<<3, /* CLKREQ PAD Control (A1 only) */
00101         P_ASPM_A1_MODE_SELECT   = 1<<2, /* A1 Mode Select (A1 only) */
00102         P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
00103         P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
00104         P_ASPM_CONTROL_MSK      = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
00105                                   | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
00106 };

enum pci_dev_reg_5

Enumerator:
P_CTL_DIV_CORE_CLK_ENA 
P_CTL_SRESET_VMAIN_AV 
P_CTL_BYPASS_VMAIN_AV 
P_CTL_TIM_VMAIN_AV_MSK 
P_REL_PCIE_RST_DE_ASS 
P_REL_GPHY_REC_PACKET 
P_REL_INT_FIFO_N_EMPTY 
P_REL_MAIN_PWR_AVAIL 
P_REL_CLKRUN_REQ_REL 
P_REL_PCIE_RESET_ASS 
P_REL_PME_ASSERTED 
P_REL_PCIE_EXIT_L1_ST 
P_REL_LOADER_NOT_FIN 
P_REL_PCIE_RX_EX_IDLE 
P_REL_GPHY_LINK_UP 
P_GAT_PCIE_RST_ASSERTED 
P_GAT_GPHY_N_REC_PACKET 
P_GAT_INT_FIFO_EMPTY 
P_GAT_MAIN_PWR_N_AVAIL 
P_GAT_CLKRUN_REQ_REL 
P_GAT_PCIE_RESET_ASS 
P_GAT_PME_DE_ASSERTED 
P_GAT_PCIE_ENTER_L1_ST 
P_GAT_LOADER_FINISHED 
P_GAT_PCIE_RX_EL_IDLE 
P_GAT_GPHY_LINK_DOWN 
PCIE_OUR5_EVENT_CLK_D3_SET 

Definition at line 109 of file sky2.h.

00109                    {
00110                                         /* Bit 31..27:  for A3 & later */
00111         P_CTL_DIV_CORE_CLK_ENA  = 1<<31, /* Divide Core Clock Enable */
00112         P_CTL_SRESET_VMAIN_AV   = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
00113         P_CTL_BYPASS_VMAIN_AV   = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
00114         P_CTL_TIM_VMAIN_AV_MSK  = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
00115                                          /* Bit 26..16: Release Clock on Event */
00116         P_REL_PCIE_RST_DE_ASS   = 1<<26, /* PCIe Reset De-Asserted */
00117         P_REL_GPHY_REC_PACKET   = 1<<25, /* GPHY Received Packet */
00118         P_REL_INT_FIFO_N_EMPTY  = 1<<24, /* Internal FIFO Not Empty */
00119         P_REL_MAIN_PWR_AVAIL    = 1<<23, /* Main Power Available */
00120         P_REL_CLKRUN_REQ_REL    = 1<<22, /* CLKRUN Request Release */
00121         P_REL_PCIE_RESET_ASS    = 1<<21, /* PCIe Reset Asserted */
00122         P_REL_PME_ASSERTED      = 1<<20, /* PME Asserted */
00123         P_REL_PCIE_EXIT_L1_ST   = 1<<19, /* PCIe Exit L1 State */
00124         P_REL_LOADER_NOT_FIN    = 1<<18, /* EPROM Loader Not Finished */
00125         P_REL_PCIE_RX_EX_IDLE   = 1<<17, /* PCIe Rx Exit Electrical Idle State */
00126         P_REL_GPHY_LINK_UP      = 1<<16, /* GPHY Link Up */
00127 
00128                                         /* Bit 10.. 0: Mask for Gate Clock */
00129         P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
00130         P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */
00131         P_GAT_INT_FIFO_EMPTY    = 1<<8, /* Internal FIFO Empty */
00132         P_GAT_MAIN_PWR_N_AVAIL  = 1<<7, /* Main Power Not Available */
00133         P_GAT_CLKRUN_REQ_REL    = 1<<6, /* CLKRUN Not Requested */
00134         P_GAT_PCIE_RESET_ASS    = 1<<5, /* PCIe Reset Asserted */
00135         P_GAT_PME_DE_ASSERTED   = 1<<4, /* PME De-Asserted */
00136         P_GAT_PCIE_ENTER_L1_ST  = 1<<3, /* PCIe Enter L1 State */
00137         P_GAT_LOADER_FINISHED   = 1<<2, /* EPROM Loader Finished */
00138         P_GAT_PCIE_RX_EL_IDLE   = 1<<1, /* PCIe Rx Electrical Idle State */
00139         P_GAT_GPHY_LINK_DOWN    = 1<<0, /* GPHY Link Down */
00140 
00141         PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
00142                                      P_REL_INT_FIFO_N_EMPTY |
00143                                      P_REL_PCIE_EXIT_L1_ST |
00144                                      P_REL_PCIE_RX_EX_IDLE |
00145                                      P_GAT_GPHY_N_REC_PACKET |
00146                                      P_GAT_INT_FIFO_EMPTY |
00147                                      P_GAT_PCIE_ENTER_L1_ST |
00148                                      P_GAT_PCIE_RX_EL_IDLE,
00149 };

enum pci_cfg_reg1

Enumerator:
P_CF1_DIS_REL_EVT_RST 
P_CF1_REL_LDR_NOT_FIN 
P_CF1_REL_VMAIN_AVLBL 
P_CF1_REL_PCIE_RESET 
P_CF1_GAT_LDR_NOT_FIN 
P_CF1_GAT_PCIE_RX_IDLE 
P_CF1_GAT_PCIE_RESET 
P_CF1_PRST_PHY_CLKREQ 
P_CF1_PCIE_RST_CLKREQ 
P_CF1_ENA_CFG_LDR_DONE 
P_CF1_ENA_TXBMU_RD_IDLE 
P_CF1_ENA_TXBMU_WR_IDLE 
PCIE_CFG1_EVENT_CLK_D3_SET 

Definition at line 152 of file sky2.h.

00152                   {
00153         P_CF1_DIS_REL_EVT_RST   = 1<<24, /* Dis. Rel. Event during PCIE reset */
00154                                                                                 /* Bit 23..21: Release Clock on Event */
00155         P_CF1_REL_LDR_NOT_FIN   = 1<<23, /* EEPROM Loader Not Finished */
00156         P_CF1_REL_VMAIN_AVLBL   = 1<<22, /* Vmain available */
00157         P_CF1_REL_PCIE_RESET    = 1<<21, /* PCI-E reset */
00158                                                                                 /* Bit 20..18: Gate Clock on Event */
00159         P_CF1_GAT_LDR_NOT_FIN   = 1<<20, /* EEPROM Loader Finished */
00160         P_CF1_GAT_PCIE_RX_IDLE  = 1<<19, /* PCI-E Rx Electrical idle */
00161         P_CF1_GAT_PCIE_RESET    = 1<<18, /* PCI-E Reset */
00162         P_CF1_PRST_PHY_CLKREQ   = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
00163         P_CF1_PCIE_RST_CLKREQ   = 1<<16, /* Enable PCI-E rst generate CLKREQ */
00164 
00165         P_CF1_ENA_CFG_LDR_DONE  = 1<<8, /* Enable core level Config loader done */
00166 
00167         P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read  IDLE for ASPM */
00168         P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
00169 
00170         PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
00171                                         P_CF1_REL_LDR_NOT_FIN |
00172                                         P_CF1_REL_VMAIN_AVLBL |
00173                                         P_CF1_REL_PCIE_RESET |
00174                                         P_CF1_GAT_LDR_NOT_FIN |
00175                                         P_CF1_GAT_PCIE_RESET |
00176                                         P_CF1_PRST_PHY_CLKREQ |
00177                                         P_CF1_ENA_CFG_LDR_DONE |
00178                                         P_CF1_ENA_TXBMU_RD_IDLE |
00179                                         P_CF1_ENA_TXBMU_WR_IDLE,
00180 };

enum csr_regs

Enumerator:
B0_RAP 
B0_CTST 
B0_LED 
B0_POWER_CTRL 
B0_ISRC 
B0_IMSK 
B0_HWE_ISRC 
B0_HWE_IMSK 
B0_SP_ISRC 
B0_XM1_IMSK 
B0_XM1_ISRC 
B0_XM1_PHY_ADDR 
B0_XM1_PHY_DATA 
B0_XM2_IMSK 
B0_XM2_ISRC 
B0_XM2_PHY_ADDR 
B0_XM2_PHY_DATA 
B0_R1_CSR 
B0_R2_CSR 
B0_XS1_CSR 
B0_XA1_CSR 
B0_XS2_CSR 
B0_XA2_CSR 
B2_MAC_1 
B2_MAC_2 
B2_MAC_3 
B2_CONN_TYP 
B2_PMD_TYP 
B2_MAC_CFG 
B2_CHIP_ID 
B2_E_0 
B2_E_1 
B2_E_2 
B2_E_3 
B2_FAR 
B2_FDP 
B2_LD_CTRL 
B2_LD_TEST 
B2_TI_INI 
B2_TI_VAL 
B2_TI_CTRL 
B2_TI_TEST 
B2_IRQM_INI 
B2_IRQM_VAL 
B2_IRQM_CTRL 
B2_IRQM_TEST 
B2_IRQM_MSK 
B2_IRQM_HWE_MSK 
B2_TST_CTRL1 
B2_TST_CTRL2 
B2_GP_IO 
B2_I2C_CTRL 
B2_I2C_DATA 
B2_I2C_IRQ 
B2_I2C_SW 
B2_BSC_INI 
B2_BSC_VAL 
B2_BSC_CTRL 
B2_BSC_STAT 
B2_BSC_TST 
B3_RAM_ADDR 
B3_RAM_DATA_LO 
B3_RAM_DATA_HI 
B3_RI_WTO_R1 
B3_RI_WTO_XA1 
B3_RI_WTO_XS1 
B3_RI_RTO_R1 
B3_RI_RTO_XA1 
B3_RI_RTO_XS1 
B3_RI_WTO_R2 
B3_RI_WTO_XA2 
B3_RI_WTO_XS2 
B3_RI_RTO_R2 
B3_RI_RTO_XA2 
B3_RI_RTO_XS2 
B3_RI_TO_VAL 
B3_RI_CTRL 
B3_RI_TEST 
B3_MA_TOINI_RX1 
B3_MA_TOINI_RX2 
B3_MA_TOINI_TX1 
B3_MA_TOINI_TX2 
B3_MA_TOVAL_RX1 
B3_MA_TOVAL_RX2 
B3_MA_TOVAL_TX1 
B3_MA_TOVAL_TX2 
B3_MA_TO_CTRL 
B3_MA_TO_TEST 
B3_MA_RCINI_RX1 
B3_MA_RCINI_RX2 
B3_MA_RCINI_TX1 
B3_MA_RCINI_TX2 
B3_MA_RCVAL_RX1 
B3_MA_RCVAL_RX2 
B3_MA_RCVAL_TX1 
B3_MA_RCVAL_TX2 
B3_MA_RC_CTRL 
B3_MA_RC_TEST 
B3_PA_TOINI_RX1 
B3_PA_TOINI_RX2 
B3_PA_TOINI_TX1 
B3_PA_TOINI_TX2 
B3_PA_TOVAL_RX1 
B3_PA_TOVAL_RX2 
B3_PA_TOVAL_TX1 
B3_PA_TOVAL_TX2 
B3_PA_CTRL 
B3_PA_TEST 
B0_RAP 
B0_CTST 
B0_Y2LED 
B0_POWER_CTRL 
B0_ISRC 
B0_IMSK 
B0_HWE_ISRC 
B0_HWE_IMSK 
B0_Y2_SP_ISRC2 
B0_Y2_SP_ISRC3 
B0_Y2_SP_EISR 
B0_Y2_SP_LISR 
B0_Y2_SP_ICR 
B2_MAC_1 
B2_MAC_2 
B2_MAC_3 
B2_CONN_TYP 
B2_PMD_TYP 
B2_MAC_CFG 
B2_CHIP_ID 
B2_E_0 
B2_Y2_CLK_GATE 
B2_Y2_HW_RES 
B2_E_3 
B2_Y2_CLK_CTRL 
B2_TI_INI 
B2_TI_VAL 
B2_TI_CTRL 
B2_TI_TEST 
B2_TST_CTRL1 
B2_TST_CTRL2 
B2_GP_IO 
B2_I2C_CTRL 
B2_I2C_DATA 
B2_I2C_IRQ 
B2_I2C_SW 
B3_RAM_ADDR 
B3_RAM_DATA_LO 
B3_RAM_DATA_HI 
RAM_BUFFER 
B3_RI_WTO_XA1 
B3_RI_WTO_XS1 
B3_RI_RTO_R1 
B3_RI_RTO_XA1 
B3_RI_RTO_XS1 
B3_RI_WTO_R2 
B3_RI_WTO_XA2 
B3_RI_WTO_XS2 
B3_RI_RTO_R2 
B3_RI_RTO_XA2 
B3_RI_RTO_XS2 
B3_RI_TO_VAL 
B3_RI_CTRL 
B3_RI_TEST 
B3_MA_TOINI_RX1 
B3_MA_TOINI_RX2 
B3_MA_TOINI_TX1 
B3_MA_TOINI_TX2 
B3_MA_TOVAL_RX1 
B3_MA_TOVAL_RX2 
B3_MA_TOVAL_TX1 
B3_MA_TOVAL_TX2 
B3_MA_TO_CTRL 
B3_MA_TO_TEST 
B3_MA_RCINI_RX1 
B3_MA_RCINI_RX2 
B3_MA_RCINI_TX1 
B3_MA_RCINI_TX2 
B3_MA_RCVAL_RX1 
B3_MA_RCVAL_RX2 
B3_MA_RCVAL_TX1 
B3_MA_RCVAL_TX2 
B3_MA_RC_CTRL 
B3_MA_RC_TEST 
B3_PA_TOINI_RX1 
B3_PA_TOINI_RX2 
B3_PA_TOINI_TX1 
B3_PA_TOINI_TX2 
B3_PA_TOVAL_RX1 
B3_PA_TOVAL_RX2 
B3_PA_TOVAL_TX1 
B3_PA_TOVAL_TX2 
B3_PA_CTRL 
B3_PA_TEST 
Y2_CFG_SPC 
Y2_CFG_AER 

Definition at line 189 of file sky2.h.

00189               {
00190         B0_RAP          = 0x0000,
00191         B0_CTST         = 0x0004,
00192         B0_Y2LED        = 0x0005,
00193         B0_POWER_CTRL   = 0x0007,
00194         B0_ISRC         = 0x0008,
00195         B0_IMSK         = 0x000c,
00196         B0_HWE_ISRC     = 0x0010,
00197         B0_HWE_IMSK     = 0x0014,
00198 
00199         /* Special ISR registers (Yukon-2 only) */
00200         B0_Y2_SP_ISRC2  = 0x001c,
00201         B0_Y2_SP_ISRC3  = 0x0020,
00202         B0_Y2_SP_EISR   = 0x0024,
00203         B0_Y2_SP_LISR   = 0x0028,
00204         B0_Y2_SP_ICR    = 0x002c,
00205 
00206         B2_MAC_1        = 0x0100,
00207         B2_MAC_2        = 0x0108,
00208         B2_MAC_3        = 0x0110,
00209         B2_CONN_TYP     = 0x0118,
00210         B2_PMD_TYP      = 0x0119,
00211         B2_MAC_CFG      = 0x011a,
00212         B2_CHIP_ID      = 0x011b,
00213         B2_E_0          = 0x011c,
00214 
00215         B2_Y2_CLK_GATE  = 0x011d,
00216         B2_Y2_HW_RES    = 0x011e,
00217         B2_E_3          = 0x011f,
00218         B2_Y2_CLK_CTRL  = 0x0120,
00219 
00220         B2_TI_INI       = 0x0130,
00221         B2_TI_VAL       = 0x0134,
00222         B2_TI_CTRL      = 0x0138,
00223         B2_TI_TEST      = 0x0139,
00224 
00225         B2_TST_CTRL1    = 0x0158,
00226         B2_TST_CTRL2    = 0x0159,
00227         B2_GP_IO        = 0x015c,
00228 
00229         B2_I2C_CTRL     = 0x0160,
00230         B2_I2C_DATA     = 0x0164,
00231         B2_I2C_IRQ      = 0x0168,
00232         B2_I2C_SW       = 0x016c,
00233 
00234         B3_RAM_ADDR     = 0x0180,
00235         B3_RAM_DATA_LO  = 0x0184,
00236         B3_RAM_DATA_HI  = 0x0188,
00237 
00238 /* RAM Interface Registers */
00239 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
00240 /*
00241  * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
00242  * not usable in SW. Please notice these are NOT real timeouts, these are
00243  * the number of qWords transferred continuously.
00244  */
00245 #define RAM_BUFFER(port, reg)   (reg | (port <<6))
00246 
00247         B3_RI_WTO_R1    = 0x0190,
00248         B3_RI_WTO_XA1   = 0x0191,
00249         B3_RI_WTO_XS1   = 0x0192,
00250         B3_RI_RTO_R1    = 0x0193,
00251         B3_RI_RTO_XA1   = 0x0194,
00252         B3_RI_RTO_XS1   = 0x0195,
00253         B3_RI_WTO_R2    = 0x0196,
00254         B3_RI_WTO_XA2   = 0x0197,
00255         B3_RI_WTO_XS2   = 0x0198,
00256         B3_RI_RTO_R2    = 0x0199,
00257         B3_RI_RTO_XA2   = 0x019a,
00258         B3_RI_RTO_XS2   = 0x019b,
00259         B3_RI_TO_VAL    = 0x019c,
00260         B3_RI_CTRL      = 0x01a0,
00261         B3_RI_TEST      = 0x01a2,
00262         B3_MA_TOINI_RX1 = 0x01b0,
00263         B3_MA_TOINI_RX2 = 0x01b1,
00264         B3_MA_TOINI_TX1 = 0x01b2,
00265         B3_MA_TOINI_TX2 = 0x01b3,
00266         B3_MA_TOVAL_RX1 = 0x01b4,
00267         B3_MA_TOVAL_RX2 = 0x01b5,
00268         B3_MA_TOVAL_TX1 = 0x01b6,
00269         B3_MA_TOVAL_TX2 = 0x01b7,
00270         B3_MA_TO_CTRL   = 0x01b8,
00271         B3_MA_TO_TEST   = 0x01ba,
00272         B3_MA_RCINI_RX1 = 0x01c0,
00273         B3_MA_RCINI_RX2 = 0x01c1,
00274         B3_MA_RCINI_TX1 = 0x01c2,
00275         B3_MA_RCINI_TX2 = 0x01c3,
00276         B3_MA_RCVAL_RX1 = 0x01c4,
00277         B3_MA_RCVAL_RX2 = 0x01c5,
00278         B3_MA_RCVAL_TX1 = 0x01c6,
00279         B3_MA_RCVAL_TX2 = 0x01c7,
00280         B3_MA_RC_CTRL   = 0x01c8,
00281         B3_MA_RC_TEST   = 0x01ca,
00282         B3_PA_TOINI_RX1 = 0x01d0,
00283         B3_PA_TOINI_RX2 = 0x01d4,
00284         B3_PA_TOINI_TX1 = 0x01d8,
00285         B3_PA_TOINI_TX2 = 0x01dc,
00286         B3_PA_TOVAL_RX1 = 0x01e0,
00287         B3_PA_TOVAL_RX2 = 0x01e4,
00288         B3_PA_TOVAL_TX1 = 0x01e8,
00289         B3_PA_TOVAL_TX2 = 0x01ec,
00290         B3_PA_CTRL      = 0x01f0,
00291         B3_PA_TEST      = 0x01f2,
00292 
00293         Y2_CFG_SPC      = 0x1c00,       /* PCI config space region */
00294         Y2_CFG_AER      = 0x1d00,       /* PCI Advanced Error Report region */
00295 };

anonymous enum

Enumerator:
Y2_VMAIN_AVAIL 
Y2_VAUX_AVAIL 
Y2_HW_WOL_ON 
Y2_HW_WOL_OFF 
Y2_ASF_ENABLE 
Y2_ASF_DISABLE 
Y2_CLK_RUN_ENA 
Y2_CLK_RUN_DIS 
Y2_LED_STAT_ON 
Y2_LED_STAT_OFF 
CS_ST_SW_IRQ 
CS_CL_SW_IRQ 
CS_STOP_DONE 
CS_STOP_MAST 
CS_MRST_CLR 
CS_MRST_SET 
CS_RST_CLR 
CS_RST_SET 

Definition at line 298 of file sky2.h.

00298      {
00299         Y2_VMAIN_AVAIL  = 1<<17,/* VMAIN available (YUKON-2 only) */
00300         Y2_VAUX_AVAIL   = 1<<16,/* VAUX available (YUKON-2 only) */
00301         Y2_HW_WOL_ON    = 1<<15,/* HW WOL On  (Yukon-EC Ultra A1 only) */
00302         Y2_HW_WOL_OFF   = 1<<14,/* HW WOL On  (Yukon-EC Ultra A1 only) */
00303         Y2_ASF_ENABLE   = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
00304         Y2_ASF_DISABLE  = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
00305         Y2_CLK_RUN_ENA  = 1<<11,/* CLK_RUN Enable  (YUKON-2 only) */
00306         Y2_CLK_RUN_DIS  = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
00307         Y2_LED_STAT_ON  = 1<<9, /* Status LED On  (YUKON-2 only) */
00308         Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
00309 
00310         CS_ST_SW_IRQ    = 1<<7, /* Set IRQ SW Request */
00311         CS_CL_SW_IRQ    = 1<<6, /* Clear IRQ SW Request */
00312         CS_STOP_DONE    = 1<<5, /* Stop Master is finished */
00313         CS_STOP_MAST    = 1<<4, /* Command Bit to stop the master */
00314         CS_MRST_CLR     = 1<<3, /* Clear Master reset   */
00315         CS_MRST_SET     = 1<<2, /* Set Master reset     */
00316         CS_RST_CLR      = 1<<1, /* Clear Software reset */
00317         CS_RST_SET      = 1,    /* Set   Software reset */
00318 };

anonymous enum

Enumerator:
LED_STAT_ON 
LED_STAT_OFF 

Definition at line 321 of file sky2.h.

00321      {
00322 /* Bit  7.. 2:  reserved */
00323         LED_STAT_ON     = 1<<1, /* Status LED on        */
00324         LED_STAT_OFF    = 1,    /* Status LED off       */
00325 };

anonymous enum

Enumerator:
PC_VAUX_ENA 
PC_VAUX_DIS 
PC_VCC_ENA 
PC_VCC_DIS 
PC_VAUX_ON 
PC_VAUX_OFF 
PC_VCC_ON 
PC_VCC_OFF 

Definition at line 328 of file sky2.h.

00328      {
00329         PC_VAUX_ENA     = 1<<7, /* Switch VAUX Enable  */
00330         PC_VAUX_DIS     = 1<<6, /* Switch VAUX Disable */
00331         PC_VCC_ENA      = 1<<5, /* Switch VCC Enable  */
00332         PC_VCC_DIS      = 1<<4, /* Switch VCC Disable */
00333         PC_VAUX_ON      = 1<<3, /* Switch VAUX On  */
00334         PC_VAUX_OFF     = 1<<2, /* Switch VAUX Off */
00335         PC_VCC_ON       = 1<<1, /* Switch VCC On  */
00336         PC_VCC_OFF      = 1<<0, /* Switch VCC Off */
00337 };

anonymous enum

Enumerator:
Y2_IS_HW_ERR 
Y2_IS_STAT_BMU 
Y2_IS_ASF 
Y2_IS_POLL_CHK 
Y2_IS_TWSI_RDY 
Y2_IS_IRQ_SW 
Y2_IS_TIMINT 
Y2_IS_IRQ_PHY2 
Y2_IS_IRQ_MAC2 
Y2_IS_CHK_RX2 
Y2_IS_CHK_TXS2 
Y2_IS_CHK_TXA2 
Y2_IS_IRQ_PHY1 
Y2_IS_IRQ_MAC1 
Y2_IS_CHK_RX1 
Y2_IS_CHK_TXS1 
Y2_IS_CHK_TXA1 
Y2_IS_BASE 
Y2_IS_PORT_1 
Y2_IS_PORT_2 
Y2_IS_ERROR 

Definition at line 345 of file sky2.h.

00345      {
00346         Y2_IS_HW_ERR    = 1<<31,        /* Interrupt HW Error */
00347         Y2_IS_STAT_BMU  = 1<<30,        /* Status BMU Interrupt */
00348         Y2_IS_ASF       = 1<<29,        /* ASF subsystem Interrupt */
00349 
00350         Y2_IS_POLL_CHK  = 1<<27,        /* Check IRQ from polling unit */
00351         Y2_IS_TWSI_RDY  = 1<<26,        /* IRQ on end of TWSI Tx */
00352         Y2_IS_IRQ_SW    = 1<<25,        /* SW forced IRQ        */
00353         Y2_IS_TIMINT    = 1<<24,        /* IRQ from Timer       */
00354 
00355         Y2_IS_IRQ_PHY2  = 1<<12,        /* Interrupt from PHY 2 */
00356         Y2_IS_IRQ_MAC2  = 1<<11,        /* Interrupt from MAC 2 */
00357         Y2_IS_CHK_RX2   = 1<<10,        /* Descriptor error Rx 2 */
00358         Y2_IS_CHK_TXS2  = 1<<9,         /* Descriptor error TXS 2 */
00359         Y2_IS_CHK_TXA2  = 1<<8,         /* Descriptor error TXA 2 */
00360 
00361         Y2_IS_IRQ_PHY1  = 1<<4,         /* Interrupt from PHY 1 */
00362         Y2_IS_IRQ_MAC1  = 1<<3,         /* Interrupt from MAC 1 */
00363         Y2_IS_CHK_RX1   = 1<<2,         /* Descriptor error Rx 1 */
00364         Y2_IS_CHK_TXS1  = 1<<1,         /* Descriptor error TXS 1 */
00365         Y2_IS_CHK_TXA1  = 1<<0,         /* Descriptor error TXA 1 */
00366 
00367         Y2_IS_BASE      = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
00368         Y2_IS_PORT_1    = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
00369                           | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
00370         Y2_IS_PORT_2    = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
00371                           | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
00372         Y2_IS_ERROR     = Y2_IS_HW_ERR |
00373                           Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
00374                           Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
00375 };

anonymous enum

Enumerator:
IS_ERR_MSK 
IS_IRQ_TIST_OV 
IS_IRQ_SENSOR 
IS_IRQ_MST_ERR 
IS_IRQ_STAT 
IS_NO_STAT_M1 
IS_NO_STAT_M2 
IS_NO_TIST_M1 
IS_NO_TIST_M2 
IS_RAM_RD_PAR 
IS_RAM_WR_PAR 
IS_M1_PAR_ERR 
IS_M2_PAR_ERR 
IS_R1_PAR_ERR 
IS_R2_PAR_ERR 

Definition at line 378 of file sky2.h.

00378      {
00379         IS_ERR_MSK      = 0x00003fff,/*                 All Error bits */
00380 
00381         IS_IRQ_TIST_OV  = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
00382         IS_IRQ_SENSOR   = 1<<12, /* IRQ from Sensor (YUKON only) */
00383         IS_IRQ_MST_ERR  = 1<<11, /* IRQ master error detected */
00384         IS_IRQ_STAT     = 1<<10, /* IRQ status exception */
00385         IS_NO_STAT_M1   = 1<<9, /* No Rx Status from MAC 1 */
00386         IS_NO_STAT_M2   = 1<<8, /* No Rx Status from MAC 2 */
00387         IS_NO_TIST_M1   = 1<<7, /* No Time Stamp from MAC 1 */
00388         IS_NO_TIST_M2   = 1<<6, /* No Time Stamp from MAC 2 */
00389         IS_RAM_RD_PAR   = 1<<5, /* RAM Read  Parity Error */
00390         IS_RAM_WR_PAR   = 1<<4, /* RAM Write Parity Error */
00391         IS_M1_PAR_ERR   = 1<<3, /* MAC 1 Parity Error */
00392         IS_M2_PAR_ERR   = 1<<2, /* MAC 2 Parity Error */
00393         IS_R1_PAR_ERR   = 1<<1, /* Queue R1 Parity Error */
00394         IS_R2_PAR_ERR   = 1<<0, /* Queue R2 Parity Error */
00395 };

anonymous enum

Enumerator:
Y2_IS_TIST_OV 
Y2_IS_SENSOR 
Y2_IS_MST_ERR 
Y2_IS_IRQ_STAT 
Y2_IS_PCI_EXP 
Y2_IS_PCI_NEXP 
Y2_IS_PAR_RD2 
Y2_IS_PAR_WR2 
Y2_IS_PAR_MAC2 
Y2_IS_PAR_RX2 
Y2_IS_TCP_TXS2 
Y2_IS_TCP_TXA2 
Y2_IS_PAR_RD1 
Y2_IS_PAR_WR1 
Y2_IS_PAR_MAC1 
Y2_IS_PAR_RX1 
Y2_IS_TCP_TXS1 
Y2_IS_TCP_TXA1 
Y2_HWE_L1_MASK 
Y2_HWE_L2_MASK 
Y2_HWE_ALL_MASK 

Definition at line 398 of file sky2.h.

00398      {
00399         Y2_IS_TIST_OV   = 1<<29,/* Time Stamp Timer overflow interrupt */
00400         Y2_IS_SENSOR    = 1<<28, /* Sensor interrupt */
00401         Y2_IS_MST_ERR   = 1<<27, /* Master error interrupt */
00402         Y2_IS_IRQ_STAT  = 1<<26, /* Status exception interrupt */
00403         Y2_IS_PCI_EXP   = 1<<25, /* PCI-Express interrupt */
00404         Y2_IS_PCI_NEXP  = 1<<24, /* PCI-Express error similar to PCI error */
00405                                                 /* Link 2 */
00406         Y2_IS_PAR_RD2   = 1<<13, /* Read RAM parity error interrupt */
00407         Y2_IS_PAR_WR2   = 1<<12, /* Write RAM parity error interrupt */
00408         Y2_IS_PAR_MAC2  = 1<<11, /* MAC hardware fault interrupt */
00409         Y2_IS_PAR_RX2   = 1<<10, /* Parity Error Rx Queue 2 */
00410         Y2_IS_TCP_TXS2  = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
00411         Y2_IS_TCP_TXA2  = 1<<8, /* TCP length mismatch async Tx queue IRQ */
00412                                                 /* Link 1 */
00413         Y2_IS_PAR_RD1   = 1<<5, /* Read RAM parity error interrupt */
00414         Y2_IS_PAR_WR1   = 1<<4, /* Write RAM parity error interrupt */
00415         Y2_IS_PAR_MAC1  = 1<<3, /* MAC hardware fault interrupt */
00416         Y2_IS_PAR_RX1   = 1<<2, /* Parity Error Rx Queue 1 */
00417         Y2_IS_TCP_TXS1  = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
00418         Y2_IS_TCP_TXA1  = 1<<0, /* TCP length mismatch async Tx queue IRQ */
00419 
00420         Y2_HWE_L1_MASK  = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
00421                           Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
00422         Y2_HWE_L2_MASK  = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
00423                           Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
00424 
00425         Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
00426                           Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
00427 };

anonymous enum

Enumerator:
DPT_START 
DPT_STOP 

Definition at line 430 of file sky2.h.

00430      {
00431         DPT_START       = 1<<1,
00432         DPT_STOP        = 1<<0,
00433 };

anonymous enum

Enumerator:
TST_FRC_DPERR_MR 
TST_FRC_DPERR_MW 
TST_FRC_DPERR_TR 
TST_FRC_DPERR_TW 
TST_FRC_APERR_M 
TST_FRC_APERR_T 
TST_CFG_WRITE_ON 
TST_CFG_WRITE_OFF 

Definition at line 436 of file sky2.h.

00436      {
00437         TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
00438         TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
00439         TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
00440         TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
00441         TST_FRC_APERR_M  = 1<<3, /* force ADDRPERR on MST */
00442         TST_FRC_APERR_T  = 1<<2, /* force ADDRPERR on TRG */
00443         TST_CFG_WRITE_ON = 1<<1, /* Enable  Config Reg WR */
00444         TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
00445 };

anonymous enum

Enumerator:
GLB_GPIO_CLK_DEB_ENA 
GLB_GPIO_CLK_DBG_MSK 
GLB_GPIO_INT_RST_D3_DIS 
GLB_GPIO_LED_PAD_SPEED_UP 
GLB_GPIO_STAT_RACE_DIS 
GLB_GPIO_TEST_SEL_MSK 
GLB_GPIO_TEST_SEL_BASE 
GLB_GPIO_RAND_ENA 
GLB_GPIO_RAND_BIT_1 

Definition at line 448 of file sky2.h.

00448      {
00449         GLB_GPIO_CLK_DEB_ENA = 1<<31,   /* Clock Debug Enable */
00450         GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
00451 
00452         GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
00453         GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
00454         GLB_GPIO_STAT_RACE_DIS  = 1<<13, /* Status Race Disable */
00455         GLB_GPIO_TEST_SEL_MSK   = 3<<11, /* Testmode Select */
00456         GLB_GPIO_TEST_SEL_BASE  = 1<<11,
00457         GLB_GPIO_RAND_ENA       = 1<<10, /* Random Enable */
00458         GLB_GPIO_RAND_BIT_1     = 1<<9,  /* Random Bit 1 */
00459 };

anonymous enum

Enumerator:
CFG_CHIP_R_MSK 
CFG_DIS_M2_CLK 
CFG_SNG_MAC 

Definition at line 462 of file sky2.h.

00462      {
00463         CFG_CHIP_R_MSK    = 0xf<<4,     /* Bit 7.. 4: Chip Revision */
00464                                         /* Bit 3.. 2:   reserved */
00465         CFG_DIS_M2_CLK    = 1<<1,       /* Disable Clock for 2nd MAC */
00466         CFG_SNG_MAC       = 1<<0,       /* MAC Config: 0=2 MACs / 1=1 MAC*/
00467 };

anonymous enum

Enumerator:
CHIP_ID_YUKON_XL 
CHIP_ID_YUKON_EC_U 
CHIP_ID_YUKON_EX 
CHIP_ID_YUKON_EC 
CHIP_ID_YUKON_FE 
CHIP_ID_YUKON_FE_P 
CHIP_ID_YUKON_SUPR 
CHIP_ID_YUKON_UL_2 

Definition at line 470 of file sky2.h.

00470      {
00471         CHIP_ID_YUKON_XL   = 0xb3, /* YUKON-2 XL */
00472         CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
00473         CHIP_ID_YUKON_EX   = 0xb5, /* YUKON-2 Extreme */
00474         CHIP_ID_YUKON_EC   = 0xb6, /* YUKON-2 EC */
00475         CHIP_ID_YUKON_FE   = 0xb7, /* YUKON-2 FE */
00476         CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
00477         CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
00478         CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
00479 };

enum yukon_ec_rev

Enumerator:
CHIP_REV_YU_EC_A1 
CHIP_REV_YU_EC_A2 
CHIP_REV_YU_EC_A3 

Definition at line 480 of file sky2.h.

00480                   {
00481         CHIP_REV_YU_EC_A1    = 0,  /* Chip Rev. for Yukon-EC A1/A0 */
00482         CHIP_REV_YU_EC_A2    = 1,  /* Chip Rev. for Yukon-EC A2 */
00483         CHIP_REV_YU_EC_A3    = 2,  /* Chip Rev. for Yukon-EC A3 */
00484 };

enum yukon_ec_u_rev

Enumerator:
CHIP_REV_YU_EC_U_A0 
CHIP_REV_YU_EC_U_A1 
CHIP_REV_YU_EC_U_B0 

Definition at line 485 of file sky2.h.

00485                     {
00486         CHIP_REV_YU_EC_U_A0  = 1,
00487         CHIP_REV_YU_EC_U_A1  = 2,
00488         CHIP_REV_YU_EC_U_B0  = 3,
00489 };

enum yukon_fe_rev

Enumerator:
CHIP_REV_YU_FE_A1 
CHIP_REV_YU_FE_A2 

Definition at line 490 of file sky2.h.

00490                   {
00491         CHIP_REV_YU_FE_A1    = 1,
00492         CHIP_REV_YU_FE_A2    = 2,
00493 };

enum yukon_fe_p_rev

Enumerator:
CHIP_REV_YU_FE2_A0 

Definition at line 494 of file sky2.h.

00494                     {
00495         CHIP_REV_YU_FE2_A0   = 0,
00496 };

enum yukon_ex_rev

Enumerator:
CHIP_REV_YU_EX_A0 
CHIP_REV_YU_EX_B0 

Definition at line 497 of file sky2.h.

00497                   {
00498         CHIP_REV_YU_EX_A0    = 1,
00499         CHIP_REV_YU_EX_B0    = 2,
00500 };

enum yukon_supr_rev

Enumerator:
CHIP_REV_YU_SU_A0 

Definition at line 501 of file sky2.h.

00501                     {
00502         CHIP_REV_YU_SU_A0    = 0,
00503 };

anonymous enum

Enumerator:
Y2_STATUS_LNK2_INAC 
Y2_CLK_GAT_LNK2_DIS 
Y2_COR_CLK_LNK2_DIS 
Y2_PCI_CLK_LNK2_DIS 
Y2_STATUS_LNK1_INAC 
Y2_CLK_GAT_LNK1_DIS 
Y2_COR_CLK_LNK1_DIS 
Y2_PCI_CLK_LNK1_DIS 

Definition at line 507 of file sky2.h.

00507      {
00508         Y2_STATUS_LNK2_INAC     = 1<<7, /* Status Link 2 inactive (0 = active) */
00509         Y2_CLK_GAT_LNK2_DIS     = 1<<6, /* Disable clock gating Link 2 */
00510         Y2_COR_CLK_LNK2_DIS     = 1<<5, /* Disable Core clock Link 2 */
00511         Y2_PCI_CLK_LNK2_DIS     = 1<<4, /* Disable PCI clock Link 2 */
00512         Y2_STATUS_LNK1_INAC     = 1<<3, /* Status Link 1 inactive (0 = active) */
00513         Y2_CLK_GAT_LNK1_DIS     = 1<<2, /* Disable clock gating Link 1 */
00514         Y2_COR_CLK_LNK1_DIS     = 1<<1, /* Disable Core clock Link 1 */
00515         Y2_PCI_CLK_LNK1_DIS     = 1<<0, /* Disable PCI clock Link 1 */
00516 };

anonymous enum

Enumerator:
CFG_LED_MODE_MSK 
CFG_LINK_2_AVAIL 
CFG_LINK_1_AVAIL 

Definition at line 519 of file sky2.h.

00519      {
00520         CFG_LED_MODE_MSK        = 7<<2, /* Bit  4.. 2:  LED Mode Mask */
00521         CFG_LINK_2_AVAIL        = 1<<1, /* Link 2 available */
00522         CFG_LINK_1_AVAIL        = 1<<0, /* Link 1 available */
00523 };

anonymous enum

Enumerator:
Y2_CLK_DIV_VAL_MSK 
Y2_CLK_DIV_VAL 
Y2_CLK_SELECT2_MSK 
Y2_CLK_DIV_VAL_2 
Y2_CLK_DIV_DIS 

Definition at line 529 of file sky2.h.

00529      {
00530         Y2_CLK_DIV_VAL_MSK      = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
00531 #define Y2_CLK_DIV_VAL(x)       (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
00532         Y2_CLK_DIV_VAL2_MSK     = 7<<21,   /* Bit 23..21: Clock Divisor Value */
00533         Y2_CLK_SELECT2_MSK      = 0x1f<<16,/* Bit 20..16: Clock Select */
00534 #define Y2_CLK_DIV_VAL_2(x)     (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
00535 #define Y2_CLK_SEL_VAL_2(x)     (((x)<<16) & Y2_CLK_SELECT2_MSK)
00536         Y2_CLK_DIV_ENA          = 1<<1, /* Enable  Core Clock Division */
00537         Y2_CLK_DIV_DIS          = 1<<0, /* Disable Core Clock Division */
00538 };

anonymous enum

Enumerator:
TIM_START 
TIM_STOP 
TIM_CLR_IRQ 

Definition at line 542 of file sky2.h.

00542      {
00543         TIM_START       = 1<<2, /* Start Timer */
00544         TIM_STOP        = 1<<1, /* Stop  Timer */
00545         TIM_CLR_IRQ     = 1<<0, /* Clear Timer IRQ (!IRQM) */
00546 };

anonymous enum

Enumerator:
TIM_T_ON 
TIM_T_OFF 
TIM_T_STEP 

Definition at line 551 of file sky2.h.

00551      {
00552         TIM_T_ON        = 1<<2, /* Test mode on */
00553         TIM_T_OFF       = 1<<1, /* Test mode off */
00554         TIM_T_STEP      = 1<<0, /* Test step */
00555 };

anonymous enum

Enumerator:
RI_CLR_RD_PERR 
RI_CLR_WR_PERR 
RI_RST_CLR 
RI_RST_SET 

Definition at line 563 of file sky2.h.

00563      {
00564         RI_CLR_RD_PERR  = 1<<9, /* Clear IRQ RAM Read Parity Err */
00565         RI_CLR_WR_PERR  = 1<<8, /* Clear IRQ RAM Write Parity Err*/
00566 
00567         RI_RST_CLR      = 1<<1, /* Clear RAM Interface Reset */
00568         RI_RST_SET      = 1<<0, /* Set   RAM Interface Reset */
00569 };

anonymous enum

Enumerator:
TXA_ENA_FSYNC 
TXA_DIS_FSYNC 
TXA_ENA_ALLOC 
TXA_DIS_ALLOC 
TXA_START_RC 
TXA_STOP_RC 
TXA_ENA_ARB 
TXA_DIS_ARB 

Definition at line 586 of file sky2.h.

00586      {
00587         TXA_ENA_FSYNC   = 1<<7, /* Enable  force of sync Tx queue */
00588         TXA_DIS_FSYNC   = 1<<6, /* Disable force of sync Tx queue */
00589         TXA_ENA_ALLOC   = 1<<5, /* Enable  alloc of free bandwidth */
00590         TXA_DIS_ALLOC   = 1<<4, /* Disable alloc of free bandwidth */
00591         TXA_START_RC    = 1<<3, /* Start sync Rate Control */
00592         TXA_STOP_RC     = 1<<2, /* Stop  sync Rate Control */
00593         TXA_ENA_ARB     = 1<<1, /* Enable  Tx Arbiter */
00594         TXA_DIS_ARB     = 1<<0, /* Disable Tx Arbiter */
00595 };

anonymous enum

Enumerator:
TXA_ITI_INI 
TXA_ITI_VAL 
TXA_LIM_INI 
TXA_LIM_VAL 
TXA_CTRL 
TXA_TEST 
TXA_STAT 

Definition at line 601 of file sky2.h.

00601      {
00602         TXA_ITI_INI     = 0x0200,/* 32 bit      Tx Arb Interval Timer Init Val*/
00603         TXA_ITI_VAL     = 0x0204,/* 32 bit      Tx Arb Interval Timer Value */
00604         TXA_LIM_INI     = 0x0208,/* 32 bit      Tx Arb Limit Counter Init Val */
00605         TXA_LIM_VAL     = 0x020c,/* 32 bit      Tx Arb Limit Counter Value */
00606         TXA_CTRL        = 0x0210,/*  8 bit      Tx Arbiter Control Register */
00607         TXA_TEST        = 0x0211,/*  8 bit      Tx Arbiter Test Register */
00608         TXA_STAT        = 0x0212,/*  8 bit      Tx Arbiter Status Register */
00609 };

anonymous enum

Enumerator:
B6_EXT_REG 
B7_CFG_SPC 
B8_RQ1_REGS 
B8_RQ2_REGS 
B8_TS1_REGS 
B8_TA1_REGS 
B8_TS2_REGS 
B8_TA2_REGS 
B16_RAM_REGS 

Definition at line 612 of file sky2.h.

00612      {
00613         B6_EXT_REG      = 0x0300,/* External registers (GENESIS only) */
00614         B7_CFG_SPC      = 0x0380,/* copy of the Configuration register */
00615         B8_RQ1_REGS     = 0x0400,/* Receive Queue 1 */
00616         B8_RQ2_REGS     = 0x0480,/* Receive Queue 2 */
00617         B8_TS1_REGS     = 0x0600,/* Transmit sync queue 1 */
00618         B8_TA1_REGS     = 0x0680,/* Transmit async queue 1 */
00619         B8_TS2_REGS     = 0x0700,/* Transmit sync queue 2 */
00620         B8_TA2_REGS     = 0x0780,/* Transmit sync queue 2 */
00621         B16_RAM_REGS    = 0x0800,/* RAM Buffer Registers */
00622 };

anonymous enum

Enumerator:
B8_Q_REGS 
Q_D 
Q_VLAN 
Q_DONE 
Q_AC_L 
Q_AC_H 
Q_BC 
Q_CSR 
Q_TEST 
Q_WM 
Q_AL 
Q_RSP 
Q_RSL 
Q_RP 
Q_RL 
Q_WP 
Q_WSP 
Q_WL 
Q_WSL 

Definition at line 625 of file sky2.h.

00625      {
00626         B8_Q_REGS = 0x0400, /* base of Queue registers */
00627         Q_D     = 0x00, /* 8*32 bit     Current Descriptor */
00628         Q_VLAN  = 0x20, /* 16 bit       Current VLAN Tag */
00629         Q_DONE  = 0x24, /* 16 bit       Done Index */
00630         Q_AC_L  = 0x28, /* 32 bit       Current Address Counter Low dWord */
00631         Q_AC_H  = 0x2c, /* 32 bit       Current Address Counter High dWord */
00632         Q_BC    = 0x30, /* 32 bit       Current Byte Counter */
00633         Q_CSR   = 0x34, /* 32 bit       BMU Control/Status Register */
00634         Q_TEST  = 0x38, /* 32 bit       Test/Control Register */
00635 
00636 /* Yukon-2 */
00637         Q_WM    = 0x40, /* 16 bit       FIFO Watermark */
00638         Q_AL    = 0x42, /*  8 bit       FIFO Alignment */
00639         Q_RSP   = 0x44, /* 16 bit       FIFO Read Shadow Pointer */
00640         Q_RSL   = 0x46, /*  8 bit       FIFO Read Shadow Level */
00641         Q_RP    = 0x48, /*  8 bit       FIFO Read Pointer */
00642         Q_RL    = 0x4a, /*  8 bit       FIFO Read Level */
00643         Q_WP    = 0x4c, /*  8 bit       FIFO Write Pointer */
00644         Q_WSP   = 0x4d, /*  8 bit       FIFO Write Shadow Pointer */
00645         Q_WL    = 0x4e, /*  8 bit       FIFO Write Level */
00646         Q_WSL   = 0x4f, /*  8 bit       FIFO Write Shadow Level */
00647 };

anonymous enum

Enumerator:
F_TX_CHK_AUTO_OFF 
F_TX_CHK_AUTO_ON 
F_M_RX_RAM_DIS 

Definition at line 651 of file sky2.h.

00651      {
00652         /* Transmit */
00653         F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
00654         F_TX_CHK_AUTO_ON  = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
00655 
00656         /* Receive */
00657         F_M_RX_RAM_DIS  = 1<<24, /* MAC Rx RAM Read Port disable */
00658 
00659         /* Hardware testbits not used */
00660 };

anonymous enum

Enumerator:
Y2_B8_PREF_REGS 
PREF_UNIT_CTRL 
PREF_UNIT_LAST_IDX 
PREF_UNIT_ADDR_LO 
PREF_UNIT_ADDR_HI 
PREF_UNIT_GET_IDX 
PREF_UNIT_PUT_IDX 
PREF_UNIT_FIFO_WP 
PREF_UNIT_FIFO_RP 
PREF_UNIT_FIFO_WM 
PREF_UNIT_FIFO_LEV 
PREF_UNIT_MASK_IDX 

Definition at line 663 of file sky2.h.

00663      {
00664         Y2_B8_PREF_REGS         = 0x0450,
00665 
00666         PREF_UNIT_CTRL          = 0x00, /* 32 bit       Control register */
00667         PREF_UNIT_LAST_IDX      = 0x04, /* 16 bit       Last Index */
00668         PREF_UNIT_ADDR_LO       = 0x08, /* 32 bit       List start addr, low part */
00669         PREF_UNIT_ADDR_HI       = 0x0c, /* 32 bit       List start addr, high part*/
00670         PREF_UNIT_GET_IDX       = 0x10, /* 16 bit       Get Index */
00671         PREF_UNIT_PUT_IDX       = 0x14, /* 16 bit       Put Index */
00672         PREF_UNIT_FIFO_WP       = 0x20, /*  8 bit       FIFO write pointer */
00673         PREF_UNIT_FIFO_RP       = 0x24, /*  8 bit       FIFO read pointer */
00674         PREF_UNIT_FIFO_WM       = 0x28, /*  8 bit       FIFO watermark */
00675         PREF_UNIT_FIFO_LEV      = 0x2c, /*  8 bit       FIFO level */
00676 
00677         PREF_UNIT_MASK_IDX      = 0x0fff,
00678 };

anonymous enum

Enumerator:
RB_START 
RB_END 
RB_WP 
RB_RP 
RB_RX_UTPP 
RB_RX_LTPP 
RB_RX_UTHP 
RB_RX_LTHP 
RB_PC 
RB_LEV 
RB_CTRL 
RB_TST1 
RB_TST2 

Definition at line 682 of file sky2.h.

00682      {
00683 
00684         RB_START        = 0x00,/* 32 bit        RAM Buffer Start Address */
00685         RB_END  = 0x04,/* 32 bit        RAM Buffer End Address */
00686         RB_WP   = 0x08,/* 32 bit        RAM Buffer Write Pointer */
00687         RB_RP   = 0x0c,/* 32 bit        RAM Buffer Read Pointer */
00688         RB_RX_UTPP      = 0x10,/* 32 bit        Rx Upper Threshold, Pause Packet */
00689         RB_RX_LTPP      = 0x14,/* 32 bit        Rx Lower Threshold, Pause Packet */
00690         RB_RX_UTHP      = 0x18,/* 32 bit        Rx Upper Threshold, High Prio */
00691         RB_RX_LTHP      = 0x1c,/* 32 bit        Rx Lower Threshold, High Prio */
00692         /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
00693         RB_PC   = 0x20,/* 32 bit        RAM Buffer Packet Counter */
00694         RB_LEV  = 0x24,/* 32 bit        RAM Buffer Level Register */
00695         RB_CTRL = 0x28,/* 32 bit        RAM Buffer Control Register */
00696         RB_TST1 = 0x29,/*  8 bit        RAM Buffer Test Register 1 */
00697         RB_TST2 = 0x2a,/*  8 bit        RAM Buffer Test Register 2 */
00698 };

anonymous enum

Enumerator:
Q_R1 
Q_R2 
Q_XS1 
Q_XA1 
Q_XS2 
Q_XA2 

Definition at line 701 of file sky2.h.

00701      {
00702         Q_R1    = 0x0000,       /* Receive Queue 1 */
00703         Q_R2    = 0x0080,       /* Receive Queue 2 */
00704         Q_XS1   = 0x0200,       /* Synchronous Transmit Queue 1 */
00705         Q_XA1   = 0x0280,       /* Asynchronous Transmit Queue 1 */
00706         Q_XS2   = 0x0300,       /* Synchronous Transmit Queue 2 */
00707         Q_XA2   = 0x0380,       /* Asynchronous Transmit Queue 2 */
00708 };

anonymous enum

Enumerator:
PHY_ADDR_MARV 

Definition at line 711 of file sky2.h.

00711      {
00712         PHY_ADDR_MARV   = 0,
00713 };

anonymous enum

Enumerator:
LNK_SYNC_INI 
LNK_SYNC_VAL 
LNK_SYNC_CTRL 
LNK_SYNC_TST 
LNK_LED_REG 
RX_GMF_EA 
RX_GMF_AF_THR 
RX_GMF_CTRL_T 
RX_GMF_FL_MSK 
RX_GMF_FL_THR 
RX_GMF_TR_THR 
RX_GMF_UP_THR 
RX_GMF_LP_THR 
RX_GMF_VLAN 
RX_GMF_WP 
RX_GMF_WLEV 
RX_GMF_RP 
RX_GMF_RLEV 

Definition at line 718 of file sky2.h.

00718      {
00719         LNK_SYNC_INI    = 0x0c30,/* 32 bit      Link Sync Cnt Init Value */
00720         LNK_SYNC_VAL    = 0x0c34,/* 32 bit      Link Sync Cnt Current Value */
00721         LNK_SYNC_CTRL   = 0x0c38,/*  8 bit      Link Sync Cnt Control Register */
00722         LNK_SYNC_TST    = 0x0c39,/*  8 bit      Link Sync Cnt Test Register */
00723 
00724         LNK_LED_REG     = 0x0c3c,/*  8 bit      Link LED Register */
00725 
00726 /* Receive GMAC FIFO (YUKON and Yukon-2) */
00727 
00728         RX_GMF_EA       = 0x0c40,/* 32 bit      Rx GMAC FIFO End Address */
00729         RX_GMF_AF_THR   = 0x0c44,/* 32 bit      Rx GMAC FIFO Almost Full Thresh. */
00730         RX_GMF_CTRL_T   = 0x0c48,/* 32 bit      Rx GMAC FIFO Control/Test */
00731         RX_GMF_FL_MSK   = 0x0c4c,/* 32 bit      Rx GMAC FIFO Flush Mask */
00732         RX_GMF_FL_THR   = 0x0c50,/* 32 bit      Rx GMAC FIFO Flush Threshold */
00733         RX_GMF_TR_THR   = 0x0c54,/* 32 bit      Rx Truncation Threshold (Yukon-2) */
00734         RX_GMF_UP_THR   = 0x0c58,/*  8 bit      Rx Upper Pause Thr (Yukon-EC_U) */
00735         RX_GMF_LP_THR   = 0x0c5a,/*  8 bit      Rx Lower Pause Thr (Yukon-EC_U) */
00736         RX_GMF_VLAN     = 0x0c5c,/* 32 bit      Rx VLAN Type Register (Yukon-2) */
00737         RX_GMF_WP       = 0x0c60,/* 32 bit      Rx GMAC FIFO Write Pointer */
00738 
00739         RX_GMF_WLEV     = 0x0c68,/* 32 bit      Rx GMAC FIFO Write Level */
00740 
00741         RX_GMF_RP       = 0x0c70,/* 32 bit      Rx GMAC FIFO Read Pointer */
00742 
00743         RX_GMF_RLEV     = 0x0c78,/* 32 bit      Rx GMAC FIFO Read Level */
00744 };

anonymous enum

Enumerator:
BMU_IDLE 
BMU_RX_TCP_PKT 
BMU_RX_IP_PKT 
BMU_ENA_RX_RSS_HASH 
BMU_DIS_RX_RSS_HASH 
BMU_ENA_RX_CHKSUM 
BMU_DIS_RX_CHKSUM 
BMU_CLR_IRQ_PAR 
BMU_CLR_IRQ_TCP 
BMU_CLR_IRQ_CHK 
BMU_STOP 
BMU_START 
BMU_FIFO_OP_ON 
BMU_FIFO_OP_OFF 
BMU_FIFO_ENA 
BMU_FIFO_RST 
BMU_OP_ON 
BMU_OP_OFF 
BMU_RST_CLR 
BMU_RST_SET 
BMU_CLR_RESET 
BMU_OPER_INIT 
BMU_WM_DEFAULT 
BMU_WM_PEX 

Definition at line 759 of file sky2.h.

00759      {
00760         BMU_IDLE        = 1<<31, /* BMU Idle State */
00761         BMU_RX_TCP_PKT  = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
00762         BMU_RX_IP_PKT   = 1<<29, /* Rx IP  Packet (when RSS Hash enabled) */
00763 
00764         BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable  Rx RSS Hash */
00765         BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
00766         BMU_ENA_RX_CHKSUM = 1<<13, /* Enable  Rx TCP/IP Checksum Check */
00767         BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
00768         BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
00769         BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
00770         BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
00771         BMU_STOP        = 1<<9, /* Stop  Rx/Tx Queue */
00772         BMU_START       = 1<<8, /* Start Rx/Tx Queue */
00773         BMU_FIFO_OP_ON  = 1<<7, /* FIFO Operational On */
00774         BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
00775         BMU_FIFO_ENA    = 1<<5, /* Enable FIFO */
00776         BMU_FIFO_RST    = 1<<4, /* Reset  FIFO */
00777         BMU_OP_ON       = 1<<3, /* BMU Operational On */
00778         BMU_OP_OFF      = 1<<2, /* BMU Operational Off */
00779         BMU_RST_CLR     = 1<<1, /* Clear BMU Reset (Enable) */
00780         BMU_RST_SET     = 1<<0, /* Set   BMU Reset */
00781 
00782         BMU_CLR_RESET   = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
00783         BMU_OPER_INIT   = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
00784                           BMU_FIFO_ENA | BMU_OP_ON,
00785 
00786         BMU_WM_DEFAULT = 0x600,
00787         BMU_WM_PEX     = 0x80,
00788 };

anonymous enum

Enumerator:
BMU_TX_IPIDINCR_ON 
BMU_TX_IPIDINCR_OFF 
BMU_TX_CLR_IRQ_TCP 

Definition at line 792 of file sky2.h.

00792      {
00793         BMU_TX_IPIDINCR_ON      = 1<<13, /* Enable  IP ID Increment */
00794         BMU_TX_IPIDINCR_OFF     = 1<<12, /* Disable IP ID Increment */
00795         BMU_TX_CLR_IRQ_TCP      = 1<<11, /* Clear IRQ on TCP segment length mismatch */
00796 };

anonymous enum

Enumerator:
PREF_UNIT_OP_ON 
PREF_UNIT_OP_OFF 
PREF_UNIT_RST_CLR 
PREF_UNIT_RST_SET 

Definition at line 800 of file sky2.h.

00800      {
00801         PREF_UNIT_OP_ON         = 1<<3, /* prefetch unit operational */
00802         PREF_UNIT_OP_OFF        = 1<<2, /* prefetch unit not operational */
00803         PREF_UNIT_RST_CLR       = 1<<1, /* Clear Prefetch Unit Reset */
00804         PREF_UNIT_RST_SET       = 1<<0, /* Set   Prefetch Unit Reset */
00805 };

anonymous enum

Enumerator:
RB_ENA_STFWD 
RB_DIS_STFWD 
RB_ENA_OP_MD 
RB_DIS_OP_MD 
RB_RST_CLR 
RB_RST_SET 

Definition at line 824 of file sky2.h.

00824      {
00825         RB_ENA_STFWD    = 1<<5, /* Enable  Store & Forward */
00826         RB_DIS_STFWD    = 1<<4, /* Disable Store & Forward */
00827         RB_ENA_OP_MD    = 1<<3, /* Enable  Operation Mode */
00828         RB_DIS_OP_MD    = 1<<2, /* Disable Operation Mode */
00829         RB_RST_CLR      = 1<<1, /* Clear RAM Buf STM Reset */
00830         RB_RST_SET      = 1<<0, /* Set   RAM Buf STM Reset */
00831 };

anonymous enum

Enumerator:
TX_GMF_EA 
TX_GMF_AE_THR 
TX_GMF_CTRL_T 
TX_GMF_WP 
TX_GMF_WSP 
TX_GMF_WLEV 
TX_GMF_RP 
TX_GMF_RSTP 
TX_GMF_RLEV 
ECU_AE_THR 
ECU_TXFF_LEV 
ECU_JUMBO_WM 

Definition at line 835 of file sky2.h.

00835      {
00836         TX_GMF_EA       = 0x0d40,/* 32 bit      Tx GMAC FIFO End Address */
00837         TX_GMF_AE_THR   = 0x0d44,/* 32 bit      Tx GMAC FIFO Almost Empty Thresh.*/
00838         TX_GMF_CTRL_T   = 0x0d48,/* 32 bit      Tx GMAC FIFO Control/Test */
00839 
00840         TX_GMF_WP       = 0x0d60,/* 32 bit      Tx GMAC FIFO Write Pointer */
00841         TX_GMF_WSP      = 0x0d64,/* 32 bit      Tx GMAC FIFO Write Shadow Ptr. */
00842         TX_GMF_WLEV     = 0x0d68,/* 32 bit      Tx GMAC FIFO Write Level */
00843 
00844         TX_GMF_RP       = 0x0d70,/* 32 bit      Tx GMAC FIFO Read Pointer */
00845         TX_GMF_RSTP     = 0x0d74,/* 32 bit      Tx GMAC FIFO Restart Pointer */
00846         TX_GMF_RLEV     = 0x0d78,/* 32 bit      Tx GMAC FIFO Read Level */
00847 
00848         /* Threshold values for Yukon-EC Ultra and Extreme */
00849         ECU_AE_THR      = 0x0070, /* Almost Empty Threshold */
00850         ECU_TXFF_LEV    = 0x01a0, /* Tx BMU FIFO Level */
00851         ECU_JUMBO_WM    = 0x0080, /* Jumbo Mode Watermark */
00852 };

anonymous enum

Enumerator:
B28_DPT_INI 
B28_DPT_VAL 
B28_DPT_CTRL 
B28_DPT_TST 

Definition at line 855 of file sky2.h.

00855      {
00856         B28_DPT_INI     = 0x0e00,/* 24 bit      Descriptor Poll Timer Init Val */
00857         B28_DPT_VAL     = 0x0e04,/* 24 bit      Descriptor Poll Timer Curr Val */
00858         B28_DPT_CTRL    = 0x0e08,/*  8 bit      Descriptor Poll Timer Ctrl Reg */
00859 
00860         B28_DPT_TST     = 0x0e0a,/*  8 bit      Descriptor Poll Timer Test Reg */
00861 };

anonymous enum

Enumerator:
GMAC_TI_ST_VAL 
GMAC_TI_ST_CTRL 
GMAC_TI_ST_TST 

Definition at line 864 of file sky2.h.

00864      {
00865         GMAC_TI_ST_VAL  = 0x0e14,/* 32 bit      Time Stamp Timer Curr Val */
00866         GMAC_TI_ST_CTRL = 0x0e18,/*  8 bit      Time Stamp Timer Ctrl Reg */
00867         GMAC_TI_ST_TST  = 0x0e1a,/*  8 bit      Time Stamp Timer Test Reg */
00868 };

anonymous enum

Enumerator:
POLL_CTRL 
POLL_LAST_IDX 
POLL_LIST_ADDR_LO 
POLL_LIST_ADDR_HI 

Definition at line 871 of file sky2.h.

00871      {
00872         POLL_CTRL       = 0x0e20, /* 32 bit     Polling Unit Control Reg */
00873         POLL_LAST_IDX   = 0x0e24,/* 16 bit      Polling Unit List Last Index */
00874 
00875         POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit     Poll. List Start Addr (low) */
00876         POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit     Poll. List Start Addr (high) */
00877 };

anonymous enum

Enumerator:
SMB_CFG 
SMB_CSR 

Definition at line 879 of file sky2.h.

00879      {
00880         SMB_CFG          = 0x0e40, /* 32 bit    SMBus Config Register */
00881         SMB_CSR          = 0x0e44, /* 32 bit    SMBus Control/Status Register */
00882 };

anonymous enum

Enumerator:
CPU_WDOG 
CPU_CNTR 
CPU_TIM 
CPU_AHB_ADDR 
CPU_AHB_WDATA 
CPU_AHB_RDATA 
HCU_MAP_BASE 
CPU_AHB_CTRL 
HCU_CCSR 
HCU_HCSR 

Definition at line 884 of file sky2.h.

00884      {
00885         CPU_WDOG         = 0x0e48, /* 32 bit    Watchdog Register  */
00886         CPU_CNTR         = 0x0e4C, /* 32 bit    Counter Register  */
00887         CPU_TIM          = 0x0e50,/* 32 bit     Timer Compare Register  */
00888         CPU_AHB_ADDR     = 0x0e54, /* 32 bit    CPU AHB Debug  Register  */
00889         CPU_AHB_WDATA    = 0x0e58, /* 32 bit    CPU AHB Debug  Register  */
00890         CPU_AHB_RDATA    = 0x0e5C, /* 32 bit    CPU AHB Debug  Register  */
00891         HCU_MAP_BASE     = 0x0e60, /* 32 bit    Reset Mapping Base */
00892         CPU_AHB_CTRL     = 0x0e64, /* 32 bit    CPU AHB Debug  Register  */
00893         HCU_CCSR         = 0x0e68, /* 32 bit    CPU Control and Status Register */
00894         HCU_HCSR         = 0x0e6C, /* 32 bit    Host Control and Status Register */
00895 };

anonymous enum

Enumerator:
B28_Y2_SMB_CONFIG 
B28_Y2_SMB_CSD_REG 
B28_Y2_ASF_IRQ_V_BASE 
B28_Y2_ASF_STAT_CMD 
B28_Y2_ASF_HOST_COM 
B28_Y2_DATA_REG_1 
B28_Y2_DATA_REG_2 
B28_Y2_DATA_REG_3 
B28_Y2_DATA_REG_4 

Definition at line 898 of file sky2.h.

00898      {
00899         B28_Y2_SMB_CONFIG  = 0x0e40,/* 32 bit   ASF SMBus Config Register */
00900         B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit   ASF SMB Control/Status/Data */
00901         B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit  ASF IRQ Vector Base */
00902 
00903         B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit   ASF Status and Command Reg */
00904         B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit   ASF Host Communication Reg */
00905         B28_Y2_DATA_REG_1  = 0x0e70,/* 32 bit   ASF/Host Data Register 1 */
00906         B28_Y2_DATA_REG_2  = 0x0e74,/* 32 bit   ASF/Host Data Register 2 */
00907         B28_Y2_DATA_REG_3  = 0x0e78,/* 32 bit   ASF/Host Data Register 3 */
00908         B28_Y2_DATA_REG_4  = 0x0e7c,/* 32 bit   ASF/Host Data Register 4 */
00909 };

anonymous enum

Enumerator:
STAT_CTRL 
STAT_LAST_IDX 
STAT_LIST_ADDR_LO 
STAT_LIST_ADDR_HI 
STAT_TXA1_RIDX 
STAT_TXS1_RIDX 
STAT_TXA2_RIDX 
STAT_TXS2_RIDX 
STAT_TX_IDX_TH 
STAT_PUT_IDX 
STAT_FIFO_WP 
STAT_FIFO_RP 
STAT_FIFO_RSP 
STAT_FIFO_LEVEL 
STAT_FIFO_SHLVL 
STAT_FIFO_WM 
STAT_FIFO_ISR_WM 
STAT_LEV_TIMER_INI 
STAT_LEV_TIMER_CNT 
STAT_LEV_TIMER_CTRL 
STAT_LEV_TIMER_TEST 
STAT_TX_TIMER_INI 
STAT_TX_TIMER_CNT 
STAT_TX_TIMER_CTRL 
STAT_TX_TIMER_TEST 
STAT_ISR_TIMER_INI 
STAT_ISR_TIMER_CNT 
STAT_ISR_TIMER_CTRL 
STAT_ISR_TIMER_TEST 

Definition at line 912 of file sky2.h.

00912      {
00913         STAT_CTRL       = 0x0e80,/* 32 bit      Status BMU Control Reg */
00914         STAT_LAST_IDX   = 0x0e84,/* 16 bit      Status BMU Last Index */
00915 
00916         STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit     Status List Start Addr (low) */
00917         STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit     Status List Start Addr (high) */
00918         STAT_TXA1_RIDX  = 0x0e90,/* 16 bit      Status TxA1 Report Index Reg */
00919         STAT_TXS1_RIDX  = 0x0e92,/* 16 bit      Status TxS1 Report Index Reg */
00920         STAT_TXA2_RIDX  = 0x0e94,/* 16 bit      Status TxA2 Report Index Reg */
00921         STAT_TXS2_RIDX  = 0x0e96,/* 16 bit      Status TxS2 Report Index Reg */
00922         STAT_TX_IDX_TH  = 0x0e98,/* 16 bit      Status Tx Index Threshold Reg */
00923         STAT_PUT_IDX    = 0x0e9c,/* 16 bit      Status Put Index Reg */
00924 
00925 /* FIFO Control/Status Registers (Yukon-2 only)*/
00926         STAT_FIFO_WP    = 0x0ea0,/*  8 bit      Status FIFO Write Pointer Reg */
00927         STAT_FIFO_RP    = 0x0ea4,/*  8 bit      Status FIFO Read Pointer Reg */
00928         STAT_FIFO_RSP   = 0x0ea6,/*  8 bit      Status FIFO Read Shadow Ptr */
00929         STAT_FIFO_LEVEL = 0x0ea8,/*  8 bit      Status FIFO Level Reg */
00930         STAT_FIFO_SHLVL = 0x0eaa,/*  8 bit      Status FIFO Shadow Level Reg */
00931         STAT_FIFO_WM    = 0x0eac,/*  8 bit      Status FIFO Watermark Reg */
00932         STAT_FIFO_ISR_WM= 0x0ead,/*  8 bit      Status FIFO ISR Watermark Reg */
00933 
00934 /* Level and ISR Timer Registers (Yukon-2 only)*/
00935         STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit    Level Timer Init. Value Reg */
00936         STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit    Level Timer Counter Reg */
00937         STAT_LEV_TIMER_CTRL= 0x0eb8,/*  8 bit   Level Timer Control Reg */
00938         STAT_LEV_TIMER_TEST= 0x0eb9,/*  8 bit   Level Timer Test Reg */
00939         STAT_TX_TIMER_INI  = 0x0ec0,/* 32 bit   Tx Timer Init. Value Reg */
00940         STAT_TX_TIMER_CNT  = 0x0ec4,/* 32 bit   Tx Timer Counter Reg */
00941         STAT_TX_TIMER_CTRL = 0x0ec8,/*  8 bit   Tx Timer Control Reg */
00942         STAT_TX_TIMER_TEST = 0x0ec9,/*  8 bit   Tx Timer Test Reg */
00943         STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit   ISR Timer Init. Value Reg */
00944         STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit   ISR Timer Counter Reg */
00945         STAT_ISR_TIMER_CTRL= 0x0ed8,/*  8 bit   ISR Timer Control Reg */
00946         STAT_ISR_TIMER_TEST= 0x0ed9,/*  8 bit   ISR Timer Test Reg */
00947 };

anonymous enum

Enumerator:
LINKLED_OFF 
LINKLED_ON 
LINKLED_LINKSYNC_OFF 
LINKLED_LINKSYNC_ON 
LINKLED_BLINK_OFF 
LINKLED_BLINK_ON 

Definition at line 949 of file sky2.h.

00949      {
00950         LINKLED_OFF          = 0x01,
00951         LINKLED_ON           = 0x02,
00952         LINKLED_LINKSYNC_OFF = 0x04,
00953         LINKLED_LINKSYNC_ON  = 0x08,
00954         LINKLED_BLINK_OFF    = 0x10,
00955         LINKLED_BLINK_ON     = 0x20,
00956 };

anonymous enum

Enumerator:
GMAC_CTRL 
GPHY_CTRL 
GMAC_IRQ_SRC 
GMAC_IRQ_MSK 
GMAC_LINK_CTRL 
WOL_CTRL_STAT 
WOL_MATCH_CTL 
WOL_MATCH_RES 
WOL_MAC_ADDR 
WOL_PATT_RPTR 
WOL_PATT_LEN_LO 
WOL_PATT_LEN_HI 
WOL_PATT_CNT_0 
WOL_PATT_CNT_4 

Definition at line 959 of file sky2.h.

00959      {
00960         GMAC_CTRL       = 0x0f00,/* 32 bit      GMAC Control Reg */
00961         GPHY_CTRL       = 0x0f04,/* 32 bit      GPHY Control Reg */
00962         GMAC_IRQ_SRC    = 0x0f08,/*  8 bit      GMAC Interrupt Source Reg */
00963         GMAC_IRQ_MSK    = 0x0f0c,/*  8 bit      GMAC Interrupt Mask Reg */
00964         GMAC_LINK_CTRL  = 0x0f10,/* 16 bit      Link Control Reg */
00965 
00966 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
00967         WOL_CTRL_STAT   = 0x0f20,/* 16 bit      WOL Control/Status Reg */
00968         WOL_MATCH_CTL   = 0x0f22,/*  8 bit      WOL Match Control Reg */
00969         WOL_MATCH_RES   = 0x0f23,/*  8 bit      WOL Match Result Reg */
00970         WOL_MAC_ADDR    = 0x0f24,/* 32 bit      WOL MAC Address */
00971         WOL_PATT_RPTR   = 0x0f2c,/*  8 bit      WOL Pattern Read Pointer */
00972 
00973 /* WOL Pattern Length Registers (YUKON only) */
00974         WOL_PATT_LEN_LO = 0x0f30,/* 32 bit      WOL Pattern Length 3..0 */
00975         WOL_PATT_LEN_HI = 0x0f34,/* 24 bit      WOL Pattern Length 6..4 */
00976 
00977 /* WOL Pattern Counter Registers (YUKON only) */
00978         WOL_PATT_CNT_0  = 0x0f38,/* 32 bit      WOL Pattern Counter 3..0 */
00979         WOL_PATT_CNT_4  = 0x0f3c,/* 24 bit      WOL Pattern Counter 6..4 */
00980 };

anonymous enum

Enumerator:
WOL_PATT_RAM_1 
WOL_PATT_RAM_2 

Definition at line 983 of file sky2.h.

00983      {
00984         WOL_PATT_RAM_1  = 0x1000,/*  WOL Pattern RAM Link 1 */
00985         WOL_PATT_RAM_2  = 0x1400,/*  WOL Pattern RAM Link 2 */
00986 };

anonymous enum

Enumerator:
BASE_GMAC_1 
BASE_GMAC_2 

Definition at line 989 of file sky2.h.

00989      {
00990         BASE_GMAC_1     = 0x2800,/* GMAC 1 registers */
00991         BASE_GMAC_2     = 0x3800,/* GMAC 2 registers */
00992 };

anonymous enum

Enumerator:
PHY_MARV_CTRL 
PHY_MARV_STAT 
PHY_MARV_ID0 
PHY_MARV_ID1 
PHY_MARV_AUNE_ADV 
PHY_MARV_AUNE_LP 
PHY_MARV_AUNE_EXP 
PHY_MARV_NEPG 
PHY_MARV_NEPG_LP 
PHY_MARV_1000T_CTRL 
PHY_MARV_1000T_STAT 
PHY_MARV_EXT_STAT 
PHY_MARV_PHY_CTRL 
PHY_MARV_PHY_STAT 
PHY_MARV_INT_MASK 
PHY_MARV_INT_STAT 
PHY_MARV_EXT_CTRL 
PHY_MARV_RXE_CNT 
PHY_MARV_EXT_ADR 
PHY_MARV_PORT_IRQ 
PHY_MARV_LED_CTRL 
PHY_MARV_LED_OVER 
PHY_MARV_EXT_CTRL_2 
PHY_MARV_EXT_P_STAT 
PHY_MARV_CABLE_DIAG 
PHY_MARV_PAGE_ADDR 
PHY_MARV_PAGE_DATA 
PHY_MARV_FE_LED_PAR 
PHY_MARV_FE_LED_SER 
PHY_MARV_FE_VCT_TX 
PHY_MARV_FE_VCT_RX 
PHY_MARV_FE_SPEC_2 

Definition at line 997 of file sky2.h.

00997      {
00998         PHY_MARV_CTRL           = 0x00,/* 16 bit r/w    PHY Control Register */
00999         PHY_MARV_STAT           = 0x01,/* 16 bit r/o    PHY Status Register */
01000         PHY_MARV_ID0            = 0x02,/* 16 bit r/o    PHY ID0 Register */
01001         PHY_MARV_ID1            = 0x03,/* 16 bit r/o    PHY ID1 Register */
01002         PHY_MARV_AUNE_ADV       = 0x04,/* 16 bit r/w    Auto-Neg. Advertisement */
01003         PHY_MARV_AUNE_LP        = 0x05,/* 16 bit r/o    Link Part Ability Reg */
01004         PHY_MARV_AUNE_EXP       = 0x06,/* 16 bit r/o    Auto-Neg. Expansion Reg */
01005         PHY_MARV_NEPG           = 0x07,/* 16 bit r/w    Next Page Register */
01006         PHY_MARV_NEPG_LP        = 0x08,/* 16 bit r/o    Next Page Link Partner */
01007         /* Marvel-specific registers */
01008         PHY_MARV_1000T_CTRL     = 0x09,/* 16 bit r/w    1000Base-T Control Reg */
01009         PHY_MARV_1000T_STAT     = 0x0a,/* 16 bit r/o    1000Base-T Status Reg */
01010         PHY_MARV_EXT_STAT       = 0x0f,/* 16 bit r/o    Extended Status Reg */
01011         PHY_MARV_PHY_CTRL       = 0x10,/* 16 bit r/w    PHY Specific Ctrl Reg */
01012         PHY_MARV_PHY_STAT       = 0x11,/* 16 bit r/o    PHY Specific Stat Reg */
01013         PHY_MARV_INT_MASK       = 0x12,/* 16 bit r/w    Interrupt Mask Reg */
01014         PHY_MARV_INT_STAT       = 0x13,/* 16 bit r/o    Interrupt Status Reg */
01015         PHY_MARV_EXT_CTRL       = 0x14,/* 16 bit r/w    Ext. PHY Specific Ctrl */
01016         PHY_MARV_RXE_CNT        = 0x15,/* 16 bit r/w    Receive Error Counter */
01017         PHY_MARV_EXT_ADR        = 0x16,/* 16 bit r/w    Ext. Ad. for Cable Diag. */
01018         PHY_MARV_PORT_IRQ       = 0x17,/* 16 bit r/o    Port 0 IRQ (88E1111 only) */
01019         PHY_MARV_LED_CTRL       = 0x18,/* 16 bit r/w    LED Control Reg */
01020         PHY_MARV_LED_OVER       = 0x19,/* 16 bit r/w    Manual LED Override Reg */
01021         PHY_MARV_EXT_CTRL_2     = 0x1a,/* 16 bit r/w    Ext. PHY Specific Ctrl 2 */
01022         PHY_MARV_EXT_P_STAT     = 0x1b,/* 16 bit r/w    Ext. PHY Spec. Stat Reg */
01023         PHY_MARV_CABLE_DIAG     = 0x1c,/* 16 bit r/o    Cable Diagnostic Reg */
01024         PHY_MARV_PAGE_ADDR      = 0x1d,/* 16 bit r/w    Extended Page Address Reg */
01025         PHY_MARV_PAGE_DATA      = 0x1e,/* 16 bit r/w    Extended Page Data Reg */
01026 
01027 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
01028         PHY_MARV_FE_LED_PAR     = 0x16,/* 16 bit r/w    LED Parallel Select Reg. */
01029         PHY_MARV_FE_LED_SER     = 0x17,/* 16 bit r/w    LED Stream Select S. LED */
01030         PHY_MARV_FE_VCT_TX      = 0x1a,/* 16 bit r/w    VCT Reg. for TXP/N Pins */
01031         PHY_MARV_FE_VCT_RX      = 0x1b,/* 16 bit r/o    VCT Reg. for RXP/N Pins */
01032         PHY_MARV_FE_SPEC_2      = 0x1c,/* 16 bit r/w    Specific Control Reg. 2 */
01033 };

anonymous enum

Enumerator:
PHY_CT_RESET 
PHY_CT_LOOP 
PHY_CT_SPS_LSB 
PHY_CT_ANE 
PHY_CT_PDOWN 
PHY_CT_ISOL 
PHY_CT_RE_CFG 
PHY_CT_DUP_MD 
PHY_CT_COL_TST 
PHY_CT_SPS_MSB 

Definition at line 1035 of file sky2.h.

01035      {
01036         PHY_CT_RESET    = 1<<15, /* Bit 15: (sc)        clear all PHY related regs */
01037         PHY_CT_LOOP     = 1<<14, /* Bit 14:     enable Loopback over PHY */
01038         PHY_CT_SPS_LSB  = 1<<13, /* Bit 13:     Speed select, lower bit */
01039         PHY_CT_ANE      = 1<<12, /* Bit 12:     Auto-Negotiation Enabled */
01040         PHY_CT_PDOWN    = 1<<11, /* Bit 11:     Power Down Mode */
01041         PHY_CT_ISOL     = 1<<10, /* Bit 10:     Isolate Mode */
01042         PHY_CT_RE_CFG   = 1<<9, /* Bit  9:      (sc) Restart Auto-Negotiation */
01043         PHY_CT_DUP_MD   = 1<<8, /* Bit  8:      Duplex Mode */
01044         PHY_CT_COL_TST  = 1<<7, /* Bit  7:      Collision Test enabled */
01045         PHY_CT_SPS_MSB  = 1<<6, /* Bit  6:      Speed select, upper bit */
01046 };

anonymous enum

Enumerator:
PHY_CT_SP1000 
PHY_CT_SP100 
PHY_CT_SP10 

Definition at line 1048 of file sky2.h.

01048      {
01049         PHY_CT_SP1000   = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
01050         PHY_CT_SP100    = PHY_CT_SPS_LSB, /* enable speed of  100 Mbps */
01051         PHY_CT_SP10     = 0,              /* enable speed of   10 Mbps */
01052 };

anonymous enum

Enumerator:
PHY_ST_EXT_ST 
PHY_ST_PRE_SUP 
PHY_ST_AN_OVER 
PHY_ST_REM_FLT 
PHY_ST_AN_CAP 
PHY_ST_LSYNC 
PHY_ST_JAB_DET 
PHY_ST_EXT_REG 

Definition at line 1054 of file sky2.h.

01054      {
01055         PHY_ST_EXT_ST   = 1<<8, /* Bit  8:      Extended Status Present */
01056 
01057         PHY_ST_PRE_SUP  = 1<<6, /* Bit  6:      Preamble Suppression */
01058         PHY_ST_AN_OVER  = 1<<5, /* Bit  5:      Auto-Negotiation Over */
01059         PHY_ST_REM_FLT  = 1<<4, /* Bit  4:      Remote Fault Condition Occured */
01060         PHY_ST_AN_CAP   = 1<<3, /* Bit  3:      Auto-Negotiation Capability */
01061         PHY_ST_LSYNC    = 1<<2, /* Bit  2:      Link Synchronized */
01062         PHY_ST_JAB_DET  = 1<<1, /* Bit  1:      Jabber Detected */
01063         PHY_ST_EXT_REG  = 1<<0, /* Bit  0:      Extended Register available */
01064 };

anonymous enum

Enumerator:
PHY_I1_OUI_MSK 
PHY_I1_MOD_NUM 
PHY_I1_REV_MSK 

Definition at line 1066 of file sky2.h.

01066      {
01067         PHY_I1_OUI_MSK  = 0x3f<<10, /* Bit 15..10:      Organization Unique ID */
01068         PHY_I1_MOD_NUM  = 0x3f<<4, /* Bit  9.. 4:       Model Number */
01069         PHY_I1_REV_MSK  = 0xf, /* Bit  3.. 0:   Revision Number */
01070 };

anonymous enum

Enumerator:
PHY_MARV_ID0_VAL 
PHY_BCOM_ID1_A1 
PHY_BCOM_ID1_B2 
PHY_BCOM_ID1_C0 
PHY_BCOM_ID1_C5 
PHY_MARV_ID1_B0 
PHY_MARV_ID1_B2 
PHY_MARV_ID1_C2 
PHY_MARV_ID1_Y2 
PHY_MARV_ID1_FE 
PHY_MARV_ID1_ECU 

Definition at line 1073 of file sky2.h.

01073      {
01074         PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
01075 
01076         PHY_BCOM_ID1_A1 = 0x6041,
01077         PHY_BCOM_ID1_B2 = 0x6043,
01078         PHY_BCOM_ID1_C0 = 0x6044,
01079         PHY_BCOM_ID1_C5 = 0x6047,
01080 
01081         PHY_MARV_ID1_B0 = 0x0C23, /* Yukon      (PHY 88E1011) */
01082         PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
01083         PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC   (PHY 88E1111) */
01084         PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2    (PHY 88E1112) */
01085         PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE   (PHY 88E3082 Rev.A1) */
01086         PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU  (PHY 88E1149 Rev.B2?) */
01087 };

anonymous enum

Enumerator:
PHY_AN_NXT_PG 
PHY_AN_ACK 
PHY_AN_RF 
PHY_AN_PAUSE_ASYM 
PHY_AN_PAUSE_CAP 
PHY_AN_100BASE4 
PHY_AN_100FULL 
PHY_AN_100HALF 
PHY_AN_10FULL 
PHY_AN_10HALF 
PHY_AN_CSMA 
PHY_AN_SEL 
PHY_AN_FULL 
PHY_AN_ALL 

Definition at line 1090 of file sky2.h.

01090      {
01091         PHY_AN_NXT_PG   = 1<<15, /* Bit 15:     Request Next Page */
01092         PHY_AN_ACK      = 1<<14, /* Bit 14:     (ro) Acknowledge Received */
01093         PHY_AN_RF       = 1<<13, /* Bit 13:     Remote Fault Bits */
01094 
01095         PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11:    Try for asymmetric */
01096         PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10:    Try for pause */
01097         PHY_AN_100BASE4 = 1<<9, /* Bit 9:       Try for 100mbps 4k packets */
01098         PHY_AN_100FULL  = 1<<8, /* Bit 8:       Try for 100mbps full-duplex */
01099         PHY_AN_100HALF  = 1<<7, /* Bit 7:       Try for 100mbps half-duplex */
01100         PHY_AN_10FULL   = 1<<6, /* Bit 6:       Try for 10mbps full-duplex */
01101         PHY_AN_10HALF   = 1<<5, /* Bit 5:       Try for 10mbps half-duplex */
01102         PHY_AN_CSMA     = 1<<0, /* Bit 0:       Only selector supported */
01103         PHY_AN_SEL      = 0x1f, /* Bit 4..0:    Selector Field, 00001=Ethernet*/
01104         PHY_AN_FULL     = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
01105         PHY_AN_ALL      = PHY_AN_10HALF | PHY_AN_10FULL |
01106                           PHY_AN_100HALF | PHY_AN_100FULL,
01107 };

anonymous enum

Enumerator:
PHY_B_1000S_MSF 
PHY_B_1000S_MSR 
PHY_B_1000S_LRS 
PHY_B_1000S_RRS 
PHY_B_1000S_LP_FD 
PHY_B_1000S_LP_HD 
PHY_B_1000S_IEC 

Definition at line 1111 of file sky2.h.

01111      {
01112         PHY_B_1000S_MSF = 1<<15, /* Bit 15:     Master/Slave Fault */
01113         PHY_B_1000S_MSR = 1<<14, /* Bit 14:     Master/Slave Result */
01114         PHY_B_1000S_LRS = 1<<13, /* Bit 13:     Local Receiver Status */
01115         PHY_B_1000S_RRS = 1<<12, /* Bit 12:     Remote Receiver Status */
01116         PHY_B_1000S_LP_FD       = 1<<11, /* Bit 11:     Link Partner can FD */
01117         PHY_B_1000S_LP_HD       = 1<<10, /* Bit 10:     Link Partner can HD */
01118                                                                         /* Bit  9..8:   reserved */
01119         PHY_B_1000S_IEC = 0xff, /* Bit  7..0:   Idle Error Count */
01120 };

anonymous enum

Marvell-Specific.

Enumerator:
PHY_M_AN_NXT_PG 
PHY_M_AN_ACK 
PHY_M_AN_RF 
PHY_M_AN_ASP 
PHY_M_AN_PC 
PHY_M_AN_100_T4 
PHY_M_AN_100_FD 
PHY_M_AN_100_HD 
PHY_M_AN_10_FD 
PHY_M_AN_10_HD 
PHY_M_AN_SEL_MSK 

Definition at line 1123 of file sky2.h.

01123      {
01124         PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
01125         PHY_M_AN_ACK    = 1<<14, /* (ro)        Acknowledge Received */
01126         PHY_M_AN_RF     = 1<<13, /* Remote Fault */
01127 
01128         PHY_M_AN_ASP    = 1<<11, /* Asymmetric Pause */
01129         PHY_M_AN_PC     = 1<<10, /* MAC Pause implemented */
01130         PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
01131         PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
01132         PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
01133         PHY_M_AN_10_FD  = 1<<6, /* Advertise 10Base-TX Full Duplex */
01134         PHY_M_AN_10_HD  = 1<<5, /* Advertise 10Base-TX Half Duplex */
01135         PHY_M_AN_SEL_MSK =0x1f<<4,      /* Bit  4.. 0: Selector Field Mask */
01136 };

anonymous enum

Enumerator:
PHY_M_AN_ASP_X 
PHY_M_AN_PC_X 
PHY_M_AN_1000X_AHD 
PHY_M_AN_1000X_AFD 

Definition at line 1139 of file sky2.h.

01139      {
01140         PHY_M_AN_ASP_X  = 1<<8, /* Asymmetric Pause */
01141         PHY_M_AN_PC_X   = 1<<7, /* MAC Pause implemented */
01142         PHY_M_AN_1000X_AHD      = 1<<6, /* Advertise 10000Base-X Half Duplex */
01143         PHY_M_AN_1000X_AFD      = 1<<5, /* Advertise 10000Base-X Full Duplex */
01144 };

anonymous enum

Enumerator:
PHY_M_P_NO_PAUSE_X 
PHY_M_P_SYM_MD_X 
PHY_M_P_ASYM_MD_X 
PHY_M_P_BOTH_MD_X 

Definition at line 1147 of file sky2.h.

01147      {
01148         PHY_M_P_NO_PAUSE_X      = 0<<7,/* Bit  8.. 7:   no Pause Mode */
01149         PHY_M_P_SYM_MD_X        = 1<<7, /* Bit  8.. 7:  symmetric Pause Mode */
01150         PHY_M_P_ASYM_MD_X       = 2<<7,/* Bit  8.. 7:   asymmetric Pause Mode */
01151         PHY_M_P_BOTH_MD_X       = 3<<7,/* Bit  8.. 7:   both Pause Mode */
01152 };

anonymous enum

Enumerator:
PHY_M_1000C_TEST 
PHY_M_1000C_MSE 
PHY_M_1000C_MSC 
PHY_M_1000C_MPD 
PHY_M_1000C_AFD 
PHY_M_1000C_AHD 

Definition at line 1155 of file sky2.h.

01155      {
01156         PHY_M_1000C_TEST        = 7<<13,/* Bit 15..13:  Test Modes */
01157         PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
01158         PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
01159         PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
01160         PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
01161         PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
01162 };

anonymous enum

Enumerator:
PHY_M_PC_TX_FFD_MSK 
PHY_M_PC_RX_FFD_MSK 
PHY_M_PC_ASS_CRS_TX 
PHY_M_PC_FL_GOOD 
PHY_M_PC_EN_DET_MSK 
PHY_M_PC_ENA_EXT_D 
PHY_M_PC_MDIX_MSK 
PHY_M_PC_DIS_125CLK 
PHY_M_PC_MAC_POW_UP 
PHY_M_PC_SQE_T_ENA 
PHY_M_PC_POL_R_DIS 
PHY_M_PC_DIS_JABBER 

Definition at line 1165 of file sky2.h.

01165      {
01166         PHY_M_PC_TX_FFD_MSK     = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
01167         PHY_M_PC_RX_FFD_MSK     = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
01168         PHY_M_PC_ASS_CRS_TX     = 1<<11, /* Assert CRS on Transmit */
01169         PHY_M_PC_FL_GOOD        = 1<<10, /* Force Link Good */
01170         PHY_M_PC_EN_DET_MSK     = 3<<8,/* Bit  9.. 8: Energy Detect Mask */
01171         PHY_M_PC_ENA_EXT_D      = 1<<7, /* Enable Ext. Distance (10BT) */
01172         PHY_M_PC_MDIX_MSK       = 3<<5,/* Bit  6.. 5: MDI/MDIX Config. Mask */
01173         PHY_M_PC_DIS_125CLK     = 1<<4, /* Disable 125 CLK */
01174         PHY_M_PC_MAC_POW_UP     = 1<<3, /* MAC Power up */
01175         PHY_M_PC_SQE_T_ENA      = 1<<2, /* SQE Test Enabled */
01176         PHY_M_PC_POL_R_DIS      = 1<<1, /* Polarity Reversal Disabled */
01177         PHY_M_PC_DIS_JABBER     = 1<<0, /* Disable Jabber */
01178 };

anonymous enum

Enumerator:
PHY_M_PC_EN_DET 
PHY_M_PC_EN_DET_PLUS 

Definition at line 1180 of file sky2.h.

01180      {
01181         PHY_M_PC_EN_DET         = 2<<8, /* Energy Detect (Mode 1) */
01182         PHY_M_PC_EN_DET_PLUS    = 3<<8, /* Energy Detect Plus (Mode 2) */
01183 };

anonymous enum

Enumerator:
PHY_M_PC_MAN_MDI 
PHY_M_PC_MAN_MDIX 
PHY_M_PC_ENA_AUTO 

Definition at line 1187 of file sky2.h.

01187      {
01188         PHY_M_PC_MAN_MDI        = 0, /* 00 = Manual MDI configuration */
01189         PHY_M_PC_MAN_MDIX       = 1, /* 01 = Manual MDIX configuration */
01190         PHY_M_PC_ENA_AUTO       = 3, /* 11 = Enable Automatic Crossover */
01191 };

anonymous enum

Enumerator:
PHY_M_PC_COP_TX_DIS 
PHY_M_PC_POW_D_ENA 

Definition at line 1194 of file sky2.h.

01194      {
01195         PHY_M_PC_COP_TX_DIS     = 1<<3, /* Copper Transmitter Disable */
01196         PHY_M_PC_POW_D_ENA      = 1<<2, /* Power Down Enable */
01197 };

anonymous enum

Enumerator:
PHY_M_PC_ENA_DTE_DT 
PHY_M_PC_ENA_ENE_DT 
PHY_M_PC_DIS_NLP_CK 
PHY_M_PC_ENA_LIP_NP 
PHY_M_PC_DIS_NLP_GN 
PHY_M_PC_DIS_SCRAMB 
PHY_M_PC_DIS_FEFI 
PHY_M_PC_SH_TP_SEL 
PHY_M_PC_RX_FD_MSK 

Definition at line 1200 of file sky2.h.

01200      {
01201         PHY_M_PC_ENA_DTE_DT     = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
01202         PHY_M_PC_ENA_ENE_DT     = 1<<14, /* Enable Energy Detect (sense & pulse) */
01203         PHY_M_PC_DIS_NLP_CK     = 1<<13, /* Disable Normal Link Puls (NLP) Check */
01204         PHY_M_PC_ENA_LIP_NP     = 1<<12, /* Enable Link Partner Next Page Reg. */
01205         PHY_M_PC_DIS_NLP_GN     = 1<<11, /* Disable Normal Link Puls Generation */
01206 
01207         PHY_M_PC_DIS_SCRAMB     = 1<<9, /* Disable Scrambler */
01208         PHY_M_PC_DIS_FEFI       = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
01209 
01210         PHY_M_PC_SH_TP_SEL      = 1<<6, /* Shielded Twisted Pair Select */
01211         PHY_M_PC_RX_FD_MSK      = 3<<2,/* Bit  3.. 2: Rx FIFO Depth Mask */
01212 };

anonymous enum

Enumerator:
PHY_M_PS_SPEED_MSK 
PHY_M_PS_SPEED_1000 
PHY_M_PS_SPEED_100 
PHY_M_PS_SPEED_10 
PHY_M_PS_FULL_DUP 
PHY_M_PS_PAGE_REC 
PHY_M_PS_SPDUP_RES 
PHY_M_PS_LINK_UP 
PHY_M_PS_CABLE_MSK 
PHY_M_PS_MDI_X_STAT 
PHY_M_PS_DOWNS_STAT 
PHY_M_PS_ENDET_STAT 
PHY_M_PS_TX_P_EN 
PHY_M_PS_RX_P_EN 
PHY_M_PS_POL_REV 
PHY_M_PS_JABBER 

Definition at line 1215 of file sky2.h.

01215      {
01216         PHY_M_PS_SPEED_MSK      = 3<<14, /* Bit 15..14: Speed Mask */
01217         PHY_M_PS_SPEED_1000     = 1<<15, /*             10 = 1000 Mbps */
01218         PHY_M_PS_SPEED_100      = 1<<14, /*             01 =  100 Mbps */
01219         PHY_M_PS_SPEED_10       = 0,     /*             00 =   10 Mbps */
01220         PHY_M_PS_FULL_DUP       = 1<<13, /* Full Duplex */
01221         PHY_M_PS_PAGE_REC       = 1<<12, /* Page Received */
01222         PHY_M_PS_SPDUP_RES      = 1<<11, /* Speed & Duplex Resolved */
01223         PHY_M_PS_LINK_UP        = 1<<10, /* Link Up */
01224         PHY_M_PS_CABLE_MSK      = 7<<7,  /* Bit  9.. 7: Cable Length Mask */
01225         PHY_M_PS_MDI_X_STAT     = 1<<6,  /* MDI Crossover Stat (1=MDIX) */
01226         PHY_M_PS_DOWNS_STAT     = 1<<5,  /* Downshift Status (1=downsh.) */
01227         PHY_M_PS_ENDET_STAT     = 1<<4,  /* Energy Detect Status (1=act) */
01228         PHY_M_PS_TX_P_EN        = 1<<3,  /* Tx Pause Enabled */
01229         PHY_M_PS_RX_P_EN        = 1<<2,  /* Rx Pause Enabled */
01230         PHY_M_PS_POL_REV        = 1<<1,  /* Polarity Reversed */
01231         PHY_M_PS_JABBER         = 1<<0,  /* Jabber */
01232 };

anonymous enum

Enumerator:
PHY_M_PS_DTE_DETECT 
PHY_M_PS_RES_SPEED 

Definition at line 1237 of file sky2.h.

01237      {
01238         PHY_M_PS_DTE_DETECT     = 1<<15, /* Data Terminal Equipment (DTE) Detected */
01239         PHY_M_PS_RES_SPEED      = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
01240 };

anonymous enum

Enumerator:
PHY_M_IS_AN_ERROR 
PHY_M_IS_LSP_CHANGE 
PHY_M_IS_DUP_CHANGE 
PHY_M_IS_AN_PR 
PHY_M_IS_AN_COMPL 
PHY_M_IS_LST_CHANGE 
PHY_M_IS_SYMB_ERROR 
PHY_M_IS_FALSE_CARR 
PHY_M_IS_FIFO_ERROR 
PHY_M_IS_MDI_CHANGE 
PHY_M_IS_DOWNSH_DET 
PHY_M_IS_END_CHANGE 
PHY_M_IS_DTE_CHANGE 
PHY_M_IS_POL_CHANGE 
PHY_M_IS_JABBER 
PHY_M_DEF_MSK 
PHY_M_AN_MSK 

Definition at line 1242 of file sky2.h.

01242      {
01243         PHY_M_IS_AN_ERROR       = 1<<15, /* Auto-Negotiation Error */
01244         PHY_M_IS_LSP_CHANGE     = 1<<14, /* Link Speed Changed */
01245         PHY_M_IS_DUP_CHANGE     = 1<<13, /* Duplex Mode Changed */
01246         PHY_M_IS_AN_PR          = 1<<12, /* Page Received */
01247         PHY_M_IS_AN_COMPL       = 1<<11, /* Auto-Negotiation Completed */
01248         PHY_M_IS_LST_CHANGE     = 1<<10, /* Link Status Changed */
01249         PHY_M_IS_SYMB_ERROR     = 1<<9, /* Symbol Error */
01250         PHY_M_IS_FALSE_CARR     = 1<<8, /* False Carrier */
01251         PHY_M_IS_FIFO_ERROR     = 1<<7, /* FIFO Overflow/Underrun Error */
01252         PHY_M_IS_MDI_CHANGE     = 1<<6, /* MDI Crossover Changed */
01253         PHY_M_IS_DOWNSH_DET     = 1<<5, /* Downshift Detected */
01254         PHY_M_IS_END_CHANGE     = 1<<4, /* Energy Detect Changed */
01255 
01256         PHY_M_IS_DTE_CHANGE     = 1<<2, /* DTE Power Det. Status Changed */
01257         PHY_M_IS_POL_CHANGE     = 1<<1, /* Polarity Changed */
01258         PHY_M_IS_JABBER         = 1<<0, /* Jabber */
01259 
01260         PHY_M_DEF_MSK           = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
01261                                  | PHY_M_IS_DUP_CHANGE,
01262         PHY_M_AN_MSK           = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
01263 };

anonymous enum

Enumerator:
PHY_M_EC_ENA_BC_EXT 
PHY_M_EC_ENA_LIN_LB 
PHY_M_EC_DIS_LINK_P 
PHY_M_EC_M_DSC_MSK 
PHY_M_EC_S_DSC_MSK 
PHY_M_EC_M_DSC_MSK2 
PHY_M_EC_DOWN_S_ENA 
PHY_M_EC_RX_TIM_CT 
PHY_M_EC_MAC_S_MSK 
PHY_M_EC_FIB_AN_ENA 
PHY_M_EC_DTE_D_ENA 
PHY_M_EC_TX_TIM_CT 
PHY_M_EC_TRANS_DIS 

Definition at line 1267 of file sky2.h.

01267      {
01268         PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
01269         PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
01270 
01271         PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
01272         PHY_M_EC_M_DSC_MSK  = 3<<10, /* Bit 11..10:     Master Downshift Counter */
01273                                         /* (88E1011 only) */
01274         PHY_M_EC_S_DSC_MSK  = 3<<8,/* Bit  9.. 8:       Slave  Downshift Counter */
01275                                        /* (88E1011 only) */
01276         PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9:       Master Downshift Counter */
01277                                         /* (88E1111 only) */
01278         PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
01279                                         /* !!! Errata in spec. (1 = disable) */
01280         PHY_M_EC_RX_TIM_CT  = 1<<7, /* RGMII Rx Timing Control*/
01281         PHY_M_EC_MAC_S_MSK  = 7<<4,/* Bit  6.. 4:       Def. MAC interface speed */
01282         PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
01283         PHY_M_EC_DTE_D_ENA  = 1<<2, /* DTE Detect Enable (88E1111 only) */
01284         PHY_M_EC_TX_TIM_CT  = 1<<1, /* RGMII Tx Timing Control */
01285         PHY_M_EC_TRANS_DIS  = 1<<0, /* Transmitter Disable (88E1111 only) */};

anonymous enum

Enumerator:
PHY_M_PC_DIS_LINK_Pa 
PHY_M_PC_DSC_MSK 
PHY_M_PC_DOWN_S_ENA 

Definition at line 1297 of file sky2.h.

01297      {
01298         PHY_M_PC_DIS_LINK_Pa    = 1<<15,/* Disable Link Pulses */
01299         PHY_M_PC_DSC_MSK        = 7<<12,/* Bit 14..12:  Downshift Counter */
01300         PHY_M_PC_DOWN_S_ENA     = 1<<11,/* Downshift Enable */
01301 };

anonymous enum

Enumerator:
MAC_TX_CLK_0_MHZ 
MAC_TX_CLK_2_5_MHZ 
MAC_TX_CLK_25_MHZ 

Definition at line 1306 of file sky2.h.

01306      {
01307         MAC_TX_CLK_0_MHZ        = 2,
01308         MAC_TX_CLK_2_5_MHZ      = 6,
01309         MAC_TX_CLK_25_MHZ       = 7,
01310 };

anonymous enum

Enumerator:
PHY_M_LEDC_DIS_LED 
PHY_M_LEDC_PULS_MSK 
PHY_M_LEDC_F_INT 
PHY_M_LEDC_BL_R_MSK 
PHY_M_LEDC_DP_C_LSB 
PHY_M_LEDC_TX_C_LSB 
PHY_M_LEDC_LK_C_MSK 

Definition at line 1313 of file sky2.h.

01313      {
01314         PHY_M_LEDC_DIS_LED      = 1<<15, /* Disable LED */
01315         PHY_M_LEDC_PULS_MSK     = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
01316         PHY_M_LEDC_F_INT        = 1<<11, /* Force Interrupt */
01317         PHY_M_LEDC_BL_R_MSK     = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
01318         PHY_M_LEDC_DP_C_LSB     = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
01319         PHY_M_LEDC_TX_C_LSB     = 1<<6, /* Tx Control (LSB, 88E1111 only) */
01320         PHY_M_LEDC_LK_C_MSK     = 7<<3,/* Bit  5.. 3: Link Control Mask */
01321                                         /* (88E1111 only) */
01322 };

anonymous enum

Enumerator:
PHY_M_LEDC_LINK_MSK 
PHY_M_LEDC_DP_CTRL 
PHY_M_LEDC_DP_C_MSB 
PHY_M_LEDC_RX_CTRL 
PHY_M_LEDC_TX_CTRL 
PHY_M_LEDC_TX_C_MSB 

Definition at line 1324 of file sky2.h.

01324      {
01325         PHY_M_LEDC_LINK_MSK     = 3<<3,/* Bit  4.. 3: Link Control Mask */
01326                                                                         /* (88E1011 only) */
01327         PHY_M_LEDC_DP_CTRL      = 1<<2, /* Duplex Control */
01328         PHY_M_LEDC_DP_C_MSB     = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
01329         PHY_M_LEDC_RX_CTRL      = 1<<1, /* Rx Activity / Link */
01330         PHY_M_LEDC_TX_CTRL      = 1<<0, /* Tx Activity / Link */
01331         PHY_M_LEDC_TX_C_MSB     = 1<<0, /* Tx Control (MSB, 88E1111 only) */
01332 };

anonymous enum

Enumerator:
PHY_M_POLC_LS1M_MSK 
PHY_M_POLC_IS0M_MSK 
PHY_M_POLC_LOS_MSK 
PHY_M_POLC_INIT_MSK 
PHY_M_POLC_STA1_MSK 
PHY_M_POLC_STA0_MSK 

Definition at line 1337 of file sky2.h.

01337      {
01338         PHY_M_POLC_LS1M_MSK     = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
01339         PHY_M_POLC_IS0M_MSK     = 0xf<<8,  /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
01340         PHY_M_POLC_LOS_MSK      = 0x3<<6,  /* Bit  7.. 6: LOS Pol. Ctrl. Mask */
01341         PHY_M_POLC_INIT_MSK     = 0x3<<4,  /* Bit  5.. 4: INIT Pol. Ctrl. Mask */
01342         PHY_M_POLC_STA1_MSK     = 0x3<<2,  /* Bit  3.. 2: STAT1 Pol. Ctrl. Mask */
01343         PHY_M_POLC_STA0_MSK     = 0x3,     /* Bit  1.. 0: STAT0 Pol. Ctrl. Mask */
01344 };

anonymous enum

Enumerator:
PULS_NO_STR 
PULS_21MS 
PULS_42MS 
PULS_84MS 
PULS_170MS 
PULS_340MS 
PULS_670MS 
PULS_1300MS 

Definition at line 1353 of file sky2.h.

01353      {
01354         PULS_NO_STR     = 0,/* no pulse stretching */
01355         PULS_21MS       = 1,/* 21 ms to 42 ms */
01356         PULS_42MS       = 2,/* 42 ms to 84 ms */
01357         PULS_84MS       = 3,/* 84 ms to 170 ms */
01358         PULS_170MS      = 4,/* 170 ms to 340 ms */
01359         PULS_340MS      = 5,/* 340 ms to 670 ms */
01360         PULS_670MS      = 6,/* 670 ms to 1.3 s */
01361         PULS_1300MS     = 7,/* 1.3 s to 2.7 s */
01362 };

anonymous enum

Enumerator:
BLINK_42MS 
BLINK_84MS 
BLINK_170MS 
BLINK_340MS 
BLINK_670MS 

Definition at line 1366 of file sky2.h.

01366      {
01367         BLINK_42MS      = 0,/* 42 ms */
01368         BLINK_84MS      = 1,/* 84 ms */
01369         BLINK_170MS     = 2,/* 170 ms */
01370         BLINK_340MS     = 3,/* 340 ms */
01371         BLINK_670MS     = 4,/* 670 ms */
01372 };

enum led_mode

Enumerator:
LED_MODE_OFF 
LED_MODE_ON 
LED_MODE_TST 
MO_LED_NORM 
MO_LED_BLINK 
MO_LED_OFF 
MO_LED_ON 

Definition at line 1384 of file sky2.h.

01384               {
01385         MO_LED_NORM  = 0,
01386         MO_LED_BLINK = 1,
01387         MO_LED_OFF   = 2,
01388         MO_LED_ON    = 3,
01389 };

anonymous enum

Enumerator:
PHY_M_EC2_FI_IMPED 
PHY_M_EC2_FO_IMPED 
PHY_M_EC2_FO_M_CLK 
PHY_M_EC2_FO_BOOST 
PHY_M_EC2_FO_AM_MSK 

Definition at line 1392 of file sky2.h.

01392      {
01393         PHY_M_EC2_FI_IMPED      = 1<<6, /* Fiber Input  Impedance */
01394         PHY_M_EC2_FO_IMPED      = 1<<5, /* Fiber Output Impedance */
01395         PHY_M_EC2_FO_M_CLK      = 1<<4, /* Fiber Mode Clock Enable */
01396         PHY_M_EC2_FO_BOOST      = 1<<3, /* Fiber Output Boost */
01397         PHY_M_EC2_FO_AM_MSK     = 7,/* Bit  2.. 0:      Fiber Output Amplitude */
01398 };

anonymous enum

Enumerator:
PHY_M_FC_AUTO_SEL 
PHY_M_FC_AN_REG_ACC 
PHY_M_FC_RESOLUTION 
PHY_M_SER_IF_AN_BP 
PHY_M_SER_IF_BP_ST 
PHY_M_IRQ_POLARITY 
PHY_M_DIS_AUT_MED 
PHY_M_UNDOC1 
PHY_M_DTE_POW_STAT 
PHY_M_MODE_MASK 

Definition at line 1401 of file sky2.h.

01401      {
01402         PHY_M_FC_AUTO_SEL       = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
01403         PHY_M_FC_AN_REG_ACC     = 1<<14, /* Fiber/Copper AN Reg. Access */
01404         PHY_M_FC_RESOLUTION     = 1<<13, /* Fiber/Copper Resolution */
01405         PHY_M_SER_IF_AN_BP      = 1<<12, /* Ser. IF AN Bypass Enable */
01406         PHY_M_SER_IF_BP_ST      = 1<<11, /* Ser. IF AN Bypass Status */
01407         PHY_M_IRQ_POLARITY      = 1<<10, /* IRQ polarity */
01408         PHY_M_DIS_AUT_MED       = 1<<9, /* Disable Aut. Medium Reg. Selection */
01409         /* (88E1111 only) */
01410 
01411         PHY_M_UNDOC1            = 1<<7, /* undocumented bit !! */
01412         PHY_M_DTE_POW_STAT      = 1<<4, /* DTE Power Status (88E1111 only) */
01413         PHY_M_MODE_MASK = 0xf, /* Bit  3.. 0: copy of HWCFG MODE[3:0] */
01414 };

anonymous enum

Enumerator:
PHY_M_FELP_LED2_MSK 
PHY_M_FELP_LED1_MSK 
PHY_M_FELP_LED0_MSK 

Definition at line 1419 of file sky2.h.

01419      {
01420         PHY_M_FELP_LED2_MSK = 0xf<<8,   /* Bit 11.. 8: LED2 Mask (LINK) */
01421         PHY_M_FELP_LED1_MSK = 0xf<<4,   /* Bit  7.. 4: LED1 Mask (ACT) */
01422         PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
01423 };

anonymous enum

Enumerator:
LED_PAR_CTRL_COLX 
LED_PAR_CTRL_ERROR 
LED_PAR_CTRL_DUPLEX 
LED_PAR_CTRL_DP_COL 
LED_PAR_CTRL_SPEED 
LED_PAR_CTRL_LINK 
LED_PAR_CTRL_TX 
LED_PAR_CTRL_RX 
LED_PAR_CTRL_ACT 
LED_PAR_CTRL_LNK_RX 
LED_PAR_CTRL_LNK_AC 
LED_PAR_CTRL_ACT_BL 
LED_PAR_CTRL_TX_BL 
LED_PAR_CTRL_RX_BL 
LED_PAR_CTRL_COL_BL 
LED_PAR_CTRL_INACT 

Definition at line 1429 of file sky2.h.

01429      {
01430         LED_PAR_CTRL_COLX       = 0x00,
01431         LED_PAR_CTRL_ERROR      = 0x01,
01432         LED_PAR_CTRL_DUPLEX     = 0x02,
01433         LED_PAR_CTRL_DP_COL     = 0x03,
01434         LED_PAR_CTRL_SPEED      = 0x04,
01435         LED_PAR_CTRL_LINK       = 0x05,
01436         LED_PAR_CTRL_TX         = 0x06,
01437         LED_PAR_CTRL_RX         = 0x07,
01438         LED_PAR_CTRL_ACT        = 0x08,
01439         LED_PAR_CTRL_LNK_RX     = 0x09,
01440         LED_PAR_CTRL_LNK_AC     = 0x0a,
01441         LED_PAR_CTRL_ACT_BL     = 0x0b,
01442         LED_PAR_CTRL_TX_BL      = 0x0c,
01443         LED_PAR_CTRL_RX_BL      = 0x0d,
01444         LED_PAR_CTRL_COL_BL     = 0x0e,
01445         LED_PAR_CTRL_INACT      = 0x0f
01446 };

anonymous enum

Enumerator:
PHY_M_FESC_DIS_WAIT 
PHY_M_FESC_ENA_MCLK 
PHY_M_FESC_SEL_CL_A 

Definition at line 1449 of file sky2.h.

01449      {
01450         PHY_M_FESC_DIS_WAIT     = 1<<2, /* Disable TDR Waiting Period */
01451         PHY_M_FESC_ENA_MCLK     = 1<<1, /* Enable MAC Rx Clock in sleep mode */
01452         PHY_M_FESC_SEL_CL_A     = 1<<0, /* Select Class A driver (100B-TX) */
01453 };

anonymous enum

Enumerator:
PHY_M_FIB_FORCE_LNK 
PHY_M_FIB_SIGD_POL 
PHY_M_FIB_TX_DIS 

Definition at line 1457 of file sky2.h.

01457      {
01458         PHY_M_FIB_FORCE_LNK     = 1<<10,/* Force Link Good */
01459         PHY_M_FIB_SIGD_POL      = 1<<9, /* SIGDET Polarity */
01460         PHY_M_FIB_TX_DIS        = 1<<3, /* Transmitter Disable */
01461 };

anonymous enum

Enumerator:
PHY_M_MAC_MD_MSK 
PHY_M_MAC_GMIF_PUP 
PHY_M_MAC_MD_AUTO 
PHY_M_MAC_MD_COPPER 
PHY_M_MAC_MD_1000BX 

Definition at line 1465 of file sky2.h.

01465      {
01466         PHY_M_MAC_MD_MSK        = 7<<7, /* Bit  9.. 7: Mode Select Mask */
01467         PHY_M_MAC_GMIF_PUP      = 1<<3, /* GMII Power Up (88E1149 only) */
01468         PHY_M_MAC_MD_AUTO       = 3,/* Auto Copper/1000Base-X */
01469         PHY_M_MAC_MD_COPPER     = 5,/* Copper only */
01470         PHY_M_MAC_MD_1000BX     = 7,/* 1000Base-X only */
01471 };

anonymous enum

Enumerator:
PHY_M_LEDC_LOS_MSK 
PHY_M_LEDC_INIT_MSK 
PHY_M_LEDC_STA1_MSK 
PHY_M_LEDC_STA0_MSK 

Definition at line 1475 of file sky2.h.

01475      {
01476         PHY_M_LEDC_LOS_MSK      = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
01477         PHY_M_LEDC_INIT_MSK     = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
01478         PHY_M_LEDC_STA1_MSK     = 0xf<<4,/* Bit  7.. 4: STAT1 LED Ctrl. Mask */
01479         PHY_M_LEDC_STA0_MSK     = 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
01480 };

anonymous enum

Enumerator:
GM_GP_STAT 
GM_GP_CTRL 
GM_TX_CTRL 
GM_RX_CTRL 
GM_TX_FLOW_CTRL 
GM_TX_PARAM 
GM_SERIAL_MODE 
GM_SRC_ADDR_1L 
GM_SRC_ADDR_1M 
GM_SRC_ADDR_1H 
GM_SRC_ADDR_2L 
GM_SRC_ADDR_2M 
GM_SRC_ADDR_2H 
GM_MC_ADDR_H1 
GM_MC_ADDR_H2 
GM_MC_ADDR_H3 
GM_MC_ADDR_H4 
GM_TX_IRQ_SRC 
GM_RX_IRQ_SRC 
GM_TR_IRQ_SRC 
GM_TX_IRQ_MSK 
GM_RX_IRQ_MSK 
GM_TR_IRQ_MSK 
GM_SMI_CTRL 
GM_SMI_DATA 
GM_PHY_ADDR 
GM_MIB_CNT_BASE 
GM_MIB_CNT_END 

Definition at line 1489 of file sky2.h.

01489      {
01490         GM_GP_STAT      = 0x0000,       /* 16 bit r/o   General Purpose Status */
01491         GM_GP_CTRL      = 0x0004,       /* 16 bit r/w   General Purpose Control */
01492         GM_TX_CTRL      = 0x0008,       /* 16 bit r/w   Transmit Control Reg. */
01493         GM_RX_CTRL      = 0x000c,       /* 16 bit r/w   Receive Control Reg. */
01494         GM_TX_FLOW_CTRL = 0x0010,       /* 16 bit r/w   Transmit Flow-Control */
01495         GM_TX_PARAM     = 0x0014,       /* 16 bit r/w   Transmit Parameter Reg. */
01496         GM_SERIAL_MODE  = 0x0018,       /* 16 bit r/w   Serial Mode Register */
01497 /* Source Address Registers */
01498         GM_SRC_ADDR_1L  = 0x001c,       /* 16 bit r/w   Source Address 1 (low) */
01499         GM_SRC_ADDR_1M  = 0x0020,       /* 16 bit r/w   Source Address 1 (middle) */
01500         GM_SRC_ADDR_1H  = 0x0024,       /* 16 bit r/w   Source Address 1 (high) */
01501         GM_SRC_ADDR_2L  = 0x0028,       /* 16 bit r/w   Source Address 2 (low) */
01502         GM_SRC_ADDR_2M  = 0x002c,       /* 16 bit r/w   Source Address 2 (middle) */
01503         GM_SRC_ADDR_2H  = 0x0030,       /* 16 bit r/w   Source Address 2 (high) */
01504 
01505 /* Multicast Address Hash Registers */
01506         GM_MC_ADDR_H1   = 0x0034,       /* 16 bit r/w   Multicast Address Hash 1 */
01507         GM_MC_ADDR_H2   = 0x0038,       /* 16 bit r/w   Multicast Address Hash 2 */
01508         GM_MC_ADDR_H3   = 0x003c,       /* 16 bit r/w   Multicast Address Hash 3 */
01509         GM_MC_ADDR_H4   = 0x0040,       /* 16 bit r/w   Multicast Address Hash 4 */
01510 
01511 /* Interrupt Source Registers */
01512         GM_TX_IRQ_SRC   = 0x0044,       /* 16 bit r/o   Tx Overflow IRQ Source */
01513         GM_RX_IRQ_SRC   = 0x0048,       /* 16 bit r/o   Rx Overflow IRQ Source */
01514         GM_TR_IRQ_SRC   = 0x004c,       /* 16 bit r/o   Tx/Rx Over. IRQ Source */
01515 
01516 /* Interrupt Mask Registers */
01517         GM_TX_IRQ_MSK   = 0x0050,       /* 16 bit r/w   Tx Overflow IRQ Mask */
01518         GM_RX_IRQ_MSK   = 0x0054,       /* 16 bit r/w   Rx Overflow IRQ Mask */
01519         GM_TR_IRQ_MSK   = 0x0058,       /* 16 bit r/w   Tx/Rx Over. IRQ Mask */
01520 
01521 /* Serial Management Interface (SMI) Registers */
01522         GM_SMI_CTRL     = 0x0080,       /* 16 bit r/w   SMI Control Register */
01523         GM_SMI_DATA     = 0x0084,       /* 16 bit r/w   SMI Data Register */
01524         GM_PHY_ADDR     = 0x0088,       /* 16 bit r/w   GPHY Address Register */
01525 /* MIB Counters */
01526         GM_MIB_CNT_BASE = 0x0100,       /* Base Address of MIB Counters */
01527         GM_MIB_CNT_END  = 0x025C,       /* Last MIB counter */
01528 };

anonymous enum

Enumerator:
GM_RXF_UC_OK 
GM_RXF_BC_OK 
GM_RXF_MPAUSE 
GM_RXF_MC_OK 
GM_RXF_FCS_ERR 
GM_RXO_OK_LO 
GM_RXO_OK_HI 
GM_RXO_ERR_LO 
GM_RXO_ERR_HI 
GM_RXF_SHT 
GM_RXE_FRAG 
GM_RXF_64B 
GM_RXF_127B 
GM_RXF_255B 
GM_RXF_511B 
GM_RXF_1023B 
GM_RXF_1518B 
GM_RXF_MAX_SZ 
GM_RXF_LNG_ERR 
GM_RXF_JAB_PKT 
GM_RXE_FIFO_OV 
GM_TXF_UC_OK 
GM_TXF_BC_OK 
GM_TXF_MPAUSE 
GM_TXF_MC_OK 
GM_TXO_OK_LO 
GM_TXO_OK_HI 
GM_TXF_64B 
GM_TXF_127B 
GM_TXF_255B 
GM_TXF_511B 
GM_TXF_1023B 
GM_TXF_1518B 
GM_TXF_MAX_SZ 
GM_TXF_COL 
GM_TXF_LAT_COL 
GM_TXF_ABO_COL 
GM_TXF_MUL_COL 
GM_TXF_SNG_COL 
GM_TXE_FIFO_UR 

Definition at line 1535 of file sky2.h.

01535      {
01536         GM_RXF_UC_OK    = GM_MIB_CNT_BASE + 0,  /* Unicast Frames Received OK */
01537         GM_RXF_BC_OK    = GM_MIB_CNT_BASE + 8,  /* Broadcast Frames Received OK */
01538         GM_RXF_MPAUSE   = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
01539         GM_RXF_MC_OK    = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
01540         GM_RXF_FCS_ERR  = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
01541 
01542         GM_RXO_OK_LO    = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
01543         GM_RXO_OK_HI    = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
01544         GM_RXO_ERR_LO   = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
01545         GM_RXO_ERR_HI   = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
01546         GM_RXF_SHT      = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
01547         GM_RXE_FRAG     = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
01548         GM_RXF_64B      = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
01549         GM_RXF_127B     = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
01550         GM_RXF_255B     = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
01551         GM_RXF_511B     = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
01552         GM_RXF_1023B    = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
01553         GM_RXF_1518B    = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
01554         GM_RXF_MAX_SZ   = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
01555         GM_RXF_LNG_ERR  = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
01556         GM_RXF_JAB_PKT  = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
01557 
01558         GM_RXE_FIFO_OV  = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
01559         GM_TXF_UC_OK    = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
01560         GM_TXF_BC_OK    = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
01561         GM_TXF_MPAUSE   = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
01562         GM_TXF_MC_OK    = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
01563         GM_TXO_OK_LO    = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
01564         GM_TXO_OK_HI    = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
01565         GM_TXF_64B      = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
01566         GM_TXF_127B     = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
01567         GM_TXF_255B     = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
01568         GM_TXF_511B     = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
01569         GM_TXF_1023B    = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
01570         GM_TXF_1518B    = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
01571         GM_TXF_MAX_SZ   = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
01572 
01573         GM_TXF_COL      = GM_MIB_CNT_BASE + 304,/* Tx Collision */
01574         GM_TXF_LAT_COL  = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
01575         GM_TXF_ABO_COL  = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
01576         GM_TXF_MUL_COL  = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
01577         GM_TXF_SNG_COL  = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
01578         GM_TXE_FIFO_UR  = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
01579 };

anonymous enum

Enumerator:
GM_GPSR_SPEED 
GM_GPSR_DUPLEX 
GM_GPSR_FC_TX_DIS 
GM_GPSR_LINK_UP 
GM_GPSR_PAUSE 
GM_GPSR_TX_ACTIVE 
GM_GPSR_EXC_COL 
GM_GPSR_LAT_COL 
GM_GPSR_PHY_ST_CH 
GM_GPSR_GIG_SPEED 
GM_GPSR_PART_MODE 
GM_GPSR_FC_RX_DIS 
GM_GPSR_PROM_EN 

Definition at line 1583 of file sky2.h.

01583      {
01584         GM_GPSR_SPEED           = 1<<15, /* Bit 15:     Port Speed (1 = 100 Mbps) */
01585         GM_GPSR_DUPLEX          = 1<<14, /* Bit 14:     Duplex Mode (1 = Full) */
01586         GM_GPSR_FC_TX_DIS       = 1<<13, /* Bit 13:     Tx Flow-Control Mode Disabled */
01587         GM_GPSR_LINK_UP         = 1<<12, /* Bit 12:     Link Up Status */
01588         GM_GPSR_PAUSE           = 1<<11, /* Bit 11:     Pause State */
01589         GM_GPSR_TX_ACTIVE       = 1<<10, /* Bit 10:     Tx in Progress */
01590         GM_GPSR_EXC_COL         = 1<<9, /* Bit  9:      Excessive Collisions Occured */
01591         GM_GPSR_LAT_COL         = 1<<8, /* Bit  8:      Late Collisions Occured */
01592 
01593         GM_GPSR_PHY_ST_CH       = 1<<5, /* Bit  5:      PHY Status Change */
01594         GM_GPSR_GIG_SPEED       = 1<<4, /* Bit  4:      Gigabit Speed (1 = 1000 Mbps) */
01595         GM_GPSR_PART_MODE       = 1<<3, /* Bit  3:      Partition mode */
01596         GM_GPSR_FC_RX_DIS       = 1<<2, /* Bit  2:      Rx Flow-Control Mode Disabled */
01597         GM_GPSR_PROM_EN         = 1<<1, /* Bit  1:      Promiscuous Mode Enabled */
01598 };

anonymous enum

Enumerator:
GM_GPCR_PROM_ENA 
GM_GPCR_FC_TX_DIS 
GM_GPCR_TX_ENA 
GM_GPCR_RX_ENA 
GM_GPCR_BURST_ENA 
GM_GPCR_LOOP_ENA 
GM_GPCR_PART_ENA 
GM_GPCR_GIGS_ENA 
GM_GPCR_FL_PASS 
GM_GPCR_DUP_FULL 
GM_GPCR_FC_RX_DIS 
GM_GPCR_SPEED_100 
GM_GPCR_AU_DUP_DIS 
GM_GPCR_AU_FCT_DIS 
GM_GPCR_AU_SPD_DIS 

Definition at line 1601 of file sky2.h.

01601      {
01602         GM_GPCR_PROM_ENA        = 1<<14,        /* Bit 14:      Enable Promiscuous Mode */
01603         GM_GPCR_FC_TX_DIS       = 1<<13, /* Bit 13:     Disable Tx Flow-Control Mode */
01604         GM_GPCR_TX_ENA          = 1<<12, /* Bit 12:     Enable Transmit */
01605         GM_GPCR_RX_ENA          = 1<<11, /* Bit 11:     Enable Receive */
01606         GM_GPCR_BURST_ENA       = 1<<10, /* Bit 10:     Enable Burst Mode */
01607         GM_GPCR_LOOP_ENA        = 1<<9, /* Bit  9:      Enable MAC Loopback Mode */
01608         GM_GPCR_PART_ENA        = 1<<8, /* Bit  8:      Enable Partition Mode */
01609         GM_GPCR_GIGS_ENA        = 1<<7, /* Bit  7:      Gigabit Speed (1000 Mbps) */
01610         GM_GPCR_FL_PASS         = 1<<6, /* Bit  6:      Force Link Pass */
01611         GM_GPCR_DUP_FULL        = 1<<5, /* Bit  5:      Full Duplex Mode */
01612         GM_GPCR_FC_RX_DIS       = 1<<4, /* Bit  4:      Disable Rx Flow-Control Mode */
01613         GM_GPCR_SPEED_100       = 1<<3,   /* Bit  3:    Port Speed 100 Mbps */
01614         GM_GPCR_AU_DUP_DIS      = 1<<2, /* Bit  2:      Disable Auto-Update Duplex */
01615         GM_GPCR_AU_FCT_DIS      = 1<<1, /* Bit  1:      Disable Auto-Update Flow-C. */
01616         GM_GPCR_AU_SPD_DIS      = 1<<0, /* Bit  0:      Disable Auto-Update Speed */
01617 };

anonymous enum

Enumerator:
GM_TXCR_FORCE_JAM 
GM_TXCR_CRC_DIS 
GM_TXCR_PAD_DIS 
GM_TXCR_COL_THR_MSK 

Definition at line 1623 of file sky2.h.

01623      {
01624         GM_TXCR_FORCE_JAM       = 1<<15, /* Bit 15:     Force Jam / Flow-Control */
01625         GM_TXCR_CRC_DIS         = 1<<14, /* Bit 14:     Disable insertion of CRC */
01626         GM_TXCR_PAD_DIS         = 1<<13, /* Bit 13:     Disable padding of packets */
01627         GM_TXCR_COL_THR_MSK     = 7<<10, /* Bit 12..10: Collision Threshold */
01628 };

anonymous enum

Enumerator:
GM_RXCR_UCF_ENA 
GM_RXCR_MCF_ENA 
GM_RXCR_CRC_DIS 
GM_RXCR_PASS_FC 

Definition at line 1634 of file sky2.h.

01634      {
01635         GM_RXCR_UCF_ENA = 1<<15, /* Bit 15:     Enable Unicast filtering */
01636         GM_RXCR_MCF_ENA = 1<<14, /* Bit 14:     Enable Multicast filtering */
01637         GM_RXCR_CRC_DIS = 1<<13, /* Bit 13:     Remove 4-byte CRC */
01638         GM_RXCR_PASS_FC = 1<<12, /* Bit 12:     Pass FC packets to FIFO */
01639 };

anonymous enum

Enumerator:
GM_TXPA_JAMLEN_MSK 
GM_TXPA_JAMIPG_MSK 
GM_TXPA_JAMDAT_MSK 
GM_TXPA_BO_LIM_MSK 
TX_JAM_LEN_DEF 
TX_JAM_IPG_DEF 
TX_IPG_JAM_DEF 
TX_BOF_LIM_DEF 

Definition at line 1642 of file sky2.h.

01642      {
01643         GM_TXPA_JAMLEN_MSK      = 0x03<<14,     /* Bit 15..14:  Jam Length */
01644         GM_TXPA_JAMIPG_MSK      = 0x1f<<9,      /* Bit 13..9:   Jam IPG */
01645         GM_TXPA_JAMDAT_MSK      = 0x1f<<4,      /* Bit  8..4:   IPG Jam to Data */
01646         GM_TXPA_BO_LIM_MSK      = 0x0f,         /* Bit  3.. 0: Backoff Limit Mask */
01647 
01648         TX_JAM_LEN_DEF          = 0x03,
01649         TX_JAM_IPG_DEF          = 0x0b,
01650         TX_IPG_JAM_DEF          = 0x1c,
01651         TX_BOF_LIM_DEF          = 0x04,
01652 };

anonymous enum

Enumerator:
GM_SMOD_DATABL_MSK 
GM_SMOD_LIMIT_4 
GM_SMOD_VLAN_ENA 
GM_SMOD_JUMBO_ENA 
GM_SMOD_IPG_MSK 

Definition at line 1661 of file sky2.h.

01661      {
01662         GM_SMOD_DATABL_MSK      = 0x1f<<11, /* Bit 15..11:      Data Blinder (r/o) */
01663         GM_SMOD_LIMIT_4         = 1<<10, /* Bit 10:     4 consecutive Tx trials */
01664         GM_SMOD_VLAN_ENA        = 1<<9, /* Bit  9:      Enable VLAN  (Max. Frame Len) */
01665         GM_SMOD_JUMBO_ENA       = 1<<8, /* Bit  8:      Enable Jumbo (Max. Frame Len) */
01666          GM_SMOD_IPG_MSK        = 0x1f  /* Bit 4..0:    Inter-Packet Gap (IPG) */
01667 };

anonymous enum

Enumerator:
GM_SMI_CT_PHY_A_MSK 
GM_SMI_CT_REG_A_MSK 
GM_SMI_CT_OP_RD 
GM_SMI_CT_RD_VAL 
GM_SMI_CT_BUSY 

Definition at line 1676 of file sky2.h.

01676      {
01677         GM_SMI_CT_PHY_A_MSK     = 0x1f<<11,/* Bit 15..11:       PHY Device Address */
01678         GM_SMI_CT_REG_A_MSK     = 0x1f<<6,/* Bit 10.. 6:        PHY Register Address */
01679         GM_SMI_CT_OP_RD         = 1<<5, /* Bit  5:      OpCode Read (0=Write)*/
01680         GM_SMI_CT_RD_VAL        = 1<<4, /* Bit  4:      Read Valid (Read completed) */
01681         GM_SMI_CT_BUSY          = 1<<3, /* Bit  3:      Busy (Operation in progress) */
01682 };

anonymous enum

Enumerator:
GM_PAR_MIB_CLR 
GM_PAR_MIB_TST 

Definition at line 1688 of file sky2.h.

01688      {
01689         GM_PAR_MIB_CLR  = 1<<5, /* Bit  5:      Set MIB Clear Counter Mode */
01690         GM_PAR_MIB_TST  = 1<<4, /* Bit  4:      MIB Load Counter (Test Mode) */
01691 };

anonymous enum

Enumerator:
GMR_FS_LEN 
GMR_FS_VLAN 
GMR_FS_JABBER 
GMR_FS_UN_SIZE 
GMR_FS_MC 
GMR_FS_BC 
GMR_FS_RX_OK 
GMR_FS_GOOD_FC 
GMR_FS_BAD_FC 
GMR_FS_MII_ERR 
GMR_FS_LONG_ERR 
GMR_FS_FRAGMENT 
GMR_FS_CRC_ERR 
GMR_FS_RX_FF_OV 
GMR_FS_ANY_ERR 

Definition at line 1694 of file sky2.h.

01694      {
01695         GMR_FS_LEN      = 0x7fff<<16, /* Bit 30..16:    Rx Frame Length */
01696         GMR_FS_VLAN     = 1<<13, /* VLAN Packet */
01697         GMR_FS_JABBER   = 1<<12, /* Jabber Packet */
01698         GMR_FS_UN_SIZE  = 1<<11, /* Undersize Packet */
01699         GMR_FS_MC       = 1<<10, /* Multicast Packet */
01700         GMR_FS_BC       = 1<<9,  /* Broadcast Packet */
01701         GMR_FS_RX_OK    = 1<<8,  /* Receive OK (Good Packet) */
01702         GMR_FS_GOOD_FC  = 1<<7,  /* Good Flow-Control Packet */
01703         GMR_FS_BAD_FC   = 1<<6,  /* Bad  Flow-Control Packet */
01704         GMR_FS_MII_ERR  = 1<<5,  /* MII Error */
01705         GMR_FS_LONG_ERR = 1<<4,  /* Too Long Packet */
01706         GMR_FS_FRAGMENT = 1<<3,  /* Fragment */
01707 
01708         GMR_FS_CRC_ERR  = 1<<1,  /* CRC Error */
01709         GMR_FS_RX_FF_OV = 1<<0,  /* Rx FIFO Overflow */
01710 
01711         GMR_FS_ANY_ERR  = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
01712                           GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
01713                           GMR_FS_MII_ERR | GMR_FS_BAD_FC |
01714                           GMR_FS_UN_SIZE | GMR_FS_JABBER,
01715 };

anonymous enum

Enumerator:
RX_TRUNC_ON 
RX_TRUNC_OFF 
RX_VLAN_STRIP_ON 
RX_VLAN_STRIP_OFF 
RX_MACSEC_FLUSH_ON 
RX_MACSEC_FLUSH_OFF 
RX_MACSEC_ASF_FLUSH_ON 
RX_MACSEC_ASF_FLUSH_OFF 
GMF_RX_OVER_ON 
GMF_RX_OVER_OFF 
GMF_ASF_RX_OVER_ON 
GMF_ASF_RX_OVER_OFF 
GMF_WP_TST_ON 
GMF_WP_TST_OFF 
GMF_WP_STEP 
GMF_RP_TST_ON 
GMF_RP_TST_OFF 
GMF_RP_STEP 
GMF_RX_F_FL_ON 
GMF_RX_F_FL_OFF 
GMF_CLI_RX_FO 
GMF_CLI_RX_C 
GMF_OPER_ON 
GMF_OPER_OFF 
GMF_RST_CLR 
GMF_RST_SET 
RX_GMF_FL_THR_DEF 
GMF_RX_CTRL_DEF 

Definition at line 1718 of file sky2.h.

01718      {
01719         RX_TRUNC_ON     = 1<<27,        /* enable  packet truncation */
01720         RX_TRUNC_OFF    = 1<<26,        /* disable packet truncation */
01721         RX_VLAN_STRIP_ON = 1<<25,       /* enable  VLAN stripping */
01722         RX_VLAN_STRIP_OFF = 1<<24,      /* disable VLAN stripping */
01723 
01724         RX_MACSEC_FLUSH_ON  = 1<<23,
01725         RX_MACSEC_FLUSH_OFF = 1<<22,
01726         RX_MACSEC_ASF_FLUSH_ON = 1<<21,
01727         RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
01728 
01729         GMF_RX_OVER_ON      = 1<<19,    /* enable flushing on receive overrun */
01730         GMF_RX_OVER_OFF     = 1<<18,    /* disable flushing on receive overrun */
01731         GMF_ASF_RX_OVER_ON  = 1<<17,    /* enable flushing of ASF when overrun */
01732         GMF_ASF_RX_OVER_OFF = 1<<16,    /* disable flushing of ASF when overrun */
01733 
01734         GMF_WP_TST_ON   = 1<<14,        /* Write Pointer Test On */
01735         GMF_WP_TST_OFF  = 1<<13,        /* Write Pointer Test Off */
01736         GMF_WP_STEP     = 1<<12,        /* Write Pointer Step/Increment */
01737 
01738         GMF_RP_TST_ON   = 1<<10,        /* Read Pointer Test On */
01739         GMF_RP_TST_OFF  = 1<<9,         /* Read Pointer Test Off */
01740         GMF_RP_STEP     = 1<<8,         /* Read Pointer Step/Increment */
01741         GMF_RX_F_FL_ON  = 1<<7,         /* Rx FIFO Flush Mode On */
01742         GMF_RX_F_FL_OFF = 1<<6,         /* Rx FIFO Flush Mode Off */
01743         GMF_CLI_RX_FO   = 1<<5,         /* Clear IRQ Rx FIFO Overrun */
01744         GMF_CLI_RX_C    = 1<<4,         /* Clear IRQ Rx Frame Complete */
01745 
01746         GMF_OPER_ON     = 1<<3,         /* Operational Mode On */
01747         GMF_OPER_OFF    = 1<<2,         /* Operational Mode Off */
01748         GMF_RST_CLR     = 1<<1,         /* Clear GMAC FIFO Reset */
01749         GMF_RST_SET     = 1<<0,         /* Set   GMAC FIFO Reset */
01750 
01751         RX_GMF_FL_THR_DEF = 0xa,        /* flush threshold (default) */
01752 
01753         GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
01754 };

anonymous enum

Enumerator:
TX_DYN_WM_ENA 

Definition at line 1757 of file sky2.h.

01757      {
01758         TX_DYN_WM_ENA   = 3,    /* Yukon-FE+ specific */
01759 };

anonymous enum

Enumerator:
TX_STFW_DIS 
TX_STFW_ENA 
TX_VLAN_TAG_ON 
TX_VLAN_TAG_OFF 
TX_JUMBO_ENA 
TX_JUMBO_DIS 
GMF_WSP_TST_ON 
GMF_WSP_TST_OFF 
GMF_WSP_STEP 
GMF_CLI_TX_FU 
GMF_CLI_TX_FC 
GMF_CLI_TX_PE 

Definition at line 1762 of file sky2.h.

01762      {
01763         TX_STFW_DIS     = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
01764         TX_STFW_ENA     = 1<<30,/* Enable  Store & Forward (Yukon-EC Ultra) */
01765 
01766         TX_VLAN_TAG_ON  = 1<<25,/* enable  VLAN tagging */
01767         TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
01768 
01769         TX_JUMBO_ENA    = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
01770         TX_JUMBO_DIS    = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
01771 
01772         GMF_WSP_TST_ON  = 1<<18,/* Write Shadow Pointer Test On */
01773         GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
01774         GMF_WSP_STEP    = 1<<16,/* Write Shadow Pointer Step/Increment */
01775 
01776         GMF_CLI_TX_FU   = 1<<6, /* Clear IRQ Tx FIFO Underrun */
01777         GMF_CLI_TX_FC   = 1<<5, /* Clear IRQ Tx Frame Complete */
01778         GMF_CLI_TX_PE   = 1<<4, /* Clear IRQ Tx Parity Error */
01779 };

anonymous enum

Enumerator:
GMT_ST_START 
GMT_ST_STOP 
GMT_ST_CLR_IRQ 

Definition at line 1782 of file sky2.h.

01782      {
01783         GMT_ST_START    = 1<<2, /* Start Time Stamp Timer */
01784         GMT_ST_STOP     = 1<<1, /* Stop  Time Stamp Timer */
01785         GMT_ST_CLR_IRQ  = 1<<0, /* Clear Time Stamp Timer IRQ */
01786 };

anonymous enum

Enumerator:
Y2_ASF_OS_PRES 
Y2_ASF_RESET 
Y2_ASF_RUNNING 
Y2_ASF_CLR_HSTI 
Y2_ASF_IRQ 
Y2_ASF_UC_STATE 
Y2_ASF_CLK_HALT 

Definition at line 1789 of file sky2.h.

01789      {
01790         Y2_ASF_OS_PRES  = 1<<4, /* ASF operation system present */
01791         Y2_ASF_RESET    = 1<<3, /* ASF system in reset state */
01792         Y2_ASF_RUNNING  = 1<<2, /* ASF system operational */
01793         Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
01794         Y2_ASF_IRQ      = 1<<0, /* Issue an IRQ to ASF system */
01795 
01796         Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
01797         Y2_ASF_CLK_HALT = 0,    /* ASF system clock stopped */
01798 };

anonymous enum

Enumerator:
Y2_ASF_CLR_ASFI 
Y2_ASF_HOST_IRQ 

Definition at line 1801 of file sky2.h.

01801      {
01802         Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
01803         Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
01804 };

anonymous enum

Enumerator:
HCU_CCSR_SMBALERT_MONITOR 
HCU_CCSR_CPU_SLEEP 
HCU_CCSR_CS_TO 
HCU_CCSR_WDOG 
HCU_CCSR_CLR_IRQ_HOST 
HCU_CCSR_SET_IRQ_HCU 
HCU_CCSR_AHB_RST 
HCU_CCSR_CPU_RST_MODE 
HCU_CCSR_SET_SYNC_CPU 
HCU_CCSR_CPU_CLK_DIVIDE_MSK 
HCU_CCSR_CPU_CLK_DIVIDE_BASE 
HCU_CCSR_OS_PRSNT 
HCU_CCSR_UC_STATE_MSK 
HCU_CCSR_UC_STATE_BASE 
HCU_CCSR_ASF_RESET 
HCU_CCSR_ASF_HALTED 
HCU_CCSR_ASF_RUNNING 

Definition at line 1806 of file sky2.h.

01806      {
01807         HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
01808         HCU_CCSR_CPU_SLEEP      = 1<<26, /* CPU sleep status */
01809         /* Clock Stretching Timeout */
01810         HCU_CCSR_CS_TO          = 1<<25,
01811         HCU_CCSR_WDOG           = 1<<24, /* Watchdog Reset */
01812 
01813         HCU_CCSR_CLR_IRQ_HOST   = 1<<17, /* Clear IRQ_HOST */
01814         HCU_CCSR_SET_IRQ_HCU    = 1<<16, /* Set IRQ_HCU */
01815 
01816         HCU_CCSR_AHB_RST        = 1<<9, /* Reset AHB bridge */
01817         HCU_CCSR_CPU_RST_MODE   = 1<<8, /* CPU Reset Mode */
01818 
01819         HCU_CCSR_SET_SYNC_CPU   = 1<<5,
01820         HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
01821         HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
01822         HCU_CCSR_OS_PRSNT       = 1<<2, /* ASF OS Present */
01823 /* Microcontroller State */
01824         HCU_CCSR_UC_STATE_MSK   = 3,
01825         HCU_CCSR_UC_STATE_BASE  = 1<<0,
01826         HCU_CCSR_ASF_RESET      = 0,
01827         HCU_CCSR_ASF_HALTED     = 1<<1,
01828         HCU_CCSR_ASF_RUNNING    = 1<<0,
01829 };

anonymous enum

Enumerator:
HCU_HCSR_SET_IRQ_CPU 
HCU_HCSR_CLR_IRQ_HCU 
HCU_HCSR_SET_IRQ_HOST 

Definition at line 1832 of file sky2.h.

01832      {
01833         HCU_HCSR_SET_IRQ_CPU    = 1<<16, /* Set IRQ_CPU */
01834 
01835         HCU_HCSR_CLR_IRQ_HCU    = 1<<1, /* Clear IRQ_HCU */
01836         HCU_HCSR_SET_IRQ_HOST   = 1<<0, /* Set IRQ_HOST */
01837 };

anonymous enum

Enumerator:
SC_STAT_CLR_IRQ 
SC_STAT_OP_ON 
SC_STAT_OP_OFF 
SC_STAT_RST_CLR 
SC_STAT_RST_SET 

Definition at line 1840 of file sky2.h.

01840      {
01841         SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
01842         SC_STAT_OP_ON   = 1<<3, /* Operational Mode On */
01843         SC_STAT_OP_OFF  = 1<<2, /* Operational Mode Off */
01844         SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
01845         SC_STAT_RST_SET = 1<<0, /* Set   Status Unit Reset */
01846 };

anonymous enum

Enumerator:
GMC_SET_RST 
GMC_SEC_RST_OFF 
GMC_BYP_MACSECRX_ON 
GMC_BYP_MACSECRX_OFF 
GMC_BYP_MACSECTX_ON 
GMC_BYP_MACSECTX_OFF 
GMC_BYP_RETR_ON 
GMC_BYP_RETR_OFF 
GMC_H_BURST_ON 
GMC_H_BURST_OFF 
GMC_F_LOOPB_ON 
GMC_F_LOOPB_OFF 
GMC_PAUSE_ON 
GMC_PAUSE_OFF 
GMC_RST_CLR 
GMC_RST_SET 

Definition at line 1849 of file sky2.h.

01849      {
01850         GMC_SET_RST         = 1<<15,/* MAC SEC RST */
01851         GMC_SEC_RST_OFF     = 1<<14,/* MAC SEC RSt OFF */
01852         GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
01853         GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
01854         GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
01855         GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX  off*/
01856         GMC_BYP_RETR_ON = 1<<9, /* Bypass retransmit FIFO On */
01857         GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */
01858 
01859         GMC_H_BURST_ON  = 1<<7, /* Half Duplex Burst Mode On */
01860         GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
01861         GMC_F_LOOPB_ON  = 1<<5, /* FIFO Loopback On */
01862         GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
01863         GMC_PAUSE_ON    = 1<<3, /* Pause On */
01864         GMC_PAUSE_OFF   = 1<<2, /* Pause Off */
01865         GMC_RST_CLR     = 1<<1, /* Clear GMAC Reset */
01866         GMC_RST_SET     = 1<<0, /* Set   GMAC Reset */
01867 };

anonymous enum

Enumerator:
GPC_TX_PAUSE 
GPC_RX_PAUSE 
GPC_SPEED 
GPC_LINK 
GPC_DUPLEX 
GPC_CLOCK 
GPC_PDOWN 
GPC_TSTMODE 
GPC_REG18 
GPC_REG12SEL 
GPC_REG18SEL 
GPC_SPILOCK 
GPC_LEDMUX 
GPC_INTPOL 
GPC_DETECT 
GPC_1000HD 
GPC_SLAVE 
GPC_PAUSE 
GPC_LEDCTL 
GPC_RST_CLR 
GPC_RST_SET 

Definition at line 1870 of file sky2.h.

01870      {
01871         GPC_TX_PAUSE    = 1<<30, /* Tx pause enabled (ro) */
01872         GPC_RX_PAUSE    = 1<<29, /* Rx pause enabled (ro) */
01873         GPC_SPEED       = 3<<27, /* PHY speed (ro) */
01874         GPC_LINK        = 1<<26, /* Link up (ro) */
01875         GPC_DUPLEX      = 1<<25, /* Duplex (ro) */
01876         GPC_CLOCK       = 1<<24, /* 125Mhz clock stable (ro) */
01877 
01878         GPC_PDOWN       = 1<<23, /* Internal regulator 2.5 power down */
01879         GPC_TSTMODE     = 1<<22, /* Test mode */
01880         GPC_REG18       = 1<<21, /* Reg18 Power down */
01881         GPC_REG12SEL    = 3<<19, /* Reg12 power setting */
01882         GPC_REG18SEL    = 3<<17, /* Reg18 power setting */
01883         GPC_SPILOCK     = 1<<16, /* SPI lock (ASF) */
01884 
01885         GPC_LEDMUX      = 3<<14, /* LED Mux */
01886         GPC_INTPOL      = 1<<13, /* Interrupt polarity */
01887         GPC_DETECT      = 1<<12, /* Energy detect */
01888         GPC_1000HD      = 1<<11, /* Enable 1000Mbit HD */
01889         GPC_SLAVE       = 1<<10, /* Slave mode */
01890         GPC_PAUSE       = 1<<9, /* Pause enable */
01891         GPC_LEDCTL      = 3<<6, /* GPHY Leds */
01892 
01893         GPC_RST_CLR     = 1<<1, /* Clear GPHY Reset */
01894         GPC_RST_SET     = 1<<0, /* Set   GPHY Reset */
01895 };

anonymous enum

Enumerator:
GM_IS_TX_CO_OV 
GM_IS_RX_CO_OV 
GM_IS_TX_FF_UR 
GM_IS_TX_COMPL 
GM_IS_RX_FF_OR 
GM_IS_RX_COMPL 
GMAC_DEF_MSK 

Definition at line 1899 of file sky2.h.

01899      {
01900         GM_IS_TX_CO_OV  = 1<<5, /* Transmit Counter Overflow IRQ */
01901         GM_IS_RX_CO_OV  = 1<<4, /* Receive Counter Overflow IRQ */
01902         GM_IS_TX_FF_UR  = 1<<3, /* Transmit FIFO Underrun */
01903         GM_IS_TX_COMPL  = 1<<2, /* Frame Transmission Complete */
01904         GM_IS_RX_FF_OR  = 1<<1, /* Receive FIFO Overrun */
01905         GM_IS_RX_COMPL  = 1<<0, /* Frame Reception Complete */
01906 
01907 #define GMAC_DEF_MSK     GM_IS_TX_FF_UR
01908 };

anonymous enum

Enumerator:
GMLC_RST_CLR 
GMLC_RST_SET 

Definition at line 1911 of file sky2.h.

01911      {                                          /* Bits 15.. 2: reserved */
01912         GMLC_RST_CLR    = 1<<1, /* Clear GMAC Link Reset */
01913         GMLC_RST_SET    = 1<<0, /* Set   GMAC Link Reset */
01914 };

anonymous enum

Enumerator:
WOL_CTL_LINK_CHG_OCC 
WOL_CTL_MAGIC_PKT_OCC 
WOL_CTL_PATTERN_OCC 
WOL_CTL_CLEAR_RESULT 
WOL_CTL_ENA_PME_ON_LINK_CHG 
WOL_CTL_DIS_PME_ON_LINK_CHG 
WOL_CTL_ENA_PME_ON_MAGIC_PKT 
WOL_CTL_DIS_PME_ON_MAGIC_PKT 
WOL_CTL_ENA_PME_ON_PATTERN 
WOL_CTL_DIS_PME_ON_PATTERN 
WOL_CTL_ENA_LINK_CHG_UNIT 
WOL_CTL_DIS_LINK_CHG_UNIT 
WOL_CTL_ENA_MAGIC_PKT_UNIT 
WOL_CTL_DIS_MAGIC_PKT_UNIT 
WOL_CTL_ENA_PATTERN_UNIT 
WOL_CTL_DIS_PATTERN_UNIT 

Definition at line 1918 of file sky2.h.

01918      {
01919         WOL_CTL_LINK_CHG_OCC            = 1<<15,
01920         WOL_CTL_MAGIC_PKT_OCC           = 1<<14,
01921         WOL_CTL_PATTERN_OCC             = 1<<13,
01922         WOL_CTL_CLEAR_RESULT            = 1<<12,
01923         WOL_CTL_ENA_PME_ON_LINK_CHG     = 1<<11,
01924         WOL_CTL_DIS_PME_ON_LINK_CHG     = 1<<10,
01925         WOL_CTL_ENA_PME_ON_MAGIC_PKT    = 1<<9,
01926         WOL_CTL_DIS_PME_ON_MAGIC_PKT    = 1<<8,
01927         WOL_CTL_ENA_PME_ON_PATTERN      = 1<<7,
01928         WOL_CTL_DIS_PME_ON_PATTERN      = 1<<6,
01929         WOL_CTL_ENA_LINK_CHG_UNIT       = 1<<5,
01930         WOL_CTL_DIS_LINK_CHG_UNIT       = 1<<4,
01931         WOL_CTL_ENA_MAGIC_PKT_UNIT      = 1<<3,
01932         WOL_CTL_DIS_MAGIC_PKT_UNIT      = 1<<2,
01933         WOL_CTL_ENA_PATTERN_UNIT        = 1<<1,
01934         WOL_CTL_DIS_PATTERN_UNIT        = 1<<0,
01935 };

anonymous enum

Enumerator:
UDPTCP 
CALSUM 
WR_SUM 
INIT_SUM 
LOCK_SUM 
INS_VLAN 
EOP 

Definition at line 1939 of file sky2.h.

01939      {
01940         UDPTCP  = 1<<0,
01941         CALSUM  = 1<<1,
01942         WR_SUM  = 1<<2,
01943         INIT_SUM= 1<<3,
01944         LOCK_SUM= 1<<4,
01945         INS_VLAN= 1<<5,
01946         EOP     = 1<<7,
01947 };

anonymous enum

Enumerator:
HW_OWNER 
OP_TCPWRITE 
OP_TCPSTART 
OP_TCPINIT 
OP_TCPLCK 
OP_TCPCHKSUM 
OP_TCPIS 
OP_TCPLW 
OP_TCPLSW 
OP_TCPLISW 
OP_ADDR64 
OP_VLAN 
OP_ADDR64VLAN 
OP_LRGLEN 
OP_LRGLENVLAN 
OP_MSS 
OP_MSSVLAN 
OP_BUFFER 
OP_PACKET 
OP_LARGESEND 
OP_LSOV2 
OP_RXSTAT 
OP_RXTIMESTAMP 
OP_RXVLAN 
OP_RXCHKS 
OP_RXCHKSVLAN 
OP_RXTIMEVLAN 
OP_RSS_HASH 
OP_TXINDEXLE 
OP_MACSEC 
OP_PUTIDX 

Definition at line 1949 of file sky2.h.

01949      {
01950         HW_OWNER        = 1<<7,
01951         OP_TCPWRITE     = 0x11,
01952         OP_TCPSTART     = 0x12,
01953         OP_TCPINIT      = 0x14,
01954         OP_TCPLCK       = 0x18,
01955         OP_TCPCHKSUM    = OP_TCPSTART,
01956         OP_TCPIS        = OP_TCPINIT | OP_TCPSTART,
01957         OP_TCPLW        = OP_TCPLCK | OP_TCPWRITE,
01958         OP_TCPLSW       = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
01959         OP_TCPLISW      = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
01960 
01961         OP_ADDR64       = 0x21,
01962         OP_VLAN         = 0x22,
01963         OP_ADDR64VLAN   = OP_ADDR64 | OP_VLAN,
01964         OP_LRGLEN       = 0x24,
01965         OP_LRGLENVLAN   = OP_LRGLEN | OP_VLAN,
01966         OP_MSS          = 0x28,
01967         OP_MSSVLAN      = OP_MSS | OP_VLAN,
01968 
01969         OP_BUFFER       = 0x40,
01970         OP_PACKET       = 0x41,
01971         OP_LARGESEND    = 0x43,
01972         OP_LSOV2        = 0x45,
01973 
01974 /* YUKON-2 STATUS opcodes defines */
01975         OP_RXSTAT       = 0x60,
01976         OP_RXTIMESTAMP  = 0x61,
01977         OP_RXVLAN       = 0x62,
01978         OP_RXCHKS       = 0x64,
01979         OP_RXCHKSVLAN   = OP_RXCHKS | OP_RXVLAN,
01980         OP_RXTIMEVLAN   = OP_RXTIMESTAMP | OP_RXVLAN,
01981         OP_RSS_HASH     = 0x65,
01982         OP_TXINDEXLE    = 0x68,
01983         OP_MACSEC       = 0x6c,
01984         OP_PUTIDX       = 0x70,
01985 };

enum status_css

Enumerator:
CSS_TCPUDPCSOK 
CSS_ISUDP 
CSS_ISTCP 
CSS_ISIPFRAG 
CSS_ISIPV6 
CSS_IPV4CSUMOK 
CSS_ISIPV4 
CSS_LINK_BIT 

Definition at line 1987 of file sky2.h.

01987                 {
01988         CSS_TCPUDPCSOK  = 1<<7, /* TCP / UDP checksum is ok */
01989         CSS_ISUDP       = 1<<6, /* packet is a UDP packet */
01990         CSS_ISTCP       = 1<<5, /* packet is a TCP packet */
01991         CSS_ISIPFRAG    = 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
01992         CSS_ISIPV6      = 1<<3, /* packet is a IPv6 packet */
01993         CSS_IPV4CSUMOK  = 1<<2, /* IP v4: TCP header checksum is ok */
01994         CSS_ISIPV4      = 1<<1, /* packet is a IPv4 packet */
01995         CSS_LINK_BIT    = 1<<0, /* port number (legacy) */
01996 };

enum flow_control

Enumerator:
FC_NONE 
FC_TX 
FC_RX 
FC_BOTH 

Definition at line 2032 of file sky2.h.

02032                   {
02033         FC_NONE = 0,
02034         FC_TX   = 1,
02035         FC_RX   = 2,
02036         FC_BOTH = 3,
02037 };

Function Documentation

FILE_LICENCE ( GPL2_ONLY   ) 

static int sky2_is_copper ( const struct sky2_hw *  hw  )  [inline, static]

Definition at line 2090 of file sky2.h.

References sky2_hw::flags, and SKY2_HW_FIBRE_PHY.

Referenced by sky2_phy_init(), and sky2_supported_modes().

02091 {
02092         return !(hw->flags & SKY2_HW_FIBRE_PHY);
02093 }

static u32 sky2_read32 ( const struct sky2_hw *  hw,
unsigned  reg 
) [inline, static]

Definition at line 2096 of file sky2.h.

References readl, and sky2_hw::regs.

Referenced by sky2_down(), sky2_hw_intr(), sky2_net_irq(), sky2_pci_read32(), sky2_poll(), sky2_power_on(), sky2_prefetch_init(), sky2_reset(), and sky2_up().

02097 {
02098         return readl(hw->regs + reg);
02099 }

static u16 sky2_read16 ( const struct sky2_hw *  hw,
unsigned  reg 
) [inline, static]

Definition at line 2101 of file sky2.h.

References readw, and sky2_hw::regs.

Referenced by gma_read16(), gma_read32(), sky2_le_error(), sky2_mac_init(), sky2_pci_read16(), sky2_poll(), sky2_power_aux(), and sky2_reset().

02102 {
02103         return readw(hw->regs + reg);
02104 }

static u8 sky2_read8 ( const struct sky2_hw *  hw,
unsigned  reg 
) [inline, static]

Definition at line 2106 of file sky2.h.

References readb, and sky2_hw::regs.

Referenced by sky2_init(), sky2_mac_intr(), sky2_poll(), sky2_ramset(), sky2_remove(), sky2_rx_stop(), and sky2_up().

02107 {
02108         return readb(hw->regs + reg);
02109 }

static void sky2_write32 ( const struct sky2_hw *  hw,
unsigned  reg,
u32  val 
) [inline, static]

Definition at line 2111 of file sky2.h.

References sky2_hw::regs, and writel.

Referenced by rx_set_checksum(), sky2_down(), sky2_hw_error(), sky2_hw_intr(), sky2_le_error(), sky2_mac_init(), sky2_net_irq(), sky2_pci_write32(), sky2_power_on(), sky2_prefetch_init(), sky2_probe(), sky2_qset(), sky2_ramset(), sky2_remove(), sky2_reset(), sky2_rx_start(), sky2_rx_stop(), sky2_set_tx_stfwd(), sky2_status_intr(), and sky2_up().

02112 {
02113         writel(val, hw->regs + reg);
02114 }

static void sky2_write16 ( const struct sky2_hw *  hw,
unsigned  reg,
u16  val 
) [inline, static]

Definition at line 2116 of file sky2.h.

References sky2_hw::regs, and writew.

Referenced by gma_write16(), sky2_down(), sky2_hw_error(), sky2_mac_init(), sky2_pci_write16(), sky2_prefetch_init(), sky2_put_idx(), sky2_remove(), sky2_reset(), sky2_rx_start(), and sky2_up().

02117 {
02118         writew(val, hw->regs + reg);
02119 }

static void sky2_write8 ( const struct sky2_hw *  hw,
unsigned  reg,
u8  val 
) [inline, static]

Definition at line 2121 of file sky2.h.

References sky2_hw::regs, and writeb.

Referenced by sky2_autoneg_done(), sky2_down(), sky2_gmac_reset(), sky2_hw_error(), sky2_hw_intr(), sky2_init(), sky2_link_down(), sky2_link_up(), sky2_mac_init(), sky2_mac_intr(), sky2_phy_init(), sky2_phy_power_down(), sky2_phy_power_up(), sky2_poll(), sky2_power_aux(), sky2_power_on(), sky2_probe(), sky2_ramset(), sky2_remove(), sky2_reset(), sky2_rx_stop(), and sky2_up().

02122 {
02123         writeb(val, hw->regs + reg);
02124 }

static u16 gma_read16 ( const struct sky2_hw *  hw,
unsigned  port,
unsigned  reg 
) [inline, static]

Definition at line 2131 of file sky2.h.

References SK_GMAC_REG, and sky2_read16().

02132 {
02133         return sky2_read16(hw, SK_GMAC_REG(port,reg));
02134 }

static u32 gma_read32 ( struct sky2_hw *  hw,
unsigned  port,
unsigned  reg 
) [inline, static]

Definition at line 2136 of file sky2.h.

References SK_GMAC_REG, sky2_read16(), and u32.

02137 {
02138         unsigned base = SK_GMAC_REG(port, reg);
02139         return (u32) sky2_read16(hw, base)
02140                 | (u32) sky2_read16(hw, base+4) << 16;
02141 }

static void gma_write16 ( const struct sky2_hw *  hw,
unsigned  port,
int  r,
u16  v 
) [inline, static]

Definition at line 2143 of file sky2.h.

References SK_GMAC_REG, and sky2_write16().

02144 {
02145         sky2_write16(hw, SK_GMAC_REG(port,r), v);
02146 }

static void gma_set_addr ( struct sky2_hw *  hw,
unsigned  port,
unsigned  reg,
const u8 *  addr 
) [inline, static]

Definition at line 2148 of file sky2.h.

References gma_write16(), and u16.

02150 {
02151         gma_write16(hw, port, reg,  (u16) addr[0] | ((u16) addr[1] << 8));
02152         gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
02153         gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
02154 }

static u32 sky2_pci_read32 ( const struct sky2_hw *  hw,
unsigned  reg 
) [inline, static]

Definition at line 2157 of file sky2.h.

References sky2_read32(), and Y2_CFG_SPC.

Referenced by sky2_phy_power_down(), sky2_phy_power_up(), and sky2_power_on().

02158 {
02159         return sky2_read32(hw, Y2_CFG_SPC + reg);
02160 }

static u16 sky2_pci_read16 ( const struct sky2_hw *  hw,
unsigned  reg 
) [inline, static]

Definition at line 2162 of file sky2.h.

References sky2_read16(), and Y2_CFG_SPC.

Referenced by sky2_hw_intr(), and sky2_reset().

02163 {
02164         return sky2_read16(hw, Y2_CFG_SPC + reg);
02165 }

static void sky2_pci_write32 ( struct sky2_hw *  hw,
unsigned  reg,
u32  val 
) [inline, static]

Definition at line 2167 of file sky2.h.

References sky2_write32(), and Y2_CFG_SPC.

Referenced by sky2_init(), sky2_phy_power_down(), sky2_phy_power_up(), and sky2_power_on().

02168 {
02169         sky2_write32(hw, Y2_CFG_SPC + reg, val);
02170 }

static void sky2_pci_write16 ( struct sky2_hw *  hw,
unsigned  reg,
u16  val 
) [inline, static]

Definition at line 2172 of file sky2.h.

References sky2_write16(), and Y2_CFG_SPC.

Referenced by sky2_hw_intr(), and sky2_reset().

02173 {
02174         sky2_write16(hw, Y2_CFG_SPC + reg, val);
02175 }

Variable Documentation

struct sky2_status_le packed

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