#include <stdint.h>#include <errno.h>#include <stdio.h>#include <unistd.h>#include <gpxe/ethernet.h>#include <gpxe/if_ether.h>#include <gpxe/iobuf.h>#include <gpxe/malloc.h>#include <gpxe/pci.h>#include <byteswap.h>#include <mii.h>#include "sky2.h"Go to the source code of this file.
Defines | |
| #define | DRV_NAME "sky2" |
| #define | DRV_VERSION "1.22" |
| #define | PFX DRV_NAME " " |
| #define | RX_LE_SIZE 128 |
| #define | RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
| #define | RX_RING_ALIGN 4096 |
| #define | RX_PENDING (RX_LE_SIZE/6 - 2) |
| #define | TX_RING_SIZE 128 |
| #define | TX_PENDING (TX_RING_SIZE - 1) |
| #define | TX_RING_ALIGN 4096 |
| #define | MAX_SKB_TX_LE 4 |
| #define | STATUS_RING_SIZE 512 |
| #define | STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
| #define | STATUS_RING_ALIGN 4096 |
| #define | PHY_RETRIES 1000 |
| #define | SKY2_EEPROM_MAGIC 0x9955aabb |
| #define | RING_NEXT(x, s) (((x)+1) & ((s)-1)) |
Functions | |
| FILE_LICENCE (GPL2_ONLY) | |
| static void | sky2_set_multicast (struct net_device *dev) |
| static int | gm_phy_write (struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
| static int | __gm_phy_read (struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
| static u16 | gm_phy_read (struct sky2_hw *hw, unsigned port, u16 reg) |
| static void | sky2_power_on (struct sky2_hw *hw) |
| static void | sky2_power_aux (struct sky2_hw *hw) |
| static void | sky2_gmac_reset (struct sky2_hw *hw, unsigned port) |
| static void | sky2_phy_init (struct sky2_hw *hw, unsigned port) |
| static void | sky2_phy_power_up (struct sky2_hw *hw, unsigned port) |
| static void | sky2_phy_power_down (struct sky2_hw *hw, unsigned port) |
| static void | sky2_set_tx_stfwd (struct sky2_hw *hw, unsigned port) |
| static void | sky2_mac_init (struct sky2_hw *hw, unsigned port) |
| static void | sky2_ramset (struct sky2_hw *hw, u16 q, u32 start, u32 space) |
| static void | sky2_qset (struct sky2_hw *hw, u16 q) |
| static void | sky2_prefetch_init (struct sky2_hw *hw, u32 qaddr, u64 addr, u32 last) |
| static struct sky2_tx_le * | get_tx_le (struct sky2_port *sky2) |
| static void | tx_init (struct sky2_port *sky2) |
| static struct tx_ring_info * | tx_le_re (struct sky2_port *sky2, struct sky2_tx_le *le) |
| static void | sky2_put_idx (struct sky2_hw *hw, unsigned q, u16 idx) |
| static struct sky2_rx_le * | sky2_next_rx (struct sky2_port *sky2) |
| static void | sky2_rx_add (struct sky2_port *sky2, u8 op, u32 map, unsigned len) |
| static void | sky2_rx_submit (struct sky2_port *sky2, const struct rx_ring_info *re) |
| static void | sky2_rx_map_iob (struct pci_device *pdev __unused, struct rx_ring_info *re, unsigned size __unused) |
| static void | rx_set_checksum (struct sky2_port *sky2) |
| static void | sky2_rx_stop (struct sky2_port *sky2) |
| static void | sky2_rx_clean (struct sky2_port *sky2) |
| static struct io_buffer * | sky2_rx_alloc (struct sky2_port *sky2) |
| static void | sky2_rx_update (struct sky2_port *sky2, unsigned rxq) |
| static int | sky2_rx_start (struct sky2_port *sky2) |
| static void | sky2_free_rings (struct sky2_port *sky2) |
| static int | sky2_up (struct net_device *dev) |
| static int | tx_dist (unsigned tail, unsigned head) |
| static int | tx_avail (const struct sky2_port *sky2) |
| static int | sky2_xmit_frame (struct net_device *dev, struct io_buffer *iob) |
| static void | sky2_tx_complete (struct sky2_port *sky2, u16 done) |
| static void | sky2_tx_clean (struct net_device *dev) |
| static void | sky2_down (struct net_device *dev) |
| static u16 | sky2_phy_speed (const struct sky2_hw *hw, u16 aux) |
| static void | sky2_link_up (struct sky2_port *sky2) |
| static void | sky2_link_down (struct sky2_port *sky2) |
| static int | sky2_autoneg_done (struct sky2_port *sky2, u16 aux) |
| static void | sky2_phy_intr (struct sky2_hw *hw, unsigned port) |
| static struct io_buffer * | receive_new (struct sky2_port *sky2, struct rx_ring_info *re, unsigned int length) |
| static struct io_buffer * | sky2_receive (struct net_device *dev, u16 length, u32 status) |
| static void | sky2_tx_done (struct net_device *dev, u16 last) |
| static void | sky2_status_intr (struct sky2_hw *hw, u16 idx) |
| static void | sky2_hw_error (struct sky2_hw *hw, unsigned port, u32 status) |
| static void | sky2_hw_intr (struct sky2_hw *hw) |
| static void | sky2_mac_intr (struct sky2_hw *hw, unsigned port) |
| static void | sky2_le_error (struct sky2_hw *hw, unsigned port, u16 q, unsigned ring_size __unused) |
| static void | sky2_err_intr (struct sky2_hw *hw, u32 status) |
| static void | sky2_poll (struct net_device *dev) |
| static u32 | sky2_mhz (const struct sky2_hw *hw) |
| static u32 | sky2_us2clk (const struct sky2_hw *hw, u32 us) |
| static u32 | sky2_clk2us (const struct sky2_hw *hw, u32 clk) |
| static int | sky2_init (struct sky2_hw *hw) |
| static void | sky2_reset (struct sky2_hw *hw) |
| static u32 | sky2_supported_modes (const struct sky2_hw *hw) |
| static struct net_device * | sky2_init_netdev (struct sky2_hw *hw, unsigned port) |
| static void | sky2_show_addr (struct net_device *dev) |
| static void | sky2_net_irq (struct net_device *dev, int enable) |
| static int | sky2_probe (struct pci_device *pdev, const struct pci_device_id *ent __unused) |
| static void | sky2_remove (struct pci_device *pdev) |
Variables | |
| static struct pci_device_id | sky2_id_table [] |
| static const unsigned | txqaddr [] = { Q_XA1, Q_XA2 } |
| static const unsigned | rxqaddr [] = { Q_R1, Q_R2 } |
| static const u32 | portirq_msk [] = { Y2_IS_PORT_1, Y2_IS_PORT_2 } |
| static const u16 | copper_fc_adv [] |
| static const u16 | fiber_fc_adv [] |
| static const u16 | gm_fc_disable [] |
| static const u32 | phy_power [] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD } |
| static const u32 | coma_mode [] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA } |
| static struct net_device_operations | sky2_operations |
| struct pci_driver sky2_driver | __pci_driver |
| #define RX_LE_SIZE 128 |
Definition at line 60 of file sky2.c.
Referenced by sky2_err_intr(), sky2_next_rx(), and sky2_rx_start().
| #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
Definition at line 61 of file sky2.c.
Referenced by sky2_free_rings(), sky2_rx_clean(), and sky2_up().
| #define RX_PENDING (RX_LE_SIZE/6 - 2) |
Definition at line 63 of file sky2.c.
Referenced by sky2_receive(), sky2_rx_clean(), sky2_rx_start(), and sky2_up().
| #define TX_PENDING (TX_RING_SIZE - 1) |
| #define STATUS_RING_SIZE 512 |
| #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
| #define STATUS_RING_ALIGN 4096 |
| #define RING_NEXT | ( | x, | |||
| s | ) | (((x)+1) & ((s)-1)) |
Definition at line 78 of file sky2.c.
Referenced by get_tx_le(), sky2_next_rx(), sky2_status_intr(), and sky2_tx_complete().
| FILE_LICENCE | ( | GPL2_ONLY | ) |
| static void sky2_set_multicast | ( | struct net_device * | dev | ) | [static] |
Definition at line 2154 of file sky2.c.
References FC_BOTH, FC_RX, filter(), sky2_port::flow_status, GM_MC_ADDR_H1, GM_MC_ADDR_H2, GM_MC_ADDR_H3, GM_MC_ADDR_H4, GM_RX_CTRL, GM_RXCR_UCF_ENA, gma_read16(), gma_write16(), sky2_port::hw, memset(), netdev_priv(), sky2_port::port, u16, and u8.
Referenced by sky2_up().
02155 { 02156 struct sky2_port *sky2 = netdev_priv(dev); 02157 struct sky2_hw *hw = sky2->hw; 02158 unsigned port = sky2->port; 02159 u16 reg; 02160 u8 filter[8]; 02161 int rx_pause; 02162 02163 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH); 02164 02165 reg = gma_read16(hw, port, GM_RX_CTRL); 02166 reg |= GM_RXCR_UCF_ENA; 02167 02168 memset(filter, 0xff, sizeof(filter)); 02169 02170 gma_write16(hw, port, GM_MC_ADDR_H1, 02171 (u16) filter[0] | ((u16) filter[1] << 8)); 02172 gma_write16(hw, port, GM_MC_ADDR_H2, 02173 (u16) filter[2] | ((u16) filter[3] << 8)); 02174 gma_write16(hw, port, GM_MC_ADDR_H3, 02175 (u16) filter[4] | ((u16) filter[5] << 8)); 02176 gma_write16(hw, port, GM_MC_ADDR_H4, 02177 (u16) filter[6] | ((u16) filter[7] << 8)); 02178 02179 gma_write16(hw, port, GM_RX_CTRL, reg); 02180 }
Definition at line 130 of file sky2.c.
References DBG, sky2_hw::dev, EIO, ETIMEDOUT, GM_SMI_CT_BUSY, GM_SMI_CT_PHY_AD, GM_SMI_CT_REG_AD, GM_SMI_CTRL, GM_SMI_DATA, gma_read16(), gma_write16(), net_device::name, PFX, PHY_ADDR_MARV, PHY_RETRIES, u16, and udelay().
00131 { 00132 int i; 00133 00134 gma_write16(hw, port, GM_SMI_DATA, val); 00135 gma_write16(hw, port, GM_SMI_CTRL, 00136 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); 00137 00138 for (i = 0; i < PHY_RETRIES; i++) { 00139 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 00140 if (ctrl == 0xffff) 00141 goto io_error; 00142 00143 if (!(ctrl & GM_SMI_CT_BUSY)) 00144 return 0; 00145 00146 udelay(10); 00147 } 00148 00149 DBG(PFX "%s: phy write timeout\n", hw->dev[port]->name); 00150 return -ETIMEDOUT; 00151 00152 io_error: 00153 DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name); 00154 return -EIO; 00155 }
Definition at line 157 of file sky2.c.
References DBG, sky2_hw::dev, EIO, ETIMEDOUT, GM_SMI_CT_OP_RD, GM_SMI_CT_PHY_AD, GM_SMI_CT_RD_VAL, GM_SMI_CT_REG_AD, GM_SMI_CTRL, GM_SMI_DATA, gma_read16(), gma_write16(), net_device::name, PFX, PHY_ADDR_MARV, PHY_RETRIES, u16, and udelay().
00158 { 00159 int i; 00160 00161 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) 00162 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 00163 00164 for (i = 0; i < PHY_RETRIES; i++) { 00165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL); 00166 if (ctrl == 0xffff) 00167 goto io_error; 00168 00169 if (ctrl & GM_SMI_CT_RD_VAL) { 00170 *val = gma_read16(hw, port, GM_SMI_DATA); 00171 return 0; 00172 } 00173 00174 udelay(10); 00175 } 00176 00177 DBG(PFX "%s: phy read timeout\n", hw->dev[port]->name); 00178 return -ETIMEDOUT; 00179 io_error: 00180 DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name); 00181 return -EIO; 00182 }
Definition at line 184 of file sky2.c.
References __gm_phy_read(), and u16.
00185 { 00186 u16 v = 0; 00187 __gm_phy_read(hw, port, reg, &v); 00188 return v; 00189 }
| static void sky2_power_on | ( | struct sky2_hw * | hw | ) | [static] |
Definition at line 192 of file sky2.c.
References B0_POWER_CTRL, B2_GP_IO, B2_Y2_CLK_CTRL, B2_Y2_CLK_GATE, sky2_hw::chip_id, CHIP_ID_YUKON_XL, sky2_hw::chip_rev, sky2_hw::flags, GLB_GPIO_STAT_RACE_DIS, P_ASPM_CONTROL_MSK, P_CTL_TIM_VMAIN_AV_MSK, PC_VAUX_ENA, PC_VAUX_OFF, PC_VCC_ENA, PC_VCC_ON, PCI_CFG_REG_1, PCI_DEV_REG3, PCI_DEV_REG4, PCI_DEV_REG5, SKY2_HW_ADV_POWER_CTL, sky2_pci_read32(), sky2_pci_write32(), sky2_read32(), sky2_write32(), sky2_write8(), u32, Y2_CLK_DIV_DIS, Y2_CLK_GAT_LNK1_DIS, Y2_CLK_GAT_LNK2_DIS, Y2_COR_CLK_LNK1_DIS, Y2_COR_CLK_LNK2_DIS, Y2_PCI_CLK_LNK1_DIS, and Y2_PCI_CLK_LNK2_DIS.
Referenced by sky2_reset().
00193 { 00194 /* switch power to VCC (WA for VAUX problem) */ 00195 sky2_write8(hw, B0_POWER_CTRL, 00196 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 00197 00198 /* disable Core Clock Division, */ 00199 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 00200 00201 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 00202 /* enable bits are inverted */ 00203 sky2_write8(hw, B2_Y2_CLK_GATE, 00204 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 00205 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 00206 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 00207 else 00208 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 00209 00210 if (hw->flags & SKY2_HW_ADV_POWER_CTL) { 00211 u32 reg; 00212 00213 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 00214 00215 reg = sky2_pci_read32(hw, PCI_DEV_REG4); 00216 /* set all bits to 0 except bits 15..12 and 8 */ 00217 reg &= P_ASPM_CONTROL_MSK; 00218 sky2_pci_write32(hw, PCI_DEV_REG4, reg); 00219 00220 reg = sky2_pci_read32(hw, PCI_DEV_REG5); 00221 /* set all bits to 0 except bits 28 & 27 */ 00222 reg &= P_CTL_TIM_VMAIN_AV_MSK; 00223 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 00224 00225 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 00226 00227 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ 00228 reg = sky2_read32(hw, B2_GP_IO); 00229 reg |= GLB_GPIO_STAT_RACE_DIS; 00230 sky2_write32(hw, B2_GP_IO, reg); 00231 00232 sky2_read32(hw, B2_GP_IO); 00233 } 00234 }
| static void sky2_power_aux | ( | struct sky2_hw * | hw | ) | [static] |
Definition at line 236 of file sky2.c.
References B0_CTST, B0_POWER_CTRL, B2_Y2_CLK_GATE, sky2_hw::chip_id, CHIP_ID_YUKON_XL, sky2_hw::chip_rev, PC_VAUX_ENA, PC_VAUX_ON, PC_VCC_ENA, PC_VCC_OFF, sky2_read16(), sky2_write8(), Y2_CLK_GAT_LNK1_DIS, Y2_CLK_GAT_LNK2_DIS, Y2_COR_CLK_LNK1_DIS, Y2_COR_CLK_LNK2_DIS, Y2_PCI_CLK_LNK1_DIS, Y2_PCI_CLK_LNK2_DIS, and Y2_VAUX_AVAIL.
Referenced by sky2_remove().
00237 { 00238 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 00239 sky2_write8(hw, B2_Y2_CLK_GATE, 0); 00240 else 00241 /* enable bits are inverted */ 00242 sky2_write8(hw, B2_Y2_CLK_GATE, 00243 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 00244 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 00245 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); 00246 00247 /* switch power to VAUX */ 00248 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) 00249 sky2_write8(hw, B0_POWER_CTRL, 00250 (PC_VAUX_ENA | PC_VCC_ENA | 00251 PC_VAUX_ON | PC_VCC_OFF)); 00252 }
| static void sky2_gmac_reset | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static] |
Definition at line 254 of file sky2.c.
References GM_MC_ADDR_H1, GM_MC_ADDR_H2, GM_MC_ADDR_H3, GM_MC_ADDR_H4, GM_RX_CTRL, GM_RXCR_MCF_ENA, GM_RXCR_UCF_ENA, gma_read16(), gma_write16(), GMAC_IRQ_MSK, SK_REG, sky2_write8(), and u16.
Referenced by sky2_down(), and sky2_reset().
00255 { 00256 u16 reg; 00257 00258 /* disable all GMAC IRQ's */ 00259 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 00260 00261 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 00262 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 00263 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 00264 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 00265 00266 reg = gma_read16(hw, port, GM_RX_CTRL); 00267 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 00268 gma_write16(hw, port, GM_RX_CTRL, reg); 00269 }
| static void sky2_phy_init | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static] |
Definition at line 296 of file sky2.c.
References ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_100baseT_Full, ADVERTISED_100baseT_Half, ADVERTISED_10baseT_Full, ADVERTISED_10baseT_Half, sky2_port::advertising, sky2_port::autoneg, AUTONEG_DISABLE, AUTONEG_ENABLE, BLINK_84MS, sky2_hw::chip_id, CHIP_ID_YUKON_EC, CHIP_ID_YUKON_EC_U, CHIP_ID_YUKON_EX, CHIP_ID_YUKON_FE, CHIP_ID_YUKON_FE_P, CHIP_ID_YUKON_SUPR, CHIP_ID_YUKON_UL_2, CHIP_ID_YUKON_XL, sky2_hw::chip_rev, CHIP_REV_YU_FE2_A0, copper_fc_adv, sky2_hw::dev, sky2_port::duplex, DUPLEX_FULL, FC_NONE, FC_RX, fiber_fc_adv, sky2_hw::flags, sky2_port::flow_mode, gm_fc_disable, GM_GP_CTRL, GM_GPCR_AU_ALL_DIS, GM_GPCR_DUP_FULL, GM_GPCR_SPEED_100, GM_GPCR_SPEED_1000, gm_phy_read(), gm_phy_write(), gma_write16(), GMAC_CTRL, GMC_PAUSE_OFF, GMC_PAUSE_ON, LED_PAR_CTRL_ACT_BL, LED_PAR_CTRL_LINK, LED_PAR_CTRL_SPEED, MAC_TX_CLK_25_MHZ, MO_LED_OFF, MO_LED_ON, netdev_priv(), PHY_AN_CSMA, PHY_CT_ANE, PHY_CT_DUP_MD, PHY_CT_RE_CFG, PHY_CT_RESET, PHY_CT_SP100, PHY_CT_SP1000, PHY_M_1000C_AFD, PHY_M_1000C_AHD, PHY_M_1000C_MSE, PHY_M_AN_1000X_AFD, PHY_M_AN_1000X_AHD, PHY_M_AN_100_FD, PHY_M_AN_100_HD, PHY_M_AN_10_FD, PHY_M_AN_10_HD, PHY_M_DEF_MSK, PHY_M_EC_DOWN_S_ENA, PHY_M_EC_DSC_2, PHY_M_EC_M_DSC, PHY_M_EC_M_DSC_MSK, PHY_M_EC_MAC_S, PHY_M_EC_MAC_S_MSK, PHY_M_EC_S_DSC, PHY_M_EC_S_DSC_MSK, PHY_M_FELP_LED0_CTRL, PHY_M_FELP_LED1_CTRL, PHY_M_FELP_LED1_MSK, PHY_M_FELP_LED2_CTRL, PHY_M_FESC_SEL_CL_A, PHY_M_FIB_SIGD_POL, PHY_M_IS_AN_COMPL, PHY_M_LED_BLINK_RT, PHY_M_LED_MO_100, PHY_M_LED_MO_RX, PHY_M_LED_PULS_DUR, PHY_M_LEDC_INIT_CTRL, PHY_M_LEDC_LOS_CTRL, PHY_M_LEDC_STA0_CTRL, PHY_M_LEDC_STA1_CTRL, PHY_M_LEDC_TX_CTRL, PHY_M_MAC_MD_1000BX, PHY_M_MAC_MD_MSK, PHY_M_MAC_MODE_SEL, PHY_M_PC_DIS_SCRAMB, PHY_M_PC_DOWN_S_ENA, PHY_M_PC_DSC, PHY_M_PC_DSC_MSK, PHY_M_PC_EN_DET_MSK, PHY_M_PC_ENA_AUTO, PHY_M_PC_ENA_ENE_DT, PHY_M_PC_ENA_LIP_NP, PHY_M_PC_MDI_XMODE, PHY_M_PC_MDIX_MSK, PHY_M_POLC_INIT_CTRL, PHY_M_POLC_IS0_P_MIX, PHY_M_POLC_LOS_CTRL, PHY_M_POLC_LS1_P_MIX, PHY_M_POLC_STA0_CTRL, PHY_M_POLC_STA1_CTRL, PHY_MARV_1000T_CTRL, PHY_MARV_AUNE_ADV, PHY_MARV_CTRL, PHY_MARV_EXT_ADR, PHY_MARV_EXT_CTRL, PHY_MARV_FE_LED_PAR, PHY_MARV_FE_SPEC_2, PHY_MARV_INT_MASK, PHY_MARV_LED_CTRL, PHY_MARV_LED_OVER, PHY_MARV_PAGE_ADDR, PHY_MARV_PAGE_DATA, PHY_MARV_PHY_CTRL, PHY_MARV_PHY_STAT, sky2_hw::pmd_type, PULS_170MS, SK_REG, SKY2_HW_FIBRE_PHY, SKY2_HW_GIGABIT, SKY2_HW_NEWER_PHY, sky2_is_copper(), sky2_write8(), sky2_port::speed, SPEED_100, SPEED_1000, and u16.
Referenced by sky2_link_down(), and sky2_mac_init().
00297 { 00298 struct sky2_port *sky2 = netdev_priv(hw->dev[port]); 00299 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; 00300 00301 if (sky2->autoneg == AUTONEG_ENABLE && 00302 !(hw->flags & SKY2_HW_NEWER_PHY)) { 00303 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 00304 00305 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 00306 PHY_M_EC_MAC_S_MSK); 00307 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 00308 00309 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */ 00310 if (hw->chip_id == CHIP_ID_YUKON_EC) 00311 /* set downshift counter to 3x and enable downshift */ 00312 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; 00313 else 00314 /* set master & slave downshift counter to 1x */ 00315 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 00316 00317 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 00318 } 00319 00320 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 00321 if (sky2_is_copper(hw)) { 00322 if (!(hw->flags & SKY2_HW_GIGABIT)) { 00323 /* enable automatic crossover */ 00324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; 00325 00326 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 00327 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 00328 u16 spec; 00329 00330 /* Enable Class A driver for FE+ A0 */ 00331 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2); 00332 spec |= PHY_M_FESC_SEL_CL_A; 00333 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec); 00334 } 00335 } else { 00336 /* disable energy detect */ 00337 ctrl &= ~PHY_M_PC_EN_DET_MSK; 00338 00339 /* enable automatic crossover */ 00340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); 00341 00342 /* downshift on PHY 88E1112 and 88E1149 is changed */ 00343 if (sky2->autoneg == AUTONEG_ENABLE 00344 && (hw->flags & SKY2_HW_NEWER_PHY)) { 00345 /* set downshift counter to 3x and enable downshift */ 00346 ctrl &= ~PHY_M_PC_DSC_MSK; 00347 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; 00348 } 00349 } 00350 } else { 00351 /* workaround for deviation #4.88 (CRC errors) */ 00352 /* disable Automatic Crossover */ 00353 00354 ctrl &= ~PHY_M_PC_MDIX_MSK; 00355 } 00356 00357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 00358 00359 /* special setup for PHY 88E1112 Fiber */ 00360 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) { 00361 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 00362 00363 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ 00364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 00365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 00366 ctrl &= ~PHY_M_MAC_MD_MSK; 00367 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); 00368 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 00369 00370 if (hw->pmd_type == 'P') { 00371 /* select page 1 to access Fiber registers */ 00372 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); 00373 00374 /* for SFP-module set SIGDET polarity to low */ 00375 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 00376 ctrl |= PHY_M_FIB_SIGD_POL; 00377 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 00378 } 00379 00380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 00381 } 00382 00383 ctrl = PHY_CT_RESET; 00384 ct1000 = 0; 00385 adv = PHY_AN_CSMA; 00386 reg = 0; 00387 00388 if (sky2->autoneg == AUTONEG_ENABLE) { 00389 if (sky2_is_copper(hw)) { 00390 if (sky2->advertising & ADVERTISED_1000baseT_Full) 00391 ct1000 |= PHY_M_1000C_AFD; 00392 if (sky2->advertising & ADVERTISED_1000baseT_Half) 00393 ct1000 |= PHY_M_1000C_AHD; 00394 if (sky2->advertising & ADVERTISED_100baseT_Full) 00395 adv |= PHY_M_AN_100_FD; 00396 if (sky2->advertising & ADVERTISED_100baseT_Half) 00397 adv |= PHY_M_AN_100_HD; 00398 if (sky2->advertising & ADVERTISED_10baseT_Full) 00399 adv |= PHY_M_AN_10_FD; 00400 if (sky2->advertising & ADVERTISED_10baseT_Half) 00401 adv |= PHY_M_AN_10_HD; 00402 00403 adv |= copper_fc_adv[sky2->flow_mode]; 00404 } else { /* special defines for FIBER (88E1040S only) */ 00405 if (sky2->advertising & ADVERTISED_1000baseT_Full) 00406 adv |= PHY_M_AN_1000X_AFD; 00407 if (sky2->advertising & ADVERTISED_1000baseT_Half) 00408 adv |= PHY_M_AN_1000X_AHD; 00409 00410 adv |= fiber_fc_adv[sky2->flow_mode]; 00411 } 00412 00413 /* Restart Auto-negotiation */ 00414 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 00415 } else { 00416 /* forced speed/duplex settings */ 00417 ct1000 = PHY_M_1000C_MSE; 00418 00419 /* Disable auto update for duplex flow control and speed */ 00420 reg |= GM_GPCR_AU_ALL_DIS; 00421 00422 switch (sky2->speed) { 00423 case SPEED_1000: 00424 ctrl |= PHY_CT_SP1000; 00425 reg |= GM_GPCR_SPEED_1000; 00426 break; 00427 case SPEED_100: 00428 ctrl |= PHY_CT_SP100; 00429 reg |= GM_GPCR_SPEED_100; 00430 break; 00431 } 00432 00433 if (sky2->duplex == DUPLEX_FULL) { 00434 reg |= GM_GPCR_DUP_FULL; 00435 ctrl |= PHY_CT_DUP_MD; 00436 } else if (sky2->speed < SPEED_1000) 00437 sky2->flow_mode = FC_NONE; 00438 00439 00440 reg |= gm_fc_disable[sky2->flow_mode]; 00441 00442 /* Forward pause packets to GMAC? */ 00443 if (sky2->flow_mode & FC_RX) 00444 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 00445 else 00446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 00447 } 00448 00449 gma_write16(hw, port, GM_GP_CTRL, reg); 00450 00451 if (hw->flags & SKY2_HW_GIGABIT) 00452 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 00453 00454 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 00455 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 00456 00457 /* Setup Phy LED's */ 00458 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); 00459 ledover = 0; 00460 00461 switch (hw->chip_id) { 00462 case CHIP_ID_YUKON_FE: 00463 /* on 88E3082 these bits are at 11..9 (shifted left) */ 00464 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; 00465 00466 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); 00467 00468 /* delete ACT LED control bits */ 00469 ctrl &= ~PHY_M_FELP_LED1_MSK; 00470 /* change ACT LED control to blink mode */ 00471 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); 00472 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 00473 break; 00474 00475 case CHIP_ID_YUKON_FE_P: 00476 /* Enable Link Partner Next Page */ 00477 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 00478 ctrl |= PHY_M_PC_ENA_LIP_NP; 00479 00480 /* disable Energy Detect and enable scrambler */ 00481 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB); 00482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 00483 00484 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */ 00485 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) | 00486 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) | 00487 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED); 00488 00489 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); 00490 break; 00491 00492 case CHIP_ID_YUKON_XL: 00493 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 00494 00495 /* select page 3 to access LED control register */ 00496 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 00497 00498 /* set LED Function Control register */ 00499 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 00500 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 00501 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ 00502 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 00503 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ 00504 00505 /* set Polarity Control register */ 00506 gm_phy_write(hw, port, PHY_MARV_PHY_STAT, 00507 (PHY_M_POLC_LS1_P_MIX(4) | 00508 PHY_M_POLC_IS0_P_MIX(4) | 00509 PHY_M_POLC_LOS_CTRL(2) | 00510 PHY_M_POLC_INIT_CTRL(2) | 00511 PHY_M_POLC_STA1_CTRL(2) | 00512 PHY_M_POLC_STA0_CTRL(2))); 00513 00514 /* restore page register */ 00515 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 00516 break; 00517 00518 case CHIP_ID_YUKON_EC_U: 00519 case CHIP_ID_YUKON_EX: 00520 case CHIP_ID_YUKON_SUPR: 00521 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); 00522 00523 /* select page 3 to access LED control register */ 00524 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); 00525 00526 /* set LED Function Control register */ 00527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, 00528 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ 00529 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ 00530 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ 00531 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ 00532 00533 /* set Blink Rate in LED Timer Control Register */ 00534 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 00535 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); 00536 /* restore page register */ 00537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); 00538 break; 00539 00540 default: 00541 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ 00542 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; 00543 00544 /* turn off the Rx LED (LED_RX) */ 00545 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); 00546 } 00547 00548 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) { 00549 /* apply fixes in PHY AFE */ 00550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); 00551 00552 /* increase differential signal amplitude in 10BASE-T */ 00553 gm_phy_write(hw, port, 0x18, 0xaa99); 00554 gm_phy_write(hw, port, 0x17, 0x2011); 00555 00556 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 00557 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ 00558 gm_phy_write(hw, port, 0x18, 0xa204); 00559 gm_phy_write(hw, port, 0x17, 0x2002); 00560 } 00561 00562 /* set page register to 0 */ 00563 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 00564 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P && 00565 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 00566 /* apply workaround for integrated resistors calibration */ 00567 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17); 00568 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60); 00569 } else if (hw->chip_id != CHIP_ID_YUKON_EX && 00570 hw->chip_id < CHIP_ID_YUKON_SUPR) { 00571 /* no effect on Yukon-XL */ 00572 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); 00573 00574 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { 00575 /* turn on 100 Mbps LED (LED_LINK100) */ 00576 ledover |= PHY_M_LED_MO_100(MO_LED_ON); 00577 } 00578 00579 if (ledover) 00580 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); 00581 00582 } 00583 00584 /* Enable phy interrupt on auto-negotiation complete (or link up) */ 00585 if (sky2->autoneg == AUTONEG_ENABLE) 00586 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); 00587 else 00588 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 00589 }
| static void sky2_phy_power_up | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static] |
Definition at line 594 of file sky2.c.
References B2_TST_CTRL1, sky2_hw::chip_id, CHIP_ID_YUKON_FE, CHIP_ID_YUKON_XL, sky2_hw::chip_rev, coma_mode, sky2_hw::flags, gm_phy_write(), GPC_RST_CLR, GPHY_CTRL, PCI_DEV_REG1, PHY_CT_ANE, PHY_MARV_CTRL, phy_power, SK_REG, SKY2_HW_ADV_POWER_CTL, sky2_pci_read32(), sky2_pci_write32(), sky2_write8(), TST_CFG_WRITE_OFF, TST_CFG_WRITE_ON, and u32.
Referenced by sky2_mac_init().
00595 { 00596 u32 reg1; 00597 00598 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 00599 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 00600 reg1 &= ~phy_power[port]; 00601 00602 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) 00603 reg1 |= coma_mode[port]; 00604 00605 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 00606 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 00607 sky2_pci_read32(hw, PCI_DEV_REG1); 00608 00609 if (hw->chip_id == CHIP_ID_YUKON_FE) 00610 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE); 00611 else if (hw->flags & SKY2_HW_ADV_POWER_CTL) 00612 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 00613 }
| static void sky2_phy_power_down | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static] |
Definition at line 615 of file sky2.c.
References B2_TST_CTRL1, sky2_hw::chip_id, CHIP_ID_YUKON_EC, CHIP_ID_YUKON_EC_U, sky2_hw::flags, GM_GP_CTRL, GM_GPCR_AU_ALL_DIS, GM_GPCR_FL_PASS, GM_GPCR_SPEED_100, gm_phy_read(), gm_phy_write(), gma_write16(), GMAC_CTRL, GMC_RST_CLR, GPC_RST_CLR, GPHY_CTRL, PCI_DEV_REG1, PHY_CT_PDOWN, PHY_M_MAC_GMIF_PUP, PHY_M_PC_POW_D_ENA, PHY_MARV_CTRL, PHY_MARV_EXT_ADR, PHY_MARV_PHY_CTRL, phy_power, SK_REG, SKY2_HW_NEWER_PHY, sky2_pci_read32(), sky2_pci_write32(), sky2_write8(), TST_CFG_WRITE_OFF, TST_CFG_WRITE_ON, u16, and u32.
Referenced by sky2_down().
00616 { 00617 u32 reg1; 00618 u16 ctrl; 00619 00620 /* release GPHY Control reset */ 00621 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 00622 00623 /* release GMAC reset */ 00624 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 00625 00626 if (hw->flags & SKY2_HW_NEWER_PHY) { 00627 /* select page 2 to access MAC control register */ 00628 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 00629 00630 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 00631 /* allow GMII Power Down */ 00632 ctrl &= ~PHY_M_MAC_GMIF_PUP; 00633 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 00634 00635 /* set page register back to 0 */ 00636 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 00637 } 00638 00639 /* setup General Purpose Control Register */ 00640 gma_write16(hw, port, GM_GP_CTRL, 00641 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS); 00642 00643 if (hw->chip_id != CHIP_ID_YUKON_EC) { 00644 if (hw->chip_id == CHIP_ID_YUKON_EC_U) { 00645 /* select page 2 to access MAC control register */ 00646 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); 00647 00648 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 00649 /* enable Power Down */ 00650 ctrl |= PHY_M_PC_POW_D_ENA; 00651 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 00652 00653 /* set page register back to 0 */ 00654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0); 00655 } 00656 00657 /* set IEEE compatible Power Down Mode (dev. #4.99) */ 00658 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN); 00659 } 00660 00661 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 00662 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); 00663 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ 00664 sky2_pci_write32(hw, PCI_DEV_REG1, reg1); 00665 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 00666 }
| static void sky2_set_tx_stfwd | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static] |
Definition at line 668 of file sky2.c.
References sky2_hw::chip_id, CHIP_ID_YUKON_EX, CHIP_ID_YUKON_FE_P, CHIP_ID_YUKON_SUPR, sky2_hw::chip_rev, CHIP_REV_YU_EX_A0, SK_REG, sky2_write32(), TX_GMF_CTRL_T, TX_JUMBO_DIS, and TX_STFW_ENA.
Referenced by sky2_mac_init().
00669 { 00670 if ( (hw->chip_id == CHIP_ID_YUKON_EX && 00671 hw->chip_rev != CHIP_REV_YU_EX_A0) || 00672 hw->chip_id == CHIP_ID_YUKON_FE_P || 00673 hw->chip_id == CHIP_ID_YUKON_SUPR) { 00674 /* disable jumbo frames on devices that support them */ 00675 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), 00676 TX_JUMBO_DIS | TX_STFW_ENA); 00677 } else { 00678 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA); 00679 } 00680 }
| static void sky2_mac_init | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static] |
Definition at line 682 of file sky2.c.
References sky2_hw::chip_id, CHIP_ID_YUKON_EX, CHIP_ID_YUKON_FE_P, CHIP_ID_YUKON_XL, sky2_hw::chip_rev, CHIP_REV_YU_FE2_A0, DATA_BLIND_DEF, DATA_BLIND_VAL, sky2_hw::dev, sky2_hw::flags, GM_MIB_CNT_BASE, GM_MIB_CNT_END, GM_PAR_MIB_CLR, GM_PHY_ADDR, gm_phy_read(), GM_RX_CTRL, GM_RX_IRQ_MSK, GM_RXCR_CRC_DIS, GM_RXCR_MCF_ENA, GM_RXCR_UCF_ENA, GM_SERIAL_MODE, GM_SMOD_VLAN_ENA, GM_SRC_ADDR_1L, GM_SRC_ADDR_2L, GM_TR_IRQ_MSK, GM_TX_CTRL, GM_TX_FLOW_CTRL, GM_TX_IRQ_MSK, GM_TX_PARAM, gma_read16(), gma_set_addr(), gma_write16(), GMAC_CTRL, GMAC_DEF_MSK, GMAC_IRQ_MSK, GMAC_IRQ_SRC, GMC_RST_CLR, GMC_RST_SET, GMF_OPER_ON, GMF_RST_CLR, GMF_RX_F_FL_ON, GMF_RX_OVER_ON, GMR_FS_ANY_ERR, GPC_RST_CLR, GPC_RST_SET, GPHY_CTRL, IPG_DATA_DEF, IPG_DATA_VAL, net_device::ll_addr, PHY_MARV_ID0, PHY_MARV_ID0_VAL, PHY_MARV_ID1, PHY_MARV_ID1_Y2, PHY_MARV_INT_MASK, RX_GMF_CTRL_T, RX_GMF_FL_MSK, RX_GMF_FL_THR, RX_GMF_FL_THR_DEF, RX_GMF_LP_THR, RX_GMF_UP_THR, SK_REG, SKY2_HW_RAM_BUFFER, sky2_phy_init(), sky2_phy_power_up(), sky2_read16(), sky2_set_tx_stfwd(), sky2_write16(), sky2_write32(), sky2_write8(), TX_BACK_OFF_LIM, TX_BOF_LIM_DEF, TX_COL_DEF, TX_COL_THR, TX_DYN_WM_ENA, TX_GMF_CTRL_T, TX_GMF_EA, TX_IPG_JAM_DATA, TX_IPG_JAM_DEF, TX_JAM_IPG_DEF, TX_JAM_IPG_VAL, TX_JAM_LEN_DEF, TX_JAM_LEN_VAL, u16, u32, and u8.
Referenced by sky2_up().
00683 { 00684 u16 reg; 00685 u32 rx_reg; 00686 int i; 00687 const u8 *addr = hw->dev[port]->ll_addr; 00688 00689 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 00690 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR); 00691 00692 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 00693 00694 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { 00695 /* WA DEV_472 -- looks like crossed wires on port 2 */ 00696 /* clear GMAC 1 Control reset */ 00697 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); 00698 do { 00699 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); 00700 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); 00701 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || 00702 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || 00703 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); 00704 } 00705 00706 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 00707 00708 /* Enable Transmit FIFO Underrun */ 00709 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 00710 00711 sky2_phy_power_up(hw, port); 00712 sky2_phy_init(hw, port); 00713 00714 /* MIB clear */ 00715 reg = gma_read16(hw, port, GM_PHY_ADDR); 00716 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 00717 00718 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) 00719 gma_read16(hw, port, i); 00720 gma_write16(hw, port, GM_PHY_ADDR, reg); 00721 00722 /* transmit control */ 00723 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 00724 00725 /* receive control reg: unicast + multicast + no FCS */ 00726 gma_write16(hw, port, GM_RX_CTRL, 00727 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 00728 00729 /* transmit flow control */ 00730 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 00731 00732 /* transmit parameter */ 00733 gma_write16(hw, port, GM_TX_PARAM, 00734 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 00735 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 00736 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | 00737 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 00738 00739 /* serial mode register */ 00740 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | 00741 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 00742 00743 gma_write16(hw, port, GM_SERIAL_MODE, reg); 00744 00745 /* virtual address for data */ 00746 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 00747 00748 /* physical address: used for pause frames */ 00749 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 00750 00751 /* ignore counter overflows */ 00752 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 00753 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 00754 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 00755 00756 /* Configure Rx MAC FIFO */ 00757 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 00758 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 00759 if (hw->chip_id == CHIP_ID_YUKON_EX || 00760 hw->chip_id == CHIP_ID_YUKON_FE_P) 00761 rx_reg |= GMF_RX_OVER_ON; 00762 00763 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg); 00764 00765 if (hw->chip_id == CHIP_ID_YUKON_XL) { 00766 /* Hardware errata - clear flush mask */ 00767 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0); 00768 } else { 00769 /* Flush Rx MAC FIFO on any flow control or error */ 00770 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 00771 } 00772 00773 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */ 00774 reg = RX_GMF_FL_THR_DEF + 1; 00775 /* Another magic mystery workaround from sk98lin */ 00776 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 00777 hw->chip_rev == CHIP_REV_YU_FE2_A0) 00778 reg = 0x178; 00779 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg); 00780 00781 /* Configure Tx MAC FIFO */ 00782 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 00783 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 00784 00785 /* On chips without ram buffer, pause is controled by MAC level */ 00786 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) { 00787 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); 00788 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); 00789 00790 sky2_set_tx_stfwd(hw, port); 00791 } 00792 00793 if (hw->chip_id == CHIP_ID_YUKON_FE_P && 00794 hw->chip_rev == CHIP_REV_YU_FE2_A0) { 00795 /* disable dynamic watermark */ 00796 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA)); 00797 reg &= ~TX_DYN_WM_ENA; 00798 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg); 00799 } 00800 }
Definition at line 803 of file sky2.c.
References Q_R1, Q_R2, RB_ADDR, RB_CTRL, RB_ENA_OP_MD, RB_ENA_STFWD, RB_END, RB_RP, RB_RST_CLR, RB_RX_LTHP, RB_RX_LTPP, RB_RX_UTHP, RB_RX_UTPP, RB_START, RB_WP, sky2_read8(), sky2_write32(), sky2_write8(), tp, and u32.
Referenced by sky2_up().
00804 { 00805 u32 end; 00806 00807 /* convert from K bytes to qwords used for hw register */ 00808 start *= 1024/8; 00809 space *= 1024/8; 00810 end = start + space - 1; 00811 00812 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 00813 sky2_write32(hw, RB_ADDR(q, RB_START), start); 00814 sky2_write32(hw, RB_ADDR(q, RB_END), end); 00815 sky2_write32(hw, RB_ADDR(q, RB_WP), start); 00816 sky2_write32(hw, RB_ADDR(q, RB_RP), start); 00817 00818 if (q == Q_R1 || q == Q_R2) { 00819 u32 tp = space - space/4; 00820 00821 /* On receive queue's set the thresholds 00822 * give receiver priority when > 3/4 full 00823 * send pause when down to 2K 00824 */ 00825 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); 00826 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); 00827 00828 tp = space - 2048/8; 00829 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); 00830 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); 00831 } else { 00832 /* Enable store & forward on Tx queue's because 00833 * Tx FIFO is only 1K on Yukon 00834 */ 00835 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 00836 } 00837 00838 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 00839 sky2_read8(hw, RB_ADDR(q, RB_CTRL)); 00840 }
Definition at line 843 of file sky2.c.
References BMU_CLR_RESET, BMU_FIFO_OP_ON, BMU_OPER_INIT, BMU_WM_DEFAULT, Q_ADDR, Q_CSR, Q_WM, and sky2_write32().
Referenced by sky2_rx_start(), and sky2_up().
00844 { 00845 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); 00846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); 00847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); 00848 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); 00849 }
Definition at line 854 of file sky2.c.
References PREF_UNIT_ADDR_HI, PREF_UNIT_ADDR_LO, PREF_UNIT_CTRL, PREF_UNIT_LAST_IDX, PREF_UNIT_OP_ON, PREF_UNIT_RST_CLR, PREF_UNIT_RST_SET, sky2_read32(), sky2_write16(), sky2_write32(), u32, and Y2_QADDR.
Referenced by sky2_rx_start(), and sky2_up().
00856 { 00857 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 00858 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); 00859 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); 00860 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); 00861 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); 00862 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); 00863 00864 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); 00865 }
| static struct sky2_tx_le* get_tx_le | ( | struct sky2_port * | sky2 | ) | [static, read] |
Definition at line 867 of file sky2.c.
References sky2_tx_le::ctrl, RING_NEXT, sky2_port::tx_le, sky2_port::tx_prod, and TX_RING_SIZE.
Referenced by sky2_xmit_frame(), and tx_init().
00868 { 00869 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; 00870 00871 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE); 00872 le->ctrl = 0; 00873 return le; 00874 }
| static void tx_init | ( | struct sky2_port * | sky2 | ) | [static] |
Definition at line 876 of file sky2.c.
References sky2_tx_le::addr, get_tx_le(), HW_OWNER, OP_ADDR64, sky2_tx_le::opcode, sky2_port::tx_cons, and sky2_port::tx_prod.
Referenced by sky2_up().
00877 { 00878 struct sky2_tx_le *le; 00879 00880 sky2->tx_prod = sky2->tx_cons = 0; 00881 00882 le = get_tx_le(sky2); 00883 le->addr = 0; 00884 le->opcode = OP_ADDR64 | HW_OWNER; 00885 }
| static struct tx_ring_info* tx_le_re | ( | struct sky2_port * | sky2, | |
| struct sky2_tx_le * | le | |||
| ) | [static, read] |
Definition at line 887 of file sky2.c.
References sky2_port::tx_le, and sky2_port::tx_ring.
Referenced by sky2_xmit_frame().
Definition at line 894 of file sky2.c.
References DBGIO, PFX, PREF_UNIT_PUT_IDX, sky2_write16(), wmb, and Y2_QADDR.
Referenced by sky2_rx_update(), and sky2_xmit_frame().
00895 { 00896 /* Make sure write' to descriptors are complete before we tell hardware */ 00897 wmb(); 00898 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); 00899 DBGIO(PFX "queue %#x idx <- %d\n", q, idx); 00900 }
| static struct sky2_rx_le* sky2_next_rx | ( | struct sky2_port * | sky2 | ) | [static, read] |
Definition at line 903 of file sky2.c.
References sky2_rx_le::ctrl, RING_NEXT, sky2_port::rx_le, RX_LE_SIZE, and sky2_port::rx_put.
Referenced by rx_set_checksum(), and sky2_rx_add().
00904 { 00905 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; 00906 00907 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); 00908 le->ctrl = 0; 00909 return le; 00910 }
Definition at line 913 of file sky2.c.
References sky2_rx_le::addr, cpu_to_le16, cpu_to_le32, HW_OWNER, sky2_rx_le::length, sky2_rx_le::opcode, and sky2_next_rx().
Referenced by sky2_rx_submit().
00915 { 00916 struct sky2_rx_le *le; 00917 00918 le = sky2_next_rx(sky2); 00919 le->addr = cpu_to_le32(map); 00920 le->length = cpu_to_le16(len); 00921 le->opcode = op | HW_OWNER; 00922 }
| static void sky2_rx_submit | ( | struct sky2_port * | sky2, | |
| const struct rx_ring_info * | re | |||
| ) | [static] |
Definition at line 925 of file sky2.c.
References rx_ring_info::data_addr, OP_PACKET, sky2_port::rx_data_size, and sky2_rx_add().
Referenced by sky2_receive(), and sky2_rx_start().
00927 { 00928 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size); 00929 }
| static void sky2_rx_map_iob | ( | struct pci_device *pdev | __unused, | |
| struct rx_ring_info * | re, | |||
| unsigned size | __unused | |||
| ) | [static] |
Definition at line 932 of file sky2.c.
References io_buffer::data, rx_ring_info::data_addr, rx_ring_info::iob, and virt_to_bus().
Referenced by receive_new(), and sky2_rx_start().
00935 { 00936 struct io_buffer *iob = re->iob; 00937 re->data_addr = virt_to_bus(iob->data); 00938 }
| static void rx_set_checksum | ( | struct sky2_port * | sky2 | ) | [static] |
Definition at line 942 of file sky2.c.
References sky2_rx_le::addr, BMU_DIS_RX_CHKSUM, cpu_to_le32, sky2_rx_le::ctrl, ETH_HLEN, sky2_port::hw, HW_OWNER, OP_TCPSTART, sky2_rx_le::opcode, sky2_port::port, Q_ADDR, Q_CSR, rxqaddr, sky2_next_rx(), and sky2_write32().
Referenced by sky2_rx_start().
00943 { 00944 struct sky2_rx_le *le = sky2_next_rx(sky2); 00945 00946 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); 00947 le->ctrl = 0; 00948 le->opcode = OP_TCPSTART | HW_OWNER; 00949 00950 sky2_write32(sky2->hw, 00951 Q_ADDR(rxqaddr[sky2->port], Q_CSR), 00952 BMU_DIS_RX_CHKSUM); 00953 }
| static void sky2_rx_stop | ( | struct sky2_port * | sky2 | ) | [static] |
Definition at line 965 of file sky2.c.
References BMU_FIFO_RST, BMU_RST_SET, DBG, sky2_port::hw, net_device::name, sky2_port::netdev, PFX, sky2_port::port, PREF_UNIT_CTRL, PREF_UNIT_RST_SET, Q_ADDR, Q_CSR, Q_RL, Q_RSL, RB_ADDR, RB_CTRL, RB_DIS_OP_MD, rxqaddr, sky2_read8(), sky2_write32(), sky2_write8(), wmb, and Y2_QADDR.
Referenced by sky2_down().
00966 { 00967 struct sky2_hw *hw = sky2->hw; 00968 unsigned rxq = rxqaddr[sky2->port]; 00969 int i; 00970 00971 /* disable the RAM Buffer receive queue */ 00972 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 00973 00974 for (i = 0; i < 0xffff; i++) 00975 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) 00976 == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) 00977 goto stopped; 00978 00979 DBG(PFX "%s: receiver stop failed\n", sky2->netdev->name); 00980 stopped: 00981 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 00982 00983 /* reset the Rx prefetch unit */ 00984 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); 00985 wmb(); 00986 }
| static void sky2_rx_clean | ( | struct sky2_port * | sky2 | ) | [static] |
Definition at line 989 of file sky2.c.
References free_iob(), rx_ring_info::iob, memset(), NULL, sky2_port::rx_le, RX_LE_BYTES, RX_PENDING, and sky2_port::rx_ring.
Referenced by sky2_down(), and sky2_rx_start().
00990 { 00991 unsigned i; 00992 00993 memset(sky2->rx_le, 0, RX_LE_BYTES); 00994 for (i = 0; i < RX_PENDING; i++) { 00995 struct rx_ring_info *re = sky2->rx_ring + i; 00996 00997 if (re->iob) { 00998 free_iob(re->iob); 00999 re->iob = NULL; 01000 } 01001 } 01002 }
Definition at line 1007 of file sky2.c.
References alloc_iob(), ETH_DATA_ALIGN, sky2_hw::flags, sky2_port::hw, iob_reserve, NULL, sky2_port::rx_data_size, and SKY2_HW_RAM_BUFFER.
Referenced by receive_new(), and sky2_rx_start().
01008 { 01009 struct io_buffer *iob; 01010 01011 iob = alloc_iob(sky2->rx_data_size + ETH_DATA_ALIGN); 01012 if (!iob) 01013 return NULL; 01014 01015 /* 01016 * Cards with a RAM buffer hang in the rx FIFO if the 01017 * receive buffer isn't aligned to (Linux module comments say 01018 * 64 bytes, Linux module code says 8 bytes). Since io_buffers 01019 * are always 2kb-aligned under gPXE, just leave it be 01020 * without ETH_DATA_ALIGN in those cases. 01021 * 01022 * XXX This causes unaligned access to the IP header, 01023 * which is undesirable, but it's less undesirable than the 01024 * card hanging. 01025 */ 01026 if (!(sky2->hw->flags & SKY2_HW_RAM_BUFFER)) { 01027 iob_reserve(iob, ETH_DATA_ALIGN); 01028 } 01029 01030 return iob; 01031 }
| static void sky2_rx_update | ( | struct sky2_port * | sky2, | |
| unsigned | rxq | |||
| ) | [inline, static] |
Definition at line 1033 of file sky2.c.
References sky2_port::hw, sky2_port::rx_put, and sky2_put_idx().
Referenced by sky2_rx_start(), and sky2_status_intr().
01034 { 01035 sky2_put_idx(sky2->hw, rxq, sky2->rx_put); 01036 }
| static int sky2_rx_start | ( | struct sky2_port * | sky2 | ) | [static] |
Definition at line 1044 of file sky2.c.
References BMU_WM_PEX, sky2_hw::chip_id, CHIP_ID_YUKON_EC_U, sky2_hw::chip_rev, CHIP_REV_YU_EC_U_A1, CHIP_REV_YU_EC_U_B0, ENOMEM, ETH_FRAME_LEN, F_M_RX_RAM_DIS, sky2_hw::flags, sky2_port::hw, rx_ring_info::iob, PCI_CAP_ID_EXP, pci_find_capability(), sky2_hw::pdev, sky2_port::port, Q_ADDR, Q_TEST, Q_WM, sky2_port::rx_data_size, RX_GMF_CTRL_T, RX_GMF_TR_THR, sky2_port::rx_le_map, RX_LE_SIZE, sky2_port::rx_next, RX_PENDING, sky2_port::rx_put, sky2_port::rx_ring, rx_set_checksum(), RX_TRUNC_OFF, RX_TRUNC_ON, rxqaddr, size, SK_REG, SKY2_HW_NEW_LE, sky2_prefetch_init(), sky2_qset(), sky2_rx_alloc(), sky2_rx_clean(), sky2_rx_map_iob(), sky2_rx_submit(), sky2_rx_update(), sky2_write16(), sky2_write32(), and u32.
Referenced by sky2_up().
01045 { 01046 struct sky2_hw *hw = sky2->hw; 01047 struct rx_ring_info *re; 01048 unsigned rxq = rxqaddr[sky2->port]; 01049 unsigned i, size, thresh; 01050 01051 sky2->rx_put = sky2->rx_next = 0; 01052 sky2_qset(hw, rxq); 01053 01054 /* On PCI express lowering the watermark gives better performance */ 01055 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) 01056 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX); 01057 01058 /* These chips have no ram buffer? 01059 * MAC Rx RAM Read is controlled by hardware */ 01060 if (hw->chip_id == CHIP_ID_YUKON_EC_U && 01061 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 01062 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) 01063 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS); 01064 01065 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); 01066 01067 if (!(hw->flags & SKY2_HW_NEW_LE)) 01068 rx_set_checksum(sky2); 01069 01070 /* Space needed for frame data + headers rounded up */ 01071 size = (ETH_FRAME_LEN + 8) & ~7; 01072 01073 /* Stopping point for hardware truncation */ 01074 thresh = (size - 8) / sizeof(u32); 01075 01076 sky2->rx_data_size = size; 01077 01078 /* Fill Rx ring */ 01079 for (i = 0; i < RX_PENDING; i++) { 01080 re = sky2->rx_ring + i; 01081 01082 re->iob = sky2_rx_alloc(sky2); 01083 if (!re->iob) 01084 goto nomem; 01085 01086 sky2_rx_map_iob(hw->pdev, re, sky2->rx_data_size); 01087 sky2_rx_submit(sky2, re); 01088 } 01089 01090 /* 01091 * The receiver hangs if it receives frames larger than the 01092 * packet buffer. As a workaround, truncate oversize frames, but 01093 * the register is limited to 9 bits, so if you do frames > 2052 01094 * you better get the MTU right! 01095 */ 01096 if (thresh > 0x1ff) 01097 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF); 01098 else { 01099 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh); 01100 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); 01101 } 01102 01103 /* Tell chip about available buffers */ 01104 sky2_rx_update(sky2, rxq); 01105 return 0; 01106 nomem: 01107 sky2_rx_clean(sky2); 01108 return -ENOMEM; 01109 }
| static void sky2_free_rings | ( | struct sky2_port * | sky2 | ) | [static] |
Definition at line 1112 of file sky2.c.
References free(), free_dma(), NULL, sky2_port::rx_le, RX_LE_BYTES, sky2_port::rx_ring, sky2_port::tx_le, sky2_port::tx_ring, and TX_RING_SIZE.
Referenced by sky2_down(), and sky2_up().
01113 { 01114 free_dma(sky2->rx_le, RX_LE_BYTES); 01115 free(sky2->rx_ring); 01116 01117 free_dma(sky2->tx_le, TX_RING_SIZE * sizeof(struct sky2_tx_le)); 01118 free(sky2->tx_ring); 01119 01120 sky2->tx_le = NULL; 01121 sky2->rx_le = NULL; 01122 01123 sky2->rx_ring = NULL; 01124 sky2->tx_ring = NULL; 01125 }
| static int sky2_up | ( | struct net_device * | dev | ) | [static] |
Definition at line 1128 of file sky2.c.
References B0_IMSK, B2_E_0, sky2_hw::chip_id, CHIP_ID_YUKON_EC_U, CHIP_ID_YUKON_EX, sky2_hw::chip_rev, CHIP_REV_YU_EC_U_A0, CHIP_REV_YU_EX_B0, DBG2, DBGIO, ECU_TXFF_LEV, ENOMEM, F_TX_CHK_AUTO_OFF, sky2_hw::flags, sky2_port::hw, malloc_dma(), memset(), net_device::name, netdev_link_down(), netdev_priv(), PFX, sky2_port::port, portirq_msk, Q_ADDR, Q_AL, Q_TEST, Q_XS1, Q_XS2, RB_ADDR, RB_CTRL, RB_RST_SET, sky2_port::rx_le, RX_LE_BYTES, sky2_port::rx_le_map, RX_PENDING, sky2_port::rx_ring, RX_RING_ALIGN, rxqaddr, sky2_free_rings(), SKY2_HW_RAM_BUFFER, sky2_mac_init(), sky2_prefetch_init(), sky2_qset(), sky2_ramset(), sky2_read32(), sky2_read8(), sky2_rx_start(), sky2_set_multicast(), sky2_write16(), sky2_write32(), sky2_write8(), sky2_hw::st_dma, sky2_hw::st_le, tx_init(), sky2_port::tx_le, sky2_port::tx_le_map, sky2_port::tx_ring, TX_RING_ALIGN, TX_RING_SIZE, txqaddr, u32, virt_to_bus(), and zalloc().
01129 { 01130 struct sky2_port *sky2 = netdev_priv(dev); 01131 struct sky2_hw *hw = sky2->hw; 01132 unsigned port = sky2->port; 01133 u32 imask, ramsize; 01134 int err = -ENOMEM; 01135 01136 netdev_link_down(dev); 01137 01138 /* must be power of 2 */ 01139 sky2->tx_le = malloc_dma(TX_RING_SIZE * sizeof(struct sky2_tx_le), TX_RING_ALIGN); 01140 sky2->tx_le_map = virt_to_bus(sky2->tx_le); 01141 if (!sky2->tx_le) 01142 goto err_out; 01143 memset(sky2->tx_le, 0, TX_RING_SIZE * sizeof(struct sky2_tx_le)); 01144 01145 sky2->tx_ring = zalloc(TX_RING_SIZE * sizeof(struct tx_ring_info)); 01146 if (!sky2->tx_ring) 01147 goto err_out; 01148 01149 tx_init(sky2); 01150 01151 sky2->rx_le = malloc_dma(RX_LE_BYTES, RX_RING_ALIGN); 01152 sky2->rx_le_map = virt_to_bus(sky2->rx_le); 01153 if (!sky2->rx_le) 01154 goto err_out; 01155 memset(sky2->rx_le, 0, RX_LE_BYTES); 01156 01157 sky2->rx_ring = zalloc(RX_PENDING * sizeof(struct rx_ring_info)); 01158 if (!sky2->rx_ring) 01159 goto err_out; 01160 01161 sky2_mac_init(hw, port); 01162 01163 /* Register is number of 4K blocks on internal RAM buffer. */ 01164 ramsize = sky2_read8(hw, B2_E_0) * 4; 01165 if (ramsize > 0) { 01166 u32 rxspace; 01167 01168 hw->flags |= SKY2_HW_RAM_BUFFER; 01169 DBG2(PFX "%s: ram buffer %dK\n", dev->name, ramsize); 01170 if (ramsize < 16) 01171 rxspace = ramsize / 2; 01172 else 01173 rxspace = 8 + (2*(ramsize - 16))/3; 01174 01175 sky2_ramset(hw, rxqaddr[port], 0, rxspace); 01176 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace); 01177 01178 /* Make sure SyncQ is disabled */ 01179 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), 01180 RB_RST_SET); 01181 } 01182 01183 sky2_qset(hw, txqaddr[port]); 01184 01185 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */ 01186 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0) 01187 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF); 01188 01189 /* Set almost empty threshold */ 01190 if (hw->chip_id == CHIP_ID_YUKON_EC_U 01191 && hw->chip_rev == CHIP_REV_YU_EC_U_A0) 01192 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV); 01193 01194 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, 01195 TX_RING_SIZE - 1); 01196 01197 err = sky2_rx_start(sky2); 01198 if (err) 01199 goto err_out; 01200 01201 /* Enable interrupts from phy/mac for port */ 01202 imask = sky2_read32(hw, B0_IMSK); 01203 imask |= portirq_msk[port]; 01204 sky2_write32(hw, B0_IMSK, imask); 01205 01206 DBGIO(PFX "%s: le bases: st %p [%x], rx %p [%x], tx %p [%x]\n", 01207 dev->name, hw->st_le, hw->st_dma, sky2->rx_le, sky2->rx_le_map, 01208 sky2->tx_le, sky2->tx_le_map); 01209 01210 sky2_set_multicast(dev); 01211 return 0; 01212 01213 err_out: 01214 sky2_free_rings(sky2); 01215 return err; 01216 }
| static int tx_dist | ( | unsigned | tail, | |
| unsigned | head | |||
| ) | [inline, static] |
Definition at line 1219 of file sky2.c.
References TX_RING_SIZE.
Referenced by tx_avail().
01220 { 01221 return (head - tail) & (TX_RING_SIZE - 1); 01222 }
| static int tx_avail | ( | const struct sky2_port * | sky2 | ) | [inline, static] |
Definition at line 1225 of file sky2.c.
References sky2_port::tx_cons, tx_dist(), TX_PENDING, and sky2_port::tx_prod.
Referenced by sky2_xmit_frame().
01226 { 01227 return TX_PENDING - tx_dist(sky2->tx_cons, sky2->tx_prod); 01228 }
| static int sky2_xmit_frame | ( | struct net_device * | dev, | |
| struct io_buffer * | iob | |||
| ) | [static] |
Definition at line 1237 of file sky2.c.
References sky2_tx_le::addr, cpu_to_le16, cpu_to_le32, sky2_tx_le::ctrl, io_buffer::data, DBGIO, EBUSY, EOP, get_tx_le(), sky2_port::hw, HW_OWNER, tx_ring_info::iob, iob_len(), sky2_tx_le::length, net_device::name, netdev_priv(), NULL, OP_PACKET, sky2_tx_le::opcode, PFX, sky2_port::port, sky2_put_idx(), tx_avail(), tx_le_re(), sky2_port::tx_prod, txqaddr, u32, u8, and virt_to_bus().
01238 { 01239 struct sky2_port *sky2 = netdev_priv(dev); 01240 struct sky2_hw *hw = sky2->hw; 01241 struct sky2_tx_le *le = NULL; 01242 struct tx_ring_info *re; 01243 unsigned len; 01244 u32 mapping; 01245 u8 ctrl; 01246 01247 if (tx_avail(sky2) < 1) 01248 return -EBUSY; 01249 01250 len = iob_len(iob); 01251 mapping = virt_to_bus(iob->data); 01252 01253 DBGIO(PFX "%s: tx queued, slot %d, len %d\n", dev->name, 01254 sky2->tx_prod, len); 01255 01256 ctrl = 0; 01257 01258 le = get_tx_le(sky2); 01259 le->addr = cpu_to_le32((u32) mapping); 01260 le->length = cpu_to_le16(len); 01261 le->ctrl = ctrl; 01262 le->opcode = (OP_PACKET | HW_OWNER); 01263 01264 re = tx_le_re(sky2, le); 01265 re->iob = iob; 01266 01267 le->ctrl |= EOP; 01268 01269 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); 01270 01271 return 0; 01272 }
Definition at line 1280 of file sky2.c.
References assert, sky2_tx_le::ctrl, DBGIO, net_device::dev, EOP, tx_ring_info::iob, mb(), net_device::name, sky2_port::netdev, netdev_tx_complete(), PFX, RING_NEXT, sky2_port::tx_cons, sky2_port::tx_le, sky2_port::tx_ring, and TX_RING_SIZE.
Referenced by sky2_tx_clean(), and sky2_tx_done().
01281 { 01282 struct net_device *dev = sky2->netdev; 01283 unsigned idx; 01284 01285 assert(done < TX_RING_SIZE); 01286 01287 for (idx = sky2->tx_cons; idx != done; 01288 idx = RING_NEXT(idx, TX_RING_SIZE)) { 01289 struct sky2_tx_le *le = sky2->tx_le + idx; 01290 struct tx_ring_info *re = sky2->tx_ring + idx; 01291 01292 if (le->ctrl & EOP) { 01293 DBGIO(PFX "%s: tx done %d\n", dev->name, idx); 01294 netdev_tx_complete(dev, re->iob); 01295 } 01296 } 01297 01298 sky2->tx_cons = idx; 01299 mb(); 01300 }
| static void sky2_tx_clean | ( | struct net_device * | dev | ) | [static] |
Definition at line 1303 of file sky2.c.
References netdev_priv(), sky2_tx_complete(), and sky2_port::tx_prod.
Referenced by sky2_down().
01304 { 01305 struct sky2_port *sky2 = netdev_priv(dev); 01306 01307 sky2_tx_complete(sky2, sky2->tx_prod); 01308 }
| static void sky2_down | ( | struct net_device * | dev | ) | [static] |
Definition at line 1311 of file sky2.c.
References B0_IMSK, B0_Y2LED, BMU_FIFO_RST, BMU_RST_SET, BMU_STOP, sky2_hw::chip_id, CHIP_ID_YUKON_XL, sky2_hw::chip_rev, DBG2, sky2_hw::dev, GM_GP_CTRL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gma_read16(), gma_write16(), GMAC_CTRL, GMC_RST_SET, GMF_RST_SET, GPC_RST_SET, GPHY_CTRL, sky2_port::hw, LED_STAT_OFF, net_device::name, netdev_priv(), PFX, sky2_port::port, portirq_msk, PREF_UNIT_CTRL, PREF_UNIT_RST_SET, Q_ADDR, Q_CSR, RB_ADDR, RB_CTRL, RB_DIS_OP_MD, RB_RST_SET, RX_GMF_CTRL_T, SK_REG, sky2_free_rings(), sky2_gmac_reset(), sky2_phy_power_down(), sky2_read32(), sky2_rx_clean(), sky2_rx_stop(), sky2_tx_clean(), sky2_write16(), sky2_write32(), sky2_write8(), TX_GMF_CTRL_T, sky2_port::tx_le, TXA_CTRL, TXA_DIS_ALLOC, TXA_DIS_FSYNC, TXA_ITI_INI, TXA_LIM_INI, TXA_STOP_RC, txqaddr, u16, u32, and Y2_QADDR.
01312 { 01313 struct sky2_port *sky2 = netdev_priv(dev); 01314 struct sky2_hw *hw = sky2->hw; 01315 unsigned port = sky2->port; 01316 u16 ctrl; 01317 u32 imask; 01318 01319 /* Never really got started! */ 01320 if (!sky2->tx_le) 01321 return; 01322 01323 DBG2(PFX "%s: disabling interface\n", dev->name); 01324 01325 /* Disable port IRQ */ 01326 imask = sky2_read32(hw, B0_IMSK); 01327 imask &= ~portirq_msk[port]; 01328 sky2_write32(hw, B0_IMSK, imask); 01329 01330 sky2_gmac_reset(hw, port); 01331 01332 /* Stop transmitter */ 01333 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); 01334 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); 01335 01336 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 01337 RB_RST_SET | RB_DIS_OP_MD); 01338 01339 ctrl = gma_read16(hw, port, GM_GP_CTRL); 01340 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); 01341 gma_write16(hw, port, GM_GP_CTRL, ctrl); 01342 01343 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 01344 01345 /* Workaround shared GMAC reset */ 01346 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 01347 && port == 0 && hw->dev[1])) 01348 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 01349 01350 /* Disable Force Sync bit and Enable Alloc bit */ 01351 sky2_write8(hw, SK_REG(port, TXA_CTRL), 01352 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 01353 01354 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 01355 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 01356 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 01357 01358 /* Reset the PCI FIFO of the async Tx queue */ 01359 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), 01360 BMU_RST_SET | BMU_FIFO_RST); 01361 01362 /* Reset the Tx prefetch units */ 01363 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), 01364 PREF_UNIT_RST_SET); 01365 01366 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 01367 01368 sky2_rx_stop(sky2); 01369 01370 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 01371 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 01372 01373 sky2_phy_power_down(hw, port); 01374 01375 /* turn off LED's */ 01376 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); 01377 01378 sky2_tx_clean(dev); 01379 sky2_rx_clean(sky2); 01380 01381 sky2_free_rings(sky2); 01382 01383 return; 01384 }
Definition at line 1386 of file sky2.c.
References sky2_hw::flags, PHY_M_PS_SPEED_100, PHY_M_PS_SPEED_1000, PHY_M_PS_SPEED_MSK, SKY2_HW_FIBRE_PHY, SKY2_HW_GIGABIT, SPEED_10, SPEED_100, and SPEED_1000.
Referenced by sky2_autoneg_done(), and sky2_phy_intr().
01387 { 01388 if (hw->flags & SKY2_HW_FIBRE_PHY) 01389 return SPEED_1000; 01390 01391 if (!(hw->flags & SKY2_HW_GIGABIT)) { 01392 if (aux & PHY_M_PS_SPEED_100) 01393 return SPEED_100; 01394 else 01395 return SPEED_10; 01396 } 01397 01398 switch (aux & PHY_M_PS_SPEED_MSK) { 01399 case PHY_M_PS_SPEED_1000: 01400 return SPEED_1000; 01401 case PHY_M_PS_SPEED_100: 01402 return SPEED_100; 01403 default: 01404 return SPEED_10; 01405 } 01406 }
| static void sky2_link_up | ( | struct sky2_port * | sky2 | ) | [static] |
Definition at line 1408 of file sky2.c.
References DBG, sky2_port::duplex, DUPLEX_FULL, FC_BOTH, FC_NONE, FC_RX, FC_TX, sky2_port::flow_status, GM_GP_CTRL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gm_phy_write(), gma_read16(), gma_write16(), sky2_port::hw, LINKLED_BLINK_OFF, LINKLED_LINKSYNC_OFF, LINKLED_ON, LNK_LED_REG, net_device::name, sky2_port::netdev, netdev_link_up(), PFX, PHY_M_DEF_MSK, PHY_MARV_INT_MASK, sky2_port::port, SK_REG, sky2_write8(), sky2_port::speed, and u16.
Referenced by sky2_phy_intr().
01409 { 01410 struct sky2_hw *hw = sky2->hw; 01411 unsigned port = sky2->port; 01412 u16 reg; 01413 static const char *fc_name[] = { 01414 [FC_NONE] = "none", 01415 [FC_TX] = "tx", 01416 [FC_RX] = "rx", 01417 [FC_BOTH] = "both", 01418 }; 01419 01420 /* enable Rx/Tx */ 01421 reg = gma_read16(hw, port, GM_GP_CTRL); 01422 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 01423 gma_write16(hw, port, GM_GP_CTRL, reg); 01424 01425 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); 01426 01427 netdev_link_up(sky2->netdev); 01428 01429 /* Turn on link LED */ 01430 sky2_write8(hw, SK_REG(port, LNK_LED_REG), 01431 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); 01432 01433 DBG(PFX "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", 01434 sky2->netdev->name, sky2->speed, 01435 sky2->duplex == DUPLEX_FULL ? "full" : "half", 01436 fc_name[sky2->flow_status]); 01437 }
| static void sky2_link_down | ( | struct sky2_port * | sky2 | ) | [static] |
Definition at line 1439 of file sky2.c.
References DBG, GM_GP_CTRL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gm_phy_write(), gma_read16(), gma_write16(), sky2_port::hw, LINKLED_OFF, LNK_LED_REG, net_device::name, sky2_port::netdev, netdev_link_down(), PFX, PHY_MARV_INT_MASK, sky2_port::port, SK_REG, sky2_phy_init(), sky2_write8(), and u16.
Referenced by sky2_phy_intr().
01440 { 01441 struct sky2_hw *hw = sky2->hw; 01442 unsigned port = sky2->port; 01443 u16 reg; 01444 01445 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); 01446 01447 reg = gma_read16(hw, port, GM_GP_CTRL); 01448 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 01449 gma_write16(hw, port, GM_GP_CTRL, reg); 01450 01451 netdev_link_down(sky2->netdev); 01452 01453 /* Turn on link LED */ 01454 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 01455 01456 DBG(PFX "%s: Link is down.\n", sky2->netdev->name); 01457 01458 sky2_phy_init(hw, port); 01459 }
Definition at line 1461 of file sky2.c.
References ADVERTISE_PAUSE_ASYM, ADVERTISE_PAUSE_CAP, sky2_hw::chip_id, CHIP_ID_YUKON_EC_U, CHIP_ID_YUKON_EX, DBG, sky2_port::duplex, DUPLEX_FULL, DUPLEX_HALF, FC_BOTH, FC_NONE, FC_RX, FC_TX, sky2_port::flow_status, gm_phy_read(), GMAC_CTRL, GMC_PAUSE_OFF, GMC_PAUSE_ON, sky2_port::hw, LPA_PAUSE_ASYM, LPA_PAUSE_CAP, net_device::name, sky2_port::netdev, PFX, PHY_M_AN_RF, PHY_M_PS_FULL_DUP, PHY_M_PS_SPDUP_RES, PHY_MARV_AUNE_ADV, PHY_MARV_AUNE_LP, sky2_port::port, SK_REG, sky2_phy_speed(), sky2_write8(), sky2_port::speed, SPEED_1000, and u16.
Referenced by sky2_phy_intr().
01462 { 01463 struct sky2_hw *hw = sky2->hw; 01464 unsigned port = sky2->port; 01465 u16 advert, lpa; 01466 01467 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 01468 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); 01469 if (lpa & PHY_M_AN_RF) { 01470 DBG(PFX "%s: remote fault\n", sky2->netdev->name); 01471 return -1; 01472 } 01473 01474 if (!(aux & PHY_M_PS_SPDUP_RES)) { 01475 DBG(PFX "%s: speed/duplex mismatch\n", sky2->netdev->name); 01476 return -1; 01477 } 01478 01479 sky2->speed = sky2_phy_speed(hw, aux); 01480 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 01481 01482 /* Since the pause result bits seem to in different positions on 01483 * different chips. look at registers. 01484 */ 01485 01486 sky2->flow_status = FC_NONE; 01487 if (advert & ADVERTISE_PAUSE_CAP) { 01488 if (lpa & LPA_PAUSE_CAP) 01489 sky2->flow_status = FC_BOTH; 01490 else if (advert & ADVERTISE_PAUSE_ASYM) 01491 sky2->flow_status = FC_RX; 01492 } else if (advert & ADVERTISE_PAUSE_ASYM) { 01493 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM)) 01494 sky2->flow_status = FC_TX; 01495 } 01496 01497 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 01498 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)) 01499 sky2->flow_status = FC_NONE; 01500 01501 if (sky2->flow_status & FC_TX) 01502 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 01503 else 01504 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 01505 01506 return 0; 01507 }
| static void sky2_phy_intr | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static] |
Definition at line 1510 of file sky2.c.
References sky2_port::autoneg, AUTONEG_ENABLE, DBGIO, sky2_hw::dev, net_device::dev, sky2_port::duplex, DUPLEX_FULL, DUPLEX_HALF, gm_phy_read(), net_device::name, sky2_port::netdev, netdev_priv(), PFX, PHY_M_IS_AN_COMPL, PHY_M_IS_DUP_CHANGE, PHY_M_IS_LSP_CHANGE, PHY_M_IS_LST_CHANGE, PHY_M_PS_FULL_DUP, PHY_M_PS_LINK_UP, PHY_MARV_INT_STAT, PHY_MARV_PHY_STAT, sky2_autoneg_done(), sky2_link_down(), sky2_link_up(), sky2_phy_speed(), sky2_port::speed, and u16.
Referenced by sky2_poll().
01511 { 01512 struct net_device *dev = hw->dev[port]; 01513 struct sky2_port *sky2 = netdev_priv(dev); 01514 u16 istatus, phystat; 01515 01516 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 01517 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 01518 01519 DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n", 01520 sky2->netdev->name, istatus, phystat); 01521 01522 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) { 01523 if (sky2_autoneg_done(sky2, phystat) == 0) 01524 sky2_link_up(sky2); 01525 return; 01526 } 01527 01528 if (istatus & PHY_M_IS_LSP_CHANGE) 01529 sky2->speed = sky2_phy_speed(hw, phystat); 01530 01531 if (istatus & PHY_M_IS_DUP_CHANGE) 01532 sky2->duplex = 01533 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 01534 01535 if (istatus & PHY_M_IS_LST_CHANGE) { 01536 if (phystat & PHY_M_PS_LINK_UP) 01537 sky2_link_up(sky2); 01538 else 01539 sky2_link_down(sky2); 01540 } 01541 }
| static struct io_buffer* receive_new | ( | struct sky2_port * | sky2, | |
| struct rx_ring_info * | re, | |||
| unsigned int | length | |||
| ) | [static, read] |
Definition at line 1544 of file sky2.c.
References sky2_port::hw, rx_ring_info::iob, iob_put, NULL, sky2_hw::pdev, sky2_port::rx_data_size, sky2_rx_alloc(), and sky2_rx_map_iob().
Referenced by sky2_receive().
01547 { 01548 struct io_buffer *iob, *niob; 01549 unsigned hdr_space = sky2->rx_data_size; 01550 01551 /* Don't be tricky about reusing pages (yet) */ 01552 niob = sky2_rx_alloc(sky2); 01553 if (!niob) 01554 return NULL; 01555 01556 iob = re->iob; 01557 01558 re->iob = niob; 01559 sky2_rx_map_iob(sky2->hw->pdev, re, hdr_space); 01560 01561 iob_put(iob, length); 01562 return iob; 01563 }
| static struct io_buffer* sky2_receive | ( | struct net_device * | dev, | |
| u16 | length, | |||
| u32 | status | |||
| ) | [static, read] |
Definition at line 1569 of file sky2.c.
References sky2_hw::chip_id, CHIP_ID_YUKON_FE_P, sky2_hw::chip_rev, CHIP_REV_YU_FE2_A0, DBG2, DBGIO, EBUSY, EINVAL, EIO, GMR_FS_ANY_ERR, GMR_FS_LEN, GMR_FS_RX_FF_OV, GMR_FS_RX_OK, sky2_port::hw, net_device::name, netdev_priv(), netdev_rx_err(), NULL, PFX, receive_new(), sky2_port::rx_next, RX_PENDING, sky2_port::rx_ring, sky2_rx_submit(), and u16.
Referenced by sky2_status_intr().
01571 { 01572 struct sky2_port *sky2 = netdev_priv(dev); 01573 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next; 01574 struct io_buffer *iob = NULL; 01575 u16 count = (status & GMR_FS_LEN) >> 16; 01576 01577 DBGIO(PFX "%s: rx slot %d status 0x%x len %d\n", 01578 dev->name, sky2->rx_next, status, length); 01579 01580 sky2->rx_next = (sky2->rx_next + 1) % RX_PENDING; 01581 01582 /* This chip has hardware problems that generates bogus status. 01583 * So do only marginal checking and expect higher level protocols 01584 * to handle crap frames. 01585 */ 01586 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P && 01587 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 && 01588 length == count) 01589 goto okay; 01590 01591 if (status & GMR_FS_ANY_ERR) 01592 goto error; 01593 01594 if (!(status & GMR_FS_RX_OK)) 01595 goto resubmit; 01596 01597 /* if length reported by DMA does not match PHY, packet was truncated */ 01598 if (length != count) 01599 goto len_error; 01600 01601 okay: 01602 iob = receive_new(sky2, re, length); 01603 resubmit: 01604 sky2_rx_submit(sky2, re); 01605 01606 return iob; 01607 01608 len_error: 01609 /* Truncation of overlength packets 01610 causes PHY length to not match MAC length */ 01611 DBG2(PFX "%s: rx length error: status %#x length %d\n", 01612 dev->name, status, length); 01613 01614 /* Pass NULL as iob because we want to keep our iob in the 01615 ring for the next packet. */ 01616 netdev_rx_err(dev, NULL, -EINVAL); 01617 goto resubmit; 01618 01619 error: 01620 if (status & GMR_FS_RX_FF_OV) { 01621 DBG2(PFX "%s: FIFO overflow error\n", dev->name); 01622 netdev_rx_err(dev, NULL, -EBUSY); 01623 goto resubmit; 01624 } 01625 01626 DBG2(PFX "%s: rx error, status 0x%x length %d\n", 01627 dev->name, status, length); 01628 netdev_rx_err(dev, NULL, -EIO); 01629 01630 goto resubmit; 01631 }
| static void sky2_tx_done | ( | struct net_device * | dev, | |
| u16 | last | |||
| ) | [inline, static] |
Definition at line 1634 of file sky2.c.
References netdev_priv(), and sky2_tx_complete().
Referenced by sky2_status_intr().
01635 { 01636 struct sky2_port *sky2 = netdev_priv(dev); 01637 01638 sky2_tx_complete(sky2, last); 01639 }
Definition at line 1642 of file sky2.c.
References assert, sky2_status_le::css, CSS_LINK_BIT, DBG, DBG2, sky2_hw::dev, net_device::dev, ENOMEM, HW_OWNER, le16_to_cpu, le32_to_cpu, sky2_status_le::length, netdev_priv(), netdev_rx(), netdev_rx_err(), NULL, OP_RXCHKS, OP_RXSTAT, OP_TXINDEXLE, sky2_status_le::opcode, PFX, Q_R1, Q_R2, RING_NEXT, rmb, SC_STAT_CLR_IRQ, sky2_receive(), sky2_rx_update(), sky2_tx_done(), sky2_write32(), sky2_hw::st_idx, sky2_hw::st_le, STAT_CTRL, sky2_status_le::status, STATUS_RING_SIZE, TX_RING_SIZE, u16, u32, and u8.
Referenced by sky2_poll().
01643 { 01644 unsigned rx[2] = { 0, 0 }; 01645 01646 rmb(); 01647 do { 01648 struct sky2_port *sky2; 01649 struct sky2_status_le *le = hw->st_le + hw->st_idx; 01650 unsigned port; 01651 struct net_device *dev; 01652 struct io_buffer *iob; 01653 u32 status; 01654 u16 length; 01655 u8 opcode = le->opcode; 01656 01657 if (!(opcode & HW_OWNER)) 01658 break; 01659 01660 port = le->css & CSS_LINK_BIT; 01661 dev = hw->dev[port]; 01662 sky2 = netdev_priv(dev); 01663 length = le16_to_cpu(le->length); 01664 status = le32_to_cpu(le->status); 01665 01666 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE); 01667 01668 le->opcode = 0; 01669 switch (opcode & ~HW_OWNER) { 01670 case OP_RXSTAT: 01671 ++rx[port]; 01672 iob = sky2_receive(dev, length, status); 01673 if (!iob) { 01674 netdev_rx_err(dev, NULL, -ENOMEM); 01675 break; 01676 } 01677 01678 netdev_rx(dev, iob); 01679 break; 01680 01681 case OP_RXCHKS: 01682 DBG2(PFX "status OP_RXCHKS but checksum offloading disabled\n"); 01683 break; 01684 01685 case OP_TXINDEXLE: 01686 /* TX index reports status for both ports */ 01687 assert(TX_RING_SIZE <= 0x1000); 01688 sky2_tx_done(hw->dev[0], status & 0xfff); 01689 if (hw->dev[1]) 01690 sky2_tx_done(hw->dev[1], 01691 ((status >> 24) & 0xff) 01692 | (u16)(length & 0xf) << 8); 01693 break; 01694 01695 default: 01696 DBG(PFX "unknown status opcode 0x%x\n", opcode); 01697 } 01698 } while (hw->st_idx != idx); 01699 01700 /* Fully processed status ring so clear irq */ 01701 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); 01702 01703 if (rx[0]) 01704 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1); 01705 01706 if (rx[1]) 01707 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2); 01708 }
Definition at line 1710 of file sky2.c.
References B3_RI_CTRL, BMU_CLR_IRQ_PAR, BMU_CLR_IRQ_TCP, DBG, DBGIO, sky2_hw::dev, net_device::dev, GMF_CLI_TX_PE, net_device::name, PFX, Q_ADDR, Q_CSR, RAM_BUFFER, RI_CLR_RD_PERR, RI_CLR_WR_PERR, rxqaddr, SK_REG, sky2_write16(), sky2_write32(), sky2_write8(), TX_GMF_CTRL_T, txqaddr, Y2_IS_PAR_MAC1, Y2_IS_PAR_RD1, Y2_IS_PAR_RX1, Y2_IS_PAR_WR1, and Y2_IS_TCP_TXA1.
Referenced by sky2_hw_intr().
01711 { 01712 struct net_device *dev = hw->dev[port]; 01713 01714 DBGIO(PFX "%s: hw error interrupt status 0x%x\n", dev->name, status); 01715 01716 if (status & Y2_IS_PAR_RD1) { 01717 DBG(PFX "%s: ram data read parity error\n", dev->name); 01718 /* Clear IRQ */ 01719 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); 01720 } 01721 01722 if (status & Y2_IS_PAR_WR1) { 01723 DBG(PFX "%s: ram data write parity error\n", dev->name); 01724 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); 01725 } 01726 01727 if (status & Y2_IS_PAR_MAC1) { 01728 DBG(PFX "%s: MAC parity error\n", dev->name); 01729 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); 01730 } 01731 01732 if (status & Y2_IS_PAR_RX1) { 01733 DBG(PFX "%s: RX parity error\n", dev->name); 01734 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); 01735 } 01736 01737 if (status & Y2_IS_TCP_TXA1) { 01738 DBG(PFX "%s: TCP segmentation error\n", dev->name); 01739 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); 01740 } 01741 }
| static void sky2_hw_intr | ( | struct sky2_hw * | hw | ) | [static] |
Definition at line 1743 of file sky2.c.
References B0_HWE_IMSK, B0_HWE_ISRC, B2_TST_CTRL1, DBG, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ, PCI_ERR_UNCOR_STATUS, PCI_STATUS, PCI_STATUS_ERROR_BITS, PFX, sky2_hw_error(), sky2_pci_read16(), sky2_pci_write16(), sky2_read32(), sky2_write32(), sky2_write8(), TST_CFG_WRITE_OFF, TST_CFG_WRITE_ON, u16, u32, Y2_CFG_AER, Y2_HWE_L1_MASK, Y2_IS_IRQ_STAT, Y2_IS_MST_ERR, Y2_IS_PCI_EXP, and Y2_IS_TIST_OV.
Referenced by sky2_err_intr().
01744 { 01745 u32 status = sky2_read32(hw, B0_HWE_ISRC); 01746 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); 01747 01748 status &= hwmsk; 01749 01750 if (status & Y2_IS_TIST_OV) 01751 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 01752 01753 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { 01754 u16 pci_err; 01755 01756 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 01757 pci_err = sky2_pci_read16(hw, PCI_STATUS); 01758 DBG(PFX "PCI hardware error (0x%x)\n", pci_err); 01759 01760 sky2_pci_write16(hw, PCI_STATUS, 01761 pci_err | PCI_STATUS_ERROR_BITS); 01762 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 01763 } 01764 01765 if (status & Y2_IS_PCI_EXP) { 01766 /* PCI-Express uncorrectable Error occurred */ 01767 u32 err; 01768 01769 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 01770 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 01771 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 01772 0xfffffffful); 01773 DBG(PFX "PCI-Express error (0x%x)\n", err); 01774 01775 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS); 01776 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 01777 } 01778 01779 if (status & Y2_HWE_L1_MASK) 01780 sky2_hw_error(hw, 0, status); 01781 status >>= 8; 01782 if (status & Y2_HWE_L1_MASK) 01783 sky2_hw_error(hw, 1, status); 01784 }
| static void sky2_mac_intr | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static] |
Definition at line 1786 of file sky2.c.
References DBGIO, sky2_hw::dev, net_device::dev, GM_IS_RX_CO_OV, GM_IS_RX_FF_OR, GM_IS_TX_CO_OV, GM_IS_TX_FF_UR, GM_RX_IRQ_SRC, GM_TX_IRQ_SRC, gma_read16(), GMAC_IRQ_SRC, GMF_CLI_RX_FO, GMF_CLI_TX_FU, net_device::name, PFX, RX_GMF_CTRL_T, SK_REG, sky2_read8(), sky2_write8(), TX_GMF_CTRL_T, and u8.
Referenced by sky2_err_intr().
01787 { 01788 struct net_device *dev = hw->dev[port]; 01789 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); 01790 01791 DBGIO(PFX "%s: mac interrupt status 0x%x\n", dev->name, status); 01792 01793 if (status & GM_IS_RX_CO_OV) 01794 gma_read16(hw, port, GM_RX_IRQ_SRC); 01795 01796 if (status & GM_IS_TX_CO_OV) 01797 gma_read16(hw, port, GM_TX_IRQ_SRC); 01798 01799 if (status & GM_IS_RX_FF_OR) { 01800 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 01801 } 01802 01803 if (status & GM_IS_TX_FF_UR) { 01804 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 01805 } 01806 }
| static void sky2_le_error | ( | struct sky2_hw * | hw, | |
| unsigned | port, | |||
| u16 | q, | |||
| unsigned ring_size | __unused | |||
| ) | [static] |
Definition at line 1809 of file sky2.c.
References BMU_CLR_IRQ_CHK, DBG, sky2_hw::dev, net_device::dev, net_device::name, netdev_priv(), PFX, PREF_UNIT_GET_IDX, PREF_UNIT_LAST_IDX, PREF_UNIT_PUT_IDX, Q_ADDR, Q_CSR, Q_R1, Q_R2, sky2_port::rx_le, sky2_port::rx_put, sky2_read16(), sky2_write32(), sky2_port::tx_le, sky2_port::tx_prod, and Y2_QADDR.
Referenced by sky2_err_intr().
01811 { 01812 struct net_device *dev = hw->dev[port]; 01813 struct sky2_port *sky2 = netdev_priv(dev); 01814 int idx; 01815 const u64 *le = (q == Q_R1 || q == Q_R2) 01816 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le; 01817 01818 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); 01819 DBG(PFX "%s: descriptor error q=%#x get=%d [%llx] last=%d put=%d should be %d\n", 01820 dev->name, (unsigned) q, idx, (unsigned long long) le[idx], 01821 (int) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_LAST_IDX)), 01822 (int) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)), 01823 le == (u64 *)sky2->rx_le? sky2->rx_put : sky2->tx_prod); 01824 01825 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK); 01826 }
Definition at line 1829 of file sky2.c.
References DBG, PFX, Q_R1, Q_R2, Q_XA1, Q_XA2, RX_LE_SIZE, sky2_hw_intr(), sky2_le_error(), sky2_mac_intr(), TX_RING_SIZE, Y2_IS_CHK_RX1, Y2_IS_CHK_RX2, Y2_IS_CHK_TXA1, Y2_IS_CHK_TXA2, Y2_IS_HW_ERR, Y2_IS_IRQ_MAC1, and Y2_IS_IRQ_MAC2.
Referenced by sky2_poll().
01830 { 01831 DBG(PFX "error interrupt status=%#x\n", status); 01832 01833 if (status & Y2_IS_HW_ERR) 01834 sky2_hw_intr(hw); 01835 01836 if (status & Y2_IS_IRQ_MAC1) 01837 sky2_mac_intr(hw, 0); 01838 01839 if (status & Y2_IS_IRQ_MAC2) 01840 sky2_mac_intr(hw, 1); 01841 01842 if (status & Y2_IS_CHK_RX1) 01843 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE); 01844 01845 if (status & Y2_IS_CHK_RX2) 01846 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE); 01847 01848 if (status & Y2_IS_CHK_TXA1) 01849 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE); 01850 01851 if (status & Y2_IS_CHK_TXA2) 01852 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE); 01853 }
| static void sky2_poll | ( | struct net_device * | dev | ) | [static] |
Definition at line 1855 of file sky2.c.
References B0_Y2_SP_EISR, B0_Y2_SP_LISR, sky2_port::hw, netdev_priv(), sky2_err_intr(), sky2_phy_intr(), sky2_read16(), sky2_read32(), sky2_read8(), sky2_status_intr(), sky2_write8(), sky2_hw::st_idx, STAT_PUT_IDX, STAT_TX_TIMER_CTRL, TIM_START, TIM_STOP, u16, u32, Y2_IS_ERROR, Y2_IS_IRQ_PHY1, and Y2_IS_IRQ_PHY2.
01856 { 01857 struct sky2_port *sky2 = netdev_priv(dev); 01858 struct sky2_hw *hw = sky2->hw; 01859 u32 status = sky2_read32(hw, B0_Y2_SP_EISR); 01860 u16 idx; 01861 01862 if (status & Y2_IS_ERROR) 01863 sky2_err_intr(hw, status); 01864 01865 if (status & Y2_IS_IRQ_PHY1) 01866 sky2_phy_intr(hw, 0); 01867 01868 if (status & Y2_IS_IRQ_PHY2) 01869 sky2_phy_intr(hw, 1); 01870 01871 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) { 01872 sky2_status_intr(hw, idx); 01873 } 01874 01875 /* Bug/Errata workaround? 01876 * Need to kick the TX irq moderation timer. 01877 */ 01878 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) { 01879 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); 01880 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 01881 } 01882 sky2_read32(hw, B0_Y2_SP_LISR); 01883 }
Definition at line 1886 of file sky2.c.
References sky2_hw::chip_id, CHIP_ID_YUKON_EC, CHIP_ID_YUKON_EC_U, CHIP_ID_YUKON_EX, CHIP_ID_YUKON_FE, CHIP_ID_YUKON_FE_P, CHIP_ID_YUKON_SUPR, CHIP_ID_YUKON_UL_2, CHIP_ID_YUKON_XL, DBG, and PFX.
Referenced by sky2_clk2us(), and sky2_us2clk().
01887 { 01888 switch (hw->chip_id) { 01889 case CHIP_ID_YUKON_EC: 01890 case CHIP_ID_YUKON_EC_U: 01891 case CHIP_ID_YUKON_EX: 01892 case CHIP_ID_YUKON_SUPR: 01893 case CHIP_ID_YUKON_UL_2: 01894 return 125; 01895 01896 case CHIP_ID_YUKON_FE: 01897 return 100; 01898 01899 case CHIP_ID_YUKON_FE_P: 01900 return 50; 01901 01902 case CHIP_ID_YUKON_XL: 01903 return 156; 01904 01905 default: 01906 DBG(PFX "unknown chip ID!\n"); 01907 return 100; /* bogus */ 01908 } 01909 }
Definition at line 1911 of file sky2.c.
References sky2_mhz().
Referenced by sky2_reset().
01912 { 01913 return sky2_mhz(hw) * us; 01914 }
Definition at line 1916 of file sky2.c.
References sky2_mhz().
01917 { 01918 return clk / sky2_mhz(hw); 01919 }
| static int sky2_init | ( | struct sky2_hw * | hw | ) | [static] |
Definition at line 1921 of file sky2.c.
References B0_CTST, B2_CHIP_ID, B2_MAC_CFG, B2_PMD_TYP, B2_Y2_CLK_GATE, B2_Y2_HW_RES, CFG_CHIP_R_MSK, CFG_DUAL_MAC_MSK, sky2_hw::chip_id, CHIP_ID_YUKON_EC, CHIP_ID_YUKON_EC_U, CHIP_ID_YUKON_EX, CHIP_ID_YUKON_FE, CHIP_ID_YUKON_FE_P, CHIP_ID_YUKON_SUPR, CHIP_ID_YUKON_UL_2, CHIP_ID_YUKON_XL, sky2_hw::chip_rev, CHIP_REV_YU_EC_A1, CS_RST_CLR, DBG, EOPNOTSUPP, sky2_hw::flags, PCI_DEV_REG3, PFX, sky2_hw::pmd_type, sky2_hw::ports, SKY2_HW_ADV_POWER_CTL, SKY2_HW_AUTO_TX_SUM, SKY2_HW_FIBRE_PHY, SKY2_HW_GIGABIT, SKY2_HW_NEW_LE, SKY2_HW_NEWER_PHY, sky2_pci_write32(), sky2_read8(), sky2_write8(), u8, and Y2_STATUS_LNK2_INAC.
Referenced by sky2_probe().
01922 { 01923 u8 t8; 01924 01925 /* Enable all clocks and check for bad PCI access */ 01926 sky2_pci_write32(hw, PCI_DEV_REG3, 0); 01927 01928 sky2_write8(hw, B0_CTST, CS_RST_CLR); 01929 01930 hw->chip_id = sky2_read8(hw, B2_CHIP_ID); 01931 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; 01932 01933 switch(hw->chip_id) { 01934 case CHIP_ID_YUKON_XL: 01935 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY; 01936 break; 01937 01938 case CHIP_ID_YUKON_EC_U: 01939 hw->flags = SKY2_HW_GIGABIT 01940 | SKY2_HW_NEWER_PHY 01941 | SKY2_HW_ADV_POWER_CTL; 01942 break; 01943 01944 case CHIP_ID_YUKON_EX: 01945 hw->flags = SKY2_HW_GIGABIT 01946 | SKY2_HW_NEWER_PHY 01947 | SKY2_HW_NEW_LE 01948 | SKY2_HW_ADV_POWER_CTL; 01949 break; 01950 01951 case CHIP_ID_YUKON_EC: 01952 /* This rev is really old, and requires untested workarounds */ 01953 if (hw->chip_rev == CHIP_REV_YU_EC_A1) { 01954 DBG(PFX "unsupported revision Yukon-EC rev A1\n"); 01955 return -EOPNOTSUPP; 01956 } 01957 hw->flags = SKY2_HW_GIGABIT; 01958 break; 01959 01960 case CHIP_ID_YUKON_FE: 01961 break; 01962 01963 case CHIP_ID_YUKON_FE_P: 01964 hw->flags = SKY2_HW_NEWER_PHY 01965 | SKY2_HW_NEW_LE 01966 | SKY2_HW_AUTO_TX_SUM 01967 | SKY2_HW_ADV_POWER_CTL; 01968 break; 01969 01970 case CHIP_ID_YUKON_SUPR: 01971 hw->flags = SKY2_HW_GIGABIT 01972 | SKY2_HW_NEWER_PHY 01973 | SKY2_HW_NEW_LE 01974 | SKY2_HW_AUTO_TX_SUM 01975 | SKY2_HW_ADV_POWER_CTL; 01976 break; 01977 01978 case CHIP_ID_YUKON_UL_2: 01979 hw->flags = SKY2_HW_GIGABIT 01980 | SKY2_HW_ADV_POWER_CTL; 01981 break; 01982 01983 default: 01984 DBG(PFX "unsupported chip type 0x%x\n", hw->chip_id); 01985 return -EOPNOTSUPP; 01986 } 01987 01988 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); 01989 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P') 01990 hw->flags |= SKY2_HW_FIBRE_PHY; 01991 01992 hw->ports = 1; 01993 t8 = sky2_read8(hw, B2_Y2_HW_RES); 01994 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { 01995 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 01996 ++hw->ports; 01997 } 01998 01999 return 0; 02000 }
| static void sky2_reset | ( | struct sky2_hw * | hw | ) | [static] |
Definition at line 2002 of file sky2.c.
References B0_CTST, B0_HWE_IMSK, B0_HWE_ISRC, B0_Y2LED, B28_DPT_CTRL, B28_Y2_ASF_STAT_CMD, B2_I2C_IRQ, B2_TI_CTRL, B2_TST_CTRL1, B3_RI_CTRL, B3_RI_RTO_R1, B3_RI_RTO_R2, B3_RI_RTO_XA1, B3_RI_RTO_XA2, B3_RI_RTO_XS1, B3_RI_RTO_XS2, B3_RI_WTO_R1, B3_RI_WTO_R2, B3_RI_WTO_XA1, B3_RI_WTO_XA2, B3_RI_WTO_XS1, B3_RI_WTO_XS2, sky2_hw::chip_id, CHIP_ID_YUKON_EX, CHIP_ID_YUKON_SUPR, CHIP_ID_YUKON_XL, sky2_hw::chip_rev, CS_MRST_CLR, CS_RST_CLR, CS_RST_SET, DBG, DPT_STOP, GMAC_CTRL, GMAC_LINK_CTRL, GMAC_TI_ST_CTRL, GMC_BYP_MACSECRX_ON, GMC_BYP_MACSECTX_ON, GMC_BYP_RETR_ON, GMLC_RST_CLR, GMLC_RST_SET, GMT_ST_CLR_IRQ, GMT_ST_STOP, HCU_CCSR, HCU_CCSR_AHB_RST, HCU_CCSR_CPU_RST_MODE, HCU_CCSR_UC_STATE_MSK, LED_STAT_ON, memset(), PCI_CAP_ID_EXP, PCI_ERR_UNCOR_STATUS, pci_find_capability(), PCI_STATUS, PCI_STATUS_ERROR_BITS, sky2_hw::pdev, PFX, sky2_hw::ports, RAM_BUFFER, RI_RST_CLR, SC_STAT_OP_ON, SC_STAT_RST_CLR, SC_STAT_RST_SET, SK_REG, SK_RI_TO_53, sky2_gmac_reset(), sky2_pci_read16(), sky2_pci_write16(), sky2_power_on(), sky2_read16(), sky2_read32(), sky2_us2clk(), sky2_write16(), sky2_write32(), sky2_write8(), sky2_hw::st_dma, sky2_hw::st_idx, sky2_hw::st_le, STAT_CTRL, STAT_FIFO_ISR_WM, STAT_FIFO_WM, STAT_ISR_TIMER_CTRL, STAT_ISR_TIMER_INI, STAT_LAST_IDX, STAT_LEV_TIMER_CTRL, STAT_LEV_TIMER_INI, STAT_LIST_ADDR_HI, STAT_LIST_ADDR_LO, STAT_TX_IDX_TH, STAT_TX_TIMER_CTRL, STAT_TX_TIMER_INI, STATUS_LE_BYTES, STATUS_RING_SIZE, TIM_CLR_IRQ, TIM_START, TIM_STOP, TST_CFG_WRITE_OFF, TST_CFG_WRITE_ON, TXA_CTRL, TXA_ENA_ARB, u16, u32, Y2_ASF_DISABLE, Y2_ASF_RESET, Y2_CFG_AER, Y2_HWE_ALL_MASK, and Y2_IS_PCI_EXP.
Referenced by sky2_probe().
02003 { 02004 u16 status; 02005 int i, cap; 02006 u32 hwe_mask = Y2_HWE_ALL_MASK; 02007 02008 /* disable ASF */ 02009 if (hw->chip_id == CHIP_ID_YUKON_EX) { 02010 status = sky2_read16(hw, HCU_CCSR); 02011 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE | 02012 HCU_CCSR_UC_STATE_MSK); 02013 sky2_write16(hw, HCU_CCSR, status); 02014 } else 02015 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 02016 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); 02017 02018 /* do a SW reset */ 02019 sky2_write8(hw, B0_CTST, CS_RST_SET); 02020 sky2_write8(hw, B0_CTST, CS_RST_CLR); 02021 02022 /* allow writes to PCI config */ 02023 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 02024 02025 /* clear PCI errors, if any */ 02026 status = sky2_pci_read16(hw, PCI_STATUS); 02027 status |= PCI_STATUS_ERROR_BITS; 02028 sky2_pci_write16(hw, PCI_STATUS, status); 02029 02030 sky2_write8(hw, B0_CTST, CS_MRST_CLR); 02031 02032 cap = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP); 02033 if (cap) { 02034 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS, 02035 0xfffffffful); 02036 02037 /* If an error bit is stuck on ignore it */ 02038 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP) 02039 DBG(PFX "ignoring stuck error report bit\n"); 02040 else 02041 hwe_mask |= Y2_IS_PCI_EXP; 02042 } 02043 02044 sky2_power_on(hw); 02045 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 02046 02047 for (i = 0; i < hw->ports; i++) { 02048 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 02049 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 02050 02051 if (hw->chip_id == CHIP_ID_YUKON_EX || 02052 hw->chip_id == CHIP_ID_YUKON_SUPR) 02053 sky2_write16(hw, SK_REG(i, GMAC_CTRL), 02054 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON 02055 | GMC_BYP_RETR_ON); 02056 } 02057 02058 /* Clear I2C IRQ noise */ 02059 sky2_write32(hw, B2_I2C_IRQ, 1); 02060 02061 /* turn off hardware timer (unused) */ 02062 sky2_write8(hw, B2_TI_CTRL, TIM_STOP); 02063 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 02064 02065 sky2_write8(hw, B0_Y2LED, LED_STAT_ON); 02066 02067 /* Turn off descriptor polling */ 02068 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); 02069 02070 /* Turn off receive timestamp */ 02071 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); 02072 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 02073 02074 /* enable the Tx Arbiters */ 02075 for (i = 0; i < hw->ports; i++) 02076 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 02077 02078 /* Initialize ram interface */ 02079 for (i = 0; i < hw->ports; i++) { 02080 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 02081 02082 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); 02083 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); 02084 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); 02085 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); 02086 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); 02087 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); 02088 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); 02089 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); 02090 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); 02091 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); 02092 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); 02093 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); 02094 } 02095 02096 sky2_write32(hw, B0_HWE_IMSK, hwe_mask); 02097 02098 for (i = 0; i < hw->ports; i++) 02099 sky2_gmac_reset(hw, i); 02100 02101 memset(hw->st_le, 0, STATUS_LE_BYTES); 02102 hw->st_idx = 0; 02103 02104 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); 02105 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); 02106 02107 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); 02108 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); 02109 02110 /* Set the list last index */ 02111 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); 02112 02113 sky2_write16(hw, STAT_TX_IDX_TH, 10); 02114 sky2_write8(hw, STAT_FIFO_WM, 16); 02115 02116 /* set Status-FIFO ISR watermark */ 02117 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) 02118 sky2_write8(hw, STAT_FIFO_ISR_WM, 4); 02119 else 02120 sky2_write8(hw, STAT_FIFO_ISR_WM, 16); 02121 02122 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); 02123 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); 02124 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); 02125 02126 /* enable status unit */ 02127 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); 02128 02129 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); 02130 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); 02131 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); 02132 }
Definition at line 2134 of file sky2.c.
References sky2_hw::flags, SKY2_HW_GIGABIT, sky2_is_copper(), SUPPORTED_1000baseT_Full, SUPPORTED_1000baseT_Half, SUPPORTED_100baseT_Full, SUPPORTED_100baseT_Half, SUPPORTED_10baseT_Full, SUPPORTED_10baseT_Half, SUPPORTED_Autoneg, SUPPORTED_FIBRE, SUPPORTED_TP, and u32.
Referenced by sky2_init_netdev().
02135 { 02136 if (sky2_is_copper(hw)) { 02137 u32 modes = SUPPORTED_10baseT_Half 02138 | SUPPORTED_10baseT_Full 02139 | SUPPORTED_100baseT_Half 02140 | SUPPORTED_100baseT_Full 02141 | SUPPORTED_Autoneg | SUPPORTED_TP; 02142 02143 if (hw->flags & SKY2_HW_GIGABIT) 02144 modes |= SUPPORTED_1000baseT_Half 02145 | SUPPORTED_1000baseT_Full; 02146 return modes; 02147 } else 02148 return SUPPORTED_1000baseT_Half 02149 | SUPPORTED_1000baseT_Full 02150 | SUPPORTED_Autoneg 02151 | SUPPORTED_FIBRE; 02152 }
| static struct net_device* sky2_init_netdev | ( | struct sky2_hw * | hw, | |
| unsigned | port | |||
| ) | [static, read] |
Definition at line 2183 of file sky2.c.
References sky2_port::advertising, alloc_etherdev(), sky2_port::autoneg, AUTONEG_ENABLE, B2_MAC_1, DBG, sky2_hw::dev, pci_device::dev, net_device::dev, sky2_port::duplex, ETH_ALEN, FC_BOTH, sky2_port::flow_mode, sky2_port::hw, net_device::hw_addr, memcpy, sky2_port::netdev, netdev_priv(), NULL, sky2_hw::pdev, PFX, sky2_port::port, sky2_hw::regs, sky2_supported_modes(), and sky2_port::speed.
Referenced by sky2_probe().
02185 { 02186 struct sky2_port *sky2; 02187 struct net_device *dev = alloc_etherdev(sizeof(*sky2)); 02188 02189 if (!dev) { 02190 DBG(PFX "etherdev alloc failed\n"); 02191 return NULL; 02192 } 02193 02194 dev->dev = &hw->pdev->dev; 02195 02196 sky2 = netdev_priv(dev); 02197 sky2->netdev = dev; 02198 sky2->hw = hw; 02199 02200 /* Auto speed and flow control */ 02201 sky2->autoneg = AUTONEG_ENABLE; 02202 sky2->flow_mode = FC_BOTH; 02203 02204 sky2->duplex = -1; 02205 sky2->speed = -1; 02206 sky2->advertising = sky2_supported_modes(hw); 02207 02208 hw->dev[port] = dev; 02209 02210 sky2->port = port; 02211 02212 /* read the mac address */ 02213 memcpy(dev->hw_addr, (void *)(hw->regs + B2_MAC_1 + port * 8), ETH_ALEN); 02214 02215 return dev; 02216 }
| static void sky2_show_addr | ( | struct net_device * | dev | ) | [static] |
Definition at line 2218 of file sky2.c.
References DBG2, net_device::name, netdev_addr(), and PFX.
Referenced by sky2_probe().
02219 { 02220 DBG2(PFX "%s: addr %s\n", dev->name, netdev_addr(dev)); 02221 }
| static void sky2_net_irq | ( | struct net_device * | dev, | |
| int | enable | |||
| ) | [static] |
Definition at line 2246 of file sky2.c.
References B0_IMSK, sky2_port::hw, netdev_priv(), sky2_port::port, portirq_msk, sky2_read32(), sky2_write32(), and u32.
02247 { 02248 struct sky2_port *sky2 = netdev_priv(dev); 02249 struct sky2_hw *hw = sky2->hw; 02250 02251 u32 imask = sky2_read32(hw, B0_IMSK); 02252 if (enable) 02253 imask |= portirq_msk[sky2->port]; 02254 else 02255 imask &= ~portirq_msk[sky2->port]; 02256 sky2_write32(hw, B0_IMSK, imask); 02257 }
| static int sky2_probe | ( | struct pci_device * | pdev, | |
| const struct pci_device_id *ent | __unused | |||
| ) | [static] |
Definition at line 2267 of file sky2.c.
References adjust_pci_device(), B0_CTST, B0_IMSK, sky2_hw::chip_id, sky2_hw::chip_rev, CS_RST_SET, DBG, DBG2, sky2_hw::dev, net_device::dev, ENOMEM, free(), free_dma(), ioremap(), iounmap(), malloc_dma(), memset(), netdev_init(), netdev_nullify(), netdev_put(), NULL, pci_bar_start(), PCI_BASE_ADDRESS_0, pci_set_drvdata(), sky2_hw::pdev, PFX, sky2_hw::ports, register_netdev(), sky2_hw::regs, sky2_init(), sky2_init_netdev(), sky2_reset(), sky2_show_addr(), sky2_write32(), sky2_write8(), sky2_hw::st_dma, sky2_hw::st_le, STATUS_LE_BYTES, STATUS_RING_ALIGN, virt_to_bus(), Y2_IS_BASE, and zalloc().
02269 { 02270 struct net_device *dev; 02271 struct sky2_hw *hw; 02272 int err; 02273 char buf1[16] __unused; /* only for debugging */ 02274 02275 adjust_pci_device(pdev); 02276 02277 err = -ENOMEM; 02278 hw = zalloc(sizeof(*hw)); 02279 if (!hw) { 02280 DBG(PFX "cannot allocate hardware struct\n"); 02281 goto err_out; 02282 } 02283 02284 hw->pdev = pdev; 02285 02286 hw->regs = (unsigned long)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0), 0x4000); 02287 if (!hw->regs) { 02288 DBG(PFX "cannot map device registers\n"); 02289 goto err_out_free_hw; 02290 } 02291 02292 /* ring for status responses */ 02293 hw->st_le = malloc_dma(STATUS_LE_BYTES, STATUS_RING_ALIGN); 02294 if (!hw->st_le) 02295 goto err_out_iounmap; 02296 hw->st_dma = virt_to_bus(hw->st_le); 02297 memset(hw->st_le, 0, STATUS_LE_BYTES); 02298 02299 err = sky2_init(hw); 02300 if (err) 02301 goto err_out_iounmap; 02302 02303 #if DBGLVL_MAX 02304 DBG2(PFX "Yukon-2 %s chip revision %d\n", 02305 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev); 02306 #endif 02307 02308 sky2_reset(hw); 02309 02310 dev = sky2_init_netdev(hw, 0); 02311 if (!dev) { 02312 err = -ENOMEM; 02313 goto err_out_free_pci; 02314 } 02315 02316 netdev_init(dev, &sky2_operations); 02317 02318 err = register_netdev(dev); 02319 if (err) { 02320 DBG(PFX "cannot register net device\n"); 02321 goto err_out_free_netdev; 02322 } 02323 02324 sky2_write32(hw, B0_IMSK, Y2_IS_BASE); 02325 02326 sky2_show_addr(dev); 02327 02328 if (hw->ports > 1) { 02329 struct net_device *dev1; 02330 02331 dev1 = sky2_init_netdev(hw, 1); 02332 if (!dev1) 02333 DBG(PFX "allocation for second device failed\n"); 02334 else if ((err = register_netdev(dev1))) { 02335 DBG(PFX "register of second port failed (%d)\n", err); 02336 hw->dev[1] = NULL; 02337 netdev_nullify(dev1); 02338 netdev_put(dev1); 02339 } else 02340 sky2_show_addr(dev1); 02341 } 02342 02343 pci_set_drvdata(pdev, dev); 02344 02345 return 0; 02346 02347 err_out_free_netdev: 02348 netdev_nullify(dev); 02349 netdev_put(dev); 02350 err_out_free_pci: 02351 sky2_write8(hw, B0_CTST, CS_RST_SET); 02352 free_dma(hw->st_le, STATUS_LE_BYTES); 02353 err_out_iounmap: 02354 iounmap((void *)hw->regs); 02355 err_out_free_hw: 02356 free(hw); 02357 err_out: 02358 pci_set_drvdata(pdev, NULL); 02359 return err; 02360 }
| static void sky2_remove | ( | struct pci_device * | pdev | ) | [static] |
Definition at line 2362 of file sky2.c.
References B0_CTST, B0_IMSK, B0_Y2LED, CS_RST_SET, sky2_hw::dev, free(), free_dma(), iounmap(), LED_STAT_OFF, netdev_nullify(), netdev_put(), NULL, pci_get_drvdata(), pci_set_drvdata(), sky2_hw::ports, sky2_hw::regs, sky2_power_aux(), sky2_read8(), sky2_write16(), sky2_write32(), sky2_write8(), sky2_hw::st_le, STATUS_LE_BYTES, and unregister_netdev().
02363 { 02364 struct sky2_hw *hw = pci_get_drvdata(pdev); 02365 int i; 02366 02367 if (!hw) 02368 return; 02369 02370 for (i = hw->ports-1; i >= 0; --i) 02371 unregister_netdev(hw->dev[i]); 02372 02373 sky2_write32(hw, B0_IMSK, 0); 02374 02375 sky2_power_aux(hw); 02376 02377 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); 02378 sky2_write8(hw, B0_CTST, CS_RST_SET); 02379 sky2_read8(hw, B0_CTST); 02380 02381 free_dma(hw->st_le, STATUS_LE_BYTES); 02382 02383 for (i = hw->ports-1; i >= 0; --i) { 02384 netdev_nullify(hw->dev[i]); 02385 netdev_put(hw->dev[i]); 02386 } 02387 02388 iounmap((void *)hw->regs); 02389 free(hw); 02390 02391 pci_set_drvdata(pdev, NULL); 02392 }
struct pci_device_id sky2_id_table[] [static] |
const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 } [static] |
const u16 copper_fc_adv[] [static] |
Initial value:
{
[FC_NONE] = 0,
[FC_TX] = PHY_M_AN_ASP,
[FC_RX] = PHY_M_AN_PC,
[FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
}
Definition at line 272 of file sky2.c.
Referenced by sky2_phy_init().
const u16 fiber_fc_adv[] [static] |
Initial value:
{
[FC_NONE] = PHY_M_P_NO_PAUSE_X,
[FC_TX] = PHY_M_P_ASYM_MD_X,
[FC_RX] = PHY_M_P_SYM_MD_X,
[FC_BOTH] = PHY_M_P_BOTH_MD_X,
}
Definition at line 280 of file sky2.c.
Referenced by sky2_phy_init().
const u16 gm_fc_disable[] [static] |
Initial value:
{
[FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
[FC_TX] = GM_GPCR_FC_RX_DIS,
[FC_RX] = GM_GPCR_FC_TX_DIS,
[FC_BOTH] = 0,
}
Definition at line 288 of file sky2.c.
Referenced by sky2_phy_init().
Definition at line 591 of file sky2.c.
Referenced by sky2_phy_power_down(), and sky2_phy_power_up().
struct net_device_operations sky2_operations [static] |
Initial value:
{
.open = sky2_up,
.close = sky2_down,
.transmit = sky2_xmit_frame,
.poll = sky2_poll,
.irq = sky2_net_irq
}
| struct pci_driver sky2_driver __pci_driver |
Initial value:
{
.ids = sky2_id_table,
.id_count = (sizeof (sky2_id_table) / sizeof (sky2_id_table[0])),
.probe = sky2_probe,
.remove = sky2_remove
}
1.5.7.1