#include <stdint.h>#include <errno.h>#include <stdio.h>#include <unistd.h>#include <gpxe/netdevice.h>#include <gpxe/ethernet.h>#include <gpxe/if_ether.h>#include <gpxe/iobuf.h>#include <gpxe/malloc.h>#include <gpxe/pci.h>#include "skge.h"Go to the source code of this file.
Enumerations | |
| enum | led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST, MO_LED_NORM = 0, MO_LED_BLINK = 1, MO_LED_OFF = 2, MO_LED_ON = 3 } |
Functions | |
| FILE_LICENCE (GPL2_ONLY) | |
| static int | skge_up (struct net_device *dev) |
| static void | skge_down (struct net_device *dev) |
| static void | skge_tx_clean (struct net_device *dev) |
| static int | xm_phy_write (struct skge_hw *hw, int port, u16 reg, u16 val) |
| static int | gm_phy_write (struct skge_hw *hw, int port, u16 reg, u16 val) |
| static void | yukon_init (struct skge_hw *hw, int port) |
| static void | genesis_mac_init (struct skge_hw *hw, int port) |
| static void | genesis_link_up (struct skge_port *skge) |
| static void | skge_phyirq (struct skge_hw *hw) |
| static void | skge_poll (struct net_device *dev) |
| static int | skge_xmit_frame (struct net_device *dev, struct io_buffer *iob) |
| static void | skge_net_irq (struct net_device *dev, int enable) |
| static void | skge_rx_refill (struct net_device *dev) |
| static u32 | skge_supported_modes (const struct skge_hw *hw) |
| static u32 | hwkhz (const struct skge_hw *hw) |
| static u32 | skge_usecs2clk (const struct skge_hw *hw, u32 usec) |
| static void | skge_led (struct skge_port *skge, enum led_mode mode) |
| static int | skge_ring_alloc (struct skge_ring *ring, void *vaddr, u32 base, size_t num) |
| static void | skge_rx_setup (struct skge_port *skge __unused, struct skge_element *e, struct io_buffer *iob, unsigned int bufsize) |
| static void | skge_rx_reuse (struct skge_element *e, unsigned int size) |
| static void | skge_rx_clean (struct skge_port *skge) |
| static void | skge_link_up (struct skge_port *skge) |
| static void | skge_link_down (struct skge_port *skge) |
| static void | xm_link_down (struct skge_hw *hw, int port) |
| static int | __xm_phy_read (struct skge_hw *hw, int port, u16 reg, u16 *val) |
| static u16 | xm_phy_read (struct skge_hw *hw, int port, u16 reg) |
| static void | genesis_init (struct skge_hw *hw) |
| static void | genesis_reset (struct skge_hw *hw, int port) |
| static void | bcom_check_link (struct skge_hw *hw, int port) |
| static void | bcom_phy_init (struct skge_port *skge) |
| static void | xm_phy_init (struct skge_port *skge) |
| static int | xm_check_link (struct net_device *dev) |
| static void | xm_link_timer (struct skge_port *skge) |
| static void | genesis_stop (struct skge_port *skge) |
| static void | bcom_phy_intr (struct skge_port *skge) |
| static int | __gm_phy_read (struct skge_hw *hw, int port, u16 reg, u16 *val) |
| static u16 | gm_phy_read (struct skge_hw *hw, int port, u16 reg) |
| static void | yukon_reset (struct skge_hw *hw, int port) |
| static int | is_yukon_lite_a0 (struct skge_hw *hw) |
| static void | yukon_mac_init (struct skge_hw *hw, int port) |
| static void | yukon_suspend (struct skge_hw *hw, int port) |
| static void | yukon_stop (struct skge_port *skge) |
| static u16 | yukon_speed (const struct skge_hw *hw __unused, u16 aux) |
| static void | yukon_link_up (struct skge_port *skge) |
| static void | yukon_link_down (struct skge_port *skge) |
| static void | yukon_phy_intr (struct skge_port *skge) |
| static void | skge_ramset (struct skge_hw *hw, u16 q, u32 start, size_t len) |
| static void | skge_qset (struct skge_port *skge, u16 q, const struct skge_element *e) |
| void | skge_free (struct net_device *dev) |
| static void | skge_rx_stop (struct skge_hw *hw, int port) |
| static int | skge_tx_avail (const struct skge_ring *ring) |
| static u16 | phy_length (const struct skge_hw *hw, u32 status) |
| static int | bad_phy_status (const struct skge_hw *hw, u32 status) |
| static void | skge_tx_done (struct net_device *dev) |
| static void | skge_rx_done (struct net_device *dev) |
| static const char * | skge_board_name (const struct skge_hw *hw) |
| static int | skge_reset (struct skge_hw *hw) |
| static struct net_device * | skge_devinit (struct skge_hw *hw, int port, int highmem __unused) |
| static void | skge_show_addr (struct net_device *dev) |
| static int | skge_probe (struct pci_device *pdev, const struct pci_device_id *ent __unused) |
| static void | skge_remove (struct pci_device *pdev) |
Variables | |
| static struct pci_device_id | skge_id_table [] |
| static struct net_device_operations | skge_operations |
| static const int | txqaddr [] = { Q_XA1, Q_XA2 } |
| static const int | rxqaddr [] = { Q_R1, Q_R2 } |
| static const u32 | rxirqmask [] = { IS_R1_F, IS_R2_F } |
| static const u32 | txirqmask [] = { IS_XA1_F, IS_XA2_F } |
| static const u32 | napimask [] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F } |
| static const u32 | portmask [] = { IS_PORT_1, IS_PORT_2 } |
| static const u16 | phy_pause_map [] |
| static const u16 | fiber_pause_map [] |
| static const u8 | pause_mc_addr [ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 } |
| struct { | |
| u8 id | |
| const char * name | |
| } | skge_chips [] |
| struct pci_driver skge_driver | __pci_driver |
| enum led_mode |
| FILE_LICENCE | ( | GPL2_ONLY | ) |
| static int skge_up | ( | struct net_device * | dev | ) | [static] |
Definition at line 1709 of file skge.c.
References assert, B0_IMSK, skge_hw::chip_id, CHIP_ID_GENESIS, CSR_IRQ_CL_F, CSR_START, DBG, DBG2, skge_port::dma, EINVAL, ENOMEM, genesis_mac_init(), skge_port::hw, skge_hw::intr_mask, LED_MODE_ON, malloc_dma(), skge_port::mem, memset(), net_device::name, netdev_priv(), NUM_RX_DESC, NUM_TX_DESC, PFX, skge_port::port, portmask, skge_hw::ports, Q_ADDR, Q_CSR, skge_hw::ram_offset, skge_hw::ram_size, RING_SIZE, skge_port::rx_ring, RX_RING_SIZE, rxqaddr, skge_free(), skge_led(), skge_qset(), skge_ramset(), SKGE_RING_ALIGN, skge_ring_alloc(), skge_rx_clean(), skge_rx_refill(), skge_write32(), skge_write8(), skge_ring::to_clean, skge_ring::to_use, skge_port::tx_ring, txqaddr, u32, virt_to_bus(), wmb, and yukon_mac_init().
01710 { 01711 struct skge_port *skge = netdev_priv(dev); 01712 struct skge_hw *hw = skge->hw; 01713 int port = skge->port; 01714 u32 chunk, ram_addr; 01715 int err; 01716 01717 DBG2(PFX "%s: enabling interface\n", dev->name); 01718 01719 skge->mem = malloc_dma(RING_SIZE, SKGE_RING_ALIGN); 01720 skge->dma = virt_to_bus(skge->mem); 01721 if (!skge->mem) 01722 return -ENOMEM; 01723 memset(skge->mem, 0, RING_SIZE); 01724 01725 assert(!(skge->dma & 7)); 01726 01727 /* FIXME: find out whether 64 bit gPXE will be loaded > 4GB */ 01728 if ((u64)skge->dma >> 32 != ((u64) skge->dma + RING_SIZE) >> 32) { 01729 DBG(PFX "pci_alloc_consistent region crosses 4G boundary\n"); 01730 err = -EINVAL; 01731 goto err; 01732 } 01733 01734 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma, NUM_RX_DESC); 01735 if (err) 01736 goto err; 01737 01738 /* this call relies on e->iob and d->control to be 0 01739 * This is assured by calling memset() on skge->mem and using zalloc() 01740 * for the skge_element structures. 01741 */ 01742 skge_rx_refill(dev); 01743 01744 err = skge_ring_alloc(&skge->tx_ring, skge->mem + RX_RING_SIZE, 01745 skge->dma + RX_RING_SIZE, NUM_TX_DESC); 01746 if (err) 01747 goto err; 01748 01749 /* Initialize MAC */ 01750 if (hw->chip_id == CHIP_ID_GENESIS) 01751 genesis_mac_init(hw, port); 01752 else 01753 yukon_mac_init(hw, port); 01754 01755 /* Configure RAMbuffers - equally between ports and tx/rx */ 01756 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2); 01757 ram_addr = hw->ram_offset + 2 * chunk * port; 01758 01759 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); 01760 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); 01761 01762 assert(!(skge->tx_ring.to_use != skge->tx_ring.to_clean)); 01763 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); 01764 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); 01765 01766 /* Start receiver BMU */ 01767 wmb(); 01768 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); 01769 skge_led(skge, LED_MODE_ON); 01770 01771 hw->intr_mask |= portmask[port]; 01772 skge_write32(hw, B0_IMSK, hw->intr_mask); 01773 01774 return 0; 01775 01776 err: 01777 skge_rx_clean(skge); 01778 skge_free(dev); 01779 01780 return err; 01781 }
| static void skge_down | ( | struct net_device * | dev | ) | [static] |
Definition at line 1792 of file skge.c.
References B0_IMSK, skge_hw::chip_id, CHIP_ID_GENESIS, CSR_SET_RESET, CSR_STOP, DBG2, genesis_stop(), GMF_RST_SET, skge_port::hw, skge_hw::intr_mask, LED_MODE_OFF, LED_OFF, LNK_LED_REG, skge_port::mem, MFF_RST_SET, net_device::name, netdev_link_down(), netdev_priv(), NULL, PFX, skge_hw::phy_type, skge_port::port, portmask, Q_ADDR, Q_CSR, Q_XA1, Q_XA2, RB_ADDR, RB_CTRL, RB_DIS_OP_MD, RB_RST_SET, RX_GMF_CTRL_T, RX_MFF_CTRL2, SK_PHY_XMAC, SK_REG, skge_free(), skge_led(), skge_rx_clean(), skge_rx_stop(), skge_tx_clean(), skge_write32(), skge_write8(), TX_GMF_CTRL_T, TX_MFF_CTRL2, TXA_CTRL, TXA_DIS_ALLOC, TXA_DIS_FSYNC, TXA_ITI_INI, TXA_LIM_INI, TXA_STOP_RC, txqaddr, skge_port::use_xm_link_timer, and yukon_stop().
01793 { 01794 struct skge_port *skge = netdev_priv(dev); 01795 struct skge_hw *hw = skge->hw; 01796 int port = skge->port; 01797 01798 if (skge->mem == NULL) 01799 return; 01800 01801 DBG2(PFX "%s: disabling interface\n", dev->name); 01802 01803 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC) 01804 skge->use_xm_link_timer = 0; 01805 01806 netdev_link_down(dev); 01807 01808 hw->intr_mask &= ~portmask[port]; 01809 skge_write32(hw, B0_IMSK, hw->intr_mask); 01810 01811 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); 01812 if (hw->chip_id == CHIP_ID_GENESIS) 01813 genesis_stop(skge); 01814 else 01815 yukon_stop(skge); 01816 01817 /* Stop transmitter */ 01818 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); 01819 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), 01820 RB_RST_SET|RB_DIS_OP_MD); 01821 01822 01823 /* Disable Force Sync bit and Enable Alloc bit */ 01824 skge_write8(hw, SK_REG(port, TXA_CTRL), 01825 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 01826 01827 /* Stop Interval Timer and Limit Counter of Tx Arbiter */ 01828 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); 01829 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); 01830 01831 /* Reset PCI FIFO */ 01832 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); 01833 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); 01834 01835 /* Reset the RAM Buffer async Tx queue */ 01836 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); 01837 01838 skge_rx_stop(hw, port); 01839 01840 if (hw->chip_id == CHIP_ID_GENESIS) { 01841 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); 01842 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); 01843 } else { 01844 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); 01845 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); 01846 } 01847 01848 skge_led(skge, LED_MODE_OFF); 01849 01850 skge_tx_clean(dev); 01851 01852 skge_rx_clean(skge); 01853 01854 skge_free(dev); 01855 return; 01856 }
| static void skge_tx_clean | ( | struct net_device * | dev | ) | [static] |
Definition at line 1911 of file skge.c.
References skge_tx_desc::control, skge_element::desc, netdev_priv(), skge_element::next, skge_ring::to_clean, skge_ring::to_use, and skge_port::tx_ring.
Referenced by skge_down().
01912 { 01913 struct skge_port *skge = netdev_priv(dev); 01914 struct skge_element *e; 01915 01916 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { 01917 struct skge_tx_desc *td = e->desc; 01918 td->control = 0; 01919 } 01920 01921 skge->tx_ring.to_clean = e; 01922 }
Definition at line 460 of file skge.c.
References EIO, ETIMEDOUT, skge_hw::phy_addr, PHY_RETRIES, udelay(), XM_MMU_CMD, XM_MMU_PHY_BUSY, XM_PHY_ADDR, XM_PHY_DATA, xm_read16(), and xm_write16().
Referenced by bcom_phy_init(), bcom_phy_intr(), genesis_link_up(), skge_led(), and xm_phy_init().
00461 { 00462 int i; 00463 00464 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 00465 for (i = 0; i < PHY_RETRIES; i++) { 00466 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 00467 goto ready; 00468 udelay(1); 00469 } 00470 return -EIO; 00471 00472 ready: 00473 xm_write16(hw, port, XM_PHY_DATA, val); 00474 for (i = 0; i < PHY_RETRIES; i++) { 00475 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) 00476 return 0; 00477 udelay(1); 00478 } 00479 return -ETIMEDOUT; 00480 }
Definition at line 1161 of file skge.c.
References DBG, skge_hw::dev, EIO, GM_SMI_CT_BUSY, GM_SMI_CT_PHY_AD, GM_SMI_CT_REG_AD, GM_SMI_CTRL, GM_SMI_DATA, gma_read16(), gma_write16(), net_device::name, PFX, skge_hw::phy_addr, PHY_RETRIES, and udelay().
Referenced by skge_led(), sky2_link_down(), sky2_link_up(), sky2_phy_init(), sky2_phy_power_down(), sky2_phy_power_up(), yukon_init(), yukon_link_down(), yukon_link_up(), yukon_reset(), and yukon_suspend().
01162 { 01163 int i; 01164 01165 gma_write16(hw, port, GM_SMI_DATA, val); 01166 gma_write16(hw, port, GM_SMI_CTRL, 01167 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); 01168 for (i = 0; i < PHY_RETRIES; i++) { 01169 udelay(1); 01170 01171 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) 01172 return 0; 01173 } 01174 01175 DBG(PFX "%s: phy write timeout port %x reg %x val %x\n", 01176 hw->dev[port]->name, 01177 port, reg, val); 01178 return -EIO; 01179 }
| static void yukon_init | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 1212 of file skge.c.
References ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, ADVERTISED_100baseT_Full, ADVERTISED_100baseT_Half, ADVERTISED_10baseT_Full, ADVERTISED_10baseT_Half, skge_port::advertising, skge_port::autoneg, AUTONEG_DISABLE, AUTONEG_ENABLE, skge_hw::copper, skge_hw::dev, skge_port::duplex, DUPLEX_FULL, fiber_pause_map, skge_port::flow_control, gm_phy_read(), gm_phy_write(), MAC_TX_CLK_25_MHZ, netdev_priv(), PHY_AN_CSMA, PHY_CT_ANE, PHY_CT_DUP_MD, PHY_CT_RE_CFG, PHY_CT_RESET, PHY_CT_SP100, PHY_CT_SP1000, PHY_M_1000C_AFD, PHY_M_1000C_AHD, PHY_M_1000C_MSE, PHY_M_AN_1000X_AFD, PHY_M_AN_1000X_AHD, PHY_M_AN_100_FD, PHY_M_AN_100_HD, PHY_M_AN_10_FD, PHY_M_AN_10_HD, PHY_M_EC_M_DSC, PHY_M_EC_M_DSC_MSK, PHY_M_EC_MAC_S, PHY_M_EC_MAC_S_MSK, PHY_M_EC_S_DSC, PHY_M_EC_S_DSC_MSK, PHY_M_IS_AN_MSK, PHY_M_IS_DEF_MSK, PHY_MARV_1000T_CTRL, PHY_MARV_AUNE_ADV, PHY_MARV_CTRL, PHY_MARV_EXT_CTRL, PHY_MARV_INT_MASK, phy_pause_map, skge_port::speed, SPEED_100, SPEED_1000, and u16.
Referenced by yukon_link_down(), and yukon_mac_init().
01213 { 01214 struct skge_port *skge = netdev_priv(hw->dev[port]); 01215 u16 ctrl, ct1000, adv; 01216 01217 if (skge->autoneg == AUTONEG_ENABLE) { 01218 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); 01219 01220 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | 01221 PHY_M_EC_MAC_S_MSK); 01222 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); 01223 01224 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); 01225 01226 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); 01227 } 01228 01229 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 01230 if (skge->autoneg == AUTONEG_DISABLE) 01231 ctrl &= ~PHY_CT_ANE; 01232 01233 ctrl |= PHY_CT_RESET; 01234 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 01235 01236 ctrl = 0; 01237 ct1000 = 0; 01238 adv = PHY_AN_CSMA; 01239 01240 if (skge->autoneg == AUTONEG_ENABLE) { 01241 if (hw->copper) { 01242 if (skge->advertising & ADVERTISED_1000baseT_Full) 01243 ct1000 |= PHY_M_1000C_AFD; 01244 if (skge->advertising & ADVERTISED_1000baseT_Half) 01245 ct1000 |= PHY_M_1000C_AHD; 01246 if (skge->advertising & ADVERTISED_100baseT_Full) 01247 adv |= PHY_M_AN_100_FD; 01248 if (skge->advertising & ADVERTISED_100baseT_Half) 01249 adv |= PHY_M_AN_100_HD; 01250 if (skge->advertising & ADVERTISED_10baseT_Full) 01251 adv |= PHY_M_AN_10_FD; 01252 if (skge->advertising & ADVERTISED_10baseT_Half) 01253 adv |= PHY_M_AN_10_HD; 01254 01255 /* Set Flow-control capabilities */ 01256 adv |= phy_pause_map[skge->flow_control]; 01257 } else { 01258 if (skge->advertising & ADVERTISED_1000baseT_Full) 01259 adv |= PHY_M_AN_1000X_AFD; 01260 if (skge->advertising & ADVERTISED_1000baseT_Half) 01261 adv |= PHY_M_AN_1000X_AHD; 01262 01263 adv |= fiber_pause_map[skge->flow_control]; 01264 } 01265 01266 /* Restart Auto-negotiation */ 01267 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; 01268 } else { 01269 /* forced speed/duplex settings */ 01270 ct1000 = PHY_M_1000C_MSE; 01271 01272 if (skge->duplex == DUPLEX_FULL) 01273 ctrl |= PHY_CT_DUP_MD; 01274 01275 switch (skge->speed) { 01276 case SPEED_1000: 01277 ctrl |= PHY_CT_SP1000; 01278 break; 01279 case SPEED_100: 01280 ctrl |= PHY_CT_SP100; 01281 break; 01282 } 01283 01284 ctrl |= PHY_CT_RESET; 01285 } 01286 01287 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); 01288 01289 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); 01290 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 01291 01292 /* Enable phy interrupt on autonegotiation complete (or link up) */ 01293 if (skge->autoneg == AUTONEG_ENABLE) 01294 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); 01295 else 01296 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); 01297 }
| static void genesis_mac_init | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 854 of file skge.c.
References B2_GP_IO, B3_MA_RCINI_RX1, B3_MA_RCINI_RX2, B3_MA_RCINI_TX1, B3_MA_RCINI_TX2, B3_MA_TO_CTRL, B3_MA_TOINI_RX1, B3_MA_TOINI_RX2, B3_MA_TOINI_TX1, B3_MA_TOINI_TX2, B3_PA_CTRL, bcom_check_link(), bcom_phy_init(), DBG, skge_hw::dev, net_device::dev, skge_port::duplex, DUPLEX_HALF, GP_DIR_0, GP_DIR_2, GP_IO_0, GP_IO_2, net_device::ll_addr, MA_RST_CLR, MFF_CLR_MAC_RST, MFF_ENA_OP_MD, MFF_ENA_TIM_PAT, MFF_RST_CLR, MFF_SET_MAC_RST, MFF_TX_CTRL_DEF, net_device::name, netdev_priv(), PA_ENA_TO_TX1, PA_ENA_TO_TX2, PFX, skge_hw::phy_type, r, RX_MFF_CTRL1, RX_MFF_CTRL2, SK_PHY_BCOM, SK_PHY_XMAC, SK_REG, skge_read16(), skge_read32(), skge_write16(), skge_write32(), skge_write8(), TX_MFF_CTRL1, TX_MFF_CTRL2, u32, u8, udelay(), XM_DEF_MODE, XM_EXM, XM_HW_CFG, XM_HW_GMII_MD, XM_MODE, xm_outaddr(), xm_phy_init(), XM_RX_CMD, XM_RX_DIS_CEXT, XM_RX_EV_MSK, XM_RX_HI_WM, XM_RX_LENERR_OK, XM_RX_STRIP_FCS, XM_SA, XM_SC_CLR_RXC, XM_SC_CLR_TXC, XM_STAT_CMD, XM_TX_AUTO_PAD, XM_TX_CMD, XM_TX_EV_MSK, XM_TX_THR, xm_write16(), xm_write32(), XMR_DEF_MSK, and XMT_DEF_MSK.
Referenced by skge_up().
00855 { 00856 struct net_device *dev = hw->dev[port]; 00857 struct skge_port *skge = netdev_priv(dev); 00858 int i; 00859 u32 r; 00860 const u8 zero[6] = { 0 }; 00861 00862 for (i = 0; i < 10; i++) { 00863 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), 00864 MFF_SET_MAC_RST); 00865 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) 00866 goto reset_ok; 00867 udelay(1); 00868 } 00869 00870 DBG(PFX "%s: genesis reset failed\n", dev->name); 00871 00872 reset_ok: 00873 /* Unreset the XMAC. */ 00874 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 00875 00876 /* 00877 * Perform additional initialization for external PHYs, 00878 * namely for the 1000baseTX cards that use the XMAC's 00879 * GMII mode. 00880 */ 00881 if (hw->phy_type != SK_PHY_XMAC) { 00882 /* Take external Phy out of reset */ 00883 r = skge_read32(hw, B2_GP_IO); 00884 if (port == 0) 00885 r |= GP_DIR_0|GP_IO_0; 00886 else 00887 r |= GP_DIR_2|GP_IO_2; 00888 00889 skge_write32(hw, B2_GP_IO, r); 00890 00891 /* Enable GMII interface */ 00892 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); 00893 } 00894 00895 00896 switch(hw->phy_type) { 00897 case SK_PHY_XMAC: 00898 xm_phy_init(skge); 00899 break; 00900 case SK_PHY_BCOM: 00901 bcom_phy_init(skge); 00902 bcom_check_link(hw, port); 00903 } 00904 00905 /* Set Station Address */ 00906 xm_outaddr(hw, port, XM_SA, dev->ll_addr); 00907 00908 /* We don't use match addresses so clear */ 00909 for (i = 1; i < 16; i++) 00910 xm_outaddr(hw, port, XM_EXM(i), zero); 00911 00912 /* Clear MIB counters */ 00913 xm_write16(hw, port, XM_STAT_CMD, 00914 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 00915 /* Clear two times according to Errata #3 */ 00916 xm_write16(hw, port, XM_STAT_CMD, 00917 XM_SC_CLR_RXC | XM_SC_CLR_TXC); 00918 00919 /* configure Rx High Water Mark (XM_RX_HI_WM) */ 00920 xm_write16(hw, port, XM_RX_HI_WM, 1450); 00921 00922 /* We don't need the FCS appended to the packet. */ 00923 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS; 00924 00925 if (skge->duplex == DUPLEX_HALF) { 00926 /* 00927 * If in manual half duplex mode the other side might be in 00928 * full duplex mode, so ignore if a carrier extension is not seen 00929 * on frames received 00930 */ 00931 r |= XM_RX_DIS_CEXT; 00932 } 00933 xm_write16(hw, port, XM_RX_CMD, r); 00934 00935 /* We want short frames padded to 60 bytes. */ 00936 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); 00937 00938 xm_write16(hw, port, XM_TX_THR, 512); 00939 00940 /* 00941 * Enable the reception of all error frames. This is is 00942 * a necessary evil due to the design of the XMAC. The 00943 * XMAC's receive FIFO is only 8K in size, however jumbo 00944 * frames can be up to 9000 bytes in length. When bad 00945 * frame filtering is enabled, the XMAC's RX FIFO operates 00946 * in 'store and forward' mode. For this to work, the 00947 * entire frame has to fit into the FIFO, but that means 00948 * that jumbo frames larger than 8192 bytes will be 00949 * truncated. Disabling all bad frame filtering causes 00950 * the RX FIFO to operate in streaming mode, in which 00951 * case the XMAC will start transferring frames out of the 00952 * RX FIFO as soon as the FIFO threshold is reached. 00953 */ 00954 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); 00955 00956 00957 /* 00958 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) 00959 * - Enable all bits excepting 'Octets Rx OK Low CntOv' 00960 * and 'Octets Rx OK Hi Cnt Ov'. 00961 */ 00962 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); 00963 00964 /* 00965 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) 00966 * - Enable all bits excepting 'Octets Tx OK Low CntOv' 00967 * and 'Octets Tx OK Hi Cnt Ov'. 00968 */ 00969 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); 00970 00971 /* Configure MAC arbiter */ 00972 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 00973 00974 /* configure timeout values */ 00975 skge_write8(hw, B3_MA_TOINI_RX1, 72); 00976 skge_write8(hw, B3_MA_TOINI_RX2, 72); 00977 skge_write8(hw, B3_MA_TOINI_TX1, 72); 00978 skge_write8(hw, B3_MA_TOINI_TX2, 72); 00979 00980 skge_write8(hw, B3_MA_RCINI_RX1, 0); 00981 skge_write8(hw, B3_MA_RCINI_RX2, 0); 00982 skge_write8(hw, B3_MA_RCINI_TX1, 0); 00983 skge_write8(hw, B3_MA_RCINI_TX2, 0); 00984 00985 /* Configure Rx MAC FIFO */ 00986 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); 00987 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); 00988 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); 00989 00990 /* Configure Tx MAC FIFO */ 00991 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); 00992 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); 00993 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); 00994 00995 /* enable timeout timers */ 00996 skge_write16(hw, B3_PA_CTRL, 00997 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); 00998 }
| static void genesis_link_up | ( | struct skge_port * | skge | ) | [static] |
Definition at line 1047 of file skge.c.
References skge_port::duplex, DUPLEX_FULL, FLOW_STAT_LOC_SEND, FLOW_STAT_NONE, FLOW_STAT_SYMMETRIC, skge_port::flow_status, skge_port::hw, MFF_DIS_PAUSE, MFF_ENA_PAUSE, PHY_B_AC_DIS_PM, PHY_B_DEF_MSK, PHY_BCOM_AUX_CTRL, PHY_BCOM_INT_MASK, skge_hw::phy_type, skge_port::port, RX_MFF_CTRL1, SK_PHY_BCOM, SK_PHY_XMAC, SK_REG, skge_link_up(), skge_write16(), u16, u32, XM_IMSK, XM_IS_TXF_UR, XM_ISRC, XM_MAC_PTIME, XM_MMU_CMD, XM_MMU_ENA_RX, XM_MMU_ENA_TX, XM_MMU_GMII_FD, XM_MMU_IGN_PF, XM_MODE, XM_PAUSE_MODE, xm_phy_read(), xm_phy_write(), xm_read16(), xm_read32(), xm_write16(), and xm_write32().
Referenced by bcom_check_link(), and xm_check_link().
01048 { 01049 struct skge_hw *hw = skge->hw; 01050 int port = skge->port; 01051 u16 cmd, msk; 01052 u32 mode; 01053 01054 cmd = xm_read16(hw, port, XM_MMU_CMD); 01055 01056 /* 01057 * enabling pause frame reception is required for 1000BT 01058 * because the XMAC is not reset if the link is going down 01059 */ 01060 if (skge->flow_status == FLOW_STAT_NONE || 01061 skge->flow_status == FLOW_STAT_LOC_SEND) 01062 /* Disable Pause Frame Reception */ 01063 cmd |= XM_MMU_IGN_PF; 01064 else 01065 /* Enable Pause Frame Reception */ 01066 cmd &= ~XM_MMU_IGN_PF; 01067 01068 xm_write16(hw, port, XM_MMU_CMD, cmd); 01069 01070 mode = xm_read32(hw, port, XM_MODE); 01071 if (skge->flow_status== FLOW_STAT_SYMMETRIC || 01072 skge->flow_status == FLOW_STAT_LOC_SEND) { 01073 /* 01074 * Configure Pause Frame Generation 01075 * Use internal and external Pause Frame Generation. 01076 * Sending pause frames is edge triggered. 01077 * Send a Pause frame with the maximum pause time if 01078 * internal oder external FIFO full condition occurs. 01079 * Send a zero pause time frame to re-start transmission. 01080 */ 01081 /* XM_PAUSE_DA = '010000C28001' (default) */ 01082 /* XM_MAC_PTIME = 0xffff (maximum) */ 01083 /* remember this value is defined in big endian (!) */ 01084 xm_write16(hw, port, XM_MAC_PTIME, 0xffff); 01085 01086 mode |= XM_PAUSE_MODE; 01087 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); 01088 } else { 01089 /* 01090 * disable pause frame generation is required for 1000BT 01091 * because the XMAC is not reset if the link is going down 01092 */ 01093 /* Disable Pause Mode in Mode Register */ 01094 mode &= ~XM_PAUSE_MODE; 01095 01096 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); 01097 } 01098 01099 xm_write32(hw, port, XM_MODE, mode); 01100 01101 /* Turn on detection of Tx underrun */ 01102 msk = xm_read16(hw, port, XM_IMSK); 01103 msk &= ~XM_IS_TXF_UR; 01104 xm_write16(hw, port, XM_IMSK, msk); 01105 01106 xm_read16(hw, port, XM_ISRC); 01107 01108 /* get MMU Command Reg. */ 01109 cmd = xm_read16(hw, port, XM_MMU_CMD); 01110 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL) 01111 cmd |= XM_MMU_GMII_FD; 01112 01113 /* 01114 * Workaround BCOM Errata (#10523) for all BCom Phys 01115 * Enable Power Management after link up 01116 */ 01117 if (hw->phy_type == SK_PHY_BCOM) { 01118 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, 01119 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) 01120 & ~PHY_B_AC_DIS_PM); 01121 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 01122 } 01123 01124 /* enable Rx/Tx */ 01125 xm_write16(hw, port, XM_MMU_CMD, 01126 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); 01127 skge_link_up(skge); 01128 }
| static void skge_phyirq | ( | struct skge_hw * | hw | ) | [static] |
Definition at line 2086 of file skge.c.
References B0_IMSK, bcom_phy_intr(), skge_hw::chip_id, CHIP_ID_GENESIS, skge_hw::dev, net_device::dev, skge_hw::intr_mask, IS_EXT_REG, netdev_priv(), skge_hw::phy_type, skge_hw::ports, SK_PHY_BCOM, skge_read32(), skge_write32(), and yukon_phy_intr().
Referenced by skge_poll().
02087 { 02088 int port; 02089 02090 for (port = 0; port < hw->ports; port++) { 02091 struct net_device *dev = hw->dev[port]; 02092 struct skge_port *skge = netdev_priv(dev); 02093 02094 if (hw->chip_id != CHIP_ID_GENESIS) 02095 yukon_phy_intr(skge); 02096 else if (hw->phy_type == SK_PHY_BCOM) 02097 bcom_phy_intr(skge); 02098 } 02099 02100 hw->intr_mask |= IS_EXT_REG; 02101 skge_write32(hw, B0_IMSK, hw->intr_mask); 02102 skge_read32(hw, B0_IMSK); 02103 }
| static void skge_poll | ( | struct net_device * | dev | ) | [static] |
Definition at line 2055 of file skge.c.
References B0_IMSK, B0_SP_ISRC, CSR_IRQ_CL_F, CSR_START, skge_port::hw, IS_EXT_REG, netdev_priv(), skge_port::port, Q_ADDR, Q_CSR, rxqaddr, skge_phyirq(), skge_read32(), skge_rx_done(), skge_tx_done(), skge_write8(), u32, skge_port::use_xm_link_timer, wmb, and xm_link_timer().
02056 { 02057 struct skge_port *skge = netdev_priv(dev); 02058 struct skge_hw *hw = skge->hw; 02059 u32 status; 02060 02061 /* reading this register ACKs interrupts */ 02062 status = skge_read32(hw, B0_SP_ISRC); 02063 02064 /* Link event? */ 02065 if (status & IS_EXT_REG) { 02066 skge_phyirq(hw); 02067 if (skge->use_xm_link_timer) 02068 xm_link_timer(skge); 02069 } 02070 02071 skge_tx_done(dev); 02072 02073 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); 02074 02075 skge_rx_done(dev); 02076 02077 /* restart receiver */ 02078 wmb(); 02079 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); 02080 02081 skge_read32(hw, B0_IMSK); 02082 02083 return; 02084 }
| static int skge_xmit_frame | ( | struct net_device * | dev, | |
| struct io_buffer * | iob | |||
| ) | [static] |
Definition at line 1865 of file skge.c.
References assert, BMU_CHECK, BMU_EOF, BMU_IRQ_EOF, BMU_OWN, BMU_STF, BMU_SW, skge_tx_desc::control, CSR_START, io_buffer::data, DBG, DBGIO, skge_element::desc, skge_tx_desc::dma_hi, skge_tx_desc::dma_lo, EBUSY, skge_port::hw, skge_element::iob, iob_len(), net_device::name, netdev_priv(), skge_element::next, PFX, skge_port::port, Q_ADDR, Q_CSR, skge_tx_avail(), skge_write8(), skge_ring::start, skge_ring::to_use, skge_port::tx_ring, txqaddr, u32, virt_to_bus(), and wmb.
01866 { 01867 struct skge_port *skge = netdev_priv(dev); 01868 struct skge_hw *hw = skge->hw; 01869 struct skge_element *e; 01870 struct skge_tx_desc *td; 01871 u32 control, len; 01872 u64 map; 01873 01874 if (skge_tx_avail(&skge->tx_ring) < 1) 01875 return -EBUSY; 01876 01877 e = skge->tx_ring.to_use; 01878 td = e->desc; 01879 assert(!(td->control & BMU_OWN)); 01880 e->iob = iob; 01881 len = iob_len(iob); 01882 map = virt_to_bus(iob->data); 01883 01884 td->dma_lo = map; 01885 td->dma_hi = map >> 32; 01886 01887 control = BMU_CHECK; 01888 01889 control |= BMU_EOF| BMU_IRQ_EOF; 01890 /* Make sure all the descriptors written */ 01891 wmb(); 01892 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; 01893 wmb(); 01894 01895 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); 01896 01897 DBGIO(PFX "%s: tx queued, slot %td, len %d\n", 01898 dev->name, e - skge->tx_ring.start, (unsigned int)len); 01899 01900 skge->tx_ring.to_use = e->next; 01901 wmb(); 01902 01903 if (skge_tx_avail(&skge->tx_ring) <= 1) { 01904 DBG(PFX "%s: transmit queue full\n", dev->name); 01905 } 01906 01907 return 0; 01908 }
| static void skge_net_irq | ( | struct net_device * | dev, | |
| int | enable | |||
| ) | [static] |
Definition at line 2455 of file skge.c.
References B0_IMSK, skge_port::hw, skge_hw::intr_mask, netdev_priv(), skge_port::port, portmask, and skge_write32().
02455 { 02456 struct skge_port *skge = netdev_priv(dev); 02457 struct skge_hw *hw = skge->hw; 02458 02459 if (enable) 02460 hw->intr_mask |= portmask[skge->port]; 02461 else 02462 hw->intr_mask &= ~portmask[skge->port]; 02463 skge_write32(hw, B0_IMSK, hw->intr_mask); 02464 }
| static void skge_rx_refill | ( | struct net_device * | dev | ) | [static] |
Definition at line 1966 of file skge.c.
References alloc_iob(), BMU_OWN, skge_rx_desc::control, DBG, DBG2, skge_element::desc, skge_element::iob, netdev_priv(), skge_element::next, NULL, NUM_RX_DESC, RX_BUF_SIZE, skge_port::rx_ring, skge_rx_setup(), skge_ring::start, skge_ring::to_clean, and u32.
Referenced by skge_rx_done(), and skge_up().
01967 { 01968 struct skge_port *skge = netdev_priv(dev); 01969 struct skge_ring *ring = &skge->rx_ring; 01970 struct skge_element *e; 01971 struct io_buffer *iob; 01972 struct skge_rx_desc *rd; 01973 u32 control; 01974 int i; 01975 01976 for (i = 0; i < NUM_RX_DESC; i++) { 01977 e = ring->to_clean; 01978 rd = e->desc; 01979 iob = e->iob; 01980 control = rd->control; 01981 01982 /* nothing to do here */ 01983 if (iob || (control & BMU_OWN)) 01984 continue; 01985 01986 DBG2("refilling rx desc %d: ", (ring->to_clean - ring->start)); 01987 01988 iob = alloc_iob(RX_BUF_SIZE); 01989 if (iob) { 01990 skge_rx_setup(skge, e, iob, RX_BUF_SIZE); 01991 } else { 01992 DBG("descr %d: alloc_iob() failed\n", 01993 (ring->to_clean - ring->start)); 01994 /* We pass the descriptor to the NIC even if the 01995 * allocation failed. The card will stop as soon as it 01996 * encounters a descriptor with the OWN bit set to 0, 01997 * thus never getting to the next descriptor that might 01998 * contain a valid io_buffer. This would effectively 01999 * stall the receive. 02000 */ 02001 skge_rx_setup(skge, e, NULL, 0); 02002 } 02003 02004 ring->to_clean = e->next; 02005 } 02006 }
Definition at line 94 of file skge.c.
References skge_hw::chip_id, CHIP_ID_GENESIS, CHIP_ID_YUKON, skge_hw::copper, SUPPORTED_1000baseT_Full, SUPPORTED_1000baseT_Half, SUPPORTED_100baseT_Full, SUPPORTED_100baseT_Half, SUPPORTED_10baseT_Full, SUPPORTED_10baseT_Half, SUPPORTED_Autoneg, SUPPORTED_FIBRE, SUPPORTED_TP, and u32.
Referenced by skge_devinit().
00095 { 00096 u32 supported; 00097 00098 if (hw->copper) { 00099 supported = SUPPORTED_10baseT_Half 00100 | SUPPORTED_10baseT_Full 00101 | SUPPORTED_100baseT_Half 00102 | SUPPORTED_100baseT_Full 00103 | SUPPORTED_1000baseT_Half 00104 | SUPPORTED_1000baseT_Full 00105 | SUPPORTED_Autoneg| SUPPORTED_TP; 00106 00107 if (hw->chip_id == CHIP_ID_GENESIS) 00108 supported &= ~(SUPPORTED_10baseT_Half 00109 | SUPPORTED_10baseT_Full 00110 | SUPPORTED_100baseT_Half 00111 | SUPPORTED_100baseT_Full); 00112 00113 else if (hw->chip_id == CHIP_ID_YUKON) 00114 supported &= ~SUPPORTED_1000baseT_Half; 00115 } else 00116 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half 00117 | SUPPORTED_FIBRE | SUPPORTED_Autoneg; 00118 00119 return supported; 00120 }
Definition at line 123 of file skge.c.
References skge_hw::chip_id, and CHIP_ID_GENESIS.
Referenced by skge_usecs2clk().
00124 { 00125 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125; 00126 }
Definition at line 129 of file skge.c.
References hwkhz().
Referenced by skge_reset().
00130 { 00131 return hwkhz(hw) * usec / 1000; 00132 }
Definition at line 135 of file skge.c.
References BLINK_84MS, skge_hw::chip_id, CHIP_ID_GENESIS, gm_phy_write(), skge_port::hw, LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST, LED_START, LED_T_OFF, LED_T_ON, LINKLED_LINKSYNC_ON, LINKLED_OFF, LINKLED_ON, LNK_LED_REG, MO_LED_OFF, MO_LED_ON, PHY_B_PEC_LED_OFF, PHY_B_PEC_LED_ON, PHY_BCOM_P_EXT_CTRL, PHY_M_LED_BLINK_RT, PHY_M_LED_MO_10, PHY_M_LED_MO_100, PHY_M_LED_MO_1000, PHY_M_LED_MO_DUP, PHY_M_LED_MO_RX, PHY_M_LED_PULS_DUR, PHY_M_LEDC_DP_CTRL, PHY_M_LEDC_TX_CTRL, PHY_MARV_LED_CTRL, PHY_MARV_LED_OVER, skge_hw::phy_type, skge_port::port, PULS_170MS, RX_LED_CTRL, RX_LED_TST, RX_LED_VAL, SK_PHY_BCOM, SK_REG, skge_write32(), skge_write8(), skge_port::speed, SPEED_100, TX_LED_CTRL, TX_LED_TST, TX_LED_VAL, and xm_phy_write().
Referenced by skge_down(), and skge_up().
00136 { 00137 struct skge_hw *hw = skge->hw; 00138 int port = skge->port; 00139 00140 if (hw->chip_id == CHIP_ID_GENESIS) { 00141 switch (mode) { 00142 case LED_MODE_OFF: 00143 if (hw->phy_type == SK_PHY_BCOM) 00144 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); 00145 else { 00146 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0); 00147 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF); 00148 } 00149 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); 00150 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); 00151 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); 00152 break; 00153 00154 case LED_MODE_ON: 00155 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); 00156 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); 00157 00158 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 00159 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); 00160 00161 break; 00162 00163 case LED_MODE_TST: 00164 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); 00165 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); 00166 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); 00167 00168 if (hw->phy_type == SK_PHY_BCOM) 00169 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); 00170 else { 00171 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON); 00172 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100); 00173 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); 00174 } 00175 00176 } 00177 } else { 00178 switch (mode) { 00179 case LED_MODE_OFF: 00180 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 00181 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 00182 PHY_M_LED_MO_DUP(MO_LED_OFF) | 00183 PHY_M_LED_MO_10(MO_LED_OFF) | 00184 PHY_M_LED_MO_100(MO_LED_OFF) | 00185 PHY_M_LED_MO_1000(MO_LED_OFF) | 00186 PHY_M_LED_MO_RX(MO_LED_OFF)); 00187 break; 00188 case LED_MODE_ON: 00189 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 00190 PHY_M_LED_PULS_DUR(PULS_170MS) | 00191 PHY_M_LED_BLINK_RT(BLINK_84MS) | 00192 PHY_M_LEDC_TX_CTRL | 00193 PHY_M_LEDC_DP_CTRL); 00194 00195 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 00196 PHY_M_LED_MO_RX(MO_LED_OFF) | 00197 (skge->speed == SPEED_100 ? 00198 PHY_M_LED_MO_100(MO_LED_ON) : 0)); 00199 break; 00200 case LED_MODE_TST: 00201 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); 00202 gm_phy_write(hw, port, PHY_MARV_LED_OVER, 00203 PHY_M_LED_MO_DUP(MO_LED_ON) | 00204 PHY_M_LED_MO_10(MO_LED_ON) | 00205 PHY_M_LED_MO_100(MO_LED_ON) | 00206 PHY_M_LED_MO_1000(MO_LED_ON) | 00207 PHY_M_LED_MO_RX(MO_LED_ON)); 00208 } 00209 } 00210 }
Definition at line 313 of file skge.c.
References skge_element::desc, ENOMEM, skge_element::next, skge_tx_desc::next_offset, skge_ring::start, skge_ring::to_clean, skge_ring::to_use, and zalloc().
Referenced by skge_up().
00315 { 00316 struct skge_tx_desc *d; 00317 struct skge_element *e; 00318 unsigned int i; 00319 00320 ring->start = zalloc(num*sizeof(*e)); 00321 if (!ring->start) 00322 return -ENOMEM; 00323 00324 for (i = 0, e = ring->start, d = vaddr; i < num; i++, e++, d++) { 00325 e->desc = d; 00326 if (i == num - 1) { 00327 e->next = ring->start; 00328 d->next_offset = base; 00329 } else { 00330 e->next = e + 1; 00331 d->next_offset = base + (i+1) * sizeof(*d); 00332 } 00333 } 00334 ring->to_use = ring->to_clean = ring->start; 00335 00336 return 0; 00337 }
| static void skge_rx_setup | ( | struct skge_port *skge | __unused, | |
| struct skge_element * | e, | |||
| struct io_buffer * | iob, | |||
| unsigned int | bufsize | |||
| ) | [static] |
Definition at line 340 of file skge.c.
References BMU_IRQ_EOF, BMU_OWN, BMU_STF, BMU_TCP_CHECK, skge_rx_desc::control, skge_rx_desc::csum1, skge_rx_desc::csum1_start, skge_rx_desc::csum2, skge_rx_desc::csum2_start, io_buffer::data, skge_element::desc, skge_rx_desc::dma_hi, skge_rx_desc::dma_lo, ETH_HLEN, skge_element::iob, NULL, virt_to_bus(), and wmb.
Referenced by skge_rx_refill().
00343 { 00344 struct skge_rx_desc *rd = e->desc; 00345 u64 map; 00346 00347 map = ( iob != NULL ) ? virt_to_bus(iob->data) : 0; 00348 00349 rd->dma_lo = map; 00350 rd->dma_hi = map >> 32; 00351 e->iob = iob; 00352 rd->csum1_start = ETH_HLEN; 00353 rd->csum2_start = ETH_HLEN; 00354 rd->csum1 = 0; 00355 rd->csum2 = 0; 00356 00357 wmb(); 00358 00359 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; 00360 }
| static void skge_rx_reuse | ( | struct skge_element * | e, | |
| unsigned int | size | |||
| ) | [inline, static] |
Definition at line 366 of file skge.c.
References BMU_IRQ_EOF, BMU_OWN, BMU_STF, BMU_TCP_CHECK, skge_rx_desc::control, skge_rx_desc::csum2, skge_rx_desc::csum2_start, skge_element::desc, ETH_HLEN, and wmb.
00367 { 00368 struct skge_rx_desc *rd = e->desc; 00369 00370 rd->csum2 = 0; 00371 rd->csum2_start = ETH_HLEN; 00372 00373 wmb(); 00374 00375 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size; 00376 }
| static void skge_rx_clean | ( | struct skge_port * | skge | ) | [static] |
Definition at line 380 of file skge.c.
References skge_rx_desc::control, skge_element::desc, free_iob(), skge_element::iob, skge_element::next, NULL, skge_port::rx_ring, and skge_ring::start.
Referenced by skge_down(), and skge_up().
00381 { 00382 struct skge_ring *ring = &skge->rx_ring; 00383 struct skge_element *e; 00384 00385 e = ring->start; 00386 do { 00387 struct skge_rx_desc *rd = e->desc; 00388 rd->control = 0; 00389 if (e->iob) { 00390 free_iob(e->iob); 00391 e->iob = NULL; 00392 } 00393 } while ((e = e->next) != ring->start); 00394 }
| static void skge_link_up | ( | struct skge_port * | skge | ) | [static] |
Definition at line 396 of file skge.c.
References DBG2, skge_port::duplex, DUPLEX_FULL, skge_port::hw, LED_BLK_OFF, LED_ON, LED_SYNC_OFF, LNK_LED_REG, net_device::name, skge_port::netdev, netdev_link_up(), PFX, skge_port::port, SK_REG, skge_write8(), and skge_port::speed.
Referenced by genesis_link_up(), and yukon_link_up().
00397 { 00398 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), 00399 LED_BLK_OFF|LED_SYNC_OFF|LED_ON); 00400 00401 netdev_link_up(skge->netdev); 00402 00403 DBG2(PFX "%s: Link is up at %d Mbps, %s duplex\n", 00404 skge->netdev->name, skge->speed, 00405 skge->duplex == DUPLEX_FULL ? "full" : "half"); 00406 }
| static void skge_link_down | ( | struct skge_port * | skge | ) | [static] |
Definition at line 408 of file skge.c.
References DBG2, skge_port::hw, LED_OFF, LNK_LED_REG, net_device::name, skge_port::netdev, netdev_link_down(), PFX, skge_port::port, SK_REG, and skge_write8().
Referenced by xm_link_down(), and yukon_link_down().
00409 { 00410 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); 00411 netdev_link_down(skge->netdev); 00412 00413 DBG2(PFX "%s: Link is down.\n", skge->netdev->name); 00414 }
| static void xm_link_down | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 417 of file skge.c.
References skge_hw::dev, net_device::dev, netdev_link_ok(), netdev_priv(), skge_link_down(), XM_IMSK, XM_IMSK_DISABLE, and xm_write16().
Referenced by bcom_check_link(), and xm_check_link().
00418 { 00419 struct net_device *dev = hw->dev[port]; 00420 struct skge_port *skge = netdev_priv(dev); 00421 00422 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); 00423 00424 if (netdev_link_ok(dev)) 00425 skge_link_down(skge); 00426 }
Definition at line 428 of file skge.c.
References ETIMEDOUT, skge_hw::phy_addr, PHY_RETRIES, skge_hw::phy_type, SK_PHY_XMAC, udelay(), XM_MMU_CMD, XM_MMU_PHY_RDY, XM_PHY_ADDR, XM_PHY_DATA, xm_read16(), and xm_write16().
Referenced by xm_phy_read().
00429 { 00430 int i; 00431 00432 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); 00433 *val = xm_read16(hw, port, XM_PHY_DATA); 00434 00435 if (hw->phy_type == SK_PHY_XMAC) 00436 goto ready; 00437 00438 for (i = 0; i < PHY_RETRIES; i++) { 00439 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) 00440 goto ready; 00441 udelay(1); 00442 } 00443 00444 return -ETIMEDOUT; 00445 ready: 00446 *val = xm_read16(hw, port, XM_PHY_DATA); 00447 00448 return 0; 00449 }
Definition at line 451 of file skge.c.
References __xm_phy_read(), DBG, skge_hw::dev, net_device::name, PFX, and u16.
Referenced by bcom_check_link(), bcom_phy_init(), bcom_phy_intr(), genesis_link_up(), and xm_check_link().
00452 { 00453 u16 v = 0; 00454 if (__xm_phy_read(hw, port, reg, &v)) 00455 DBG(PFX "%s: phy read timed out\n", 00456 hw->dev[port]->name); 00457 return v; 00458 }
| static void genesis_init | ( | struct skge_hw * | hw | ) | [static] |
Definition at line 482 of file skge.c.
References B2_BSC_CTRL, B2_BSC_INI, B3_MA_RCINI_RX1, B3_MA_RCINI_RX2, B3_MA_RCINI_TX1, B3_MA_RCINI_TX2, B3_MA_TO_CTRL, B3_MA_TOINI_RX1, B3_MA_TOINI_RX2, B3_MA_TOINI_TX1, B3_MA_TOINI_TX2, B3_PA_CTRL, B3_PA_TOINI_RX1, B3_PA_TOINI_RX2, B3_PA_TOINI_TX1, B3_PA_TOINI_TX2, BSC_START, MA_RST_CLR, PA_RST_CLR, SK_BLK_DUR, SK_FACT_53, SK_MAC_TO_53, SK_PKT_TO_MAX, skge_write16(), skge_write32(), and skge_write8().
Referenced by skge_reset().
00483 { 00484 /* set blink source counter */ 00485 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); 00486 skge_write8(hw, B2_BSC_CTRL, BSC_START); 00487 00488 /* configure mac arbiter */ 00489 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); 00490 00491 /* configure mac arbiter timeout values */ 00492 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); 00493 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); 00494 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); 00495 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); 00496 00497 skge_write8(hw, B3_MA_RCINI_RX1, 0); 00498 skge_write8(hw, B3_MA_RCINI_RX2, 0); 00499 skge_write8(hw, B3_MA_RCINI_TX1, 0); 00500 skge_write8(hw, B3_MA_RCINI_TX2, 0); 00501 00502 /* configure packet arbiter timeout */ 00503 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); 00504 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); 00505 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); 00506 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); 00507 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); 00508 }
| static void genesis_reset | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 510 of file skge.c.
References GMAC_IRQ_MSK, PHY_BCOM_INT_MASK, skge_hw::phy_type, SK_PHY_BCOM, SK_REG, skge_write8(), u32, u8, XM_GP_PORT, XM_GP_RES_STAT, XM_HSM, XM_IMSK, XM_IMSK_DISABLE, XM_MD_FRF, XM_MD_FTF, XM_MODE, xm_outhash(), xm_read32(), XM_RX_CMD, XM_TX_CMD, xm_write16(), and xm_write32().
Referenced by genesis_stop(), and skge_reset().
00511 { 00512 const u8 zero[8] = { 0 }; 00513 u32 reg; 00514 00515 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 00516 00517 /* reset the statistics module */ 00518 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); 00519 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE); 00520 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ 00521 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ 00522 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ 00523 00524 /* disable Broadcom PHY IRQ */ 00525 if (hw->phy_type == SK_PHY_BCOM) 00526 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); 00527 00528 xm_outhash(hw, port, XM_HSM, zero); 00529 00530 /* Flush TX and RX fifo */ 00531 reg = xm_read32(hw, port, XM_MODE); 00532 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF); 00533 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); 00534 }
| static void bcom_check_link | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 555 of file skge.c.
References skge_port::autoneg, AUTONEG_ENABLE, DBG, skge_hw::dev, net_device::dev, skge_port::duplex, DUPLEX_FULL, DUPLEX_HALF, FLOW_STAT_LOC_SEND, FLOW_STAT_NONE, FLOW_STAT_REM_SEND, FLOW_STAT_SYMMETRIC, skge_port::flow_status, genesis_link_up(), net_device::name, netdev_link_ok(), netdev_priv(), PFX, PHY_B_AN_RF, PHY_B_AS_AN_RES_MSK, PHY_B_AS_PAUSE_MSK, PHY_B_AS_PRR, PHY_B_AS_PRT, PHY_B_RES_1000FD, PHY_B_RES_1000HD, PHY_BCOM_AUX_STAT, PHY_BCOM_STAT, PHY_ST_AN_OVER, PHY_ST_LSYNC, PHY_XMAC_AUNE_LP, skge_port::speed, SPEED_1000, u16, xm_link_down(), and xm_phy_read().
Referenced by bcom_phy_intr(), and genesis_mac_init().
00556 { 00557 struct net_device *dev = hw->dev[port]; 00558 struct skge_port *skge = netdev_priv(dev); 00559 u16 status; 00560 00561 /* read twice because of latch */ 00562 xm_phy_read(hw, port, PHY_BCOM_STAT); 00563 status = xm_phy_read(hw, port, PHY_BCOM_STAT); 00564 00565 if ((status & PHY_ST_LSYNC) == 0) { 00566 xm_link_down(hw, port); 00567 return; 00568 } 00569 00570 if (skge->autoneg == AUTONEG_ENABLE) { 00571 u16 lpa, aux; 00572 00573 if (!(status & PHY_ST_AN_OVER)) 00574 return; 00575 00576 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); 00577 if (lpa & PHY_B_AN_RF) { 00578 DBG(PFX "%s: remote fault\n", 00579 dev->name); 00580 return; 00581 } 00582 00583 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); 00584 00585 /* Check Duplex mismatch */ 00586 switch (aux & PHY_B_AS_AN_RES_MSK) { 00587 case PHY_B_RES_1000FD: 00588 skge->duplex = DUPLEX_FULL; 00589 break; 00590 case PHY_B_RES_1000HD: 00591 skge->duplex = DUPLEX_HALF; 00592 break; 00593 default: 00594 DBG(PFX "%s: duplex mismatch\n", 00595 dev->name); 00596 return; 00597 } 00598 00599 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 00600 switch (aux & PHY_B_AS_PAUSE_MSK) { 00601 case PHY_B_AS_PAUSE_MSK: 00602 skge->flow_status = FLOW_STAT_SYMMETRIC; 00603 break; 00604 case PHY_B_AS_PRR: 00605 skge->flow_status = FLOW_STAT_REM_SEND; 00606 break; 00607 case PHY_B_AS_PRT: 00608 skge->flow_status = FLOW_STAT_LOC_SEND; 00609 break; 00610 default: 00611 skge->flow_status = FLOW_STAT_NONE; 00612 } 00613 skge->speed = SPEED_1000; 00614 } 00615 00616 if (!netdev_link_ok(dev)) 00617 genesis_link_up(skge); 00618 }
| static void bcom_phy_init | ( | struct skge_port * | skge | ) | [static] |
Definition at line 623 of file skge.c.
References ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, skge_port::advertising, ARRAY_SIZE, skge_port::autoneg, AUTONEG_ENABLE, skge_port::duplex, DUPLEX_FULL, skge_port::flow_control, skge_port::hw, PHY_AN_CSMA, PHY_B_1000C_AFD, PHY_B_1000C_AHD, PHY_B_1000C_MSE, PHY_B_1000C_RD, PHY_B_AC_DIS_PM, PHY_B_DEF_MSK, PHY_B_PEC_EN_LTR, PHY_BCOM_1000T_CTRL, PHY_BCOM_AUNE_ADV, PHY_BCOM_AUX_CTRL, PHY_BCOM_CTRL, PHY_BCOM_ID1_A1, PHY_BCOM_ID1_C0, PHY_BCOM_INT_MASK, PHY_BCOM_P_EXT_CTRL, PHY_CT_ANE, PHY_CT_DUP_MD, PHY_CT_RE_CFG, PHY_CT_SP1000, phy_pause_map, PHY_XMAC_ID1, skge_port::port, r, u16, XM_ISRC, XM_MMU_CMD, XM_MMU_NO_PRE, xm_phy_read(), xm_phy_write(), xm_read16(), and xm_write16().
Referenced by genesis_mac_init().
00624 { 00625 struct skge_hw *hw = skge->hw; 00626 int port = skge->port; 00627 unsigned int i; 00628 u16 id1, r, ext, ctl; 00629 00630 /* magic workaround patterns for Broadcom */ 00631 static const struct { 00632 u16 reg; 00633 u16 val; 00634 } A1hack[] = { 00635 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, 00636 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, 00637 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, 00638 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, 00639 }, C0hack[] = { 00640 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, 00641 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, 00642 }; 00643 00644 /* read Id from external PHY (all have the same address) */ 00645 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); 00646 00647 /* Optimize MDIO transfer by suppressing preamble. */ 00648 r = xm_read16(hw, port, XM_MMU_CMD); 00649 r |= XM_MMU_NO_PRE; 00650 xm_write16(hw, port, XM_MMU_CMD,r); 00651 00652 switch (id1) { 00653 case PHY_BCOM_ID1_C0: 00654 /* 00655 * Workaround BCOM Errata for the C0 type. 00656 * Write magic patterns to reserved registers. 00657 */ 00658 for (i = 0; i < ARRAY_SIZE(C0hack); i++) 00659 xm_phy_write(hw, port, 00660 C0hack[i].reg, C0hack[i].val); 00661 00662 break; 00663 case PHY_BCOM_ID1_A1: 00664 /* 00665 * Workaround BCOM Errata for the A1 type. 00666 * Write magic patterns to reserved registers. 00667 */ 00668 for (i = 0; i < ARRAY_SIZE(A1hack); i++) 00669 xm_phy_write(hw, port, 00670 A1hack[i].reg, A1hack[i].val); 00671 break; 00672 } 00673 00674 /* 00675 * Workaround BCOM Errata (#10523) for all BCom PHYs. 00676 * Disable Power Management after reset. 00677 */ 00678 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); 00679 r |= PHY_B_AC_DIS_PM; 00680 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); 00681 00682 /* Dummy read */ 00683 xm_read16(hw, port, XM_ISRC); 00684 00685 ext = PHY_B_PEC_EN_LTR; /* enable tx led */ 00686 ctl = PHY_CT_SP1000; /* always 1000mbit */ 00687 00688 if (skge->autoneg == AUTONEG_ENABLE) { 00689 /* 00690 * Workaround BCOM Errata #1 for the C5 type. 00691 * 1000Base-T Link Acquisition Failure in Slave Mode 00692 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register 00693 */ 00694 u16 adv = PHY_B_1000C_RD; 00695 if (skge->advertising & ADVERTISED_1000baseT_Half) 00696 adv |= PHY_B_1000C_AHD; 00697 if (skge->advertising & ADVERTISED_1000baseT_Full) 00698 adv |= PHY_B_1000C_AFD; 00699 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); 00700 00701 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG; 00702 } else { 00703 if (skge->duplex == DUPLEX_FULL) 00704 ctl |= PHY_CT_DUP_MD; 00705 /* Force to slave */ 00706 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); 00707 } 00708 00709 /* Set autonegotiation pause parameters */ 00710 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, 00711 phy_pause_map[skge->flow_control] | PHY_AN_CSMA); 00712 00713 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); 00714 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); 00715 00716 /* Use link status change interrupt */ 00717 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 00718 }
| static void xm_phy_init | ( | struct skge_port * | skge | ) | [static] |
Definition at line 720 of file skge.c.
References ADVERTISED_1000baseT_Full, ADVERTISED_1000baseT_Half, skge_port::advertising, skge_port::autoneg, AUTONEG_ENABLE, skge_port::duplex, DUPLEX_FULL, fiber_pause_map, skge_port::flow_control, skge_port::hw, PHY_CT_ANE, PHY_CT_DUP_MD, PHY_CT_RE_CFG, PHY_X_AN_FD, PHY_X_AN_HD, PHY_XMAC_AUNE_ADV, PHY_XMAC_CTRL, skge_port::port, u16, skge_port::use_xm_link_timer, and xm_phy_write().
Referenced by genesis_mac_init().
00721 { 00722 struct skge_hw *hw = skge->hw; 00723 int port = skge->port; 00724 u16 ctrl = 0; 00725 00726 if (skge->autoneg == AUTONEG_ENABLE) { 00727 if (skge->advertising & ADVERTISED_1000baseT_Half) 00728 ctrl |= PHY_X_AN_HD; 00729 if (skge->advertising & ADVERTISED_1000baseT_Full) 00730 ctrl |= PHY_X_AN_FD; 00731 00732 ctrl |= fiber_pause_map[skge->flow_control]; 00733 00734 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl); 00735 00736 /* Restart Auto-negotiation */ 00737 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG; 00738 } else { 00739 /* Set DuplexMode in Config register */ 00740 if (skge->duplex == DUPLEX_FULL) 00741 ctrl |= PHY_CT_DUP_MD; 00742 /* 00743 * Do NOT enable Auto-negotiation here. This would hold 00744 * the link down because no IDLEs are transmitted 00745 */ 00746 } 00747 00748 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl); 00749 00750 /* Poll PHY for status changes */ 00751 skge->use_xm_link_timer = 1; 00752 }
| static int xm_check_link | ( | struct net_device * | dev | ) | [static] |
Definition at line 754 of file skge.c.
References skge_port::autoneg, AUTONEG_ENABLE, DBG, skge_port::duplex, DUPLEX_FULL, DUPLEX_HALF, skge_port::flow_control, FLOW_MODE_LOC_SEND, FLOW_MODE_SYM_OR_REM, FLOW_MODE_SYMMETRIC, FLOW_STAT_LOC_SEND, FLOW_STAT_NONE, FLOW_STAT_REM_SEND, FLOW_STAT_SYMMETRIC, skge_port::flow_status, genesis_link_up(), skge_port::hw, net_device::name, netdev_link_ok(), netdev_priv(), PFX, PHY_B_AN_RF, PHY_ST_AN_OVER, PHY_ST_LSYNC, PHY_X_P_ASYM_MD, PHY_X_P_BOTH_MD, PHY_X_P_SYM_MD, PHY_X_RS_FD, PHY_X_RS_HD, PHY_X_RS_PAUSE, PHY_XMAC_AUNE_LP, PHY_XMAC_RES_ABI, PHY_XMAC_STAT, skge_port::port, skge_port::speed, SPEED_1000, u16, xm_link_down(), and xm_phy_read().
Referenced by xm_link_timer().
00755 { 00756 struct skge_port *skge = netdev_priv(dev); 00757 struct skge_hw *hw = skge->hw; 00758 int port = skge->port; 00759 u16 status; 00760 00761 /* read twice because of latch */ 00762 xm_phy_read(hw, port, PHY_XMAC_STAT); 00763 status = xm_phy_read(hw, port, PHY_XMAC_STAT); 00764 00765 if ((status & PHY_ST_LSYNC) == 0) { 00766 xm_link_down(hw, port); 00767 return 0; 00768 } 00769 00770 if (skge->autoneg == AUTONEG_ENABLE) { 00771 u16 lpa, res; 00772 00773 if (!(status & PHY_ST_AN_OVER)) 00774 return 0; 00775 00776 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP); 00777 if (lpa & PHY_B_AN_RF) { 00778 DBG(PFX "%s: remote fault\n", 00779 dev->name); 00780 return 0; 00781 } 00782 00783 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI); 00784 00785 /* Check Duplex mismatch */ 00786 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) { 00787 case PHY_X_RS_FD: 00788 skge->duplex = DUPLEX_FULL; 00789 break; 00790 case PHY_X_RS_HD: 00791 skge->duplex = DUPLEX_HALF; 00792 break; 00793 default: 00794 DBG(PFX "%s: duplex mismatch\n", 00795 dev->name); 00796 return 0; 00797 } 00798 00799 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 00800 if ((skge->flow_control == FLOW_MODE_SYMMETRIC || 00801 skge->flow_control == FLOW_MODE_SYM_OR_REM) && 00802 (lpa & PHY_X_P_SYM_MD)) 00803 skge->flow_status = FLOW_STAT_SYMMETRIC; 00804 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM && 00805 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) 00806 /* Enable PAUSE receive, disable PAUSE transmit */ 00807 skge->flow_status = FLOW_STAT_REM_SEND; 00808 else if (skge->flow_control == FLOW_MODE_LOC_SEND && 00809 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) 00810 /* Disable PAUSE receive, enable PAUSE transmit */ 00811 skge->flow_status = FLOW_STAT_LOC_SEND; 00812 else 00813 skge->flow_status = FLOW_STAT_NONE; 00814 00815 skge->speed = SPEED_1000; 00816 } 00817 00818 if (!netdev_link_ok(dev)) 00819 genesis_link_up(skge); 00820 return 1; 00821 }
| static void xm_link_timer | ( | struct skge_port * | skge | ) | [static] |
Definition at line 829 of file skge.c.
References net_device::dev, skge_port::hw, skge_port::netdev, skge_port::port, u16, xm_check_link(), XM_GP_INP_ASS, XM_GP_PORT, XM_IMSK, XM_IS_INP_ASS, XM_ISRC, xm_read16(), and xm_write16().
Referenced by skge_poll().
00830 { 00831 struct net_device *dev = skge->netdev; 00832 struct skge_hw *hw = skge->hw; 00833 int port = skge->port; 00834 int i; 00835 00836 /* 00837 * Verify that the link by checking GPIO register three times. 00838 * This pin has the signal from the link_sync pin connected to it. 00839 */ 00840 for (i = 0; i < 3; i++) { 00841 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS) 00842 return; 00843 } 00844 00845 /* Re-enable interrupt to detect link down */ 00846 if (xm_check_link(dev)) { 00847 u16 msk = xm_read16(hw, port, XM_IMSK); 00848 msk &= ~XM_IS_INP_ASS; 00849 xm_write16(hw, port, XM_IMSK, msk); 00850 xm_read16(hw, port, XM_ISRC); 00851 } 00852 }
| static void genesis_stop | ( | struct skge_port * | skge | ) | [static] |
Definition at line 1000 of file skge.c.
References B2_GP_IO, B3_PA_CTRL, genesis_reset(), GP_DIR_0, GP_DIR_2, GP_IO_0, GP_IO_2, skge_port::hw, MFF_CLR_MAC_RST, MFF_SET_MAC_RST, PA_CLR_TO_TX1, PA_CLR_TO_TX2, skge_hw::phy_type, skge_port::port, SK_PHY_XMAC, SK_REG, skge_read16(), skge_read32(), skge_write16(), skge_write32(), TX_MFF_CTRL1, u16, u32, XM_MMU_CMD, XM_MMU_ENA_RX, XM_MMU_ENA_TX, xm_read16(), and xm_write16().
Referenced by skge_down().
01001 { 01002 struct skge_hw *hw = skge->hw; 01003 int port = skge->port; 01004 unsigned retries = 1000; 01005 u16 cmd; 01006 01007 /* Disable Tx and Rx */ 01008 cmd = xm_read16(hw, port, XM_MMU_CMD); 01009 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); 01010 xm_write16(hw, port, XM_MMU_CMD, cmd); 01011 01012 genesis_reset(hw, port); 01013 01014 /* Clear Tx packet arbiter timeout IRQ */ 01015 skge_write16(hw, B3_PA_CTRL, 01016 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); 01017 01018 /* Reset the MAC */ 01019 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); 01020 do { 01021 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); 01022 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)) 01023 break; 01024 } while (--retries > 0); 01025 01026 /* For external PHYs there must be special handling */ 01027 if (hw->phy_type != SK_PHY_XMAC) { 01028 u32 reg = skge_read32(hw, B2_GP_IO); 01029 if (port == 0) { 01030 reg |= GP_DIR_0; 01031 reg &= ~GP_IO_0; 01032 } else { 01033 reg |= GP_DIR_2; 01034 reg &= ~GP_IO_2; 01035 } 01036 skge_write32(hw, B2_GP_IO, reg); 01037 skge_read32(hw, B2_GP_IO); 01038 } 01039 01040 xm_write16(hw, port, XM_MMU_CMD, 01041 xm_read16(hw, port, XM_MMU_CMD) 01042 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); 01043 01044 xm_read16(hw, port, XM_MMU_CMD); 01045 }
| static void bcom_phy_intr | ( | struct skge_port * | skge | ) | [inline, static] |
Definition at line 1131 of file skge.c.
References bcom_check_link(), DBG, DBGIO, skge_hw::dev, skge_port::hw, net_device::name, skge_port::netdev, PFX, PHY_B_IS_AN_PR, PHY_B_IS_LST_CHANGE, PHY_B_IS_NO_HDCL, PHY_B_IS_PSE, PHY_BCOM_CTRL, PHY_BCOM_INT_STAT, PHY_CT_LOOP, skge_port::port, u16, xm_phy_read(), and xm_phy_write().
Referenced by skge_phyirq().
01132 { 01133 struct skge_hw *hw = skge->hw; 01134 int port = skge->port; 01135 u16 isrc; 01136 01137 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); 01138 DBGIO(PFX "%s: phy interrupt status 0x%x\n", 01139 skge->netdev->name, isrc); 01140 01141 if (isrc & PHY_B_IS_PSE) 01142 DBG(PFX "%s: uncorrectable pair swap error\n", 01143 hw->dev[port]->name); 01144 01145 /* Workaround BCom Errata: 01146 * enable and disable loopback mode if "NO HCD" occurs. 01147 */ 01148 if (isrc & PHY_B_IS_NO_HDCL) { 01149 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); 01150 xm_phy_write(hw, port, PHY_BCOM_CTRL, 01151 ctrl | PHY_CT_LOOP); 01152 xm_phy_write(hw, port, PHY_BCOM_CTRL, 01153 ctrl & ~PHY_CT_LOOP); 01154 } 01155 01156 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) 01157 bcom_check_link(hw, port); 01158 01159 }
Definition at line 1181 of file skge.c.
References ETIMEDOUT, GM_SMI_CT_OP_RD, GM_SMI_CT_PHY_AD, GM_SMI_CT_RD_VAL, GM_SMI_CT_REG_AD, GM_SMI_CTRL, GM_SMI_DATA, gma_read16(), gma_write16(), skge_hw::phy_addr, PHY_RETRIES, and udelay().
Referenced by gm_phy_read().
01182 { 01183 int i; 01184 01185 gma_write16(hw, port, GM_SMI_CTRL, 01186 GM_SMI_CT_PHY_AD(hw->phy_addr) 01187 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 01188 01189 for (i = 0; i < PHY_RETRIES; i++) { 01190 udelay(1); 01191 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) 01192 goto ready; 01193 } 01194 01195 return -ETIMEDOUT; 01196 ready: 01197 *val = gma_read16(hw, port, GM_SMI_DATA); 01198 return 0; 01199 }
Definition at line 1201 of file skge.c.
References __gm_phy_read(), DBG, skge_hw::dev, net_device::name, PFX, and u16.
Referenced by sky2_autoneg_done(), sky2_mac_init(), sky2_phy_init(), sky2_phy_intr(), sky2_phy_power_down(), yukon_init(), yukon_link_down(), yukon_phy_intr(), and yukon_suspend().
01202 { 01203 u16 v = 0; 01204 if (__gm_phy_read(hw, port, reg, &v)) 01205 DBG(PFX "%s: phy read timeout port %x reg %x val %x\n", 01206 hw->dev[port]->name, 01207 port, reg, v); 01208 return v; 01209 }
| static void yukon_reset | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 1299 of file skge.c.
References GM_MC_ADDR_H1, GM_MC_ADDR_H2, GM_MC_ADDR_H3, GM_MC_ADDR_H4, gm_phy_write(), GM_RX_CTRL, GM_RXCR_MCF_ENA, GM_RXCR_UCF_ENA, gma_read16(), gma_write16(), and PHY_MARV_INT_MASK.
Referenced by skge_reset(), and yukon_stop().
01300 { 01301 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ 01302 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ 01303 gma_write16(hw, port, GM_MC_ADDR_H2, 0); 01304 gma_write16(hw, port, GM_MC_ADDR_H3, 0); 01305 gma_write16(hw, port, GM_MC_ADDR_H4, 0); 01306 01307 gma_write16(hw, port, GM_RX_CTRL, 01308 gma_read16(hw, port, GM_RX_CTRL) 01309 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 01310 }
| static int is_yukon_lite_a0 | ( | struct skge_hw * | hw | ) | [static] |
Definition at line 1313 of file skge.c.
References B2_FAR, skge_hw::chip_id, CHIP_ID_YUKON, skge_read32(), skge_read8(), skge_write32(), skge_write8(), and u32.
Referenced by yukon_mac_init().
01314 { 01315 u32 reg; 01316 int ret; 01317 01318 if (hw->chip_id != CHIP_ID_YUKON) 01319 return 0; 01320 01321 reg = skge_read32(hw, B2_FAR); 01322 skge_write8(hw, B2_FAR + 3, 0xff); 01323 ret = (skge_read8(hw, B2_FAR + 3) != 0); 01324 skge_write32(hw, B2_FAR, reg); 01325 return ret; 01326 }
| static void yukon_mac_init | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 1328 of file skge.c.
References skge_port::autoneg, AUTONEG_DISABLE, B2_GP_IO, skge_hw::chip_id, CHIP_ID_YUKON_LITE, skge_hw::chip_rev, CHIP_REV_YU_LITE_A3, skge_hw::copper, DATA_BLIND_DEF, DATA_BLIND_VAL, skge_hw::dev, skge_port::duplex, DUPLEX_FULL, skge_port::flow_control, FLOW_MODE_LOC_SEND, FLOW_MODE_NONE, FLOW_MODE_SYM_OR_REM, FLOW_MODE_SYMMETRIC, GM_GP_CTRL, GM_GPCR_AU_ALL_DIS, GM_GPCR_AU_FCT_DIS, GM_GPCR_DUP_FULL, GM_GPCR_FC_RX_DIS, GM_GPCR_FC_TX_DIS, GM_GPCR_SPEED_100, GM_GPCR_SPEED_1000, GM_MIB_CNT_BASE, GM_MIB_CNT_SIZE, GM_PAR_MIB_CLR, GM_PHY_ADDR, GM_RX_CTRL, GM_RX_IRQ_MSK, GM_RXCR_CRC_DIS, GM_RXCR_MCF_ENA, GM_RXCR_UCF_ENA, GM_SERIAL_MODE, GM_SMOD_VLAN_ENA, GM_SRC_ADDR_1L, GM_SRC_ADDR_2L, GM_TR_IRQ_MSK, GM_TX_CTRL, GM_TX_FLOW_CTRL, GM_TX_IRQ_MSK, GM_TX_PARAM, gma_read16(), gma_set_addr(), gma_write16(), GMAC_CTRL, GMAC_IRQ_SRC, GMC_PAUSE_OFF, GMC_PAUSE_ON, GMC_RST_CLR, GMC_RST_SET, GMF_OPER_ON, GMF_RST_CLR, GMF_RX_F_FL_ON, GP_DIR_9, GP_IO_9, GPC_ANEG_ADV_ALL_M, GPC_DIS_FC, GPC_DIS_SLEEP, GPC_ENA_PAUSE, GPC_ENA_XC, GPC_HWCFG_GMII_COP, GPC_HWCFG_GMII_FIB, GPC_INT_POL_HI, GPC_RST_CLR, GPC_RST_SET, GPHY_CTRL, IPG_DATA_DEF, IPG_DATA_VAL, is_yukon_lite_a0(), net_device::ll_addr, netdev_priv(), RX_FF_FL_DEF_MSK, RX_GMF_CTRL_T, RX_GMF_FL_MSK, RX_GMF_FL_THR, RX_GMF_FL_THR_DEF, SK_REG, skge_read16(), skge_read32(), skge_write16(), skge_write32(), skge_write8(), skge_port::speed, SPEED_10, SPEED_100, SPEED_1000, TX_COL_DEF, TX_COL_THR, TX_GMF_CTRL_T, TX_IPG_JAM_DATA, TX_IPG_JAM_DEF, TX_JAM_IPG_DEF, TX_JAM_IPG_VAL, TX_JAM_LEN_DEF, TX_JAM_LEN_VAL, u32, u8, and yukon_init().
Referenced by skge_up().
01329 { 01330 struct skge_port *skge = netdev_priv(hw->dev[port]); 01331 int i; 01332 u32 reg; 01333 const u8 *addr = hw->dev[port]->ll_addr; 01334 01335 /* WA code for COMA mode -- set PHY reset */ 01336 if (hw->chip_id == CHIP_ID_YUKON_LITE && 01337 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 01338 reg = skge_read32(hw, B2_GP_IO); 01339 reg |= GP_DIR_9 | GP_IO_9; 01340 skge_write32(hw, B2_GP_IO, reg); 01341 } 01342 01343 /* hard reset */ 01344 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 01345 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 01346 01347 /* WA code for COMA mode -- clear PHY reset */ 01348 if (hw->chip_id == CHIP_ID_YUKON_LITE && 01349 hw->chip_rev >= CHIP_REV_YU_LITE_A3) { 01350 reg = skge_read32(hw, B2_GP_IO); 01351 reg |= GP_DIR_9; 01352 reg &= ~GP_IO_9; 01353 skge_write32(hw, B2_GP_IO, reg); 01354 } 01355 01356 /* Set hardware config mode */ 01357 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | 01358 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; 01359 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; 01360 01361 /* Clear GMC reset */ 01362 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); 01363 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); 01364 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); 01365 01366 if (skge->autoneg == AUTONEG_DISABLE) { 01367 reg = GM_GPCR_AU_ALL_DIS; 01368 gma_write16(hw, port, GM_GP_CTRL, 01369 gma_read16(hw, port, GM_GP_CTRL) | reg); 01370 01371 switch (skge->speed) { 01372 case SPEED_1000: 01373 reg &= ~GM_GPCR_SPEED_100; 01374 reg |= GM_GPCR_SPEED_1000; 01375 break; 01376 case SPEED_100: 01377 reg &= ~GM_GPCR_SPEED_1000; 01378 reg |= GM_GPCR_SPEED_100; 01379 break; 01380 case SPEED_10: 01381 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); 01382 break; 01383 } 01384 01385 if (skge->duplex == DUPLEX_FULL) 01386 reg |= GM_GPCR_DUP_FULL; 01387 } else 01388 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; 01389 01390 switch (skge->flow_control) { 01391 case FLOW_MODE_NONE: 01392 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 01393 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 01394 break; 01395 case FLOW_MODE_LOC_SEND: 01396 /* disable Rx flow-control */ 01397 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; 01398 break; 01399 case FLOW_MODE_SYMMETRIC: 01400 case FLOW_MODE_SYM_OR_REM: 01401 /* enable Tx & Rx flow-control */ 01402 break; 01403 } 01404 01405 gma_write16(hw, port, GM_GP_CTRL, reg); 01406 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); 01407 01408 yukon_init(hw, port); 01409 01410 /* MIB clear */ 01411 reg = gma_read16(hw, port, GM_PHY_ADDR); 01412 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); 01413 01414 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 01415 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); 01416 gma_write16(hw, port, GM_PHY_ADDR, reg); 01417 01418 /* transmit control */ 01419 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 01420 01421 /* receive control reg: unicast + multicast + no FCS */ 01422 gma_write16(hw, port, GM_RX_CTRL, 01423 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); 01424 01425 /* transmit flow control */ 01426 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); 01427 01428 /* transmit parameter */ 01429 gma_write16(hw, port, GM_TX_PARAM, 01430 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | 01431 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 01432 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); 01433 01434 /* configure the Serial Mode Register */ 01435 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) 01436 | GM_SMOD_VLAN_ENA 01437 | IPG_DATA_VAL(IPG_DATA_DEF); 01438 01439 gma_write16(hw, port, GM_SERIAL_MODE, reg); 01440 01441 /* physical address: used for pause frames */ 01442 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); 01443 /* virtual address for data */ 01444 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); 01445 01446 /* enable interrupt mask for counter overflows */ 01447 gma_write16(hw, port, GM_TX_IRQ_MSK, 0); 01448 gma_write16(hw, port, GM_RX_IRQ_MSK, 0); 01449 gma_write16(hw, port, GM_TR_IRQ_MSK, 0); 01450 01451 /* Initialize Mac Fifo */ 01452 01453 /* Configure Rx MAC FIFO */ 01454 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); 01455 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 01456 01457 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ 01458 if (is_yukon_lite_a0(hw)) 01459 reg &= ~GMF_RX_F_FL_ON; 01460 01461 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); 01462 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); 01463 /* 01464 * because Pause Packet Truncation in GMAC is not working 01465 * we have to increase the Flush Threshold to 64 bytes 01466 * in order to flush pause packets in Rx FIFO on Yukon-1 01467 */ 01468 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); 01469 01470 /* Configure Tx MAC FIFO */ 01471 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); 01472 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); 01473 }
| static void yukon_suspend | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 1476 of file skge.c.
References gm_phy_read(), gm_phy_write(), PHY_CT_PDOWN, PHY_CT_RESET, PHY_M_PC_POL_R_DIS, PHY_MARV_CTRL, PHY_MARV_PHY_CTRL, and u16.
Referenced by yukon_stop().
01477 { 01478 u16 ctrl; 01479 01480 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); 01481 ctrl |= PHY_M_PC_POL_R_DIS; 01482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); 01483 01484 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 01485 ctrl |= PHY_CT_RESET; 01486 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 01487 01488 /* switch IEEE compatible power down mode on */ 01489 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); 01490 ctrl |= PHY_CT_PDOWN; 01491 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); 01492 }
| static void yukon_stop | ( | struct skge_port * | skge | ) | [static] |
Definition at line 1494 of file skge.c.
References GM_GP_CTRL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gma_read16(), gma_write16(), GMAC_CTRL, GMAC_IRQ_MSK, GMC_RST_SET, GPC_RST_SET, GPHY_CTRL, skge_port::hw, skge_port::port, SK_REG, skge_write8(), yukon_reset(), and yukon_suspend().
Referenced by skge_down().
01495 { 01496 struct skge_hw *hw = skge->hw; 01497 int port = skge->port; 01498 01499 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); 01500 yukon_reset(hw, port); 01501 01502 gma_write16(hw, port, GM_GP_CTRL, 01503 gma_read16(hw, port, GM_GP_CTRL) 01504 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); 01505 gma_read16(hw, port, GM_GP_CTRL); 01506 01507 yukon_suspend(hw, port); 01508 01509 /* set GPHY Control reset */ 01510 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 01511 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); 01512 }
Definition at line 1514 of file skge.c.
References PHY_M_PS_SPEED_100, PHY_M_PS_SPEED_1000, PHY_M_PS_SPEED_MSK, SPEED_10, SPEED_100, and SPEED_1000.
Referenced by yukon_phy_intr().
01515 { 01516 switch (aux & PHY_M_PS_SPEED_MSK) { 01517 case PHY_M_PS_SPEED_1000: 01518 return SPEED_1000; 01519 case PHY_M_PS_SPEED_100: 01520 return SPEED_100; 01521 default: 01522 return SPEED_10; 01523 } 01524 }
| static void yukon_link_up | ( | struct skge_port * | skge | ) | [static] |
Definition at line 1526 of file skge.c.
References skge_port::autoneg, AUTONEG_ENABLE, skge_port::duplex, DUPLEX_FULL, GM_GP_CTRL, GM_GPCR_DUP_FULL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gm_phy_write(), gma_read16(), gma_write16(), GMAC_DEF_MSK, GMAC_IRQ_MSK, skge_port::hw, PHY_M_IS_DEF_MSK, PHY_MARV_INT_MASK, skge_port::port, SK_REG, skge_link_up(), skge_write8(), and u16.
Referenced by yukon_phy_intr().
01527 { 01528 struct skge_hw *hw = skge->hw; 01529 int port = skge->port; 01530 u16 reg; 01531 01532 /* Enable Transmit FIFO Underrun */ 01533 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); 01534 01535 reg = gma_read16(hw, port, GM_GP_CTRL); 01536 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) 01537 reg |= GM_GPCR_DUP_FULL; 01538 01539 /* enable Rx/Tx */ 01540 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 01541 gma_write16(hw, port, GM_GP_CTRL, reg); 01542 01543 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); 01544 skge_link_up(skge); 01545 }
| static void yukon_link_down | ( | struct skge_port * | skge | ) | [static] |
Definition at line 1547 of file skge.c.
References FLOW_STAT_REM_SEND, skge_port::flow_status, GM_GP_CTRL, GM_GPCR_RX_ENA, GM_GPCR_TX_ENA, gm_phy_read(), gm_phy_write(), gma_read16(), gma_write16(), skge_port::hw, PHY_M_AN_ASP, PHY_MARV_AUNE_ADV, skge_port::port, skge_link_down(), u16, and yukon_init().
Referenced by yukon_phy_intr().
01548 { 01549 struct skge_hw *hw = skge->hw; 01550 int port = skge->port; 01551 u16 ctrl; 01552 01553 ctrl = gma_read16(hw, port, GM_GP_CTRL); 01554 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 01555 gma_write16(hw, port, GM_GP_CTRL, ctrl); 01556 01557 if (skge->flow_status == FLOW_STAT_REM_SEND) { 01558 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV); 01559 ctrl |= PHY_M_AN_ASP; 01560 /* restore Asymmetric Pause bit */ 01561 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl); 01562 } 01563 01564 skge_link_down(skge); 01565 01566 yukon_init(hw, port); 01567 }
| static void yukon_phy_intr | ( | struct skge_port * | skge | ) | [static] |
Definition at line 1569 of file skge.c.
References DBG, DBGIO, skge_port::duplex, DUPLEX_FULL, DUPLEX_HALF, FLOW_STAT_LOC_SEND, FLOW_STAT_NONE, FLOW_STAT_REM_SEND, FLOW_STAT_SYMMETRIC, skge_port::flow_status, gm_phy_read(), GMAC_CTRL, GMC_PAUSE_OFF, GMC_PAUSE_ON, skge_port::hw, net_device::name, skge_port::netdev, NULL, PFX, PHY_B_1000S_MSF, PHY_M_AN_RF, PHY_M_IS_AN_COMPL, PHY_M_IS_DUP_CHANGE, PHY_M_IS_LSP_CHANGE, PHY_M_IS_LST_CHANGE, PHY_M_PS_FULL_DUP, PHY_M_PS_LINK_UP, PHY_M_PS_PAUSE_MSK, PHY_M_PS_RX_P_EN, PHY_M_PS_SPDUP_RES, PHY_M_PS_TX_P_EN, PHY_MARV_1000T_STAT, PHY_MARV_AUNE_LP, PHY_MARV_INT_STAT, PHY_MARV_PHY_STAT, skge_port::port, SK_REG, skge_write8(), skge_port::speed, SPEED_1000, u16, yukon_link_down(), yukon_link_up(), and yukon_speed().
Referenced by skge_phyirq().
01570 { 01571 struct skge_hw *hw = skge->hw; 01572 int port = skge->port; 01573 const char *reason = NULL; 01574 u16 istatus, phystat; 01575 01576 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); 01577 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); 01578 01579 DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n", 01580 skge->netdev->name, istatus, phystat); 01581 01582 if (istatus & PHY_M_IS_AN_COMPL) { 01583 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) 01584 & PHY_M_AN_RF) { 01585 reason = "remote fault"; 01586 goto failed; 01587 } 01588 01589 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { 01590 reason = "master/slave fault"; 01591 goto failed; 01592 } 01593 01594 if (!(phystat & PHY_M_PS_SPDUP_RES)) { 01595 reason = "speed/duplex"; 01596 goto failed; 01597 } 01598 01599 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) 01600 ? DUPLEX_FULL : DUPLEX_HALF; 01601 skge->speed = yukon_speed(hw, phystat); 01602 01603 /* We are using IEEE 802.3z/D5.0 Table 37-4 */ 01604 switch (phystat & PHY_M_PS_PAUSE_MSK) { 01605 case PHY_M_PS_PAUSE_MSK: 01606 skge->flow_status = FLOW_STAT_SYMMETRIC; 01607 break; 01608 case PHY_M_PS_RX_P_EN: 01609 skge->flow_status = FLOW_STAT_REM_SEND; 01610 break; 01611 case PHY_M_PS_TX_P_EN: 01612 skge->flow_status = FLOW_STAT_LOC_SEND; 01613 break; 01614 default: 01615 skge->flow_status = FLOW_STAT_NONE; 01616 } 01617 01618 if (skge->flow_status == FLOW_STAT_NONE || 01619 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) 01620 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); 01621 else 01622 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); 01623 yukon_link_up(skge); 01624 return; 01625 } 01626 01627 if (istatus & PHY_M_IS_LSP_CHANGE) 01628 skge->speed = yukon_speed(hw, phystat); 01629 01630 if (istatus & PHY_M_IS_DUP_CHANGE) 01631 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; 01632 if (istatus & PHY_M_IS_LST_CHANGE) { 01633 if (phystat & PHY_M_PS_LINK_UP) 01634 yukon_link_up(skge); 01635 else 01636 yukon_link_down(skge); 01637 } 01638 return; 01639 failed: 01640 DBG(PFX "%s: autonegotiation failed (%s)\n", 01641 skge->netdev->name, reason); 01642 01643 /* XXX restart autonegotiation? */ 01644 }
Definition at line 1646 of file skge.c.
References Q_R1, Q_R2, RB_ADDR, RB_CTRL, RB_ENA_OP_MD, RB_ENA_STFWD, RB_END, RB_RP, RB_RST_CLR, RB_RX_LTPP, RB_RX_UTPP, RB_START, RB_WP, skge_write32(), skge_write8(), and u32.
Referenced by skge_up().
01647 { 01648 u32 end; 01649 01650 start /= 8; 01651 len /= 8; 01652 end = start + len - 1; 01653 01654 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); 01655 skge_write32(hw, RB_ADDR(q, RB_START), start); 01656 skge_write32(hw, RB_ADDR(q, RB_WP), start); 01657 skge_write32(hw, RB_ADDR(q, RB_RP), start); 01658 skge_write32(hw, RB_ADDR(q, RB_END), end); 01659 01660 if (q == Q_R1 || q == Q_R2) { 01661 /* Set thresholds on receive queue's */ 01662 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), 01663 start + (2*len)/3); 01664 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), 01665 start + (len/3)); 01666 } else { 01667 /* Enable store & forward on Tx queue's because 01668 * Tx FIFO is only 4K on Genesis and 1K on Yukon 01669 */ 01670 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); 01671 } 01672 01673 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); 01674 }
| static void skge_qset | ( | struct skge_port * | skge, | |
| u16 | q, | |||
| const struct skge_element * | e | |||
| ) | [static] |
Definition at line 1677 of file skge.c.
References B0_CTST, CS_BUS_CLOCK, CS_BUS_SLOT_SZ, CSR_CLR_RESET, skge_element::desc, skge_port::dma, skge_port::hw, skge_port::mem, Q_ADDR, Q_CSR, Q_DA_H, Q_DA_L, Q_F, skge_read16(), skge_write32(), and u32.
Referenced by skge_up().
01679 { 01680 struct skge_hw *hw = skge->hw; 01681 u32 watermark = 0x600; 01682 u64 base = skge->dma + (e->desc - skge->mem); 01683 01684 /* optimization to reduce window on 32bit/33mhz */ 01685 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) 01686 watermark /= 2; 01687 01688 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); 01689 skge_write32(hw, Q_ADDR(q, Q_F), watermark); 01690 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); 01691 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); 01692 }
| void skge_free | ( | struct net_device * | dev | ) |
Definition at line 1694 of file skge.c.
References skge_port::dma, free(), free_dma(), skge_port::mem, netdev_priv(), NULL, RING_SIZE, skge_port::rx_ring, skge_ring::start, and skge_port::tx_ring.
Referenced by skge_down(), and skge_up().
01695 { 01696 struct skge_port *skge = netdev_priv(dev); 01697 01698 free(skge->rx_ring.start); 01699 skge->rx_ring.start = NULL; 01700 01701 free(skge->tx_ring.start); 01702 skge->tx_ring.start = NULL; 01703 01704 free_dma(skge->mem, RING_SIZE); 01705 skge->mem = NULL; 01706 skge->dma = 0; 01707 }
| static void skge_rx_stop | ( | struct skge_hw * | hw, | |
| int | port | |||
| ) | [static] |
Definition at line 1784 of file skge.c.
References CSR_SET_RESET, CSR_STOP, Q_ADDR, Q_CSR, Q_R1, Q_R2, RB_ADDR, RB_CTRL, RB_DIS_OP_MD, RB_RST_SET, rxqaddr, skge_write32(), and skge_write8().
Referenced by skge_down().
01785 { 01786 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); 01787 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), 01788 RB_RST_SET|RB_DIS_OP_MD); 01789 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); 01790 }
| static int skge_tx_avail | ( | const struct skge_ring * | ring | ) | [inline, static] |
Definition at line 1858 of file skge.c.
References mb(), NUM_TX_DESC, skge_ring::to_clean, and skge_ring::to_use.
Referenced by skge_xmit_frame().
01859 { 01860 mb(); 01861 return ((ring->to_clean > ring->to_use) ? 0 : NUM_TX_DESC) 01862 + (ring->to_clean - ring->to_use) - 1; 01863 }
Definition at line 1926 of file skge.c.
References skge_hw::chip_id, CHIP_ID_GENESIS, GMR_FS_LEN_SHIFT, and XMR_FS_LEN_SHIFT.
Referenced by skge_rx_done().
01927 { 01928 if (hw->chip_id == CHIP_ID_GENESIS) 01929 return status >> XMR_FS_LEN_SHIFT; 01930 else 01931 return status >> GMR_FS_LEN_SHIFT; 01932 }
Definition at line 1934 of file skge.c.
References skge_hw::chip_id, CHIP_ID_GENESIS, GMR_FS_ANY_ERR, GMR_FS_RX_OK, XMR_FS_2L_VLAN, and XMR_FS_ERR.
Referenced by skge_rx_done().
01935 { 01936 if (hw->chip_id == CHIP_ID_GENESIS) 01937 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; 01938 else 01939 return (status & GMR_FS_ANY_ERR) || 01940 (status & GMR_FS_RX_OK) == 0; 01941 }
| static void skge_tx_done | ( | struct net_device * | dev | ) | [static] |
Definition at line 1944 of file skge.c.
References BMU_OWN, CSR_IRQ_CL_F, skge_element::desc, skge_port::hw, skge_element::iob, mb(), netdev_priv(), netdev_tx_complete(), skge_element::next, skge_port::port, Q_ADDR, Q_CSR, skge_write8(), skge_ring::to_clean, skge_ring::to_use, skge_port::tx_ring, txqaddr, and u32.
Referenced by skge_poll().
01945 { 01946 struct skge_port *skge = netdev_priv(dev); 01947 struct skge_ring *ring = &skge->tx_ring; 01948 struct skge_element *e; 01949 01950 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); 01951 01952 for (e = ring->to_clean; e != ring->to_use; e = e->next) { 01953 u32 control = ((const struct skge_tx_desc *) e->desc)->control; 01954 01955 if (control & BMU_OWN) 01956 break; 01957 01958 netdev_tx_complete(dev, e->iob); 01959 } 01960 skge->tx_ring.to_clean = e; 01961 01962 /* Can run lockless until we need to synchronize to restart queue. */ 01963 mb(); 01964 }
| static void skge_rx_done | ( | struct net_device * | dev | ) | [static] |
Definition at line 2008 of file skge.c.
References bad_phy_status(), BMU_BBC, BMU_OWN, skge_rx_desc::control, DBG, DBG2, skge_element::desc, EIO, skge_port::hw, skge_element::iob, iob_put, netdev_priv(), netdev_rx(), netdev_rx_err(), skge_element::next, NULL, NUM_RX_DESC, phy_length(), rmb, skge_port::rx_ring, skge_rx_refill(), skge_rx_desc::status, skge_ring::to_clean, u16, and u32.
Referenced by skge_poll().
02009 { 02010 struct skge_port *skge = netdev_priv(dev); 02011 struct skge_ring *ring = &skge->rx_ring; 02012 struct skge_rx_desc *rd; 02013 struct skge_element *e; 02014 struct io_buffer *iob; 02015 u32 control; 02016 u16 len; 02017 int i; 02018 02019 e = ring->to_clean; 02020 for (i = 0; i < NUM_RX_DESC; i++) { 02021 iob = e->iob; 02022 rd = e->desc; 02023 02024 rmb(); 02025 control = rd->control; 02026 02027 if ((control & BMU_OWN)) 02028 break; 02029 02030 if (!iob) 02031 continue; 02032 02033 len = control & BMU_BBC; 02034 02035 /* catch RX errors */ 02036 if ((bad_phy_status(skge->hw, rd->status)) || 02037 (phy_length(skge->hw, rd->status) != len)) { 02038 /* report receive errors */ 02039 DBG("rx error\n"); 02040 netdev_rx_err(dev, iob, -EIO); 02041 } else { 02042 DBG2("received packet, len %d\n", len); 02043 iob_put(iob, len); 02044 netdev_rx(dev, iob); 02045 } 02046 02047 /* io_buffer passed to core, make sure we don't reuse it */ 02048 e->iob = NULL; 02049 02050 e = e->next; 02051 } 02052 skge_rx_refill(dev); 02053 }
| static const char* skge_board_name | ( | const struct skge_hw * | hw | ) | [static] |
Definition at line 2115 of file skge.c.
References ARRAY_SIZE, skge_hw::chip_id, skge_chips, and snprintf().
Referenced by skge_probe().
02116 { 02117 unsigned int i; 02118 static char buf[16]; 02119 02120 for (i = 0; i < ARRAY_SIZE(skge_chips); i++) 02121 if (skge_chips[i].id == hw->chip_id) 02122 return skge_chips[i].name; 02123 02124 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); 02125 return buf; 02126 }
| static int skge_reset | ( | struct skge_hw * | hw | ) | [static] |
Definition at line 2133 of file skge.c.
References B0_CTST, B0_HWE_IMSK, B0_HWE_ISRC, B0_IMSK, B0_ISRC, B0_LED, B0_POWER_CTRL, B2_CHIP_ID, B2_E_0, B2_E_1, B2_IRQM_CTRL, B2_IRQM_INI, B2_IRQM_MSK, B2_MAC_CFG, B2_PMD_TYP, B2_TI_CTRL, B2_TST_CTRL1, B2_TST_CTRL2, B3_RI_CTRL, B3_RI_RTO_R1, B3_RI_RTO_R2, B3_RI_RTO_XA1, B3_RI_RTO_XA2, B3_RI_RTO_XS1, B3_RI_RTO_XS2, B3_RI_WTO_R1, B3_RI_WTO_R2, B3_RI_WTO_XA1, B3_RI_WTO_XA2, B3_RI_WTO_XS1, B3_RI_WTO_XS2, CFG_CHIP_R_MSK, CFG_SNG_MAC, skge_hw::chip_id, CHIP_ID_GENESIS, CHIP_ID_YUKON, CHIP_ID_YUKON_LITE, CHIP_ID_YUKON_LP, skge_hw::chip_rev, skge_hw::copper, CS_CLK_RUN_ENA, CS_CLK_RUN_HOT, CS_CLK_RUN_RST, CS_MRST_CLR, CS_RST_CLR, CS_RST_SET, DBG, EOPNOTSUPP, genesis_init(), genesis_reset(), GMAC_LINK_CTRL, GMLC_RST_CLR, GMLC_RST_SET, skge_hw::intr_mask, IS_ERR_MSK, IS_EXT_REG, IS_HW_ERR, IS_IRQ_SENSOR, IS_XA1_F, IS_XA2_F, LED_STAT_ON, PC_VAUX_ENA, PC_VAUX_OFF, PC_VCC_ENA, PC_VCC_ON, PCI_DEV_REG1, PCI_PHY_COMA, pci_read_config_dword(), pci_read_config_word(), PCI_STATUS, PCI_STATUS_ERROR_BITS, pci_write_config_dword(), pci_write_config_word(), skge_hw::pdev, PFX, skge_hw::phy_addr, PHY_ADDR_BCOM, PHY_ADDR_MARV, PHY_ADDR_XMAC, skge_hw::phy_type, skge_hw::ports, skge_hw::ram_offset, skge_hw::ram_size, RI_RST_CLR, SK_PHY_BCOM, SK_PHY_MARV_COPPER, SK_PHY_XMAC, SK_REG, SK_RI_TO_53, skge_read16(), skge_read32(), skge_read8(), skge_usecs2clk(), skge_write16(), skge_write32(), skge_write8(), TIM_CLR_IRQ, TIM_START, TIM_STOP, TST_CFG_WRITE_OFF, TST_CFG_WRITE_ON, TXA_CTRL, TXA_ENA_ARB, u16, u32, u8, and yukon_reset().
Referenced by skge_probe().
02134 { 02135 u32 reg; 02136 u16 ctst, pci_status; 02137 u8 t8, mac_cfg, pmd_type; 02138 int i; 02139 02140 ctst = skge_read16(hw, B0_CTST); 02141 02142 /* do a SW reset */ 02143 skge_write8(hw, B0_CTST, CS_RST_SET); 02144 skge_write8(hw, B0_CTST, CS_RST_CLR); 02145 02146 /* clear PCI errors, if any */ 02147 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 02148 skge_write8(hw, B2_TST_CTRL2, 0); 02149 02150 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); 02151 pci_write_config_word(hw->pdev, PCI_STATUS, 02152 pci_status | PCI_STATUS_ERROR_BITS); 02153 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 02154 skge_write8(hw, B0_CTST, CS_MRST_CLR); 02155 02156 /* restore CLK_RUN bits (for Yukon-Lite) */ 02157 skge_write16(hw, B0_CTST, 02158 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); 02159 02160 hw->chip_id = skge_read8(hw, B2_CHIP_ID); 02161 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf; 02162 pmd_type = skge_read8(hw, B2_PMD_TYP); 02163 hw->copper = (pmd_type == 'T' || pmd_type == '1'); 02164 02165 switch (hw->chip_id) { 02166 case CHIP_ID_GENESIS: 02167 switch (hw->phy_type) { 02168 case SK_PHY_XMAC: 02169 hw->phy_addr = PHY_ADDR_XMAC; 02170 break; 02171 case SK_PHY_BCOM: 02172 hw->phy_addr = PHY_ADDR_BCOM; 02173 break; 02174 default: 02175 DBG(PFX "unsupported phy type 0x%x\n", 02176 hw->phy_type); 02177 return -EOPNOTSUPP; 02178 } 02179 break; 02180 02181 case CHIP_ID_YUKON: 02182 case CHIP_ID_YUKON_LITE: 02183 case CHIP_ID_YUKON_LP: 02184 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') 02185 hw->copper = 1; 02186 02187 hw->phy_addr = PHY_ADDR_MARV; 02188 break; 02189 02190 default: 02191 DBG(PFX "unsupported chip type 0x%x\n", 02192 hw->chip_id); 02193 return -EOPNOTSUPP; 02194 } 02195 02196 mac_cfg = skge_read8(hw, B2_MAC_CFG); 02197 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; 02198 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; 02199 02200 /* read the adapters RAM size */ 02201 t8 = skge_read8(hw, B2_E_0); 02202 if (hw->chip_id == CHIP_ID_GENESIS) { 02203 if (t8 == 3) { 02204 /* special case: 4 x 64k x 36, offset = 0x80000 */ 02205 hw->ram_size = 0x100000; 02206 hw->ram_offset = 0x80000; 02207 } else 02208 hw->ram_size = t8 * 512; 02209 } 02210 else if (t8 == 0) 02211 hw->ram_size = 0x20000; 02212 else 02213 hw->ram_size = t8 * 4096; 02214 02215 hw->intr_mask = IS_HW_ERR; 02216 02217 /* Use PHY IRQ for all but fiber based Genesis board */ 02218 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)) 02219 hw->intr_mask |= IS_EXT_REG; 02220 02221 if (hw->chip_id == CHIP_ID_GENESIS) 02222 genesis_init(hw); 02223 else { 02224 /* switch power to VCC (WA for VAUX problem) */ 02225 skge_write8(hw, B0_POWER_CTRL, 02226 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 02227 02228 /* avoid boards with stuck Hardware error bits */ 02229 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && 02230 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { 02231 DBG(PFX "stuck hardware sensor bit\n"); 02232 hw->intr_mask &= ~IS_HW_ERR; 02233 } 02234 02235 /* Clear PHY COMA */ 02236 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); 02237 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); 02238 reg &= ~PCI_PHY_COMA; 02239 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); 02240 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 02241 02242 02243 for (i = 0; i < hw->ports; i++) { 02244 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); 02245 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); 02246 } 02247 } 02248 02249 /* turn off hardware timer (unused) */ 02250 skge_write8(hw, B2_TI_CTRL, TIM_STOP); 02251 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); 02252 skge_write8(hw, B0_LED, LED_STAT_ON); 02253 02254 /* enable the Tx Arbiters */ 02255 for (i = 0; i < hw->ports; i++) 02256 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); 02257 02258 /* Initialize ram interface */ 02259 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); 02260 02261 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); 02262 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); 02263 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); 02264 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); 02265 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); 02266 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); 02267 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); 02268 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); 02269 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); 02270 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); 02271 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); 02272 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); 02273 02274 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); 02275 02276 /* Set interrupt moderation for Transmit only 02277 * Receive interrupts avoided by NAPI 02278 */ 02279 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); 02280 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); 02281 skge_write32(hw, B2_IRQM_CTRL, TIM_START); 02282 02283 skge_write32(hw, B0_IMSK, hw->intr_mask); 02284 02285 for (i = 0; i < hw->ports; i++) { 02286 if (hw->chip_id == CHIP_ID_GENESIS) 02287 genesis_reset(hw, i); 02288 else 02289 yukon_reset(hw, i); 02290 } 02291 02292 return 0; 02293 }
| static struct net_device* skge_devinit | ( | struct skge_hw * | hw, | |
| int | port, | |||
| int highmem | __unused | |||
| ) | [static, read] |
Definition at line 2296 of file skge.c.
References skge_port::advertising, alloc_etherdev(), skge_port::autoneg, AUTONEG_ENABLE, B2_MAC_1, DBG, skge_hw::dev, pci_device::dev, net_device::dev, skge_port::duplex, ETH_ALEN, skge_port::flow_control, FLOW_MODE_SYM_OR_REM, skge_port::hw, net_device::hw_addr, memcpy, skge_port::netdev, netdev_link_down(), netdev_priv(), NULL, skge_hw::pdev, PFX, skge_port::port, skge_hw::regs, skge_supported_modes(), and skge_port::speed.
Referenced by skge_probe().
02298 { 02299 struct skge_port *skge; 02300 struct net_device *dev = alloc_etherdev(sizeof(*skge)); 02301 02302 if (!dev) { 02303 DBG(PFX "etherdev alloc failed\n"); 02304 return NULL; 02305 } 02306 02307 dev->dev = &hw->pdev->dev; 02308 02309 skge = netdev_priv(dev); 02310 skge->netdev = dev; 02311 skge->hw = hw; 02312 02313 /* Auto speed and flow control */ 02314 skge->autoneg = AUTONEG_ENABLE; 02315 skge->flow_control = FLOW_MODE_SYM_OR_REM; 02316 skge->duplex = -1; 02317 skge->speed = -1; 02318 skge->advertising = skge_supported_modes(hw); 02319 02320 hw->dev[port] = dev; 02321 02322 skge->port = port; 02323 02324 /* read the mac address */ 02325 memcpy(dev->hw_addr, (void *) (hw->regs + B2_MAC_1 + port*8), ETH_ALEN); 02326 02327 /* device is off until link detection */ 02328 netdev_link_down(dev); 02329 02330 return dev; 02331 }
| static void skge_show_addr | ( | struct net_device * | dev | ) | [static] |
Definition at line 2333 of file skge.c.
References DBG2, net_device::name, netdev_addr(), and PFX.
Referenced by skge_probe().
02334 { 02335 DBG2(PFX "%s: addr %s\n", 02336 dev->name, netdev_addr(dev)); 02337 }
| static int skge_probe | ( | struct pci_device * | pdev, | |
| const struct pci_device_id *ent | __unused | |||
| ) | [static] |
Definition at line 2339 of file skge.c.
References adjust_pci_device(), B0_LED, skge_hw::chip_rev, DBG, skge_hw::dev, net_device::dev, ENOMEM, free(), pci_device::ioaddr, ioremap(), iounmap(), pci_device::irq, LED_STAT_OFF, netdev_init(), netdev_nullify(), netdev_put(), NULL, pci_bar_start(), PCI_BASE_ADDRESS_0, pci_set_drvdata(), skge_hw::pdev, PFX, skge_hw::ports, register_netdev(), skge_hw::regs, skge_board_name(), skge_devinit(), SKGE_REG_SIZE, skge_reset(), skge_show_addr(), skge_write16(), u32, and zalloc().
02341 { 02342 struct net_device *dev, *dev1; 02343 struct skge_hw *hw; 02344 int err, using_dac = 0; 02345 02346 adjust_pci_device(pdev); 02347 02348 err = -ENOMEM; 02349 hw = zalloc(sizeof(*hw)); 02350 if (!hw) { 02351 DBG(PFX "cannot allocate hardware struct\n"); 02352 goto err_out_free_regions; 02353 } 02354 02355 hw->pdev = pdev; 02356 02357 hw->regs = (u32)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0), 02358 SKGE_REG_SIZE); 02359 if (!hw->regs) { 02360 DBG(PFX "cannot map device registers\n"); 02361 goto err_out_free_hw; 02362 } 02363 02364 err = skge_reset(hw); 02365 if (err) 02366 goto err_out_iounmap; 02367 02368 DBG(PFX " addr 0x%llx irq %d chip %s rev %d\n", 02369 (unsigned long long)pdev->ioaddr, pdev->irq, 02370 skge_board_name(hw), hw->chip_rev); 02371 02372 dev = skge_devinit(hw, 0, using_dac); 02373 if (!dev) 02374 goto err_out_led_off; 02375 02376 netdev_init ( dev, &skge_operations ); 02377 02378 err = register_netdev(dev); 02379 if (err) { 02380 DBG(PFX "cannot register net device\n"); 02381 goto err_out_free_netdev; 02382 } 02383 02384 skge_show_addr(dev); 02385 02386 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { 02387 if (register_netdev(dev1) == 0) 02388 skge_show_addr(dev1); 02389 else { 02390 /* Failure to register second port need not be fatal */ 02391 DBG(PFX "register of second port failed\n"); 02392 hw->dev[1] = NULL; 02393 netdev_nullify(dev1); 02394 netdev_put(dev1); 02395 } 02396 } 02397 pci_set_drvdata(pdev, hw); 02398 02399 return 0; 02400 02401 err_out_free_netdev: 02402 netdev_nullify(dev); 02403 netdev_put(dev); 02404 err_out_led_off: 02405 skge_write16(hw, B0_LED, LED_STAT_OFF); 02406 err_out_iounmap: 02407 iounmap((void*)hw->regs); 02408 err_out_free_hw: 02409 free(hw); 02410 err_out_free_regions: 02411 pci_set_drvdata(pdev, NULL); 02412 return err; 02413 }
| static void skge_remove | ( | struct pci_device * | pdev | ) | [static] |
Definition at line 2415 of file skge.c.
References B0_CTST, B0_IMSK, B0_LED, CS_RST_SET, skge_hw::dev, free(), skge_hw::intr_mask, iounmap(), LED_STAT_OFF, netdev_nullify(), netdev_put(), NULL, pci_get_drvdata(), pci_set_drvdata(), skge_hw::regs, skge_read32(), skge_write16(), skge_write32(), skge_write8(), and unregister_netdev().
02416 { 02417 struct skge_hw *hw = pci_get_drvdata(pdev); 02418 struct net_device *dev0, *dev1; 02419 02420 if (!hw) 02421 return; 02422 02423 if ((dev1 = hw->dev[1])) 02424 unregister_netdev(dev1); 02425 dev0 = hw->dev[0]; 02426 unregister_netdev(dev0); 02427 02428 hw->intr_mask = 0; 02429 skge_write32(hw, B0_IMSK, 0); 02430 skge_read32(hw, B0_IMSK); 02431 02432 skge_write16(hw, B0_LED, LED_STAT_OFF); 02433 skge_write8(hw, B0_CTST, CS_RST_SET); 02434 02435 if (dev1) { 02436 netdev_nullify(dev1); 02437 netdev_put(dev1); 02438 } 02439 netdev_nullify(dev0); 02440 netdev_put(dev0); 02441 02442 iounmap((void*)hw->regs); 02443 free(hw); 02444 pci_set_drvdata(pdev, NULL); 02445 }
struct pci_device_id skge_id_table[] [static] |
Initial value:
{
PCI_ROM(0x10b7, 0x1700, "3C940", "3COM 3C940", 0),
PCI_ROM(0x10b7, 0x80eb, "3C940B", "3COM 3C940", 0),
PCI_ROM(0x1148, 0x4300, "GE", "Syskonnect GE", 0),
PCI_ROM(0x1148, 0x4320, "YU", "Syskonnect YU", 0),
PCI_ROM(0x1186, 0x4C00, "DGE510T", "DLink DGE-510T", 0),
PCI_ROM(0x1186, 0x4b01, "DGE530T", "DLink DGE-530T", 0),
PCI_ROM(0x11ab, 0x4320, "id4320", "Marvell id4320", 0),
PCI_ROM(0x11ab, 0x5005, "id5005", "Marvell id5005", 0),
PCI_ROM(0x1371, 0x434e, "Gigacard", "CNET Gigacard", 0),
PCI_ROM(0x1737, 0x1064, "EG1064", "Linksys EG1064", 0),
}
struct net_device_operations skge_operations [static] |
Initial value:
{
.open = skge_up,
.close = skge_down,
.transmit = skge_xmit_frame,
.poll = skge_poll,
.irq = skge_net_irq
}
const int txqaddr[] = { Q_XA1, Q_XA2 } [static] |
Definition at line 84 of file skge.c.
Referenced by skge_down(), skge_tx_done(), skge_up(), skge_xmit_frame(), sky2_down(), sky2_hw_error(), sky2_up(), and sky2_xmit_frame().
const int rxqaddr[] = { Q_R1, Q_R2 } [static] |
Definition at line 85 of file skge.c.
Referenced by rx_set_checksum(), skge_poll(), skge_rx_stop(), skge_up(), sky2_hw_error(), sky2_rx_start(), sky2_rx_stop(), and sky2_up().
const u16 phy_pause_map[] [static] |
Initial value:
{
[FLOW_MODE_NONE] = 0,
[FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
[FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
[FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
}
Definition at line 538 of file skge.c.
Referenced by bcom_phy_init(), and yukon_init().
const u16 fiber_pause_map[] [static] |
Initial value:
{
[FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
[FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
[FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
[FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
}
Definition at line 546 of file skge.c.
Referenced by xm_phy_init(), and yukon_init().
const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 } [static] |
Definition at line 2106 of file skge.c.
Referenced by eepro_probe1(), eisa_probe(), isapnp_probe(), mca_probe(), pci_find_capability(), pci_probe(), and vring_get_buf().
struct { ... } skge_chips[] [static] |
Referenced by skge_board_name().
| struct pci_driver skge_driver __pci_driver |
Initial value:
{
.ids = skge_id_table,
.id_count = ( sizeof (skge_id_table) / sizeof (skge_id_table[0]) ),
.probe = skge_probe,
.remove = skge_remove
}
1.5.7.1