reg.h File Reference

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Defines

#define AR5K_NOQCU_TXDP0   0x0000

#define AR5K_NOQCU_TXDP1   0x0004

#define AR5K_CR   0x0008

#define AR5K_CR_TXE0   0x00000001

#define AR5K_CR_TXE1   0x00000002

#define AR5K_CR_RXE   0x00000004

#define AR5K_CR_TXD0   0x00000008

#define AR5K_CR_TXD1   0x00000010

#define AR5K_CR_RXD   0x00000020

#define AR5K_CR_SWI   0x00000040

#define AR5K_RXDP   0x000c

#define AR5K_CFG   0x0014

#define AR5K_CFG_SWTD   0x00000001

#define AR5K_CFG_SWTB   0x00000002

#define AR5K_CFG_SWRD   0x00000004

#define AR5K_CFG_SWRB   0x00000008

#define AR5K_CFG_SWRG   0x00000010

#define AR5K_CFG_IBSS   0x00000020

#define AR5K_CFG_PHY_OK   0x00000100

#define AR5K_CFG_EEBS   0x00000200

#define AR5K_CFG_CLKGD   0x00000400

#define AR5K_CFG_TXCNT   0x00007800

#define AR5K_CFG_TXCNT_S   11

#define AR5K_CFG_TXFSTAT   0x00008000

#define AR5K_CFG_TXFSTRT   0x00010000

#define AR5K_CFG_PCI_THRES   0x00060000

#define AR5K_CFG_PCI_THRES_S   17

#define AR5K_IER   0x0024

#define AR5K_IER_DISABLE   0x00000000

#define AR5K_IER_ENABLE   0x00000001

#define AR5K_BCR   0x0028

#define AR5K_BCR_AP   0x00000000

#define AR5K_BCR_ADHOC   0x00000001

#define AR5K_BCR_BDMAE   0x00000002

#define AR5K_BCR_TQ1FV   0x00000004

#define AR5K_BCR_TQ1V   0x00000008

#define AR5K_BCR_BCGET   0x00000010

#define AR5K_RTSD0   0x0028

#define AR5K_RTSD0_6   0x000000ff

#define AR5K_RTSD0_6_S   0

#define AR5K_RTSD0_9   0x0000ff00

#define AR5K_RTSD0_9_S   8

#define AR5K_RTSD0_12   0x00ff0000

#define AR5K_RTSD0_12_S   16

#define AR5K_RTSD0_18   0xff000000

#define AR5K_RTSD0_18_S   24

#define AR5K_BSR   0x002c

#define AR5K_BSR_BDLYSW   0x00000001

#define AR5K_BSR_BDLYDMA   0x00000002

#define AR5K_BSR_TXQ1F   0x00000004

#define AR5K_BSR_ATIMDLY   0x00000008

#define AR5K_BSR_SNPADHOC   0x00000100

#define AR5K_BSR_SNPBDMAE   0x00000200

#define AR5K_BSR_SNPTQ1FV   0x00000400

#define AR5K_BSR_SNPTQ1V   0x00000800

#define AR5K_BSR_SNAPSHOTSVALID   0x00001000

#define AR5K_BSR_SWBA_CNT   0x00ff0000

#define AR5K_RTSD1   0x002c

#define AR5K_RTSD1_24   0x000000ff

#define AR5K_RTSD1_24_S   0

#define AR5K_RTSD1_36   0x0000ff00

#define AR5K_RTSD1_36_S   8

#define AR5K_RTSD1_48   0x00ff0000

#define AR5K_RTSD1_48_S   16

#define AR5K_RTSD1_54   0xff000000

#define AR5K_RTSD1_54_S   24

#define AR5K_TXCFG   0x0030

#define AR5K_TXCFG_SDMAMR   0x00000007

#define AR5K_TXCFG_SDMAMR_S   0

#define AR5K_TXCFG_B_MODE   0x00000008

#define AR5K_TXCFG_TXFSTP   0x00000008

#define AR5K_TXCFG_TXFULL   0x000003f0

#define AR5K_TXCFG_TXFULL_S   4

#define AR5K_TXCFG_TXFULL_0B   0x00000000

#define AR5K_TXCFG_TXFULL_64B   0x00000010

#define AR5K_TXCFG_TXFULL_128B   0x00000020

#define AR5K_TXCFG_TXFULL_192B   0x00000030

#define AR5K_TXCFG_TXFULL_256B   0x00000040

#define AR5K_TXCFG_TXCONT_EN   0x00000080

#define AR5K_TXCFG_DMASIZE   0x00000100

#define AR5K_TXCFG_JUMBO_DESC_EN   0x00000400

#define AR5K_TXCFG_ADHOC_BCN_ATIM   0x00000800

#define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS   0x00001000

#define AR5K_TXCFG_RTSRND   0x00001000

#define AR5K_TXCFG_FRMPAD_DIS   0x00002000

#define AR5K_TXCFG_RDY_CBR_DIS   0x00004000

#define AR5K_TXCFG_JUMBO_FRM_MODE   0x00008000

#define AR5K_TXCFG_DCU_DBL_BUF_DIS   0x00008000

#define AR5K_TXCFG_DCU_CACHING_DIS   0x00010000

#define AR5K_RXCFG   0x0034

#define AR5K_RXCFG_SDMAMW   0x00000007

#define AR5K_RXCFG_SDMAMW_S   0

#define AR5K_RXCFG_ZLFDMA   0x00000008

#define AR5K_RXCFG_DEF_ANTENNA   0x00000010

#define AR5K_RXCFG_JUMBO_RXE   0x00000020

#define AR5K_RXCFG_JUMBO_WRAP   0x00000040

#define AR5K_RXCFG_SLE_ENTRY   0x00000080

#define AR5K_RXJLA   0x0038

#define AR5K_MIBC   0x0040

#define AR5K_MIBC_COW   0x00000001

#define AR5K_MIBC_FMC   0x00000002

#define AR5K_MIBC_CMC   0x00000004

#define AR5K_MIBC_MCS   0x00000008

#define AR5K_TOPS   0x0044

#define AR5K_TOPS_M   0x0000ffff

#define AR5K_RXNOFRM   0x0048

#define AR5K_RXNOFRM_M   0x000003ff

#define AR5K_TXNOFRM   0x004c

#define AR5K_TXNOFRM_M   0x000003ff

#define AR5K_TXNOFRM_QCU   0x000ffc00

#define AR5K_TXNOFRM_QCU_S   10

#define AR5K_RPGTO   0x0050

#define AR5K_RPGTO_M   0x000003ff

#define AR5K_RFCNT   0x0054

#define AR5K_RFCNT_M   0x0000001f

#define AR5K_RFCNT_RFCL   0x0000000f

#define AR5K_MISC   0x0058

#define AR5K_MISC_DMA_OBS_M   0x000001e0

#define AR5K_MISC_DMA_OBS_S   5

#define AR5K_MISC_MISC_OBS_M   0x00000e00

#define AR5K_MISC_MISC_OBS_S   9

#define AR5K_MISC_MAC_OBS_LSB_M   0x00007000

#define AR5K_MISC_MAC_OBS_LSB_S   12

#define AR5K_MISC_MAC_OBS_MSB_M   0x00038000

#define AR5K_MISC_MAC_OBS_MSB_S   15

#define AR5K_MISC_LED_DECAY   0x001c0000

#define AR5K_MISC_LED_BLINK   0x00e00000

#define AR5K_QCUDCU_CLKGT   0x005c

#define AR5K_QCUDCU_CLKGT_QCU   0x0000ffff

#define AR5K_QCUDCU_CLKGT_DCU   0x07ff0000

#define AR5K_ISR   0x001c

#define AR5K_PISR   0x0080

#define AR5K_ISR_RXOK   0x00000001

#define AR5K_ISR_RXDESC   0x00000002

#define AR5K_ISR_RXERR   0x00000004

#define AR5K_ISR_RXNOFRM   0x00000008

#define AR5K_ISR_RXEOL   0x00000010

#define AR5K_ISR_RXORN   0x00000020

#define AR5K_ISR_TXOK   0x00000040

#define AR5K_ISR_TXDESC   0x00000080

#define AR5K_ISR_TXERR   0x00000100

#define AR5K_ISR_TXNOFRM   0x00000200

#define AR5K_ISR_TXEOL   0x00000400

#define AR5K_ISR_TXURN   0x00000800

#define AR5K_ISR_MIB   0x00001000

#define AR5K_ISR_SWI   0x00002000

#define AR5K_ISR_RXPHY   0x00004000

#define AR5K_ISR_RXKCM   0x00008000

#define AR5K_ISR_SWBA   0x00010000

#define AR5K_ISR_BRSSI   0x00020000

#define AR5K_ISR_BMISS   0x00040000

#define AR5K_ISR_HIUERR   0x00080000

#define AR5K_ISR_BNR   0x00100000

#define AR5K_ISR_MCABT   0x00100000

#define AR5K_ISR_RXCHIRP   0x00200000

#define AR5K_ISR_SSERR   0x00200000

#define AR5K_ISR_DPERR   0x00400000

#define AR5K_ISR_RXDOPPLER   0x00400000

#define AR5K_ISR_TIM   0x00800000

#define AR5K_ISR_BCNMISC   0x00800000

#define AR5K_ISR_GPIO   0x01000000

#define AR5K_ISR_QCBRORN   0x02000000

#define AR5K_ISR_QCBRURN   0x04000000

#define AR5K_ISR_QTRIG   0x08000000

#define AR5K_SISR0   0x0084

#define AR5K_SISR0_QCU_TXOK   0x000003ff

#define AR5K_SISR0_QCU_TXOK_S   0

#define AR5K_SISR0_QCU_TXDESC   0x03ff0000

#define AR5K_SISR0_QCU_TXDESC_S   16

#define AR5K_SISR1   0x0088

#define AR5K_SISR1_QCU_TXERR   0x000003ff

#define AR5K_SISR1_QCU_TXERR_S   0

#define AR5K_SISR1_QCU_TXEOL   0x03ff0000

#define AR5K_SISR1_QCU_TXEOL_S   16

#define AR5K_SISR2   0x008c

#define AR5K_SISR2_QCU_TXURN   0x000003ff

#define AR5K_SISR2_QCU_TXURN_S   0

#define AR5K_SISR2_MCABT   0x00100000

#define AR5K_SISR2_SSERR   0x00200000

#define AR5K_SISR2_DPERR   0x00400000

#define AR5K_SISR2_TIM   0x01000000

#define AR5K_SISR2_CAB_END   0x02000000

#define AR5K_SISR2_DTIM_SYNC   0x04000000

#define AR5K_SISR2_BCN_TIMEOUT   0x08000000

#define AR5K_SISR2_CAB_TIMEOUT   0x10000000

#define AR5K_SISR2_DTIM   0x20000000

#define AR5K_SISR2_TSFOOR   0x80000000

#define AR5K_SISR3   0x0090

#define AR5K_SISR3_QCBRORN   0x000003ff

#define AR5K_SISR3_QCBRORN_S   0

#define AR5K_SISR3_QCBRURN   0x03ff0000

#define AR5K_SISR3_QCBRURN_S   16

#define AR5K_SISR4   0x0094

#define AR5K_SISR4_QTRIG   0x000003ff

#define AR5K_SISR4_QTRIG_S   0

#define AR5K_RAC_PISR   0x00c0

#define AR5K_RAC_SISR0   0x00c4

#define AR5K_RAC_SISR1   0x00c8

#define AR5K_RAC_SISR2   0x00cc

#define AR5K_RAC_SISR3   0x00d0

#define AR5K_RAC_SISR4   0x00d4

#define AR5K_IMR   0x0020

#define AR5K_PIMR   0x00a0

#define AR5K_IMR_RXOK   0x00000001

#define AR5K_IMR_RXDESC   0x00000002

#define AR5K_IMR_RXERR   0x00000004

#define AR5K_IMR_RXNOFRM   0x00000008

#define AR5K_IMR_RXEOL   0x00000010

#define AR5K_IMR_RXORN   0x00000020

#define AR5K_IMR_TXOK   0x00000040

#define AR5K_IMR_TXDESC   0x00000080

#define AR5K_IMR_TXERR   0x00000100

#define AR5K_IMR_TXNOFRM   0x00000200

#define AR5K_IMR_TXEOL   0x00000400

#define AR5K_IMR_TXURN   0x00000800

#define AR5K_IMR_MIB   0x00001000

#define AR5K_IMR_SWI   0x00002000

#define AR5K_IMR_RXPHY   0x00004000

#define AR5K_IMR_RXKCM   0x00008000

#define AR5K_IMR_SWBA   0x00010000

#define AR5K_IMR_BRSSI   0x00020000

#define AR5K_IMR_BMISS   0x00040000

#define AR5K_IMR_HIUERR   0x00080000

#define AR5K_IMR_BNR   0x00100000

#define AR5K_IMR_MCABT   0x00100000

#define AR5K_IMR_RXCHIRP   0x00200000

#define AR5K_IMR_SSERR   0x00200000

#define AR5K_IMR_DPERR   0x00400000

#define AR5K_IMR_RXDOPPLER   0x00400000

#define AR5K_IMR_TIM   0x00800000

#define AR5K_IMR_BCNMISC   0x00800000

#define AR5K_IMR_GPIO   0x01000000

#define AR5K_IMR_QCBRORN   0x02000000

#define AR5K_IMR_QCBRURN   0x04000000

#define AR5K_IMR_QTRIG   0x08000000

#define AR5K_SIMR0   0x00a4

#define AR5K_SIMR0_QCU_TXOK   0x000003ff

#define AR5K_SIMR0_QCU_TXOK_S   0

#define AR5K_SIMR0_QCU_TXDESC   0x03ff0000

#define AR5K_SIMR0_QCU_TXDESC_S   16

#define AR5K_SIMR1   0x00a8

#define AR5K_SIMR1_QCU_TXERR   0x000003ff

#define AR5K_SIMR1_QCU_TXERR_S   0

#define AR5K_SIMR1_QCU_TXEOL   0x03ff0000

#define AR5K_SIMR1_QCU_TXEOL_S   16

#define AR5K_SIMR2   0x00ac

#define AR5K_SIMR2_QCU_TXURN   0x000003ff

#define AR5K_SIMR2_QCU_TXURN_S   0

#define AR5K_SIMR2_MCABT   0x00100000

#define AR5K_SIMR2_SSERR   0x00200000

#define AR5K_SIMR2_DPERR   0x00400000

#define AR5K_SIMR2_TIM   0x01000000

#define AR5K_SIMR2_CAB_END   0x02000000

#define AR5K_SIMR2_DTIM_SYNC   0x04000000

#define AR5K_SIMR2_BCN_TIMEOUT   0x08000000

#define AR5K_SIMR2_CAB_TIMEOUT   0x10000000

#define AR5K_SIMR2_DTIM   0x20000000

#define AR5K_SIMR2_TSFOOR   0x80000000

#define AR5K_SIMR3   0x00b0

#define AR5K_SIMR3_QCBRORN   0x000003ff

#define AR5K_SIMR3_QCBRORN_S   0

#define AR5K_SIMR3_QCBRURN   0x03ff0000

#define AR5K_SIMR3_QCBRURN_S   16

#define AR5K_SIMR4   0x00b4

#define AR5K_SIMR4_QTRIG   0x000003ff

#define AR5K_SIMR4_QTRIG_S   0

#define AR5K_DCM_ADDR   0x0400

#define AR5K_DCM_DATA   0x0404

#define AR5K_WOW_PCFG   0x0410

#define AR5K_WOW_PCFG_PAT_MATCH_EN   0x00000001

#define AR5K_WOW_PCFG_LONG_FRAME_POL   0x00000002

#define AR5K_WOW_PCFG_WOBMISS   0x00000004

#define AR5K_WOW_PCFG_PAT_0_EN   0x00000100

#define AR5K_WOW_PCFG_PAT_1_EN   0x00000200

#define AR5K_WOW_PCFG_PAT_2_EN   0x00000400

#define AR5K_WOW_PCFG_PAT_3_EN   0x00000800

#define AR5K_WOW_PCFG_PAT_4_EN   0x00001000

#define AR5K_WOW_PCFG_PAT_5_EN   0x00002000

#define AR5K_WOW_PAT_IDX   0x0414

#define AR5K_WOW_PAT_DATA   0x0418

#define AR5K_WOW_PAT_DATA_0_3_V   0x00000001

#define AR5K_WOW_PAT_DATA_1_4_V   0x00000100

#define AR5K_WOW_PAT_DATA_2_5_V   0x00010000

#define AR5K_WOW_PAT_DATA_0_3_M   0x01000000

#define AR5K_WOW_PAT_DATA_1_4_M   0x04000000

#define AR5K_WOW_PAT_DATA_2_5_M   0x10000000

#define AR5K_DCCFG   0x0420

#define AR5K_DCCFG_GLOBAL_EN   0x00000001

#define AR5K_DCCFG_BYPASS_EN   0x00000002

#define AR5K_DCCFG_BCAST_EN   0x00000004

#define AR5K_DCCFG_MCAST_EN   0x00000008

#define AR5K_CCFG   0x0600

#define AR5K_CCFG_WINDOW_SIZE   0x00000007

#define AR5K_CCFG_CPC_EN   0x00000008

#define AR5K_CCFG_CCU   0x0604

#define AR5K_CCFG_CCU_CUP_EN   0x00000001

#define AR5K_CCFG_CCU_CREDIT   0x00000002

#define AR5K_CCFG_CCU_CD_THRES   0x00000080

#define AR5K_CCFG_CCU_CUP_LCNT   0x00010000

#define AR5K_CCFG_CCU_INIT   0x00100200

#define AR5K_CPC0   0x0610

#define AR5K_CPC1   0x0614

#define AR5K_CPC2   0x0618

#define AR5K_CPC3   0x061c

#define AR5K_CPCOVF   0x0620

#define AR5K_QUEUE_REG(_r, _q)   (((_q) << 2) + _r)

#define AR5K_QCU_GLOBAL_READ(_r, _q)   (AR5K_REG_READ(_r) & (1 << _q))

#define AR5K_QCU_GLOBAL_WRITE(_r, _q)   AR5K_REG_WRITE(_r, (1 << _q))

#define AR5K_QCU_TXDP_BASE   0x0800

#define AR5K_QUEUE_TXDP(_q)   AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)

#define AR5K_QCU_TXE   0x0840

#define AR5K_ENABLE_QUEUE(_q)   AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)

#define AR5K_QUEUE_ENABLED(_q)   AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)

#define AR5K_QCU_TXD   0x0880

#define AR5K_DISABLE_QUEUE(_q)   AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)

#define AR5K_QUEUE_DISABLED(_q)   AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)

#define AR5K_QCU_CBRCFG_BASE   0x08c0

#define AR5K_QCU_CBRCFG_INTVAL   0x00ffffff

#define AR5K_QCU_CBRCFG_INTVAL_S   0

#define AR5K_QCU_CBRCFG_ORN_THRES   0xff000000

#define AR5K_QCU_CBRCFG_ORN_THRES_S   24

#define AR5K_QUEUE_CBRCFG(_q)   AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)

#define AR5K_QCU_RDYTIMECFG_BASE   0x0900

#define AR5K_QCU_RDYTIMECFG_INTVAL   0x00ffffff

#define AR5K_QCU_RDYTIMECFG_INTVAL_S   0

#define AR5K_QCU_RDYTIMECFG_ENABLE   0x01000000

#define AR5K_QUEUE_RDYTIMECFG(_q)   AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)

#define AR5K_QCU_ONESHOTARM_SET   0x0940

#define AR5K_QCU_ONESHOTARM_SET_M   0x0000ffff

#define AR5K_QCU_ONESHOTARM_CLEAR   0x0980

#define AR5K_QCU_ONESHOTARM_CLEAR_M   0x0000ffff

#define AR5K_QCU_MISC_BASE   0x09c0

#define AR5K_QCU_MISC_FRSHED_M   0x0000000f

#define AR5K_QCU_MISC_FRSHED_ASAP   0

#define AR5K_QCU_MISC_FRSHED_CBR   1

#define AR5K_QCU_MISC_FRSHED_DBA_GT   2

#define AR5K_QCU_MISC_FRSHED_TIM_GT   3

#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT   4

#define AR5K_QCU_MISC_ONESHOT_ENABLE   0x00000010

#define AR5K_QCU_MISC_CBREXP_DIS   0x00000020

#define AR5K_QCU_MISC_CBREXP_BCN_DIS   0x00000040

#define AR5K_QCU_MISC_BCN_ENABLE   0x00000080

#define AR5K_QCU_MISC_CBR_THRES_ENABLE   0x00000100

#define AR5K_QCU_MISC_RDY_VEOL_POLICY   0x00000200

#define AR5K_QCU_MISC_CBR_RESET_CNT   0x00000400

#define AR5K_QCU_MISC_DCU_EARLY   0x00000800

#define AR5K_QCU_MISC_DCU_CMP_EN   0x00001000

#define AR5K_QUEUE_MISC(_q)   AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)

#define AR5K_QCU_STS_BASE   0x0a00

#define AR5K_QCU_STS_FRMPENDCNT   0x00000003

#define AR5K_QCU_STS_CBREXPCNT   0x0000ff00

#define AR5K_QUEUE_STATUS(_q)   AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)

#define AR5K_QCU_RDYTIMESHDN   0x0a40

#define AR5K_QCU_RDYTIMESHDN_M   0x000003ff

#define AR5K_QCU_CBB_SELECT   0x0b00

#define AR5K_QCU_CBB_ADDR   0x0b04

#define AR5K_QCU_CBB_ADDR_S   9

#define AR5K_QCU_CBCFG   0x0b08

#define AR5K_DCU_QCUMASK_BASE   0x1000

#define AR5K_DCU_QCUMASK_M   0x000003ff

#define AR5K_QUEUE_QCUMASK(_q)   AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)

#define AR5K_DCU_LCL_IFS_BASE   0x1040

#define AR5K_DCU_LCL_IFS_CW_MIN   0x000003ff

#define AR5K_DCU_LCL_IFS_CW_MIN_S   0

#define AR5K_DCU_LCL_IFS_CW_MAX   0x000ffc00

#define AR5K_DCU_LCL_IFS_CW_MAX_S   10

#define AR5K_DCU_LCL_IFS_AIFS   0x0ff00000

#define AR5K_DCU_LCL_IFS_AIFS_S   20

#define AR5K_DCU_LCL_IFS_AIFS_MAX   0xfc

#define AR5K_QUEUE_DFS_LOCAL_IFS(_q)   AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)

#define AR5K_DCU_RETRY_LMT_BASE   0x1080

#define AR5K_DCU_RETRY_LMT_SH_RETRY   0x0000000f

#define AR5K_DCU_RETRY_LMT_SH_RETRY_S   0

#define AR5K_DCU_RETRY_LMT_LG_RETRY   0x000000f0

#define AR5K_DCU_RETRY_LMT_LG_RETRY_S   4

#define AR5K_DCU_RETRY_LMT_SSH_RETRY   0x00003f00

#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S   8

#define AR5K_DCU_RETRY_LMT_SLG_RETRY   0x000fc000

#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S   14

#define AR5K_QUEUE_DFS_RETRY_LIMIT(_q)   AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)

#define AR5K_DCU_CHAN_TIME_BASE   0x10c0

#define AR5K_DCU_CHAN_TIME_DUR   0x000fffff

#define AR5K_DCU_CHAN_TIME_DUR_S   0

#define AR5K_DCU_CHAN_TIME_ENABLE   0x00100000

#define AR5K_QUEUE_DFS_CHANNEL_TIME(_q)   AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)

#define AR5K_DCU_MISC_BASE   0x1100

#define AR5K_DCU_MISC_BACKOFF   0x0000003f

#define AR5K_DCU_MISC_ETS_RTS_POL   0x00000040

#define AR5K_DCU_MISC_ETS_CW_POL   0x00000080

#define AR5K_DCU_MISC_FRAG_WAIT   0x00000100

#define AR5K_DCU_MISC_BACKOFF_FRAG   0x00000200

#define AR5K_DCU_MISC_HCFPOLL_ENABLE   0x00000800

#define AR5K_DCU_MISC_BACKOFF_PERSIST   0x00001000

#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE   0x00002000

#define AR5K_DCU_MISC_VIRTCOL   0x0000c000

#define AR5K_DCU_MISC_VIRTCOL_NORMAL   0

#define AR5K_DCU_MISC_VIRTCOL_IGNORE   1

#define AR5K_DCU_MISC_BCN_ENABLE   0x00010000

#define AR5K_DCU_MISC_ARBLOCK_CTL   0x00060000

#define AR5K_DCU_MISC_ARBLOCK_CTL_S   17

#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE   0

#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM   1

#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL   2

#define AR5K_DCU_MISC_ARBLOCK_IGNORE   0x00080000

#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS   0x00100000

#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS   0x00200000

#define AR5K_DCU_MISC_VIRT_COLL_POLICY   0x00400000

#define AR5K_DCU_MISC_BLOWN_IFS_POLICY   0x00800000

#define AR5K_DCU_MISC_SEQNUM_CTL   0x01000000

#define AR5K_QUEUE_DFS_MISC(_q)   AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)

#define AR5K_DCU_SEQNUM_BASE   0x1140

#define AR5K_DCU_SEQNUM_M   0x00000fff

#define AR5K_QUEUE_DCU_SEQNUM(_q)   AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)

#define AR5K_DCU_GBL_IFS_SIFS   0x1030

#define AR5K_DCU_GBL_IFS_SIFS_M   0x0000ffff

#define AR5K_DCU_GBL_IFS_SLOT   0x1070

#define AR5K_DCU_GBL_IFS_SLOT_M   0x0000ffff

#define AR5K_DCU_GBL_IFS_EIFS   0x10b0

#define AR5K_DCU_GBL_IFS_EIFS_M   0x0000ffff

#define AR5K_DCU_GBL_IFS_MISC   0x10f0

#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE   0x00000007

#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE   0x00000008

#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC   0x000003f0

#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR   0x000ffc00

#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S   10

#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY   0x00300000

#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST   0x00400000

#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST   0x00800000

#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS   0x01000000

#define AR5K_DCU_FP   0x1230

#define AR5K_DCU_FP_NOBURST_DCU_EN   0x00000001

#define AR5K_DCU_FP_NOBURST_EN   0x00000010

#define AR5K_DCU_FP_BURST_DCU_EN   0x00000020

#define AR5K_DCU_TXP   0x1270

#define AR5K_DCU_TXP_M   0x000003ff

#define AR5K_DCU_TXP_STATUS   0x00010000

#define AR5K_DCU_TX_FILTER_0_BASE   0x1038

#define AR5K_DCU_TX_FILTER_0(_n)   (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))

#define AR5K_DCU_TX_FILTER_1_BASE   0x103c

#define AR5K_DCU_TX_FILTER_1(_n)   (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))

#define AR5K_DCU_TX_FILTER_CLR   0x143c

#define AR5K_DCU_TX_FILTER_SET   0x147c

#define AR5K_RESET_CTL   0x4000

#define AR5K_RESET_CTL_PCU   0x00000001

#define AR5K_RESET_CTL_DMA   0x00000002

#define AR5K_RESET_CTL_BASEBAND   0x00000002

#define AR5K_RESET_CTL_MAC   0x00000004

#define AR5K_RESET_CTL_PHY   0x00000008

#define AR5K_RESET_CTL_PCI   0x00000010

#define AR5K_SLEEP_CTL   0x4004

#define AR5K_SLEEP_CTL_SLDUR   0x0000ffff

#define AR5K_SLEEP_CTL_SLDUR_S   0

#define AR5K_SLEEP_CTL_SLE   0x00030000

#define AR5K_SLEEP_CTL_SLE_S   16

#define AR5K_SLEEP_CTL_SLE_WAKE   0x00000000

#define AR5K_SLEEP_CTL_SLE_SLP   0x00010000

#define AR5K_SLEEP_CTL_SLE_ALLOW   0x00020000

#define AR5K_SLEEP_CTL_SLE_UNITS   0x00000008

#define AR5K_SLEEP_CTL_DUR_TIM_POL   0x00040000

#define AR5K_SLEEP_CTL_DUR_WRITE_POL   0x00080000

#define AR5K_SLEEP_CTL_SLE_POL   0x00100000

#define AR5K_INTPEND   0x4008

#define AR5K_INTPEND_M   0x00000001

#define AR5K_SFR   0x400c

#define AR5K_SFR_EN   0x00000001

#define AR5K_PCICFG   0x4010

#define AR5K_PCICFG_EEAE   0x00000001

#define AR5K_PCICFG_SLEEP_CLOCK_EN   0x00000002

#define AR5K_PCICFG_CLKRUNEN   0x00000004

#define AR5K_PCICFG_EESIZE   0x00000018

#define AR5K_PCICFG_EESIZE_S   3

#define AR5K_PCICFG_EESIZE_4K   0

#define AR5K_PCICFG_EESIZE_8K   1

#define AR5K_PCICFG_EESIZE_16K   2

#define AR5K_PCICFG_EESIZE_FAIL   3

#define AR5K_PCICFG_LED   0x00000060

#define AR5K_PCICFG_LED_NONE   0x00000000

#define AR5K_PCICFG_LED_PEND   0x00000020

#define AR5K_PCICFG_LED_ASSOC   0x00000040

#define AR5K_PCICFG_BUS_SEL   0x00000380

#define AR5K_PCICFG_CBEFIX_DIS   0x00000400

#define AR5K_PCICFG_SL_INTEN   0x00000800

#define AR5K_PCICFG_LED_BCTL   0x00001000

#define AR5K_PCICFG_RETRY_FIX   0x00001000

#define AR5K_PCICFG_SL_INPEN   0x00002000

#define AR5K_PCICFG_SPWR_DN   0x00010000

#define AR5K_PCICFG_LEDMODE   0x000e0000

#define AR5K_PCICFG_LEDMODE_PROP   0x00000000

#define AR5K_PCICFG_LEDMODE_PROM   0x00020000

#define AR5K_PCICFG_LEDMODE_PWR   0x00040000

#define AR5K_PCICFG_LEDMODE_RAND   0x00060000

#define AR5K_PCICFG_LEDBLINK   0x00700000

#define AR5K_PCICFG_LEDBLINK_S   20

#define AR5K_PCICFG_LEDSLOW   0x00800000

#define AR5K_PCICFG_LEDSTATE

#define AR5K_PCICFG_SLEEP_CLOCK_RATE   0x03000000

#define AR5K_PCICFG_SLEEP_CLOCK_RATE_S   24

#define AR5K_NUM_GPIO   6

#define AR5K_GPIOCR   0x4014

#define AR5K_GPIOCR_INT_ENA   0x00008000

#define AR5K_GPIOCR_INT_SELL   0x00000000

#define AR5K_GPIOCR_INT_SELH   0x00010000

#define AR5K_GPIOCR_IN(n)   (0 << ((n) * 2))

#define AR5K_GPIOCR_OUT0(n)   (1 << ((n) * 2))

#define AR5K_GPIOCR_OUT1(n)   (2 << ((n) * 2))

#define AR5K_GPIOCR_OUT(n)   (3 << ((n) * 2))

#define AR5K_GPIOCR_INT_SEL(n)   ((n) << 12)

#define AR5K_GPIODO   0x4018

#define AR5K_GPIODI   0x401c

#define AR5K_GPIODI_M   0x0000002f

#define AR5K_SREV   0x4020

#define AR5K_SREV_REV   0x0000000f

#define AR5K_SREV_REV_S   0

#define AR5K_SREV_VER   0x000000ff

#define AR5K_SREV_VER_S   4

#define AR5K_TXEPOST   0x4028

#define AR5K_QCU_SLEEP_MASK   0x402c

#define AR5K_5414_CBCFG   0x4068

#define AR5K_5414_CBCFG_BUF_DIS   0x10

#define AR5K_PCIE_PM_CTL   0x4068

#define AR5K_PCIE_PM_CTL_L1_WHEN_D2   0x00000001

#define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR   0x00000002

#define AR5K_PCIE_PM_CTL_L0_L0S_EN   0x00000004

#define AR5K_PCIE_PM_CTL_LDRESET_EN   0x00000008

#define AR5K_PCIE_PM_CTL_PME_EN   0x00000010

#define AR5K_PCIE_PM_CTL_AUX_PWR_DET   0x00000020

#define AR5K_PCIE_PM_CTL_PME_CLEAR   0x00000040

#define AR5K_PCIE_PM_CTL_PSM_D0   0x00000080

#define AR5K_PCIE_PM_CTL_PSM_D1   0x00000100

#define AR5K_PCIE_PM_CTL_PSM_D2   0x00000200

#define AR5K_PCIE_PM_CTL_PSM_D3   0x00000400

#define AR5K_PCIE_WAEN   0x407c

#define AR5K_PCIE_SERDES   0x4080

#define AR5K_PCIE_SERDES_RESET   0x4084

#define AR5K_EEPROM_BASE   0x6000

#define AR5K_EEPROM_DATA_5211   0x6004

#define AR5K_EEPROM_DATA_5210   0x6800

#define AR5K_EEPROM_DATA

#define AR5K_EEPROM_CMD   0x6008

#define AR5K_EEPROM_CMD_READ   0x00000001

#define AR5K_EEPROM_CMD_WRITE   0x00000002

#define AR5K_EEPROM_CMD_RESET   0x00000004

#define AR5K_EEPROM_STAT_5210   0x6c00

#define AR5K_EEPROM_STAT_5211   0x600c

#define AR5K_EEPROM_STATUS

#define AR5K_EEPROM_STAT_RDERR   0x00000001

#define AR5K_EEPROM_STAT_RDDONE   0x00000002

#define AR5K_EEPROM_STAT_WRERR   0x00000004

#define AR5K_EEPROM_STAT_WRDONE   0x00000008

#define AR5K_EEPROM_CFG   0x6010

#define AR5K_EEPROM_CFG_SIZE   0x00000003

#define AR5K_EEPROM_CFG_SIZE_AUTO   0

#define AR5K_EEPROM_CFG_SIZE_4KBIT   1

#define AR5K_EEPROM_CFG_SIZE_8KBIT   2

#define AR5K_EEPROM_CFG_SIZE_16KBIT   3

#define AR5K_EEPROM_CFG_WR_WAIT_DIS   0x00000004

#define AR5K_EEPROM_CFG_CLK_RATE   0x00000018

#define AR5K_EEPROM_CFG_CLK_RATE_S   3

#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ   0

#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ   1

#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ   2

#define AR5K_EEPROM_CFG_PROT_KEY   0x00ffff00

#define AR5K_EEPROM_CFG_PROT_KEY_S   8

#define AR5K_EEPROM_CFG_LIND_EN   0x01000000

#define AR5K_PCU_MIN   0x8000

#define AR5K_PCU_MAX   0x8fff

#define AR5K_STA_ID0   0x8000

#define AR5K_STA_ID0_ARRD_L32   0xffffffff

#define AR5K_STA_ID1   0x8004

#define AR5K_STA_ID1_ADDR_U16   0x0000ffff

#define AR5K_STA_ID1_AP   0x00010000

#define AR5K_STA_ID1_ADHOC   0x00020000

#define AR5K_STA_ID1_PWR_SV   0x00040000

#define AR5K_STA_ID1_NO_KEYSRCH   0x00080000

#define AR5K_STA_ID1_NO_PSPOLL   0x00100000

#define AR5K_STA_ID1_PCF_5211   0x00100000

#define AR5K_STA_ID1_PCF_5210   0x00200000

#define AR5K_STA_ID1_PCF

#define AR5K_STA_ID1_DEFAULT_ANTENNA   0x00200000

#define AR5K_STA_ID1_DESC_ANTENNA   0x00400000

#define AR5K_STA_ID1_RTS_DEF_ANTENNA   0x00800000

#define AR5K_STA_ID1_ACKCTS_6MB   0x01000000

#define AR5K_STA_ID1_BASE_RATE_11B   0x02000000

#define AR5K_STA_ID1_SELFGEN_DEF_ANT   0x04000000

#define AR5K_STA_ID1_CRYPT_MIC_EN   0x08000000

#define AR5K_STA_ID1_KEYSRCH_MODE   0x10000000

#define AR5K_STA_ID1_PRESERVE_SEQ_NUM   0x20000000

#define AR5K_STA_ID1_CBCIV_ENDIAN   0x40000000

#define AR5K_STA_ID1_KEYSRCH_MCAST   0x80000000

#define AR5K_BSS_ID0   0x8008

#define AR5K_BSS_ID1   0x800c

#define AR5K_BSS_ID1_AID   0xffff0000

#define AR5K_BSS_ID1_AID_S   16

#define AR5K_SLOT_TIME   0x8010

#define AR5K_TIME_OUT   0x8014

#define AR5K_TIME_OUT_ACK   0x00001fff

#define AR5K_TIME_OUT_ACK_S   0

#define AR5K_TIME_OUT_CTS   0x1fff0000

#define AR5K_TIME_OUT_CTS_S   16

#define AR5K_RSSI_THR   0x8018

#define AR5K_RSSI_THR_M   0x000000ff

#define AR5K_RSSI_THR_BMISS_5210   0x00000700

#define AR5K_RSSI_THR_BMISS_5210_S   8

#define AR5K_RSSI_THR_BMISS_5211   0x0000ff00

#define AR5K_RSSI_THR_BMISS_5211_S   8

#define AR5K_RSSI_THR_BMISS

#define AR5K_RSSI_THR_BMISS_S   8

#define AR5K_NODCU_RETRY_LMT   0x801c

#define AR5K_NODCU_RETRY_LMT_SH_RETRY   0x0000000f

#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S   0

#define AR5K_NODCU_RETRY_LMT_LG_RETRY   0x000000f0

#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S   4

#define AR5K_NODCU_RETRY_LMT_SSH_RETRY   0x00003f00

#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S   8

#define AR5K_NODCU_RETRY_LMT_SLG_RETRY   0x000fc000

#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S   14

#define AR5K_NODCU_RETRY_LMT_CW_MIN   0x3ff00000

#define AR5K_NODCU_RETRY_LMT_CW_MIN_S   20

#define AR5K_USEC_5210   0x8020

#define AR5K_USEC_5211   0x801c

#define AR5K_USEC

#define AR5K_USEC_1   0x0000007f

#define AR5K_USEC_1_S   0

#define AR5K_USEC_32   0x00003f80

#define AR5K_USEC_32_S   7

#define AR5K_USEC_TX_LATENCY_5211   0x007fc000

#define AR5K_USEC_TX_LATENCY_5211_S   14

#define AR5K_USEC_RX_LATENCY_5211   0x1f800000

#define AR5K_USEC_RX_LATENCY_5211_S   23

#define AR5K_USEC_TX_LATENCY_5210   0x000fc000

#define AR5K_USEC_TX_LATENCY_5210_S   14

#define AR5K_USEC_RX_LATENCY_5210   0x03f00000

#define AR5K_USEC_RX_LATENCY_5210_S   20

#define AR5K_BEACON_5210   0x8024

#define AR5K_BEACON_5211   0x8020

#define AR5K_BEACON

#define AR5K_BEACON_PERIOD   0x0000ffff

#define AR5K_BEACON_PERIOD_S   0

#define AR5K_BEACON_TIM   0x007f0000

#define AR5K_BEACON_TIM_S   16

#define AR5K_BEACON_ENABLE   0x00800000

#define AR5K_BEACON_RESET_TSF   0x01000000

#define AR5K_CFP_PERIOD_5210   0x8028

#define AR5K_CFP_PERIOD_5211   0x8024

#define AR5K_CFP_PERIOD

#define AR5K_TIMER0_5210   0x802c

#define AR5K_TIMER0_5211   0x8028

#define AR5K_TIMER0

#define AR5K_TIMER1_5210   0x8030

#define AR5K_TIMER1_5211   0x802c

#define AR5K_TIMER1

#define AR5K_TIMER2_5210   0x8034

#define AR5K_TIMER2_5211   0x8030

#define AR5K_TIMER2

#define AR5K_TIMER3_5210   0x8038

#define AR5K_TIMER3_5211   0x8034

#define AR5K_TIMER3

#define AR5K_IFS0   0x8040

#define AR5K_IFS0_SIFS   0x000007ff

#define AR5K_IFS0_SIFS_S   0

#define AR5K_IFS0_DIFS   0x007ff800

#define AR5K_IFS0_DIFS_S   11

#define AR5K_IFS1   0x8044

#define AR5K_IFS1_PIFS   0x00000fff

#define AR5K_IFS1_PIFS_S   0

#define AR5K_IFS1_EIFS   0x03fff000

#define AR5K_IFS1_EIFS_S   12

#define AR5K_IFS1_CS_EN   0x04000000

#define AR5K_CFP_DUR_5210   0x8048

#define AR5K_CFP_DUR_5211   0x8038

#define AR5K_CFP_DUR

#define AR5K_RX_FILTER_5210   0x804c

#define AR5K_RX_FILTER_5211   0x803c

#define AR5K_RX_FILTER

#define AR5K_RX_FILTER_UCAST   0x00000001

#define AR5K_RX_FILTER_MCAST   0x00000002

#define AR5K_RX_FILTER_BCAST   0x00000004

#define AR5K_RX_FILTER_CONTROL   0x00000008

#define AR5K_RX_FILTER_BEACON   0x00000010

#define AR5K_RX_FILTER_PROM   0x00000020

#define AR5K_RX_FILTER_XRPOLL   0x00000040

#define AR5K_RX_FILTER_PROBEREQ   0x00000080

#define AR5K_RX_FILTER_PHYERR_5212   0x00000100

#define AR5K_RX_FILTER_RADARERR_5212   0x00000200

#define AR5K_RX_FILTER_PHYERR_5211   0x00000040

#define AR5K_RX_FILTER_RADARERR_5211   0x00000080

#define AR5K_RX_FILTER_PHYERR

#define AR5K_RX_FILTER_RADARERR

#define AR5K_MCAST_FILTER0_5210   0x8050

#define AR5K_MCAST_FILTER0_5211   0x8040

#define AR5K_MCAST_FILTER0

#define AR5K_MCAST_FILTER1_5210   0x8054

#define AR5K_MCAST_FILTER1_5211   0x8044

#define AR5K_MCAST_FILTER1

#define AR5K_TX_MASK0   0x8058

#define AR5K_TX_MASK1   0x805c

#define AR5K_CLR_TMASK   0x8060

#define AR5K_TRIG_LVL   0x8064

#define AR5K_DIAG_SW_5210   0x8068

#define AR5K_DIAG_SW_5211   0x8048

#define AR5K_DIAG_SW

#define AR5K_DIAG_SW_DIS_WEP_ACK   0x00000001

#define AR5K_DIAG_SW_DIS_ACK   0x00000002

#define AR5K_DIAG_SW_DIS_CTS   0x00000004

#define AR5K_DIAG_SW_DIS_ENC   0x00000008

#define AR5K_DIAG_SW_DIS_DEC   0x00000010

#define AR5K_DIAG_SW_DIS_TX   0x00000020

#define AR5K_DIAG_SW_DIS_RX_5210   0x00000040

#define AR5K_DIAG_SW_DIS_RX_5211   0x00000020

#define AR5K_DIAG_SW_DIS_RX

#define AR5K_DIAG_SW_LOOP_BACK_5210   0x00000080

#define AR5K_DIAG_SW_LOOP_BACK_5211   0x00000040

#define AR5K_DIAG_SW_LOOP_BACK

#define AR5K_DIAG_SW_CORR_FCS_5210   0x00000100

#define AR5K_DIAG_SW_CORR_FCS_5211   0x00000080

#define AR5K_DIAG_SW_CORR_FCS

#define AR5K_DIAG_SW_CHAN_INFO_5210   0x00000200

#define AR5K_DIAG_SW_CHAN_INFO_5211   0x00000100

#define AR5K_DIAG_SW_CHAN_INFO

#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210   0x00000400

#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211   0x00000200

#define AR5K_DIAG_SW_EN_SCRAM_SEED

#define AR5K_DIAG_SW_ECO_ENABLE   0x00000400

#define AR5K_DIAG_SW_SCVRAM_SEED   0x0003f800

#define AR5K_DIAG_SW_SCRAM_SEED_M   0x0001fc00

#define AR5K_DIAG_SW_SCRAM_SEED_S   10

#define AR5K_DIAG_SW_DIS_SEQ_INC   0x00040000

#define AR5K_DIAG_SW_FRAME_NV0_5210   0x00080000

#define AR5K_DIAG_SW_FRAME_NV0_5211   0x00020000

#define AR5K_DIAG_SW_FRAME_NV0

#define AR5K_DIAG_SW_OBSPT_M   0x000c0000

#define AR5K_DIAG_SW_OBSPT_S   18

#define AR5K_DIAG_SW_RX_CLEAR_HIGH   0x0010000

#define AR5K_DIAG_SW_IGNORE_CARR_SENSE   0x0020000

#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH   0x0040000

#define AR5K_DIAG_SW_PHEAR_ME   0x0080000

#define AR5K_TSF_L32_5210   0x806c

#define AR5K_TSF_L32_5211   0x804c

#define AR5K_TSF_L32

#define AR5K_TSF_U32_5210   0x8070

#define AR5K_TSF_U32_5211   0x8050

#define AR5K_TSF_U32

#define AR5K_LAST_TSTP   0x8080

#define AR5K_ADDAC_TEST   0x8054

#define AR5K_ADDAC_TEST_TXCONT   0x00000001

#define AR5K_ADDAC_TEST_TST_MODE   0x00000002

#define AR5K_ADDAC_TEST_LOOP_EN   0x00000004

#define AR5K_ADDAC_TEST_LOOP_LEN   0x00000008

#define AR5K_ADDAC_TEST_USE_U8   0x00004000

#define AR5K_ADDAC_TEST_MSB   0x00008000

#define AR5K_ADDAC_TEST_TRIG_SEL   0x00010000

#define AR5K_ADDAC_TEST_TRIG_PTY   0x00020000

#define AR5K_ADDAC_TEST_RXCONT   0x00040000

#define AR5K_ADDAC_TEST_CAPTURE   0x00080000

#define AR5K_ADDAC_TEST_TST_ARM   0x00100000

#define AR5K_DEFAULT_ANTENNA   0x8058

#define AR5K_FRAME_CTL_QOSM   0x805c

#define AR5K_SEQ_MASK   0x8060

#define AR5K_RETRY_CNT   0x8084

#define AR5K_RETRY_CNT_SSH   0x0000003f

#define AR5K_RETRY_CNT_SLG   0x00000fc0

#define AR5K_BACKOFF   0x8088

#define AR5K_BACKOFF_CW   0x000003ff

#define AR5K_BACKOFF_CNT   0x03ff0000

#define AR5K_NAV_5210   0x808c

#define AR5K_NAV_5211   0x8084

#define AR5K_NAV

#define AR5K_RTS_OK_5210   0x8090

#define AR5K_RTS_OK_5211   0x8088

#define AR5K_RTS_OK

#define AR5K_RTS_FAIL_5210   0x8094

#define AR5K_RTS_FAIL_5211   0x808c

#define AR5K_RTS_FAIL

#define AR5K_ACK_FAIL_5210   0x8098

#define AR5K_ACK_FAIL_5211   0x8090

#define AR5K_ACK_FAIL

#define AR5K_FCS_FAIL_5210   0x809c

#define AR5K_FCS_FAIL_5211   0x8094

#define AR5K_FCS_FAIL

#define AR5K_BEACON_CNT_5210   0x80a0

#define AR5K_BEACON_CNT_5211   0x8098

#define AR5K_BEACON_CNT

#define AR5K_TPC   0x80e8

#define AR5K_TPC_ACK   0x0000003f

#define AR5K_TPC_ACK_S   0

#define AR5K_TPC_CTS   0x00003f00

#define AR5K_TPC_CTS_S   8

#define AR5K_TPC_CHIRP   0x003f0000

#define AR5K_TPC_CHIRP_S   16

#define AR5K_TPC_DOPPLER   0x0f000000

#define AR5K_TPC_DOPPLER_S   24

#define AR5K_XRMODE   0x80c0

#define AR5K_XRMODE_POLL_TYPE_M   0x0000003f

#define AR5K_XRMODE_POLL_TYPE_S   0

#define AR5K_XRMODE_POLL_SUBTYPE_M   0x0000003c

#define AR5K_XRMODE_POLL_SUBTYPE_S   2

#define AR5K_XRMODE_POLL_WAIT_ALL   0x00000080

#define AR5K_XRMODE_SIFS_DELAY   0x000fff00

#define AR5K_XRMODE_FRAME_HOLD_M   0xfff00000

#define AR5K_XRMODE_FRAME_HOLD_S   20

#define AR5K_XRDELAY   0x80c4

#define AR5K_XRDELAY_SLOT_DELAY_M   0x0000ffff

#define AR5K_XRDELAY_SLOT_DELAY_S   0

#define AR5K_XRDELAY_CHIRP_DELAY_M   0xffff0000

#define AR5K_XRDELAY_CHIRP_DELAY_S   16

#define AR5K_XRTIMEOUT   0x80c8

#define AR5K_XRTIMEOUT_CHIRP_M   0x0000ffff

#define AR5K_XRTIMEOUT_CHIRP_S   0

#define AR5K_XRTIMEOUT_POLL_M   0xffff0000

#define AR5K_XRTIMEOUT_POLL_S   16

#define AR5K_XRCHIRP   0x80cc

#define AR5K_XRCHIRP_SEND   0x00000001

#define AR5K_XRCHIRP_GAP   0xffff0000

#define AR5K_XRSTOMP   0x80d0

#define AR5K_XRSTOMP_TX   0x00000001

#define AR5K_XRSTOMP_RX   0x00000002

#define AR5K_XRSTOMP_TX_RSSI   0x00000004

#define AR5K_XRSTOMP_TX_BSSID   0x00000008

#define AR5K_XRSTOMP_DATA   0x00000010

#define AR5K_XRSTOMP_RSSI_THRES   0x0000ff00

#define AR5K_SLEEP0   0x80d4

#define AR5K_SLEEP0_NEXT_DTIM   0x0007ffff

#define AR5K_SLEEP0_NEXT_DTIM_S   0

#define AR5K_SLEEP0_ASSUME_DTIM   0x00080000

#define AR5K_SLEEP0_ENH_SLEEP_EN   0x00100000

#define AR5K_SLEEP0_CABTO   0xff000000

#define AR5K_SLEEP0_CABTO_S   24

#define AR5K_SLEEP1   0x80d8

#define AR5K_SLEEP1_NEXT_TIM   0x0007ffff

#define AR5K_SLEEP1_NEXT_TIM_S   0

#define AR5K_SLEEP1_BEACON_TO   0xff000000

#define AR5K_SLEEP1_BEACON_TO_S   24

#define AR5K_SLEEP2   0x80dc

#define AR5K_SLEEP2_TIM_PER   0x0000ffff

#define AR5K_SLEEP2_TIM_PER_S   0

#define AR5K_SLEEP2_DTIM_PER   0xffff0000

#define AR5K_SLEEP2_DTIM_PER_S   16

#define AR5K_BSS_IDM0   0x80e0

#define AR5K_BSS_IDM1   0x80e4

#define AR5K_TXPC   0x80e8

#define AR5K_TXPC_ACK_M   0x0000003f

#define AR5K_TXPC_ACK_S   0

#define AR5K_TXPC_CTS_M   0x00003f00

#define AR5K_TXPC_CTS_S   8

#define AR5K_TXPC_CHIRP_M   0x003f0000

#define AR5K_TXPC_CHIRP_S   16

#define AR5K_TXPC_DOPPLER   0x0f000000

#define AR5K_TXPC_DOPPLER_S   24

#define AR5K_PROFCNT_TX   0x80ec

#define AR5K_PROFCNT_RX   0x80f0

#define AR5K_PROFCNT_RXCLR   0x80f4

#define AR5K_PROFCNT_CYCLE   0x80f8

#define AR5K_QUIET_CTL1   0x80fc

#define AR5K_QUIET_CTL1_NEXT_QT_TSF   0x0000ffff

#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S   0

#define AR5K_QUIET_CTL1_QT_EN   0x00010000

#define AR5K_QUIET_CTL1_ACK_CTS_EN   0x00020000

#define AR5K_QUIET_CTL2   0x8100

#define AR5K_QUIET_CTL2_QT_PER   0x0000ffff

#define AR5K_QUIET_CTL2_QT_PER_S   0

#define AR5K_QUIET_CTL2_QT_DUR   0xffff0000

#define AR5K_QUIET_CTL2_QT_DUR_S   16

#define AR5K_TSF_PARM   0x8104

#define AR5K_TSF_PARM_INC   0x000000ff

#define AR5K_TSF_PARM_INC_S   0

#define AR5K_QOS_NOACK   0x8108

#define AR5K_QOS_NOACK_2BIT_VALUES   0x0000000f

#define AR5K_QOS_NOACK_2BIT_VALUES_S   0

#define AR5K_QOS_NOACK_BIT_OFFSET   0x00000070

#define AR5K_QOS_NOACK_BIT_OFFSET_S   4

#define AR5K_QOS_NOACK_BYTE_OFFSET   0x00000180

#define AR5K_QOS_NOACK_BYTE_OFFSET_S   7

#define AR5K_PHY_ERR_FIL   0x810c

#define AR5K_PHY_ERR_FIL_RADAR   0x00000020

#define AR5K_PHY_ERR_FIL_OFDM   0x00020000

#define AR5K_PHY_ERR_FIL_CCK   0x02000000

#define AR5K_XRLAT_TX   0x8110

#define AR5K_ACKSIFS   0x8114

#define AR5K_ACKSIFS_INC   0x00000000

#define AR5K_MIC_QOS_CTL   0x8118

#define AR5K_MIC_QOS_CTL_OFF(_n)   (1 << (_n * 2))

#define AR5K_MIC_QOS_CTL_MQ_EN   0x00010000

#define AR5K_MIC_QOS_SEL   0x811c

#define AR5K_MIC_QOS_SEL_OFF(_n)   (1 << (_n * 4))

#define AR5K_MISC_MODE   0x8120

#define AR5K_MISC_MODE_FBSSID_MATCH   0x00000001

#define AR5K_MISC_MODE_ACKSIFS_MEM   0x00000002

#define AR5K_MISC_MODE_COMBINED_MIC   0x00000004

#define AR5K_OFDM_FIL_CNT   0x8124

#define AR5K_CCK_FIL_CNT   0x8128

#define AR5K_PHYERR_CNT1   0x812c

#define AR5K_PHYERR_CNT1_MASK   0x8130

#define AR5K_PHYERR_CNT2   0x8134

#define AR5K_PHYERR_CNT2_MASK   0x8138

#define AR5K_TSF_THRES   0x813c

#define AR5K_RATE_ACKSIFS_BASE   0x8680

#define AR5K_RATE_ACKSIFS(_n)   (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))

#define AR5K_RATE_ACKSIFS_NORMAL   0x00000001

#define AR5K_RATE_ACKSIFS_TURBO   0x00000400

#define AR5K_RATE_DUR_BASE   0x8700

#define AR5K_RATE_DUR(_n)   (AR5K_RATE_DUR_BASE + ((_n) << 2))

#define AR5K_RATE2DB_BASE   0x87c0

#define AR5K_RATE2DB(_n)   (AR5K_RATE2DB_BASE + ((_n) << 2))

#define AR5K_DB2RATE_BASE   0x87e0

#define AR5K_DB2RATE(_n)   (AR5K_DB2RATE_BASE + ((_n) << 2))

#define AR5K_KEYTABLE_0_5210   0x9000

#define AR5K_KEYTABLE_0_5211   0x8800

#define AR5K_KEYTABLE_5210(_n)   (AR5K_KEYTABLE_0_5210 + ((_n) << 5))

#define AR5K_KEYTABLE_5211(_n)   (AR5K_KEYTABLE_0_5211 + ((_n) << 5))

#define AR5K_KEYTABLE(_n)

#define AR5K_KEYTABLE_OFF(_n, x)   (AR5K_KEYTABLE(_n) + (x << 2))

#define AR5K_KEYTABLE_TYPE(_n)   AR5K_KEYTABLE_OFF(_n, 5)

#define AR5K_KEYTABLE_TYPE_40   0x00000000

#define AR5K_KEYTABLE_TYPE_104   0x00000001

#define AR5K_KEYTABLE_TYPE_128   0x00000003

#define AR5K_KEYTABLE_TYPE_TKIP   0x00000004

#define AR5K_KEYTABLE_TYPE_AES   0x00000005

#define AR5K_KEYTABLE_TYPE_CCM   0x00000006

#define AR5K_KEYTABLE_TYPE_NULL   0x00000007

#define AR5K_KEYTABLE_ANTENNA   0x00000008

#define AR5K_KEYTABLE_MAC0(_n)   AR5K_KEYTABLE_OFF(_n, 6)

#define AR5K_KEYTABLE_MAC1(_n)   AR5K_KEYTABLE_OFF(_n, 7)

#define AR5K_KEYTABLE_VALID   0x00008000

#define AR5K_KEYTABLE_MIC_OFFSET   64

#define AR5K_KEYTABLE_SIZE_5210   64

#define AR5K_KEYTABLE_SIZE_5211   128

#define AR5K_KEYTABLE_SIZE

#define AR5K_PHY_BASE   0x9800

#define AR5K_PHY(_n)   (AR5K_PHY_BASE + ((_n) << 2))

#define AR5K_PHY_TST2   0x9800

#define AR5K_PHY_TST2_TRIG_SEL   0x00000007

#define AR5K_PHY_TST2_TRIG   0x00000010

#define AR5K_PHY_TST2_CBUS_MODE   0x00000060

#define AR5K_PHY_TST2_CLK32   0x00000400

#define AR5K_PHY_TST2_CHANCOR_DUMP_EN   0x00000800

#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP   0x00001000

#define AR5K_PHY_TST2_RFSILENT_EN   0x00002000

#define AR5K_PHY_TST2_ALT_RFDATA   0x00004000

#define AR5K_PHY_TST2_MINI_OBS_EN   0x00008000

#define AR5K_PHY_TST2_RX2_IS_RX5_INV   0x00010000

#define AR5K_PHY_TST2_SLOW_CLK160   0x00020000

#define AR5K_PHY_TST2_AGC_OBS_SEL_3   0x00040000

#define AR5K_PHY_TST2_BBB_OBS_SEL   0x00080000

#define AR5K_PHY_TST2_ADC_OBS_SEL   0x00800000

#define AR5K_PHY_TST2_RX_CLR_SEL   0x08000000

#define AR5K_PHY_TST2_FORCE_AGC_CLR   0x10000000

#define AR5K_PHY_SHIFT_2GHZ   0x00004007

#define AR5K_PHY_SHIFT_5GHZ   0x00000007

#define AR5K_PHY_TURBO   0x9804

#define AR5K_PHY_TURBO_MODE   0x00000001

#define AR5K_PHY_TURBO_SHORT   0x00000002

#define AR5K_PHY_TURBO_MIMO   0x00000004

#define AR5K_PHY_AGC   0x9808

#define AR5K_PHY_TST1   0x9808

#define AR5K_PHY_AGC_DISABLE   0x08000000

#define AR5K_PHY_TST1_TXHOLD   0x00003800

#define AR5K_PHY_TST1_TXSRC_SRC   0x00000002

#define AR5K_PHY_TST1_TXSRC_SRC_S   1

#define AR5K_PHY_TST1_TXSRC_ALT   0x00000080

#define AR5K_PHY_TST1_TXSRC_ALT_S   7

#define AR5K_PHY_TIMING_3   0x9814

#define AR5K_PHY_TIMING_3_DSC_MAN   0xfffe0000

#define AR5K_PHY_TIMING_3_DSC_MAN_S   17

#define AR5K_PHY_TIMING_3_DSC_EXP   0x0001e000

#define AR5K_PHY_TIMING_3_DSC_EXP_S   13

#define AR5K_PHY_CHIP_ID   0x9818

#define AR5K_PHY_ACT   0x981c

#define AR5K_PHY_ACT_ENABLE   0x00000001

#define AR5K_PHY_ACT_DISABLE   0x00000002

#define AR5K_PHY_RF_CTL2   0x9824

#define AR5K_PHY_RF_CTL2_TXF2TXD_START   0x0000000f

#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S   0

#define AR5K_PHY_RF_CTL3   0x9828

#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON   0x0000ff00

#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S   8

#define AR5K_PHY_ADC_CTL   0x982c

#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF   0x00000003

#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S   0

#define AR5K_PHY_ADC_CTL_PWD_DAC_OFF   0x00002000

#define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF   0x00004000

#define AR5K_PHY_ADC_CTL_PWD_ADC_OFF   0x00008000

#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON   0x00030000

#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S   16

#define AR5K_PHY_RF_CTL4   0x9834

#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON   0x00000001

#define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON   0x00000100

#define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF   0x00010000

#define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF   0x01000000

#define AR5K_PHY_PA_CTL   0x9838

#define AR5K_PHY_PA_CTL_XPA_A_HI   0x00000001

#define AR5K_PHY_PA_CTL_XPA_B_HI   0x00000002

#define AR5K_PHY_PA_CTL_XPA_A_EN   0x00000004

#define AR5K_PHY_PA_CTL_XPA_B_EN   0x00000008

#define AR5K_PHY_SETTLING   0x9844

#define AR5K_PHY_SETTLING_AGC   0x0000007f

#define AR5K_PHY_SETTLING_AGC_S   0

#define AR5K_PHY_SETTLING_SWITCH   0x00003f80

#define AR5K_PHY_SETTLING_SWITCH_S   7

#define AR5K_PHY_GAIN   0x9848

#define AR5K_PHY_GAIN_TXRX_ATTEN   0x0003f000

#define AR5K_PHY_GAIN_TXRX_ATTEN_S   12

#define AR5K_PHY_GAIN_TXRX_RF_MAX   0x007c0000

#define AR5K_PHY_GAIN_TXRX_RF_MAX_S   18

#define AR5K_PHY_GAIN_OFFSET   0x984c

#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG   0x00020000

#define AR5K_PHY_DESIRED_SIZE   0x9850

#define AR5K_PHY_DESIRED_SIZE_ADC   0x000000ff

#define AR5K_PHY_DESIRED_SIZE_ADC_S   0

#define AR5K_PHY_DESIRED_SIZE_PGA   0x0000ff00

#define AR5K_PHY_DESIRED_SIZE_PGA_S   8

#define AR5K_PHY_DESIRED_SIZE_TOT   0x0ff00000

#define AR5K_PHY_DESIRED_SIZE_TOT_S   20

#define AR5K_PHY_SIG   0x9858

#define AR5K_PHY_SIG_FIRSTEP   0x0003f000

#define AR5K_PHY_SIG_FIRSTEP_S   12

#define AR5K_PHY_SIG_FIRPWR   0x03fc0000

#define AR5K_PHY_SIG_FIRPWR_S   18

#define AR5K_PHY_AGCCOARSE   0x985c

#define AR5K_PHY_AGCCOARSE_LO   0x00007f80

#define AR5K_PHY_AGCCOARSE_LO_S   7

#define AR5K_PHY_AGCCOARSE_HI   0x003f8000

#define AR5K_PHY_AGCCOARSE_HI_S   15

#define AR5K_PHY_AGCCTL   0x9860

#define AR5K_PHY_AGCCTL_CAL   0x00000001

#define AR5K_PHY_AGCCTL_NF   0x00000002

#define AR5K_PHY_AGCCTL_NF_EN   0x00008000

#define AR5K_PHY_AGCCTL_NF_NOUPDATE   0x00020000

#define AR5K_PHY_NF   0x9864

#define AR5K_PHY_NF_M   0x000001ff

#define AR5K_PHY_NF_ACTIVE   0x00000100

#define AR5K_PHY_NF_RVAL(_n)   (((_n) >> 19) & AR5K_PHY_NF_M)

#define AR5K_PHY_NF_AVAL(_n)   (-((_n) ^ AR5K_PHY_NF_M) + 1)

#define AR5K_PHY_NF_SVAL(_n)   (((_n) & AR5K_PHY_NF_M) | (1 << 9))

#define AR5K_PHY_NF_THRESH62   0x0007f000

#define AR5K_PHY_NF_THRESH62_S   12

#define AR5K_PHY_NF_MINCCA_PWR   0x0ff80000

#define AR5K_PHY_NF_MINCCA_PWR_S   19

#define AR5K_PHY_ADCSAT   0x9868

#define AR5K_PHY_ADCSAT_ICNT   0x0001f800

#define AR5K_PHY_ADCSAT_ICNT_S   11

#define AR5K_PHY_ADCSAT_THR   0x000007e0

#define AR5K_PHY_ADCSAT_THR_S   5

#define AR5K_PHY_WEAK_OFDM_HIGH_THR   0x9868

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT   0x0000001f

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S   0

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1   0x00fe0000

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S   17

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2   0x7f000000

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S   24

#define AR5K_PHY_WEAK_OFDM_LOW_THR   0x986c

#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN   0x00000001

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT   0x00003f00

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S   8

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1   0x001fc000

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S   14

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2   0x0fe00000

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S   21

#define AR5K_PHY_SCR   0x9870

#define AR5K_PHY_SLMT   0x9874

#define AR5K_PHY_SLMT_32MHZ   0x0000007f

#define AR5K_PHY_SCAL   0x9878

#define AR5K_PHY_SCAL_32MHZ   0x0000000e

#define AR5K_PHY_SCAL_32MHZ_2417   0x0000000a

#define AR5K_PHY_SCAL_32MHZ_HB63   0x00000032

#define AR5K_PHY_PLL   0x987c

#define AR5K_PHY_PLL_20MHZ   0x00000013

#define AR5K_PHY_PLL_40MHZ_5211   0x00000018

#define AR5K_PHY_PLL_40MHZ_5212   0x000000aa

#define AR5K_PHY_PLL_40MHZ_5413   0x00000004

#define AR5K_PHY_PLL_40MHZ

#define AR5K_PHY_PLL_44MHZ_5211   0x00000019

#define AR5K_PHY_PLL_44MHZ_5212   0x000000ab

#define AR5K_PHY_PLL_44MHZ

#define AR5K_PHY_PLL_RF5111   0x00000000

#define AR5K_PHY_PLL_RF5112   0x00000040

#define AR5K_PHY_PLL_HALF_RATE   0x00000100

#define AR5K_PHY_PLL_QUARTER_RATE   0x00000200

#define AR5K_RF_BUFFER   0x989c

#define AR5K_RF_BUFFER_CONTROL_0   0x98c0

#define AR5K_RF_BUFFER_CONTROL_1   0x98c4

#define AR5K_RF_BUFFER_CONTROL_2   0x98cc

#define AR5K_RF_BUFFER_CONTROL_3   0x98d0

#define AR5K_RF_BUFFER_CONTROL_4   0x98d4

#define AR5K_RF_BUFFER_CONTROL_5   0x98d8

#define AR5K_RF_BUFFER_CONTROL_6   0x98dc

#define AR5K_PHY_RFSTG   0x98d4

#define AR5K_PHY_RFSTG_DISABLE   0x00000021

#define AR5K_PHY_BIN_MASK_1   0x9900

#define AR5K_PHY_BIN_MASK_2   0x9904

#define AR5K_PHY_BIN_MASK_3   0x9908

#define AR5K_PHY_BIN_MASK_CTL   0x990c

#define AR5K_PHY_BIN_MASK_CTL_MASK_4   0x00003fff

#define AR5K_PHY_BIN_MASK_CTL_MASK_4_S   0

#define AR5K_PHY_BIN_MASK_CTL_RATE   0xff000000

#define AR5K_PHY_BIN_MASK_CTL_RATE_S   24

#define AR5K_PHY_ANT_CTL   0x9910

#define AR5K_PHY_ANT_CTL_TXRX_EN   0x00000001

#define AR5K_PHY_ANT_CTL_SECTORED_ANT   0x00000004

#define AR5K_PHY_ANT_CTL_HITUNE5   0x00000008

#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE   0x000003f0

#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S   4

#define AR5K_PHY_RX_DELAY   0x9914

#define AR5K_PHY_RX_DELAY_M   0x00003fff

#define AR5K_PHY_MAX_RX_LEN   0x991c

#define AR5K_PHY_IQ   0x9920

#define AR5K_PHY_IQ_CORR_Q_Q_COFF   0x0000001f

#define AR5K_PHY_IQ_CORR_Q_I_COFF   0x000007e0

#define AR5K_PHY_IQ_CORR_Q_I_COFF_S   5

#define AR5K_PHY_IQ_CORR_ENABLE   0x00000800

#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX   0x0000f000

#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S   12

#define AR5K_PHY_IQ_RUN   0x00010000

#define AR5K_PHY_IQ_USE_PT_DF   0x00020000

#define AR5K_PHY_IQ_EARLY_TRIG_THR   0x00200000

#define AR5K_PHY_IQ_PILOT_MASK_EN   0x10000000

#define AR5K_PHY_IQ_CHAN_MASK_EN   0x20000000

#define AR5K_PHY_IQ_SPUR_FILT_EN   0x40000000

#define AR5K_PHY_IQ_SPUR_RSSI_EN   0x80000000

#define AR5K_PHY_OFDM_SELFCORR   0x9924

#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN   0x00000001

#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1   0x000000fe

#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S   1

#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3   0x00000100

#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN   0x00008000

#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR   0x00010000

#define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI   0x00800000

#define AR5K_PHY_WARM_RESET   0x9928

#define AR5K_PHY_CTL   0x992c

#define AR5K_PHY_CTL_RX_DRAIN_RATE   0x00000001

#define AR5K_PHY_CTL_LATE_TX_SIG_SYM   0x00000002

#define AR5K_PHY_CTL_GEN_SCRAMBLER   0x00000004

#define AR5K_PHY_CTL_TX_ANT_SEL   0x00000008

#define AR5K_PHY_CTL_TX_ANT_STATIC   0x00000010

#define AR5K_PHY_CTL_RX_ANT_SEL   0x00000020

#define AR5K_PHY_CTL_RX_ANT_STATIC   0x00000040

#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN   0x00000080

#define AR5K_PHY_PAPD_PROBE   0x9930

#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR   0x00000001

#define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS   0x00000002

#define AR5K_PHY_PAPD_PROBE_COMP_GAIN   0x00000040

#define AR5K_PHY_PAPD_PROBE_TXPOWER   0x00007e00

#define AR5K_PHY_PAPD_PROBE_TXPOWER_S   9

#define AR5K_PHY_PAPD_PROBE_TX_NEXT   0x00008000

#define AR5K_PHY_PAPD_PROBE_PREDIST_EN   0x00010000

#define AR5K_PHY_PAPD_PROBE_TYPE   0x01800000

#define AR5K_PHY_PAPD_PROBE_TYPE_S   23

#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM   0

#define AR5K_PHY_PAPD_PROBE_TYPE_XR   1

#define AR5K_PHY_PAPD_PROBE_TYPE_CCK   2

#define AR5K_PHY_PAPD_PROBE_GAINF   0xfe000000

#define AR5K_PHY_PAPD_PROBE_GAINF_S   25

#define AR5K_PHY_PAPD_PROBE_INI_5111   0x00004883

#define AR5K_PHY_PAPD_PROBE_INI_5112   0x00004882

#define AR5K_PHY_TXPOWER_RATE1   0x9934

#define AR5K_PHY_TXPOWER_RATE2   0x9938

#define AR5K_PHY_TXPOWER_RATE_MAX   0x993c

#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE   0x00000040

#define AR5K_PHY_TXPOWER_RATE3   0xa234

#define AR5K_PHY_TXPOWER_RATE4   0xa238

#define AR5K_PHY_FRAME_CTL_5210   0x9804

#define AR5K_PHY_FRAME_CTL_5211   0x9944

#define AR5K_PHY_FRAME_CTL

#define AR5K_PHY_FRAME_CTL_TX_CLIP   0x00000038

#define AR5K_PHY_FRAME_CTL_TX_CLIP_S   3

#define AR5K_PHY_FRAME_CTL_PREP_CHINFO   0x00010000

#define AR5K_PHY_FRAME_CTL_EMU   0x80000000

#define AR5K_PHY_FRAME_CTL_EMU_S   31

#define AR5K_PHY_FRAME_CTL_TIMING_ERR   0x01000000

#define AR5K_PHY_FRAME_CTL_PARITY_ERR   0x02000000

#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR   0x04000000

#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR   0x08000000

#define AR5K_PHY_FRAME_CTL_SERVICE_ERR   0x20000000

#define AR5K_PHY_FRAME_CTL_TXURN_ERR   0x40000000

#define AR5K_PHY_FRAME_CTL_INI

#define AR5K_PHY_TX_PWR_ADJ   0x994c

#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA   0x00000fc0

#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S   6

#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX   0x00fc0000

#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S   18

#define AR5K_PHY_RADAR   0x9954

#define AR5K_PHY_RADAR_ENABLE   0x00000001

#define AR5K_PHY_RADAR_DISABLE   0x00000000

#define AR5K_PHY_RADAR_INBANDTHR   0x0000003e

#define AR5K_PHY_RADAR_INBANDTHR_S   1

#define AR5K_PHY_RADAR_PRSSI_THR   0x00000fc0

#define AR5K_PHY_RADAR_PRSSI_THR_S   6

#define AR5K_PHY_RADAR_PHEIGHT_THR   0x0003f000

#define AR5K_PHY_RADAR_PHEIGHT_THR_S   12

#define AR5K_PHY_RADAR_RSSI_THR   0x00fc0000

#define AR5K_PHY_RADAR_RSSI_THR_S   18

#define AR5K_PHY_RADAR_FIRPWR_THR   0x7f000000

#define AR5K_PHY_RADAR_FIRPWR_THRS   24

#define AR5K_PHY_ANT_SWITCH_TABLE_0   0x9960

#define AR5K_PHY_ANT_SWITCH_TABLE_1   0x9964

#define AR5K_PHY_NFTHRES   0x9968

#define AR5K_PHY_SIGMA_DELTA   0x996C

#define AR5K_PHY_SIGMA_DELTA_ADC_SEL   0x00000003

#define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S   0

#define AR5K_PHY_SIGMA_DELTA_FILT2   0x000000f8

#define AR5K_PHY_SIGMA_DELTA_FILT2_S   3

#define AR5K_PHY_SIGMA_DELTA_FILT1   0x00001f00

#define AR5K_PHY_SIGMA_DELTA_FILT1_S   8

#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP   0x01ffe000

#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S   13

#define AR5K_PHY_RESTART   0x9970

#define AR5K_PHY_RESTART_DIV_GC   0x001c0000

#define AR5K_PHY_RESTART_DIV_GC_S   18

#define AR5K_PHY_RFBUS_REQ   0x997C

#define AR5K_PHY_RFBUS_REQ_REQUEST   0x00000001

#define AR5K_PHY_TIMING_7   0x9980

#define AR5K_PHY_TIMING_8   0x9984

#define AR5K_PHY_TIMING_8_PILOT_MASK_2   0x000fffff

#define AR5K_PHY_TIMING_8_PILOT_MASK_2_S   0

#define AR5K_PHY_BIN_MASK2_1   0x9988

#define AR5K_PHY_BIN_MASK2_2   0x998c

#define AR5K_PHY_BIN_MASK2_3   0x9990

#define AR5K_PHY_BIN_MASK2_4   0x9994

#define AR5K_PHY_BIN_MASK2_4_MASK_4   0x00003fff

#define AR5K_PHY_BIN_MASK2_4_MASK_4_S   0

#define AR5K_PHY_TIMING_9   0x9998

#define AR5K_PHY_TIMING_10   0x999c

#define AR5K_PHY_TIMING_10_PILOT_MASK_2   0x000fffff

#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S   0

#define AR5K_PHY_TIMING_11   0x99a0

#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE   0x000fffff

#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S   0

#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD   0x3ff00000

#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S   20

#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC   0x40000000

#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR   0x80000000

#define AR5K_BB_GAIN_BASE   0x9b00

#define AR5K_BB_GAIN(_n)   (AR5K_BB_GAIN_BASE + ((_n) << 2))

#define AR5K_RF_GAIN_BASE   0x9a00

#define AR5K_RF_GAIN(_n)   (AR5K_RF_GAIN_BASE + ((_n) << 2))

#define AR5K_PHY_IQRES_CAL_PWR_I   0x9c10

#define AR5K_PHY_IQRES_CAL_PWR_Q   0x9c14

#define AR5K_PHY_IQRES_CAL_CORR   0x9c18

#define AR5K_PHY_CURRENT_RSSI   0x9c1c

#define AR5K_PHY_RFBUS_GRANT   0x9c20

#define AR5K_PHY_RFBUS_GRANT_OK   0x00000001

#define AR5K_PHY_ADC_TEST   0x9c24

#define AR5K_PHY_ADC_TEST_I   0x00000001

#define AR5K_PHY_ADC_TEST_Q   0x00000200

#define AR5K_PHY_DAC_TEST   0x9c28

#define AR5K_PHY_DAC_TEST_I   0x00000001

#define AR5K_PHY_DAC_TEST_Q   0x00000200

#define AR5K_PHY_PTAT   0x9c2c

#define AR5K_PHY_BAD_TX_RATE   0x9c30

#define AR5K_PHY_SPUR_PWR   0x9c34

#define AR5K_PHY_SPUR_PWR_I   0x00000001

#define AR5K_PHY_SPUR_PWR_Q   0x00000100

#define AR5K_PHY_SPUR_PWR_FILT   0x00010000

#define AR5K_PHY_CHAN_STATUS   0x9c38

#define AR5K_PHY_CHAN_STATUS_BT_ACT   0x00000001

#define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW   0x00000002

#define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC   0x00000004

#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP   0x00000008

#define AR5K_PHY_HEAVY_CLIP_ENABLE   0x99e0

#define AR5K_PHY_SCLOCK   0x99f0

#define AR5K_PHY_SCLOCK_32MHZ   0x0000000c

#define AR5K_PHY_SDELAY   0x99f4

#define AR5K_PHY_SDELAY_32MHZ   0x000000ff

#define AR5K_PHY_SPENDING   0x99f8

#define AR5K_PHY_PAPD_I_BASE   0xa000

#define AR5K_PHY_PAPD_I(_n)   (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))

#define AR5K_PHY_PCDAC_TXPOWER_BASE   0xa180

#define AR5K_PHY_PCDAC_TXPOWER(_n)   (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))

#define AR5K_PHY_MODE   0x0a200

#define AR5K_PHY_MODE_MOD   0x00000001

#define AR5K_PHY_MODE_MOD_OFDM   0

#define AR5K_PHY_MODE_MOD_CCK   1

#define AR5K_PHY_MODE_FREQ   0x00000002

#define AR5K_PHY_MODE_FREQ_5GHZ   0

#define AR5K_PHY_MODE_FREQ_2GHZ   2

#define AR5K_PHY_MODE_MOD_DYN   0x00000004

#define AR5K_PHY_MODE_RAD   0x00000008

#define AR5K_PHY_MODE_RAD_RF5111   0

#define AR5K_PHY_MODE_RAD_RF5112   8

#define AR5K_PHY_MODE_XR   0x00000010

#define AR5K_PHY_MODE_HALF_RATE   0x00000020

#define AR5K_PHY_MODE_QUARTER_RATE   0x00000040

#define AR5K_PHY_CCKTXCTL   0xa204

#define AR5K_PHY_CCKTXCTL_WORLD   0x00000000

#define AR5K_PHY_CCKTXCTL_JAPAN   0x00000010

#define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS   0x00000001

#define AR5K_PHY_CCKTXCTK_DAC_SCALE   0x00000004

#define AR5K_PHY_CCK_CROSSCORR   0xa208

#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR   0x0000000f

#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S   0

#define AR5K_PHY_FAST_ANT_DIV   0xa208

#define AR5K_PHY_FAST_ANT_DIV_EN   0x00002000

#define AR5K_PHY_GAIN_2GHZ   0xa20c

#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX   0x00fc0000

#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S   18

#define AR5K_PHY_GAIN_2GHZ_INI_5111   0x6480416c

#define AR5K_PHY_CCK_RX_CTL_4   0xa21c

#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT   0x01f80000

#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S   19

#define AR5K_PHY_DAG_CCK_CTL   0xa228

#define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR   0x00000200

#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR   0x0001fc00

#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S   10

#define AR5K_PHY_FAST_ADC   0xa24c

#define AR5K_PHY_BLUETOOTH   0xa254

#define AR5K_PHY_TPC_RG1   0xa258

#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN   0x0000c000

#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S   14

#define AR5K_PHY_TPC_RG1_PDGAIN_1   0x00030000

#define AR5K_PHY_TPC_RG1_PDGAIN_1_S   16

#define AR5K_PHY_TPC_RG1_PDGAIN_2   0x000c0000

#define AR5K_PHY_TPC_RG1_PDGAIN_2_S   18

#define AR5K_PHY_TPC_RG1_PDGAIN_3   0x00300000

#define AR5K_PHY_TPC_RG1_PDGAIN_3_S   20

#define AR5K_PHY_TPC_RG5   0xa26C

#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP   0x0000000F

#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S   0

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1   0x000003F0

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S   4

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2   0x0000FC00

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S   10

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3   0x003F0000

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S   16

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4   0x0FC00000

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S   22

#define AR5K_PHY_PDADC_TXPOWER_BASE   0xa280

#define AR5K_PHY_PDADC_TXPOWER(_n)   (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))

Define Documentation

#define AR5K_NOQCU_TXDP0 0x0000

Definition at line 47 of file reg.h.

Referenced by ath5k_hw_get_txdp(), and ath5k_hw_set_txdp().

#define AR5K_NOQCU_TXDP1 0x0004

Definition at line 48 of file reg.h.

#define AR5K_CR 0x0008

Definition at line 53 of file reg.h.

Referenced by ath5k_hw_start_rx_dma(), ath5k_hw_start_tx_dma(), ath5k_hw_stop_rx_dma(), and ath5k_hw_stop_tx_dma().

#define AR5K_CR_TXE0 0x00000001

Definition at line 54 of file reg.h.

Referenced by ath5k_hw_start_tx_dma(), and ath5k_hw_stop_tx_dma().

#define AR5K_CR_TXE1 0x00000002

Definition at line 55 of file reg.h.

#define AR5K_CR_RXE 0x00000004

Definition at line 56 of file reg.h.

Referenced by ath5k_hw_start_rx_dma(), and ath5k_hw_stop_rx_dma().

#define AR5K_CR_TXD0 0x00000008

Definition at line 57 of file reg.h.

Referenced by ath5k_hw_start_tx_dma(), and ath5k_hw_stop_tx_dma().

#define AR5K_CR_TXD1 0x00000010

Definition at line 58 of file reg.h.

#define AR5K_CR_RXD 0x00000020

Definition at line 59 of file reg.h.

Referenced by ath5k_hw_stop_rx_dma().

#define AR5K_CR_SWI 0x00000040

Definition at line 60 of file reg.h.

#define AR5K_RXDP 0x000c

Definition at line 65 of file reg.h.

Referenced by ath5k_hw_get_rxdp(), ath5k_hw_nic_reset(), and ath5k_hw_set_rxdp().

#define AR5K_CFG 0x0014

Definition at line 70 of file reg.h.

Referenced by ath5k_hw_nic_reset().

#define AR5K_CFG_SWTD 0x00000001

Definition at line 71 of file reg.h.

#define AR5K_CFG_SWTB 0x00000002

Definition at line 72 of file reg.h.

#define AR5K_CFG_SWRD 0x00000004

Definition at line 73 of file reg.h.

#define AR5K_CFG_SWRB 0x00000008

Definition at line 74 of file reg.h.

#define AR5K_CFG_SWRG 0x00000010

Definition at line 75 of file reg.h.

#define AR5K_CFG_IBSS 0x00000020

Definition at line 76 of file reg.h.

#define AR5K_CFG_PHY_OK 0x00000100

Definition at line 77 of file reg.h.

#define AR5K_CFG_EEBS 0x00000200

Definition at line 78 of file reg.h.

#define AR5K_CFG_CLKGD 0x00000400

Definition at line 79 of file reg.h.

#define AR5K_CFG_TXCNT 0x00007800

Definition at line 80 of file reg.h.

#define AR5K_CFG_TXCNT_S 11

Definition at line 81 of file reg.h.

#define AR5K_CFG_TXFSTAT 0x00008000

Definition at line 82 of file reg.h.

#define AR5K_CFG_TXFSTRT 0x00010000

Definition at line 83 of file reg.h.

#define AR5K_CFG_PCI_THRES 0x00060000

Definition at line 84 of file reg.h.

#define AR5K_CFG_PCI_THRES_S 17

Definition at line 85 of file reg.h.

#define AR5K_IER 0x0024

Definition at line 90 of file reg.h.

Referenced by ath5k_hw_set_imr(), and ath5k_irq().

#define AR5K_IER_DISABLE 0x00000000

Definition at line 91 of file reg.h.

Referenced by ath5k_hw_set_imr(), and ath5k_irq().

#define AR5K_IER_ENABLE 0x00000001

Definition at line 92 of file reg.h.

Referenced by ath5k_irq().

#define AR5K_BCR 0x0028

Definition at line 103 of file reg.h.

Referenced by ath5k_hw_set_opmode().

#define AR5K_BCR_AP 0x00000000

Definition at line 104 of file reg.h.

#define AR5K_BCR_ADHOC 0x00000001

Definition at line 105 of file reg.h.

#define AR5K_BCR_BDMAE 0x00000002

Definition at line 106 of file reg.h.

#define AR5K_BCR_TQ1FV 0x00000004

Definition at line 107 of file reg.h.

#define AR5K_BCR_TQ1V 0x00000008

Definition at line 108 of file reg.h.

#define AR5K_BCR_BCGET 0x00000010

Definition at line 109 of file reg.h.

#define AR5K_RTSD0 0x0028

Definition at line 114 of file reg.h.

#define AR5K_RTSD0_6 0x000000ff

Definition at line 115 of file reg.h.

#define AR5K_RTSD0_6_S 0

Definition at line 116 of file reg.h.

#define AR5K_RTSD0_9 0x0000ff00

Definition at line 117 of file reg.h.

#define AR5K_RTSD0_9_S 8

Definition at line 118 of file reg.h.

#define AR5K_RTSD0_12 0x00ff0000

Definition at line 119 of file reg.h.

#define AR5K_RTSD0_12_S 16

Definition at line 120 of file reg.h.

#define AR5K_RTSD0_18 0xff000000

Definition at line 121 of file reg.h.

#define AR5K_RTSD0_18_S 24

Definition at line 122 of file reg.h.

#define AR5K_BSR 0x002c

Definition at line 140 of file reg.h.

#define AR5K_BSR_BDLYSW 0x00000001

Definition at line 141 of file reg.h.

#define AR5K_BSR_BDLYDMA 0x00000002

Definition at line 142 of file reg.h.

#define AR5K_BSR_TXQ1F 0x00000004

Definition at line 143 of file reg.h.

#define AR5K_BSR_ATIMDLY 0x00000008

Definition at line 144 of file reg.h.

#define AR5K_BSR_SNPADHOC 0x00000100

Definition at line 145 of file reg.h.

#define AR5K_BSR_SNPBDMAE 0x00000200

Definition at line 146 of file reg.h.

#define AR5K_BSR_SNPTQ1FV 0x00000400

Definition at line 147 of file reg.h.

#define AR5K_BSR_SNPTQ1V 0x00000800

Definition at line 148 of file reg.h.

#define AR5K_BSR_SNAPSHOTSVALID 0x00001000

Definition at line 149 of file reg.h.

#define AR5K_BSR_SWBA_CNT 0x00ff0000

Definition at line 150 of file reg.h.

#define AR5K_RTSD1 0x002c

Definition at line 155 of file reg.h.

#define AR5K_RTSD1_24 0x000000ff

Definition at line 156 of file reg.h.

#define AR5K_RTSD1_24_S 0

Definition at line 157 of file reg.h.

#define AR5K_RTSD1_36 0x0000ff00

Definition at line 158 of file reg.h.

#define AR5K_RTSD1_36_S 8

Definition at line 159 of file reg.h.

#define AR5K_RTSD1_48 0x00ff0000

Definition at line 160 of file reg.h.

#define AR5K_RTSD1_48_S 16

Definition at line 161 of file reg.h.

#define AR5K_RTSD1_54 0xff000000

Definition at line 162 of file reg.h.

#define AR5K_RTSD1_54_S 24

Definition at line 163 of file reg.h.

#define AR5K_TXCFG 0x0030

Definition at line 169 of file reg.h.

Referenced by ath5k_hw_reset(), ath5k_hw_tweak_initval_settings(), and ath5k_hw_update_tx_triglevel().

#define AR5K_TXCFG_SDMAMR 0x00000007

Definition at line 170 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_TXCFG_SDMAMR_S 0

Definition at line 171 of file reg.h.

#define AR5K_TXCFG_B_MODE 0x00000008

Definition at line 172 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_TXCFG_TXFSTP 0x00000008

Definition at line 173 of file reg.h.

#define AR5K_TXCFG_TXFULL 0x000003f0

Definition at line 174 of file reg.h.

Referenced by ath5k_hw_update_tx_triglevel().

#define AR5K_TXCFG_TXFULL_S 4

Definition at line 175 of file reg.h.

#define AR5K_TXCFG_TXFULL_0B 0x00000000

Definition at line 176 of file reg.h.

#define AR5K_TXCFG_TXFULL_64B 0x00000010

Definition at line 177 of file reg.h.

#define AR5K_TXCFG_TXFULL_128B 0x00000020

Definition at line 178 of file reg.h.

#define AR5K_TXCFG_TXFULL_192B 0x00000030

Definition at line 179 of file reg.h.

#define AR5K_TXCFG_TXFULL_256B 0x00000040

Definition at line 180 of file reg.h.

#define AR5K_TXCFG_TXCONT_EN 0x00000080

Definition at line 181 of file reg.h.

#define AR5K_TXCFG_DMASIZE 0x00000100

Definition at line 182 of file reg.h.

#define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400

Definition at line 183 of file reg.h.

#define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800

Definition at line 184 of file reg.h.

#define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000

Definition at line 185 of file reg.h.

#define AR5K_TXCFG_RTSRND 0x00001000

Definition at line 186 of file reg.h.

#define AR5K_TXCFG_FRMPAD_DIS 0x00002000

Definition at line 187 of file reg.h.

#define AR5K_TXCFG_RDY_CBR_DIS 0x00004000

Definition at line 188 of file reg.h.

#define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000

Definition at line 189 of file reg.h.

#define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000

Definition at line 190 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000

Definition at line 191 of file reg.h.

#define AR5K_RXCFG 0x0034

Definition at line 196 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_set_rx_filter().

#define AR5K_RXCFG_SDMAMW 0x00000007

Definition at line 197 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_RXCFG_SDMAMW_S 0

Definition at line 198 of file reg.h.

#define AR5K_RXCFG_ZLFDMA 0x00000008

Definition at line 199 of file reg.h.

Referenced by ath5k_hw_set_rx_filter().

#define AR5K_RXCFG_DEF_ANTENNA 0x00000010

Definition at line 200 of file reg.h.

#define AR5K_RXCFG_JUMBO_RXE 0x00000020

Definition at line 201 of file reg.h.

#define AR5K_RXCFG_JUMBO_WRAP 0x00000040

Definition at line 202 of file reg.h.

#define AR5K_RXCFG_SLE_ENTRY 0x00000080

Definition at line 203 of file reg.h.

#define AR5K_RXJLA 0x0038

Definition at line 209 of file reg.h.

#define AR5K_MIBC 0x0040

Definition at line 214 of file reg.h.

#define AR5K_MIBC_COW 0x00000001

Definition at line 215 of file reg.h.

#define AR5K_MIBC_FMC 0x00000002

Definition at line 216 of file reg.h.

#define AR5K_MIBC_CMC 0x00000004

Definition at line 217 of file reg.h.

#define AR5K_MIBC_MCS 0x00000008

Definition at line 218 of file reg.h.

#define AR5K_TOPS 0x0044

Definition at line 223 of file reg.h.

#define AR5K_TOPS_M 0x0000ffff

Definition at line 224 of file reg.h.

#define AR5K_RXNOFRM 0x0048

Definition at line 229 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_RXNOFRM_M 0x000003ff

Definition at line 230 of file reg.h.

#define AR5K_TXNOFRM 0x004c

Definition at line 235 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXNOFRM_M 0x000003ff

Definition at line 236 of file reg.h.

#define AR5K_TXNOFRM_QCU 0x000ffc00

Definition at line 237 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_TXNOFRM_QCU_S 10

Definition at line 238 of file reg.h.

#define AR5K_RPGTO 0x0050

Definition at line 243 of file reg.h.

#define AR5K_RPGTO_M 0x000003ff

Definition at line 244 of file reg.h.

#define AR5K_RFCNT 0x0054

Definition at line 249 of file reg.h.

#define AR5K_RFCNT_M 0x0000001f

Definition at line 250 of file reg.h.

#define AR5K_RFCNT_RFCL 0x0000000f

Definition at line 251 of file reg.h.

#define AR5K_MISC 0x0058

Definition at line 257 of file reg.h.

#define AR5K_MISC_DMA_OBS_M 0x000001e0

Definition at line 258 of file reg.h.

#define AR5K_MISC_DMA_OBS_S 5

Definition at line 259 of file reg.h.

#define AR5K_MISC_MISC_OBS_M 0x00000e00

Definition at line 260 of file reg.h.

#define AR5K_MISC_MISC_OBS_S 9

Definition at line 261 of file reg.h.

#define AR5K_MISC_MAC_OBS_LSB_M 0x00007000

Definition at line 262 of file reg.h.

#define AR5K_MISC_MAC_OBS_LSB_S 12

Definition at line 263 of file reg.h.

#define AR5K_MISC_MAC_OBS_MSB_M 0x00038000

Definition at line 264 of file reg.h.

#define AR5K_MISC_MAC_OBS_MSB_S 15

Definition at line 265 of file reg.h.

#define AR5K_MISC_LED_DECAY 0x001c0000

Definition at line 266 of file reg.h.

#define AR5K_MISC_LED_BLINK 0x00e00000

Definition at line 267 of file reg.h.

#define AR5K_QCUDCU_CLKGT 0x005c

Definition at line 273 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff

Definition at line 274 of file reg.h.

#define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000

Definition at line 275 of file reg.h.

#define AR5K_ISR 0x001c

Definition at line 285 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_PISR 0x0080

Definition at line 286 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_ISR_RXOK 0x00000001

Definition at line 287 of file reg.h.

#define AR5K_ISR_RXDESC 0x00000002

Definition at line 288 of file reg.h.

#define AR5K_ISR_RXERR 0x00000004

Definition at line 289 of file reg.h.

#define AR5K_ISR_RXNOFRM 0x00000008

Definition at line 290 of file reg.h.

#define AR5K_ISR_RXEOL 0x00000010

Definition at line 291 of file reg.h.

#define AR5K_ISR_RXORN 0x00000020

Definition at line 292 of file reg.h.

#define AR5K_ISR_TXOK 0x00000040

Definition at line 293 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_TXDESC 0x00000080

Definition at line 294 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_TXERR 0x00000100

Definition at line 295 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_TXNOFRM 0x00000200

Definition at line 296 of file reg.h.

#define AR5K_ISR_TXEOL 0x00000400

Definition at line 297 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_TXURN 0x00000800

Definition at line 298 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_MIB 0x00001000

Definition at line 299 of file reg.h.

#define AR5K_ISR_SWI 0x00002000

Definition at line 300 of file reg.h.

#define AR5K_ISR_RXPHY 0x00004000

Definition at line 301 of file reg.h.

#define AR5K_ISR_RXKCM 0x00008000

Definition at line 302 of file reg.h.

#define AR5K_ISR_SWBA 0x00010000

Definition at line 303 of file reg.h.

#define AR5K_ISR_BRSSI 0x00020000

Definition at line 304 of file reg.h.

#define AR5K_ISR_BMISS 0x00040000

Definition at line 305 of file reg.h.

#define AR5K_ISR_HIUERR 0x00080000

Definition at line 306 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_BNR 0x00100000

Definition at line 307 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_MCABT 0x00100000

Definition at line 308 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_RXCHIRP 0x00200000

Definition at line 309 of file reg.h.

#define AR5K_ISR_SSERR 0x00200000

Definition at line 310 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_DPERR 0x00400000

Definition at line 311 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_RXDOPPLER 0x00400000

Definition at line 312 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_TIM 0x00800000

Definition at line 313 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_BCNMISC 0x00800000

Definition at line 314 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_GPIO 0x01000000

Definition at line 316 of file reg.h.

#define AR5K_ISR_QCBRORN 0x02000000

Definition at line 317 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_QCBRURN 0x04000000

Definition at line 318 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_ISR_QTRIG 0x08000000

Definition at line 319 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR0 0x0084

Definition at line 327 of file reg.h.

#define AR5K_SISR0_QCU_TXOK 0x000003ff

Definition at line 328 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR0_QCU_TXOK_S 0

Definition at line 329 of file reg.h.

#define AR5K_SISR0_QCU_TXDESC 0x03ff0000

Definition at line 330 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR0_QCU_TXDESC_S 16

Definition at line 331 of file reg.h.

#define AR5K_SISR1 0x0088

Definition at line 333 of file reg.h.

#define AR5K_SISR1_QCU_TXERR 0x000003ff

Definition at line 334 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR1_QCU_TXERR_S 0

Definition at line 335 of file reg.h.

#define AR5K_SISR1_QCU_TXEOL 0x03ff0000

Definition at line 336 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR1_QCU_TXEOL_S 16

Definition at line 337 of file reg.h.

#define AR5K_SISR2 0x008c

Definition at line 339 of file reg.h.

#define AR5K_SISR2_QCU_TXURN 0x000003ff

Definition at line 340 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR2_QCU_TXURN_S 0

Definition at line 341 of file reg.h.

#define AR5K_SISR2_MCABT 0x00100000

Definition at line 342 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR2_SSERR 0x00200000

Definition at line 343 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR2_DPERR 0x00400000

Definition at line 344 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR2_TIM 0x01000000

Definition at line 345 of file reg.h.

Referenced by ath5k_hw_get_isr(), and ath5k_hw_set_imr().

#define AR5K_SISR2_CAB_END 0x02000000

Definition at line 346 of file reg.h.

#define AR5K_SISR2_DTIM_SYNC 0x04000000

Definition at line 347 of file reg.h.

Referenced by ath5k_hw_get_isr(), and ath5k_hw_set_imr().

#define AR5K_SISR2_BCN_TIMEOUT 0x08000000

Definition at line 348 of file reg.h.

Referenced by ath5k_hw_get_isr(), and ath5k_hw_set_imr().

#define AR5K_SISR2_CAB_TIMEOUT 0x10000000

Definition at line 349 of file reg.h.

Referenced by ath5k_hw_get_isr(), and ath5k_hw_set_imr().

#define AR5K_SISR2_DTIM 0x20000000

Definition at line 350 of file reg.h.

Referenced by ath5k_hw_get_isr(), and ath5k_hw_set_imr().

#define AR5K_SISR2_TSFOOR 0x80000000

Definition at line 351 of file reg.h.

#define AR5K_SISR3 0x0090

Definition at line 353 of file reg.h.

#define AR5K_SISR3_QCBRORN 0x000003ff

Definition at line 354 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR3_QCBRORN_S 0

Definition at line 355 of file reg.h.

#define AR5K_SISR3_QCBRURN 0x03ff0000

Definition at line 356 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR3_QCBRURN_S 16

Definition at line 357 of file reg.h.

#define AR5K_SISR4 0x0094

Definition at line 359 of file reg.h.

#define AR5K_SISR4_QTRIG 0x000003ff

Definition at line 360 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_SISR4_QTRIG_S 0

Definition at line 361 of file reg.h.

#define AR5K_RAC_PISR 0x00c0

Definition at line 366 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_RAC_SISR0 0x00c4

Definition at line 367 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_RAC_SISR1 0x00c8

Definition at line 368 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_RAC_SISR2 0x00cc

Definition at line 369 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_RAC_SISR3 0x00d0

Definition at line 370 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_RAC_SISR4 0x00d4

Definition at line 371 of file reg.h.

Referenced by ath5k_hw_get_isr().

#define AR5K_IMR 0x0020

Definition at line 379 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_PIMR 0x00a0

Definition at line 380 of file reg.h.

Referenced by ath5k_hw_set_gpio_intr(), and ath5k_hw_set_imr().

#define AR5K_IMR_RXOK 0x00000001

Definition at line 381 of file reg.h.

#define AR5K_IMR_RXDESC 0x00000002

Definition at line 382 of file reg.h.

#define AR5K_IMR_RXERR 0x00000004

Definition at line 383 of file reg.h.

#define AR5K_IMR_RXNOFRM 0x00000008

Definition at line 384 of file reg.h.

#define AR5K_IMR_RXEOL 0x00000010

Definition at line 385 of file reg.h.

#define AR5K_IMR_RXORN 0x00000020

Definition at line 386 of file reg.h.

#define AR5K_IMR_TXOK 0x00000040

Definition at line 387 of file reg.h.

#define AR5K_IMR_TXDESC 0x00000080

Definition at line 388 of file reg.h.

#define AR5K_IMR_TXERR 0x00000100

Definition at line 389 of file reg.h.

#define AR5K_IMR_TXNOFRM 0x00000200

Definition at line 390 of file reg.h.

#define AR5K_IMR_TXEOL 0x00000400

Definition at line 391 of file reg.h.

#define AR5K_IMR_TXURN 0x00000800

Definition at line 392 of file reg.h.

#define AR5K_IMR_MIB 0x00001000

Definition at line 393 of file reg.h.

#define AR5K_IMR_SWI 0x00002000

Definition at line 394 of file reg.h.

#define AR5K_IMR_RXPHY 0x00004000

Definition at line 395 of file reg.h.

#define AR5K_IMR_RXKCM 0x00008000

Definition at line 396 of file reg.h.

#define AR5K_IMR_SWBA 0x00010000

Definition at line 397 of file reg.h.

#define AR5K_IMR_BRSSI 0x00020000

Definition at line 398 of file reg.h.

#define AR5K_IMR_BMISS 0x00040000

Definition at line 399 of file reg.h.

#define AR5K_IMR_HIUERR 0x00080000

Definition at line 400 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_IMR_BNR 0x00100000

Definition at line 401 of file reg.h.

#define AR5K_IMR_MCABT 0x00100000

Definition at line 402 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_IMR_RXCHIRP 0x00200000

Definition at line 403 of file reg.h.

#define AR5K_IMR_SSERR 0x00200000

Definition at line 404 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_IMR_DPERR 0x00400000

Definition at line 405 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_IMR_RXDOPPLER 0x00400000

Definition at line 406 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_IMR_TIM 0x00800000

Definition at line 407 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_IMR_BCNMISC 0x00800000

Definition at line 408 of file reg.h.

#define AR5K_IMR_GPIO 0x01000000

Definition at line 410 of file reg.h.

Referenced by ath5k_hw_set_gpio_intr().

#define AR5K_IMR_QCBRORN 0x02000000

Definition at line 411 of file reg.h.

#define AR5K_IMR_QCBRURN 0x04000000

Definition at line 412 of file reg.h.

#define AR5K_IMR_QTRIG 0x08000000

Definition at line 413 of file reg.h.

#define AR5K_SIMR0 0x00a4

Definition at line 418 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR0_QCU_TXOK 0x000003ff

Definition at line 419 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR0_QCU_TXOK_S 0

Definition at line 420 of file reg.h.

#define AR5K_SIMR0_QCU_TXDESC 0x03ff0000

Definition at line 421 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR0_QCU_TXDESC_S 16

Definition at line 422 of file reg.h.

#define AR5K_SIMR1 0x00a8

Definition at line 424 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR1_QCU_TXERR 0x000003ff

Definition at line 425 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR1_QCU_TXERR_S 0

Definition at line 426 of file reg.h.

#define AR5K_SIMR1_QCU_TXEOL 0x03ff0000

Definition at line 427 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR1_QCU_TXEOL_S 16

Definition at line 428 of file reg.h.

#define AR5K_SIMR2 0x00ac

Definition at line 430 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue(), and ath5k_hw_set_imr().

#define AR5K_SIMR2_QCU_TXURN 0x000003ff

Definition at line 431 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue(), and ath5k_hw_set_imr().

#define AR5K_SIMR2_QCU_TXURN_S 0

Definition at line 432 of file reg.h.

#define AR5K_SIMR2_MCABT 0x00100000

Definition at line 433 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_SIMR2_SSERR 0x00200000

Definition at line 434 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_SIMR2_DPERR 0x00400000

Definition at line 435 of file reg.h.

Referenced by ath5k_hw_set_imr().

#define AR5K_SIMR2_TIM 0x01000000

Definition at line 436 of file reg.h.

#define AR5K_SIMR2_CAB_END 0x02000000

Definition at line 437 of file reg.h.

#define AR5K_SIMR2_DTIM_SYNC 0x04000000

Definition at line 438 of file reg.h.

#define AR5K_SIMR2_BCN_TIMEOUT 0x08000000

Definition at line 439 of file reg.h.

#define AR5K_SIMR2_CAB_TIMEOUT 0x10000000

Definition at line 440 of file reg.h.

#define AR5K_SIMR2_DTIM 0x20000000

Definition at line 441 of file reg.h.

#define AR5K_SIMR2_TSFOOR 0x80000000

Definition at line 442 of file reg.h.

#define AR5K_SIMR3 0x00b0

Definition at line 444 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR3_QCBRORN 0x000003ff

Definition at line 445 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR3_QCBRORN_S 0

Definition at line 446 of file reg.h.

#define AR5K_SIMR3_QCBRURN 0x03ff0000

Definition at line 447 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR3_QCBRURN_S 16

Definition at line 448 of file reg.h.

#define AR5K_SIMR4 0x00b4

Definition at line 450 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR4_QTRIG 0x000003ff

Definition at line 451 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_SIMR4_QTRIG_S 0

Definition at line 452 of file reg.h.

#define AR5K_DCM_ADDR 0x0400

Definition at line 462 of file reg.h.

#define AR5K_DCM_DATA 0x0404

Definition at line 463 of file reg.h.

#define AR5K_WOW_PCFG 0x0410

Definition at line 468 of file reg.h.

#define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001

Definition at line 469 of file reg.h.

#define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002

Definition at line 470 of file reg.h.

#define AR5K_WOW_PCFG_WOBMISS 0x00000004

Definition at line 471 of file reg.h.

#define AR5K_WOW_PCFG_PAT_0_EN 0x00000100

Definition at line 472 of file reg.h.

#define AR5K_WOW_PCFG_PAT_1_EN 0x00000200

Definition at line 473 of file reg.h.

#define AR5K_WOW_PCFG_PAT_2_EN 0x00000400

Definition at line 474 of file reg.h.

#define AR5K_WOW_PCFG_PAT_3_EN 0x00000800

Definition at line 475 of file reg.h.

#define AR5K_WOW_PCFG_PAT_4_EN 0x00001000

Definition at line 476 of file reg.h.

#define AR5K_WOW_PCFG_PAT_5_EN 0x00002000

Definition at line 477 of file reg.h.

#define AR5K_WOW_PAT_IDX 0x0414

Definition at line 482 of file reg.h.

#define AR5K_WOW_PAT_DATA 0x0418

Definition at line 487 of file reg.h.

#define AR5K_WOW_PAT_DATA_0_3_V 0x00000001

Definition at line 488 of file reg.h.

#define AR5K_WOW_PAT_DATA_1_4_V 0x00000100

Definition at line 489 of file reg.h.

#define AR5K_WOW_PAT_DATA_2_5_V 0x00010000

Definition at line 490 of file reg.h.

#define AR5K_WOW_PAT_DATA_0_3_M 0x01000000

Definition at line 491 of file reg.h.

#define AR5K_WOW_PAT_DATA_1_4_M 0x04000000

Definition at line 492 of file reg.h.

#define AR5K_WOW_PAT_DATA_2_5_M 0x10000000

Definition at line 493 of file reg.h.

#define AR5K_DCCFG 0x0420

Definition at line 498 of file reg.h.

#define AR5K_DCCFG_GLOBAL_EN 0x00000001

Definition at line 499 of file reg.h.

#define AR5K_DCCFG_BYPASS_EN 0x00000002

Definition at line 500 of file reg.h.

#define AR5K_DCCFG_BCAST_EN 0x00000004

Definition at line 501 of file reg.h.

#define AR5K_DCCFG_MCAST_EN 0x00000008

Definition at line 502 of file reg.h.

#define AR5K_CCFG 0x0600

Definition at line 507 of file reg.h.

#define AR5K_CCFG_WINDOW_SIZE 0x00000007

Definition at line 508 of file reg.h.

#define AR5K_CCFG_CPC_EN 0x00000008

Definition at line 509 of file reg.h.

#define AR5K_CCFG_CCU 0x0604

Definition at line 511 of file reg.h.

#define AR5K_CCFG_CCU_CUP_EN 0x00000001

Definition at line 512 of file reg.h.

#define AR5K_CCFG_CCU_CREDIT 0x00000002

Definition at line 513 of file reg.h.

#define AR5K_CCFG_CCU_CD_THRES 0x00000080

Definition at line 514 of file reg.h.

#define AR5K_CCFG_CCU_CUP_LCNT 0x00010000

Definition at line 515 of file reg.h.

#define AR5K_CCFG_CCU_INIT 0x00100200

Definition at line 516 of file reg.h.

#define AR5K_CPC0 0x0610

Definition at line 521 of file reg.h.

#define AR5K_CPC1 0x0614

Definition at line 522 of file reg.h.

#define AR5K_CPC2 0x0618

Definition at line 523 of file reg.h.

#define AR5K_CPC3 0x061c

Definition at line 524 of file reg.h.

#define AR5K_CPCOVF 0x0620

Definition at line 525 of file reg.h.

#define AR5K_QUEUE_REG	(	_r,
		_q		)	(((_q) << 2) + _r)

Definition at line 546 of file reg.h.

#define AR5K_QCU_GLOBAL_READ	(	_r,
		_q		)	(AR5K_REG_READ(_r) & (1 << _q))

Definition at line 547 of file reg.h.

#define AR5K_QCU_GLOBAL_WRITE	(	_r,
		_q		)	AR5K_REG_WRITE(_r, (1 << _q))

Definition at line 548 of file reg.h.

#define AR5K_QCU_TXDP_BASE 0x0800

Definition at line 553 of file reg.h.

#define AR5K_QUEUE_TXDP ( _q ) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q)

Definition at line 554 of file reg.h.

Referenced by ath5k_hw_get_txdp(), and ath5k_hw_set_txdp().

#define AR5K_QCU_TXE 0x0840

Definition at line 559 of file reg.h.

Referenced by ath5k_hw_set_txdp(), and ath5k_hw_start_tx_dma().

#define AR5K_ENABLE_QUEUE ( _q ) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q)

Definition at line 560 of file reg.h.

#define AR5K_QUEUE_ENABLED ( _q ) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q)

Definition at line 561 of file reg.h.

#define AR5K_QCU_TXD 0x0880

Definition at line 566 of file reg.h.

Referenced by ath5k_hw_start_tx_dma(), and ath5k_hw_stop_tx_dma().

#define AR5K_DISABLE_QUEUE ( _q ) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q)

Definition at line 567 of file reg.h.

#define AR5K_QUEUE_DISABLED ( _q ) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q)

Definition at line 568 of file reg.h.

#define AR5K_QCU_CBRCFG_BASE 0x08c0

Definition at line 573 of file reg.h.

#define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff

Definition at line 574 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_CBRCFG_INTVAL_S 0

Definition at line 575 of file reg.h.

#define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000

Definition at line 576 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_CBRCFG_ORN_THRES_S 24

Definition at line 577 of file reg.h.

#define AR5K_QUEUE_CBRCFG ( _q ) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q)

Definition at line 578 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_RDYTIMECFG_BASE 0x0900

Definition at line 583 of file reg.h.

#define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff

Definition at line 584 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_RDYTIMECFG_INTVAL_S 0

Definition at line 585 of file reg.h.

#define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000

Definition at line 586 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QUEUE_RDYTIMECFG ( _q ) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q)

Definition at line 587 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_ONESHOTARM_SET 0x0940

Definition at line 592 of file reg.h.

#define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff

Definition at line 593 of file reg.h.

#define AR5K_QCU_ONESHOTARM_CLEAR 0x0980

Definition at line 598 of file reg.h.

#define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff

Definition at line 599 of file reg.h.

#define AR5K_QCU_MISC_BASE 0x09c0

Definition at line 604 of file reg.h.

#define AR5K_QCU_MISC_FRSHED_M 0x0000000f

Definition at line 605 of file reg.h.

#define AR5K_QCU_MISC_FRSHED_ASAP 0

Definition at line 606 of file reg.h.

#define AR5K_QCU_MISC_FRSHED_CBR 1

Definition at line 607 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_MISC_FRSHED_DBA_GT 2

Definition at line 608 of file reg.h.

#define AR5K_QCU_MISC_FRSHED_TIM_GT 3

Definition at line 609 of file reg.h.

#define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4

Definition at line 610 of file reg.h.

#define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010

Definition at line 611 of file reg.h.

#define AR5K_QCU_MISC_CBREXP_DIS 0x00000020

Definition at line 612 of file reg.h.

#define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040

Definition at line 613 of file reg.h.

#define AR5K_QCU_MISC_BCN_ENABLE 0x00000080

Definition at line 614 of file reg.h.

#define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100

Definition at line 615 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200

Definition at line 616 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400

Definition at line 617 of file reg.h.

#define AR5K_QCU_MISC_DCU_EARLY 0x00000800

Definition at line 618 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000

Definition at line 619 of file reg.h.

#define AR5K_QUEUE_MISC ( _q ) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q)

Definition at line 620 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QCU_STS_BASE 0x0a00

Definition at line 626 of file reg.h.

#define AR5K_QCU_STS_FRMPENDCNT 0x00000003

Definition at line 627 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_QCU_STS_CBREXPCNT 0x0000ff00

Definition at line 628 of file reg.h.

#define AR5K_QUEUE_STATUS ( _q ) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q)

Definition at line 629 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_QCU_RDYTIMESHDN 0x0a40

Definition at line 634 of file reg.h.

#define AR5K_QCU_RDYTIMESHDN_M 0x000003ff

Definition at line 635 of file reg.h.

#define AR5K_QCU_CBB_SELECT 0x0b00

Definition at line 640 of file reg.h.

#define AR5K_QCU_CBB_ADDR 0x0b04

Definition at line 641 of file reg.h.

#define AR5K_QCU_CBB_ADDR_S 9

Definition at line 642 of file reg.h.

#define AR5K_QCU_CBCFG 0x0b08

Definition at line 648 of file reg.h.

#define AR5K_DCU_QCUMASK_BASE 0x1000

Definition at line 671 of file reg.h.

#define AR5K_DCU_QCUMASK_M 0x000003ff

Definition at line 672 of file reg.h.

#define AR5K_QUEUE_QCUMASK ( _q ) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q)

Definition at line 673 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_LCL_IFS_BASE 0x1040

Definition at line 678 of file reg.h.

#define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff

Definition at line 679 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_LCL_IFS_CW_MIN_S 0

Definition at line 680 of file reg.h.

#define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00

Definition at line 681 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_LCL_IFS_CW_MAX_S 10

Definition at line 682 of file reg.h.

#define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000

Definition at line 683 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_LCL_IFS_AIFS_S 20

Definition at line 684 of file reg.h.

#define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc

Definition at line 685 of file reg.h.

#define AR5K_QUEUE_DFS_LOCAL_IFS ( _q ) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q)

Definition at line 686 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_RETRY_LMT_BASE 0x1080

Definition at line 691 of file reg.h.

#define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f

Definition at line 692 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0

Definition at line 693 of file reg.h.

#define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0

Definition at line 694 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4

Definition at line 695 of file reg.h.

#define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00

Definition at line 696 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8

Definition at line 697 of file reg.h.

#define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000

Definition at line 698 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14

Definition at line 699 of file reg.h.

#define AR5K_QUEUE_DFS_RETRY_LIMIT ( _q ) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q)

Definition at line 700 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_CHAN_TIME_BASE 0x10c0

Definition at line 705 of file reg.h.

#define AR5K_DCU_CHAN_TIME_DUR 0x000fffff

Definition at line 706 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_CHAN_TIME_DUR_S 0

Definition at line 707 of file reg.h.

#define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000

Definition at line 708 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QUEUE_DFS_CHANNEL_TIME ( _q ) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q)

Definition at line 709 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_MISC_BASE 0x1100

Definition at line 723 of file reg.h.

#define AR5K_DCU_MISC_BACKOFF 0x0000003f

Definition at line 724 of file reg.h.

#define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040

Definition at line 725 of file reg.h.

#define AR5K_DCU_MISC_ETS_CW_POL 0x00000080

Definition at line 728 of file reg.h.

#define AR5K_DCU_MISC_FRAG_WAIT 0x00000100

Definition at line 730 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200

Definition at line 731 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800

Definition at line 732 of file reg.h.

#define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000

Definition at line 733 of file reg.h.

#define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000

Definition at line 734 of file reg.h.

#define AR5K_DCU_MISC_VIRTCOL 0x0000c000

Definition at line 735 of file reg.h.

#define AR5K_DCU_MISC_VIRTCOL_NORMAL 0

Definition at line 736 of file reg.h.

#define AR5K_DCU_MISC_VIRTCOL_IGNORE 1

Definition at line 737 of file reg.h.

#define AR5K_DCU_MISC_BCN_ENABLE 0x00010000

Definition at line 738 of file reg.h.

#define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000

Definition at line 739 of file reg.h.

#define AR5K_DCU_MISC_ARBLOCK_CTL_S 17

Definition at line 740 of file reg.h.

#define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0

Definition at line 741 of file reg.h.

#define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1

Definition at line 742 of file reg.h.

#define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2

Definition at line 743 of file reg.h.

#define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000

Definition at line 744 of file reg.h.

#define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000

Definition at line 745 of file reg.h.

#define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000

Definition at line 746 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000

Definition at line 747 of file reg.h.

#define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000

Definition at line 748 of file reg.h.

#define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000

Definition at line 749 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_QUEUE_DFS_MISC ( _q ) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q)

Definition at line 750 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_DCU_SEQNUM_BASE 0x1140

Definition at line 755 of file reg.h.

#define AR5K_DCU_SEQNUM_M 0x00000fff

Definition at line 756 of file reg.h.

#define AR5K_QUEUE_DCU_SEQNUM ( _q ) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q)

Definition at line 757 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_DCU_GBL_IFS_SIFS 0x1030

Definition at line 762 of file reg.h.

#define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff

Definition at line 763 of file reg.h.

#define AR5K_DCU_GBL_IFS_SLOT 0x1070

Definition at line 768 of file reg.h.

Referenced by ath5k_hw_set_slot_time().

#define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff

Definition at line 769 of file reg.h.

#define AR5K_DCU_GBL_IFS_EIFS 0x10b0

Definition at line 774 of file reg.h.

#define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff

Definition at line 775 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC 0x10f0

Definition at line 787 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007

Definition at line 788 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008

Definition at line 789 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0

Definition at line 790 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00

Definition at line 791 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10

Definition at line 792 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000

Definition at line 793 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000

Definition at line 794 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000

Definition at line 795 of file reg.h.

#define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000

Definition at line 796 of file reg.h.

#define AR5K_DCU_FP 0x1230

Definition at line 801 of file reg.h.

#define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001

Definition at line 802 of file reg.h.

#define AR5K_DCU_FP_NOBURST_EN 0x00000010

Definition at line 803 of file reg.h.

#define AR5K_DCU_FP_BURST_DCU_EN 0x00000020

Definition at line 804 of file reg.h.

#define AR5K_DCU_TXP 0x1270

Definition at line 809 of file reg.h.

#define AR5K_DCU_TXP_M 0x000003ff

Definition at line 810 of file reg.h.

#define AR5K_DCU_TXP_STATUS 0x00010000

Definition at line 811 of file reg.h.

#define AR5K_DCU_TX_FILTER_0_BASE 0x1038

Definition at line 818 of file reg.h.

#define AR5K_DCU_TX_FILTER_0 ( _n ) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64))

Definition at line 819 of file reg.h.

#define AR5K_DCU_TX_FILTER_1_BASE 0x103c

Definition at line 824 of file reg.h.

#define AR5K_DCU_TX_FILTER_1 ( _n ) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64))

Definition at line 825 of file reg.h.

#define AR5K_DCU_TX_FILTER_CLR 0x143c

Definition at line 830 of file reg.h.

#define AR5K_DCU_TX_FILTER_SET 0x147c

Definition at line 835 of file reg.h.

#define AR5K_RESET_CTL 0x4000

Definition at line 840 of file reg.h.

Referenced by ath5k_hw_nic_reset().

#define AR5K_RESET_CTL_PCU 0x00000001

Definition at line 841 of file reg.h.

Referenced by ath5k_hw_nic_reset(), and ath5k_hw_nic_wakeup().

#define AR5K_RESET_CTL_DMA 0x00000002

Definition at line 842 of file reg.h.

Referenced by ath5k_hw_nic_reset(), and ath5k_hw_nic_wakeup().

#define AR5K_RESET_CTL_BASEBAND 0x00000002

Definition at line 843 of file reg.h.

Referenced by ath5k_hw_nic_reset(), and ath5k_hw_nic_wakeup().

#define AR5K_RESET_CTL_MAC 0x00000004

Definition at line 844 of file reg.h.

Referenced by ath5k_hw_nic_reset(), and ath5k_hw_nic_wakeup().

#define AR5K_RESET_CTL_PHY 0x00000008

Definition at line 845 of file reg.h.

Referenced by ath5k_hw_nic_reset(), and ath5k_hw_nic_wakeup().

#define AR5K_RESET_CTL_PCI 0x00000010

Definition at line 846 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_SLEEP_CTL 0x4004

Definition at line 851 of file reg.h.

Referenced by ath5k_hw_wake().

#define AR5K_SLEEP_CTL_SLDUR 0x0000ffff

Definition at line 852 of file reg.h.

#define AR5K_SLEEP_CTL_SLDUR_S 0

Definition at line 853 of file reg.h.

#define AR5K_SLEEP_CTL_SLE 0x00030000

Definition at line 854 of file reg.h.

#define AR5K_SLEEP_CTL_SLE_S 16

Definition at line 855 of file reg.h.

#define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000

Definition at line 856 of file reg.h.

#define AR5K_SLEEP_CTL_SLE_SLP 0x00010000

Definition at line 857 of file reg.h.

#define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000

Definition at line 858 of file reg.h.

#define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008

Definition at line 859 of file reg.h.

#define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000

Definition at line 860 of file reg.h.

#define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000

Definition at line 861 of file reg.h.

#define AR5K_SLEEP_CTL_SLE_POL 0x00100000

Definition at line 862 of file reg.h.

#define AR5K_INTPEND 0x4008

Definition at line 867 of file reg.h.

Referenced by ath5k_hw_is_intr_pending().

#define AR5K_INTPEND_M 0x00000001

Definition at line 868 of file reg.h.

#define AR5K_SFR 0x400c

Definition at line 873 of file reg.h.

#define AR5K_SFR_EN 0x00000001

Definition at line 874 of file reg.h.

#define AR5K_PCICFG 0x4010

Definition at line 880 of file reg.h.

Referenced by ath5k_hw_attach(), ath5k_hw_eeprom_read(), ath5k_hw_reset(), and ath5k_hw_wake().

#define AR5K_PCICFG_EEAE 0x00000001

Definition at line 881 of file reg.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002

Definition at line 882 of file reg.h.

#define AR5K_PCICFG_CLKRUNEN 0x00000004

Definition at line 883 of file reg.h.

#define AR5K_PCICFG_EESIZE 0x00000018

Definition at line 884 of file reg.h.

#define AR5K_PCICFG_EESIZE_S 3

Definition at line 885 of file reg.h.

#define AR5K_PCICFG_EESIZE_4K 0

Definition at line 886 of file reg.h.

#define AR5K_PCICFG_EESIZE_8K 1

Definition at line 887 of file reg.h.

#define AR5K_PCICFG_EESIZE_16K 2

Definition at line 888 of file reg.h.

#define AR5K_PCICFG_EESIZE_FAIL 3

Definition at line 889 of file reg.h.

#define AR5K_PCICFG_LED 0x00000060

Definition at line 890 of file reg.h.

#define AR5K_PCICFG_LED_NONE 0x00000000

Definition at line 891 of file reg.h.

#define AR5K_PCICFG_LED_PEND 0x00000020

Definition at line 892 of file reg.h.

#define AR5K_PCICFG_LED_ASSOC 0x00000040

Definition at line 893 of file reg.h.

#define AR5K_PCICFG_BUS_SEL 0x00000380

Definition at line 894 of file reg.h.

#define AR5K_PCICFG_CBEFIX_DIS 0x00000400

Definition at line 895 of file reg.h.

#define AR5K_PCICFG_SL_INTEN 0x00000800

Definition at line 896 of file reg.h.

#define AR5K_PCICFG_LED_BCTL 0x00001000

Definition at line 897 of file reg.h.

#define AR5K_PCICFG_RETRY_FIX 0x00001000

Definition at line 898 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_PCICFG_SL_INPEN 0x00002000

Definition at line 899 of file reg.h.

#define AR5K_PCICFG_SPWR_DN 0x00010000

Definition at line 900 of file reg.h.

Referenced by ath5k_hw_wake().

#define AR5K_PCICFG_LEDMODE 0x000e0000

Definition at line 901 of file reg.h.

#define AR5K_PCICFG_LEDMODE_PROP 0x00000000

Definition at line 902 of file reg.h.

#define AR5K_PCICFG_LEDMODE_PROM 0x00020000

Definition at line 903 of file reg.h.

#define AR5K_PCICFG_LEDMODE_PWR 0x00040000

Definition at line 904 of file reg.h.

#define AR5K_PCICFG_LEDMODE_RAND 0x00060000

Definition at line 905 of file reg.h.

#define AR5K_PCICFG_LEDBLINK 0x00700000

Definition at line 906 of file reg.h.

#define AR5K_PCICFG_LEDBLINK_S 20

Definition at line 907 of file reg.h.

#define AR5K_PCICFG_LEDSLOW 0x00800000

Definition at line 908 of file reg.h.

#define AR5K_PCICFG_LEDSTATE

Value:

(AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE |        \
        AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW)

Definition at line 909 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000

Definition at line 912 of file reg.h.

#define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24

Definition at line 913 of file reg.h.

#define AR5K_NUM_GPIO 6

Definition at line 931 of file reg.h.

Referenced by ath5k_hw_get_gpio(), ath5k_hw_set_capabilities(), ath5k_hw_set_gpio(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), and ath5k_hw_set_gpio_output().

#define AR5K_GPIOCR 0x4014

Definition at line 933 of file reg.h.

Referenced by ath5k_hw_reset(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), and ath5k_hw_set_gpio_output().

#define AR5K_GPIOCR_INT_ENA 0x00008000

Definition at line 934 of file reg.h.

Referenced by ath5k_hw_set_gpio_intr().

#define AR5K_GPIOCR_INT_SELL 0x00000000

Definition at line 935 of file reg.h.

#define AR5K_GPIOCR_INT_SELH 0x00010000

Definition at line 936 of file reg.h.

Referenced by ath5k_hw_set_gpio_intr().

#define AR5K_GPIOCR_IN ( n ) (0 << ((n) * 2))

Definition at line 937 of file reg.h.

Referenced by ath5k_hw_set_gpio_input().

#define AR5K_GPIOCR_OUT0 ( n ) (1 << ((n) * 2))

Definition at line 938 of file reg.h.

#define AR5K_GPIOCR_OUT1 ( n ) (2 << ((n) * 2))

Definition at line 939 of file reg.h.

#define AR5K_GPIOCR_OUT ( n ) (3 << ((n) * 2))

Definition at line 940 of file reg.h.

Referenced by ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), and ath5k_hw_set_gpio_output().

#define AR5K_GPIOCR_INT_SEL ( n ) ((n) << 12)

Definition at line 941 of file reg.h.

Referenced by ath5k_hw_set_gpio_intr().

#define AR5K_GPIODO 0x4018

Definition at line 946 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_set_gpio().

#define AR5K_GPIODI 0x401c

Definition at line 951 of file reg.h.

Referenced by ath5k_hw_get_gpio().

#define AR5K_GPIODI_M 0x0000002f

Definition at line 952 of file reg.h.

Referenced by ath5k_hw_get_gpio().

#define AR5K_SREV 0x4020

Definition at line 957 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_REV 0x0000000f

Definition at line 958 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_REV_S 0

Definition at line 959 of file reg.h.

#define AR5K_SREV_VER 0x000000ff

Definition at line 960 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_SREV_VER_S 4

Definition at line 961 of file reg.h.

#define AR5K_TXEPOST 0x4028

Definition at line 966 of file reg.h.

#define AR5K_QCU_SLEEP_MASK 0x402c

Definition at line 971 of file reg.h.

#define AR5K_5414_CBCFG 0x4068

Definition at line 981 of file reg.h.

#define AR5K_5414_CBCFG_BUF_DIS 0x10

Definition at line 982 of file reg.h.

#define AR5K_PCIE_PM_CTL 0x4068

Definition at line 988 of file reg.h.

#define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001

Definition at line 990 of file reg.h.

#define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002

Definition at line 992 of file reg.h.

#define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004

Definition at line 993 of file reg.h.

#define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008

Definition at line 994 of file reg.h.

#define AR5K_PCIE_PM_CTL_PME_EN 0x00000010

Definition at line 997 of file reg.h.

#define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020

Definition at line 998 of file reg.h.

#define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040

Definition at line 999 of file reg.h.

#define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080

Definition at line 1000 of file reg.h.

#define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100

Definition at line 1001 of file reg.h.

#define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200

Definition at line 1002 of file reg.h.

#define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400

Definition at line 1003 of file reg.h.

#define AR5K_PCIE_WAEN 0x407c

Definition at line 1008 of file reg.h.

#define AR5K_PCIE_SERDES 0x4080

Definition at line 1014 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_PCIE_SERDES_RESET 0x4084

Definition at line 1015 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_EEPROM_BASE 0x6000

Definition at line 1054 of file reg.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_EEPROM_DATA_5211 0x6004

Definition at line 1059 of file reg.h.

#define AR5K_EEPROM_DATA_5210 0x6800

Definition at line 1060 of file reg.h.

#define AR5K_EEPROM_DATA

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211)

Definition at line 1061 of file reg.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_EEPROM_CMD 0x6008

Definition at line 1067 of file reg.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_EEPROM_CMD_READ 0x00000001

Definition at line 1068 of file reg.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_EEPROM_CMD_WRITE 0x00000002

Definition at line 1069 of file reg.h.

#define AR5K_EEPROM_CMD_RESET 0x00000004

Definition at line 1070 of file reg.h.

#define AR5K_EEPROM_STAT_5210 0x6c00

Definition at line 1075 of file reg.h.

#define AR5K_EEPROM_STAT_5211 0x600c

Definition at line 1076 of file reg.h.

#define AR5K_EEPROM_STATUS

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211)

Definition at line 1077 of file reg.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_EEPROM_STAT_RDERR 0x00000001

Definition at line 1079 of file reg.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_EEPROM_STAT_RDDONE 0x00000002

Definition at line 1080 of file reg.h.

Referenced by ath5k_hw_eeprom_read().

#define AR5K_EEPROM_STAT_WRERR 0x00000004

Definition at line 1081 of file reg.h.

#define AR5K_EEPROM_STAT_WRDONE 0x00000008

Definition at line 1082 of file reg.h.

#define AR5K_EEPROM_CFG 0x6010

Definition at line 1087 of file reg.h.

#define AR5K_EEPROM_CFG_SIZE 0x00000003

Definition at line 1088 of file reg.h.

#define AR5K_EEPROM_CFG_SIZE_AUTO 0

Definition at line 1089 of file reg.h.

#define AR5K_EEPROM_CFG_SIZE_4KBIT 1

Definition at line 1090 of file reg.h.

#define AR5K_EEPROM_CFG_SIZE_8KBIT 2

Definition at line 1091 of file reg.h.

#define AR5K_EEPROM_CFG_SIZE_16KBIT 3

Definition at line 1092 of file reg.h.

#define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004

Definition at line 1093 of file reg.h.

#define AR5K_EEPROM_CFG_CLK_RATE 0x00000018

Definition at line 1094 of file reg.h.

#define AR5K_EEPROM_CFG_CLK_RATE_S 3

Definition at line 1095 of file reg.h.

#define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0

Definition at line 1096 of file reg.h.

#define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1

Definition at line 1097 of file reg.h.

#define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2

Definition at line 1098 of file reg.h.

#define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00

Definition at line 1099 of file reg.h.

#define AR5K_EEPROM_CFG_PROT_KEY_S 8

Definition at line 1100 of file reg.h.

#define AR5K_EEPROM_CFG_LIND_EN 0x01000000

Definition at line 1101 of file reg.h.

#define AR5K_PCU_MIN 0x8000

Definition at line 1116 of file reg.h.

Referenced by ath5k_hw_ini_registers().

#define AR5K_PCU_MAX 0x8fff

Definition at line 1117 of file reg.h.

Referenced by ath5k_hw_ini_registers().

#define AR5K_STA_ID0 0x8000

Definition at line 1122 of file reg.h.

Referenced by ath5k_hw_post(), ath5k_hw_reset(), ath5k_hw_set_lladdr(), and ath5k_hw_set_opmode().

#define AR5K_STA_ID0_ARRD_L32 0xffffffff

Definition at line 1123 of file reg.h.

#define AR5K_STA_ID1 0x8004

Definition at line 1128 of file reg.h.

Referenced by ath5k_hw_reset(), ath5k_hw_set_ack_bitrate_high(), ath5k_hw_set_lladdr(), ath5k_hw_set_opmode(), and ath5k_hw_wake().

#define AR5K_STA_ID1_ADDR_U16 0x0000ffff

Definition at line 1129 of file reg.h.

#define AR5K_STA_ID1_AP 0x00010000

Definition at line 1130 of file reg.h.

Referenced by ath5k_hw_set_opmode().

#define AR5K_STA_ID1_ADHOC 0x00020000

Definition at line 1131 of file reg.h.

Referenced by ath5k_hw_set_opmode().

#define AR5K_STA_ID1_PWR_SV 0x00040000

Definition at line 1132 of file reg.h.

Referenced by ath5k_hw_set_opmode(), and ath5k_hw_wake().

#define AR5K_STA_ID1_NO_KEYSRCH 0x00080000

Definition at line 1133 of file reg.h.

#define AR5K_STA_ID1_NO_PSPOLL 0x00100000

Definition at line 1134 of file reg.h.

Referenced by ath5k_hw_set_opmode().

#define AR5K_STA_ID1_PCF_5211 0x00100000

Definition at line 1135 of file reg.h.

#define AR5K_STA_ID1_PCF_5210 0x00200000

Definition at line 1136 of file reg.h.

#define AR5K_STA_ID1_PCF

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211)

Definition at line 1137 of file reg.h.

#define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000

Definition at line 1139 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_STA_ID1_DESC_ANTENNA 0x00400000

Definition at line 1140 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000

Definition at line 1141 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_STA_ID1_ACKCTS_6MB 0x01000000

Definition at line 1142 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_set_ack_bitrate_high().

#define AR5K_STA_ID1_BASE_RATE_11B 0x02000000

Definition at line 1143 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_set_ack_bitrate_high().

#define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000

Definition at line 1144 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000

Definition at line 1145 of file reg.h.

#define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000

Definition at line 1146 of file reg.h.

Referenced by ath5k_hw_set_opmode().

#define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000

Definition at line 1147 of file reg.h.

#define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000

Definition at line 1148 of file reg.h.

#define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000

Definition at line 1149 of file reg.h.

#define AR5K_BSS_ID0 0x8008

Definition at line 1154 of file reg.h.

Referenced by ath5k_hw_set_associd().

#define AR5K_BSS_ID1 0x800c

Definition at line 1161 of file reg.h.

Referenced by ath5k_hw_set_associd().

#define AR5K_BSS_ID1_AID 0xffff0000

Definition at line 1162 of file reg.h.

#define AR5K_BSS_ID1_AID_S 16

Definition at line 1163 of file reg.h.

Referenced by ath5k_hw_set_associd().

#define AR5K_SLOT_TIME 0x8010

Definition at line 1168 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue(), and ath5k_hw_set_slot_time().

#define AR5K_TIME_OUT 0x8014

Definition at line 1173 of file reg.h.

Referenced by ath5k_hw_get_ack_timeout(), ath5k_hw_get_cts_timeout(), ath5k_hw_set_ack_timeout(), and ath5k_hw_set_cts_timeout().

#define AR5K_TIME_OUT_ACK 0x00001fff

Definition at line 1174 of file reg.h.

Referenced by ath5k_hw_get_ack_timeout(), and ath5k_hw_set_ack_timeout().

#define AR5K_TIME_OUT_ACK_S 0

Definition at line 1175 of file reg.h.

#define AR5K_TIME_OUT_CTS 0x1fff0000

Definition at line 1176 of file reg.h.

Referenced by ath5k_hw_get_cts_timeout(), and ath5k_hw_set_cts_timeout().

#define AR5K_TIME_OUT_CTS_S 16

Definition at line 1177 of file reg.h.

#define AR5K_RSSI_THR 0x8018

Definition at line 1182 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_RSSI_THR_M 0x000000ff

Definition at line 1183 of file reg.h.

#define AR5K_RSSI_THR_BMISS_5210 0x00000700

Definition at line 1184 of file reg.h.

#define AR5K_RSSI_THR_BMISS_5210_S 8

Definition at line 1185 of file reg.h.

#define AR5K_RSSI_THR_BMISS_5211 0x0000ff00

Definition at line 1186 of file reg.h.

#define AR5K_RSSI_THR_BMISS_5211_S 8

Definition at line 1187 of file reg.h.

#define AR5K_RSSI_THR_BMISS

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211)

Definition at line 1188 of file reg.h.

#define AR5K_RSSI_THR_BMISS_S 8

Definition at line 1190 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_NODCU_RETRY_LMT 0x801c

Definition at line 1205 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f

Definition at line 1206 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0

Definition at line 1207 of file reg.h.

#define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0

Definition at line 1208 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4

Definition at line 1209 of file reg.h.

#define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00

Definition at line 1210 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8

Definition at line 1211 of file reg.h.

#define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000

Definition at line 1212 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14

Definition at line 1213 of file reg.h.

#define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000

Definition at line 1214 of file reg.h.

#define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20

Definition at line 1215 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_USEC_5210 0x8020

Definition at line 1220 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_USEC_5211 0x801c

Definition at line 1221 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_USEC

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_USEC_5210 : AR5K_USEC_5211)

Definition at line 1222 of file reg.h.

#define AR5K_USEC_1 0x0000007f

Definition at line 1224 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_USEC_1_S 0

Definition at line 1225 of file reg.h.

#define AR5K_USEC_32 0x00003f80

Definition at line 1226 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_USEC_32_S 7

Definition at line 1227 of file reg.h.

#define AR5K_USEC_TX_LATENCY_5211 0x007fc000

Definition at line 1228 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_USEC_TX_LATENCY_5211_S 14

Definition at line 1229 of file reg.h.

#define AR5K_USEC_RX_LATENCY_5211 0x1f800000

Definition at line 1230 of file reg.h.

#define AR5K_USEC_RX_LATENCY_5211_S 23

Definition at line 1231 of file reg.h.

#define AR5K_USEC_TX_LATENCY_5210 0x000fc000

Definition at line 1232 of file reg.h.

#define AR5K_USEC_TX_LATENCY_5210_S 14

Definition at line 1233 of file reg.h.

#define AR5K_USEC_RX_LATENCY_5210 0x03f00000

Definition at line 1234 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_USEC_RX_LATENCY_5210_S 20

Definition at line 1235 of file reg.h.

#define AR5K_BEACON_5210 0x8024

Definition at line 1240 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_BEACON_5211 0x8020

Definition at line 1241 of file reg.h.

#define AR5K_BEACON

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_BEACON_5210 : AR5K_BEACON_5211)

Definition at line 1242 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_BEACON_PERIOD 0x0000ffff

Definition at line 1244 of file reg.h.

#define AR5K_BEACON_PERIOD_S 0

Definition at line 1245 of file reg.h.

#define AR5K_BEACON_TIM 0x007f0000

Definition at line 1246 of file reg.h.

#define AR5K_BEACON_TIM_S 16

Definition at line 1247 of file reg.h.

#define AR5K_BEACON_ENABLE 0x00800000

Definition at line 1248 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_rf5110_calibrate().

#define AR5K_BEACON_RESET_TSF 0x01000000

Definition at line 1249 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_CFP_PERIOD_5210 0x8028

Definition at line 1254 of file reg.h.

#define AR5K_CFP_PERIOD_5211 0x8024

Definition at line 1255 of file reg.h.

#define AR5K_CFP_PERIOD

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211)

Definition at line 1256 of file reg.h.

#define AR5K_TIMER0_5210 0x802c

Definition at line 1262 of file reg.h.

#define AR5K_TIMER0_5211 0x8028

Definition at line 1263 of file reg.h.

#define AR5K_TIMER0

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_TIMER0_5210 : AR5K_TIMER0_5211)

Definition at line 1264 of file reg.h.

#define AR5K_TIMER1_5210 0x8030

Definition at line 1270 of file reg.h.

#define AR5K_TIMER1_5211 0x802c

Definition at line 1271 of file reg.h.

#define AR5K_TIMER1

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_TIMER1_5210 : AR5K_TIMER1_5211)

Definition at line 1272 of file reg.h.

#define AR5K_TIMER2_5210 0x8034

Definition at line 1278 of file reg.h.

#define AR5K_TIMER2_5211 0x8030

Definition at line 1279 of file reg.h.

#define AR5K_TIMER2

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_TIMER2_5210 : AR5K_TIMER2_5211)

Definition at line 1280 of file reg.h.

#define AR5K_TIMER3_5210 0x8038

Definition at line 1286 of file reg.h.

#define AR5K_TIMER3_5211 0x8034

Definition at line 1287 of file reg.h.

#define AR5K_TIMER3

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_TIMER3_5210 : AR5K_TIMER3_5211)

Definition at line 1288 of file reg.h.

#define AR5K_IFS0 0x8040

Definition at line 1295 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_IFS0_SIFS 0x000007ff

Definition at line 1296 of file reg.h.

#define AR5K_IFS0_SIFS_S 0

Definition at line 1297 of file reg.h.

#define AR5K_IFS0_DIFS 0x007ff800

Definition at line 1298 of file reg.h.

#define AR5K_IFS0_DIFS_S 11

Definition at line 1299 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_IFS1 0x8044

Definition at line 1304 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_IFS1_PIFS 0x00000fff

Definition at line 1305 of file reg.h.

#define AR5K_IFS1_PIFS_S 0

Definition at line 1306 of file reg.h.

#define AR5K_IFS1_EIFS 0x03fff000

Definition at line 1307 of file reg.h.

#define AR5K_IFS1_EIFS_S 12

Definition at line 1308 of file reg.h.

#define AR5K_IFS1_CS_EN 0x04000000

Definition at line 1309 of file reg.h.

#define AR5K_CFP_DUR_5210 0x8048

Definition at line 1315 of file reg.h.

#define AR5K_CFP_DUR_5211 0x8038

Definition at line 1316 of file reg.h.

#define AR5K_CFP_DUR

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211)

Definition at line 1317 of file reg.h.

#define AR5K_RX_FILTER_5210 0x804c

Definition at line 1323 of file reg.h.

#define AR5K_RX_FILTER_5211 0x803c

Definition at line 1324 of file reg.h.

#define AR5K_RX_FILTER

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211)

Definition at line 1325 of file reg.h.

Referenced by ath5k_hw_get_rx_filter(), and ath5k_hw_set_rx_filter().

#define AR5K_RX_FILTER_UCAST 0x00000001

Definition at line 1327 of file reg.h.

Referenced by ath5k_configure_filter().

#define AR5K_RX_FILTER_MCAST 0x00000002

Definition at line 1328 of file reg.h.

Referenced by ath5k_configure_filter().

#define AR5K_RX_FILTER_BCAST 0x00000004

Definition at line 1329 of file reg.h.

Referenced by ath5k_configure_filter().

#define AR5K_RX_FILTER_CONTROL 0x00000008

Definition at line 1330 of file reg.h.

#define AR5K_RX_FILTER_BEACON 0x00000010

Definition at line 1331 of file reg.h.

Referenced by ath5k_configure_filter().

#define AR5K_RX_FILTER_PROM 0x00000020

Definition at line 1332 of file reg.h.

Referenced by ath5k_hw_set_rx_filter().

#define AR5K_RX_FILTER_XRPOLL 0x00000040

Definition at line 1333 of file reg.h.

#define AR5K_RX_FILTER_PROBEREQ 0x00000080

Definition at line 1334 of file reg.h.

#define AR5K_RX_FILTER_PHYERR_5212 0x00000100

Definition at line 1335 of file reg.h.

#define AR5K_RX_FILTER_RADARERR_5212 0x00000200

Definition at line 1336 of file reg.h.

#define AR5K_RX_FILTER_PHYERR_5211 0x00000040

Definition at line 1337 of file reg.h.

#define AR5K_RX_FILTER_RADARERR_5211 0x00000080

Definition at line 1338 of file reg.h.

#define AR5K_RX_FILTER_PHYERR

Value:

((ah->ah_version == AR5K_AR5211 ? \
        AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212))

Definition at line 1339 of file reg.h.

Referenced by ath5k_hw_get_rx_filter(), and ath5k_hw_set_rx_filter().

#define AR5K_RX_FILTER_RADARERR

Value:

((ah->ah_version == AR5K_AR5211 ? \
        AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212))

Definition at line 1342 of file reg.h.

Referenced by ath5k_hw_get_rx_filter(), and ath5k_hw_set_rx_filter().

#define AR5K_MCAST_FILTER0_5210 0x8050

Definition at line 1349 of file reg.h.

#define AR5K_MCAST_FILTER0_5211 0x8040

Definition at line 1350 of file reg.h.

#define AR5K_MCAST_FILTER0

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211)

Definition at line 1351 of file reg.h.

Referenced by ath5k_hw_set_mcast_filter().

#define AR5K_MCAST_FILTER1_5210 0x8054

Definition at line 1357 of file reg.h.

#define AR5K_MCAST_FILTER1_5211 0x8044

Definition at line 1358 of file reg.h.

#define AR5K_MCAST_FILTER1

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211)

Definition at line 1359 of file reg.h.

Referenced by ath5k_hw_set_mcast_filter().

#define AR5K_TX_MASK0 0x8058

Definition at line 1366 of file reg.h.

#define AR5K_TX_MASK1 0x805c

Definition at line 1371 of file reg.h.

#define AR5K_CLR_TMASK 0x8060

Definition at line 1376 of file reg.h.

#define AR5K_TRIG_LVL 0x8064

Definition at line 1381 of file reg.h.

Referenced by ath5k_hw_update_tx_triglevel().

#define AR5K_DIAG_SW_5210 0x8068

Definition at line 1390 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_DIAG_SW_5211 0x8048

Definition at line 1391 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma(), and ath5k_hw_tweak_initval_settings().

#define AR5K_DIAG_SW

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211)

Definition at line 1392 of file reg.h.

Referenced by ath5k_hw_start_rx_pcu(), and ath5k_hw_stop_rx_pcu().

#define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001

Definition at line 1394 of file reg.h.

#define AR5K_DIAG_SW_DIS_ACK 0x00000002

Definition at line 1395 of file reg.h.

#define AR5K_DIAG_SW_DIS_CTS 0x00000004

Definition at line 1396 of file reg.h.

#define AR5K_DIAG_SW_DIS_ENC 0x00000008

Definition at line 1397 of file reg.h.

#define AR5K_DIAG_SW_DIS_DEC 0x00000010

Definition at line 1398 of file reg.h.

#define AR5K_DIAG_SW_DIS_TX 0x00000020

Definition at line 1399 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_DIAG_SW_DIS_RX_5210 0x00000040

Definition at line 1400 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_DIAG_SW_DIS_RX_5211 0x00000020

Definition at line 1401 of file reg.h.

#define AR5K_DIAG_SW_DIS_RX

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211)

Definition at line 1402 of file reg.h.

Referenced by ath5k_hw_start_rx_pcu(), and ath5k_hw_stop_rx_pcu().

#define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080

Definition at line 1404 of file reg.h.

#define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040

Definition at line 1405 of file reg.h.

#define AR5K_DIAG_SW_LOOP_BACK

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211)

Definition at line 1406 of file reg.h.

#define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100

Definition at line 1408 of file reg.h.

#define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080

Definition at line 1409 of file reg.h.

#define AR5K_DIAG_SW_CORR_FCS

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211)

Definition at line 1410 of file reg.h.

#define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200

Definition at line 1412 of file reg.h.

#define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100

Definition at line 1413 of file reg.h.

#define AR5K_DIAG_SW_CHAN_INFO

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211)

Definition at line 1414 of file reg.h.

#define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400

Definition at line 1416 of file reg.h.

#define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200

Definition at line 1417 of file reg.h.

#define AR5K_DIAG_SW_EN_SCRAM_SEED

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211)

Definition at line 1418 of file reg.h.

#define AR5K_DIAG_SW_ECO_ENABLE 0x00000400

Definition at line 1420 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800

Definition at line 1421 of file reg.h.

#define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00

Definition at line 1422 of file reg.h.

#define AR5K_DIAG_SW_SCRAM_SEED_S 10

Definition at line 1423 of file reg.h.

#define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000

Definition at line 1424 of file reg.h.

#define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000

Definition at line 1425 of file reg.h.

#define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000

Definition at line 1426 of file reg.h.

#define AR5K_DIAG_SW_FRAME_NV0

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211)

Definition at line 1427 of file reg.h.

#define AR5K_DIAG_SW_OBSPT_M 0x000c0000

Definition at line 1429 of file reg.h.

#define AR5K_DIAG_SW_OBSPT_S 18

Definition at line 1430 of file reg.h.

#define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000

Definition at line 1431 of file reg.h.

#define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000

Definition at line 1432 of file reg.h.

#define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000

Definition at line 1433 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_DIAG_SW_PHEAR_ME 0x0080000

Definition at line 1434 of file reg.h.

#define AR5K_TSF_L32_5210 0x806c

Definition at line 1439 of file reg.h.

#define AR5K_TSF_L32_5211 0x804c

Definition at line 1440 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_TSF_L32

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211)

Definition at line 1441 of file reg.h.

#define AR5K_TSF_U32_5210 0x8070

Definition at line 1447 of file reg.h.

#define AR5K_TSF_U32_5211 0x8050

Definition at line 1448 of file reg.h.

#define AR5K_TSF_U32

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211)

Definition at line 1449 of file reg.h.

#define AR5K_LAST_TSTP 0x8080

Definition at line 1455 of file reg.h.

#define AR5K_ADDAC_TEST 0x8054

Definition at line 1460 of file reg.h.

#define AR5K_ADDAC_TEST_TXCONT 0x00000001

Definition at line 1461 of file reg.h.

#define AR5K_ADDAC_TEST_TST_MODE 0x00000002

Definition at line 1462 of file reg.h.

#define AR5K_ADDAC_TEST_LOOP_EN 0x00000004

Definition at line 1463 of file reg.h.

#define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008

Definition at line 1464 of file reg.h.

#define AR5K_ADDAC_TEST_USE_U8 0x00004000

Definition at line 1465 of file reg.h.

#define AR5K_ADDAC_TEST_MSB 0x00008000

Definition at line 1466 of file reg.h.

#define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000

Definition at line 1467 of file reg.h.

#define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000

Definition at line 1468 of file reg.h.

#define AR5K_ADDAC_TEST_RXCONT 0x00040000

Definition at line 1469 of file reg.h.

#define AR5K_ADDAC_TEST_CAPTURE 0x00080000

Definition at line 1470 of file reg.h.

#define AR5K_ADDAC_TEST_TST_ARM 0x00100000

Definition at line 1471 of file reg.h.

#define AR5K_DEFAULT_ANTENNA 0x8058

Definition at line 1476 of file reg.h.

Referenced by ath5k_hw_get_def_antenna(), ath5k_hw_reset(), and ath5k_hw_set_def_antenna().

#define AR5K_FRAME_CTL_QOSM 0x805c

Definition at line 1482 of file reg.h.

#define AR5K_SEQ_MASK 0x8060

Definition at line 1487 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_RETRY_CNT 0x8084

Definition at line 1492 of file reg.h.

#define AR5K_RETRY_CNT_SSH 0x0000003f

Definition at line 1493 of file reg.h.

#define AR5K_RETRY_CNT_SLG 0x00000fc0

Definition at line 1494 of file reg.h.

#define AR5K_BACKOFF 0x8088

Definition at line 1499 of file reg.h.

#define AR5K_BACKOFF_CW 0x000003ff

Definition at line 1500 of file reg.h.

#define AR5K_BACKOFF_CNT 0x03ff0000

Definition at line 1501 of file reg.h.

#define AR5K_NAV_5210 0x808c

Definition at line 1508 of file reg.h.

#define AR5K_NAV_5211 0x8084

Definition at line 1509 of file reg.h.

#define AR5K_NAV

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_NAV_5210 : AR5K_NAV_5211)

Definition at line 1510 of file reg.h.

#define AR5K_RTS_OK_5210 0x8090

Definition at line 1516 of file reg.h.

#define AR5K_RTS_OK_5211 0x8088

Definition at line 1517 of file reg.h.

#define AR5K_RTS_OK

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211)

Definition at line 1518 of file reg.h.

#define AR5K_RTS_FAIL_5210 0x8094

Definition at line 1524 of file reg.h.

#define AR5K_RTS_FAIL_5211 0x808c

Definition at line 1525 of file reg.h.

#define AR5K_RTS_FAIL

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211)

Definition at line 1526 of file reg.h.

#define AR5K_ACK_FAIL_5210 0x8098

Definition at line 1532 of file reg.h.

#define AR5K_ACK_FAIL_5211 0x8090

Definition at line 1533 of file reg.h.

#define AR5K_ACK_FAIL

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211)

Definition at line 1534 of file reg.h.

#define AR5K_FCS_FAIL_5210 0x809c

Definition at line 1540 of file reg.h.

#define AR5K_FCS_FAIL_5211 0x8094

Definition at line 1541 of file reg.h.

#define AR5K_FCS_FAIL

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211)

Definition at line 1542 of file reg.h.

#define AR5K_BEACON_CNT_5210 0x80a0

Definition at line 1548 of file reg.h.

#define AR5K_BEACON_CNT_5211 0x8098

Definition at line 1549 of file reg.h.

#define AR5K_BEACON_CNT

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211)

Definition at line 1550 of file reg.h.

#define AR5K_TPC 0x80e8

Definition at line 1559 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_TPC_ACK 0x0000003f

Definition at line 1560 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_TPC_ACK_S 0

Definition at line 1561 of file reg.h.

#define AR5K_TPC_CTS 0x00003f00

Definition at line 1562 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_TPC_CTS_S 8

Definition at line 1563 of file reg.h.

#define AR5K_TPC_CHIRP 0x003f0000

Definition at line 1564 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_TPC_CHIRP_S 16

Definition at line 1565 of file reg.h.

#define AR5K_TPC_DOPPLER 0x0f000000

Definition at line 1566 of file reg.h.

#define AR5K_TPC_DOPPLER_S 24

Definition at line 1567 of file reg.h.

#define AR5K_XRMODE 0x80c0

Definition at line 1572 of file reg.h.

#define AR5K_XRMODE_POLL_TYPE_M 0x0000003f

Definition at line 1573 of file reg.h.

#define AR5K_XRMODE_POLL_TYPE_S 0

Definition at line 1574 of file reg.h.

#define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c

Definition at line 1575 of file reg.h.

#define AR5K_XRMODE_POLL_SUBTYPE_S 2

Definition at line 1576 of file reg.h.

#define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080

Definition at line 1577 of file reg.h.

#define AR5K_XRMODE_SIFS_DELAY 0x000fff00

Definition at line 1578 of file reg.h.

#define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000

Definition at line 1579 of file reg.h.

#define AR5K_XRMODE_FRAME_HOLD_S 20

Definition at line 1580 of file reg.h.

#define AR5K_XRDELAY 0x80c4

Definition at line 1585 of file reg.h.

#define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff

Definition at line 1586 of file reg.h.

#define AR5K_XRDELAY_SLOT_DELAY_S 0

Definition at line 1587 of file reg.h.

#define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000

Definition at line 1588 of file reg.h.

#define AR5K_XRDELAY_CHIRP_DELAY_S 16

Definition at line 1589 of file reg.h.

#define AR5K_XRTIMEOUT 0x80c8

Definition at line 1594 of file reg.h.

#define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff

Definition at line 1595 of file reg.h.

#define AR5K_XRTIMEOUT_CHIRP_S 0

Definition at line 1596 of file reg.h.

#define AR5K_XRTIMEOUT_POLL_M 0xffff0000

Definition at line 1597 of file reg.h.

#define AR5K_XRTIMEOUT_POLL_S 16

Definition at line 1598 of file reg.h.

#define AR5K_XRCHIRP 0x80cc

Definition at line 1603 of file reg.h.

#define AR5K_XRCHIRP_SEND 0x00000001

Definition at line 1604 of file reg.h.

#define AR5K_XRCHIRP_GAP 0xffff0000

Definition at line 1605 of file reg.h.

#define AR5K_XRSTOMP 0x80d0

Definition at line 1610 of file reg.h.

#define AR5K_XRSTOMP_TX 0x00000001

Definition at line 1611 of file reg.h.

#define AR5K_XRSTOMP_RX 0x00000002

Definition at line 1612 of file reg.h.

#define AR5K_XRSTOMP_TX_RSSI 0x00000004

Definition at line 1613 of file reg.h.

#define AR5K_XRSTOMP_TX_BSSID 0x00000008

Definition at line 1614 of file reg.h.

#define AR5K_XRSTOMP_DATA 0x00000010

Definition at line 1615 of file reg.h.

#define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00

Definition at line 1616 of file reg.h.

#define AR5K_SLEEP0 0x80d4

Definition at line 1621 of file reg.h.

#define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff

Definition at line 1622 of file reg.h.

#define AR5K_SLEEP0_NEXT_DTIM_S 0

Definition at line 1623 of file reg.h.

#define AR5K_SLEEP0_ASSUME_DTIM 0x00080000

Definition at line 1624 of file reg.h.

#define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000

Definition at line 1625 of file reg.h.

#define AR5K_SLEEP0_CABTO 0xff000000

Definition at line 1626 of file reg.h.

#define AR5K_SLEEP0_CABTO_S 24

Definition at line 1627 of file reg.h.

#define AR5K_SLEEP1 0x80d8

Definition at line 1632 of file reg.h.

#define AR5K_SLEEP1_NEXT_TIM 0x0007ffff

Definition at line 1633 of file reg.h.

#define AR5K_SLEEP1_NEXT_TIM_S 0

Definition at line 1634 of file reg.h.

#define AR5K_SLEEP1_BEACON_TO 0xff000000

Definition at line 1635 of file reg.h.

#define AR5K_SLEEP1_BEACON_TO_S 24

Definition at line 1636 of file reg.h.

#define AR5K_SLEEP2 0x80dc

Definition at line 1641 of file reg.h.

#define AR5K_SLEEP2_TIM_PER 0x0000ffff

Definition at line 1642 of file reg.h.

#define AR5K_SLEEP2_TIM_PER_S 0

Definition at line 1643 of file reg.h.

#define AR5K_SLEEP2_DTIM_PER 0xffff0000

Definition at line 1644 of file reg.h.

#define AR5K_SLEEP2_DTIM_PER_S 16

Definition at line 1645 of file reg.h.

#define AR5K_BSS_IDM0 0x80e0

Definition at line 1650 of file reg.h.

Referenced by ath5k_hw_set_associd(), and ath5k_hw_set_bssid_mask().

#define AR5K_BSS_IDM1 0x80e4

Definition at line 1651 of file reg.h.

Referenced by ath5k_hw_set_associd(), and ath5k_hw_set_bssid_mask().

#define AR5K_TXPC 0x80e8

Definition at line 1659 of file reg.h.

#define AR5K_TXPC_ACK_M 0x0000003f

Definition at line 1660 of file reg.h.

#define AR5K_TXPC_ACK_S 0

Definition at line 1661 of file reg.h.

#define AR5K_TXPC_CTS_M 0x00003f00

Definition at line 1662 of file reg.h.

#define AR5K_TXPC_CTS_S 8

Definition at line 1663 of file reg.h.

#define AR5K_TXPC_CHIRP_M 0x003f0000

Definition at line 1664 of file reg.h.

#define AR5K_TXPC_CHIRP_S 16

Definition at line 1665 of file reg.h.

#define AR5K_TXPC_DOPPLER 0x0f000000

Definition at line 1666 of file reg.h.

#define AR5K_TXPC_DOPPLER_S 24

Definition at line 1667 of file reg.h.

#define AR5K_PROFCNT_TX 0x80ec

Definition at line 1672 of file reg.h.

#define AR5K_PROFCNT_RX 0x80f0

Definition at line 1673 of file reg.h.

#define AR5K_PROFCNT_RXCLR 0x80f4

Definition at line 1674 of file reg.h.

#define AR5K_PROFCNT_CYCLE 0x80f8

Definition at line 1675 of file reg.h.

#define AR5K_QUIET_CTL1 0x80fc

Definition at line 1680 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff

Definition at line 1681 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0

Definition at line 1682 of file reg.h.

#define AR5K_QUIET_CTL1_QT_EN 0x00010000

Definition at line 1683 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000

Definition at line 1684 of file reg.h.

#define AR5K_QUIET_CTL2 0x8100

Definition at line 1686 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_QUIET_CTL2_QT_PER 0x0000ffff

Definition at line 1687 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_QUIET_CTL2_QT_PER_S 0

Definition at line 1688 of file reg.h.

#define AR5K_QUIET_CTL2_QT_DUR 0xffff0000

Definition at line 1689 of file reg.h.

Referenced by ath5k_hw_stop_tx_dma().

#define AR5K_QUIET_CTL2_QT_DUR_S 16

Definition at line 1690 of file reg.h.

#define AR5K_TSF_PARM 0x8104

Definition at line 1695 of file reg.h.

#define AR5K_TSF_PARM_INC 0x000000ff

Definition at line 1696 of file reg.h.

#define AR5K_TSF_PARM_INC_S 0

Definition at line 1697 of file reg.h.

#define AR5K_QOS_NOACK 0x8108

Definition at line 1702 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f

Definition at line 1703 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_QOS_NOACK_2BIT_VALUES_S 0

Definition at line 1704 of file reg.h.

#define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070

Definition at line 1705 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_QOS_NOACK_BIT_OFFSET_S 4

Definition at line 1706 of file reg.h.

#define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180

Definition at line 1707 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_QOS_NOACK_BYTE_OFFSET_S 7

Definition at line 1708 of file reg.h.

#define AR5K_PHY_ERR_FIL 0x810c

Definition at line 1713 of file reg.h.

Referenced by ath5k_hw_get_rx_filter(), and ath5k_hw_set_rx_filter().

#define AR5K_PHY_ERR_FIL_RADAR 0x00000020

Definition at line 1714 of file reg.h.

Referenced by ath5k_hw_get_rx_filter(), and ath5k_hw_set_rx_filter().

#define AR5K_PHY_ERR_FIL_OFDM 0x00020000

Definition at line 1715 of file reg.h.

Referenced by ath5k_hw_get_rx_filter(), and ath5k_hw_set_rx_filter().

#define AR5K_PHY_ERR_FIL_CCK 0x02000000

Definition at line 1716 of file reg.h.

Referenced by ath5k_hw_get_rx_filter(), and ath5k_hw_set_rx_filter().

#define AR5K_XRLAT_TX 0x8110

Definition at line 1721 of file reg.h.

#define AR5K_ACKSIFS 0x8114

Definition at line 1726 of file reg.h.

#define AR5K_ACKSIFS_INC 0x00000000

Definition at line 1727 of file reg.h.

#define AR5K_MIC_QOS_CTL 0x8118

Definition at line 1732 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_MIC_QOS_CTL_OFF ( _n ) (1 << (_n * 2))

Definition at line 1733 of file reg.h.

#define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000

Definition at line 1734 of file reg.h.

#define AR5K_MIC_QOS_SEL 0x811c

Definition at line 1739 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_MIC_QOS_SEL_OFF ( _n ) (1 << (_n * 4))

Definition at line 1740 of file reg.h.

#define AR5K_MISC_MODE 0x8120

Definition at line 1745 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001

Definition at line 1746 of file reg.h.

#define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002

Definition at line 1747 of file reg.h.

#define AR5K_MISC_MODE_COMBINED_MIC 0x00000004

Definition at line 1748 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_OFDM_FIL_CNT 0x8124

Definition at line 1754 of file reg.h.

#define AR5K_CCK_FIL_CNT 0x8128

Definition at line 1759 of file reg.h.

#define AR5K_PHYERR_CNT1 0x812c

Definition at line 1764 of file reg.h.

#define AR5K_PHYERR_CNT1_MASK 0x8130

Definition at line 1765 of file reg.h.

#define AR5K_PHYERR_CNT2 0x8134

Definition at line 1767 of file reg.h.

#define AR5K_PHYERR_CNT2_MASK 0x8138

Definition at line 1768 of file reg.h.

#define AR5K_TSF_THRES 0x813c

Definition at line 1773 of file reg.h.

#define AR5K_RATE_ACKSIFS_BASE 0x8680

Definition at line 1783 of file reg.h.

#define AR5K_RATE_ACKSIFS ( _n ) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2))

Definition at line 1784 of file reg.h.

#define AR5K_RATE_ACKSIFS_NORMAL 0x00000001

Definition at line 1785 of file reg.h.

#define AR5K_RATE_ACKSIFS_TURBO 0x00000400

Definition at line 1786 of file reg.h.

#define AR5K_RATE_DUR_BASE 0x8700

Definition at line 1791 of file reg.h.

#define AR5K_RATE_DUR ( _n ) (AR5K_RATE_DUR_BASE + ((_n) << 2))

Definition at line 1792 of file reg.h.

Referenced by ath5k_hw_write_rate_duration().

#define AR5K_RATE2DB_BASE 0x87c0

Definition at line 1798 of file reg.h.

#define AR5K_RATE2DB ( _n ) (AR5K_RATE2DB_BASE + ((_n) << 2))

Definition at line 1799 of file reg.h.

#define AR5K_DB2RATE_BASE 0x87e0

Definition at line 1805 of file reg.h.

#define AR5K_DB2RATE ( _n ) (AR5K_DB2RATE_BASE + ((_n) << 2))

Definition at line 1806 of file reg.h.

#define AR5K_KEYTABLE_0_5210 0x9000

Definition at line 1813 of file reg.h.

#define AR5K_KEYTABLE_0_5211 0x8800

Definition at line 1814 of file reg.h.

#define AR5K_KEYTABLE_5210 ( _n ) (AR5K_KEYTABLE_0_5210 + ((_n) << 5))

Definition at line 1815 of file reg.h.

#define AR5K_KEYTABLE_5211 ( _n ) (AR5K_KEYTABLE_0_5211 + ((_n) << 5))

Definition at line 1816 of file reg.h.

#define AR5K_KEYTABLE ( _n )

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n))

Definition at line 1817 of file reg.h.

#define AR5K_KEYTABLE_OFF	(	_n,
		x		)	(AR5K_KEYTABLE(_n) + (x << 2))

Definition at line 1819 of file reg.h.

Referenced by ath5k_hw_reset_key().

#define AR5K_KEYTABLE_TYPE ( _n ) AR5K_KEYTABLE_OFF(_n, 5)

Definition at line 1820 of file reg.h.

Referenced by ath5k_hw_reset_key().

#define AR5K_KEYTABLE_TYPE_40 0x00000000

Definition at line 1821 of file reg.h.

#define AR5K_KEYTABLE_TYPE_104 0x00000001

Definition at line 1822 of file reg.h.

#define AR5K_KEYTABLE_TYPE_128 0x00000003

Definition at line 1823 of file reg.h.

#define AR5K_KEYTABLE_TYPE_TKIP 0x00000004

Definition at line 1824 of file reg.h.

Referenced by ath5k_hw_reset_key().

#define AR5K_KEYTABLE_TYPE_AES 0x00000005

Definition at line 1825 of file reg.h.

#define AR5K_KEYTABLE_TYPE_CCM 0x00000006

Definition at line 1826 of file reg.h.

#define AR5K_KEYTABLE_TYPE_NULL 0x00000007

Definition at line 1827 of file reg.h.

Referenced by ath5k_hw_reset_key().

#define AR5K_KEYTABLE_ANTENNA 0x00000008

Definition at line 1828 of file reg.h.

#define AR5K_KEYTABLE_MAC0 ( _n ) AR5K_KEYTABLE_OFF(_n, 6)

Definition at line 1829 of file reg.h.

#define AR5K_KEYTABLE_MAC1 ( _n ) AR5K_KEYTABLE_OFF(_n, 7)

Definition at line 1830 of file reg.h.

#define AR5K_KEYTABLE_VALID 0x00008000

Definition at line 1831 of file reg.h.

#define AR5K_KEYTABLE_MIC_OFFSET 64

Definition at line 1835 of file reg.h.

Referenced by ath5k_hw_reset_key().

#define AR5K_KEYTABLE_SIZE_5210 64

Definition at line 1849 of file reg.h.

#define AR5K_KEYTABLE_SIZE_5211 128

Definition at line 1850 of file reg.h.

#define AR5K_KEYTABLE_SIZE

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211)

Definition at line 1851 of file reg.h.

Referenced by ath5k_init().

#define AR5K_PHY_BASE 0x9800

Definition at line 1860 of file reg.h.

#define AR5K_PHY ( _n ) (AR5K_PHY_BASE + ((_n) << 2))

Definition at line 1861 of file reg.h.

Referenced by ath5k_hw_attach(), ath5k_hw_post(), ath5k_hw_radio_revision(), and ath5k_hw_reset().

#define AR5K_PHY_TST2 0x9800

Definition at line 1866 of file reg.h.

#define AR5K_PHY_TST2_TRIG_SEL 0x00000007

Definition at line 1867 of file reg.h.

#define AR5K_PHY_TST2_TRIG 0x00000010

Definition at line 1868 of file reg.h.

#define AR5K_PHY_TST2_CBUS_MODE 0x00000060

Definition at line 1869 of file reg.h.

#define AR5K_PHY_TST2_CLK32 0x00000400

Definition at line 1870 of file reg.h.

#define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800

Definition at line 1871 of file reg.h.

#define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000

Definition at line 1872 of file reg.h.

#define AR5K_PHY_TST2_RFSILENT_EN 0x00002000

Definition at line 1873 of file reg.h.

#define AR5K_PHY_TST2_ALT_RFDATA 0x00004000

Definition at line 1874 of file reg.h.

#define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000

Definition at line 1875 of file reg.h.

#define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000

Definition at line 1876 of file reg.h.

#define AR5K_PHY_TST2_SLOW_CLK160 0x00020000

Definition at line 1877 of file reg.h.

#define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000

Definition at line 1878 of file reg.h.

#define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000

Definition at line 1879 of file reg.h.

#define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000

Definition at line 1880 of file reg.h.

#define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000

Definition at line 1881 of file reg.h.

#define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000

Definition at line 1882 of file reg.h.

#define AR5K_PHY_SHIFT_2GHZ 0x00004007

Definition at line 1883 of file reg.h.

Referenced by ath5k_hw_radio_revision().

#define AR5K_PHY_SHIFT_5GHZ 0x00000007

Definition at line 1884 of file reg.h.

Referenced by ath5k_hw_radio_revision(), and ath5k_hw_reset().

#define AR5K_PHY_TURBO 0x9804

Definition at line 1896 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_TURBO_MODE 0x00000001

Definition at line 1897 of file reg.h.

Referenced by ath5k_hw_nic_wakeup(), and ath5k_hw_reset_tx_queue().

#define AR5K_PHY_TURBO_SHORT 0x00000002

Definition at line 1898 of file reg.h.

Referenced by ath5k_hw_nic_wakeup(), and ath5k_hw_reset_tx_queue().

#define AR5K_PHY_TURBO_MIMO 0x00000004

Definition at line 1899 of file reg.h.

#define AR5K_PHY_AGC 0x9808

Definition at line 1905 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate(), and ath5k_hw_write_initvals().

#define AR5K_PHY_TST1 0x9808

Definition at line 1906 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_PHY_AGC_DISABLE 0x08000000

Definition at line 1907 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_TST1_TXHOLD 0x00003800

Definition at line 1908 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_PHY_TST1_TXSRC_SRC 0x00000002

Definition at line 1909 of file reg.h.

#define AR5K_PHY_TST1_TXSRC_SRC_S 1

Definition at line 1910 of file reg.h.

#define AR5K_PHY_TST1_TXSRC_ALT 0x00000080

Definition at line 1911 of file reg.h.

#define AR5K_PHY_TST1_TXSRC_ALT_S 7

Definition at line 1912 of file reg.h.

#define AR5K_PHY_TIMING_3 0x9814

Definition at line 1918 of file reg.h.

Referenced by ath5k_hw_write_ofdm_timings().

#define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000

Definition at line 1919 of file reg.h.

Referenced by ath5k_hw_write_ofdm_timings().

#define AR5K_PHY_TIMING_3_DSC_MAN_S 17

Definition at line 1920 of file reg.h.

#define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000

Definition at line 1921 of file reg.h.

Referenced by ath5k_hw_write_ofdm_timings().

#define AR5K_PHY_TIMING_3_DSC_EXP_S 13

Definition at line 1922 of file reg.h.

#define AR5K_PHY_CHIP_ID 0x9818

Definition at line 1927 of file reg.h.

Referenced by ath5k_hw_attach().

#define AR5K_PHY_ACT 0x981c

Definition at line 1932 of file reg.h.

Referenced by ath5k_hw_phy_disable(), ath5k_hw_reset(), and ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_ACT_ENABLE 0x00000001

Definition at line 1933 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_ACT_DISABLE 0x00000002

Definition at line 1934 of file reg.h.

Referenced by ath5k_hw_phy_disable(), and ath5k_hw_reset().

#define AR5K_PHY_RF_CTL2 0x9824

Definition at line 1939 of file reg.h.

#define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f

Definition at line 1940 of file reg.h.

#define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0

Definition at line 1941 of file reg.h.

#define AR5K_PHY_RF_CTL3 0x9828

Definition at line 1943 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00

Definition at line 1944 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8

Definition at line 1945 of file reg.h.

#define AR5K_PHY_ADC_CTL 0x982c

Definition at line 1947 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003

Definition at line 1948 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0

Definition at line 1949 of file reg.h.

#define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000

Definition at line 1950 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000

Definition at line 1951 of file reg.h.

#define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000

Definition at line 1952 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000

Definition at line 1953 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16

Definition at line 1954 of file reg.h.

#define AR5K_PHY_RF_CTL4 0x9834

Definition at line 1956 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001

Definition at line 1957 of file reg.h.

#define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100

Definition at line 1958 of file reg.h.

#define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000

Definition at line 1959 of file reg.h.

#define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000

Definition at line 1960 of file reg.h.

#define AR5K_PHY_PA_CTL 0x9838

Definition at line 1966 of file reg.h.

#define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001

Definition at line 1967 of file reg.h.

#define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002

Definition at line 1968 of file reg.h.

#define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004

Definition at line 1969 of file reg.h.

#define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008

Definition at line 1970 of file reg.h.

#define AR5K_PHY_SETTLING 0x9844

Definition at line 1975 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings(), and ath5k_hw_reset_tx_queue().

#define AR5K_PHY_SETTLING_AGC 0x0000007f

Definition at line 1976 of file reg.h.

#define AR5K_PHY_SETTLING_AGC_S 0

Definition at line 1977 of file reg.h.

#define AR5K_PHY_SETTLING_SWITCH 0x00003f80

Definition at line 1978 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_SETTLING_SWITCH_S 7

Definition at line 1979 of file reg.h.

#define AR5K_PHY_GAIN 0x9848

Definition at line 1984 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000

Definition at line 1985 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_GAIN_TXRX_ATTEN_S 12

Definition at line 1986 of file reg.h.

#define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000

Definition at line 1987 of file reg.h.

#define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18

Definition at line 1988 of file reg.h.

#define AR5K_PHY_GAIN_OFFSET 0x984c

Definition at line 1990 of file reg.h.

#define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000

Definition at line 1991 of file reg.h.

#define AR5K_PHY_DESIRED_SIZE 0x9850

Definition at line 1997 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff

Definition at line 1998 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_DESIRED_SIZE_ADC_S 0

Definition at line 1999 of file reg.h.

#define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00

Definition at line 2000 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_DESIRED_SIZE_PGA_S 8

Definition at line 2001 of file reg.h.

#define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000

Definition at line 2002 of file reg.h.

#define AR5K_PHY_DESIRED_SIZE_TOT_S 20

Definition at line 2003 of file reg.h.

#define AR5K_PHY_SIG 0x9858

Definition at line 2009 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_SIG_FIRSTEP 0x0003f000

Definition at line 2010 of file reg.h.

#define AR5K_PHY_SIG_FIRSTEP_S 12

Definition at line 2011 of file reg.h.

#define AR5K_PHY_SIG_FIRPWR 0x03fc0000

Definition at line 2012 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_SIG_FIRPWR_S 18

Definition at line 2013 of file reg.h.

#define AR5K_PHY_AGCCOARSE 0x985c

Definition at line 2019 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_AGCCOARSE_LO 0x00007f80

Definition at line 2020 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_AGCCOARSE_LO_S 7

Definition at line 2021 of file reg.h.

#define AR5K_PHY_AGCCOARSE_HI 0x003f8000

Definition at line 2022 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_AGCCOARSE_HI_S 15

Definition at line 2023 of file reg.h.

#define AR5K_PHY_AGCCTL 0x9860

Definition at line 2028 of file reg.h.

Referenced by ath5k_hw_noise_floor_calibration(), ath5k_hw_reset(), and ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_AGCCTL_CAL 0x00000001

Definition at line 2029 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_AGCCTL_NF 0x00000002

Definition at line 2030 of file reg.h.

Referenced by ath5k_hw_noise_floor_calibration().

#define AR5K_PHY_AGCCTL_NF_EN 0x00008000

Definition at line 2031 of file reg.h.

#define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000

Definition at line 2032 of file reg.h.

#define AR5K_PHY_NF 0x9864

Definition at line 2037 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings(), and ath5k_hw_noise_floor_calibration().

#define AR5K_PHY_NF_M 0x000001ff

Definition at line 2038 of file reg.h.

#define AR5K_PHY_NF_ACTIVE 0x00000100

Definition at line 2039 of file reg.h.

Referenced by ath5k_hw_noise_floor_calibration().

#define AR5K_PHY_NF_RVAL ( _n ) (((_n) >> 19) & AR5K_PHY_NF_M)

Definition at line 2040 of file reg.h.

Referenced by ath5k_hw_noise_floor_calibration().

#define AR5K_PHY_NF_AVAL ( _n ) (-((_n) ^ AR5K_PHY_NF_M) + 1)

Definition at line 2041 of file reg.h.

Referenced by ath5k_hw_noise_floor_calibration().

#define AR5K_PHY_NF_SVAL ( _n ) (((_n) & AR5K_PHY_NF_M) | (1 << 9))

Definition at line 2042 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_NF_THRESH62 0x0007f000

Definition at line 2043 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_NF_THRESH62_S 12

Definition at line 2044 of file reg.h.

#define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000

Definition at line 2045 of file reg.h.

#define AR5K_PHY_NF_MINCCA_PWR_S 19

Definition at line 2046 of file reg.h.

#define AR5K_PHY_ADCSAT 0x9868

Definition at line 2051 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_ADCSAT_ICNT 0x0001f800

Definition at line 2052 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_ADCSAT_ICNT_S 11

Definition at line 2053 of file reg.h.

#define AR5K_PHY_ADCSAT_THR 0x000007e0

Definition at line 2054 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_ADCSAT_THR_S 5

Definition at line 2055 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868

Definition at line 2062 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f

Definition at line 2063 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0

Definition at line 2064 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000

Definition at line 2065 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17

Definition at line 2066 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000

Definition at line 2067 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24

Definition at line 2068 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c

Definition at line 2071 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001

Definition at line 2072 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00

Definition at line 2073 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8

Definition at line 2074 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000

Definition at line 2075 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14

Definition at line 2076 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000

Definition at line 2077 of file reg.h.

#define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21

Definition at line 2078 of file reg.h.

#define AR5K_PHY_SCR 0x9870

Definition at line 2084 of file reg.h.

#define AR5K_PHY_SLMT 0x9874

Definition at line 2086 of file reg.h.

#define AR5K_PHY_SLMT_32MHZ 0x0000007f

Definition at line 2087 of file reg.h.

#define AR5K_PHY_SCAL 0x9878

Definition at line 2089 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_SCAL_32MHZ 0x0000000e

Definition at line 2090 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a

Definition at line 2091 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032

Definition at line 2092 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_PLL 0x987c

Definition at line 2097 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_PLL_20MHZ 0x00000013

Definition at line 2098 of file reg.h.

#define AR5K_PHY_PLL_40MHZ_5211 0x00000018

Definition at line 2100 of file reg.h.

#define AR5K_PHY_PLL_40MHZ_5212 0x000000aa

Definition at line 2101 of file reg.h.

#define AR5K_PHY_PLL_40MHZ_5413 0x00000004

Definition at line 2102 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_PLL_40MHZ

Value:

(ah->ah_version == AR5K_AR5211 ? \
                                        AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212)

Definition at line 2103 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_PLL_44MHZ_5211 0x00000019

Definition at line 2106 of file reg.h.

#define AR5K_PHY_PLL_44MHZ_5212 0x000000ab

Definition at line 2107 of file reg.h.

#define AR5K_PHY_PLL_44MHZ

Value:

(ah->ah_version == AR5K_AR5211 ? \
                                        AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212)

Definition at line 2108 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_PLL_RF5111 0x00000000

Definition at line 2111 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_PLL_RF5112 0x00000040

Definition at line 2112 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_PLL_HALF_RATE 0x00000100

Definition at line 2113 of file reg.h.

#define AR5K_PHY_PLL_QUARTER_RATE 0x00000200

Definition at line 2114 of file reg.h.

#define AR5K_RF_BUFFER 0x989c

Definition at line 2125 of file reg.h.

Referenced by ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_channel(), ath5k_hw_rf5111_channel(), and ath5k_hw_rf5112_channel().

#define AR5K_RF_BUFFER_CONTROL_0 0x98c0

Definition at line 2126 of file reg.h.

Referenced by ath5k_hw_rf5110_channel().

#define AR5K_RF_BUFFER_CONTROL_1 0x98c4

Definition at line 2127 of file reg.h.

#define AR5K_RF_BUFFER_CONTROL_2 0x98cc

Definition at line 2128 of file reg.h.

#define AR5K_RF_BUFFER_CONTROL_3 0x98d0

Definition at line 2130 of file reg.h.

Referenced by ath5k_hw_rf5111_channel().

#define AR5K_RF_BUFFER_CONTROL_4 0x98d4

Definition at line 2134 of file reg.h.

#define AR5K_RF_BUFFER_CONTROL_5 0x98d8

Definition at line 2139 of file reg.h.

Referenced by ath5k_hw_rf2425_channel(), and ath5k_hw_rf5112_channel().

#define AR5K_RF_BUFFER_CONTROL_6 0x98dc

Definition at line 2144 of file reg.h.

#define AR5K_PHY_RFSTG 0x98d4

Definition at line 2149 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_RFSTG_DISABLE 0x00000021

Definition at line 2150 of file reg.h.

Referenced by ath5k_hw_rf5110_calibrate().

#define AR5K_PHY_BIN_MASK_1 0x9900

Definition at line 2155 of file reg.h.

#define AR5K_PHY_BIN_MASK_2 0x9904

Definition at line 2156 of file reg.h.

#define AR5K_PHY_BIN_MASK_3 0x9908

Definition at line 2157 of file reg.h.

#define AR5K_PHY_BIN_MASK_CTL 0x990c

Definition at line 2159 of file reg.h.

#define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff

Definition at line 2160 of file reg.h.

#define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0

Definition at line 2161 of file reg.h.

#define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000

Definition at line 2162 of file reg.h.

#define AR5K_PHY_BIN_MASK_CTL_RATE_S 24

Definition at line 2163 of file reg.h.

#define AR5K_PHY_ANT_CTL 0x9910

Definition at line 2168 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001

Definition at line 2169 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004

Definition at line 2170 of file reg.h.

#define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008

Definition at line 2171 of file reg.h.

#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0

Definition at line 2172 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4

Definition at line 2173 of file reg.h.

#define AR5K_PHY_RX_DELAY 0x9914

Definition at line 2178 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_PHY_RX_DELAY_M 0x00003fff

Definition at line 2179 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_PHY_MAX_RX_LEN 0x991c

Definition at line 2184 of file reg.h.

#define AR5K_PHY_IQ 0x9920

Definition at line 2190 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings(), ath5k_hw_reset(), and ath5k_hw_rf511x_calibrate().

#define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f

Definition at line 2191 of file reg.h.

#define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0

Definition at line 2192 of file reg.h.

#define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5

Definition at line 2193 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings(), and ath5k_hw_rf511x_calibrate().

#define AR5K_PHY_IQ_CORR_ENABLE 0x00000800

Definition at line 2194 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings(), and ath5k_hw_rf511x_calibrate().

#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000

Definition at line 2195 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_rf511x_calibrate().

#define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12

Definition at line 2196 of file reg.h.

#define AR5K_PHY_IQ_RUN 0x00010000

Definition at line 2197 of file reg.h.

Referenced by ath5k_hw_reset(), and ath5k_hw_rf511x_calibrate().

#define AR5K_PHY_IQ_USE_PT_DF 0x00020000

Definition at line 2198 of file reg.h.

#define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000

Definition at line 2199 of file reg.h.

#define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000

Definition at line 2200 of file reg.h.

#define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000

Definition at line 2201 of file reg.h.

#define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000

Definition at line 2202 of file reg.h.

#define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000

Definition at line 2203 of file reg.h.

#define AR5K_PHY_OFDM_SELFCORR 0x9924

Definition at line 2210 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001

Definition at line 2211 of file reg.h.

#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe

Definition at line 2212 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1

Definition at line 2213 of file reg.h.

#define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100

Definition at line 2214 of file reg.h.

#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000

Definition at line 2215 of file reg.h.

#define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000

Definition at line 2216 of file reg.h.

#define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000

Definition at line 2217 of file reg.h.

#define AR5K_PHY_WARM_RESET 0x9928

Definition at line 2222 of file reg.h.

#define AR5K_PHY_CTL 0x992c

Definition at line 2227 of file reg.h.

#define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001

Definition at line 2228 of file reg.h.

#define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002

Definition at line 2229 of file reg.h.

#define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004

Definition at line 2230 of file reg.h.

#define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008

Definition at line 2231 of file reg.h.

#define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010

Definition at line 2232 of file reg.h.

#define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020

Definition at line 2233 of file reg.h.

#define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040

Definition at line 2234 of file reg.h.

#define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080

Definition at line 2235 of file reg.h.

#define AR5K_PHY_PAPD_PROBE 0x9930

Definition at line 2240 of file reg.h.

Referenced by ath5k_hw_gainf_calibrate(), and ath5k_hw_request_rfgain_probe().

#define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001

Definition at line 2241 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002

Definition at line 2242 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040

Definition at line 2243 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00

Definition at line 2244 of file reg.h.

Referenced by ath5k_hw_request_rfgain_probe().

#define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9

Definition at line 2245 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000

Definition at line 2246 of file reg.h.

Referenced by ath5k_hw_gainf_calibrate(), and ath5k_hw_request_rfgain_probe().

#define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000

Definition at line 2247 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000

Definition at line 2248 of file reg.h.

Referenced by ath5k_hw_gainf_calibrate().

#define AR5K_PHY_PAPD_PROBE_TYPE_S 23

Definition at line 2249 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0

Definition at line 2250 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_TYPE_XR 1

Definition at line 2251 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2

Definition at line 2252 of file reg.h.

Referenced by ath5k_hw_gainf_calibrate().

#define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000

Definition at line 2253 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_GAINF_S 25

Definition at line 2254 of file reg.h.

Referenced by ath5k_hw_gainf_calibrate().

#define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883

Definition at line 2255 of file reg.h.

#define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882

Definition at line 2256 of file reg.h.

#define AR5K_PHY_TXPOWER_RATE1 0x9934

Definition at line 2261 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_PHY_TXPOWER_RATE2 0x9938

Definition at line 2262 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_PHY_TXPOWER_RATE_MAX 0x993c

Definition at line 2263 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040

Definition at line 2264 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_PHY_TXPOWER_RATE3 0xa234

Definition at line 2265 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_PHY_TXPOWER_RATE4 0xa238

Definition at line 2266 of file reg.h.

Referenced by ath5k_hw_txpower().

#define AR5K_PHY_FRAME_CTL_5210 0x9804

Definition at line 2271 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_PHY_FRAME_CTL_5211 0x9944

Definition at line 2272 of file reg.h.

#define AR5K_PHY_FRAME_CTL

Value:

(ah->ah_version == AR5K_AR5210 ? \
                                        AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)

Definition at line 2273 of file reg.h.

Referenced by ath5k_hw_rfregs_init(), and ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038

Definition at line 2276 of file reg.h.

Referenced by ath5k_hw_rfregs_init().

#define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3

Definition at line 2277 of file reg.h.

#define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000

Definition at line 2278 of file reg.h.

#define AR5K_PHY_FRAME_CTL_EMU 0x80000000

Definition at line 2279 of file reg.h.

#define AR5K_PHY_FRAME_CTL_EMU_S 31

Definition at line 2280 of file reg.h.

#define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000

Definition at line 2282 of file reg.h.

#define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000

Definition at line 2283 of file reg.h.

#define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000

Definition at line 2284 of file reg.h.

#define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000

Definition at line 2285 of file reg.h.

#define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000

Definition at line 2286 of file reg.h.

#define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000

Definition at line 2287 of file reg.h.

#define AR5K_PHY_FRAME_CTL_INI

Value:

AR5K_PHY_FRAME_CTL_SERVICE_ERR | \
                        AR5K_PHY_FRAME_CTL_TXURN_ERR | \
                        AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \
                        AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \
                        AR5K_PHY_FRAME_CTL_PARITY_ERR | \
                        AR5K_PHY_FRAME_CTL_TIMING_ERR

Definition at line 2288 of file reg.h.

Referenced by ath5k_hw_reset_tx_queue().

#define AR5K_PHY_TX_PWR_ADJ 0x994c

Definition at line 2298 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0

Definition at line 2299 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6

Definition at line 2300 of file reg.h.

#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000

Definition at line 2301 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18

Definition at line 2302 of file reg.h.

#define AR5K_PHY_RADAR 0x9954

Definition at line 2307 of file reg.h.

#define AR5K_PHY_RADAR_ENABLE 0x00000001

Definition at line 2308 of file reg.h.

#define AR5K_PHY_RADAR_DISABLE 0x00000000

Definition at line 2309 of file reg.h.

#define AR5K_PHY_RADAR_INBANDTHR 0x0000003e

Definition at line 2310 of file reg.h.

#define AR5K_PHY_RADAR_INBANDTHR_S 1

Definition at line 2313 of file reg.h.

#define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0

Definition at line 2315 of file reg.h.

#define AR5K_PHY_RADAR_PRSSI_THR_S 6

Definition at line 2318 of file reg.h.

#define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000

Definition at line 2320 of file reg.h.

#define AR5K_PHY_RADAR_PHEIGHT_THR_S 12

Definition at line 2323 of file reg.h.

#define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000

Definition at line 2325 of file reg.h.

#define AR5K_PHY_RADAR_RSSI_THR_S 18

Definition at line 2328 of file reg.h.

#define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000

Definition at line 2330 of file reg.h.

#define AR5K_PHY_RADAR_FIRPWR_THRS 24

Definition at line 2334 of file reg.h.

#define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960

Definition at line 2339 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964

Definition at line 2340 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_NFTHRES 0x9968

Definition at line 2345 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_SIGMA_DELTA 0x996C

Definition at line 2350 of file reg.h.

#define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003

Definition at line 2351 of file reg.h.

#define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0

Definition at line 2352 of file reg.h.

#define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8

Definition at line 2353 of file reg.h.

#define AR5K_PHY_SIGMA_DELTA_FILT2_S 3

Definition at line 2354 of file reg.h.

#define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00

Definition at line 2355 of file reg.h.

#define AR5K_PHY_SIGMA_DELTA_FILT1_S 8

Definition at line 2356 of file reg.h.

#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000

Definition at line 2357 of file reg.h.

#define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13

Definition at line 2358 of file reg.h.

#define AR5K_PHY_RESTART 0x9970

Definition at line 2363 of file reg.h.

#define AR5K_PHY_RESTART_DIV_GC 0x001c0000

Definition at line 2364 of file reg.h.

#define AR5K_PHY_RESTART_DIV_GC_S 18

Definition at line 2365 of file reg.h.

#define AR5K_PHY_RFBUS_REQ 0x997C

Definition at line 2370 of file reg.h.

#define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001

Definition at line 2371 of file reg.h.

#define AR5K_PHY_TIMING_7 0x9980

Definition at line 2376 of file reg.h.

#define AR5K_PHY_TIMING_8 0x9984

Definition at line 2377 of file reg.h.

#define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff

Definition at line 2378 of file reg.h.

#define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0

Definition at line 2379 of file reg.h.

#define AR5K_PHY_BIN_MASK2_1 0x9988

Definition at line 2381 of file reg.h.

#define AR5K_PHY_BIN_MASK2_2 0x998c

Definition at line 2382 of file reg.h.

#define AR5K_PHY_BIN_MASK2_3 0x9990

Definition at line 2383 of file reg.h.

#define AR5K_PHY_BIN_MASK2_4 0x9994

Definition at line 2385 of file reg.h.

#define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff

Definition at line 2386 of file reg.h.

#define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0

Definition at line 2387 of file reg.h.

#define AR5K_PHY_TIMING_9 0x9998

Definition at line 2389 of file reg.h.

#define AR5K_PHY_TIMING_10 0x999c

Definition at line 2390 of file reg.h.

#define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff

Definition at line 2391 of file reg.h.

#define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0

Definition at line 2392 of file reg.h.

#define AR5K_PHY_TIMING_11 0x99a0

Definition at line 2397 of file reg.h.

#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff

Definition at line 2398 of file reg.h.

#define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0

Definition at line 2399 of file reg.h.

#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000

Definition at line 2400 of file reg.h.

#define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20

Definition at line 2401 of file reg.h.

#define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000

Definition at line 2402 of file reg.h.

#define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000

Definition at line 2403 of file reg.h.

#define AR5K_BB_GAIN_BASE 0x9b00

Definition at line 2408 of file reg.h.

#define AR5K_BB_GAIN ( _n ) (AR5K_BB_GAIN_BASE + ((_n) << 2))

Definition at line 2409 of file reg.h.

#define AR5K_RF_GAIN_BASE 0x9a00

Definition at line 2410 of file reg.h.

#define AR5K_RF_GAIN ( _n ) (AR5K_RF_GAIN_BASE + ((_n) << 2))

Definition at line 2411 of file reg.h.

#define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10

Definition at line 2416 of file reg.h.

Referenced by ath5k_hw_rf511x_calibrate().

#define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14

Definition at line 2417 of file reg.h.

Referenced by ath5k_hw_rf511x_calibrate().

#define AR5K_PHY_IQRES_CAL_CORR 0x9c18

Definition at line 2418 of file reg.h.

Referenced by ath5k_hw_rf511x_calibrate().

#define AR5K_PHY_CURRENT_RSSI 0x9c1c

Definition at line 2423 of file reg.h.

#define AR5K_PHY_RFBUS_GRANT 0x9c20

Definition at line 2428 of file reg.h.

#define AR5K_PHY_RFBUS_GRANT_OK 0x00000001

Definition at line 2429 of file reg.h.

#define AR5K_PHY_ADC_TEST 0x9c24

Definition at line 2434 of file reg.h.

Referenced by ath5k_hw_reset().

#define AR5K_PHY_ADC_TEST_I 0x00000001

Definition at line 2435 of file reg.h.

#define AR5K_PHY_ADC_TEST_Q 0x00000200

Definition at line 2436 of file reg.h.

#define AR5K_PHY_DAC_TEST 0x9c28

Definition at line 2441 of file reg.h.

#define AR5K_PHY_DAC_TEST_I 0x00000001

Definition at line 2442 of file reg.h.

#define AR5K_PHY_DAC_TEST_Q 0x00000200

Definition at line 2443 of file reg.h.

#define AR5K_PHY_PTAT 0x9c2c

Definition at line 2448 of file reg.h.

#define AR5K_PHY_BAD_TX_RATE 0x9c30

Definition at line 2453 of file reg.h.

#define AR5K_PHY_SPUR_PWR 0x9c34

Definition at line 2458 of file reg.h.

#define AR5K_PHY_SPUR_PWR_I 0x00000001

Definition at line 2459 of file reg.h.

#define AR5K_PHY_SPUR_PWR_Q 0x00000100

Definition at line 2460 of file reg.h.

#define AR5K_PHY_SPUR_PWR_FILT 0x00010000

Definition at line 2461 of file reg.h.

#define AR5K_PHY_CHAN_STATUS 0x9c38

Definition at line 2466 of file reg.h.

#define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001

Definition at line 2467 of file reg.h.

#define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002

Definition at line 2468 of file reg.h.

#define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004

Definition at line 2469 of file reg.h.

#define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008

Definition at line 2470 of file reg.h.

#define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0

Definition at line 2475 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_SCLOCK 0x99f0

Definition at line 2480 of file reg.h.

#define AR5K_PHY_SCLOCK_32MHZ 0x0000000c

Definition at line 2481 of file reg.h.

#define AR5K_PHY_SDELAY 0x99f4

Definition at line 2482 of file reg.h.

#define AR5K_PHY_SDELAY_32MHZ 0x000000ff

Definition at line 2483 of file reg.h.

#define AR5K_PHY_SPENDING 0x99f8

Definition at line 2484 of file reg.h.

#define AR5K_PHY_PAPD_I_BASE 0xa000

Definition at line 2491 of file reg.h.

#define AR5K_PHY_PAPD_I ( _n ) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2))

Definition at line 2492 of file reg.h.

#define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180

Definition at line 2497 of file reg.h.

#define AR5K_PHY_PCDAC_TXPOWER ( _n ) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2))

Definition at line 2498 of file reg.h.

Referenced by ath5k_setup_pcdac_table().

#define AR5K_PHY_MODE 0x0a200

Definition at line 2503 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_MODE_MOD 0x00000001

Definition at line 2504 of file reg.h.

#define AR5K_PHY_MODE_MOD_OFDM 0

Definition at line 2505 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_MODE_MOD_CCK 1

Definition at line 2506 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_MODE_FREQ 0x00000002

Definition at line 2507 of file reg.h.

#define AR5K_PHY_MODE_FREQ_5GHZ 0

Definition at line 2508 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_MODE_FREQ_2GHZ 2

Definition at line 2509 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_MODE_MOD_DYN 0x00000004

Definition at line 2510 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_MODE_RAD 0x00000008

Definition at line 2511 of file reg.h.

#define AR5K_PHY_MODE_RAD_RF5111 0

Definition at line 2512 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_MODE_RAD_RF5112 8

Definition at line 2513 of file reg.h.

Referenced by ath5k_hw_nic_wakeup().

#define AR5K_PHY_MODE_XR 0x00000010

Definition at line 2514 of file reg.h.

#define AR5K_PHY_MODE_HALF_RATE 0x00000020

Definition at line 2515 of file reg.h.

#define AR5K_PHY_MODE_QUARTER_RATE 0x00000040

Definition at line 2516 of file reg.h.

#define AR5K_PHY_CCKTXCTL 0xa204

Definition at line 2521 of file reg.h.

Referenced by ath5k_hw_channel(), and ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_CCKTXCTL_WORLD 0x00000000

Definition at line 2522 of file reg.h.

Referenced by ath5k_hw_channel(), and ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010

Definition at line 2523 of file reg.h.

Referenced by ath5k_hw_channel().

#define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001

Definition at line 2524 of file reg.h.

#define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004

Definition at line 2525 of file reg.h.

#define AR5K_PHY_CCK_CROSSCORR 0xa208

Definition at line 2530 of file reg.h.

#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000000f

Definition at line 2531 of file reg.h.

#define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0

Definition at line 2532 of file reg.h.

#define AR5K_PHY_FAST_ANT_DIV 0xa208

Definition at line 2535 of file reg.h.

#define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000

Definition at line 2536 of file reg.h.

#define AR5K_PHY_GAIN_2GHZ 0xa20c

Definition at line 2541 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000

Definition at line 2542 of file reg.h.

Referenced by ath5k_hw_commit_eeprom_settings().

#define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18

Definition at line 2543 of file reg.h.

#define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c

Definition at line 2544 of file reg.h.

#define AR5K_PHY_CCK_RX_CTL_4 0xa21c

Definition at line 2546 of file reg.h.

#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000

Definition at line 2547 of file reg.h.

#define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19

Definition at line 2548 of file reg.h.

#define AR5K_PHY_DAG_CCK_CTL 0xa228

Definition at line 2550 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200

Definition at line 2551 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00

Definition at line 2552 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10

Definition at line 2553 of file reg.h.

#define AR5K_PHY_FAST_ADC 0xa24c

Definition at line 2555 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_BLUETOOTH 0xa254

Definition at line 2557 of file reg.h.

Referenced by ath5k_hw_tweak_initval_settings().

#define AR5K_PHY_TPC_RG1 0xa258

Definition at line 2563 of file reg.h.

Referenced by ath5k_setup_pwr_to_pdadc_table().

#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000

Definition at line 2564 of file reg.h.

Referenced by ath5k_setup_pwr_to_pdadc_table().

#define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14

Definition at line 2565 of file reg.h.

#define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000

Definition at line 2566 of file reg.h.

Referenced by ath5k_setup_pwr_to_pdadc_table().

#define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16

Definition at line 2567 of file reg.h.

#define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000

Definition at line 2568 of file reg.h.

Referenced by ath5k_setup_pwr_to_pdadc_table().

#define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18

Definition at line 2569 of file reg.h.

#define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000

Definition at line 2570 of file reg.h.

Referenced by ath5k_setup_pwr_to_pdadc_table().

#define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20

Definition at line 2571 of file reg.h.

#define AR5K_PHY_TPC_RG5 0xa26C

Definition at line 2573 of file reg.h.

Referenced by ath5k_combine_pwr_to_pdadc_curves().

#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F

Definition at line 2574 of file reg.h.

Referenced by ath5k_combine_pwr_to_pdadc_curves().

#define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0

Definition at line 2575 of file reg.h.

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0

Definition at line 2576 of file reg.h.

Referenced by ath5k_combine_pwr_to_pdadc_curves().

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4

Definition at line 2577 of file reg.h.

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00

Definition at line 2578 of file reg.h.

Referenced by ath5k_combine_pwr_to_pdadc_curves().

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10

Definition at line 2579 of file reg.h.

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000

Definition at line 2580 of file reg.h.

Referenced by ath5k_combine_pwr_to_pdadc_curves().

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16

Definition at line 2581 of file reg.h.

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000

Definition at line 2582 of file reg.h.

Referenced by ath5k_combine_pwr_to_pdadc_curves().

#define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22

Definition at line 2583 of file reg.h.

#define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280

Definition at line 2588 of file reg.h.

#define AR5K_PHY_PDADC_TXPOWER ( _n ) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))

Definition at line 2589 of file reg.h.

Referenced by ath5k_setup_pwr_to_pdadc_table().