r8169.h File Reference

Go to the source code of this file.

Data Structures

struct  TxDesc
struct  RxDesc
struct  rtl8169_private

Defines

#define ARRAY_SIZE(x)   (sizeof(x) / sizeof((x)[0]))
#define PCI_EXP_DEVCTL   8
 FIXME: include/linux/pci_regs.h has these PCI regs, maybe we need such a file in gPXE?
#define PCI_EXP_DEVCTL_READRQ   0x7000
#define PCI_EXP_LNKCTL   16
#define PCI_EXP_LNKCTL_CLKREQ_EN   0x100
#define PCI_EXP_DEVCTL_NOSNOOP_EN   0x0800
#define SPEED_10   10
 FIXME: update mii.h in src/include/mii.h from Linux sources so we don't have to include these definitiions.
#define SPEED_100   100
#define SPEED_1000   1000
#define SPEED_2500   2500
#define SPEED_10000   10000
#define DUPLEX_HALF   0x00
#define DUPLEX_FULL   0x01
#define AUTONEG_DISABLE   0x00
#define AUTONEG_ENABLE   0x01
#define MAC_ADDR_LEN   6
#define MAX_READ_REQUEST_SHIFT   12
#define RX_FIFO_THRESH   7
#define RX_DMA_BURST   6
#define TX_DMA_BURST   6
#define EarlyTxThld   0x3F
#define RxPacketMaxSize   0x3FE8
#define SafeMtu   0x1c20
#define InterFrameGap   0x03
#define R8169_REGS_SIZE   256
#define R8169_NAPI_WEIGHT   64
#define NUM_TX_DESC   8
#define NUM_RX_DESC   8
#define RX_BUF_SIZE   1536
#define R8169_TX_RING_BYTES   (NUM_TX_DESC * sizeof(struct TxDesc))
#define R8169_RX_RING_BYTES   (NUM_RX_DESC * sizeof(struct RxDesc))
#define TX_RING_ALIGN   256
#define RX_RING_ALIGN   256
#define RTL8169_TX_TIMEOUT   (6*HZ)
#define RTL8169_PHY_TIMEOUT   (10*HZ)
#define RTL_EEPROM_SIG   cpu_to_le32(0x8129)
#define RTL_EEPROM_SIG_MASK   cpu_to_le32(0xffff)
#define RTL_EEPROM_SIG_ADDR   0x0000
#define RTL_W8(reg, val8)   writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16)   writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32)   writel ((val32), ioaddr + (reg))
#define RTL_R8(reg)   readb (ioaddr + (reg))
#define RTL_R16(reg)   readw (ioaddr + (reg))
#define RTL_R32(reg)   ((unsigned long) readl (ioaddr + (reg)))
#define _R(NAME, MAC, MASK)   { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
#define CSIAR_FLAG   0x80000000
#define CSIAR_WRITE_CMD   0x80000000
#define CSIAR_BYTE_ENABLE   0x0f
#define CSIAR_BYTE_ENABLE_SHIFT   12
#define CSIAR_ADDR_MASK   0x0fff
#define EPHYAR_FLAG   0x80000000
#define EPHYAR_WRITE_CMD   0x80000000
#define EPHYAR_REG_MASK   0x1f
#define EPHYAR_REG_SHIFT   16
#define EPHYAR_DATA_MASK   0xffff
#define FIX_NAK_1   (1 << 4)
#define FIX_NAK_2   (1 << 3)
#define RxProtoUDP   (PID1)
#define RxProtoTCP   (PID0)
#define RxProtoIP   (PID1 | PID0)
#define RxProtoMask   RxProtoIP
#define RsvdMask   0x3fffc000

Enumerations

enum  mac_version {
  RTL_GIGA_MAC_VER_01 = 0x01, RTL_GIGA_MAC_VER_02 = 0x02, RTL_GIGA_MAC_VER_03 = 0x03, RTL_GIGA_MAC_VER_04 = 0x04,
  RTL_GIGA_MAC_VER_05 = 0x05, RTL_GIGA_MAC_VER_06 = 0x06, RTL_GIGA_MAC_VER_07 = 0x07, RTL_GIGA_MAC_VER_08 = 0x08,
  RTL_GIGA_MAC_VER_09 = 0x09, RTL_GIGA_MAC_VER_10 = 0x0a, RTL_GIGA_MAC_VER_11 = 0x0b, RTL_GIGA_MAC_VER_12 = 0x0c,
  RTL_GIGA_MAC_VER_13 = 0x0d, RTL_GIGA_MAC_VER_14 = 0x0e, RTL_GIGA_MAC_VER_15 = 0x0f, RTL_GIGA_MAC_VER_16 = 0x11,
  RTL_GIGA_MAC_VER_17 = 0x10, RTL_GIGA_MAC_VER_18 = 0x12, RTL_GIGA_MAC_VER_19 = 0x13, RTL_GIGA_MAC_VER_20 = 0x14,
  RTL_GIGA_MAC_VER_21 = 0x15, RTL_GIGA_MAC_VER_22 = 0x16, RTL_GIGA_MAC_VER_23 = 0x17, RTL_GIGA_MAC_VER_24 = 0x18,
  RTL_GIGA_MAC_VER_25 = 0x19
}
enum  cfg_version { RTL_CFG_0 = 0x00, RTL_CFG_1, RTL_CFG_2 }
enum  rtl_registers {
  MAC0 = 0, MAC4 = 4, MAR0 = 8, CounterAddrLow = 0x10,
  CounterAddrHigh = 0x14, TxDescStartAddrLow = 0x20, TxDescStartAddrHigh = 0x24, TxHDescStartAddrLow = 0x28,
  TxHDescStartAddrHigh = 0x2c, FLASH = 0x30, ERSR = 0x36, ChipCmd = 0x37,
  TxPoll = 0x38, IntrMask = 0x3c, IntrStatus = 0x3e, TxConfig = 0x40,
  RxConfig = 0x44, RxMissed = 0x4c, Cfg9346 = 0x50, Config0 = 0x51,
  Config1 = 0x52, Config2 = 0x53, Config3 = 0x54, Config4 = 0x55,
  Config5 = 0x56, MultiIntr = 0x5c, PHYAR = 0x60, PHYstatus = 0x6c,
  RxMaxSize = 0xda, CPlusCmd = 0xe0, IntrMitigate = 0xe2, RxDescAddrLow = 0xe4,
  RxDescAddrHigh = 0xe8, EarlyTxThres = 0xec, FuncEvent = 0xf0, FuncEventMask = 0xf4,
  FuncPresetState = 0xf8, FuncForceEvent = 0xfc
}
enum  rtl8110_registers { TBICSR = 0x64, TBI_ANAR = 0x68, TBI_LPAR = 0x6a }
enum  rtl8168_8101_registers {
  CSIDR = 0x64, CSIAR = 0x68, EPHYAR = 0x80, DBG_REG = 0xd1,
  FIX_NAK_2
}
enum  rtl_register_content {
  SYSErr = 0x8000, PCSTimeout = 0x4000, SWInt = 0x0100, TxDescUnavail = 0x0080,
  RxFIFOOver = 0x0040, LinkChg = 0x0020, RxOverflow = 0x0010, TxErr = 0x0008,
  TxOK = 0x0004, RxErr = 0x0002, RxOK = 0x0001, RxFOVF = (1 << 23),
  RxRWT = (1 << 22), RxRES = (1 << 21), RxRUNT = (1 << 20), RxCRC = (1 << 19),
  CmdReset = 0x10, CmdRxEnb = 0x08, CmdTxEnb = 0x04, RxBufEmpty = 0x01,
  HPQ = 0x80, NPQ = 0x40, FSWInt = 0x01, Cfg9346_Lock = 0x00,
  Cfg9346_Unlock = 0xc0, AcceptErr = 0x20, AcceptRunt = 0x10, AcceptBroadcast = 0x08,
  AcceptMulticast = 0x04, AcceptMyPhys = 0x02, AcceptAllPhys = 0x01, RxCfgFIFOShift = 13,
  RxCfgDMAShift = 8, TxInterFrameGapShift = 24, TxDMAShift = 8, LEDS1 = (1 << 7),
  LEDS0 = (1 << 6), MSIEnable = (1 << 5), Speed_down = (1 << 4), MEMMAP = (1 << 3),
  IOMAP = (1 << 2), VPD = (1 << 1), PMEnable = (1 << 0), PCI_Clock_66MHz = 0x01,
  PCI_Clock_33MHz = 0x00, MagicPacket = (1 << 5), LinkUp = (1 << 4), Beacon_en = (1 << 0),
  BWF = (1 << 6), MWF = (1 << 5), UWF = (1 << 4), LanWake = (1 << 1),
  PMEStatus = (1 << 0), TBIReset = 0x80000000, TBILoopback = 0x40000000, TBINwEnable = 0x20000000,
  TBINwRestart = 0x10000000, TBILinkOk = 0x02000000, TBINwComplete = 0x01000000, EnableBist = (1 << 15),
  Mac_dbgo_oe = (1 << 14), Normal_mode = (1 << 13), Force_half_dup = (1 << 12), Force_rxflow_en = (1 << 11),
  Force_txflow_en = (1 << 10), Cxpl_dbg_sel = (1 << 9), ASF = (1 << 8), PktCntrDisable = (1 << 7),
  Mac_dbgo_sel = 0x001c, RxVlan = (1 << 6), RxChkSum = (1 << 5), PCIDAC = (1 << 4),
  PCIMulRW = (1 << 3), INTT_0 = 0x0000, INTT_1 = 0x0001, INTT_2 = 0x0002,
  INTT_3 = 0x0003, TBI_Enable = 0x80, TxFlowCtrl = 0x40, RxFlowCtrl = 0x20,
  _1000bpsF = 0x10, _100bps = 0x08, _10bps = 0x04, LinkStatus = 0x02,
  FullDup = 0x01, TBILinkOK = 0x02000000, CounterDump = 0x8
}
enum  desc_status_bit {
  DescOwn = (1 << 31), RingEnd = (1 << 30), FirstFrag = (1 << 29), LastFrag = (1 << 28),
  LargeSend = (1 << 27), MSSShift = 16, MSSMask = 0xfff, IPCS = (1 << 18),
  UDPCS = (1 << 17), TCPCS = (1 << 16), TxVlanTag = (1 << 17), PID1 = (1 << 18),
  PID0 = (1 << 17), IPFail = (1 << 16), UDPFail = (1 << 15), TCPFail = (1 << 14),
  RxVlanTag = (1 << 16)
}
enum  features { RTL_FEATURE_WOL = (1 << 0), RTL_FEATURE_MSI = (1 << 1), RTL_FEATURE_GMII = (1 << 2) }

Functions

 FILE_LICENCE (GPL2_OR_LATER)
static void rtl_hw_start_8169 (struct net_device *)
static void rtl_hw_start_8168 (struct net_device *)
static void rtl_hw_start_8101 (struct net_device *)

Variables

struct {
   const char *   name
   u8   mac_version
   u32   RxConfigMask
} rtl_chip_info []
static const unsigned int rtl8169_rx_config

Define Documentation

#define ARRAY_SIZE ( x   )     (sizeof(x) / sizeof((x)[0]))

Definition at line 32 of file r8169.h.

#define PCI_EXP_DEVCTL   8

FIXME: include/linux/pci_regs.h has these PCI regs, maybe we need such a file in gPXE?

Definition at line 37 of file r8169.h.

Referenced by rtl_hw_start_8101(), and rtl_tx_performance_tweak().

#define PCI_EXP_DEVCTL_READRQ   0x7000

Definition at line 38 of file r8169.h.

Referenced by rtl_tx_performance_tweak().

#define PCI_EXP_LNKCTL   16

Definition at line 39 of file r8169.h.

Referenced by rtl_disable_clock_request().

#define PCI_EXP_LNKCTL_CLKREQ_EN   0x100

Definition at line 40 of file r8169.h.

Referenced by rtl_disable_clock_request().

#define PCI_EXP_DEVCTL_NOSNOOP_EN   0x0800

Definition at line 41 of file r8169.h.

Referenced by rtl_hw_start_8101(), and rtl_hw_start_8168bb().

#define SPEED_10   10

FIXME: update mii.h in src/include/mii.h from Linux sources so we don't have to include these definitiions.

Definition at line 47 of file r8169.h.

#define SPEED_100   100

Definition at line 48 of file r8169.h.

#define SPEED_1000   1000

Definition at line 49 of file r8169.h.

#define SPEED_2500   2500

Definition at line 50 of file r8169.h.

#define SPEED_10000   10000

Definition at line 51 of file r8169.h.

#define DUPLEX_HALF   0x00

Definition at line 54 of file r8169.h.

#define DUPLEX_FULL   0x01

Definition at line 55 of file r8169.h.

#define AUTONEG_DISABLE   0x00

Definition at line 57 of file r8169.h.

#define AUTONEG_ENABLE   0x01

Definition at line 58 of file r8169.h.

#define MAC_ADDR_LEN   6

Definition at line 61 of file r8169.h.

Referenced by rtl8169_probe().

#define MAX_READ_REQUEST_SHIFT   12

Definition at line 63 of file r8169.h.

Referenced by __rtl_hw_start_8168cp(), rtl_hw_start_8102e_1(), rtl_hw_start_8102e_2(), rtl_hw_start_8168bb(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), and rtl_hw_start_8168d().

#define RX_FIFO_THRESH   7

Definition at line 64 of file r8169.h.

Referenced by rtl_open().

#define RX_DMA_BURST   6

Definition at line 65 of file r8169.h.

Referenced by rtl_open().

#define TX_DMA_BURST   6

Definition at line 66 of file r8169.h.

Referenced by rtl_hw_start_8168(), rtl_open(), and rtl_set_rx_tx_config_registers().

#define EarlyTxThld   0x3F

Definition at line 67 of file r8169.h.

Referenced by rtl_hw_start_8101(), rtl_hw_start_8168(), rtl_hw_start_8168bef(), rtl_hw_start_8168cp_3(), rtl_hw_start_8168d(), and rtl_hw_start_8169().

#define RxPacketMaxSize   0x3FE8

Definition at line 68 of file r8169.h.

#define SafeMtu   0x1c20

Definition at line 69 of file r8169.h.

#define InterFrameGap   0x03

Definition at line 70 of file r8169.h.

Referenced by rtl_hw_start_8168(), and rtl_set_rx_tx_config_registers().

#define R8169_REGS_SIZE   256

Definition at line 72 of file r8169.h.

Referenced by rtl8169_probe().

#define R8169_NAPI_WEIGHT   64

Definition at line 73 of file r8169.h.

#define NUM_TX_DESC   8

Definition at line 74 of file r8169.h.

#define NUM_RX_DESC   8

Definition at line 75 of file r8169.h.

#define RX_BUF_SIZE   1536

Definition at line 76 of file r8169.h.

#define R8169_TX_RING_BYTES   (NUM_TX_DESC * sizeof(struct TxDesc))

Definition at line 77 of file r8169.h.

Referenced by rtl8169_free_tx_resources(), and rtl8169_setup_tx_resources().

#define R8169_RX_RING_BYTES   (NUM_RX_DESC * sizeof(struct RxDesc))

Definition at line 78 of file r8169.h.

Referenced by rtl8169_free_rx_resources(), and rtl8169_setup_rx_resources().

#define TX_RING_ALIGN   256

Definition at line 80 of file r8169.h.

#define RX_RING_ALIGN   256

Definition at line 81 of file r8169.h.

#define RTL8169_TX_TIMEOUT   (6*HZ)

Definition at line 83 of file r8169.h.

#define RTL8169_PHY_TIMEOUT   (10*HZ)

Definition at line 84 of file r8169.h.

#define RTL_EEPROM_SIG   cpu_to_le32(0x8129)

Definition at line 86 of file r8169.h.

#define RTL_EEPROM_SIG_MASK   cpu_to_le32(0xffff)

Definition at line 87 of file r8169.h.

#define RTL_EEPROM_SIG_ADDR   0x0000

Definition at line 88 of file r8169.h.

#define RTL_W8 ( reg,
val8   )     writeb ((val8), ioaddr + (reg))

Definition at line 91 of file r8169.h.

Referenced by __rtl_hw_start_8168cp(), rtl8169_hw_reset(), rtl8169_init_phy(), rtl8169_transmit(), rtl_hw_start_8101(), rtl_hw_start_8102e_1(), rtl_hw_start_8102e_2(), rtl_hw_start_8168(), rtl_hw_start_8168bb(), rtl_hw_start_8168bef(), rtl_hw_start_8168c_1(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), rtl_hw_start_8168d(), rtl_hw_start_8169(), and rtl_soft_reset().

#define RTL_W16 ( reg,
val16   )     writew ((val16), ioaddr + (reg))

Definition at line 92 of file r8169.h.

Referenced by __rtl_hw_start_8168cp(), rtl8169_irq_enable(), rtl8169_irq_mask_and_ack(), rtl8169_poll(), rtl_hw_start_8101(), rtl_hw_start_8102e_1(), rtl_hw_start_8102e_2(), rtl_hw_start_8168(), rtl_hw_start_8168bb(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), rtl_hw_start_8168d(), rtl_hw_start_8169(), rtl_rw_cpluscmd(), and rtl_set_rx_max_size().

#define RTL_W32 ( reg,
val32   )     writel ((val32), ioaddr + (reg))

Definition at line 93 of file r8169.h.

Referenced by mdio_read(), mdio_write(), rtl8169_set_magic_reg(), rtl8169_set_speed_tbi(), rtl8169_tbi_reset_enable(), rtl_csi_read(), rtl_csi_write(), rtl_ephy_read(), rtl_ephy_write(), rtl_hw_start_8168(), rtl_hw_start_8169(), rtl_set_rx_mode(), rtl_set_rx_tx_config_registers(), and rtl_set_rx_tx_desc_registers().

#define RTL_R8 ( reg   )     readb (ioaddr + (reg))

Definition at line 94 of file r8169.h.

Referenced by __rtl_hw_start_8168cp(), rtl8169_hw_reset(), rtl8169_init_phy(), rtl8169_probe(), rtl8169_set_magic_reg(), rtl8169_xmii_link_ok(), rtl_hw_start_8101(), rtl_hw_start_8102e_1(), rtl_hw_start_8102e_2(), rtl_hw_start_8168(), rtl_hw_start_8168bb(), rtl_hw_start_8168bef(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), rtl_hw_start_8169(), and rtl_soft_reset().

#define RTL_R16 ( reg   )     readw (ioaddr + (reg))

Definition at line 95 of file r8169.h.

Referenced by __rtl_hw_start_8168cp(), rtl8169_poll(), rtl_hw_start_8101(), rtl_hw_start_8102e_1(), rtl_hw_start_8102e_2(), rtl_hw_start_8168(), rtl_hw_start_8168bb(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), rtl_hw_start_8168d(), rtl_hw_start_8169(), and rtl_rw_cpluscmd().

#define RTL_R32 ( reg   )     ((unsigned long) readl (ioaddr + (reg)))

Definition at line 96 of file r8169.h.

Referenced by mdio_read(), mdio_write(), rtl8169_get_mac_version(), rtl8169_open(), rtl8169_set_speed_tbi(), rtl8169_tbi_link_ok(), rtl8169_tbi_reset_enable(), rtl8169_tbi_reset_pending(), rtl_csi_read(), rtl_csi_write(), rtl_ephy_read(), rtl_ephy_write(), rtl_set_rx_mode(), and rtl_set_rx_tx_config_registers().

#define _R ( NAME,
MAC,
MASK   )     { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

Definition at line 126 of file r8169.h.

#define CSIAR_FLAG   0x80000000

Referenced by rtl_csi_read(), and rtl_csi_write().

#define CSIAR_WRITE_CMD   0x80000000

Referenced by rtl_csi_write().

#define CSIAR_BYTE_ENABLE   0x0f

Referenced by rtl_csi_read(), and rtl_csi_write().

#define CSIAR_BYTE_ENABLE_SHIFT   12

Referenced by rtl_csi_read(), and rtl_csi_write().

#define CSIAR_ADDR_MASK   0x0fff

Referenced by rtl_csi_read(), and rtl_csi_write().

#define EPHYAR_FLAG   0x80000000

Referenced by rtl_ephy_read(), and rtl_ephy_write().

#define EPHYAR_WRITE_CMD   0x80000000

Referenced by rtl_ephy_write().

#define EPHYAR_REG_MASK   0x1f

Referenced by rtl_ephy_read(), and rtl_ephy_write().

#define EPHYAR_REG_SHIFT   16

Referenced by rtl_ephy_read(), and rtl_ephy_write().

#define EPHYAR_DATA_MASK   0xffff

Referenced by rtl_ephy_read(), and rtl_ephy_write().

#define FIX_NAK_1   (1 << 4)

Referenced by rtl_hw_start_8102e_1(), and rtl_hw_start_8168c_1().

#define FIX_NAK_2   (1 << 3)

Referenced by rtl_hw_start_8168c_1().

#define RxProtoUDP   (PID1)

#define RxProtoTCP   (PID0)

#define RxProtoIP   (PID1 | PID0)

#define RxProtoMask   RxProtoIP

#define RsvdMask   0x3fffc000

Definition at line 407 of file r8169.h.

Enumeration Type Documentation

enum mac_version

Enumerator:
RTL_GIGA_MAC_VER_01 
RTL_GIGA_MAC_VER_02 
RTL_GIGA_MAC_VER_03 
RTL_GIGA_MAC_VER_04 
RTL_GIGA_MAC_VER_05 
RTL_GIGA_MAC_VER_06 
RTL_GIGA_MAC_VER_07 
RTL_GIGA_MAC_VER_08 
RTL_GIGA_MAC_VER_09 
RTL_GIGA_MAC_VER_10 
RTL_GIGA_MAC_VER_11 
RTL_GIGA_MAC_VER_12 
RTL_GIGA_MAC_VER_13 
RTL_GIGA_MAC_VER_14 
RTL_GIGA_MAC_VER_15 
RTL_GIGA_MAC_VER_16 
RTL_GIGA_MAC_VER_17 
RTL_GIGA_MAC_VER_18 
RTL_GIGA_MAC_VER_19 
RTL_GIGA_MAC_VER_20 
RTL_GIGA_MAC_VER_21 
RTL_GIGA_MAC_VER_22 
RTL_GIGA_MAC_VER_23 
RTL_GIGA_MAC_VER_24 
RTL_GIGA_MAC_VER_25 

Definition at line 98 of file r8169.h.

00098                  {
00099         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
00100         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
00101         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
00102         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
00103         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
00104         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
00105         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
00106         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
00107         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
00108         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
00109         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
00110         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
00111         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
00112         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
00113         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
00114         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
00115         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
00116         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
00117         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
00118         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
00119         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
00120         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
00121         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
00122         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
00123         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
00124 };

enum cfg_version

Enumerator:
RTL_CFG_0 
RTL_CFG_1 
RTL_CFG_2 

Definition at line 162 of file r8169.h.

00162                  {
00163         RTL_CFG_0 = 0x00,
00164         RTL_CFG_1,
00165         RTL_CFG_2
00166 };

enum rtl_registers

Enumerator:
MAC0 
MAC4 
MAR0 
CounterAddrLow 
CounterAddrHigh 
TxDescStartAddrLow 
TxDescStartAddrHigh 
TxHDescStartAddrLow 
TxHDescStartAddrHigh 
FLASH 
ERSR 
ChipCmd 
TxPoll 
IntrMask 
IntrStatus 
TxConfig 
RxConfig 
RxMissed 
Cfg9346 
Config0 
Config1 
Config2 
Config3 
Config4 
Config5 
MultiIntr 
PHYAR 
PHYstatus 
RxMaxSize 
CPlusCmd 
IntrMitigate 
RxDescAddrLow 
RxDescAddrHigh 
EarlyTxThres 
FuncEvent 
FuncEventMask 
FuncPresetState 
FuncForceEvent 

Definition at line 187 of file r8169.h.

00187                    {
00188         MAC0            = 0,    /* Ethernet hardware address. */
00189         MAC4            = 4,
00190         MAR0            = 8,    /* Multicast filter. */
00191         CounterAddrLow          = 0x10,
00192         CounterAddrHigh         = 0x14,
00193         TxDescStartAddrLow      = 0x20,
00194         TxDescStartAddrHigh     = 0x24,
00195         TxHDescStartAddrLow     = 0x28,
00196         TxHDescStartAddrHigh    = 0x2c,
00197         FLASH           = 0x30,
00198         ERSR            = 0x36,
00199         ChipCmd         = 0x37,
00200         TxPoll          = 0x38,
00201         IntrMask        = 0x3c,
00202         IntrStatus      = 0x3e,
00203         TxConfig        = 0x40,
00204         RxConfig        = 0x44,
00205         RxMissed        = 0x4c,
00206         Cfg9346         = 0x50,
00207         Config0         = 0x51,
00208         Config1         = 0x52,
00209         Config2         = 0x53,
00210         Config3         = 0x54,
00211         Config4         = 0x55,
00212         Config5         = 0x56,
00213         MultiIntr       = 0x5c,
00214         PHYAR           = 0x60,
00215         PHYstatus       = 0x6c,
00216         RxMaxSize       = 0xda,
00217         CPlusCmd        = 0xe0,
00218         IntrMitigate    = 0xe2,
00219         RxDescAddrLow   = 0xe4,
00220         RxDescAddrHigh  = 0xe8,
00221         EarlyTxThres    = 0xec,
00222         FuncEvent       = 0xf0,
00223         FuncEventMask   = 0xf4,
00224         FuncPresetState = 0xf8,
00225         FuncForceEvent  = 0xfc,
00226 };

enum rtl8110_registers

Enumerator:
TBICSR 
TBI_ANAR 
TBI_LPAR 

Definition at line 228 of file r8169.h.

00228                        {
00229         TBICSR                  = 0x64,
00230         TBI_ANAR                = 0x68,
00231         TBI_LPAR                = 0x6a,
00232 };

enum rtl8168_8101_registers

Enumerator:
CSIDR 
CSIAR 
EPHYAR 
DBG_REG 
FIX_NAK_2 

Definition at line 234 of file r8169.h.

00234                             {
00235         CSIDR                   = 0x64,
00236         CSIAR                   = 0x68,
00237 #define CSIAR_FLAG                      0x80000000
00238 #define CSIAR_WRITE_CMD                 0x80000000
00239 #define CSIAR_BYTE_ENABLE               0x0f
00240 #define CSIAR_BYTE_ENABLE_SHIFT         12
00241 #define CSIAR_ADDR_MASK                 0x0fff
00242 
00243         EPHYAR                  = 0x80,
00244 #define EPHYAR_FLAG                     0x80000000
00245 #define EPHYAR_WRITE_CMD                0x80000000
00246 #define EPHYAR_REG_MASK                 0x1f
00247 #define EPHYAR_REG_SHIFT                16
00248 #define EPHYAR_DATA_MASK                0xffff
00249         DBG_REG                 = 0xd1,
00250 #define FIX_NAK_1                       (1 << 4)
00251 #define FIX_NAK_2                       (1 << 3)
00252 };

enum rtl_register_content

Enumerator:
SYSErr 
PCSTimeout 
SWInt 
TxDescUnavail 
RxFIFOOver 
LinkChg 
RxOverflow 
TxErr 
TxOK 
RxErr 
RxOK 
RxFOVF 
RxRWT 
RxRES 
RxRUNT 
RxCRC 
CmdReset 
CmdRxEnb 
CmdTxEnb 
RxBufEmpty 
HPQ 
NPQ 
FSWInt 
Cfg9346_Lock 
Cfg9346_Unlock 
AcceptErr 
AcceptRunt 
AcceptBroadcast 
AcceptMulticast 
AcceptMyPhys 
AcceptAllPhys 
RxCfgFIFOShift 
RxCfgDMAShift 
TxInterFrameGapShift 
TxDMAShift 
LEDS1 
LEDS0 
MSIEnable 
Speed_down 
MEMMAP 
IOMAP 
VPD 
PMEnable 
PCI_Clock_66MHz 
PCI_Clock_33MHz 
MagicPacket 
LinkUp 
Beacon_en 
BWF 
MWF 
UWF 
LanWake 
PMEStatus 
TBIReset 
TBILoopback 
TBINwEnable 
TBINwRestart 
TBILinkOk 
TBINwComplete 
EnableBist 
Mac_dbgo_oe 
Normal_mode 
Force_half_dup 
Force_rxflow_en 
Force_txflow_en 
Cxpl_dbg_sel 
ASF 
PktCntrDisable 
Mac_dbgo_sel 
RxVlan 
RxChkSum 
PCIDAC 
PCIMulRW 
INTT_0 
INTT_1 
INTT_2 
INTT_3 
TBI_Enable 
TxFlowCtrl 
RxFlowCtrl 
_1000bpsF 
_100bps 
_10bps 
LinkStatus 
FullDup 
TBILinkOK 
CounterDump 

Definition at line 254 of file r8169.h.

00254                           {
00255         /* InterruptStatusBits */
00256         SYSErr          = 0x8000,
00257         PCSTimeout      = 0x4000,
00258         SWInt           = 0x0100,
00259         TxDescUnavail   = 0x0080,
00260         RxFIFOOver      = 0x0040,
00261         LinkChg         = 0x0020,
00262         RxOverflow      = 0x0010,
00263         TxErr           = 0x0008,
00264         TxOK            = 0x0004,
00265         RxErr           = 0x0002,
00266         RxOK            = 0x0001,
00267 
00268         /* RxStatusDesc */
00269         RxFOVF  = (1 << 23),
00270         RxRWT   = (1 << 22),
00271         RxRES   = (1 << 21),
00272         RxRUNT  = (1 << 20),
00273         RxCRC   = (1 << 19),
00274 
00275         /* ChipCmdBits */
00276         CmdReset        = 0x10,
00277         CmdRxEnb        = 0x08,
00278         CmdTxEnb        = 0x04,
00279         RxBufEmpty      = 0x01,
00280 
00281         /* TXPoll register p.5 */
00282         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
00283         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
00284         FSWInt          = 0x01,         /* Forced software interrupt */
00285 
00286         /* Cfg9346Bits */
00287         Cfg9346_Lock    = 0x00,
00288         Cfg9346_Unlock  = 0xc0,
00289 
00290         /* rx_mode_bits */
00291         AcceptErr       = 0x20,
00292         AcceptRunt      = 0x10,
00293         AcceptBroadcast = 0x08,
00294         AcceptMulticast = 0x04,
00295         AcceptMyPhys    = 0x02,
00296         AcceptAllPhys   = 0x01,
00297 
00298         /* RxConfigBits */
00299         RxCfgFIFOShift  = 13,
00300         RxCfgDMAShift   =  8,
00301 
00302         /* TxConfigBits */
00303         TxInterFrameGapShift = 24,
00304         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
00305 
00306         /* Config1 register p.24 */
00307         LEDS1           = (1 << 7),
00308         LEDS0           = (1 << 6),
00309         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
00310         Speed_down      = (1 << 4),
00311         MEMMAP          = (1 << 3),
00312         IOMAP           = (1 << 2),
00313         VPD             = (1 << 1),
00314         PMEnable        = (1 << 0),     /* Power Management Enable */
00315 
00316         /* Config2 register p. 25 */
00317         PCI_Clock_66MHz = 0x01,
00318         PCI_Clock_33MHz = 0x00,
00319 
00320         /* Config3 register p.25 */
00321         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
00322         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
00323         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
00324 
00325         /* Config5 register p.27 */
00326         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
00327         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
00328         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
00329         LanWake         = (1 << 1),     /* LanWake enable/disable */
00330         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
00331 
00332         /* TBICSR p.28 */
00333         TBIReset        = 0x80000000,
00334         TBILoopback     = 0x40000000,
00335         TBINwEnable     = 0x20000000,
00336         TBINwRestart    = 0x10000000,
00337         TBILinkOk       = 0x02000000,
00338         TBINwComplete   = 0x01000000,
00339 
00340         /* CPlusCmd p.31 */
00341         EnableBist      = (1 << 15),    // 8168 8101
00342         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
00343         Normal_mode     = (1 << 13),    // unused
00344         Force_half_dup  = (1 << 12),    // 8168 8101
00345         Force_rxflow_en = (1 << 11),    // 8168 8101
00346         Force_txflow_en = (1 << 10),    // 8168 8101
00347         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
00348         ASF             = (1 << 8),     // 8168 8101
00349         PktCntrDisable  = (1 << 7),     // 8168 8101
00350         Mac_dbgo_sel    = 0x001c,       // 8168
00351         RxVlan          = (1 << 6),
00352         RxChkSum        = (1 << 5),
00353         PCIDAC          = (1 << 4),
00354         PCIMulRW        = (1 << 3),
00355         INTT_0          = 0x0000,       // 8168
00356         INTT_1          = 0x0001,       // 8168
00357         INTT_2          = 0x0002,       // 8168
00358         INTT_3          = 0x0003,       // 8168
00359 
00360         /* rtl8169_PHYstatus */
00361         TBI_Enable      = 0x80,
00362         TxFlowCtrl      = 0x40,
00363         RxFlowCtrl      = 0x20,
00364         _1000bpsF       = 0x10,
00365         _100bps         = 0x08,
00366         _10bps          = 0x04,
00367         LinkStatus      = 0x02,
00368         FullDup         = 0x01,
00369 
00370         /* _TBICSRBit */
00371         TBILinkOK       = 0x02000000,
00372 
00373         /* DumpCounterCommand */
00374         CounterDump     = 0x8,
00375 };

enum desc_status_bit

Enumerator:
DescOwn 
RingEnd 
FirstFrag 
LastFrag 
LargeSend 
MSSShift 
MSSMask 
IPCS 
UDPCS 
TCPCS 
TxVlanTag 
PID1 
PID0 
IPFail 
UDPFail 
TCPFail 
RxVlanTag 

Definition at line 377 of file r8169.h.

00377                      {
00378         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
00379         RingEnd         = (1 << 30), /* End of descriptor ring */
00380         FirstFrag       = (1 << 29), /* First segment of a packet */
00381         LastFrag        = (1 << 28), /* Final segment of a packet */
00382 
00383         /* Tx private */
00384         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
00385         MSSShift        = 16,        /* MSS value position */
00386         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
00387         IPCS            = (1 << 18), /* Calculate IP checksum */
00388         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
00389         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
00390         TxVlanTag       = (1 << 17), /* Add VLAN tag */
00391 
00392         /* Rx private */
00393         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
00394         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
00395 
00396 #define RxProtoUDP      (PID1)
00397 #define RxProtoTCP      (PID0)
00398 #define RxProtoIP       (PID1 | PID0)
00399 #define RxProtoMask     RxProtoIP
00400 
00401         IPFail          = (1 << 16), /* IP checksum failed */
00402         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
00403         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
00404         RxVlanTag       = (1 << 16), /* VLAN tag available */
00405 };

enum features

Enumerator:
RTL_FEATURE_WOL 
RTL_FEATURE_MSI 
RTL_FEATURE_GMII 

Definition at line 423 of file r8169.h.

00423               {
00424         RTL_FEATURE_WOL         = (1 << 0),
00425         RTL_FEATURE_MSI         = (1 << 1),
00426         RTL_FEATURE_GMII        = (1 << 2),
00427 };

Function Documentation

FILE_LICENCE ( GPL2_OR_LATER   ) 

static void rtl_hw_start_8169 ( struct net_device *   )  [static]

static void rtl_hw_start_8168 ( struct net_device *   )  [static]

static void rtl_hw_start_8101 ( struct net_device *   )  [static]

Variable Documentation

const char* name

Definition at line 130 of file r8169.h.

Referenced by dhcp_tag_name(), eepro_probe(), expand_command(), imgargs_exec(), imgexec_exec(), imgfetch_core_exec(), imgfree_exec(), imgload_exec(), parse_eeprom(), rtl8169_probe(), sis900_probe(), t515_reset(), tftp_rx_oack(), tlan_probe(), tulip_probe(), vxgetlink(), vxsetlink(), and wpa_check_pmkid().

u8 mac_version

Definition at line 131 of file r8169.h.

u32 RxConfigMask

Definition at line 132 of file r8169.h.

struct { ... } rtl_chip_info[] [static]

Referenced by rtl8169_probe(), rtl_set_rx_mode(), and rtl_set_rx_tx_config_registers().

const unsigned int rtl8169_rx_config [static]

Initial value:

        (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift)

Definition at line 476 of file r8169.h.

Referenced by rtl_set_rx_mode(), and rtl_set_rx_tx_config_registers().

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