#include <stdint.h>#include <stdio.h>#include <stdlib.h>#include <string.h>#include <unistd.h>#include <assert.h>#include <byteswap.h>#include <errno.h>#include <gpxe/ethernet.h>#include <gpxe/if_ether.h>#include <gpxe/io.h>#include <gpxe/iobuf.h>#include <gpxe/malloc.h>#include <gpxe/netdevice.h>#include <gpxe/pci.h>#include <gpxe/timer.h>#include <mii.h>#include "r8169.h"Go to the source code of this file.
Data Structures | |
| struct | phy_reg |
| struct | rtl_cfg_info |
| struct | ephy_info |
Defines | |
| #define | R8168_CPCMD_QUIRK_MASK |
| #define | R810X_CPCMD_QUIRK_MASK |
| #define | _R(VENDOR, DEVICE, INDEX) { .vendor = VENDOR, .device = DEVICE, .index = INDEX } |
| FIXME: Because gPXE's pci_device_id structure does not contain a field to contain arbitrary data, we need the following table to associate PCI IDs with nic variants, because a lot of driver routines depend on knowing which kind of variant they are dealing with. | |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| static void | mdio_write (void *ioaddr, int reg_addr, int value) |
| static int | mdio_read (void *ioaddr, int reg_addr) |
| static void | mdio_patch (void *ioaddr, int reg_addr, int value) |
| static void | rtl_ephy_write (void *ioaddr, int reg_addr, int value) |
| static u16 | rtl_ephy_read (void *ioaddr, int reg_addr) |
| static void | rtl_csi_write (void *ioaddr, int addr, int value) |
| static u32 | rtl_csi_read (void *ioaddr, int addr) |
| static void | rtl8169_irq_mask_and_ack (void *ioaddr) |
| static unsigned int | rtl8169_tbi_reset_pending (void *ioaddr) |
| static unsigned int | rtl8169_xmii_reset_pending (void *ioaddr) |
| static unsigned int | rtl8169_tbi_link_ok (void *ioaddr) |
| static unsigned int | rtl8169_xmii_link_ok (void *ioaddr) |
| static void | rtl8169_tbi_reset_enable (void *ioaddr) |
| static void | rtl8169_xmii_reset_enable (void *ioaddr) |
| static int | rtl8169_set_speed_tbi (struct net_device *dev, u8 autoneg, u16 speed, u8 duplex) |
| static int | rtl8169_set_speed_xmii (struct net_device *dev, u8 autoneg, u16 speed, u8 duplex) |
| static int | rtl8169_set_speed (struct net_device *dev, u8 autoneg, u16 speed, u8 duplex) |
| static void | rtl8169_write_gmii_reg_bit (void *ioaddr, int reg, int bitnum, int bitval) |
| static void | rtl8169_get_mac_version (struct rtl8169_private *tp, void *ioaddr) |
| static void | rtl_phy_write (void *ioaddr, struct phy_reg *regs, int len) |
| static void | rtl8169s_hw_phy_config (void *ioaddr) |
| static void | rtl8169sb_hw_phy_config (void *ioaddr) |
| static void | rtl8168bb_hw_phy_config (void *ioaddr) |
| static void | rtl8168bef_hw_phy_config (void *ioaddr) |
| static void | rtl8168cp_1_hw_phy_config (void *ioaddr) |
| static void | rtl8168cp_2_hw_phy_config (void *ioaddr) |
| static void | rtl8168c_1_hw_phy_config (void *ioaddr) |
| static void | rtl8168c_2_hw_phy_config (void *ioaddr) |
| static void | rtl8168c_3_hw_phy_config (void *ioaddr) |
| static void | rtl8168c_4_hw_phy_config (void *ioaddr) |
| static void | rtl8168d_hw_phy_config (void *ioaddr) |
| static void | rtl8102e_hw_phy_config (void *ioaddr) |
| static void | rtl_hw_phy_config (struct net_device *dev) |
| static void | rtl8169_phy_reset (struct net_device *dev __unused, struct rtl8169_private *tp) |
| static void | rtl8169_init_phy (struct net_device *dev, struct rtl8169_private *tp) |
| static void | rtl8169_hw_reset (void *ioaddr) |
| static void | rtl_set_rx_tx_config_registers (struct rtl8169_private *tp) |
| static void | rtl_soft_reset (struct net_device *dev) |
| static void | rtl_hw_start (struct net_device *dev) |
| static void | rtl_set_rx_tx_desc_registers (struct rtl8169_private *tp, void *ioaddr) |
| static u16 | rtl_rw_cpluscmd (void *ioaddr) |
| static void | rtl_set_rx_max_size (void *ioaddr) |
| static void | rtl8169_set_magic_reg (void *ioaddr, unsigned mac_version) |
| static void | rtl_set_rx_mode (struct net_device *netdev) |
| static void | rtl_hw_start_8169 (struct net_device *dev) |
| static void | rtl_tx_performance_tweak (struct pci_device *pdev, u16 force) |
| static void | rtl_csi_access_enable (void *ioaddr) |
| static void | rtl_ephy_init (void *ioaddr, struct ephy_info *e, int len) |
| static void | rtl_disable_clock_request (struct pci_device *pdev) |
| static void | rtl_hw_start_8168bb (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168bef (void *ioaddr, struct pci_device *pdev) |
| static void | __rtl_hw_start_8168cp (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168cp_1 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168cp_2 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168cp_3 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168c_1 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168c_2 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168c_3 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168c_4 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168d (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8168 (struct net_device *dev) |
| static void | rtl_hw_start_8102e_1 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8102e_2 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8102e_3 (void *ioaddr, struct pci_device *pdev) |
| static void | rtl_hw_start_8101 (struct net_device *dev) |
| static int | rtl8169_setup_tx_resources (struct rtl8169_private *tp) |
| setup_tx_resources - allocate tx resources (descriptors) | |
| static void | rtl8169_process_tx_packets (struct net_device *netdev) |
| static void | rtl8169_free_tx_resources (struct rtl8169_private *tp) |
| static void | rtl8169_populate_rx_descriptor (struct rtl8169_private *tp, struct RxDesc *rx_desc, uint32_t index) |
| static void | rtl8169_refill_rx_ring (struct rtl8169_private *tp) |
| Refill descriptor ring. | |
| static int | rtl8169_setup_rx_resources (struct rtl8169_private *tp) |
| setup_rx_resources - allocate Rx resources (Descriptors) | |
| static void | rtl8169_process_rx_packets (struct net_device *netdev) |
| static void | rtl8169_free_rx_resources (struct rtl8169_private *tp) |
| static int | rtl8169_get_nic_variant (uint16_t vendor, uint16_t device) |
| static void | rtl8169_irq_enable (struct rtl8169_private *tp) |
| static void | rtl8169_irq_disable (struct rtl8169_private *tp) |
| static int | rtl8169_open (struct net_device *netdev) |
| open - Called when a network interface is made active | |
| static int | rtl8169_transmit (struct net_device *netdev, struct io_buffer *iobuf) |
| transmit - Transmit a packet | |
| static void | rtl8169_poll (struct net_device *netdev) |
| poll - Poll for received packets | |
| static void | rtl8169_close (struct net_device *netdev) |
| close - Disable network interface | |
| static void | rtl8169_irq (struct net_device *netdev, int action) |
| irq - enable or Disable interrupts | |
| static int | rtl8169_probe (struct pci_device *pdev, const struct pci_device_id *ent) |
| probe - Initial configuration of NIC | |
| static void | rtl8169_remove (struct pci_device *pdev) |
| remove - Device Removal Routine | |
Variables | |
| static struct rtl_cfg_info | rtl_cfg_infos [] |
| struct { | |
| uint16_t vendor | |
| uint16_t device | |
| int index | |
| } | nic_variant_table [] |
| static struct net_device_operations | rtl8169_operations |
| static struct pci_device_id | rtl8169_nics [] |
| struct pci_driver rtl8169_driver | __pci_driver |
| #define R8168_CPCMD_QUIRK_MASK |
Value:
(\
EnableBist | \
Mac_dbgo_oe | \
Force_half_dup | \
Force_rxflow_en | \
Force_txflow_en | \
Cxpl_dbg_sel | \
ASF | \
PktCntrDisable | \
Mac_dbgo_sel)
Definition at line 1191 of file r8169.c.
Referenced by __rtl_hw_start_8168cp(), rtl_hw_start_8168bb(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), and rtl_hw_start_8168d().
| #define R810X_CPCMD_QUIRK_MASK |
Value:
(\
EnableBist | \
Mac_dbgo_oe | \
Force_half_dup | \
Force_half_dup | \
Force_txflow_en | \
Cxpl_dbg_sel | \
ASF | \
PktCntrDisable | \
PCIDAC | \
PCIMulRW)
Definition at line 1448 of file r8169.c.
Referenced by rtl_hw_start_8102e_1(), and rtl_hw_start_8102e_2().
FIXME: Because gPXE's pci_device_id structure does not contain a field to contain arbitrary data, we need the following table to associate PCI IDs with nic variants, because a lot of driver routines depend on knowing which kind of variant they are dealing with.
--mdc
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
| static void mdio_write | ( | void * | ioaddr, | |
| int | reg_addr, | |||
| int | value | |||
| ) | [static] |
Definition at line 50 of file r8169.c.
References DBGP, PHYAR, RTL_R32, RTL_W32, and udelay().
Referenced by __mdio_write(), mdio_patch(), rtl8102e_hw_phy_config(), rtl8168bb_hw_phy_config(), rtl8168c_1_hw_phy_config(), rtl8168c_2_hw_phy_config(), rtl8168c_3_hw_phy_config(), rtl8168cp_2_hw_phy_config(), rtl8168d_hw_phy_config(), rtl8169_init_phy(), rtl8169_set_speed_xmii(), rtl8169_write_gmii_reg_bit(), rtl8169_xmii_reset_enable(), rtl8169s_hw_phy_config(), rtl_phy_write(), select_media(), sis190_default_phy(), sis190_mii_probe_88e1111_fixup(), sis190_phy_task(), sis190_set_speed_auto(), start_link(), and sundance_probe().
00051 { 00052 int i; 00053 00054 DBGP ( "mdio_write\n" ); 00055 00056 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); 00057 00058 for (i = 20; i > 0; i--) { 00059 /* 00060 * Check if the RTL8169 has completed writing to the specified 00061 * MII register. 00062 */ 00063 if (!(RTL_R32(PHYAR) & 0x80000000)) 00064 break; 00065 udelay(25); 00066 } 00067 }
| static int mdio_read | ( | void * | ioaddr, | |
| int | reg_addr | |||
| ) | [static] |
Definition at line 69 of file r8169.c.
References DBGP, PHYAR, RTL_R32, RTL_W32, and udelay().
00070 { 00071 int i, value = -1; 00072 00073 DBGP ( "mdio_read\n" ); 00074 00075 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); 00076 00077 for (i = 20; i > 0; i--) { 00078 /* 00079 * Check if the RTL8169 has completed retrieving data from 00080 * the specified MII register. 00081 */ 00082 if (RTL_R32(PHYAR) & 0x80000000) { 00083 value = RTL_R32(PHYAR) & 0xffff; 00084 break; 00085 } 00086 udelay(25); 00087 } 00088 return value; 00089 }
| static void mdio_patch | ( | void * | ioaddr, | |
| int | reg_addr, | |||
| int | value | |||
| ) | [static] |
Definition at line 91 of file r8169.c.
References DBGP, mdio_read(), and mdio_write().
Referenced by rtl8102e_hw_phy_config(), rtl8168bb_hw_phy_config(), rtl8168c_1_hw_phy_config(), rtl8168c_2_hw_phy_config(), rtl8168c_3_hw_phy_config(), and rtl8168cp_2_hw_phy_config().
00092 { 00093 DBGP ( "mdio_patch\n" ); 00094 00095 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); 00096 }
| static void rtl_ephy_write | ( | void * | ioaddr, | |
| int | reg_addr, | |||
| int | value | |||
| ) | [static] |
Definition at line 98 of file r8169.c.
References DBGP, EPHYAR, EPHYAR_DATA_MASK, EPHYAR_FLAG, EPHYAR_REG_MASK, EPHYAR_REG_SHIFT, EPHYAR_WRITE_CMD, RTL_R32, RTL_W32, and udelay().
Referenced by rtl_ephy_init(), and rtl_hw_start_8102e_3().
00099 { 00100 unsigned int i; 00101 00102 DBGP ( "rtl_ephy_write\n" ); 00103 00104 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 00105 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 00106 00107 for (i = 0; i < 100; i++) { 00108 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) 00109 break; 00110 udelay(10); 00111 } 00112 }
| static u16 rtl_ephy_read | ( | void * | ioaddr, | |
| int | reg_addr | |||
| ) | [static] |
Definition at line 114 of file r8169.c.
References DBGP, EPHYAR, EPHYAR_DATA_MASK, EPHYAR_FLAG, EPHYAR_REG_MASK, EPHYAR_REG_SHIFT, RTL_R32, RTL_W32, u16, and udelay().
Referenced by rtl_ephy_init().
00115 { 00116 u16 value = 0xffff; 00117 unsigned int i; 00118 00119 DBGP ( "rtl_ephy_read\n" ); 00120 00121 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 00122 00123 for (i = 0; i < 100; i++) { 00124 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { 00125 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; 00126 break; 00127 } 00128 udelay(10); 00129 } 00130 00131 return value; 00132 }
| static void rtl_csi_write | ( | void * | ioaddr, | |
| int | addr, | |||
| int | value | |||
| ) | [static] |
Definition at line 134 of file r8169.c.
References CSIAR, CSIAR_ADDR_MASK, CSIAR_BYTE_ENABLE, CSIAR_BYTE_ENABLE_SHIFT, CSIAR_FLAG, CSIAR_WRITE_CMD, CSIDR, DBGP, RTL_R32, RTL_W32, and udelay().
Referenced by rtl_csi_access_enable().
00135 { 00136 unsigned int i; 00137 00138 DBGP ( "rtl_csi_write\n" ); 00139 00140 RTL_W32(CSIDR, value); 00141 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 00142 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); 00143 00144 for (i = 0; i < 100; i++) { 00145 if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) 00146 break; 00147 udelay(10); 00148 } 00149 }
| static u32 rtl_csi_read | ( | void * | ioaddr, | |
| int | addr | |||
| ) | [static] |
Definition at line 151 of file r8169.c.
References CSIAR, CSIAR_ADDR_MASK, CSIAR_BYTE_ENABLE, CSIAR_BYTE_ENABLE_SHIFT, CSIAR_FLAG, CSIDR, DBGP, RTL_R32, RTL_W32, u32, and udelay().
Referenced by rtl_csi_access_enable().
00152 { 00153 u32 value = ~0x00; 00154 unsigned int i; 00155 00156 DBGP ( "rtl_csi_read\n" ); 00157 00158 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | 00159 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); 00160 00161 for (i = 0; i < 100; i++) { 00162 if (RTL_R32(CSIAR) & CSIAR_FLAG) { 00163 value = RTL_R32(CSIDR); 00164 break; 00165 } 00166 udelay(10); 00167 } 00168 00169 return value; 00170 }
| static void rtl8169_irq_mask_and_ack | ( | void * | ioaddr | ) | [static] |
Definition at line 172 of file r8169.c.
References DBGP, IntrMask, IntrStatus, and RTL_W16.
Referenced by rtl8169_hw_reset(), rtl8169_irq_disable(), and rtl8169_probe().
00173 { 00174 DBGP ( "rtl8169_irq_mask_and_ack\n" ); 00175 00176 RTL_W16(IntrMask, 0x0000); 00177 00178 RTL_W16(IntrStatus, 0xffff); 00179 }
| static unsigned int rtl8169_tbi_reset_pending | ( | void * | ioaddr | ) | [static] |
| static unsigned int rtl8169_xmii_reset_pending | ( | void * | ioaddr | ) | [static] |
Definition at line 188 of file r8169.c.
References BMCR_RESET, DBGP, mdio_read(), and MII_BMCR.
Referenced by rtl8169_probe().
00189 { 00190 DBGP ( "rtl8169_xmii_reset_pending\n" ); 00191 00192 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; 00193 }
| static unsigned int rtl8169_tbi_link_ok | ( | void * | ioaddr | ) | [static] |
| static unsigned int rtl8169_xmii_link_ok | ( | void * | ioaddr | ) | [static] |
Definition at line 202 of file r8169.c.
References DBGP, LinkStatus, PHYstatus, and RTL_R8.
Referenced by rtl8169_probe().
00203 { 00204 DBGP ( "rtl8169_xmii_link_ok\n" ); 00205 00206 return RTL_R8(PHYstatus) & LinkStatus; 00207 }
| static void rtl8169_tbi_reset_enable | ( | void * | ioaddr | ) | [static] |
| static void rtl8169_xmii_reset_enable | ( | void * | ioaddr | ) | [static] |
Definition at line 216 of file r8169.c.
References BMCR_RESET, DBGP, mdio_read(), mdio_write(), and MII_BMCR.
Referenced by rtl8169_probe().
00217 { 00218 unsigned int val; 00219 00220 DBGP ( "rtl8169_xmii_reset_enable\n" ); 00221 00222 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; 00223 mdio_write(ioaddr, MII_BMCR, val & 0xffff); 00224 }
| static int rtl8169_set_speed_tbi | ( | struct net_device * | dev, | |
| u8 | autoneg, | |||
| u16 | speed, | |||
| u8 | duplex | |||
| ) | [static] |
Definition at line 226 of file r8169.c.
References AUTONEG_DISABLE, AUTONEG_ENABLE, DBG, DBGP, DUPLEX_FULL, EOPNOTSUPP, ioaddr, rtl8169_private::mmio_addr, netdev_priv(), RTL_R32, RTL_W32, SPEED_1000, TBICSR, TBINwEnable, TBINwRestart, tp, and u32.
Referenced by rtl8169_probe().
00228 { 00229 struct rtl8169_private *tp = netdev_priv(dev); 00230 void *ioaddr = tp->mmio_addr; 00231 int ret = 0; 00232 u32 reg; 00233 00234 DBGP ( "rtl8169_set_speed_tbi\n" ); 00235 00236 reg = RTL_R32(TBICSR); 00237 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && 00238 (duplex == DUPLEX_FULL)) { 00239 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); 00240 } else if (autoneg == AUTONEG_ENABLE) 00241 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); 00242 else { 00243 DBG ( "incorrect speed setting refused in TBI mode\n" ); 00244 ret = -EOPNOTSUPP; 00245 } 00246 return ret; 00247 }
| static int rtl8169_set_speed_xmii | ( | struct net_device * | dev, | |
| u8 | autoneg, | |||
| u16 | speed, | |||
| u8 | duplex | |||
| ) | [static] |
Definition at line 249 of file r8169.c.
References ADVERTISE_1000FULL, ADVERTISE_1000HALF, ADVERTISE_100FULL, ADVERTISE_100HALF, ADVERTISE_10FULL, ADVERTISE_10HALF, ADVERTISE_CSMA, ADVERTISE_PAUSE_ASYM, ADVERTISE_PAUSE_CAP, AUTONEG_ENABLE, BMCR_ANENABLE, BMCR_ANRESTART, DBG, DBGP, DUPLEX_FULL, DUPLEX_HALF, ioaddr, rtl8169_private::mac_version, mdio_read(), mdio_write(), MII_ADVERTISE, MII_BMCR, MII_CTRL1000, rtl8169_private::mmio_addr, netdev_priv(), rtl8169_private::phy_1000_ctrl_reg, rtl8169_private::phy_auto_nego_reg, RTL_GIGA_MAC_VER_07, RTL_GIGA_MAC_VER_08, RTL_GIGA_MAC_VER_09, RTL_GIGA_MAC_VER_10, RTL_GIGA_MAC_VER_11, RTL_GIGA_MAC_VER_12, RTL_GIGA_MAC_VER_13, RTL_GIGA_MAC_VER_14, RTL_GIGA_MAC_VER_15, RTL_GIGA_MAC_VER_16, RTL_GIGA_MAC_VER_17, SPEED_10, SPEED_100, SPEED_1000, and tp.
Referenced by rtl8169_probe().
00251 { 00252 struct rtl8169_private *tp = netdev_priv(dev); 00253 void *ioaddr = tp->mmio_addr; 00254 int auto_nego, giga_ctrl; 00255 00256 DBGP ( "rtl8169_set_speed_xmii\n" ); 00257 00258 auto_nego = mdio_read(ioaddr, MII_ADVERTISE); 00259 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 00260 ADVERTISE_100HALF | ADVERTISE_100FULL); 00261 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); 00262 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 00263 00264 if (autoneg == AUTONEG_ENABLE) { 00265 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | 00266 ADVERTISE_100HALF | ADVERTISE_100FULL); 00267 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 00268 } else { 00269 if (speed == SPEED_10) 00270 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; 00271 else if (speed == SPEED_100) 00272 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; 00273 else if (speed == SPEED_1000) 00274 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 00275 00276 if (duplex == DUPLEX_HALF) 00277 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); 00278 00279 if (duplex == DUPLEX_FULL) 00280 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); 00281 00282 /* This tweak comes straight from Realtek's driver. */ 00283 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && 00284 ((tp->mac_version == RTL_GIGA_MAC_VER_13) || 00285 (tp->mac_version == RTL_GIGA_MAC_VER_16))) { 00286 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; 00287 } 00288 } 00289 00290 /* The 8100e/8101e/8102e do Fast Ethernet only. */ 00291 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) || 00292 (tp->mac_version == RTL_GIGA_MAC_VER_08) || 00293 (tp->mac_version == RTL_GIGA_MAC_VER_09) || 00294 (tp->mac_version == RTL_GIGA_MAC_VER_10) || 00295 (tp->mac_version == RTL_GIGA_MAC_VER_13) || 00296 (tp->mac_version == RTL_GIGA_MAC_VER_14) || 00297 (tp->mac_version == RTL_GIGA_MAC_VER_15) || 00298 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { 00299 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF))) { 00300 DBG ( "PHY does not support 1000Mbps.\n" ); 00301 } 00302 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 00303 } 00304 00305 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 00306 00307 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || 00308 (tp->mac_version == RTL_GIGA_MAC_VER_12) || 00309 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { 00310 /* 00311 * Wake up the PHY. 00312 * Vendor specific (0x1f) and reserved (0x0e) MII registers. 00313 */ 00314 mdio_write(ioaddr, 0x1f, 0x0000); 00315 mdio_write(ioaddr, 0x0e, 0x0000); 00316 } 00317 00318 tp->phy_auto_nego_reg = auto_nego; 00319 tp->phy_1000_ctrl_reg = giga_ctrl; 00320 00321 mdio_write(ioaddr, MII_ADVERTISE, auto_nego); 00322 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); 00323 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); 00324 return 0; 00325 }
| static int rtl8169_set_speed | ( | struct net_device * | dev, | |
| u8 | autoneg, | |||
| u16 | speed, | |||
| u8 | duplex | |||
| ) | [static] |
Definition at line 327 of file r8169.c.
References DBGP, netdev_priv(), rtl8169_private::set_speed, and tp.
Referenced by rtl8169_init_phy().
00329 { 00330 struct rtl8169_private *tp = netdev_priv(dev); 00331 int ret; 00332 00333 DBGP ( "rtl8169_set_speed\n" ); 00334 00335 ret = tp->set_speed(dev, autoneg, speed, duplex); 00336 00337 return ret; 00338 }
| static void rtl8169_write_gmii_reg_bit | ( | void * | ioaddr, | |
| int | reg, | |||
| int | bitnum, | |||
| int | bitval | |||
| ) | [static] |
Definition at line 340 of file r8169.c.
References DBGP, mdio_read(), and mdio_write().
Referenced by rtl8169s_hw_phy_config().
00342 { 00343 int val; 00344 00345 DBGP ( "rtl8169_write_gmii_reg_bit\n" ); 00346 00347 val = mdio_read(ioaddr, reg); 00348 val = (bitval == 1) ? 00349 val | (bitval << bitnum) : val & ~(0x0001 << bitnum); 00350 mdio_write(ioaddr, reg, val & 0xffff); 00351 }
| static void rtl8169_get_mac_version | ( | struct rtl8169_private * | tp, | |
| void * | ioaddr | |||
| ) | [static] |
Definition at line 353 of file r8169.c.
References DBG, DBGP, rtl8169_private::mac_version, RTL_GIGA_MAC_VER_01, RTL_GIGA_MAC_VER_02, RTL_GIGA_MAC_VER_03, RTL_GIGA_MAC_VER_04, RTL_GIGA_MAC_VER_05, RTL_GIGA_MAC_VER_06, RTL_GIGA_MAC_VER_07, RTL_GIGA_MAC_VER_08, RTL_GIGA_MAC_VER_09, RTL_GIGA_MAC_VER_10, RTL_GIGA_MAC_VER_11, RTL_GIGA_MAC_VER_12, RTL_GIGA_MAC_VER_13, RTL_GIGA_MAC_VER_14, RTL_GIGA_MAC_VER_15, RTL_GIGA_MAC_VER_16, RTL_GIGA_MAC_VER_17, RTL_GIGA_MAC_VER_18, RTL_GIGA_MAC_VER_19, RTL_GIGA_MAC_VER_20, RTL_GIGA_MAC_VER_21, RTL_GIGA_MAC_VER_22, RTL_GIGA_MAC_VER_23, RTL_GIGA_MAC_VER_24, RTL_GIGA_MAC_VER_25, RTL_R32, TxConfig, and u32.
Referenced by rtl8169_probe().
00355 { 00356 /* 00357 * The driver currently handles the 8168Bf and the 8168Be identically 00358 * but they can be identified more specifically through the test below 00359 * if needed: 00360 * 00361 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 00362 * 00363 * Same thing for the 8101Eb and the 8101Ec: 00364 * 00365 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 00366 */ 00367 const struct { 00368 u32 mask; 00369 u32 val; 00370 int mac_version; 00371 } mac_info[] = { 00372 /* 8168D family. */ 00373 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 }, 00374 00375 /* 8168C family. */ 00376 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, 00377 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, 00378 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, 00379 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, 00380 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, 00381 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, 00382 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, 00383 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, 00384 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, 00385 00386 /* 8168B family. */ 00387 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, 00388 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, 00389 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, 00390 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, 00391 00392 /* 8101 family. */ 00393 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, 00394 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, 00395 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, 00396 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, 00397 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, 00398 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, 00399 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, 00400 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, 00401 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, 00402 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, 00403 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, 00404 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, 00405 /* FIXME: where did these entries come from ? -- FR */ 00406 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, 00407 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, 00408 00409 /* 8110 family. */ 00410 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, 00411 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, 00412 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, 00413 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, 00414 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, 00415 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, 00416 00417 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ 00418 }, *p = mac_info; 00419 u32 reg; 00420 00421 DBGP ( "rtl8169_get_mac_version\n" ); 00422 00423 reg = RTL_R32(TxConfig); 00424 while ((reg & p->mask) != p->val) 00425 p++; 00426 tp->mac_version = p->mac_version; 00427 00428 DBG ( "tp->mac_version = %d\n", tp->mac_version ); 00429 00430 if (p->mask == 0x00000000) { 00431 DBG ( "unknown MAC (%08x)\n", reg ); 00432 } 00433 }
| static void rtl_phy_write | ( | void * | ioaddr, | |
| struct phy_reg * | regs, | |||
| int | len | |||
| ) | [static] |
Definition at line 440 of file r8169.c.
References DBGP, mdio_write(), phy_reg::reg, and phy_reg::val.
Referenced by rtl8102e_hw_phy_config(), rtl8168bb_hw_phy_config(), rtl8168bef_hw_phy_config(), rtl8168c_1_hw_phy_config(), rtl8168c_2_hw_phy_config(), rtl8168c_3_hw_phy_config(), rtl8168cp_1_hw_phy_config(), rtl8168cp_2_hw_phy_config(), rtl8168d_hw_phy_config(), and rtl8169sb_hw_phy_config().
00441 { 00442 DBGP ( "rtl_phy_write\n" ); 00443 00444 while (len-- > 0) { 00445 mdio_write(ioaddr, regs->reg, regs->val); 00446 regs++; 00447 } 00448 }
| static void rtl8169s_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 450 of file r8169.c.
References ARRAY_SIZE, DBGP, mdio_read(), mdio_write(), rtl8169_write_gmii_reg_bit(), and u16.
Referenced by rtl_hw_phy_config().
00451 { 00452 struct { 00453 u16 regs[5]; /* Beware of bit-sign propagation */ 00454 } phy_magic[5] = { { 00455 { 0x0000, //w 4 15 12 0 00456 0x00a1, //w 3 15 0 00a1 00457 0x0008, //w 2 15 0 0008 00458 0x1020, //w 1 15 0 1020 00459 0x1000 } },{ //w 0 15 0 1000 00460 { 0x7000, //w 4 15 12 7 00461 0xff41, //w 3 15 0 ff41 00462 0xde60, //w 2 15 0 de60 00463 0x0140, //w 1 15 0 0140 00464 0x0077 } },{ //w 0 15 0 0077 00465 { 0xa000, //w 4 15 12 a 00466 0xdf01, //w 3 15 0 df01 00467 0xdf20, //w 2 15 0 df20 00468 0xff95, //w 1 15 0 ff95 00469 0xfa00 } },{ //w 0 15 0 fa00 00470 { 0xb000, //w 4 15 12 b 00471 0xff41, //w 3 15 0 ff41 00472 0xde20, //w 2 15 0 de20 00473 0x0140, //w 1 15 0 0140 00474 0x00bb } },{ //w 0 15 0 00bb 00475 { 0xf000, //w 4 15 12 f 00476 0xdf01, //w 3 15 0 df01 00477 0xdf20, //w 2 15 0 df20 00478 0xff95, //w 1 15 0 ff95 00479 0xbf00 } //w 0 15 0 bf00 00480 } 00481 }, *p = phy_magic; 00482 unsigned int i; 00483 00484 DBGP ( "rtl8169s_hw_phy_config\n" ); 00485 00486 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 00487 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 00488 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 00489 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 00490 00491 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { 00492 int val, pos = 4; 00493 00494 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); 00495 mdio_write(ioaddr, pos, val); 00496 while (--pos >= 0) 00497 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); 00498 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 00499 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 00500 } 00501 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 00502 }
| static void rtl8169sb_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 504 of file r8169.c.
References ARRAY_SIZE, DBGP, and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00505 { 00506 struct phy_reg phy_reg_init[] = { 00507 { 0x1f, 0x0002 }, 00508 { 0x01, 0x90d0 }, 00509 { 0x1f, 0x0000 } 00510 }; 00511 00512 DBGP ( "rtl8169sb_hw_phy_config\n" ); 00513 00514 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00515 }
| static void rtl8168bb_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 517 of file r8169.c.
References ARRAY_SIZE, DBGP, mdio_patch(), mdio_write(), and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00518 { 00519 struct phy_reg phy_reg_init[] = { 00520 { 0x10, 0xf41b }, 00521 { 0x1f, 0x0000 } 00522 }; 00523 00524 mdio_write(ioaddr, 0x1f, 0x0001); 00525 mdio_patch(ioaddr, 0x16, 1 << 0); 00526 00527 DBGP ( "rtl8168bb_hw_phy_config\n" ); 00528 00529 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00530 }
| static void rtl8168bef_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 532 of file r8169.c.
References ARRAY_SIZE, DBGP, and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00533 { 00534 struct phy_reg phy_reg_init[] = { 00535 { 0x1f, 0x0001 }, 00536 { 0x10, 0xf41b }, 00537 { 0x1f, 0x0000 } 00538 }; 00539 00540 DBGP ( "rtl8168bef_hw_phy_config\n" ); 00541 00542 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00543 }
| static void rtl8168cp_1_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 545 of file r8169.c.
References ARRAY_SIZE, DBGP, and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00546 { 00547 struct phy_reg phy_reg_init[] = { 00548 { 0x1f, 0x0000 }, 00549 { 0x1d, 0x0f00 }, 00550 { 0x1f, 0x0002 }, 00551 { 0x0c, 0x1ec8 }, 00552 { 0x1f, 0x0000 } 00553 }; 00554 00555 DBGP ( "rtl8168cp_1_hw_phy_config\n" ); 00556 00557 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00558 }
| static void rtl8168cp_2_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 560 of file r8169.c.
References ARRAY_SIZE, DBGP, mdio_patch(), mdio_write(), and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00561 { 00562 struct phy_reg phy_reg_init[] = { 00563 { 0x1f, 0x0001 }, 00564 { 0x1d, 0x3d98 }, 00565 { 0x1f, 0x0000 } 00566 }; 00567 00568 DBGP ( "rtl8168cp_2_hw_phy_config\n" ); 00569 00570 mdio_write(ioaddr, 0x1f, 0x0000); 00571 mdio_patch(ioaddr, 0x14, 1 << 5); 00572 mdio_patch(ioaddr, 0x0d, 1 << 5); 00573 00574 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00575 }
| static void rtl8168c_1_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 577 of file r8169.c.
References ARRAY_SIZE, DBGP, mdio_patch(), mdio_write(), and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00578 { 00579 struct phy_reg phy_reg_init[] = { 00580 { 0x1f, 0x0001 }, 00581 { 0x12, 0x2300 }, 00582 { 0x1f, 0x0002 }, 00583 { 0x00, 0x88d4 }, 00584 { 0x01, 0x82b1 }, 00585 { 0x03, 0x7002 }, 00586 { 0x08, 0x9e30 }, 00587 { 0x09, 0x01f0 }, 00588 { 0x0a, 0x5500 }, 00589 { 0x0c, 0x00c8 }, 00590 { 0x1f, 0x0003 }, 00591 { 0x12, 0xc096 }, 00592 { 0x16, 0x000a }, 00593 { 0x1f, 0x0000 }, 00594 { 0x1f, 0x0000 }, 00595 { 0x09, 0x2000 }, 00596 { 0x09, 0x0000 } 00597 }; 00598 00599 DBGP ( "rtl8168c_1_hw_phy_config\n" ); 00600 00601 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00602 00603 mdio_patch(ioaddr, 0x14, 1 << 5); 00604 mdio_patch(ioaddr, 0x0d, 1 << 5); 00605 mdio_write(ioaddr, 0x1f, 0x0000); 00606 }
| static void rtl8168c_2_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 608 of file r8169.c.
References ARRAY_SIZE, DBGP, mdio_patch(), mdio_write(), and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00609 { 00610 struct phy_reg phy_reg_init[] = { 00611 { 0x1f, 0x0001 }, 00612 { 0x12, 0x2300 }, 00613 { 0x03, 0x802f }, 00614 { 0x02, 0x4f02 }, 00615 { 0x01, 0x0409 }, 00616 { 0x00, 0xf099 }, 00617 { 0x04, 0x9800 }, 00618 { 0x04, 0x9000 }, 00619 { 0x1d, 0x3d98 }, 00620 { 0x1f, 0x0002 }, 00621 { 0x0c, 0x7eb8 }, 00622 { 0x06, 0x0761 }, 00623 { 0x1f, 0x0003 }, 00624 { 0x16, 0x0f0a }, 00625 { 0x1f, 0x0000 } 00626 }; 00627 00628 DBGP ( "rtl8168c_2_hw_phy_config\n" ); 00629 00630 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00631 00632 mdio_patch(ioaddr, 0x16, 1 << 0); 00633 mdio_patch(ioaddr, 0x14, 1 << 5); 00634 mdio_patch(ioaddr, 0x0d, 1 << 5); 00635 mdio_write(ioaddr, 0x1f, 0x0000); 00636 }
| static void rtl8168c_3_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 638 of file r8169.c.
References ARRAY_SIZE, DBGP, mdio_patch(), mdio_write(), and rtl_phy_write().
Referenced by rtl8168c_4_hw_phy_config(), and rtl_hw_phy_config().
00639 { 00640 struct phy_reg phy_reg_init[] = { 00641 { 0x1f, 0x0001 }, 00642 { 0x12, 0x2300 }, 00643 { 0x1d, 0x3d98 }, 00644 { 0x1f, 0x0002 }, 00645 { 0x0c, 0x7eb8 }, 00646 { 0x06, 0x5461 }, 00647 { 0x1f, 0x0003 }, 00648 { 0x16, 0x0f0a }, 00649 { 0x1f, 0x0000 } 00650 }; 00651 00652 DBGP ( "rtl8168c_3_hw_phy_config\n" ); 00653 00654 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00655 00656 mdio_patch(ioaddr, 0x16, 1 << 0); 00657 mdio_patch(ioaddr, 0x14, 1 << 5); 00658 mdio_patch(ioaddr, 0x0d, 1 << 5); 00659 mdio_write(ioaddr, 0x1f, 0x0000); 00660 }
| static void rtl8168c_4_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 662 of file r8169.c.
References DBGP, and rtl8168c_3_hw_phy_config().
Referenced by rtl_hw_phy_config().
00663 { 00664 DBGP ( "rtl8168c_4_hw_phy_config\n" ); 00665 00666 rtl8168c_3_hw_phy_config(ioaddr); 00667 }
| static void rtl8168d_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 669 of file r8169.c.
References ARRAY_SIZE, DBGP, mdio_read(), mdio_write(), and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00670 { 00671 struct phy_reg phy_reg_init_0[] = { 00672 { 0x1f, 0x0001 }, 00673 { 0x09, 0x2770 }, 00674 { 0x08, 0x04d0 }, 00675 { 0x0b, 0xad15 }, 00676 { 0x0c, 0x5bf0 }, 00677 { 0x1c, 0xf101 }, 00678 { 0x1f, 0x0003 }, 00679 { 0x14, 0x94d7 }, 00680 { 0x12, 0xf4d6 }, 00681 { 0x09, 0xca0f }, 00682 { 0x1f, 0x0002 }, 00683 { 0x0b, 0x0b10 }, 00684 { 0x0c, 0xd1f7 }, 00685 { 0x1f, 0x0002 }, 00686 { 0x06, 0x5461 }, 00687 { 0x1f, 0x0002 }, 00688 { 0x05, 0x6662 }, 00689 { 0x1f, 0x0000 }, 00690 { 0x14, 0x0060 }, 00691 { 0x1f, 0x0000 }, 00692 { 0x0d, 0xf8a0 }, 00693 { 0x1f, 0x0005 }, 00694 { 0x05, 0xffc2 } 00695 }; 00696 00697 DBGP ( "rtl8168d_hw_phy_config\n" ); 00698 00699 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); 00700 00701 if (mdio_read(ioaddr, 0x06) == 0xc400) { 00702 struct phy_reg phy_reg_init_1[] = { 00703 { 0x1f, 0x0005 }, 00704 { 0x01, 0x0300 }, 00705 { 0x1f, 0x0000 }, 00706 { 0x11, 0x401c }, 00707 { 0x16, 0x4100 }, 00708 { 0x1f, 0x0005 }, 00709 { 0x07, 0x0010 }, 00710 { 0x05, 0x83dc }, 00711 { 0x06, 0x087d }, 00712 { 0x05, 0x8300 }, 00713 { 0x06, 0x0101 }, 00714 { 0x06, 0x05f8 }, 00715 { 0x06, 0xf9fa }, 00716 { 0x06, 0xfbef }, 00717 { 0x06, 0x79e2 }, 00718 { 0x06, 0x835f }, 00719 { 0x06, 0xe0f8 }, 00720 { 0x06, 0x9ae1 }, 00721 { 0x06, 0xf89b }, 00722 { 0x06, 0xef31 }, 00723 { 0x06, 0x3b65 }, 00724 { 0x06, 0xaa07 }, 00725 { 0x06, 0x81e4 }, 00726 { 0x06, 0xf89a }, 00727 { 0x06, 0xe5f8 }, 00728 { 0x06, 0x9baf }, 00729 { 0x06, 0x06ae }, 00730 { 0x05, 0x83dc }, 00731 { 0x06, 0x8300 }, 00732 }; 00733 00734 rtl_phy_write(ioaddr, phy_reg_init_1, 00735 ARRAY_SIZE(phy_reg_init_1)); 00736 } 00737 00738 mdio_write(ioaddr, 0x1f, 0x0000); 00739 }
| static void rtl8102e_hw_phy_config | ( | void * | ioaddr | ) | [static] |
Definition at line 741 of file r8169.c.
References ARRAY_SIZE, DBGP, mdio_patch(), mdio_write(), and rtl_phy_write().
Referenced by rtl_hw_phy_config().
00742 { 00743 struct phy_reg phy_reg_init[] = { 00744 { 0x1f, 0x0003 }, 00745 { 0x08, 0x441d }, 00746 { 0x01, 0x9100 }, 00747 { 0x1f, 0x0000 } 00748 }; 00749 00750 DBGP ( "rtl8102e_hw_phy_config\n" ); 00751 00752 mdio_write(ioaddr, 0x1f, 0x0000); 00753 mdio_patch(ioaddr, 0x11, 1 << 12); 00754 mdio_patch(ioaddr, 0x19, 1 << 13); 00755 00756 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); 00757 }
| static void rtl_hw_phy_config | ( | struct net_device * | dev | ) | [static] |
Definition at line 759 of file r8169.c.
References DBG, DBGP, ioaddr, rtl8169_private::mac_version, rtl8169_private::mmio_addr, netdev_priv(), rtl8102e_hw_phy_config(), rtl8168bb_hw_phy_config(), rtl8168bef_hw_phy_config(), rtl8168c_1_hw_phy_config(), rtl8168c_2_hw_phy_config(), rtl8168c_3_hw_phy_config(), rtl8168c_4_hw_phy_config(), rtl8168cp_1_hw_phy_config(), rtl8168cp_2_hw_phy_config(), rtl8168d_hw_phy_config(), rtl8169s_hw_phy_config(), rtl8169sb_hw_phy_config(), RTL_GIGA_MAC_VER_01, RTL_GIGA_MAC_VER_02, RTL_GIGA_MAC_VER_03, RTL_GIGA_MAC_VER_04, RTL_GIGA_MAC_VER_07, RTL_GIGA_MAC_VER_08, RTL_GIGA_MAC_VER_09, RTL_GIGA_MAC_VER_11, RTL_GIGA_MAC_VER_12, RTL_GIGA_MAC_VER_17, RTL_GIGA_MAC_VER_18, RTL_GIGA_MAC_VER_19, RTL_GIGA_MAC_VER_20, RTL_GIGA_MAC_VER_21, RTL_GIGA_MAC_VER_22, RTL_GIGA_MAC_VER_23, RTL_GIGA_MAC_VER_24, RTL_GIGA_MAC_VER_25, and tp.
Referenced by rtl8169_init_phy().
00760 { 00761 struct rtl8169_private *tp = netdev_priv(dev); 00762 void *ioaddr = tp->mmio_addr; 00763 00764 DBGP ( "rtl_hw_phy_config\n" ); 00765 00766 DBG ( "mac_version = 0x%02x\n", tp->mac_version ); 00767 00768 switch (tp->mac_version) { 00769 case RTL_GIGA_MAC_VER_01: 00770 break; 00771 case RTL_GIGA_MAC_VER_02: 00772 case RTL_GIGA_MAC_VER_03: 00773 rtl8169s_hw_phy_config(ioaddr); 00774 break; 00775 case RTL_GIGA_MAC_VER_04: 00776 rtl8169sb_hw_phy_config(ioaddr); 00777 break; 00778 case RTL_GIGA_MAC_VER_07: 00779 case RTL_GIGA_MAC_VER_08: 00780 case RTL_GIGA_MAC_VER_09: 00781 rtl8102e_hw_phy_config(ioaddr); 00782 break; 00783 case RTL_GIGA_MAC_VER_11: 00784 rtl8168bb_hw_phy_config(ioaddr); 00785 break; 00786 case RTL_GIGA_MAC_VER_12: 00787 rtl8168bef_hw_phy_config(ioaddr); 00788 break; 00789 case RTL_GIGA_MAC_VER_17: 00790 rtl8168bef_hw_phy_config(ioaddr); 00791 break; 00792 case RTL_GIGA_MAC_VER_18: 00793 rtl8168cp_1_hw_phy_config(ioaddr); 00794 break; 00795 case RTL_GIGA_MAC_VER_19: 00796 rtl8168c_1_hw_phy_config(ioaddr); 00797 break; 00798 case RTL_GIGA_MAC_VER_20: 00799 rtl8168c_2_hw_phy_config(ioaddr); 00800 break; 00801 case RTL_GIGA_MAC_VER_21: 00802 rtl8168c_3_hw_phy_config(ioaddr); 00803 break; 00804 case RTL_GIGA_MAC_VER_22: 00805 rtl8168c_4_hw_phy_config(ioaddr); 00806 break; 00807 case RTL_GIGA_MAC_VER_23: 00808 case RTL_GIGA_MAC_VER_24: 00809 rtl8168cp_2_hw_phy_config(ioaddr); 00810 break; 00811 case RTL_GIGA_MAC_VER_25: 00812 rtl8168d_hw_phy_config(ioaddr); 00813 break; 00814 00815 default: 00816 break; 00817 } 00818 }
| static void rtl8169_phy_reset | ( | struct net_device *dev | __unused, | |
| struct rtl8169_private * | tp | |||
| ) | [static] |
Definition at line 820 of file r8169.c.
References DBG, DBGP, ioaddr, mdelay(), rtl8169_private::mmio_addr, rtl8169_private::phy_reset_enable, and rtl8169_private::phy_reset_pending.
Referenced by rtl8169_init_phy().
00822 { 00823 void *ioaddr = tp->mmio_addr; 00824 unsigned int i; 00825 00826 DBGP ( "rtl8169_phy_reset\n" ); 00827 00828 tp->phy_reset_enable(ioaddr); 00829 for (i = 0; i < 100; i++) { 00830 if (!tp->phy_reset_pending(ioaddr)) 00831 return; 00832 mdelay ( 1 ); 00833 } 00834 DBG ( "PHY reset failed.\n" ); 00835 }
| static void rtl8169_init_phy | ( | struct net_device * | dev, | |
| struct rtl8169_private * | tp | |||
| ) | [static] |
Definition at line 837 of file r8169.c.
References AUTONEG_ENABLE, DBG, DBGP, DUPLEX_FULL, ioaddr, rtl8169_private::mac_version, mdio_write(), rtl8169_private::mmio_addr, PCI_CACHE_LINE_SIZE, rtl8169_private::pci_dev, PCI_LATENCY_TIMER, pci_write_config_byte(), PHYstatus, rtl8169_phy_reset(), rtl8169_set_speed(), RTL_GIGA_MAC_VER_02, RTL_GIGA_MAC_VER_06, rtl_hw_phy_config(), RTL_R8, RTL_W8, SPEED_1000, and TBI_Enable.
Referenced by rtl8169_probe().
00838 { 00839 void *ioaddr = tp->mmio_addr; 00840 00841 DBGP ( "rtl8169_init_phy\n" ); 00842 00843 rtl_hw_phy_config(dev); 00844 00845 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 00846 DBG ( "Set MAC Reg C+CR Offset 0x82h = 0x01h\n" ); 00847 RTL_W8(0x82, 0x01); 00848 } 00849 00850 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 00851 00852 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 00853 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 00854 00855 if (tp->mac_version == RTL_GIGA_MAC_VER_02) { 00856 DBG ( "Set MAC Reg C+CR Offset 0x82h = 0x01h\n" ); 00857 RTL_W8(0x82, 0x01); 00858 DBG ( "Set PHY Reg 0x0bh = 0x00h\n" ); 00859 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 00860 } 00861 00862 rtl8169_phy_reset(dev, tp); 00863 00864 /* 00865 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet 00866 * only 8101. Don't panic. 00867 */ 00868 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); 00869 00870 if ((RTL_R8(PHYstatus) & TBI_Enable)) 00871 DBG ( "TBI auto-negotiating\n" ); 00872 }
| static void rtl8169_hw_reset | ( | void * | ioaddr | ) | [static] |
Definition at line 910 of file r8169.c.
References ChipCmd, CmdReset, DBGP, rtl8169_irq_mask_and_ack(), RTL_R8, and RTL_W8.
Referenced by rtl8169_close(), rtl8169_open(), and rtl8169_remove().
00911 { 00912 DBGP ( "rtl8169_hw_reset\n" ); 00913 00914 /* Disable interrupts */ 00915 rtl8169_irq_mask_and_ack(ioaddr); 00916 00917 /* Reset the chipset */ 00918 RTL_W8(ChipCmd, CmdReset); 00919 00920 /* PCI commit */ 00921 RTL_R8(ChipCmd); 00922 }
| static void rtl_set_rx_tx_config_registers | ( | struct rtl8169_private * | tp | ) | [static] |
Definition at line 924 of file r8169.c.
References cfg, rtl8169_private::chipset, DBGP, InterFrameGap, ioaddr, rtl8169_private::mmio_addr, rtl8169_rx_config, rtl_chip_info, RTL_R32, RTL_W32, RxConfig, TX_DMA_BURST, TxConfig, TxDMAShift, TxInterFrameGapShift, and u32.
Referenced by rtl_hw_start_8101(), and rtl_hw_start_8169().
00925 { 00926 void *ioaddr = tp->mmio_addr; 00927 u32 cfg = rtl8169_rx_config; 00928 00929 DBGP ( "rtl_set_rx_tx_config_registers\n" ); 00930 00931 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); 00932 RTL_W32(RxConfig, cfg); 00933 00934 /* Set DMA burst size and Interframe Gap Time */ 00935 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 00936 (InterFrameGap << TxInterFrameGapShift)); 00937 }
| static void rtl_soft_reset | ( | struct net_device * | dev | ) | [static] |
Definition at line 939 of file r8169.c.
References ChipCmd, CmdReset, DBG, DBGP, ioaddr, mdelay(), rtl8169_private::mmio_addr, netdev_priv(), RTL_R8, RTL_W8, and tp.
Referenced by rtl8169_probe(), and rtl_hw_start().
00940 { 00941 struct rtl8169_private *tp = netdev_priv(dev); 00942 void *ioaddr = tp->mmio_addr; 00943 unsigned int i; 00944 00945 DBGP ( "rtl_hw_soft_reset\n" ); 00946 00947 /* Soft reset the chip. */ 00948 RTL_W8(ChipCmd, CmdReset); 00949 00950 /* Check that the chip has finished the reset. */ 00951 for (i = 0; i < 100; i++) { 00952 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 00953 break; 00954 mdelay ( 1 ); 00955 } 00956 00957 if ( i == 100 ) { 00958 DBG ( "Reset Failed! (> 100 iterations)\n" ); 00959 } 00960 }
| static void rtl_hw_start | ( | struct net_device * | dev | ) | [static] |
Definition at line 962 of file r8169.c.
References DBGP, rtl8169_private::hw_start, netdev_priv(), rtl_soft_reset(), and tp.
Referenced by rtl8169_open().
00963 { 00964 struct rtl8169_private *tp = netdev_priv ( dev ); 00965 00966 DBGP ( "rtl_hw_start\n" ); 00967 00968 /* Soft reset NIC */ 00969 rtl_soft_reset ( dev ); 00970 00971 tp->hw_start ( dev ); 00972 }
| static void rtl_set_rx_tx_desc_registers | ( | struct rtl8169_private * | tp, | |
| void * | ioaddr | |||
| ) | [static] |
Definition at line 974 of file r8169.c.
References DBGP, RTL_W32, rtl8169_private::rx_base, RxDescAddrHigh, RxDescAddrLow, rtl8169_private::tx_base, TxDescStartAddrHigh, TxDescStartAddrLow, and virt_to_bus().
Referenced by rtl_hw_start_8101(), rtl_hw_start_8168(), and rtl_hw_start_8169().
00976 { 00977 DBGP ( "rtl_set_rx_tx_desc_registers\n" ); 00978 00979 /* 00980 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 00981 * register to be written before TxDescAddrLow to work. 00982 * Switching from MMIO to I/O access fixes the issue as well. 00983 */ 00984 RTL_W32 ( TxDescStartAddrHigh, 0 ); 00985 RTL_W32 ( TxDescStartAddrLow, virt_to_bus ( tp->tx_base ) ); 00986 RTL_W32 ( RxDescAddrHigh, 0 ); 00987 RTL_W32 ( RxDescAddrLow, virt_to_bus ( tp->rx_base ) ); 00988 }
| static u16 rtl_rw_cpluscmd | ( | void * | ioaddr | ) | [static] |
Definition at line 990 of file r8169.c.
References CPlusCmd, DBGP, RTL_R16, RTL_W16, and u16.
Referenced by rtl_hw_start_8101(), and rtl_hw_start_8169().
00991 { 00992 u16 cmd; 00993 00994 DBGP ( "rtl_rw_cpluscmd\n" ); 00995 00996 cmd = RTL_R16(CPlusCmd); 00997 RTL_W16(CPlusCmd, cmd); 00998 return cmd; 00999 }
| static void rtl_set_rx_max_size | ( | void * | ioaddr | ) | [static] |
Definition at line 1001 of file r8169.c.
References DBGP, RTL_W16, RX_BUF_SIZE, and RxMaxSize.
Referenced by rtl_hw_start_8101(), rtl_hw_start_8168(), and rtl_hw_start_8169().
01002 { 01003 DBGP ( "rtl_set_rx_max_size\n" ); 01004 01005 RTL_W16 ( RxMaxSize, RX_BUF_SIZE ); 01006 }
| static void rtl8169_set_magic_reg | ( | void * | ioaddr, | |
| unsigned | mac_version | |||
| ) | [static] |
Definition at line 1008 of file r8169.c.
References ARRAY_SIZE, Config2, DBGP, PCI_Clock_33MHz, PCI_Clock_66MHz, RTL_GIGA_MAC_VER_05, RTL_GIGA_MAC_VER_06, RTL_R8, RTL_W32, and u32.
Referenced by rtl_hw_start_8169().
01009 { 01010 struct { 01011 u32 mac_version; 01012 u32 clk; 01013 u32 val; 01014 } cfg2_info [] = { 01015 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd 01016 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, 01017 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe 01018 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } 01019 }, *p = cfg2_info; 01020 unsigned int i; 01021 u32 clk; 01022 01023 DBGP ( "rtl8169_set_magic_reg\n" ); 01024 01025 clk = RTL_R8(Config2) & PCI_Clock_66MHz; 01026 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { 01027 if ((p->mac_version == mac_version) && (p->clk == clk)) { 01028 RTL_W32(0x7c, p->val); 01029 break; 01030 } 01031 } 01032 }
| static void rtl_set_rx_mode | ( | struct net_device * | netdev | ) | [static] |
Definition at line 1034 of file r8169.c.
References AcceptBroadcast, AcceptMulticast, AcceptMyPhys, rtl8169_private::chipset, DBGP, ioaddr, MAR0, rtl8169_private::mmio_addr, netdev_priv(), rtl8169_rx_config, rtl_chip_info, RTL_R32, RTL_W32, RxConfig, tp, and u32.
Referenced by rtl_hw_start_8101(), rtl_hw_start_8168(), and rtl_hw_start_8169().
01035 { 01036 struct rtl8169_private *tp = netdev_priv ( netdev ); 01037 void *ioaddr = tp->mmio_addr; 01038 u32 tmp; 01039 01040 DBGP ( "rtl_set_rx_mode\n" ); 01041 01042 /* Accept all Multicast Packets */ 01043 01044 RTL_W32 ( MAR0 + 0, 0xffffffff ); 01045 RTL_W32 ( MAR0 + 4, 0xffffffff ); 01046 01047 tmp = rtl8169_rx_config | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | 01048 ( RTL_R32 ( RxConfig ) & rtl_chip_info[tp->chipset].RxConfigMask ); 01049 01050 RTL_W32 ( RxConfig, tmp ); 01051 }
| static void rtl_hw_start_8169 | ( | struct net_device * | dev | ) | [static] |
Definition at line 1053 of file r8169.c.
References Cfg9346, Cfg9346_Lock, Cfg9346_Unlock, ChipCmd, CmdRxEnb, CmdTxEnb, rtl8169_private::cp_cmd, CPlusCmd, DBG, DBGP, EarlyTxThld, EarlyTxThres, IntrMask, IntrMitigate, ioaddr, rtl8169_private::mac_version, rtl8169_private::mmio_addr, MultiIntr, netdev_priv(), PCI_CACHE_LINE_SIZE, rtl8169_private::pci_dev, pci_write_config_byte(), PCIMulRW, rtl8169_set_magic_reg(), RTL_GIGA_MAC_VER_01, RTL_GIGA_MAC_VER_02, RTL_GIGA_MAC_VER_03, RTL_GIGA_MAC_VER_04, RTL_GIGA_MAC_VER_05, RTL_R16, RTL_R8, rtl_rw_cpluscmd(), rtl_set_rx_max_size(), rtl_set_rx_mode(), rtl_set_rx_tx_config_registers(), rtl_set_rx_tx_desc_registers(), RTL_W16, RTL_W32, RTL_W8, RxMissed, and tp.
01054 { 01055 struct rtl8169_private *tp = netdev_priv(dev); 01056 void *ioaddr = tp->mmio_addr; 01057 struct pci_device *pdev = tp->pci_dev; 01058 01059 DBGP ( "rtl_hw_start_8169\n" ); 01060 01061 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { 01062 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); 01063 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); 01064 } 01065 01066 RTL_W8(Cfg9346, Cfg9346_Unlock); 01067 01068 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || 01069 (tp->mac_version == RTL_GIGA_MAC_VER_02) || 01070 (tp->mac_version == RTL_GIGA_MAC_VER_03) || 01071 (tp->mac_version == RTL_GIGA_MAC_VER_04)) 01072 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 01073 01074 RTL_W8(EarlyTxThres, EarlyTxThld); 01075 01076 rtl_set_rx_max_size(ioaddr); 01077 01078 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || 01079 (tp->mac_version == RTL_GIGA_MAC_VER_02) || 01080 (tp->mac_version == RTL_GIGA_MAC_VER_03) || 01081 (tp->mac_version == RTL_GIGA_MAC_VER_04)) 01082 rtl_set_rx_tx_config_registers(tp); 01083 01084 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; 01085 01086 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || 01087 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { 01088 DBG ( "Set MAC Reg C+CR Offset 0xE0. " 01089 "Bit-3 and bit-14 MUST be 1\n" ); 01090 tp->cp_cmd |= (1 << 14); 01091 } 01092 01093 RTL_W16(CPlusCmd, tp->cp_cmd); 01094 01095 rtl8169_set_magic_reg(ioaddr, tp->mac_version); 01096 01097 /* 01098 * Undocumented corner. Supposedly: 01099 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets 01100 */ 01101 RTL_W16(IntrMitigate, 0x0000); 01102 01103 rtl_set_rx_tx_desc_registers(tp, ioaddr); 01104 01105 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && 01106 (tp->mac_version != RTL_GIGA_MAC_VER_02) && 01107 (tp->mac_version != RTL_GIGA_MAC_VER_03) && 01108 (tp->mac_version != RTL_GIGA_MAC_VER_04)) { 01109 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 01110 rtl_set_rx_tx_config_registers(tp); 01111 } 01112 01113 RTL_W8(Cfg9346, Cfg9346_Lock); 01114 01115 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 01116 RTL_R8(IntrMask); 01117 01118 RTL_W32(RxMissed, 0); 01119 01120 rtl_set_rx_mode(dev); 01121 01122 /* no early-rx interrupts */ 01123 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 01124 01125 // RTL_W16(IntrMask, tp->intr_event); 01126 }
| static void rtl_tx_performance_tweak | ( | struct pci_device * | pdev, | |
| u16 | force | |||
| ) | [static] |
Definition at line 1128 of file r8169.c.
References DBGP, net_device::dev, netdev_priv(), PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_READRQ, pci_get_drvdata(), pci_read_config_word(), pci_write_config_word(), rtl8169_private::pcie_cap, tp, and u16.
Referenced by __rtl_hw_start_8168cp(), rtl_hw_start_8102e_1(), rtl_hw_start_8102e_2(), rtl_hw_start_8168bb(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), and rtl_hw_start_8168d().
01129 { 01130 struct net_device *dev = pci_get_drvdata(pdev); 01131 struct rtl8169_private *tp = netdev_priv(dev); 01132 int cap = tp->pcie_cap; 01133 01134 DBGP ( "rtl_tx_performance_tweak\n" ); 01135 01136 if (cap) { 01137 u16 ctl; 01138 01139 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); 01140 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; 01141 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); 01142 } 01143 }
| static void rtl_csi_access_enable | ( | void * | ioaddr | ) | [static] |
Definition at line 1145 of file r8169.c.
References DBGP, rtl_csi_read(), rtl_csi_write(), and u32.
Referenced by rtl_hw_start_8102e_1(), rtl_hw_start_8102e_2(), rtl_hw_start_8168c_1(), rtl_hw_start_8168c_2(), rtl_hw_start_8168c_4(), rtl_hw_start_8168cp_1(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), and rtl_hw_start_8168d().
01146 { 01147 u32 csi; 01148 01149 DBGP ( "rtl_csi_access_enable\n" ); 01150 01151 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; 01152 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); 01153 }
| static void rtl_ephy_init | ( | void * | ioaddr, | |
| struct ephy_info * | e, | |||
| int | len | |||
| ) | [static] |
Definition at line 1161 of file r8169.c.
References ephy_info::bits, DBGP, ephy_info::mask, ephy_info::offset, rtl_ephy_read(), rtl_ephy_write(), and u16.
Referenced by rtl_hw_start_8102e_1(), rtl_hw_start_8168c_1(), rtl_hw_start_8168c_2(), and rtl_hw_start_8168cp_1().
01162 { 01163 u16 w; 01164 01165 DBGP ( "rtl_ephy_init\n" ); 01166 01167 while (len-- > 0) { 01168 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; 01169 rtl_ephy_write(ioaddr, e->offset, w); 01170 e++; 01171 } 01172 }
| static void rtl_disable_clock_request | ( | struct pci_device * | pdev | ) | [static] |
Definition at line 1174 of file r8169.c.
References DBGP, net_device::dev, netdev_priv(), PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_CLKREQ_EN, pci_get_drvdata(), pci_read_config_word(), pci_write_config_word(), rtl8169_private::pcie_cap, tp, and u16.
Referenced by __rtl_hw_start_8168cp(), and rtl_hw_start_8168d().
01175 { 01176 struct net_device *dev = pci_get_drvdata(pdev); 01177 struct rtl8169_private *tp = netdev_priv(dev); 01178 int cap = tp->pcie_cap; 01179 01180 DBGP ( "rtl_disable_clock_request\n" ); 01181 01182 if (cap) { 01183 u16 ctl; 01184 01185 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); 01186 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; 01187 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); 01188 } 01189 }
| static void rtl_hw_start_8168bb | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1202 of file r8169.c.
References Beacon_en, Config3, CPlusCmd, DBGP, MAX_READ_REQUEST_SHIFT, PCI_EXP_DEVCTL_NOSNOOP_EN, R8168_CPCMD_QUIRK_MASK, RTL_R16, RTL_R8, rtl_tx_performance_tweak(), RTL_W16, and RTL_W8.
Referenced by rtl_hw_start_8168(), and rtl_hw_start_8168bef().
01203 { 01204 DBGP ( "rtl_hw_start_8168bb\n" ); 01205 01206 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 01207 01208 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 01209 01210 rtl_tx_performance_tweak(pdev, 01211 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); 01212 }
| static void rtl_hw_start_8168bef | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1214 of file r8169.c.
References Config4, DBGP, EarlyTxThld, EarlyTxThres, rtl_hw_start_8168bb(), RTL_R8, and RTL_W8.
Referenced by rtl_hw_start_8168().
01215 { 01216 DBGP ( "rtl_hw_start_8168bef\n" ); 01217 01218 rtl_hw_start_8168bb(ioaddr, pdev); 01219 01220 RTL_W8(EarlyTxThres, EarlyTxThld); 01221 01222 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); 01223 }
| static void __rtl_hw_start_8168cp | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1225 of file r8169.c.
References Beacon_en, Config1, Config3, CPlusCmd, DBGP, MAX_READ_REQUEST_SHIFT, R8168_CPCMD_QUIRK_MASK, rtl_disable_clock_request(), RTL_R16, RTL_R8, rtl_tx_performance_tweak(), RTL_W16, RTL_W8, and Speed_down.
Referenced by rtl_hw_start_8168c_1(), rtl_hw_start_8168c_2(), rtl_hw_start_8168c_4(), and rtl_hw_start_8168cp_1().
01226 { 01227 DBGP ( "__rtl_hw_start_8168cp\n" ); 01228 01229 RTL_W8(Config1, RTL_R8(Config1) | Speed_down); 01230 01231 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 01232 01233 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 01234 01235 rtl_disable_clock_request(pdev); 01236 01237 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 01238 }
| static void rtl_hw_start_8168cp_1 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1240 of file r8169.c.
References __rtl_hw_start_8168cp(), ARRAY_SIZE, DBGP, rtl_csi_access_enable(), and rtl_ephy_init().
Referenced by rtl_hw_start_8168().
01241 { 01242 static struct ephy_info e_info_8168cp[] = { 01243 { 0x01, 0, 0x0001 }, 01244 { 0x02, 0x0800, 0x1000 }, 01245 { 0x03, 0, 0x0042 }, 01246 { 0x06, 0x0080, 0x0000 }, 01247 { 0x07, 0, 0x2000 } 01248 }; 01249 01250 DBGP ( "rtl_hw_start_8168cp_1\n" ); 01251 01252 rtl_csi_access_enable(ioaddr); 01253 01254 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); 01255 01256 __rtl_hw_start_8168cp(ioaddr, pdev); 01257 }
| static void rtl_hw_start_8168cp_2 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1259 of file r8169.c.
References Beacon_en, Config3, CPlusCmd, DBGP, MAX_READ_REQUEST_SHIFT, R8168_CPCMD_QUIRK_MASK, rtl_csi_access_enable(), RTL_R16, RTL_R8, rtl_tx_performance_tweak(), RTL_W16, and RTL_W8.
Referenced by rtl_hw_start_8168().
01260 { 01261 DBGP ( "rtl_hw_start_8168cp_2\n" ); 01262 01263 rtl_csi_access_enable(ioaddr); 01264 01265 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 01266 01267 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 01268 01269 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 01270 }
| static void rtl_hw_start_8168cp_3 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1272 of file r8169.c.
References Beacon_en, Config3, CPlusCmd, DBG_REG, DBGP, EarlyTxThld, EarlyTxThres, MAX_READ_REQUEST_SHIFT, R8168_CPCMD_QUIRK_MASK, rtl_csi_access_enable(), RTL_R16, RTL_R8, rtl_tx_performance_tweak(), RTL_W16, and RTL_W8.
Referenced by rtl_hw_start_8168().
01273 { 01274 DBGP ( "rtl_hw_start_8168cp_3\n" ); 01275 01276 rtl_csi_access_enable(ioaddr); 01277 01278 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 01279 01280 /* Magic. */ 01281 RTL_W8(DBG_REG, 0x20); 01282 01283 RTL_W8(EarlyTxThres, EarlyTxThld); 01284 01285 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 01286 01287 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 01288 }
| static void rtl_hw_start_8168c_1 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1290 of file r8169.c.
References __rtl_hw_start_8168cp(), ARRAY_SIZE, DBG_REG, DBGP, FIX_NAK_1, FIX_NAK_2, rtl_csi_access_enable(), rtl_ephy_init(), and RTL_W8.
Referenced by rtl_hw_start_8168().
01291 { 01292 static struct ephy_info e_info_8168c_1[] = { 01293 { 0x02, 0x0800, 0x1000 }, 01294 { 0x03, 0, 0x0002 }, 01295 { 0x06, 0x0080, 0x0000 } 01296 }; 01297 01298 DBGP ( "rtl_hw_start_8168c_1\n" ); 01299 01300 rtl_csi_access_enable(ioaddr); 01301 01302 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 01303 01304 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); 01305 01306 __rtl_hw_start_8168cp(ioaddr, pdev); 01307 }
| static void rtl_hw_start_8168c_2 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1309 of file r8169.c.
References __rtl_hw_start_8168cp(), ARRAY_SIZE, DBGP, rtl_csi_access_enable(), and rtl_ephy_init().
Referenced by rtl_hw_start_8168(), and rtl_hw_start_8168c_3().
01310 { 01311 static struct ephy_info e_info_8168c_2[] = { 01312 { 0x01, 0, 0x0001 }, 01313 { 0x03, 0x0400, 0x0220 } 01314 }; 01315 01316 DBGP ( "rtl_hw_start_8168c_2\n" ); 01317 01318 rtl_csi_access_enable(ioaddr); 01319 01320 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); 01321 01322 __rtl_hw_start_8168cp(ioaddr, pdev); 01323 }
| static void rtl_hw_start_8168c_3 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1325 of file r8169.c.
References DBGP, and rtl_hw_start_8168c_2().
Referenced by rtl_hw_start_8168().
01326 { 01327 DBGP ( "rtl_hw_start_8168c_3\n" ); 01328 01329 rtl_hw_start_8168c_2(ioaddr, pdev); 01330 }
| static void rtl_hw_start_8168c_4 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1332 of file r8169.c.
References __rtl_hw_start_8168cp(), DBGP, and rtl_csi_access_enable().
Referenced by rtl_hw_start_8168().
01333 { 01334 DBGP ( "rtl_hw_start_8168c_4\n" ); 01335 01336 rtl_csi_access_enable(ioaddr); 01337 01338 __rtl_hw_start_8168cp(ioaddr, pdev); 01339 }
| static void rtl_hw_start_8168d | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1341 of file r8169.c.
References CPlusCmd, DBGP, EarlyTxThld, EarlyTxThres, MAX_READ_REQUEST_SHIFT, R8168_CPCMD_QUIRK_MASK, rtl_csi_access_enable(), rtl_disable_clock_request(), RTL_R16, rtl_tx_performance_tweak(), RTL_W16, and RTL_W8.
Referenced by rtl_hw_start_8168().
01342 { 01343 DBGP ( "rtl_hw_start_8168d\n" ); 01344 01345 rtl_csi_access_enable(ioaddr); 01346 01347 rtl_disable_clock_request(pdev); 01348 01349 RTL_W8(EarlyTxThres, EarlyTxThld); 01350 01351 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 01352 01353 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); 01354 }
| static void rtl_hw_start_8168 | ( | struct net_device * | dev | ) | [static] |
Definition at line 1356 of file r8169.c.
References Cfg9346, Cfg9346_Lock, Cfg9346_Unlock, ChipCmd, CmdRxEnb, CmdTxEnb, rtl8169_private::cp_cmd, CPlusCmd, DBG, DBGP, EarlyTxThld, EarlyTxThres, InterFrameGap, rtl8169_private::intr_event, IntrMask, IntrMitigate, INTT_1, ioaddr, rtl8169_private::mac_version, rtl8169_private::mmio_addr, MultiIntr, netdev_priv(), rtl8169_private::pci_dev, PCSTimeout, PktCntrDisable, RTL_GIGA_MAC_VER_11, RTL_GIGA_MAC_VER_12, RTL_GIGA_MAC_VER_17, RTL_GIGA_MAC_VER_18, RTL_GIGA_MAC_VER_19, RTL_GIGA_MAC_VER_20, RTL_GIGA_MAC_VER_21, RTL_GIGA_MAC_VER_22, RTL_GIGA_MAC_VER_23, RTL_GIGA_MAC_VER_24, RTL_GIGA_MAC_VER_25, rtl_hw_start_8168bb(), rtl_hw_start_8168bef(), rtl_hw_start_8168c_1(), rtl_hw_start_8168c_2(), rtl_hw_start_8168c_3(), rtl_hw_start_8168c_4(), rtl_hw_start_8168cp_1(), rtl_hw_start_8168cp_2(), rtl_hw_start_8168cp_3(), rtl_hw_start_8168d(), RTL_R16, RTL_R8, rtl_set_rx_max_size(), rtl_set_rx_mode(), rtl_set_rx_tx_desc_registers(), RTL_W16, RTL_W32, RTL_W8, RxFIFOOver, RxOverflow, tp, TX_DMA_BURST, TxConfig, TxDMAShift, and TxInterFrameGapShift.
01357 { 01358 struct rtl8169_private *tp = netdev_priv(dev); 01359 void *ioaddr = tp->mmio_addr; 01360 struct pci_device *pdev = tp->pci_dev; 01361 01362 DBGP ( "rtl_hw_start_8168\n" ); 01363 01364 RTL_W8(Cfg9346, Cfg9346_Unlock); 01365 01366 RTL_W8(EarlyTxThres, EarlyTxThld); 01367 01368 rtl_set_rx_max_size(ioaddr); 01369 01370 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; 01371 01372 RTL_W16(CPlusCmd, tp->cp_cmd); 01373 01374 RTL_W16(IntrMitigate, 0x5151); 01375 01376 /* Work around for RxFIFO overflow. */ 01377 if (tp->mac_version == RTL_GIGA_MAC_VER_11) { 01378 tp->intr_event |= RxFIFOOver | PCSTimeout; 01379 tp->intr_event &= ~RxOverflow; 01380 } 01381 01382 rtl_set_rx_tx_desc_registers(tp, ioaddr); 01383 01384 rtl_set_rx_mode(dev); 01385 01386 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 01387 (InterFrameGap << TxInterFrameGapShift)); 01388 01389 RTL_R8(IntrMask); 01390 01391 switch (tp->mac_version) { 01392 case RTL_GIGA_MAC_VER_11: 01393 rtl_hw_start_8168bb(ioaddr, pdev); 01394 break; 01395 01396 case RTL_GIGA_MAC_VER_12: 01397 case RTL_GIGA_MAC_VER_17: 01398 rtl_hw_start_8168bef(ioaddr, pdev); 01399 break; 01400 01401 case RTL_GIGA_MAC_VER_18: 01402 rtl_hw_start_8168cp_1(ioaddr, pdev); 01403 break; 01404 01405 case RTL_GIGA_MAC_VER_19: 01406 rtl_hw_start_8168c_1(ioaddr, pdev); 01407 break; 01408 01409 case RTL_GIGA_MAC_VER_20: 01410 rtl_hw_start_8168c_2(ioaddr, pdev); 01411 break; 01412 01413 case RTL_GIGA_MAC_VER_21: 01414 rtl_hw_start_8168c_3(ioaddr, pdev); 01415 break; 01416 01417 case RTL_GIGA_MAC_VER_22: 01418 rtl_hw_start_8168c_4(ioaddr, pdev); 01419 break; 01420 01421 case RTL_GIGA_MAC_VER_23: 01422 rtl_hw_start_8168cp_2(ioaddr, pdev); 01423 break; 01424 01425 case RTL_GIGA_MAC_VER_24: 01426 rtl_hw_start_8168cp_3(ioaddr, pdev); 01427 break; 01428 01429 case RTL_GIGA_MAC_VER_25: 01430 rtl_hw_start_8168d(ioaddr, pdev); 01431 break; 01432 01433 default: 01434 DBG ( "Unknown chipset (mac_version = %d).\n", 01435 tp->mac_version ); 01436 break; 01437 } 01438 01439 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 01440 01441 RTL_W8(Cfg9346, Cfg9346_Lock); 01442 01443 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 01444 01445 // RTL_W16(IntrMask, tp->intr_event); 01446 }
| static void rtl_hw_start_8102e_1 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1460 of file r8169.c.
References ARRAY_SIZE, Beacon_en, Config1, Config3, CPlusCmd, DBG_REG, DBGP, FIX_NAK_1, IOMAP, LEDS0, LEDS1, MAX_READ_REQUEST_SHIFT, MEMMAP, PMEnable, R810X_CPCMD_QUIRK_MASK, rtl_csi_access_enable(), rtl_ephy_init(), RTL_R16, RTL_R8, rtl_tx_performance_tweak(), RTL_W16, RTL_W8, Speed_down, u8, and VPD.
Referenced by rtl_hw_start_8101().
01461 { 01462 static struct ephy_info e_info_8102e_1[] = { 01463 { 0x01, 0, 0x6e65 }, 01464 { 0x02, 0, 0x091f }, 01465 { 0x03, 0, 0xc2f9 }, 01466 { 0x06, 0, 0xafb5 }, 01467 { 0x07, 0, 0x0e00 }, 01468 { 0x19, 0, 0xec80 }, 01469 { 0x01, 0, 0x2e65 }, 01470 { 0x01, 0, 0x6e65 } 01471 }; 01472 u8 cfg1; 01473 01474 DBGP ( "rtl_hw_start_8102e_1\n" ); 01475 01476 rtl_csi_access_enable(ioaddr); 01477 01478 RTL_W8(DBG_REG, FIX_NAK_1); 01479 01480 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 01481 01482 RTL_W8(Config1, 01483 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 01484 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 01485 01486 cfg1 = RTL_R8(Config1); 01487 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 01488 RTL_W8(Config1, cfg1 & ~LEDS0); 01489 01490 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); 01491 01492 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); 01493 }
| static void rtl_hw_start_8102e_2 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1495 of file r8169.c.
References Beacon_en, Config1, Config3, CPlusCmd, DBGP, IOMAP, MAX_READ_REQUEST_SHIFT, MEMMAP, PMEnable, R810X_CPCMD_QUIRK_MASK, rtl_csi_access_enable(), RTL_R16, RTL_R8, rtl_tx_performance_tweak(), RTL_W16, RTL_W8, and VPD.
Referenced by rtl_hw_start_8101(), and rtl_hw_start_8102e_3().
01496 { 01497 DBGP ( "rtl_hw_start_8102e_2\n" ); 01498 01499 rtl_csi_access_enable(ioaddr); 01500 01501 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); 01502 01503 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); 01504 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 01505 01506 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); 01507 }
| static void rtl_hw_start_8102e_3 | ( | void * | ioaddr, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1509 of file r8169.c.
References DBGP, rtl_ephy_write(), and rtl_hw_start_8102e_2().
Referenced by rtl_hw_start_8101().
01510 { 01511 DBGP ( "rtl_hw_start_8102e_3\n" ); 01512 01513 rtl_hw_start_8102e_2(ioaddr, pdev); 01514 01515 rtl_ephy_write(ioaddr, 0x03, 0xc2f9); 01516 }
| static void rtl_hw_start_8101 | ( | struct net_device * | dev | ) | [static] |
Definition at line 1518 of file r8169.c.
References Cfg9346, Cfg9346_Lock, Cfg9346_Unlock, ChipCmd, CmdRxEnb, CmdTxEnb, rtl8169_private::cp_cmd, CPlusCmd, DBGP, EarlyTxThld, EarlyTxThres, IntrMask, IntrMitigate, ioaddr, rtl8169_private::mac_version, rtl8169_private::mmio_addr, MultiIntr, netdev_priv(), rtl8169_private::pci_dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_NOSNOOP_EN, pci_write_config_word(), rtl8169_private::pcie_cap, PCIMulRW, RTL_GIGA_MAC_VER_07, RTL_GIGA_MAC_VER_08, RTL_GIGA_MAC_VER_09, RTL_GIGA_MAC_VER_13, RTL_GIGA_MAC_VER_16, rtl_hw_start_8102e_1(), rtl_hw_start_8102e_2(), rtl_hw_start_8102e_3(), RTL_R16, RTL_R8, rtl_rw_cpluscmd(), rtl_set_rx_max_size(), rtl_set_rx_mode(), rtl_set_rx_tx_config_registers(), rtl_set_rx_tx_desc_registers(), RTL_W16, RTL_W8, and tp.
01519 { 01520 struct rtl8169_private *tp = netdev_priv(dev); 01521 void *ioaddr = tp->mmio_addr; 01522 struct pci_device *pdev = tp->pci_dev; 01523 01524 DBGP ( "rtl_hw_start_8101\n" ); 01525 01526 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || 01527 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { 01528 int cap = tp->pcie_cap; 01529 01530 if (cap) { 01531 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, 01532 PCI_EXP_DEVCTL_NOSNOOP_EN); 01533 } 01534 } 01535 01536 switch (tp->mac_version) { 01537 case RTL_GIGA_MAC_VER_07: 01538 rtl_hw_start_8102e_1(ioaddr, pdev); 01539 break; 01540 01541 case RTL_GIGA_MAC_VER_08: 01542 rtl_hw_start_8102e_3(ioaddr, pdev); 01543 break; 01544 01545 case RTL_GIGA_MAC_VER_09: 01546 rtl_hw_start_8102e_2(ioaddr, pdev); 01547 break; 01548 } 01549 01550 RTL_W8(Cfg9346, Cfg9346_Unlock); 01551 01552 RTL_W8(EarlyTxThres, EarlyTxThld); 01553 01554 rtl_set_rx_max_size(ioaddr); 01555 01556 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; 01557 01558 RTL_W16(CPlusCmd, tp->cp_cmd); 01559 01560 RTL_W16(IntrMitigate, 0x0000); 01561 01562 rtl_set_rx_tx_desc_registers(tp, ioaddr); 01563 01564 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 01565 rtl_set_rx_tx_config_registers(tp); 01566 01567 RTL_W8(Cfg9346, Cfg9346_Lock); 01568 01569 RTL_R8(IntrMask); 01570 01571 rtl_set_rx_mode(dev); 01572 01573 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 01574 01575 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); 01576 01577 // RTL_W16(IntrMask, tp->intr_event); 01578 }
| static int rtl8169_setup_tx_resources | ( | struct rtl8169_private * | tp | ) | [static] |
setup_tx_resources - allocate tx resources (descriptors)
| tp | Driver private storage |
| rc | Returns 0 on success, negative on failure |
Definition at line 1590 of file r8169.c.
References DBG, DBGP, ENOMEM, malloc_dma(), memset(), R8169_TX_RING_BYTES, rtl8169_private::tx_base, rtl8169_private::tx_curr, rtl8169_private::tx_fill_ctr, TX_RING_ALIGN, rtl8169_private::tx_tail, and virt_to_bus().
Referenced by rtl8169_open().
01591 { 01592 DBGP ( "rtl8169_setup_tx_resources\n" ); 01593 01594 tp->tx_base = malloc_dma ( R8169_TX_RING_BYTES, TX_RING_ALIGN ); 01595 01596 if ( ! tp->tx_base ) { 01597 return -ENOMEM; 01598 } 01599 01600 memset ( tp->tx_base, 0, R8169_TX_RING_BYTES ); 01601 01602 DBG ( "tp->tx_base = %#08lx\n", virt_to_bus ( tp->tx_base ) ); 01603 01604 tp->tx_fill_ctr = 0; 01605 tp->tx_curr = 0; 01606 tp->tx_tail = 0; 01607 01608 return 0; 01609 }
| static void rtl8169_process_tx_packets | ( | struct net_device * | netdev | ) | [static] |
Definition at line 1612 of file r8169.c.
References DBG, DBG2, DBGP, DescOwn, memset(), netdev_priv(), netdev_tx_complete(), NUM_TX_DESC, TxDesc::opts1, tp, rtl8169_private::tx_base, rtl8169_private::tx_curr, rtl8169_private::tx_fill_ctr, rtl8169_private::tx_iobuf, rtl8169_private::tx_tail, and virt_to_bus().
Referenced by rtl8169_poll().
01613 { 01614 struct rtl8169_private *tp = netdev_priv ( netdev ); 01615 01616 uint32_t tx_status; 01617 struct TxDesc *tx_curr_desc; 01618 01619 DBGP ( "rtl8169_process_tx_packets\n" ); 01620 01621 while ( tp->tx_tail != tp->tx_curr ) { 01622 01623 tx_curr_desc = tp->tx_base + tp->tx_tail; 01624 01625 tx_status = tx_curr_desc->opts1; 01626 01627 DBG2 ( "Before DescOwn check tx_status: %#08x\n", tx_status ); 01628 01629 /* if the packet at tx_tail is not owned by hardware it is for us */ 01630 if ( tx_status & DescOwn ) 01631 break; 01632 01633 DBG ( "Transmitted packet.\n" ); 01634 DBG ( "tp->tx_fill_ctr = %d\n", tp->tx_fill_ctr ); 01635 DBG ( "tp->tx_tail = %d\n", tp->tx_tail ); 01636 DBG ( "tp->tx_curr = %d\n", tp->tx_curr ); 01637 DBG ( "tx_status = %d\n", tx_status ); 01638 DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) ); 01639 01640 /* Pass packet to core for processing */ 01641 netdev_tx_complete ( netdev, tp->tx_iobuf[tp->tx_tail] ); 01642 01643 memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) ); 01644 01645 /* Decrement count of used descriptors */ 01646 tp->tx_fill_ctr--; 01647 01648 /* Increment sent packets index */ 01649 tp->tx_tail = ( tp->tx_tail + 1 ) % NUM_TX_DESC; 01650 } 01651 }
| static void rtl8169_free_tx_resources | ( | struct rtl8169_private * | tp | ) | [static] |
Definition at line 1654 of file r8169.c.
References DBGP, free_dma(), R8169_TX_RING_BYTES, and rtl8169_private::tx_base.
Referenced by rtl8169_close(), and rtl8169_open().
01655 { 01656 DBGP ( "rtl8169_free_tx_resources\n" ); 01657 01658 free_dma ( tp->tx_base, R8169_TX_RING_BYTES ); 01659 }
| static void rtl8169_populate_rx_descriptor | ( | struct rtl8169_private * | tp, | |
| struct RxDesc * | rx_desc, | |||
| uint32_t | index | |||
| ) | [static] |
Definition at line 1662 of file r8169.c.
References RxDesc::addr_hi, RxDesc::addr_lo, io_buffer::data, DBG, DBGP, DescOwn, memset(), NUM_RX_DESC, RxDesc::opts1, RxDesc::opts2, RingEnd, RX_BUF_SIZE, rtl8169_private::rx_iobuf, and virt_to_bus().
Referenced by rtl8169_refill_rx_ring().
01663 { 01664 DBGP ( "rtl8169_populate_rx_descriptor\n" ); 01665 01666 DBG ( "Populating rx descriptor %d\n", index ); 01667 01668 memset ( rx_desc, 0, sizeof ( *rx_desc ) ); 01669 01670 rx_desc->addr_hi = 0; 01671 rx_desc->addr_lo = virt_to_bus ( tp->rx_iobuf[index]->data ); 01672 rx_desc->opts2 = 0; 01673 rx_desc->opts1 = ( index == ( NUM_RX_DESC - 1 ) ? RingEnd : 0 ) | 01674 RX_BUF_SIZE; 01675 rx_desc->opts1 |= DescOwn; 01676 }
| static void rtl8169_refill_rx_ring | ( | struct rtl8169_private * | tp | ) | [static] |
Refill descriptor ring.
| netdev | Net device |
If we can't get an iobuf for this descriptor try again later (next poll).
Definition at line 1683 of file r8169.c.
References alloc_iob(), DBG, DBGP, DescOwn, NULL, NUM_RX_DESC, RxDesc::opts1, rtl8169_populate_rx_descriptor(), rtl8169_private::rx_base, RX_BUF_SIZE, rtl8169_private::rx_curr, and rtl8169_private::rx_iobuf.
Referenced by rtl8169_process_rx_packets(), and rtl8169_setup_rx_resources().
01684 { 01685 struct RxDesc *rx_curr_desc; 01686 int i; 01687 01688 DBGP ( "rtl8169_refill_rx_ring\n" ); 01689 01690 for ( i = 0; i < NUM_RX_DESC; i++ ) { 01691 01692 rx_curr_desc = ( tp->rx_base ) + i; 01693 01694 /* Don't touch descriptors owned by the NIC */ 01695 if ( rx_curr_desc->opts1 & DescOwn ) 01696 continue; 01697 01698 /* Don't touch descriptors with iobufs, they still need to be 01699 processed by the poll routine */ 01700 if ( tp->rx_iobuf[tp->rx_curr] != NULL ) 01701 continue; 01702 01703 /** If we can't get an iobuf for this descriptor 01704 try again later (next poll). 01705 */ 01706 if ( ! ( tp->rx_iobuf[i] = alloc_iob ( RX_BUF_SIZE ) ) ) { 01707 DBG ( "Refill rx ring failed!!\n" ); 01708 break; 01709 } 01710 01711 rtl8169_populate_rx_descriptor ( tp, rx_curr_desc, i ); 01712 } 01713 }
| static int rtl8169_setup_rx_resources | ( | struct rtl8169_private * | tp | ) | [static] |
setup_rx_resources - allocate Rx resources (Descriptors)
| tp,: | Driver private structure |
| rc | Returns 0 on success, negative on failure |
Definition at line 1724 of file r8169.c.
References DBG, DBGP, ENOMEM, malloc_dma(), memset(), R8169_RX_RING_BYTES, rtl8169_refill_rx_ring(), rtl8169_private::rx_base, rtl8169_private::rx_curr, RX_RING_ALIGN, and virt_to_bus().
Referenced by rtl8169_open().
01725 { 01726 DBGP ( "rtl8169_setup_rx_resources\n" ); 01727 01728 tp->rx_base = malloc_dma ( R8169_RX_RING_BYTES, RX_RING_ALIGN ); 01729 01730 DBG ( "tp->rx_base = %#08lx\n", virt_to_bus ( tp->rx_base ) ); 01731 01732 if ( ! tp->rx_base ) { 01733 return -ENOMEM; 01734 } 01735 memset ( tp->rx_base, 0, R8169_RX_RING_BYTES ); 01736 01737 rtl8169_refill_rx_ring ( tp ); 01738 01739 tp->rx_curr = 0; 01740 01741 return 0; 01742 }
| static void rtl8169_process_rx_packets | ( | struct net_device * | netdev | ) | [static] |
Definition at line 1745 of file r8169.c.
References DBG, DBG2, DBGP, DescOwn, EINVAL, iob_put, memset(), netdev_priv(), netdev_rx(), netdev_rx_err(), NULL, NUM_RX_DESC, RxDesc::opts1, rtl8169_refill_rx_ring(), rtl8169_private::rx_base, rtl8169_private::rx_curr, rtl8169_private::rx_iobuf, RxRES, tp, and virt_to_bus().
Referenced by rtl8169_poll().
01746 { 01747 struct rtl8169_private *tp = netdev_priv ( netdev ); 01748 uint32_t rx_status; 01749 uint16_t rx_len; 01750 struct RxDesc *rx_curr_desc; 01751 int i; 01752 01753 DBGP ( "rtl8169_process_rx_packets\n" ); 01754 01755 for ( i = 0; i < NUM_RX_DESC; i++ ) { 01756 01757 rx_curr_desc = tp->rx_base + tp->rx_curr; 01758 01759 rx_status = rx_curr_desc->opts1; 01760 01761 DBG2 ( "Before DescOwn check rx_status: %#08x\n", rx_status ); 01762 01763 /* Hardware still owns the descriptor */ 01764 if ( rx_status & DescOwn ) 01765 break; 01766 01767 /* We own the descriptor, but it has not been refilled yet */ 01768 if ( tp->rx_iobuf[tp->rx_curr] == NULL ) 01769 break; 01770 01771 rx_len = rx_status & 0x3fff; 01772 01773 DBG ( "Received packet.\n" ); 01774 DBG ( "tp->rx_curr = %d\n", tp->rx_curr ); 01775 DBG ( "rx_len = %d\n", rx_len ); 01776 DBG ( "rx_status = %#08x\n", rx_status ); 01777 DBG ( "rx_curr_desc = %#08lx\n", virt_to_bus ( rx_curr_desc ) ); 01778 01779 if ( rx_status & RxRES ) { 01780 01781 netdev_rx_err ( netdev, tp->rx_iobuf[tp->rx_curr], -EINVAL ); 01782 01783 DBG ( "rtl8169_poll: Corrupted packet received!\n" 01784 " rx_status: %#08x\n", rx_status ); 01785 01786 } else { 01787 01788 /* Adjust size of the iobuf to reflect received data */ 01789 iob_put ( tp->rx_iobuf[tp->rx_curr], rx_len ); 01790 01791 /* Add this packet to the receive queue. */ 01792 netdev_rx ( netdev, tp->rx_iobuf[tp->rx_curr] ); 01793 } 01794 01795 /* Invalidate this iobuf and descriptor */ 01796 tp->rx_iobuf[tp->rx_curr] = NULL; 01797 memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) ); 01798 01799 /* Update pointer to next available rx descriptor */ 01800 tp->rx_curr = ( tp->rx_curr + 1 ) % NUM_RX_DESC; 01801 } 01802 rtl8169_refill_rx_ring ( tp ); 01803 }
| static void rtl8169_free_rx_resources | ( | struct rtl8169_private * | tp | ) | [static] |
Definition at line 1806 of file r8169.c.
References DBGP, free_dma(), free_iob(), NULL, NUM_RX_DESC, R8169_RX_RING_BYTES, rtl8169_private::rx_base, and rtl8169_private::rx_iobuf.
Referenced by rtl8169_close().
01807 { 01808 int i; 01809 01810 DBGP ( "rtl8169_free_rx_resources\n" ); 01811 01812 free_dma ( tp->rx_base, R8169_RX_RING_BYTES ); 01813 01814 for ( i = 0; i < NUM_RX_DESC; i++ ) { 01815 free_iob ( tp->rx_iobuf[i] ); 01816 tp->rx_iobuf[i] = NULL; 01817 } 01818 }
Definition at line 1850 of file r8169.c.
References ARRAY_SIZE, DBG, DBGP, index, nic_variant_table, RTL_CFG_0, and u32.
Referenced by rtl8169_probe().
01851 { 01852 u32 i; 01853 01854 DBGP ( "rtl8169_get_nic_variant\n" ); 01855 01856 for (i = 0; i < ARRAY_SIZE(nic_variant_table); i++) { 01857 if ( ( nic_variant_table[i].vendor == vendor ) && 01858 ( nic_variant_table[i].device == device ) ) { 01859 return ( nic_variant_table[i].index ); 01860 } 01861 } 01862 DBG ( "No matching NIC variant found!\n" ); 01863 return ( RTL_CFG_0 ); 01864 }
| static void rtl8169_irq_enable | ( | struct rtl8169_private * | tp | ) | [static] |
Definition at line 1866 of file r8169.c.
References DBGP, rtl8169_private::intr_event, IntrMask, ioaddr, rtl8169_private::mmio_addr, and RTL_W16.
Referenced by rtl8169_irq().
01867 { 01868 void *ioaddr = tp->mmio_addr; 01869 01870 DBGP ( "rtl8169_irq_enable\n" ); 01871 01872 RTL_W16 ( IntrMask, tp->intr_event ); 01873 }
| static void rtl8169_irq_disable | ( | struct rtl8169_private * | tp | ) | [static] |
Definition at line 1875 of file r8169.c.
References DBGP, ioaddr, rtl8169_private::mmio_addr, and rtl8169_irq_mask_and_ack().
Referenced by rtl8169_irq().
01876 { 01877 void *ioaddr = tp->mmio_addr; 01878 01879 DBGP ( "rtl8169_irq_disable\n" ); 01880 01881 rtl8169_irq_mask_and_ack ( ioaddr ); 01882 }
| static int rtl8169_open | ( | struct net_device * | netdev | ) | [static] |
open - Called when a network interface is made active
| rc | Return status code, 0 on success, negative value on failure |
Definition at line 1894 of file r8169.c.
References DBG, DBGP, ioaddr, rtl8169_private::mmio_addr, netdev_priv(), rtl8169_free_tx_resources(), rtl8169_hw_reset(), rtl8169_setup_rx_resources(), rtl8169_setup_tx_resources(), rtl_hw_start(), RTL_R32, RxDescAddrHigh, RxDescAddrLow, tp, TxDescStartAddrHigh, and TxDescStartAddrLow.
01895 { 01896 struct rtl8169_private *tp = netdev_priv ( netdev ); 01897 void *ioaddr = tp->mmio_addr; 01898 int rc; 01899 01900 DBGP ( "rtl8169_open\n" ); 01901 01902 /* allocate transmit descriptors */ 01903 rc = rtl8169_setup_tx_resources ( tp ); 01904 if ( rc ) { 01905 DBG ( "Error setting up TX resources!\n" ); 01906 goto err_setup_tx; 01907 } 01908 01909 /* allocate receive descriptors */ 01910 rc = rtl8169_setup_rx_resources ( tp ); 01911 if ( rc ) { 01912 DBG ( "Error setting up RX resources!\n" ); 01913 goto err_setup_rx; 01914 } 01915 01916 rtl_hw_start ( netdev ); 01917 01918 DBG ( "TxDescStartAddrHigh = %#08lx\n", RTL_R32 ( TxDescStartAddrHigh ) ); 01919 DBG ( "TxDescStartAddrLow = %#08lx\n", RTL_R32 ( TxDescStartAddrLow ) ); 01920 DBG ( "RxDescAddrHigh = %#08lx\n", RTL_R32 ( RxDescAddrHigh ) ); 01921 DBG ( "RxDescAddrLow = %#08lx\n", RTL_R32 ( RxDescAddrLow ) ); 01922 01923 return 0; 01924 01925 err_setup_rx: 01926 rtl8169_free_tx_resources ( tp ); 01927 err_setup_tx: 01928 rtl8169_hw_reset ( ioaddr ); 01929 01930 return rc; 01931 }
| static int rtl8169_transmit | ( | struct net_device * | netdev, | |
| struct io_buffer * | iobuf | |||
| ) | [static] |
transmit - Transmit a packet
| netdev | Network device | |
| iobuf | I/O buffer |
| rc | Returns 0 on success, negative on failure |
The rtl8169 family automatically pads short packets to a minimum size, but if it did not, like some older cards, we could do: iob_pad ( iobuf, ETH_ZLEN );
Definition at line 1942 of file r8169.c.
References TxDesc::addr_hi, TxDesc::addr_lo, io_buffer::data, DBG, DBGP, DescOwn, ENOBUFS, FirstFrag, ioaddr, iob_len(), LastFrag, rtl8169_private::mmio_addr, netdev_priv(), NPQ, NUM_TX_DESC, TxDesc::opts1, TxDesc::opts2, RingEnd, RTL_W8, tp, rtl8169_private::tx_base, rtl8169_private::tx_curr, rtl8169_private::tx_fill_ctr, rtl8169_private::tx_iobuf, TxPoll, and virt_to_bus().
01943 { 01944 struct rtl8169_private *tp = netdev_priv ( netdev ); 01945 void *ioaddr = tp->mmio_addr; 01946 uint32_t tx_len = iob_len ( iobuf ); 01947 01948 struct TxDesc *tx_curr_desc; 01949 01950 DBGP ("rtl8169_transmit\n"); 01951 01952 if ( tp->tx_fill_ctr == NUM_TX_DESC ) { 01953 DBG ("TX overflow\n"); 01954 return -ENOBUFS; 01955 } 01956 01957 /** 01958 * The rtl8169 family automatically pads short packets to a 01959 * minimum size, but if it did not, like some older cards, 01960 * we could do: 01961 * iob_pad ( iobuf, ETH_ZLEN ); 01962 */ 01963 01964 /* Save pointer to this iobuf we have been given to transmit so 01965 we can pass it to netdev_tx_complete() later */ 01966 tp->tx_iobuf[tp->tx_curr] = iobuf; 01967 01968 tx_curr_desc = tp->tx_base + tp->tx_curr; 01969 01970 DBG ( "tp->tx_fill_ctr = %d\n", tp->tx_fill_ctr ); 01971 DBG ( "tp->tx_curr = %d\n", tp->tx_curr ); 01972 DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) ); 01973 DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) ); 01974 DBG ( "tx_len = %d\n", tx_len ); 01975 01976 /* Configure current descriptor to transmit supplied packet */ 01977 tx_curr_desc->addr_hi = 0; 01978 tx_curr_desc->addr_lo = virt_to_bus ( iobuf->data ); 01979 tx_curr_desc->opts2 = 0; 01980 tx_curr_desc->opts1 = FirstFrag | LastFrag | 01981 ( tp->tx_curr == ( NUM_TX_DESC - 1 ) ? RingEnd : 0 ) | 01982 tx_len; 01983 01984 /* Mark descriptor as owned by NIC */ 01985 tx_curr_desc->opts1 |= DescOwn; 01986 01987 DBG ( "tx_curr_desc->opts1 = %#08x\n", tx_curr_desc->opts1 ); 01988 DBG ( "tx_curr_desc->opts2 = %#08x\n", tx_curr_desc->opts2 ); 01989 DBG ( "tx_curr_desc->addr_hi = %#08x\n", tx_curr_desc->addr_hi ); 01990 DBG ( "tx_curr_desc->addr_lo = %#08x\n", tx_curr_desc->addr_lo ); 01991 01992 RTL_W8 ( TxPoll, NPQ ); /* set polling bit */ 01993 01994 /* Point to next free descriptor */ 01995 tp->tx_curr = ( tp->tx_curr + 1 ) % NUM_TX_DESC; 01996 01997 /* Increment number of tx descriptors in use */ 01998 tp->tx_fill_ctr++; 01999 02000 return 0; 02001 }
| static void rtl8169_poll | ( | struct net_device * | netdev | ) | [static] |
poll - Poll for received packets
| netdev | Network device |
Definition at line 2009 of file r8169.c.
References DBG2, DBGP, IntrMask, IntrStatus, ioaddr, rtl8169_private::mmio_addr, netdev_priv(), rtl8169_process_rx_packets(), rtl8169_process_tx_packets(), RTL_R16, RTL_W16, and tp.
02010 { 02011 struct rtl8169_private *tp = netdev_priv ( netdev ); 02012 void *ioaddr = tp->mmio_addr; 02013 02014 uint16_t intr_status; 02015 uint16_t intr_mask; 02016 02017 DBGP ( "rtl8169_poll\n" ); 02018 02019 intr_status = RTL_R16 ( IntrStatus ); 02020 intr_mask = RTL_R16 ( IntrMask ); 02021 02022 DBG2 ( "rtl8169_poll (before): intr_mask = %#04x intr_status = %#04x\n", 02023 intr_mask, intr_status ); 02024 02025 RTL_W16 ( IntrStatus, 0xffff ); 02026 02027 /* hotplug / major error / no more work / shared irq */ 02028 if ( intr_status == 0xffff ) 02029 return; 02030 02031 /* Process transmitted packets */ 02032 rtl8169_process_tx_packets ( netdev ); 02033 02034 /* Process received packets */ 02035 rtl8169_process_rx_packets ( netdev ); 02036 }
| static void rtl8169_close | ( | struct net_device * | netdev | ) | [static] |
close - Disable network interface
Definition at line 2045 of file r8169.c.
References DBGP, ioaddr, rtl8169_private::mmio_addr, netdev_priv(), rtl8169_free_rx_resources(), rtl8169_free_tx_resources(), rtl8169_hw_reset(), and tp.
02046 { 02047 struct rtl8169_private *tp = netdev_priv ( netdev ); 02048 void *ioaddr = tp->mmio_addr; 02049 02050 DBGP ( "r8169_close\n" ); 02051 02052 rtl8169_hw_reset ( ioaddr ); 02053 02054 rtl8169_free_tx_resources ( tp ); 02055 rtl8169_free_rx_resources ( tp ); 02056 }
| static void rtl8169_irq | ( | struct net_device * | netdev, | |
| int | action | |||
| ) | [static] |
irq - enable or Disable interrupts
| netdev | network adapter | |
| action | requested interrupt action |
Definition at line 2066 of file r8169.c.
References DBGP, netdev_priv(), rtl8169_irq_disable(), rtl8169_irq_enable(), and tp.
02067 { 02068 struct rtl8169_private *tp = netdev_priv ( netdev ); 02069 02070 DBGP ( "rtl8169_irq\n" ); 02071 02072 switch ( action ) { 02073 case 0 : 02074 rtl8169_irq_disable ( tp ); 02075 break; 02076 default : 02077 rtl8169_irq_enable ( tp ); 02078 break; 02079 } 02080 }
| static int rtl8169_probe | ( | struct pci_device * | pdev, | |
| const struct pci_device_id * | ent | |||
| ) | [static] |
probe - Initial configuration of NIC
| pci | PCI device | |
| id | PCI IDs |
| rc | Return status code |
FIXME: This lookup is necessary because gPXE does not have a "data" element in the structure pci_device_id which can pass an arbitrary piece of data to the driver. It might be useful to add it. Then we could just use ent->data instead of having to look up cfg_index.
Definition at line 2099 of file r8169.c.
References adjust_pci_device(), ADVERTISE_1000FULL, alloc_etherdev(), ARRAY_SIZE, cfg, rtl8169_private::cfg_index, rtl8169_private::chipset, rtl8169_private::cp_cmd, DBG, DBGP, pci_device::dev, net_device::dev, pci_device_id::device, EIO, ENOMEM, eth_ntoa(), net_device::hw_addr, rtl_cfg_info::hw_start, rtl8169_private::hw_start, rtl8169_private::intr_event, rtl_cfg_info::intr_event, ioaddr, ioremap(), pci_device::irq, rtl8169_private::irqno, rtl8169_private::link_ok, MAC0, MAC_ADDR_LEN, rtl8169_private::mac_version, pci_device::membase, memset(), rtl8169_private::mmio_addr, name, rtl8169_private::netdev, netdev, netdev_init(), netdev_link_up(), netdev_priv(), netdev_put(), PCI_CAP_ID_EXP, rtl8169_private::pci_dev, pci_find_capability(), pci_set_drvdata(), rtl8169_private::pcie_cap, PCIMulRW, rtl8169_private::phy_1000_ctrl_reg, rtl8169_private::phy_reset_enable, rtl8169_private::phy_reset_pending, PHYstatus, R8169_REGS_SIZE, register_netdev(), rtl8169_get_mac_version(), rtl8169_get_nic_variant(), rtl8169_init_phy(), rtl8169_irq_mask_and_ack(), rtl8169_set_speed_tbi(), rtl8169_set_speed_xmii(), rtl8169_tbi_link_ok(), rtl8169_tbi_reset_enable(), rtl8169_tbi_reset_pending(), rtl8169_xmii_link_ok(), rtl8169_xmii_reset_enable(), rtl8169_xmii_reset_pending(), rtl_cfg_infos, rtl_chip_info, RTL_GIGA_MAC_VER_06, RTL_R8, rtl_soft_reset(), rtl8169_private::set_speed, TBI_Enable, tp, u32, and pci_device_id::vendor.
02100 { 02101 int i, rc; 02102 struct net_device *netdev; 02103 struct rtl8169_private *tp; 02104 void *ioaddr; 02105 02106 /** FIXME: This lookup is necessary because gPXE does not have a "data" 02107 element in the structure pci_device_id which can pass an arbitrary 02108 piece of data to the driver. It might be useful to add it. Then we 02109 could just use ent->data instead of having to look up cfg_index. 02110 **/ 02111 int cfg_index = rtl8169_get_nic_variant ( ent->vendor, ent->device ); 02112 const struct rtl_cfg_info *cfg = rtl_cfg_infos + cfg_index; 02113 02114 DBGP ( "rtl8169_probe\n" ); 02115 02116 DBG ( "ent->vendor = %#04x, ent->device = %#04x\n", ent->vendor, ent->device ); 02117 02118 DBG ( "cfg_index = %d\n", cfg_index ); 02119 DBG ( "cfg->intr_event = %#04x\n", cfg->intr_event ); 02120 02121 rc = -ENOMEM; 02122 02123 /* Allocate net device ( also allocates memory for netdev->priv 02124 and makes netdev-priv point to it ) 02125 */ 02126 netdev = alloc_etherdev ( sizeof ( *tp ) ); 02127 02128 if ( ! netdev ) 02129 goto err_alloc_etherdev; 02130 02131 /* Associate driver-specific network operations with 02132 generic network device layer 02133 */ 02134 netdev_init ( netdev, &rtl8169_operations ); 02135 02136 /* Associate this network device with the given PCI device */ 02137 pci_set_drvdata ( pdev, netdev ); 02138 netdev->dev = &pdev->dev; 02139 02140 /* Initialize driver private storage */ 02141 tp = netdev_priv ( netdev ); 02142 memset ( tp, 0, ( sizeof ( *tp ) ) ); 02143 02144 tp->pci_dev = pdev; 02145 tp->irqno = pdev->irq; 02146 tp->netdev = netdev; 02147 tp->cfg_index = cfg_index; 02148 tp->intr_event = cfg->intr_event; 02149 tp->cp_cmd = PCIMulRW; 02150 02151 tp->hw_start = cfg->hw_start; 02152 02153 rc = -EIO; 02154 02155 adjust_pci_device ( pdev ); 02156 02157 /* ioremap MMIO region */ 02158 ioaddr = ioremap ( pdev->membase, R8169_REGS_SIZE ); 02159 02160 if ( ! ioaddr ) { 02161 DBG ( "cannot remap MMIO\n" ); 02162 rc = -EIO; 02163 goto err_ioremap; 02164 } 02165 02166 tp->mmio_addr = ioaddr; 02167 02168 tp->pcie_cap = pci_find_capability ( pdev, PCI_CAP_ID_EXP ); 02169 if ( tp->pcie_cap ) { 02170 DBG ( "PCI Express capability\n" ); 02171 } else { 02172 DBG ( "No PCI Express capability\n" ); 02173 } 02174 02175 /* Mask interrupts just in case */ 02176 rtl8169_irq_mask_and_ack ( ioaddr ); 02177 02178 /* Soft reset NIC */ 02179 rtl_soft_reset ( netdev ); 02180 02181 /* Identify chip attached to board */ 02182 rtl8169_get_mac_version ( tp, ioaddr ); 02183 02184 for ( i = 0; (u32) i < ARRAY_SIZE ( rtl_chip_info ); i++ ) { 02185 if ( tp->mac_version == rtl_chip_info[i].mac_version ) 02186 break; 02187 } 02188 if ( i == ARRAY_SIZE(rtl_chip_info ) ) { 02189 /* Unknown chip: assume array element #0, original RTL-8169 */ 02190 DBG ( "Unknown chip version, assuming %s\n", rtl_chip_info[0].name ); 02191 i = 0; 02192 } 02193 tp->chipset = i; 02194 02195 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && 02196 (RTL_R8(PHYstatus) & TBI_Enable)) { 02197 tp->set_speed = rtl8169_set_speed_tbi; 02198 tp->phy_reset_enable = rtl8169_tbi_reset_enable; 02199 tp->phy_reset_pending = rtl8169_tbi_reset_pending; 02200 tp->link_ok = rtl8169_tbi_link_ok; 02201 02202 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ 02203 } else { 02204 tp->set_speed = rtl8169_set_speed_xmii; 02205 tp->phy_reset_enable = rtl8169_xmii_reset_enable; 02206 tp->phy_reset_pending = rtl8169_xmii_reset_pending; 02207 tp->link_ok = rtl8169_xmii_link_ok; 02208 } 02209 02210 /* Get MAC address */ 02211 for ( i = 0; i < MAC_ADDR_LEN; i++ ) 02212 netdev->hw_addr[i] = RTL_R8 ( MAC0 + i ); 02213 02214 DBG ( "%s\n", eth_ntoa ( netdev->hw_addr ) ); 02215 02216 rtl8169_init_phy ( netdev, tp ); 02217 02218 if ( ( rc = register_netdev ( netdev ) ) != 0 ) 02219 goto err_register; 02220 02221 /* Mark as link up; we don't yet handle link state */ 02222 netdev_link_up ( netdev ); 02223 02224 DBG ( "rtl8169_probe succeeded!\n" ); 02225 02226 /* No errors, return success */ 02227 return 0; 02228 02229 /* Error return paths */ 02230 err_register: 02231 err_ioremap: 02232 netdev_put ( netdev ); 02233 err_alloc_etherdev: 02234 return rc; 02235 }
| static void rtl8169_remove | ( | struct pci_device * | pdev | ) | [static] |
remove - Device Removal Routine
| pdev | PCI device information struct |
Definition at line 2244 of file r8169.c.
References DBGP, ioaddr, rtl8169_private::mmio_addr, netdev, netdev_nullify(), netdev_priv(), netdev_put(), pci_get_drvdata(), rtl8169_hw_reset(), tp, and unregister_netdev().
02245 { 02246 struct net_device *netdev = pci_get_drvdata ( pdev ); 02247 struct rtl8169_private *tp = netdev_priv ( netdev ); 02248 void *ioaddr = tp->mmio_addr; 02249 02250 DBGP ( "rtl8169_remove\n" ); 02251 02252 rtl8169_hw_reset ( ioaddr ); 02253 02254 unregister_netdev ( netdev ); 02255 netdev_nullify ( netdev ); 02256 netdev_put ( netdev ); 02257 }
struct rtl_cfg_info rtl_cfg_infos[] [static] |
Referenced by rtl8169_probe().
| int index |
Definition at line 1834 of file r8169.c.
Referenced by amd8111e_poll(), amd8111e_transmit(), arbel_mcast_attach(), arbel_mcast_detach(), ath5k_hw_rfb_op(), atl1e_clean_tx_ring(), bitmap_set(), bitmap_test(), hermon_mcast_attach(), hermon_mcast_detach(), mtnic_alloc_iobuf(), mtnic_free_io_buffers(), mtnic_process_rx_cq(), mtnic_process_tx_cq(), mtnic_transmit(), phantom_clp_cmd(), phantom_refill_rx_ring(), phantom_transmit(), phantom_update_macaddr(), and rtl8169_get_nic_variant().
struct { ... } nic_variant_table[] [static] |
Referenced by rtl8169_get_nic_variant().
struct net_device_operations rtl8169_operations [static] |
Initial value:
{
.open = rtl8169_open,
.transmit = rtl8169_transmit,
.poll = rtl8169_poll,
.close = rtl8169_close,
.irq = rtl8169_irq,
}
struct pci_device_id rtl8169_nics[] [static] |
Initial value:
{
PCI_ROM(0x10ec, 0x8129, "rtl8169-0x8129", "rtl8169-0x8129", 0),
PCI_ROM(0x10ec, 0x8136, "rtl8169-0x8136", "rtl8169-0x8136", 0),
PCI_ROM(0x10ec, 0x8167, "rtl8169-0x8167", "rtl8169-0x8167", 0),
PCI_ROM(0x10ec, 0x8168, "rtl8169-0x8168", "rtl8169-0x8168", 0),
PCI_ROM(0x10ec, 0x8169, "rtl8169-0x8169", "rtl8169-0x8169", 0),
PCI_ROM(0x1186, 0x4300, "rtl8169-0x4300", "rtl8169-0x4300", 0),
PCI_ROM(0x1259, 0xc107, "rtl8169-0xc107", "rtl8169-0xc107", 0),
PCI_ROM(0x16ec, 0x0116, "rtl8169-0x0116", "rtl8169-0x0116", 0),
PCI_ROM(0x1737, 0x1032, "rtl8169-0x1032", "rtl8169-0x1032", 0),
PCI_ROM(0x0001, 0x8168, "rtl8169-0x8168", "rtl8169-0x8168", 0),
}
| struct pci_driver rtl8169_driver __pci_driver |
Initial value:
{
.ids = rtl8169_nics,
.id_count = ( sizeof ( rtl8169_nics ) / sizeof ( rtl8169_nics[0] ) ),
.probe = rtl8169_probe,
.remove = rtl8169_remove,
}
1.5.7.1