00001 /* 00002 * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved. 00003 * 00004 * 00005 * This software is available to you under a choice of one of two 00006 * licenses. You may choose to be licensed under the terms of the GNU 00007 * General Public License (GPL) Version 2, available from the file 00008 * COPYING in the main directory of this source tree, or the 00009 * OpenIB.org BSD license below: 00010 * 00011 * Redistribution and use in source and binary forms, with or 00012 * without modification, are permitted provided that the following 00013 * conditions are met: 00014 * 00015 * - Redistributions of source code must retain the above 00016 * copyright notice, this list of conditions and the following 00017 * disclaimer. 00018 * 00019 * - Redistributions in binary form must reproduce the above 00020 * copyright notice, this list of conditions and the following 00021 * disclaimer in the documentation and/or other materials 00022 * provided with the distribution. 00023 * 00024 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 00025 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00026 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 00027 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 00028 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 00029 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 00030 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 00031 * SOFTWARE. 00032 * 00033 */ 00034 /* This file is mechanically generated from RTL. Any hand-edits will be lost! */ 00035 00036 /* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */ 00037 00038 FILE_LICENCE ( GPL2_ONLY ); 00039 00040 #define QIB_7220_Revision_offset 0x00000000UL 00041 struct QIB_7220_Revision_pb { 00042 pseudo_bit_t R_ChipRevMinor[8]; 00043 pseudo_bit_t R_ChipRevMajor[8]; 00044 pseudo_bit_t R_Arch[8]; 00045 pseudo_bit_t R_SW[8]; 00046 pseudo_bit_t BoardID[8]; 00047 pseudo_bit_t R_Emulation_Revcode[22]; 00048 pseudo_bit_t R_Emulation[1]; 00049 pseudo_bit_t R_Simulator[1]; 00050 }; 00051 struct QIB_7220_Revision { 00052 PSEUDO_BIT_STRUCT ( struct QIB_7220_Revision_pb ); 00053 }; 00054 00055 #define QIB_7220_Control_offset 0x00000008UL 00056 struct QIB_7220_Control_pb { 00057 pseudo_bit_t SyncReset[1]; 00058 pseudo_bit_t FreezeMode[1]; 00059 pseudo_bit_t LinkEn[1]; 00060 pseudo_bit_t PCIERetryBufDiagEn[1]; 00061 pseudo_bit_t TxLatency[1]; 00062 pseudo_bit_t Reserved[1]; 00063 pseudo_bit_t PCIECplQDiagEn[1]; 00064 pseudo_bit_t SyncResetExceptPcieIRAMRST[1]; 00065 pseudo_bit_t _unused_0[56]; 00066 }; 00067 struct QIB_7220_Control { 00068 PSEUDO_BIT_STRUCT ( struct QIB_7220_Control_pb ); 00069 }; 00070 00071 #define QIB_7220_PageAlign_offset 0x00000010UL 00072 00073 #define QIB_7220_PortCnt_offset 0x00000018UL 00074 00075 #define QIB_7220_DbgPortSel_offset 0x00000020UL 00076 struct QIB_7220_DbgPortSel_pb { 00077 pseudo_bit_t NibbleSel0[4]; 00078 pseudo_bit_t NibbleSel1[4]; 00079 pseudo_bit_t NibbleSel2[4]; 00080 pseudo_bit_t NibbleSel3[4]; 00081 pseudo_bit_t NibbleSel4[4]; 00082 pseudo_bit_t NibbleSel5[4]; 00083 pseudo_bit_t NibbleSel6[4]; 00084 pseudo_bit_t NibbleSel7[4]; 00085 pseudo_bit_t SrcMuxSel[14]; 00086 pseudo_bit_t DbgClkPortSel[5]; 00087 pseudo_bit_t EnDbgPort[1]; 00088 pseudo_bit_t EnEnhancedDebugMode[1]; 00089 pseudo_bit_t EnhMode_SrcMuxSelIndex[10]; 00090 pseudo_bit_t EnhMode_SrcMuxSelWrEn[1]; 00091 }; 00092 struct QIB_7220_DbgPortSel { 00093 PSEUDO_BIT_STRUCT ( struct QIB_7220_DbgPortSel_pb ); 00094 }; 00095 00096 #define QIB_7220_DebugSigsIntSel_offset 0x00000028UL 00097 struct QIB_7220_DebugSigsIntSel_pb { 00098 pseudo_bit_t debug_port_sel_pcs_pipe_lane07[3]; 00099 pseudo_bit_t debug_port_sel_pcs_pipe_lane815[3]; 00100 pseudo_bit_t debug_port_sel_pcs_sdout[1]; 00101 pseudo_bit_t debug_port_sel_pcs_symlock_elfifo_lane[4]; 00102 pseudo_bit_t debug_port_sel_pcs_rxdet_encdec_lane[4]; 00103 pseudo_bit_t debug_port_sel_pcie_rx_tx[1]; 00104 pseudo_bit_t debug_port_sel_xgxs[4]; 00105 pseudo_bit_t debug_port_sel_epb_pcie[1]; 00106 pseudo_bit_t _unused_0[43]; 00107 }; 00108 struct QIB_7220_DebugSigsIntSel { 00109 PSEUDO_BIT_STRUCT ( struct QIB_7220_DebugSigsIntSel_pb ); 00110 }; 00111 00112 #define QIB_7220_SendRegBase_offset 0x00000030UL 00113 00114 #define QIB_7220_UserRegBase_offset 0x00000038UL 00115 00116 #define QIB_7220_CntrRegBase_offset 0x00000040UL 00117 00118 #define QIB_7220_Scratch_offset 0x00000048UL 00119 00120 #define QIB_7220_REG_000050_offset 0x00000050UL 00121 00122 #define QIB_7220_IntBlocked_offset 0x00000060UL 00123 struct QIB_7220_IntBlocked_pb { 00124 pseudo_bit_t RcvAvail0IntBlocked[1]; 00125 pseudo_bit_t RcvAvail1IntBlocked[1]; 00126 pseudo_bit_t RcvAvail2IntBlocked[1]; 00127 pseudo_bit_t RcvAvail3IntBlocked[1]; 00128 pseudo_bit_t RcvAvail4IntBlocked[1]; 00129 pseudo_bit_t RcvAvail5IntBlocked[1]; 00130 pseudo_bit_t RcvAvail6IntBlocked[1]; 00131 pseudo_bit_t RcvAvail7IntBlocked[1]; 00132 pseudo_bit_t RcvAvail8IntBlocked[1]; 00133 pseudo_bit_t RcvAvail9IntBlocked[1]; 00134 pseudo_bit_t RcvAvail10IntBlocked[1]; 00135 pseudo_bit_t RcvAvail11IntBlocked[1]; 00136 pseudo_bit_t RcvAvail12IntBlocked[1]; 00137 pseudo_bit_t RcvAvail13IntBlocked[1]; 00138 pseudo_bit_t RcvAvail14IntBlocked[1]; 00139 pseudo_bit_t RcvAvail15IntBlocked[1]; 00140 pseudo_bit_t RcvAvail16IntBlocked[1]; 00141 pseudo_bit_t Reserved1[9]; 00142 pseudo_bit_t JIntBlocked[1]; 00143 pseudo_bit_t IBSerdesTrimDoneIntBlocked[1]; 00144 pseudo_bit_t assertGPIOIntBlocked[1]; 00145 pseudo_bit_t PioBufAvailIntBlocked[1]; 00146 pseudo_bit_t PioSetIntBlocked[1]; 00147 pseudo_bit_t ErrorIntBlocked[1]; 00148 pseudo_bit_t RcvUrg0IntBlocked[1]; 00149 pseudo_bit_t RcvUrg1IntBlocked[1]; 00150 pseudo_bit_t RcvUrg2IntBlocked[1]; 00151 pseudo_bit_t RcvUrg3IntBlocked[1]; 00152 pseudo_bit_t RcvUrg4IntBlocked[1]; 00153 pseudo_bit_t RcvUrg5IntBlocked[1]; 00154 pseudo_bit_t RcvUrg6IntBlocked[1]; 00155 pseudo_bit_t RcvUrg7IntBlocked[1]; 00156 pseudo_bit_t RcvUrg8IntBlocked[1]; 00157 pseudo_bit_t RcvUrg9IntBlocked[1]; 00158 pseudo_bit_t RcvUrg10IntBlocked[1]; 00159 pseudo_bit_t RcvUrg11IntBlocked[1]; 00160 pseudo_bit_t RcvUrg12IntBlocked[1]; 00161 pseudo_bit_t RcvUrg13IntBlocked[1]; 00162 pseudo_bit_t RcvUrg14IntBlocked[1]; 00163 pseudo_bit_t RcvUrg15IntBlocked[1]; 00164 pseudo_bit_t RcvUrg16IntBlocked[1]; 00165 pseudo_bit_t Reserved[13]; 00166 pseudo_bit_t SDmaDisabledBlocked[1]; 00167 pseudo_bit_t SDmaIntBlocked[1]; 00168 }; 00169 struct QIB_7220_IntBlocked { 00170 PSEUDO_BIT_STRUCT ( struct QIB_7220_IntBlocked_pb ); 00171 }; 00172 00173 #define QIB_7220_IntMask_offset 0x00000068UL 00174 struct QIB_7220_IntMask_pb { 00175 pseudo_bit_t RcvAvail0IntMask[1]; 00176 pseudo_bit_t RcvAvail1IntMask[1]; 00177 pseudo_bit_t RcvAvail2IntMask[1]; 00178 pseudo_bit_t RcvAvail3IntMask[1]; 00179 pseudo_bit_t RcvAvail4IntMask[1]; 00180 pseudo_bit_t RcvAvail5IntMask[1]; 00181 pseudo_bit_t RcvAvail6IntMask[1]; 00182 pseudo_bit_t RcvAvail7IntMask[1]; 00183 pseudo_bit_t RcvAvail8IntMask[1]; 00184 pseudo_bit_t RcvAvail9IntMask[1]; 00185 pseudo_bit_t RcvAvail10IntMask[1]; 00186 pseudo_bit_t RcvAvail11IntMask[1]; 00187 pseudo_bit_t RcvAvail12IntMask[1]; 00188 pseudo_bit_t RcvAvail13IntMask[1]; 00189 pseudo_bit_t RcvAvail14IntMask[1]; 00190 pseudo_bit_t RcvAvail15IntMask[1]; 00191 pseudo_bit_t RcvAvail16IntMask[1]; 00192 pseudo_bit_t Reserved1[9]; 00193 pseudo_bit_t JIntMask[1]; 00194 pseudo_bit_t IBSerdesTrimDoneIntMask[1]; 00195 pseudo_bit_t assertGPIOIntMask[1]; 00196 pseudo_bit_t PioBufAvailIntMask[1]; 00197 pseudo_bit_t PioSetIntMask[1]; 00198 pseudo_bit_t ErrorIntMask[1]; 00199 pseudo_bit_t RcvUrg0IntMask[1]; 00200 pseudo_bit_t RcvUrg1IntMask[1]; 00201 pseudo_bit_t RcvUrg2IntMask[1]; 00202 pseudo_bit_t RcvUrg3IntMask[1]; 00203 pseudo_bit_t RcvUrg4IntMask[1]; 00204 pseudo_bit_t RcvUrg5IntMask[1]; 00205 pseudo_bit_t RcvUrg6IntMask[1]; 00206 pseudo_bit_t RcvUrg7IntMask[1]; 00207 pseudo_bit_t RcvUrg8IntMask[1]; 00208 pseudo_bit_t RcvUrg9IntMask[1]; 00209 pseudo_bit_t RcvUrg10IntMask[1]; 00210 pseudo_bit_t RcvUrg11IntMask[1]; 00211 pseudo_bit_t RcvUrg12IntMask[1]; 00212 pseudo_bit_t RcvUrg13IntMask[1]; 00213 pseudo_bit_t RcvUrg14IntMask[1]; 00214 pseudo_bit_t RcvUrg15IntMask[1]; 00215 pseudo_bit_t RcvUrg16IntMask[1]; 00216 pseudo_bit_t Reserved[13]; 00217 pseudo_bit_t SDmaDisabledMasked[1]; 00218 pseudo_bit_t SDmaIntMask[1]; 00219 }; 00220 struct QIB_7220_IntMask { 00221 PSEUDO_BIT_STRUCT ( struct QIB_7220_IntMask_pb ); 00222 }; 00223 00224 #define QIB_7220_IntStatus_offset 0x00000070UL 00225 struct QIB_7220_IntStatus_pb { 00226 pseudo_bit_t RcvAvail0[1]; 00227 pseudo_bit_t RcvAvail1[1]; 00228 pseudo_bit_t RcvAvail2[1]; 00229 pseudo_bit_t RcvAvail3[1]; 00230 pseudo_bit_t RcvAvail4[1]; 00231 pseudo_bit_t RcvAvail5[1]; 00232 pseudo_bit_t RcvAvail6[1]; 00233 pseudo_bit_t RcvAvail7[1]; 00234 pseudo_bit_t RcvAvail8[1]; 00235 pseudo_bit_t RcvAvail9[1]; 00236 pseudo_bit_t RcvAvail10[1]; 00237 pseudo_bit_t RcvAvail11[1]; 00238 pseudo_bit_t RcvAvail12[1]; 00239 pseudo_bit_t RcvAvail13[1]; 00240 pseudo_bit_t RcvAvail14[1]; 00241 pseudo_bit_t RcvAvail15[1]; 00242 pseudo_bit_t RcvAvail16[1]; 00243 pseudo_bit_t Reserved1[9]; 00244 pseudo_bit_t JInt[1]; 00245 pseudo_bit_t IBSerdesTrimDone[1]; 00246 pseudo_bit_t assertGPIO[1]; 00247 pseudo_bit_t PioBufAvail[1]; 00248 pseudo_bit_t PioSent[1]; 00249 pseudo_bit_t Error[1]; 00250 pseudo_bit_t RcvUrg0[1]; 00251 pseudo_bit_t RcvUrg1[1]; 00252 pseudo_bit_t RcvUrg2[1]; 00253 pseudo_bit_t RcvUrg3[1]; 00254 pseudo_bit_t RcvUrg4[1]; 00255 pseudo_bit_t RcvUrg5[1]; 00256 pseudo_bit_t RcvUrg6[1]; 00257 pseudo_bit_t RcvUrg7[1]; 00258 pseudo_bit_t RcvUrg8[1]; 00259 pseudo_bit_t RcvUrg9[1]; 00260 pseudo_bit_t RcvUrg10[1]; 00261 pseudo_bit_t RcvUrg11[1]; 00262 pseudo_bit_t RcvUrg12[1]; 00263 pseudo_bit_t RcvUrg13[1]; 00264 pseudo_bit_t RcvUrg14[1]; 00265 pseudo_bit_t RcvUrg15[1]; 00266 pseudo_bit_t RcvUrg16[1]; 00267 pseudo_bit_t Reserved[13]; 00268 pseudo_bit_t SDmaDisabled[1]; 00269 pseudo_bit_t SDmaInt[1]; 00270 }; 00271 struct QIB_7220_IntStatus { 00272 PSEUDO_BIT_STRUCT ( struct QIB_7220_IntStatus_pb ); 00273 }; 00274 00275 #define QIB_7220_IntClear_offset 0x00000078UL 00276 struct QIB_7220_IntClear_pb { 00277 pseudo_bit_t RcvAvail0IntClear[1]; 00278 pseudo_bit_t RcvAvail1IntClear[1]; 00279 pseudo_bit_t RcvAvail2IntClear[1]; 00280 pseudo_bit_t RcvAvail3IntClear[1]; 00281 pseudo_bit_t RcvAvail4IntClear[1]; 00282 pseudo_bit_t RcvAvail5IntClear[1]; 00283 pseudo_bit_t RcvAvail6IntClear[1]; 00284 pseudo_bit_t RcvAvail7IntClear[1]; 00285 pseudo_bit_t RcvAvail8IntClear[1]; 00286 pseudo_bit_t RcvAvail9IntClear[1]; 00287 pseudo_bit_t RcvAvail10IntClear[1]; 00288 pseudo_bit_t RcvAvail11IntClear[1]; 00289 pseudo_bit_t RcvAvail12IntClear[1]; 00290 pseudo_bit_t RcvAvail13IntClear[1]; 00291 pseudo_bit_t RcvAvail14IntClear[1]; 00292 pseudo_bit_t RcvAvail15IntClear[1]; 00293 pseudo_bit_t RcvAvail16IntClear[1]; 00294 pseudo_bit_t Reserved1[9]; 00295 pseudo_bit_t JIntClear[1]; 00296 pseudo_bit_t IBSerdesTrimDoneClear[1]; 00297 pseudo_bit_t assertGPIOIntClear[1]; 00298 pseudo_bit_t PioBufAvailIntClear[1]; 00299 pseudo_bit_t PioSetIntClear[1]; 00300 pseudo_bit_t ErrorIntClear[1]; 00301 pseudo_bit_t RcvUrg0IntClear[1]; 00302 pseudo_bit_t RcvUrg1IntClear[1]; 00303 pseudo_bit_t RcvUrg2IntClear[1]; 00304 pseudo_bit_t RcvUrg3IntClear[1]; 00305 pseudo_bit_t RcvUrg4IntClear[1]; 00306 pseudo_bit_t RcvUrg5IntClear[1]; 00307 pseudo_bit_t RcvUrg6IntClear[1]; 00308 pseudo_bit_t RcvUrg7IntClear[1]; 00309 pseudo_bit_t RcvUrg8IntClear[1]; 00310 pseudo_bit_t RcvUrg9IntClear[1]; 00311 pseudo_bit_t RcvUrg10IntClear[1]; 00312 pseudo_bit_t RcvUrg11IntClear[1]; 00313 pseudo_bit_t RcvUrg12IntClear[1]; 00314 pseudo_bit_t RcvUrg13IntClear[1]; 00315 pseudo_bit_t RcvUrg14IntClear[1]; 00316 pseudo_bit_t RcvUrg15IntClear[1]; 00317 pseudo_bit_t RcvUrg16IntClear[1]; 00318 pseudo_bit_t Reserved[13]; 00319 pseudo_bit_t SDmaDisabledClear[1]; 00320 pseudo_bit_t SDmaIntClear[1]; 00321 }; 00322 struct QIB_7220_IntClear { 00323 PSEUDO_BIT_STRUCT ( struct QIB_7220_IntClear_pb ); 00324 }; 00325 00326 #define QIB_7220_ErrMask_offset 0x00000080UL 00327 struct QIB_7220_ErrMask_pb { 00328 pseudo_bit_t RcvFormatErrMask[1]; 00329 pseudo_bit_t RcvVCRCErrMask[1]; 00330 pseudo_bit_t RcvICRCErrMask[1]; 00331 pseudo_bit_t RcvMinPktLenErrMask[1]; 00332 pseudo_bit_t RcvMaxPktLenErrMask[1]; 00333 pseudo_bit_t RcvLongPktLenErrMask[1]; 00334 pseudo_bit_t RcvShortPktLenErrMask[1]; 00335 pseudo_bit_t RcvUnexpectedCharErrMask[1]; 00336 pseudo_bit_t RcvUnsupportedVLErrMask[1]; 00337 pseudo_bit_t RcvEBPErrMask[1]; 00338 pseudo_bit_t RcvIBFlowErrMask[1]; 00339 pseudo_bit_t RcvBadVersionErrMask[1]; 00340 pseudo_bit_t RcvEgrFullErrMask[1]; 00341 pseudo_bit_t RcvHdrFullErrMask[1]; 00342 pseudo_bit_t RcvBadTidErrMask[1]; 00343 pseudo_bit_t RcvHdrLenErrMask[1]; 00344 pseudo_bit_t RcvHdrErrMask[1]; 00345 pseudo_bit_t RcvIBLostLinkErrMask[1]; 00346 pseudo_bit_t Reserved1[9]; 00347 pseudo_bit_t SendSpecialTriggerErrMask[1]; 00348 pseudo_bit_t SDmaDisabledErrMask[1]; 00349 pseudo_bit_t SendMinPktLenErrMask[1]; 00350 pseudo_bit_t SendMaxPktLenErrMask[1]; 00351 pseudo_bit_t SendUnderRunErrMask[1]; 00352 pseudo_bit_t SendPktLenErrMask[1]; 00353 pseudo_bit_t SendDroppedSmpPktErrMask[1]; 00354 pseudo_bit_t SendDroppedDataPktErrMask[1]; 00355 pseudo_bit_t SendPioArmLaunchErrMask[1]; 00356 pseudo_bit_t SendUnexpectedPktNumErrMask[1]; 00357 pseudo_bit_t SendUnsupportedVLErrMask[1]; 00358 pseudo_bit_t SendBufMisuseErrMask[1]; 00359 pseudo_bit_t SDmaGenMismatchErrMask[1]; 00360 pseudo_bit_t SDmaOutOfBoundErrMask[1]; 00361 pseudo_bit_t SDmaTailOutOfBoundErrMask[1]; 00362 pseudo_bit_t SDmaBaseErrMask[1]; 00363 pseudo_bit_t SDma1stDescErrMask[1]; 00364 pseudo_bit_t SDmaRpyTagErrMask[1]; 00365 pseudo_bit_t SDmaDwEnErrMask[1]; 00366 pseudo_bit_t SDmaMissingDwErrMask[1]; 00367 pseudo_bit_t SDmaUnexpDataErrMask[1]; 00368 pseudo_bit_t IBStatusChangedMask[1]; 00369 pseudo_bit_t InvalidAddrErrMask[1]; 00370 pseudo_bit_t ResetNegatedMask[1]; 00371 pseudo_bit_t HardwareErrMask[1]; 00372 pseudo_bit_t SDmaDescAddrMisalignErrMask[1]; 00373 pseudo_bit_t InvalidEEPCmdMask[1]; 00374 pseudo_bit_t Reserved[10]; 00375 }; 00376 struct QIB_7220_ErrMask { 00377 PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrMask_pb ); 00378 }; 00379 00380 #define QIB_7220_ErrStatus_offset 0x00000088UL 00381 struct QIB_7220_ErrStatus_pb { 00382 pseudo_bit_t RcvFormatErr[1]; 00383 pseudo_bit_t RcvVCRCErr[1]; 00384 pseudo_bit_t RcvICRCErr[1]; 00385 pseudo_bit_t RcvMinPktLenErr[1]; 00386 pseudo_bit_t RcvMaxPktLenErr[1]; 00387 pseudo_bit_t RcvLongPktLenErr[1]; 00388 pseudo_bit_t RcvShortPktLenErr[1]; 00389 pseudo_bit_t RcvUnexpectedCharErr[1]; 00390 pseudo_bit_t RcvUnsupportedVLErr[1]; 00391 pseudo_bit_t RcvEBPErr[1]; 00392 pseudo_bit_t RcvIBFlowErr[1]; 00393 pseudo_bit_t RcvBadVersionErr[1]; 00394 pseudo_bit_t RcvEgrFullErr[1]; 00395 pseudo_bit_t RcvHdrFullErr[1]; 00396 pseudo_bit_t RcvBadTidErr[1]; 00397 pseudo_bit_t RcvHdrLenErr[1]; 00398 pseudo_bit_t RcvHdrErr[1]; 00399 pseudo_bit_t RcvIBLostLinkErr[1]; 00400 pseudo_bit_t Reserved1[9]; 00401 pseudo_bit_t SendSpecialTriggerErr[1]; 00402 pseudo_bit_t SDmaDisabledErr[1]; 00403 pseudo_bit_t SendMinPktLenErr[1]; 00404 pseudo_bit_t SendMaxPktLenErr[1]; 00405 pseudo_bit_t SendUnderRunErr[1]; 00406 pseudo_bit_t SendPktLenErr[1]; 00407 pseudo_bit_t SendDroppedSmpPktErr[1]; 00408 pseudo_bit_t SendDroppedDataPktErr[1]; 00409 pseudo_bit_t SendPioArmLaunchErr[1]; 00410 pseudo_bit_t SendUnexpectedPktNumErr[1]; 00411 pseudo_bit_t SendUnsupportedVLErr[1]; 00412 pseudo_bit_t SendBufMisuseErr[1]; 00413 pseudo_bit_t SDmaGenMismatchErr[1]; 00414 pseudo_bit_t SDmaOutOfBoundErr[1]; 00415 pseudo_bit_t SDmaTailOutOfBoundErr[1]; 00416 pseudo_bit_t SDmaBaseErr[1]; 00417 pseudo_bit_t SDma1stDescErr[1]; 00418 pseudo_bit_t SDmaRpyTagErr[1]; 00419 pseudo_bit_t SDmaDwEnErr[1]; 00420 pseudo_bit_t SDmaMissingDwErr[1]; 00421 pseudo_bit_t SDmaUnexpDataErr[1]; 00422 pseudo_bit_t IBStatusChanged[1]; 00423 pseudo_bit_t InvalidAddrErr[1]; 00424 pseudo_bit_t ResetNegated[1]; 00425 pseudo_bit_t HardwareErr[1]; 00426 pseudo_bit_t SDmaDescAddrMisalignErr[1]; 00427 pseudo_bit_t InvalidEEPCmdErr[1]; 00428 pseudo_bit_t Reserved[10]; 00429 }; 00430 struct QIB_7220_ErrStatus { 00431 PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrStatus_pb ); 00432 }; 00433 00434 #define QIB_7220_ErrClear_offset 0x00000090UL 00435 struct QIB_7220_ErrClear_pb { 00436 pseudo_bit_t RcvFormatErrClear[1]; 00437 pseudo_bit_t RcvVCRCErrClear[1]; 00438 pseudo_bit_t RcvICRCErrClear[1]; 00439 pseudo_bit_t RcvMinPktLenErrClear[1]; 00440 pseudo_bit_t RcvMaxPktLenErrClear[1]; 00441 pseudo_bit_t RcvLongPktLenErrClear[1]; 00442 pseudo_bit_t RcvShortPktLenErrClear[1]; 00443 pseudo_bit_t RcvUnexpectedCharErrClear[1]; 00444 pseudo_bit_t RcvUnsupportedVLErrClear[1]; 00445 pseudo_bit_t RcvEBPErrClear[1]; 00446 pseudo_bit_t RcvIBFlowErrClear[1]; 00447 pseudo_bit_t RcvBadVersionErrClear[1]; 00448 pseudo_bit_t RcvEgrFullErrClear[1]; 00449 pseudo_bit_t RcvHdrFullErrClear[1]; 00450 pseudo_bit_t RcvBadTidErrClear[1]; 00451 pseudo_bit_t RcvHdrLenErrClear[1]; 00452 pseudo_bit_t RcvHdrErrClear[1]; 00453 pseudo_bit_t RcvIBLostLinkErrClear[1]; 00454 pseudo_bit_t Reserved1[9]; 00455 pseudo_bit_t SendSpecialTriggerErrClear[1]; 00456 pseudo_bit_t SDmaDisabledErrClear[1]; 00457 pseudo_bit_t SendMinPktLenErrClear[1]; 00458 pseudo_bit_t SendMaxPktLenErrClear[1]; 00459 pseudo_bit_t SendUnderRunErrClear[1]; 00460 pseudo_bit_t SendPktLenErrClear[1]; 00461 pseudo_bit_t SendDroppedSmpPktErrClear[1]; 00462 pseudo_bit_t SendDroppedDataPktErrClear[1]; 00463 pseudo_bit_t SendPioArmLaunchErrClear[1]; 00464 pseudo_bit_t SendUnexpectedPktNumErrClear[1]; 00465 pseudo_bit_t SendUnsupportedVLErrClear[1]; 00466 pseudo_bit_t SendBufMisuseErrClear[1]; 00467 pseudo_bit_t SDmaGenMismatchErrClear[1]; 00468 pseudo_bit_t SDmaOutOfBoundErrClear[1]; 00469 pseudo_bit_t SDmaTailOutOfBoundErrClear[1]; 00470 pseudo_bit_t SDmaBaseErrClear[1]; 00471 pseudo_bit_t SDma1stDescErrClear[1]; 00472 pseudo_bit_t SDmaRpyTagErrClear[1]; 00473 pseudo_bit_t SDmaDwEnErrClear[1]; 00474 pseudo_bit_t SDmaMissingDwErrClear[1]; 00475 pseudo_bit_t SDmaUnexpDataErrClear[1]; 00476 pseudo_bit_t IBStatusChangedClear[1]; 00477 pseudo_bit_t InvalidAddrErrClear[1]; 00478 pseudo_bit_t ResetNegatedClear[1]; 00479 pseudo_bit_t HardwareErrClear[1]; 00480 pseudo_bit_t SDmaDescAddrMisalignErrClear[1]; 00481 pseudo_bit_t InvalidEEPCmdErrClear[1]; 00482 pseudo_bit_t Reserved[10]; 00483 }; 00484 struct QIB_7220_ErrClear { 00485 PSEUDO_BIT_STRUCT ( struct QIB_7220_ErrClear_pb ); 00486 }; 00487 00488 #define QIB_7220_HwErrMask_offset 0x00000098UL 00489 struct QIB_7220_HwErrMask_pb { 00490 pseudo_bit_t PCIeMemParityErrMask[8]; 00491 pseudo_bit_t Reserved3[20]; 00492 pseudo_bit_t SDmaMemReadErrMask[1]; 00493 pseudo_bit_t PoisonedTLPMask[1]; 00494 pseudo_bit_t PcieCplTimeoutMask[1]; 00495 pseudo_bit_t PCIeBusParityErrMask[3]; 00496 pseudo_bit_t Reserved2[2]; 00497 pseudo_bit_t PCIEOct0_uC_MemoryParityErrMask[1]; 00498 pseudo_bit_t PCIEOct1_uC_MemoryParityErrMask[1]; 00499 pseudo_bit_t IB_uC_MemoryParityErrMask[1]; 00500 pseudo_bit_t DDSRXEQMemoryParityErrMask[1]; 00501 pseudo_bit_t TXEMemParityErrMask[4]; 00502 pseudo_bit_t RXEMemParityErrMask[7]; 00503 pseudo_bit_t Reserved1[3]; 00504 pseudo_bit_t PowerOnBISTFailedMask[1]; 00505 pseudo_bit_t Reserved[1]; 00506 pseudo_bit_t PCIESerdesQ0PClkNotDetectMask[1]; 00507 pseudo_bit_t PCIESerdesQ1PClkNotDetectMask[1]; 00508 pseudo_bit_t PCIESerdesQ2PClkNotDetectMask[1]; 00509 pseudo_bit_t PCIESerdesQ3PClkNotDetectMask[1]; 00510 pseudo_bit_t IBSerdesPClkNotDetectMask[1]; 00511 pseudo_bit_t Clk_uC_PLLNotLockedMask[1]; 00512 pseudo_bit_t IBCBusToSPCParityErrMask[1]; 00513 pseudo_bit_t IBCBusFromSPCParityErrMask[1]; 00514 }; 00515 struct QIB_7220_HwErrMask { 00516 PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrMask_pb ); 00517 }; 00518 00519 #define QIB_7220_HwErrStatus_offset 0x000000a0UL 00520 struct QIB_7220_HwErrStatus_pb { 00521 pseudo_bit_t PCIeMemParity[8]; 00522 pseudo_bit_t Reserved3[20]; 00523 pseudo_bit_t SDmaMemReadErr[1]; 00524 pseudo_bit_t PoisenedTLP[1]; 00525 pseudo_bit_t PcieCplTimeout[1]; 00526 pseudo_bit_t PCIeBusParity[3]; 00527 pseudo_bit_t Reserved2[2]; 00528 pseudo_bit_t PCIE_uC_Oct0MemoryParityErr[1]; 00529 pseudo_bit_t PCIE_uC_Oct1MemoryParityErr[1]; 00530 pseudo_bit_t IB_uC_MemoryParityErr[1]; 00531 pseudo_bit_t DDSRXEQMemoryParityErr[1]; 00532 pseudo_bit_t TXEMemParity[4]; 00533 pseudo_bit_t RXEMemParity[7]; 00534 pseudo_bit_t Reserved1[3]; 00535 pseudo_bit_t PowerOnBISTFailed[1]; 00536 pseudo_bit_t Reserved[1]; 00537 pseudo_bit_t PCIESerdesQ0PClkNotDetect[1]; 00538 pseudo_bit_t PCIESerdesQ1PClkNotDetect[1]; 00539 pseudo_bit_t PCIESerdesQ2PClkNotDetect[1]; 00540 pseudo_bit_t PCIESerdesQ3PClkNotDetect[1]; 00541 pseudo_bit_t IBSerdesPClkNotDetect[1]; 00542 pseudo_bit_t Clk_uC_PLLNotLocked[1]; 00543 pseudo_bit_t IBCBusToSPCParityErr[1]; 00544 pseudo_bit_t IBCBusFromSPCParityErr[1]; 00545 }; 00546 struct QIB_7220_HwErrStatus { 00547 PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrStatus_pb ); 00548 }; 00549 00550 #define QIB_7220_HwErrClear_offset 0x000000a8UL 00551 struct QIB_7220_HwErrClear_pb { 00552 pseudo_bit_t PCIeMemParityClr[8]; 00553 pseudo_bit_t Reserved3[20]; 00554 pseudo_bit_t SDmaMemReadErrClear[1]; 00555 pseudo_bit_t PoisonedTLPClear[1]; 00556 pseudo_bit_t PcieCplTimeoutClear[1]; 00557 pseudo_bit_t PCIeBusParityClr[3]; 00558 pseudo_bit_t Reserved2[2]; 00559 pseudo_bit_t PCIE_uC_Oct0MemoryParityErrClear[1]; 00560 pseudo_bit_t PCIE_uC_Oct1MemoryParityErrClear[1]; 00561 pseudo_bit_t IB_uC_MemoryParityErrClear[1]; 00562 pseudo_bit_t DDSRXEQMemoryParityErrClear[1]; 00563 pseudo_bit_t TXEMemParityClear[4]; 00564 pseudo_bit_t RXEMemParityClear[7]; 00565 pseudo_bit_t Reserved1[3]; 00566 pseudo_bit_t PowerOnBISTFailedClear[1]; 00567 pseudo_bit_t Reserved[1]; 00568 pseudo_bit_t PCIESerdesQ0PClkNotDetectClear[1]; 00569 pseudo_bit_t PCIESerdesQ1PClkNotDetectClear[1]; 00570 pseudo_bit_t PCIESerdesQ2PClkNotDetectClear[1]; 00571 pseudo_bit_t PCIESerdesQ3PClkNotDetectClear[1]; 00572 pseudo_bit_t IBSerdesPClkNotDetectClear[1]; 00573 pseudo_bit_t Clk_uC_PLLNotLockedClear[1]; 00574 pseudo_bit_t IBCBusToSPCparityErrClear[1]; 00575 pseudo_bit_t IBCBusFromSPCParityErrClear[1]; 00576 }; 00577 struct QIB_7220_HwErrClear { 00578 PSEUDO_BIT_STRUCT ( struct QIB_7220_HwErrClear_pb ); 00579 }; 00580 00581 #define QIB_7220_HwDiagCtrl_offset 0x000000b0UL 00582 struct QIB_7220_HwDiagCtrl_pb { 00583 pseudo_bit_t forcePCIeMemParity[8]; 00584 pseudo_bit_t Reserved2[23]; 00585 pseudo_bit_t forcePCIeBusParity[4]; 00586 pseudo_bit_t Reserved1[1]; 00587 pseudo_bit_t ForcePCIE_uC_Oct0MemoryParityErr[1]; 00588 pseudo_bit_t ForcePCIE_uC_Oct1MemoryParityErr[1]; 00589 pseudo_bit_t ForceIB_uC_MemoryParityErr[1]; 00590 pseudo_bit_t ForceDDSRXEQMemoryParityErr[1]; 00591 pseudo_bit_t ForceTxMemparityErr[4]; 00592 pseudo_bit_t ForceRxMemParityErr[7]; 00593 pseudo_bit_t Reserved[9]; 00594 pseudo_bit_t CounterDisable[1]; 00595 pseudo_bit_t CounterWrEnable[1]; 00596 pseudo_bit_t ForceIBCBusToSPCParityErr[1]; 00597 pseudo_bit_t ForceIBCBusFromSPCParityErr[1]; 00598 }; 00599 struct QIB_7220_HwDiagCtrl { 00600 PSEUDO_BIT_STRUCT ( struct QIB_7220_HwDiagCtrl_pb ); 00601 }; 00602 00603 #define QIB_7220_REG_0000B8_offset 0x000000b8UL 00604 00605 #define QIB_7220_IBCStatus_offset 0x000000c0UL 00606 struct QIB_7220_IBCStatus_pb { 00607 pseudo_bit_t LinkTrainingState[5]; 00608 pseudo_bit_t LinkState[3]; 00609 pseudo_bit_t LinkSpeedActive[1]; 00610 pseudo_bit_t LinkWidthActive[1]; 00611 pseudo_bit_t DDS_RXEQ_FAIL[1]; 00612 pseudo_bit_t IB_SERDES_TRIM_DONE[1]; 00613 pseudo_bit_t IBRxLaneReversed[1]; 00614 pseudo_bit_t IBTxLaneReversed[1]; 00615 pseudo_bit_t Reserved[16]; 00616 pseudo_bit_t TxReady[1]; 00617 pseudo_bit_t TxCreditOk[1]; 00618 pseudo_bit_t _unused_0[32]; 00619 }; 00620 struct QIB_7220_IBCStatus { 00621 PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCStatus_pb ); 00622 }; 00623 00624 #define QIB_7220_IBCCtrl_offset 0x000000c8UL 00625 struct QIB_7220_IBCCtrl_pb { 00626 pseudo_bit_t FlowCtrlPeriod[8]; 00627 pseudo_bit_t FlowCtrlWaterMark[8]; 00628 pseudo_bit_t LinkInitCmd[3]; 00629 pseudo_bit_t LinkCmd[2]; 00630 pseudo_bit_t MaxPktLen[11]; 00631 pseudo_bit_t PhyerrThreshold[4]; 00632 pseudo_bit_t OverrunThreshold[4]; 00633 pseudo_bit_t CreditScale[3]; 00634 pseudo_bit_t Reserved[19]; 00635 pseudo_bit_t LinkDownDefaultState[1]; 00636 pseudo_bit_t Loopback[1]; 00637 }; 00638 struct QIB_7220_IBCCtrl { 00639 PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCCtrl_pb ); 00640 }; 00641 00642 #define QIB_7220_EXTStatus_offset 0x000000d0UL 00643 struct QIB_7220_EXTStatus_pb { 00644 pseudo_bit_t Reserved2[14]; 00645 pseudo_bit_t MemBISTEndTest[1]; 00646 pseudo_bit_t MemBISTDisabled[1]; 00647 pseudo_bit_t Reserved1[16]; 00648 pseudo_bit_t Reserved[16]; 00649 pseudo_bit_t GPIOIn[16]; 00650 }; 00651 struct QIB_7220_EXTStatus { 00652 PSEUDO_BIT_STRUCT ( struct QIB_7220_EXTStatus_pb ); 00653 }; 00654 00655 #define QIB_7220_EXTCtrl_offset 0x000000d8UL 00656 struct QIB_7220_EXTCtrl_pb { 00657 pseudo_bit_t LEDGblErrRedOff[1]; 00658 pseudo_bit_t LEDGblOkGreenOn[1]; 00659 pseudo_bit_t LEDPriPortYellowOn[1]; 00660 pseudo_bit_t LEDPriPortGreenOn[1]; 00661 pseudo_bit_t Reserved[28]; 00662 pseudo_bit_t GPIOInvert[16]; 00663 pseudo_bit_t GPIOOe[16]; 00664 }; 00665 struct QIB_7220_EXTCtrl { 00666 PSEUDO_BIT_STRUCT ( struct QIB_7220_EXTCtrl_pb ); 00667 }; 00668 00669 #define QIB_7220_GPIOOut_offset 0x000000e0UL 00670 00671 #define QIB_7220_GPIOMask_offset 0x000000e8UL 00672 00673 #define QIB_7220_GPIOStatus_offset 0x000000f0UL 00674 00675 #define QIB_7220_GPIOClear_offset 0x000000f8UL 00676 00677 #define QIB_7220_RcvCtrl_offset 0x00000100UL 00678 struct QIB_7220_RcvCtrl_pb { 00679 pseudo_bit_t PortEnable[17]; 00680 pseudo_bit_t IntrAvail[17]; 00681 pseudo_bit_t RcvPartitionKeyDisable[1]; 00682 pseudo_bit_t TailUpd[1]; 00683 pseudo_bit_t PortCfg[2]; 00684 pseudo_bit_t RcvQPMapEnable[1]; 00685 pseudo_bit_t Reserved[25]; 00686 }; 00687 struct QIB_7220_RcvCtrl { 00688 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvCtrl_pb ); 00689 }; 00690 00691 #define QIB_7220_RcvBTHQP_offset 0x00000108UL 00692 struct QIB_7220_RcvBTHQP_pb { 00693 pseudo_bit_t RcvBTHQP[24]; 00694 pseudo_bit_t Reserved[8]; 00695 pseudo_bit_t _unused_0[32]; 00696 }; 00697 struct QIB_7220_RcvBTHQP { 00698 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvBTHQP_pb ); 00699 }; 00700 00701 #define QIB_7220_RcvHdrSize_offset 0x00000110UL 00702 00703 #define QIB_7220_RcvHdrCnt_offset 0x00000118UL 00704 00705 #define QIB_7220_RcvHdrEntSize_offset 0x00000120UL 00706 00707 #define QIB_7220_RcvTIDBase_offset 0x00000128UL 00708 00709 #define QIB_7220_RcvTIDCnt_offset 0x00000130UL 00710 00711 #define QIB_7220_RcvEgrBase_offset 0x00000138UL 00712 00713 #define QIB_7220_RcvEgrCnt_offset 0x00000140UL 00714 00715 #define QIB_7220_RcvBufBase_offset 0x00000148UL 00716 00717 #define QIB_7220_RcvBufSize_offset 0x00000150UL 00718 00719 #define QIB_7220_RxIntMemBase_offset 0x00000158UL 00720 00721 #define QIB_7220_RxIntMemSize_offset 0x00000160UL 00722 00723 #define QIB_7220_RcvPartitionKey_offset 0x00000168UL 00724 00725 #define QIB_7220_RcvQPMulticastPort_offset 0x00000170UL 00726 struct QIB_7220_RcvQPMulticastPort_pb { 00727 pseudo_bit_t RcvQpMcPort[5]; 00728 pseudo_bit_t Reserved[59]; 00729 }; 00730 struct QIB_7220_RcvQPMulticastPort { 00731 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvQPMulticastPort_pb ); 00732 }; 00733 00734 #define QIB_7220_RcvPktLEDCnt_offset 0x00000178UL 00735 struct QIB_7220_RcvPktLEDCnt_pb { 00736 pseudo_bit_t OFFperiod[32]; 00737 pseudo_bit_t ONperiod[32]; 00738 }; 00739 struct QIB_7220_RcvPktLEDCnt { 00740 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvPktLEDCnt_pb ); 00741 }; 00742 00743 #define QIB_7220_IBCDDRCtrl_offset 0x00000180UL 00744 struct QIB_7220_IBCDDRCtrl_pb { 00745 pseudo_bit_t IB_ENHANCED_MODE[1]; 00746 pseudo_bit_t SD_SPEED[1]; 00747 pseudo_bit_t SD_SPEED_SDR[1]; 00748 pseudo_bit_t SD_SPEED_DDR[1]; 00749 pseudo_bit_t SD_SPEED_QDR[1]; 00750 pseudo_bit_t IB_NUM_CHANNELS[2]; 00751 pseudo_bit_t IB_POLARITY_REV_SUPP[1]; 00752 pseudo_bit_t IB_LANE_REV_SUPPORTED[1]; 00753 pseudo_bit_t SD_RX_EQUAL_ENABLE[1]; 00754 pseudo_bit_t SD_ADD_ENB[1]; 00755 pseudo_bit_t SD_DDSV[1]; 00756 pseudo_bit_t SD_DDS[4]; 00757 pseudo_bit_t HRTBT_ENB[1]; 00758 pseudo_bit_t HRTBT_AUTO[1]; 00759 pseudo_bit_t HRTBT_PORT[8]; 00760 pseudo_bit_t HRTBT_REQ[1]; 00761 pseudo_bit_t Reserved[5]; 00762 pseudo_bit_t IB_DLID[16]; 00763 pseudo_bit_t IB_DLID_MASK[16]; 00764 }; 00765 struct QIB_7220_IBCDDRCtrl { 00766 PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRCtrl_pb ); 00767 }; 00768 00769 #define QIB_7220_HRTBT_GUID_offset 0x00000188UL 00770 00771 #define QIB_7220_IB_SDTEST_IF_TX_offset 0x00000190UL 00772 struct QIB_7220_IB_SDTEST_IF_TX_pb { 00773 pseudo_bit_t TS_T_TX_VALID[1]; 00774 pseudo_bit_t TS_3_TX_VALID[1]; 00775 pseudo_bit_t Reserved1[9]; 00776 pseudo_bit_t TS_TX_OPCODE[2]; 00777 pseudo_bit_t TS_TX_SPEED[3]; 00778 pseudo_bit_t Reserved[16]; 00779 pseudo_bit_t TS_TX_TX_CFG[16]; 00780 pseudo_bit_t TS_TX_RX_CFG[16]; 00781 }; 00782 struct QIB_7220_IB_SDTEST_IF_TX { 00783 PSEUDO_BIT_STRUCT ( struct QIB_7220_IB_SDTEST_IF_TX_pb ); 00784 }; 00785 00786 #define QIB_7220_IB_SDTEST_IF_RX_offset 0x00000198UL 00787 struct QIB_7220_IB_SDTEST_IF_RX_pb { 00788 pseudo_bit_t TS_T_RX_VALID[1]; 00789 pseudo_bit_t TS_3_RX_VALID[1]; 00790 pseudo_bit_t Reserved[14]; 00791 pseudo_bit_t TS_RX_A[8]; 00792 pseudo_bit_t TS_RX_B[8]; 00793 pseudo_bit_t TS_RX_TX_CFG[16]; 00794 pseudo_bit_t TS_RX_RX_CFG[16]; 00795 }; 00796 struct QIB_7220_IB_SDTEST_IF_RX { 00797 PSEUDO_BIT_STRUCT ( struct QIB_7220_IB_SDTEST_IF_RX_pb ); 00798 }; 00799 00800 #define QIB_7220_IBCDDRCtrl2_offset 0x000001a0UL 00801 struct QIB_7220_IBCDDRCtrl2_pb { 00802 pseudo_bit_t IB_FRONT_PORCH[5]; 00803 pseudo_bit_t IB_BACK_PORCH[5]; 00804 pseudo_bit_t _unused_0[54]; 00805 }; 00806 struct QIB_7220_IBCDDRCtrl2 { 00807 PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRCtrl2_pb ); 00808 }; 00809 00810 #define QIB_7220_IBCDDRStatus_offset 0x000001a8UL 00811 struct QIB_7220_IBCDDRStatus_pb { 00812 pseudo_bit_t LinkRoundTripLatency[26]; 00813 pseudo_bit_t ReqDDSLocalFromRmt[4]; 00814 pseudo_bit_t RxEqLocalDevice[2]; 00815 pseudo_bit_t heartbeat_crosstalk[4]; 00816 pseudo_bit_t heartbeat_timed_out[1]; 00817 pseudo_bit_t _unused_0[27]; 00818 }; 00819 struct QIB_7220_IBCDDRStatus { 00820 PSEUDO_BIT_STRUCT ( struct QIB_7220_IBCDDRStatus_pb ); 00821 }; 00822 00823 #define QIB_7220_JIntReload_offset 0x000001b0UL 00824 struct QIB_7220_JIntReload_pb { 00825 pseudo_bit_t J_reload[16]; 00826 pseudo_bit_t J_limit_reload[16]; 00827 pseudo_bit_t _unused_0[32]; 00828 }; 00829 struct QIB_7220_JIntReload { 00830 PSEUDO_BIT_STRUCT ( struct QIB_7220_JIntReload_pb ); 00831 }; 00832 00833 #define QIB_7220_IBNCModeCtrl_offset 0x000001b8UL 00834 struct QIB_7220_IBNCModeCtrl_pb { 00835 pseudo_bit_t TSMEnable_send_TS1[1]; 00836 pseudo_bit_t TSMEnable_send_TS2[1]; 00837 pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1]; 00838 pseudo_bit_t Reserved1[5]; 00839 pseudo_bit_t TSMCode_TS1[9]; 00840 pseudo_bit_t TSMCode_TS2[9]; 00841 pseudo_bit_t Reserved[38]; 00842 }; 00843 struct QIB_7220_IBNCModeCtrl { 00844 PSEUDO_BIT_STRUCT ( struct QIB_7220_IBNCModeCtrl_pb ); 00845 }; 00846 00847 #define QIB_7220_SendCtrl_offset 0x000001c0UL 00848 struct QIB_7220_SendCtrl_pb { 00849 pseudo_bit_t Abort[1]; 00850 pseudo_bit_t SendIntBufAvail[1]; 00851 pseudo_bit_t SendBufAvailUpd[1]; 00852 pseudo_bit_t SPioEnable[1]; 00853 pseudo_bit_t SSpecialTriggerEn[1]; 00854 pseudo_bit_t Reserved2[4]; 00855 pseudo_bit_t SDmaIntEnable[1]; 00856 pseudo_bit_t SDmaSingleDescriptor[1]; 00857 pseudo_bit_t SDmaEnable[1]; 00858 pseudo_bit_t SDmaHalt[1]; 00859 pseudo_bit_t Reserved1[3]; 00860 pseudo_bit_t DisarmPIOBuf[8]; 00861 pseudo_bit_t AvailUpdThld[5]; 00862 pseudo_bit_t Reserved[2]; 00863 pseudo_bit_t Disarm[1]; 00864 pseudo_bit_t _unused_0[32]; 00865 }; 00866 struct QIB_7220_SendCtrl { 00867 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendCtrl_pb ); 00868 }; 00869 00870 #define QIB_7220_SendBufBase_offset 0x000001c8UL 00871 struct QIB_7220_SendBufBase_pb { 00872 pseudo_bit_t BaseAddr_SmallPIO[21]; 00873 pseudo_bit_t Reserved1[11]; 00874 pseudo_bit_t BaseAddr_LargePIO[21]; 00875 pseudo_bit_t Reserved[11]; 00876 }; 00877 struct QIB_7220_SendBufBase { 00878 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufBase_pb ); 00879 }; 00880 00881 #define QIB_7220_SendBufSize_offset 0x000001d0UL 00882 struct QIB_7220_SendBufSize_pb { 00883 pseudo_bit_t Size_SmallPIO[12]; 00884 pseudo_bit_t Reserved1[20]; 00885 pseudo_bit_t Size_LargePIO[13]; 00886 pseudo_bit_t Reserved[19]; 00887 }; 00888 struct QIB_7220_SendBufSize { 00889 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufSize_pb ); 00890 }; 00891 00892 #define QIB_7220_SendBufCnt_offset 0x000001d8UL 00893 struct QIB_7220_SendBufCnt_pb { 00894 pseudo_bit_t Num_SmallBuffers[9]; 00895 pseudo_bit_t Reserved1[23]; 00896 pseudo_bit_t Num_LargeBuffers[4]; 00897 pseudo_bit_t Reserved[28]; 00898 }; 00899 struct QIB_7220_SendBufCnt { 00900 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufCnt_pb ); 00901 }; 00902 00903 #define QIB_7220_SendBufAvailAddr_offset 0x000001e0UL 00904 struct QIB_7220_SendBufAvailAddr_pb { 00905 pseudo_bit_t Reserved[6]; 00906 pseudo_bit_t SendBufAvailAddr[34]; 00907 pseudo_bit_t _unused_0[24]; 00908 }; 00909 struct QIB_7220_SendBufAvailAddr { 00910 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvailAddr_pb ); 00911 }; 00912 00913 #define QIB_7220_TxIntMemBase_offset 0x000001e8UL 00914 00915 #define QIB_7220_TxIntMemSize_offset 0x000001f0UL 00916 00917 #define QIB_7220_SendDmaBase_offset 0x000001f8UL 00918 struct QIB_7220_SendDmaBase_pb { 00919 pseudo_bit_t SendDmaBase[48]; 00920 pseudo_bit_t Reserved[16]; 00921 }; 00922 struct QIB_7220_SendDmaBase { 00923 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBase_pb ); 00924 }; 00925 00926 #define QIB_7220_SendDmaLenGen_offset 0x00000200UL 00927 struct QIB_7220_SendDmaLenGen_pb { 00928 pseudo_bit_t Length[16]; 00929 pseudo_bit_t Generation[3]; 00930 pseudo_bit_t Reserved[45]; 00931 }; 00932 struct QIB_7220_SendDmaLenGen { 00933 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaLenGen_pb ); 00934 }; 00935 00936 #define QIB_7220_SendDmaTail_offset 0x00000208UL 00937 struct QIB_7220_SendDmaTail_pb { 00938 pseudo_bit_t SendDmaTail[16]; 00939 pseudo_bit_t Reserved[48]; 00940 }; 00941 struct QIB_7220_SendDmaTail { 00942 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaTail_pb ); 00943 }; 00944 00945 #define QIB_7220_SendDmaHead_offset 0x00000210UL 00946 struct QIB_7220_SendDmaHead_pb { 00947 pseudo_bit_t SendDmaHead[16]; 00948 pseudo_bit_t Reserved1[16]; 00949 pseudo_bit_t InternalSendDmaHead[16]; 00950 pseudo_bit_t Reserved[16]; 00951 }; 00952 struct QIB_7220_SendDmaHead { 00953 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaHead_pb ); 00954 }; 00955 00956 #define QIB_7220_SendDmaHeadAddr_offset 0x00000218UL 00957 struct QIB_7220_SendDmaHeadAddr_pb { 00958 pseudo_bit_t SendDmaHeadAddr[48]; 00959 pseudo_bit_t Reserved[16]; 00960 }; 00961 struct QIB_7220_SendDmaHeadAddr { 00962 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaHeadAddr_pb ); 00963 }; 00964 00965 #define QIB_7220_SendDmaBufMask0_offset 0x00000220UL 00966 struct QIB_7220_SendDmaBufMask0_pb { 00967 pseudo_bit_t BufMask_63_0[0]; 00968 pseudo_bit_t _unused_0[64]; 00969 }; 00970 struct QIB_7220_SendDmaBufMask0 { 00971 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBufMask0_pb ); 00972 }; 00973 00974 #define QIB_7220_SendDmaStatus_offset 0x00000238UL 00975 struct QIB_7220_SendDmaStatus_pb { 00976 pseudo_bit_t SplFifoDescIndex[16]; 00977 pseudo_bit_t SplFifoBufNum[8]; 00978 pseudo_bit_t SplFifoFull[1]; 00979 pseudo_bit_t SplFifoEmpty[1]; 00980 pseudo_bit_t SplFifoDisarmed[1]; 00981 pseudo_bit_t SplFifoReadyToGo[1]; 00982 pseudo_bit_t ScbFetchDescFlag[1]; 00983 pseudo_bit_t ScbEntryValid[1]; 00984 pseudo_bit_t ScbEmpty[1]; 00985 pseudo_bit_t ScbFull[1]; 00986 pseudo_bit_t RpyTag_7_0[8]; 00987 pseudo_bit_t RpyLowAddr_6_0[7]; 00988 pseudo_bit_t ScbDescIndex_13_0[14]; 00989 pseudo_bit_t InternalSDmaEnable[1]; 00990 pseudo_bit_t AbortInProg[1]; 00991 pseudo_bit_t ScoreBoardDrainInProg[1]; 00992 }; 00993 struct QIB_7220_SendDmaStatus { 00994 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaStatus_pb ); 00995 }; 00996 00997 #define QIB_7220_SendBufErr0_offset 0x00000240UL 00998 struct QIB_7220_SendBufErr0_pb { 00999 pseudo_bit_t SendBufErr_63_0[0]; 01000 pseudo_bit_t _unused_0[64]; 01001 }; 01002 struct QIB_7220_SendBufErr0 { 01003 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufErr0_pb ); 01004 }; 01005 01006 #define QIB_7220_REG_000258_offset 0x00000258UL 01007 01008 #define QIB_7220_AvailUpdCount_offset 0x00000268UL 01009 struct QIB_7220_AvailUpdCount_pb { 01010 pseudo_bit_t AvailUpdCount[5]; 01011 pseudo_bit_t _unused_0[59]; 01012 }; 01013 struct QIB_7220_AvailUpdCount { 01014 PSEUDO_BIT_STRUCT ( struct QIB_7220_AvailUpdCount_pb ); 01015 }; 01016 01017 #define QIB_7220_RcvHdrAddr0_offset 0x00000270UL 01018 struct QIB_7220_RcvHdrAddr0_pb { 01019 pseudo_bit_t Reserved[2]; 01020 pseudo_bit_t RcvHdrAddr0[38]; 01021 pseudo_bit_t _unused_0[24]; 01022 }; 01023 struct QIB_7220_RcvHdrAddr0 { 01024 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrAddr0_pb ); 01025 }; 01026 01027 #define QIB_7220_REG_0002F8_offset 0x000002f8UL 01028 01029 #define QIB_7220_RcvHdrTailAddr0_offset 0x00000300UL 01030 struct QIB_7220_RcvHdrTailAddr0_pb { 01031 pseudo_bit_t Reserved[2]; 01032 pseudo_bit_t RcvHdrTailAddr0[38]; 01033 pseudo_bit_t _unused_0[24]; 01034 }; 01035 struct QIB_7220_RcvHdrTailAddr0 { 01036 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrTailAddr0_pb ); 01037 }; 01038 01039 #define QIB_7220_REG_000388_offset 0x00000388UL 01040 01041 #define QIB_7220_ibsd_epb_access_ctrl_offset 0x000003c0UL 01042 struct QIB_7220_ibsd_epb_access_ctrl_pb { 01043 pseudo_bit_t sw_ib_epb_req[1]; 01044 pseudo_bit_t Reserved[7]; 01045 pseudo_bit_t sw_ib_epb_req_granted[1]; 01046 pseudo_bit_t _unused_0[55]; 01047 }; 01048 struct QIB_7220_ibsd_epb_access_ctrl { 01049 PSEUDO_BIT_STRUCT ( struct QIB_7220_ibsd_epb_access_ctrl_pb ); 01050 }; 01051 01052 #define QIB_7220_ibsd_epb_transaction_reg_offset 0x000003c8UL 01053 struct QIB_7220_ibsd_epb_transaction_reg_pb { 01054 pseudo_bit_t ib_epb_data[8]; 01055 pseudo_bit_t ib_epb_address[15]; 01056 pseudo_bit_t Reserved2[1]; 01057 pseudo_bit_t ib_epb_read_write[1]; 01058 pseudo_bit_t ib_epb_cs[2]; 01059 pseudo_bit_t Reserved1[1]; 01060 pseudo_bit_t mem_data_parity[1]; 01061 pseudo_bit_t Reserved[1]; 01062 pseudo_bit_t ib_epb_req_error[1]; 01063 pseudo_bit_t ib_epb_rdy[1]; 01064 pseudo_bit_t _unused_0[32]; 01065 }; 01066 struct QIB_7220_ibsd_epb_transaction_reg { 01067 PSEUDO_BIT_STRUCT ( struct QIB_7220_ibsd_epb_transaction_reg_pb ); 01068 }; 01069 01070 #define QIB_7220_REG_0003D0_offset 0x000003d0UL 01071 01072 #define QIB_7220_XGXSCfg_offset 0x000003d8UL 01073 struct QIB_7220_XGXSCfg_pb { 01074 pseudo_bit_t tx_rx_reset[1]; 01075 pseudo_bit_t Reserved2[1]; 01076 pseudo_bit_t xcv_reset[1]; 01077 pseudo_bit_t Reserved1[6]; 01078 pseudo_bit_t link_sync_mask[10]; 01079 pseudo_bit_t Reserved[44]; 01080 pseudo_bit_t sel_link_down_for_fctrl_lane_sync_reset[1]; 01081 }; 01082 struct QIB_7220_XGXSCfg { 01083 PSEUDO_BIT_STRUCT ( struct QIB_7220_XGXSCfg_pb ); 01084 }; 01085 01086 #define QIB_7220_IBSerDesCtrl_offset 0x000003e0UL 01087 struct QIB_7220_IBSerDesCtrl_pb { 01088 pseudo_bit_t ResetIB_uC_Core[1]; 01089 pseudo_bit_t Reserved2[7]; 01090 pseudo_bit_t NumSerDesRegsToWrForDDS[5]; 01091 pseudo_bit_t NumSerDesRegsToWrForRXEQ[5]; 01092 pseudo_bit_t Reserved1[14]; 01093 pseudo_bit_t TXINV[1]; 01094 pseudo_bit_t RXINV[1]; 01095 pseudo_bit_t RXIDLE[1]; 01096 pseudo_bit_t TWC[1]; 01097 pseudo_bit_t TXOBPD[1]; 01098 pseudo_bit_t PLLM[3]; 01099 pseudo_bit_t PLLN[2]; 01100 pseudo_bit_t CKSEL_uC[2]; 01101 pseudo_bit_t INT_uC[1]; 01102 pseudo_bit_t Reserved[19]; 01103 }; 01104 struct QIB_7220_IBSerDesCtrl { 01105 PSEUDO_BIT_STRUCT ( struct QIB_7220_IBSerDesCtrl_pb ); 01106 }; 01107 01108 #define QIB_7220_EEPCtlStat_offset 0x000003e8UL 01109 struct QIB_7220_EEPCtlStat_pb { 01110 pseudo_bit_t EPAccEn[2]; 01111 pseudo_bit_t EPReset[1]; 01112 pseudo_bit_t ByteProg[1]; 01113 pseudo_bit_t PageMode[1]; 01114 pseudo_bit_t LstDatWr[1]; 01115 pseudo_bit_t CmdWrErr[1]; 01116 pseudo_bit_t Reserved[24]; 01117 pseudo_bit_t CtlrStat[1]; 01118 pseudo_bit_t _unused_0[32]; 01119 }; 01120 struct QIB_7220_EEPCtlStat { 01121 PSEUDO_BIT_STRUCT ( struct QIB_7220_EEPCtlStat_pb ); 01122 }; 01123 01124 #define QIB_7220_EEPAddrCmd_offset 0x000003f0UL 01125 struct QIB_7220_EEPAddrCmd_pb { 01126 pseudo_bit_t EPAddr[24]; 01127 pseudo_bit_t EPCmd[8]; 01128 pseudo_bit_t _unused_0[32]; 01129 }; 01130 struct QIB_7220_EEPAddrCmd { 01131 PSEUDO_BIT_STRUCT ( struct QIB_7220_EEPAddrCmd_pb ); 01132 }; 01133 01134 #define QIB_7220_EEPData_offset 0x000003f8UL 01135 01136 #define QIB_7220_pciesd_epb_access_ctrl_offset 0x00000400UL 01137 struct QIB_7220_pciesd_epb_access_ctrl_pb { 01138 pseudo_bit_t sw_pcie_epb_req[1]; 01139 pseudo_bit_t sw_pcieepb_star_en[2]; 01140 pseudo_bit_t Reserved[5]; 01141 pseudo_bit_t sw_pcie_epb_req_granted[1]; 01142 pseudo_bit_t _unused_0[55]; 01143 }; 01144 struct QIB_7220_pciesd_epb_access_ctrl { 01145 PSEUDO_BIT_STRUCT ( struct QIB_7220_pciesd_epb_access_ctrl_pb ); 01146 }; 01147 01148 #define QIB_7220_pciesd_epb_transaction_reg_offset 0x00000408UL 01149 struct QIB_7220_pciesd_epb_transaction_reg_pb { 01150 pseudo_bit_t pcie_epb_data[8]; 01151 pseudo_bit_t pcie_epb_address[15]; 01152 pseudo_bit_t Reserved1[1]; 01153 pseudo_bit_t pcie_epb_read_write[1]; 01154 pseudo_bit_t pcie_epb_cs[3]; 01155 pseudo_bit_t mem_data_parity[1]; 01156 pseudo_bit_t Reserved[1]; 01157 pseudo_bit_t pcie_epb_req_error[1]; 01158 pseudo_bit_t pcie_epb_rdy[1]; 01159 pseudo_bit_t _unused_0[32]; 01160 }; 01161 struct QIB_7220_pciesd_epb_transaction_reg { 01162 PSEUDO_BIT_STRUCT ( struct QIB_7220_pciesd_epb_transaction_reg_pb ); 01163 }; 01164 01165 #define QIB_7220_efuse_control_reg_offset 0x00000410UL 01166 struct QIB_7220_efuse_control_reg_pb { 01167 pseudo_bit_t start_op[1]; 01168 pseudo_bit_t operation[1]; 01169 pseudo_bit_t read_valid[1]; 01170 pseudo_bit_t req_error[1]; 01171 pseudo_bit_t Reserved[27]; 01172 pseudo_bit_t rdy[1]; 01173 pseudo_bit_t _unused_0[32]; 01174 }; 01175 struct QIB_7220_efuse_control_reg { 01176 PSEUDO_BIT_STRUCT ( struct QIB_7220_efuse_control_reg_pb ); 01177 }; 01178 01179 #define QIB_7220_efuse_rddata0_reg_offset 0x00000418UL 01180 01181 #define QIB_7220_procmon_register_offset 0x00000438UL 01182 struct QIB_7220_procmon_register_pb { 01183 pseudo_bit_t interval_time[12]; 01184 pseudo_bit_t Reserved1[2]; 01185 pseudo_bit_t clear_counter[1]; 01186 pseudo_bit_t start_counter[1]; 01187 pseudo_bit_t procmon_count[9]; 01188 pseudo_bit_t Reserved[6]; 01189 pseudo_bit_t procmon_count_valid[1]; 01190 pseudo_bit_t _unused_0[32]; 01191 }; 01192 struct QIB_7220_procmon_register { 01193 PSEUDO_BIT_STRUCT ( struct QIB_7220_procmon_register_pb ); 01194 }; 01195 01196 #define QIB_7220_PcieRbufTestReg0_offset 0x00000440UL 01197 01198 #define QIB_7220_PcieRBufTestReg1_offset 0x00000448UL 01199 01200 #define QIB_7220_SPC_JTAG_ACCESS_REG_offset 0x00000460UL 01201 struct QIB_7220_SPC_JTAG_ACCESS_REG_pb { 01202 pseudo_bit_t rdy[1]; 01203 pseudo_bit_t tdo[1]; 01204 pseudo_bit_t tdi[1]; 01205 pseudo_bit_t opcode[2]; 01206 pseudo_bit_t bist_en[5]; 01207 pseudo_bit_t SPC_JTAG_ACCESS_EN[1]; 01208 pseudo_bit_t _unused_0[53]; 01209 }; 01210 struct QIB_7220_SPC_JTAG_ACCESS_REG { 01211 PSEUDO_BIT_STRUCT ( struct QIB_7220_SPC_JTAG_ACCESS_REG_pb ); 01212 }; 01213 01214 #define QIB_7220_LAControlReg_offset 0x00000468UL 01215 struct QIB_7220_LAControlReg_pb { 01216 pseudo_bit_t Finished[1]; 01217 pseudo_bit_t Address[8]; 01218 pseudo_bit_t Mode[2]; 01219 pseudo_bit_t Delay[20]; 01220 pseudo_bit_t Reserved[1]; 01221 pseudo_bit_t _unused_0[32]; 01222 }; 01223 struct QIB_7220_LAControlReg { 01224 PSEUDO_BIT_STRUCT ( struct QIB_7220_LAControlReg_pb ); 01225 }; 01226 01227 #define QIB_7220_GPIODebugSelReg_offset 0x00000470UL 01228 struct QIB_7220_GPIODebugSelReg_pb { 01229 pseudo_bit_t GPIOSourceSelDebug[16]; 01230 pseudo_bit_t SelPulse[16]; 01231 pseudo_bit_t _unused_0[32]; 01232 }; 01233 struct QIB_7220_GPIODebugSelReg { 01234 PSEUDO_BIT_STRUCT ( struct QIB_7220_GPIODebugSelReg_pb ); 01235 }; 01236 01237 #define QIB_7220_DebugPortValueReg_offset 0x00000478UL 01238 01239 #define QIB_7220_SendDmaBufUsed0_offset 0x00000480UL 01240 struct QIB_7220_SendDmaBufUsed0_pb { 01241 pseudo_bit_t BufUsed_63_0[0]; 01242 pseudo_bit_t _unused_0[64]; 01243 }; 01244 struct QIB_7220_SendDmaBufUsed0 { 01245 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaBufUsed0_pb ); 01246 }; 01247 01248 #define QIB_7220_SendDmaReqTagUsed_offset 0x00000498UL 01249 struct QIB_7220_SendDmaReqTagUsed_pb { 01250 pseudo_bit_t ReqTagUsed_7_0[8]; 01251 pseudo_bit_t _unused_0[8]; 01252 pseudo_bit_t Reserved[48]; 01253 }; 01254 struct QIB_7220_SendDmaReqTagUsed { 01255 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendDmaReqTagUsed_pb ); 01256 }; 01257 01258 #define QIB_7220_efuse_pgm_data0_offset 0x000004a0UL 01259 01260 #define QIB_7220_MEM_0004B0_offset 0x000004b0UL 01261 01262 #define QIB_7220_SerDes_DDSRXEQ0_offset 0x00000500UL 01263 struct QIB_7220_SerDes_DDSRXEQ0_pb { 01264 pseudo_bit_t element_num[4]; 01265 pseudo_bit_t reg_addr[6]; 01266 pseudo_bit_t _unused_0[54]; 01267 }; 01268 struct QIB_7220_SerDes_DDSRXEQ0 { 01269 PSEUDO_BIT_STRUCT ( struct QIB_7220_SerDes_DDSRXEQ0_pb ); 01270 }; 01271 01272 #define QIB_7220_MEM_0005F0_offset 0x000005f0UL 01273 01274 #define QIB_7220_LAMemory_offset 0x00000600UL 01275 01276 #define QIB_7220_MEM_0007F0_offset 0x000007f0UL 01277 01278 #define QIB_7220_SendBufAvail0_offset 0x00001000UL 01279 struct QIB_7220_SendBufAvail0_pb { 01280 pseudo_bit_t SendBuf_31_0[0]; 01281 pseudo_bit_t _unused_0[64]; 01282 }; 01283 struct QIB_7220_SendBufAvail0 { 01284 PSEUDO_BIT_STRUCT ( struct QIB_7220_SendBufAvail0_pb ); 01285 }; 01286 01287 #define QIB_7220_MEM_001028_offset 0x00001028UL 01288 01289 #define QIB_7220_LBIntCnt_offset 0x00013000UL 01290 01291 #define QIB_7220_LBFlowStallCnt_offset 0x00013008UL 01292 01293 #define QIB_7220_TxSDmaDescCnt_offset 0x00013010UL 01294 01295 #define QIB_7220_TxUnsupVLErrCnt_offset 0x00013018UL 01296 01297 #define QIB_7220_TxDataPktCnt_offset 0x00013020UL 01298 01299 #define QIB_7220_TxFlowPktCnt_offset 0x00013028UL 01300 01301 #define QIB_7220_TxDwordCnt_offset 0x00013030UL 01302 01303 #define QIB_7220_TxLenErrCnt_offset 0x00013038UL 01304 01305 #define QIB_7220_TxMaxMinLenErrCnt_offset 0x00013040UL 01306 01307 #define QIB_7220_TxUnderrunCnt_offset 0x00013048UL 01308 01309 #define QIB_7220_TxFlowStallCnt_offset 0x00013050UL 01310 01311 #define QIB_7220_TxDroppedPktCnt_offset 0x00013058UL 01312 01313 #define QIB_7220_RxDroppedPktCnt_offset 0x00013060UL 01314 01315 #define QIB_7220_RxDataPktCnt_offset 0x00013068UL 01316 01317 #define QIB_7220_RxFlowPktCnt_offset 0x00013070UL 01318 01319 #define QIB_7220_RxDwordCnt_offset 0x00013078UL 01320 01321 #define QIB_7220_RxLenErrCnt_offset 0x00013080UL 01322 01323 #define QIB_7220_RxMaxMinLenErrCnt_offset 0x00013088UL 01324 01325 #define QIB_7220_RxICRCErrCnt_offset 0x00013090UL 01326 01327 #define QIB_7220_RxVCRCErrCnt_offset 0x00013098UL 01328 01329 #define QIB_7220_RxFlowCtrlViolCnt_offset 0x000130a0UL 01330 01331 #define QIB_7220_RxVersionErrCnt_offset 0x000130a8UL 01332 01333 #define QIB_7220_RxLinkMalformCnt_offset 0x000130b0UL 01334 01335 #define QIB_7220_RxEBPCnt_offset 0x000130b8UL 01336 01337 #define QIB_7220_RxLPCRCErrCnt_offset 0x000130c0UL 01338 01339 #define QIB_7220_RxBufOvflCnt_offset 0x000130c8UL 01340 01341 #define QIB_7220_RxTIDFullErrCnt_offset 0x000130d0UL 01342 01343 #define QIB_7220_RxTIDValidErrCnt_offset 0x000130d8UL 01344 01345 #define QIB_7220_RxPKeyMismatchCnt_offset 0x000130e0UL 01346 01347 #define QIB_7220_RxP0HdrEgrOvflCnt_offset 0x000130e8UL 01348 01349 #define QIB_7220_IBStatusChangeCnt_offset 0x00013170UL 01350 01351 #define QIB_7220_IBLinkErrRecoveryCnt_offset 0x00013178UL 01352 01353 #define QIB_7220_IBLinkDownedCnt_offset 0x00013180UL 01354 01355 #define QIB_7220_IBSymbolErrCnt_offset 0x00013188UL 01356 01357 #define QIB_7220_RxVL15DroppedPktCnt_offset 0x00013190UL 01358 01359 #define QIB_7220_RxOtherLocalPhyErrCnt_offset 0x00013198UL 01360 01361 #define QIB_7220_PcieRetryBufDiagQwordCnt_offset 0x000131a0UL 01362 01363 #define QIB_7220_ExcessBufferOvflCnt_offset 0x000131a8UL 01364 01365 #define QIB_7220_LocalLinkIntegrityErrCnt_offset 0x000131b0UL 01366 01367 #define QIB_7220_RxVlErrCnt_offset 0x000131b8UL 01368 01369 #define QIB_7220_RxDlidFltrCnt_offset 0x000131c0UL 01370 01371 #define QIB_7220_CNT_0131C8_offset 0x000131c8UL 01372 01373 #define QIB_7220_PSStat_offset 0x00013200UL 01374 01375 #define QIB_7220_PSStart_offset 0x00013208UL 01376 01377 #define QIB_7220_PSInterval_offset 0x00013210UL 01378 01379 #define QIB_7220_PSRcvDataCount_offset 0x00013218UL 01380 01381 #define QIB_7220_PSRcvPktsCount_offset 0x00013220UL 01382 01383 #define QIB_7220_PSXmitDataCount_offset 0x00013228UL 01384 01385 #define QIB_7220_PSXmitPktsCount_offset 0x00013230UL 01386 01387 #define QIB_7220_PSXmitWaitCount_offset 0x00013238UL 01388 01389 #define QIB_7220_CNT_013240_offset 0x00013240UL 01390 01391 #define QIB_7220_RcvEgrArray_offset 0x00014000UL 01392 01393 #define QIB_7220_MEM_038000_offset 0x00038000UL 01394 01395 #define QIB_7220_RcvTIDArray0_offset 0x00053000UL 01396 01397 #define QIB_7220_PIOLaunchFIFO_offset 0x00064000UL 01398 01399 #define QIB_7220_MEM_064480_offset 0x00064480UL 01400 01401 #define QIB_7220_SendPIOpbcCache_offset 0x00064800UL 01402 01403 #define QIB_7220_MEM_064C80_offset 0x00064c80UL 01404 01405 #define QIB_7220_PreLaunchFIFO_offset 0x00065000UL 01406 01407 #define QIB_7220_MEM_065080_offset 0x00065080UL 01408 01409 #define QIB_7220_ScoreBoard_offset 0x00065400UL 01410 01411 #define QIB_7220_MEM_065440_offset 0x00065440UL 01412 01413 #define QIB_7220_DescriptorFIFO_offset 0x00065800UL 01414 01415 #define QIB_7220_MEM_065880_offset 0x00065880UL 01416 01417 #define QIB_7220_RcvBuf1_offset 0x00072000UL 01418 01419 #define QIB_7220_MEM_074800_offset 0x00074800UL 01420 01421 #define QIB_7220_RcvBuf2_offset 0x00075000UL 01422 01423 #define QIB_7220_MEM_076400_offset 0x00076400UL 01424 01425 #define QIB_7220_RcvFlags_offset 0x00077000UL 01426 01427 #define QIB_7220_MEM_078400_offset 0x00078400UL 01428 01429 #define QIB_7220_RcvLookupBuf1_offset 0x00079000UL 01430 01431 #define QIB_7220_MEM_07A400_offset 0x0007a400UL 01432 01433 #define QIB_7220_RcvDMADatBuf_offset 0x0007b000UL 01434 01435 #define QIB_7220_RcvDMAHdrBuf_offset 0x0007b800UL 01436 01437 #define QIB_7220_MiscRXEIntMem_offset 0x0007c000UL 01438 01439 #define QIB_7220_MEM_07D400_offset 0x0007d400UL 01440 01441 #define QIB_7220_PCIERcvBuf_offset 0x00080000UL 01442 01443 #define QIB_7220_PCIERetryBuf_offset 0x00084000UL 01444 01445 #define QIB_7220_PCIERcvBufRdToWrAddr_offset 0x00088000UL 01446 01447 #define QIB_7220_PCIECplBuf_offset 0x00090000UL 01448 01449 #define QIB_7220_IBSerDesMappTable_offset 0x00094000UL 01450 01451 #define QIB_7220_MEM_095000_offset 0x00095000UL 01452 01453 #define QIB_7220_SendBuf0_MA_offset 0x00100000UL 01454 01455 #define QIB_7220_MEM_1A0000_offset 0x001a0000UL 01456 01457 #define QIB_7220_RcvHdrTail0_offset 0x00200000UL 01458 01459 #define QIB_7220_RcvHdrHead0_offset 0x00200008UL 01460 struct QIB_7220_RcvHdrHead0_pb { 01461 pseudo_bit_t RcvHeadPointer[32]; 01462 pseudo_bit_t counter[16]; 01463 pseudo_bit_t Reserved[16]; 01464 }; 01465 struct QIB_7220_RcvHdrHead0 { 01466 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead0_pb ); 01467 }; 01468 01469 #define QIB_7220_RcvEgrIndexTail0_offset 0x00200010UL 01470 01471 #define QIB_7220_RcvEgrIndexHead0_offset 0x00200018UL 01472 01473 #define QIB_7220_MEM_200020_offset 0x00200020UL 01474 01475 #define QIB_7220_RcvHdrTail1_offset 0x00210000UL 01476 01477 #define QIB_7220_RcvHdrHead1_offset 0x00210008UL 01478 struct QIB_7220_RcvHdrHead1_pb { 01479 pseudo_bit_t RcvHeadPointer[32]; 01480 pseudo_bit_t counter[16]; 01481 pseudo_bit_t Reserved[16]; 01482 }; 01483 struct QIB_7220_RcvHdrHead1 { 01484 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead1_pb ); 01485 }; 01486 01487 #define QIB_7220_RcvEgrIndexTail1_offset 0x00210010UL 01488 01489 #define QIB_7220_RcvEgrIndexHead1_offset 0x00210018UL 01490 01491 #define QIB_7220_MEM_210020_offset 0x00210020UL 01492 01493 #define QIB_7220_RcvHdrTail2_offset 0x00220000UL 01494 01495 #define QIB_7220_RcvHdrHead2_offset 0x00220008UL 01496 struct QIB_7220_RcvHdrHead2_pb { 01497 pseudo_bit_t RcvHeadPointer[32]; 01498 pseudo_bit_t counter[16]; 01499 pseudo_bit_t Reserved[16]; 01500 }; 01501 struct QIB_7220_RcvHdrHead2 { 01502 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead2_pb ); 01503 }; 01504 01505 #define QIB_7220_RcvEgrIndexTail2_offset 0x00220010UL 01506 01507 #define QIB_7220_RcvEgrIndexHead2_offset 0x00220018UL 01508 01509 #define QIB_7220_MEM_220020_offset 0x00220020UL 01510 01511 #define QIB_7220_RcvHdrTail3_offset 0x00230000UL 01512 01513 #define QIB_7220_RcvHdrHead3_offset 0x00230008UL 01514 struct QIB_7220_RcvHdrHead3_pb { 01515 pseudo_bit_t RcvHeadPointer[32]; 01516 pseudo_bit_t counter[16]; 01517 pseudo_bit_t Reserved[16]; 01518 }; 01519 struct QIB_7220_RcvHdrHead3 { 01520 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead3_pb ); 01521 }; 01522 01523 #define QIB_7220_RcvEgrIndexTail3_offset 0x00230010UL 01524 01525 #define QIB_7220_RcvEgrIndexHead3_offset 0x00230018UL 01526 01527 #define QIB_7220_MEM_230020_offset 0x00230020UL 01528 01529 #define QIB_7220_RcvHdrTail4_offset 0x00240000UL 01530 01531 #define QIB_7220_RcvHdrHead4_offset 0x00240008UL 01532 struct QIB_7220_RcvHdrHead4_pb { 01533 pseudo_bit_t RcvHeadPointer[32]; 01534 pseudo_bit_t counter[16]; 01535 pseudo_bit_t Reserved[16]; 01536 }; 01537 struct QIB_7220_RcvHdrHead4 { 01538 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead4_pb ); 01539 }; 01540 01541 #define QIB_7220_RcvEgrIndexTail4_offset 0x00240010UL 01542 01543 #define QIB_7220_RcvEgrIndexHead4_offset 0x00240018UL 01544 01545 #define QIB_7220_MEM_240020_offset 0x00240020UL 01546 01547 #define QIB_7220_RcvHdrTail5_offset 0x00250000UL 01548 01549 #define QIB_7220_RcvHdrHead5_offset 0x00250008UL 01550 struct QIB_7220_RcvHdrHead5_pb { 01551 pseudo_bit_t RcvHeadPointer[32]; 01552 pseudo_bit_t counter[16]; 01553 pseudo_bit_t Reserved[16]; 01554 }; 01555 struct QIB_7220_RcvHdrHead5 { 01556 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead5_pb ); 01557 }; 01558 01559 #define QIB_7220_RcvEgrIndexTail5_offset 0x00250010UL 01560 01561 #define QIB_7220_RcvEgrIndexHead5_offset 0x00250018UL 01562 01563 #define QIB_7220_MEM_250020_offset 0x00250020UL 01564 01565 #define QIB_7220_RcvHdrTail6_offset 0x00260000UL 01566 01567 #define QIB_7220_RcvHdrHead6_offset 0x00260008UL 01568 struct QIB_7220_RcvHdrHead6_pb { 01569 pseudo_bit_t RcvHeadPointer[32]; 01570 pseudo_bit_t counter[16]; 01571 pseudo_bit_t Reserved[16]; 01572 }; 01573 struct QIB_7220_RcvHdrHead6 { 01574 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead6_pb ); 01575 }; 01576 01577 #define QIB_7220_RcvEgrIndexTail6_offset 0x00260010UL 01578 01579 #define QIB_7220_RcvEgrIndexHead6_offset 0x00260018UL 01580 01581 #define QIB_7220_MEM_260020_offset 0x00260020UL 01582 01583 #define QIB_7220_RcvHdrTail7_offset 0x00270000UL 01584 01585 #define QIB_7220_RcvHdrHead7_offset 0x00270008UL 01586 struct QIB_7220_RcvHdrHead7_pb { 01587 pseudo_bit_t RcvHeadPointer[32]; 01588 pseudo_bit_t counter[16]; 01589 pseudo_bit_t Reserved[16]; 01590 }; 01591 struct QIB_7220_RcvHdrHead7 { 01592 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead7_pb ); 01593 }; 01594 01595 #define QIB_7220_RcvEgrIndexTail7_offset 0x00270010UL 01596 01597 #define QIB_7220_RcvEgrIndexHead7_offset 0x00270018UL 01598 01599 #define QIB_7220_MEM_270020_offset 0x00270020UL 01600 01601 #define QIB_7220_RcvHdrTail8_offset 0x00280000UL 01602 01603 #define QIB_7220_RcvHdrHead8_offset 0x00280008UL 01604 struct QIB_7220_RcvHdrHead8_pb { 01605 pseudo_bit_t RcvHeadPointer[32]; 01606 pseudo_bit_t counter[16]; 01607 pseudo_bit_t Reserved[16]; 01608 }; 01609 struct QIB_7220_RcvHdrHead8 { 01610 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead8_pb ); 01611 }; 01612 01613 #define QIB_7220_RcvEgrIndexTail8_offset 0x00280010UL 01614 01615 #define QIB_7220_RcvEgrIndexHead8_offset 0x00280018UL 01616 01617 #define QIB_7220_MEM_280020_offset 0x00280020UL 01618 01619 #define QIB_7220_RcvHdrTail9_offset 0x00290000UL 01620 01621 #define QIB_7220_RcvHdrHead9_offset 0x00290008UL 01622 struct QIB_7220_RcvHdrHead9_pb { 01623 pseudo_bit_t RcvHeadPointer[32]; 01624 pseudo_bit_t counter[16]; 01625 pseudo_bit_t Reserved[16]; 01626 }; 01627 struct QIB_7220_RcvHdrHead9 { 01628 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead9_pb ); 01629 }; 01630 01631 #define QIB_7220_RcvEgrIndexTail9_offset 0x00290010UL 01632 01633 #define QIB_7220_RcvEgrIndexHead9_offset 0x00290018UL 01634 01635 #define QIB_7220_MEM_290020_offset 0x00290020UL 01636 01637 #define QIB_7220_RcvHdrTail10_offset 0x002a0000UL 01638 01639 #define QIB_7220_RcvHdrHead10_offset 0x002a0008UL 01640 struct QIB_7220_RcvHdrHead10_pb { 01641 pseudo_bit_t RcvHeadPointer[32]; 01642 pseudo_bit_t counter[16]; 01643 pseudo_bit_t Reserved[16]; 01644 }; 01645 struct QIB_7220_RcvHdrHead10 { 01646 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead10_pb ); 01647 }; 01648 01649 #define QIB_7220_RcvEgrIndexTail10_offset 0x002a0010UL 01650 01651 #define QIB_7220_RcvEgrIndexHead10_offset 0x002a0018UL 01652 01653 #define QIB_7220_MEM_2A0020_offset 0x002a0020UL 01654 01655 #define QIB_7220_RcvHdrTail11_offset 0x002b0000UL 01656 01657 #define QIB_7220_RcvHdrHead11_offset 0x002b0008UL 01658 struct QIB_7220_RcvHdrHead11_pb { 01659 pseudo_bit_t RcvHeadPointer[32]; 01660 pseudo_bit_t counter[16]; 01661 pseudo_bit_t Reserved[16]; 01662 }; 01663 struct QIB_7220_RcvHdrHead11 { 01664 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead11_pb ); 01665 }; 01666 01667 #define QIB_7220_RcvEgrIndexTail11_offset 0x002b0010UL 01668 01669 #define QIB_7220_RcvEgrIndexHead11_offset 0x002b0018UL 01670 01671 #define QIB_7220_MEM_2B0020_offset 0x002b0020UL 01672 01673 #define QIB_7220_RcvHdrTail12_offset 0x002c0000UL 01674 01675 #define QIB_7220_RcvHdrHead12_offset 0x002c0008UL 01676 struct QIB_7220_RcvHdrHead12_pb { 01677 pseudo_bit_t RcvHeadPointer[32]; 01678 pseudo_bit_t counter[16]; 01679 pseudo_bit_t Reserved[16]; 01680 }; 01681 struct QIB_7220_RcvHdrHead12 { 01682 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead12_pb ); 01683 }; 01684 01685 #define QIB_7220_RcvEgrIndexTail12_offset 0x002c0010UL 01686 01687 #define QIB_7220_RcvEgrIndexHead12_offset 0x002c0018UL 01688 01689 #define QIB_7220_MEM_2C0020_offset 0x002c0020UL 01690 01691 #define QIB_7220_RcvHdrTail13_offset 0x002d0000UL 01692 01693 #define QIB_7220_RcvHdrHead13_offset 0x002d0008UL 01694 struct QIB_7220_RcvHdrHead13_pb { 01695 pseudo_bit_t RcvHeadPointer[32]; 01696 pseudo_bit_t counter[16]; 01697 pseudo_bit_t Reserved[16]; 01698 }; 01699 struct QIB_7220_RcvHdrHead13 { 01700 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead13_pb ); 01701 }; 01702 01703 #define QIB_7220_RcvEgrIndexTail13_offset 0x002d0010UL 01704 01705 #define QIB_7220_RcvEgrIndexHead13_offset 0x002d0018UL 01706 01707 #define QIB_7220_MEM_2D0020_offset 0x002d0020UL 01708 01709 #define QIB_7220_RcvHdrTail14_offset 0x002e0000UL 01710 01711 #define QIB_7220_RcvHdrHead14_offset 0x002e0008UL 01712 struct QIB_7220_RcvHdrHead14_pb { 01713 pseudo_bit_t RcvHeadPointer[32]; 01714 pseudo_bit_t counter[16]; 01715 pseudo_bit_t Reserved[16]; 01716 }; 01717 struct QIB_7220_RcvHdrHead14 { 01718 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead14_pb ); 01719 }; 01720 01721 #define QIB_7220_RcvEgrIndexTail14_offset 0x002e0010UL 01722 01723 #define QIB_7220_RcvEgrIndexHead14_offset 0x002e0018UL 01724 01725 #define QIB_7220_MEM_2E0020_offset 0x002e0020UL 01726 01727 #define QIB_7220_RcvHdrTail15_offset 0x002f0000UL 01728 01729 #define QIB_7220_RcvHdrHead15_offset 0x002f0008UL 01730 struct QIB_7220_RcvHdrHead15_pb { 01731 pseudo_bit_t RcvHeadPointer[32]; 01732 pseudo_bit_t counter[16]; 01733 pseudo_bit_t Reserved[16]; 01734 }; 01735 struct QIB_7220_RcvHdrHead15 { 01736 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead15_pb ); 01737 }; 01738 01739 #define QIB_7220_RcvEgrIndexTail15_offset 0x002f0010UL 01740 01741 #define QIB_7220_RcvEgrIndexHead15_offset 0x002f0018UL 01742 01743 #define QIB_7220_MEM_2F0020_offset 0x002f0020UL 01744 01745 #define QIB_7220_RcvHdrTail16_offset 0x00300000UL 01746 01747 #define QIB_7220_RcvHdrHead16_offset 0x00300008UL 01748 struct QIB_7220_RcvHdrHead16_pb { 01749 pseudo_bit_t RcvHeadPointer[32]; 01750 pseudo_bit_t counter[16]; 01751 pseudo_bit_t Reserved[16]; 01752 }; 01753 struct QIB_7220_RcvHdrHead16 { 01754 PSEUDO_BIT_STRUCT ( struct QIB_7220_RcvHdrHead16_pb ); 01755 }; 01756 01757 #define QIB_7220_RcvEgrIndexTail16_offset 0x00300010UL 01758 01759 #define QIB_7220_RcvEgrIndexHead16_offset 0x00300018UL 01760 01761 #define QIB_7220_MEM_300020_offset 0x00300020UL 01762
1.5.7.1