#include <stdint.h>#include <gpxe/device.h>#include <gpxe/tables.h>#include <gpxe/pci_io.h>#include "pci_ids.h"Go to the source code of this file.
| #define PCI_COMMAND_IO 0x1 |
| #define PCI_COMMAND_MEM 0x2 |
Definition at line 33 of file pci.h.
Referenced by adjust_pci_device(), atl1e_reset_hw(), and atl1e_setup_pcicmd().
| #define PCI_COMMAND_MASTER 0x4 |
Definition at line 34 of file pci.h.
Referenced by adjust_pci_device(), atl1e_reset_hw(), and atl1e_setup_pcicmd().
| #define PCI_CACHE_LINE_SIZE 0x0c |
Definition at line 36 of file pci.h.
Referenced by ath5k_probe(), rtl8169_init_phy(), and rtl_hw_start_8169().
| #define PCI_LATENCY_TIMER 0x0d |
Definition at line 37 of file pci.h.
Referenced by adjust_pci_device(), ath5k_probe(), rtl8169_init_phy(), and tg3_get_invariants().
| #define PCI_COMMAND_INVALIDATE 0x10 |
| #define PCI_COMMAND_PARITY 0x40 |
| #define PCI_COMMAND_SERR 0x100 |
| #define PCI_COMMAND_INTX_DISABLE 0x400 |
| #define PCI_VENDOR_ID 0x00 |
| #define PCI_COMMAND 0x04 |
Definition at line 51 of file pci.h.
Referenced by __vxge_hw_device_pci_e_init(), adjust_pci_device(), atl1e_reset_hw(), atl1e_setup_pcicmd(), bnx2_init_board(), e1000_pci_clear_mwi(), e1000_pci_set_mwi(), e1000_sw_init(), igb_sw_init(), myri10ge_net_irq(), pci_bar_size(), tg3_chip_reset(), and tg3_get_invariants().
| #define PCI_STATUS 0x06 |
Definition at line 53 of file pci.h.
Referenced by pci_find_capability(), skge_reset(), sky2_hw_intr(), and sky2_reset().
| #define PCI_STATUS_CAP_LIST 0x10 |
| #define PCI_REVISION 0x08 |
Definition at line 69 of file pci.h.
Referenced by pcibus_probe(), rhine_probe1(), sis900_probe(), and tulip_probe().
| #define PCI_REVISION_ID 0x08 |
Definition at line 70 of file pci.h.
Referenced by atl1e_sw_init(), dmfe_probe(), e1000_sw_init(), igb_sw_init(), sundance_probe(), velocity_get_pci_info(), and vxge_probe().
| #define PCI_CLASS_REVISION 0x08 |
| #define PCI_HEADER_TYPE 0x0e |
| #define PCI_HEADER_TYPE_NORMAL 0 |
| #define PCI_HEADER_TYPE_BRIDGE 1 |
| #define PCI_HEADER_TYPE_CARDBUS 2 |
| #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
| #define PCI_SUBSYSTEM_ID 0x2e |
| #define PCI_BASE_ADDRESS_0 0x10 |
Definition at line 85 of file pci.h.
Referenced by amd8111e_probe(), bnx2_init_board(), dmfe_probe(), e1000_probe(), e1000e_probe(), forcedeth_probe(), igb_probe(), mtnic_init_pci(), pci_read_bases(), phantom_map_crb(), skge_probe(), sky2_probe(), tg3_probe(), velocity_get_pci_info(), and vxge_probe().
| #define PCI_BASE_ADDRESS_1 0x14 |
Definition at line 86 of file pci.h.
Referenced by e1000e_probe(), ns83820_probe(), and velocity_get_pci_info().
| #define PCI_BASE_ADDRESS_2 0x18 |
| #define PCI_BASE_ADDRESS_5 0x24 |
| #define PCI_BASE_ADDRESS_MEM_MASK (~0x0f) |
Definition at line 100 of file pci.h.
Referenced by pci_bar_size(), pci_bar_start(), pci_read_bases(), and pci_resource_flags().
| #define PCI_BASE_ADDRESS_IO_MASK (~0x03) |
Definition at line 101 of file pci.h.
Referenced by pci_bar_size(), pci_bar_start(), pci_read_bases(), pci_resource_flags(), and prism2_find_plx().
| #define PCI_ROM_ADDRESS 0x30 |
| #define PCI_CAPABILITY_LIST 0x34 |
| #define PCI_INTERRUPT_LINE 0x3c |
| #define PCI_CB_CAPABILITY_LIST 0x14 |
| #define PCI_CAP_LIST_ID 0 |
| #define PCI_CAP_ID_PM 0x01 |
Definition at line 156 of file pci.h.
Referenced by bnx2_init_board(), pci_set_power_state(), and tg3_probe().
| #define PCI_CAP_LIST_NEXT 1 |
| #define PCI_PM_PMC 2 |
| #define PCI_PM_CAP_D1 0x0200 |
| #define PCI_PM_CAP_D2 0x0400 |
| #define PCI_PM_CTRL 4 |
Definition at line 184 of file pci.h.
Referenced by bnx2_set_power_state_0(), pci_set_power_state(), and tg3_set_power_state_0().
| #define PCI_PM_CTRL_STATE_MASK 0x0003 |
Definition at line 185 of file pci.h.
Referenced by bnx2_set_power_state_0(), pci_set_power_state(), and tg3_set_power_state_0().
| #define PCI_PM_CTRL_PME_STATUS 0x8000 |
Definition at line 189 of file pci.h.
Referenced by bnx2_set_power_state_0(), and tg3_set_power_state_0().
| #define PCI_ERR_UNCOR_STATUS 4 |
| #define PCI_ANY_ID 0xffff |
| #define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" ) |
struct pci_driver sis190_pci_driver __pci_driver __table_entry ( PCI_DRIVERS, 01 ) [read] |
| #define PCI_DEVFN | ( | slot, | |||
| func | ) | ( ( (slot) << 3 ) | (func) ) |
| #define PCI_SLOT | ( | devfn | ) | ( ( (devfn) >> 3 ) & 0x1f ) |
Definition at line 350 of file pci.h.
Referenced by adjust_pci_device(), efipci_address(), efipci_read(), efipci_write(), pci_probe(), pci_remove(), pcibus_probe(), phantom_map_crb(), phantom_probe(), pxenv_undi_get_nic_type(), undi_load(), and vxge_probe().
| #define PCI_FUNC | ( | devfn | ) | ( (devfn) & 0x07 ) |
Definition at line 351 of file pci.h.
Referenced by adjust_pci_device(), efipci_address(), efipci_read(), efipci_write(), pci_probe(), pci_remove(), pcibus_probe(), phantom_map_crb(), phantom_probe(), pxenv_undi_get_nic_type(), tg3_get_device_address(), undi_load(), and vxge_probe().
| #define PCI_BUS | ( | busdevfn | ) | ( (busdevfn) >> 8 ) |
| #define PCI_BUSDEVFN | ( | bus, | |||
| devfn | ) | ( ( (bus) << 8 ) | (devfn) ) |
Definition at line 353 of file pci.h.
Referenced by efi_snp_netdev(), pcibios_read(), pcibios_write(), pcibus_probe(), and undipci_probe().
| #define PCI_BASE_CLASS | ( | class | ) | ( (class) >> 16 ) |
| #define PCI_SUB_CLASS | ( | class | ) | ( ( (class) >> 8 ) & 0xff ) |
| #define PCI_PROG_INTF | ( | class | ) | ( (class) & 0xff ) |
| #define PCI_ID | ( | _vendor, | |||
| _device, | |||||
| _name, | |||||
| _description, | |||||
| _data | ) |
| #define PCI_ROM | ( | _vendor, | |||
| _device, | |||||
| _name, | |||||
| _description, | |||||
| _data | ) | PCI_ID( _vendor, _device, _name, _description, _data ) |
| FILE_LICENCE | ( | GPL2_ONLY | ) |
| void adjust_pci_device | ( | struct pci_device * | pci | ) |
Enable PCI device.
| pci | PCI device |
Definition at line 143 of file pci.c.
References pci_device::bus, DBG, pci_device::devfn, PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEM, PCI_FUNC, PCI_LATENCY_TIMER, pci_read_config_byte(), pci_read_config_word(), PCI_SLOT, pci_write_config_byte(), and pci_write_config_word().
Referenced by a3c90x_probe(), amd8111e_probe(), arbel_probe(), ath5k_probe(), atl1e_probe(), b44_probe(), bnx2_init_board(), dmfe_probe(), e1000_probe(), e1000e_probe(), efab_probe(), forcedeth_probe(), hermon_probe(), ifec_pci_probe(), igb_probe(), linda_probe(), mtd_probe(), mtnic_probe(), myri10ge_pci_probe(), natsemi_probe(), ns83820_probe(), pcnet32_probe(), phantom_probe(), pnic_probe(), rhine_probe(), rtl8169_probe(), rtl818x_probe(), rtl_probe(), sis190_init_board(), sis900_probe(), skge_probe(), sky2_probe(), sundance_probe(), tg3_probe(), tlan_probe(), tulip_probe(), velocity_get_pci_info(), virtnet_probe(), vxge_probe(), and w89c840_probe().
00143 { 00144 unsigned short new_command, pci_command; 00145 unsigned char pci_latency; 00146 00147 pci_read_config_word ( pci, PCI_COMMAND, &pci_command ); 00148 new_command = ( pci_command | PCI_COMMAND_MASTER | 00149 PCI_COMMAND_MEM | PCI_COMMAND_IO ); 00150 if ( pci_command != new_command ) { 00151 DBG ( "PCI BIOS has not enabled device %02x:%02x.%x! " 00152 "Updating PCI command %04x->%04x\n", pci->bus, 00153 PCI_SLOT ( pci->devfn ), PCI_FUNC ( pci->devfn ), 00154 pci_command, new_command ); 00155 pci_write_config_word ( pci, PCI_COMMAND, new_command ); 00156 } 00157 00158 pci_read_config_byte ( pci, PCI_LATENCY_TIMER, &pci_latency); 00159 if ( pci_latency < 32 ) { 00160 DBG ( "PCI device %02x:%02x.%x latency timer is unreasonably " 00161 "low at %d. Setting to 32.\n", pci->bus, 00162 PCI_SLOT ( pci->devfn ), PCI_FUNC ( pci->devfn ), 00163 pci_latency ); 00164 pci_write_config_byte ( pci, PCI_LATENCY_TIMER, 32); 00165 } 00166 }
| unsigned long pci_bar_start | ( | struct pci_device * | pci, | |
| unsigned int | reg | |||
| ) |
Find the start of a PCI BAR.
| pci | PCI device | |
| reg | PCI register number |
| start | BAR start address |
If the address exceeds the size of an unsigned long (i.e. if a 64-bit BAR has a non-zero high dword on a 32-bit machine), the return value will be zero.
Definition at line 90 of file pci.c.
References pci_bar(), PCI_BASE_ADDRESS_IO_MASK, PCI_BASE_ADDRESS_MEM_MASK, PCI_BASE_ADDRESS_SPACE, and PCI_BASE_ADDRESS_SPACE_MEMORY.
Referenced by amd8111e_probe(), arbel_probe(), bnx2_init_board(), dmfe_probe(), e1000_probe(), e1000e_probe(), efab_probe(), forcedeth_probe(), hermon_probe(), igb_probe(), mtnic_init_pci(), ns83820_probe(), phantom_map_crb(), skge_probe(), sky2_probe(), tg3_probe(), undipci_find_rom(), velocity_get_pci_info(), and vxge_probe().
00090 { 00091 unsigned long bar; 00092 00093 bar = pci_bar ( pci, reg ); 00094 if ( (bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY ){ 00095 return ( bar & PCI_BASE_ADDRESS_MEM_MASK ); 00096 } else { 00097 return ( bar & PCI_BASE_ADDRESS_IO_MASK ); 00098 } 00099 }
| int pci_find_capability | ( | struct pci_device * | pci, | |
| int | cap | |||
| ) |
Look for a PCI capability.
| pci | PCI device to query | |
| cap | Capability code |
| address | Address of capability, or 0 if not found |
Definition at line 18 of file pciextra.c.
References DBG, id, PCI_CAP_LIST_ID, PCI_CAP_LIST_NEXT, PCI_CAPABILITY_LIST, PCI_CB_CAPABILITY_LIST, PCI_HEADER_TYPE, PCI_HEADER_TYPE_BRIDGE, PCI_HEADER_TYPE_CARDBUS, PCI_HEADER_TYPE_NORMAL, pci_read_config_byte(), pci_read_config_word(), PCI_STATUS, and PCI_STATUS_CAP_LIST.
Referenced by ath5k_hw_attach(), ath5k_hw_nic_wakeup(), bnx2_init_board(), e1000_read_pcie_cap_reg(), e1000e_read_pcie_cap_reg(), igb_read_pcie_cap_reg(), igb_write_pcie_cap_reg(), mac_address_from_string_specs(), pci_set_power_state(), rtl8169_probe(), sky2_reset(), sky2_rx_start(), tg3_get_invariants(), and tg3_probe().
00018 { 00019 uint16_t status; 00020 uint8_t pos, id; 00021 uint8_t hdr_type; 00022 int ttl = 48; 00023 00024 pci_read_config_word ( pci, PCI_STATUS, &status ); 00025 if ( ! ( status & PCI_STATUS_CAP_LIST ) ) 00026 return 0; 00027 00028 pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type ); 00029 switch ( hdr_type & 0x7F ) { 00030 case PCI_HEADER_TYPE_NORMAL: 00031 case PCI_HEADER_TYPE_BRIDGE: 00032 default: 00033 pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos ); 00034 break; 00035 case PCI_HEADER_TYPE_CARDBUS: 00036 pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos ); 00037 break; 00038 } 00039 while ( ttl-- && pos >= 0x40 ) { 00040 pos &= ~3; 00041 pci_read_config_byte ( pci, pos + PCI_CAP_LIST_ID, &id ); 00042 DBG ( "PCI Capability: %d\n", id ); 00043 if ( id == 0xff ) 00044 break; 00045 if ( id == cap ) 00046 return pos; 00047 pci_read_config_byte ( pci, pos + PCI_CAP_LIST_NEXT, &pos ); 00048 } 00049 return 0; 00050 }
| unsigned long pci_bar_size | ( | struct pci_device * | pci, | |
| unsigned int | reg | |||
| ) |
Find the size of a PCI BAR.
| pci | PCI device | |
| reg | PCI register number |
| size | BAR size |
Definition at line 62 of file pciextra.c.
References PCI_BASE_ADDRESS_IO_MASK, PCI_BASE_ADDRESS_MEM_MASK, PCI_BASE_ADDRESS_SPACE_IO, PCI_COMMAND, pci_read_config_dword(), pci_read_config_word(), pci_write_config_dword(), pci_write_config_word(), and size.
Referenced by amd8111e_probe(), e1000_probe(), e1000e_probe(), efab_probe(), forcedeth_probe(), igb_probe(), phantom_map_crb(), tg3_probe(), velocity_get_pci_info(), and vxge_probe().
00062 { 00063 uint16_t cmd; 00064 uint32_t start, size; 00065 00066 /* Save the original command register */ 00067 pci_read_config_word ( pci, PCI_COMMAND, &cmd ); 00068 /* Save the original bar */ 00069 pci_read_config_dword ( pci, reg, &start ); 00070 /* Compute which bits can be set */ 00071 pci_write_config_dword ( pci, reg, ~0 ); 00072 pci_read_config_dword ( pci, reg, &size ); 00073 /* Restore the original size */ 00074 pci_write_config_dword ( pci, reg, start ); 00075 /* Find the significant bits */ 00076 /* Restore the original command register. This reenables decoding. */ 00077 pci_write_config_word ( pci, PCI_COMMAND, cmd ); 00078 if ( start & PCI_BASE_ADDRESS_SPACE_IO ) { 00079 size &= PCI_BASE_ADDRESS_IO_MASK; 00080 } else { 00081 size &= PCI_BASE_ADDRESS_MEM_MASK; 00082 } 00083 /* Find the lowest bit set */ 00084 size = size & ~( size - 1 ); 00085 return size; 00086 }
| static void pci_set_drvdata | ( | struct pci_device * | pci, | |
| void * | priv | |||
| ) | [inline, static] |
Set PCI driver-private data.
| pci | PCI device | |
| priv | Private data |
Definition at line 388 of file pci.h.
References pci_device::priv.
Referenced by a3c90x_probe(), arbel_probe(), ath5k_probe(), atl1e_init_netdev(), b44_probe(), e1000_probe(), e1000e_probe(), efab_probe(), hermon_probe(), ifec_pci_probe(), igb_probe(), legacy_pci_set_drvdata(), linda_probe(), mtnic_probe(), myri10ge_pci_probe(), natsemi_probe(), phantom_probe(), pnic_probe(), rtl8169_probe(), rtl818x_probe(), rtl_probe(), sis190_probe(), skge_probe(), skge_remove(), sky2_probe(), sky2_remove(), undipci_probe(), undipci_remove(), vxge_probe(), and vxge_remove().
| static void* pci_get_drvdata | ( | struct pci_device * | pci | ) | [inline, static] |
Get PCI driver-private data.
| pci | PCI device |
| priv | Private data |
Definition at line 398 of file pci.h.
References pci_device::priv.
Referenced by a3c90x_remove(), arbel_remove(), ath5k_remove(), atl1e_remove(), b44_remove(), e1000_remove(), e1000e_remove(), efab_remove(), hermon_remove(), ifec_pci_remove(), igb_remove(), legacy_pci_get_drvdata(), linda_remove(), mtnic_disable(), myri10ge_pci_remove(), natsemi_remove(), phantom_remove(), pnic_remove(), rtl8169_remove(), rtl818x_remove(), rtl_disable_clock_request(), rtl_remove(), rtl_tx_performance_tweak(), sis190_remove(), skge_remove(), sky2_remove(), undipci_remove(), vxge_close(), vxge_irq(), vxge_open(), vxge_open_vpaths(), vxge_poll(), vxge_remove(), and vxge_xmit().
00398 { 00399 return pci->priv; 00400 }
1.5.7.1