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Data Structures | |
| struct | ringbuffer |
Defines | |
| #define | VENDOR_NONE 0 |
| #define | VENDOR_WD 1 |
| #define | VENDOR_NOVELL 2 |
| #define | VENDOR_3COM 3 |
| #define | FLAG_PIO 0x01 |
| #define | FLAG_16BIT 0x02 |
| #define | FLAG_790 0x04 |
| #define | MEM_8192 32 |
| #define | MEM_16384 64 |
| #define | MEM_32768 128 |
| #define | ISA_MAX_ADDR 0x400 |
| #define | WD_LOW_BASE 0x200 |
| #define | WD_HIGH_BASE 0x3e0 |
| #define | WD_DEFAULT_MEM 0xD0000 |
| #define | WD_NIC_ADDR 0x10 |
| #define | WD_MSR 0x00 |
| #define | WD_ICR 0x01 |
| #define | WD_IAR 0x02 |
| #define | WD_BIO 0x03 |
| #define | WD_IRR 0x04 |
| #define | WD_LAAR 0x05 |
| #define | WD_IJR 0x06 |
| #define | WD_GP2 0x07 |
| #define | WD_LAR 0x08 |
| #define | WD_BID 0x0E |
| #define | WD_ICR_16BIT 0x01 |
| #define | WD_MSR_MENB 0x40 |
| #define | WD_LAAR_L16EN 0x40 |
| #define | WD_LAAR_M16EN 0x80 |
| #define | WD_SOFTCONFIG 0x20 |
| #define | TYPE_WD8003S 0x02 |
| #define | TYPE_WD8003E 0x03 |
| #define | TYPE_WD8013EBT 0x05 |
| #define | TYPE_WD8003W 0x24 |
| #define | TYPE_WD8003EB 0x25 |
| #define | TYPE_WD8013W 0x26 |
| #define | TYPE_WD8013EP 0x27 |
| #define | TYPE_WD8013WC 0x28 |
| #define | TYPE_WD8013EPC 0x29 |
| #define | TYPE_SMC8216T 0x2a |
| #define | TYPE_SMC8216C 0x2b |
| #define | TYPE_SMC8416T 0x00 |
| #define | TYPE_SMC8416C 0x00 |
| #define | TYPE_SMC8013EBP 0x2c |
| #define | _3COM_BASE 0x300 |
| #define | _3COM_TX_PAGE_OFFSET_8BIT 0x20 |
| #define | _3COM_TX_PAGE_OFFSET_16BIT 0x0 |
| #define | _3COM_RX_PAGE_OFFSET_16BIT 0x20 |
| #define | _3COM_ASIC_OFFSET 0x400 |
| #define | _3COM_NIC_OFFSET 0x0 |
| #define | _3COM_PSTR 0 |
| #define | _3COM_PSPR 1 |
| #define | _3COM_BCFR 3 |
| #define | _3COM_BCFR_2E0 0x01 |
| #define | _3COM_BCFR_2A0 0x02 |
| #define | _3COM_BCFR_280 0x04 |
| #define | _3COM_BCFR_250 0x08 |
| #define | _3COM_BCFR_350 0x10 |
| #define | _3COM_BCFR_330 0x20 |
| #define | _3COM_BCFR_310 0x40 |
| #define | _3COM_BCFR_300 0x80 |
| #define | _3COM_PCFR 4 |
| #define | _3COM_PCFR_PIO 0 |
| #define | _3COM_PCFR_C8000 0x10 |
| #define | _3COM_PCFR_CC000 0x20 |
| #define | _3COM_PCFR_D8000 0x40 |
| #define | _3COM_PCFR_DC000 0x80 |
| #define | _3COM_CR 6 |
| #define | _3COM_CR_RST 0x01 |
| #define | _3COM_CR_XSEL 0x02 |
| #define | _3COM_CR_EALO 0x04 |
| #define | _3COM_CR_EAHI 0x08 |
| #define | _3COM_CR_SHARE 0x10 |
| #define | _3COM_CR_DBSEL 0x20 |
| #define | _3COM_CR_DDIR 0x40 |
| #define | _3COM_CR_START 0x80 |
| #define | _3COM_GACFR 5 |
| #define | _3COM_GACFR_MBS0 0x01 |
| #define | _3COM_GACFR_MBS1 0x02 |
| #define | _3COM_GACFR_MBS2 0x04 |
| #define | _3COM_GACFR_RSEL 0x08 |
| #define | _3COM_GACFR_TEST 0x10 |
| #define | _3COM_GACFR_OWS 0x20 |
| #define | _3COM_GACFR_TCM 0x40 |
| #define | _3COM_GACFR_NIM 0x80 |
| #define | _3COM_STREG 7 |
| #define | _3COM_STREG_REV 0x07 |
| #define | _3COM_STREG_DIP 0x08 |
| #define | _3COM_STREG_DTC 0x10 |
| #define | _3COM_STREG_OFLW 0x20 |
| #define | _3COM_STREG_UFLW 0x40 |
| #define | _3COM_STREG_DPRDY 0x80 |
| #define | _3COM_IDCFR 8 |
| #define | _3COM_IDCFR_DRQ0 0x01 |
| #define | _3COM_IDCFR_DRQ1 0x02 |
| #define | _3COM_IDCFR_DRQ2 0x04 |
| #define | _3COM_IDCFR_UNUSED 0x08 |
| #define | _3COM_IDCFR_IRQ2 0x10 |
| #define | _3COM_IDCFR_IRQ3 0x20 |
| #define | _3COM_IDCFR_IRQ4 0x40 |
| #define | _3COM_IDCFR_IRQ5 0x80 |
| #define | _3COM_IRQ2 2 |
| #define | _3COM_IRQ3 3 |
| #define | _3COM_IRQ4 4 |
| #define | _3COM_IRQ5 5 |
| #define | _3COM_DAMSB 9 |
| #define | _3COM_DALSB 0x0a |
| #define | _3COM_VPTR2 0x0b |
| #define | _3COM_VPTR1 0x0c |
| #define | _3COM_VPTR0 0x0d |
| #define | _3COM_RFMSB 0x0e |
| #define | _3COM_RFLSB 0x0f |
| #define | NE_ASIC_OFFSET 0x10 |
| #define | NE_RESET 0x0F |
| #define | NE_DATA 0x00 |
| #define | COMPEX_RL2000_TRIES 200 |
| #define | D8390_P0_COMMAND 0x00 |
| #define | D8390_P0_PSTART 0x01 |
| #define | D8390_P0_PSTOP 0x02 |
| #define | D8390_P0_BOUND 0x03 |
| #define | D8390_P0_TSR 0x04 |
| #define | D8390_P0_TPSR 0x04 |
| #define | D8390_P0_TBCR0 0x05 |
| #define | D8390_P0_TBCR1 0x06 |
| #define | D8390_P0_ISR 0x07 |
| #define | D8390_P0_RSAR0 0x08 |
| #define | D8390_P0_RSAR1 0x09 |
| #define | D8390_P0_RBCR0 0x0A |
| #define | D8390_P0_RBCR1 0x0B |
| #define | D8390_P0_RSR 0x0C |
| #define | D8390_P0_RCR 0x0C |
| #define | D8390_P0_TCR 0x0D |
| #define | D8390_P0_DCR 0x0E |
| #define | D8390_P0_IMR 0x0F |
| #define | D8390_P1_COMMAND 0x00 |
| #define | D8390_P1_PAR0 0x01 |
| #define | D8390_P1_PAR1 0x02 |
| #define | D8390_P1_PAR2 0x03 |
| #define | D8390_P1_PAR3 0x04 |
| #define | D8390_P1_PAR4 0x05 |
| #define | D8390_P1_PAR5 0x06 |
| #define | D8390_P1_CURR 0x07 |
| #define | D8390_P1_MAR0 0x08 |
| #define | D8390_COMMAND_PS0 0x0 |
| #define | D8390_COMMAND_PS1 0x40 |
| #define | D8390_COMMAND_PS2 0x80 |
| #define | D8390_COMMAND_RD2 0x20 |
| #define | D8390_COMMAND_RD1 0x10 |
| #define | D8390_COMMAND_RD0 0x08 |
| #define | D8390_COMMAND_TXP 0x04 |
| #define | D8390_COMMAND_STA 0x02 |
| #define | D8390_COMMAND_STP 0x01 |
| #define | D8390_RCR_MON 0x20 |
| #define | D8390_DCR_FT1 0x40 |
| #define | D8390_DCR_LS 0x08 |
| #define | D8390_DCR_WTS 0x01 |
| #define | D8390_ISR_PRX 0x01 |
| #define | D8390_ISR_PTX 0x02 |
| #define | D8390_ISR_RXE 0x04 |
| #define | D8390_ISR_TXE 0x08 |
| #define | D8390_ISR_OVW 0x10 |
| #define | D8390_ISR_CNT 0x20 |
| #define | D8390_ISR_RDC 0x40 |
| #define | D8390_ISR_RST 0x80 |
| #define | D8390_RSTAT_PRX 0x01 |
| #define | D8390_RSTAT_CRC 0x02 |
| #define | D8390_RSTAT_FAE 0x04 |
| #define | D8390_RSTAT_OVER 0x08 |
| #define | D8390_TXBUF_SIZE 6 |
| #define | D8390_RXBUF_END 32 |
| #define | D8390_PAGE_SIZE 256 |
Functions | |
| FILE_LICENCE (BSD2) | |
| #define VENDOR_NONE 0 |
| #define VENDOR_WD 1 |
| #define VENDOR_NOVELL 2 |
| #define VENDOR_3COM 3 |
| #define FLAG_PIO 0x01 |
Definition at line 16 of file ns8390.h.
Referenced by eth_probe(), ne_poll(), ne_probe(), ns8390_poll(), and ns8390_transmit().
| #define FLAG_16BIT 0x02 |
Definition at line 17 of file ns8390.h.
Referenced by eth_pio_read(), eth_pio_write(), eth_probe(), ne_probe(), ne_reset(), ns8390_poll(), ns8390_reset(), and ns8390_transmit().
| #define FLAG_790 0x04 |
Definition at line 18 of file ns8390.h.
Referenced by eth_probe(), eth_rx_overrun(), ns8390_poll(), ns8390_reset(), and ns8390_transmit().
| #define MEM_8192 32 |
| #define MEM_16384 64 |
| #define MEM_32768 128 |
| #define ISA_MAX_ADDR 0x400 |
| #define WD_LOW_BASE 0x200 |
| #define WD_HIGH_BASE 0x3e0 |
| #define WD_DEFAULT_MEM 0xD0000 |
| #define WD_NIC_ADDR 0x10 |
| #define WD_MSR 0x00 |
Definition at line 39 of file ns8390.h.
Referenced by eth_probe(), ns8390_poll(), and ns8390_transmit().
| #define WD_ICR 0x01 |
| #define WD_LAAR 0x05 |
Definition at line 44 of file ns8390.h.
Referenced by eth_probe(), ns8390_poll(), and ns8390_transmit().
| #define WD_GP2 0x07 |
| #define WD_LAR 0x08 |
| #define WD_BID 0x0E |
| #define WD_ICR_16BIT 0x01 |
| #define WD_MSR_MENB 0x40 |
Definition at line 52 of file ns8390.h.
Referenced by eth_probe(), ns8390_poll(), and ns8390_transmit().
| #define WD_LAAR_L16EN 0x40 |
| #define WD_LAAR_M16EN 0x80 |
Definition at line 55 of file ns8390.h.
Referenced by eth_probe(), ns8390_poll(), and ns8390_transmit().
| #define WD_SOFTCONFIG 0x20 |
| #define TYPE_WD8013EP 0x27 |
| #define TYPE_SMC8216T 0x2a |
| #define TYPE_SMC8216C 0x2b |
| #define _3COM_ASIC_OFFSET 0x400 |
| #define _3COM_PSTR 0 |
| #define _3COM_PSPR 1 |
| #define _3COM_BCFR 3 |
| #define _3COM_PCFR 4 |
| #define _3COM_PCFR_PIO 0 |
| #define _3COM_PCFR_C8000 0x10 |
| #define _3COM_PCFR_CC000 0x20 |
| #define _3COM_PCFR_D8000 0x40 |
| #define _3COM_PCFR_DC000 0x80 |
| #define _3COM_CR 6 |
Definition at line 110 of file ns8390.h.
Referenced by eth_pio_read(), eth_pio_write(), eth_probe(), and ns8390_reset().
| #define _3COM_CR_RST 0x01 |
| #define _3COM_CR_XSEL 0x02 |
| #define _3COM_CR_EALO 0x04 |
| #define _3COM_CR_DDIR 0x40 |
| #define _3COM_CR_START 0x80 |
| #define _3COM_GACFR 5 |
| #define _3COM_GACFR_MBS0 0x01 |
| #define _3COM_GACFR_RSEL 0x08 |
| #define _3COM_GACFR_TCM 0x40 |
| #define _3COM_GACFR_NIM 0x80 |
| #define _3COM_STREG 7 |
| #define _3COM_STREG_DPRDY 0x80 |
| #define _3COM_DAMSB 9 |
| #define _3COM_DALSB 0x0a |
| #define _3COM_VPTR2 0x0b |
| #define _3COM_VPTR1 0x0c |
| #define _3COM_VPTR0 0x0d |
| #define NE_ASIC_OFFSET 0x10 |
| #define NE_RESET 0x0F |
| #define COMPEX_RL2000_TRIES 200 |
| #define D8390_P0_COMMAND 0x00 |
Definition at line 168 of file ns8390.h.
Referenced by enable_multicast(), eth_pio_read(), eth_pio_write(), eth_probe(), eth_rx_overrun(), ne_poll(), ne_probe(), ne_reset(), ne_transmit(), ns8390_poll(), ns8390_reset(), and ns8390_transmit().
| #define D8390_P0_PSTART 0x01 |
Definition at line 169 of file ns8390.h.
Referenced by eth_probe(), ne_probe(), ne_reset(), and ns8390_reset().
| #define D8390_P0_PSTOP 0x02 |
Definition at line 170 of file ns8390.h.
Referenced by eth_probe(), ne_probe(), ne_reset(), and ns8390_reset().
| #define D8390_P0_BOUND 0x03 |
Definition at line 171 of file ns8390.h.
Referenced by ne_poll(), ne_reset(), ns8390_poll(), and ns8390_reset().
| #define D8390_P0_TPSR 0x04 |
Definition at line 173 of file ns8390.h.
Referenced by ne_reset(), ne_transmit(), ns8390_reset(), and ns8390_transmit().
| #define D8390_P0_TBCR0 0x05 |
| #define D8390_P0_TBCR1 0x06 |
| #define D8390_P0_ISR 0x07 |
Definition at line 176 of file ns8390.h.
Referenced by eth_pio_write(), eth_rx_overrun(), ne_reset(), ns8390_poll(), and ns8390_reset().
| #define D8390_P0_RSAR0 0x08 |
| #define D8390_P0_RSAR1 0x09 |
| #define D8390_P0_RBCR0 0x0A |
Definition at line 179 of file ns8390.h.
Referenced by eth_pio_read(), eth_pio_write(), eth_rx_overrun(), ne_reset(), and ns8390_reset().
| #define D8390_P0_RBCR1 0x0B |
Definition at line 180 of file ns8390.h.
Referenced by eth_pio_read(), eth_pio_write(), eth_rx_overrun(), ne_reset(), and ns8390_reset().
| #define D8390_P0_RSR 0x0C |
| #define D8390_P0_RCR 0x0C |
Definition at line 182 of file ns8390.h.
Referenced by enable_multicast(), eth_probe(), ne_probe(), ne_reset(), and ns8390_reset().
| #define D8390_P0_TCR 0x0D |
Definition at line 183 of file ns8390.h.
Referenced by eth_rx_overrun(), ne_probe1(), ne_reset(), and ns8390_reset().
| #define D8390_P0_DCR 0x0E |
Definition at line 184 of file ns8390.h.
Referenced by eth_probe(), ne_probe(), ne_reset(), and ns8390_reset().
| #define D8390_P0_IMR 0x0F |
| #define D8390_P1_PAR0 0x01 |
| #define D8390_P1_CURR 0x07 |
Definition at line 193 of file ns8390.h.
Referenced by ne_poll(), ne_reset(), ns8390_poll(), and ns8390_reset().
| #define D8390_P1_MAR0 0x08 |
| #define D8390_COMMAND_PS0 0x0 |
Definition at line 196 of file ns8390.h.
Referenced by enable_multicast(), eth_rx_overrun(), ne_poll(), ne_reset(), ne_transmit(), ns8390_poll(), ns8390_reset(), and ns8390_transmit().
| #define D8390_COMMAND_PS1 0x40 |
Definition at line 197 of file ns8390.h.
Referenced by enable_multicast(), ne_poll(), ne_probe1(), ne_reset(), ns8390_poll(), and ns8390_reset().
| #define D8390_COMMAND_RD2 0x20 |
Definition at line 199 of file ns8390.h.
Referenced by enable_multicast(), eth_pio_read(), eth_pio_write(), eth_probe(), eth_rx_overrun(), ne_probe(), ne_probe1(), ne_reset(), ne_transmit(), ns8390_reset(), and ns8390_transmit().
| #define D8390_COMMAND_RD1 0x10 |
| #define D8390_COMMAND_RD0 0x08 |
| #define D8390_COMMAND_TXP 0x04 |
| #define D8390_COMMAND_STA 0x02 |
Definition at line 203 of file ns8390.h.
Referenced by eth_pio_read(), eth_pio_write(), eth_rx_overrun(), ne_reset(), ne_transmit(), ns8390_reset(), and ns8390_transmit().
| #define D8390_COMMAND_STP 0x01 |
Definition at line 204 of file ns8390.h.
Referenced by eth_probe(), eth_rx_overrun(), ne_probe(), ne_probe1(), ne_reset(), and ns8390_reset().
| #define D8390_RCR_MON 0x20 |
| #define D8390_DCR_FT1 0x40 |
| #define D8390_DCR_LS 0x08 |
| #define D8390_DCR_WTS 0x01 |
| #define D8390_ISR_OVW 0x10 |
| #define D8390_ISR_RDC 0x40 |
| #define D8390_RSTAT_PRX 0x01 |
| #define D8390_TXBUF_SIZE 6 |
| FILE_LICENCE | ( | BSD2 | ) |
1.5.7.1