#include "etherboot.h"#include "nic.h"#include <gpxe/pci.h>Go to the source code of this file.
Data Structures | |
| struct | ring_desc |
| struct | ns83820_private |
Defines | |
| #define | USE_64BIT_ADDR |
| #define | dprintf(x) |
| #define | HZ 100 |
| #define | virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) |
| #define | le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) |
| #define | TRY_DAC 1 |
| #define | RX_BUF_SIZE 1500 |
| #define | NR_RX_DESC 64 |
| #define | NR_TX_DESC 1 |
| #define | REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14 + 6) |
| #define | MIN_TX_DESC_FREE 8 |
| #define | CFGCS 0x04 |
| #define | CR_TXE 0x00000001 |
| #define | CR_TXD 0x00000002 |
| #define | CR_RXE 0x00000004 |
| #define | CR_RXD 0x00000008 |
| #define | CR_TXR 0x00000010 |
| #define | CR_RXR 0x00000020 |
| #define | CR_SWI 0x00000080 |
| #define | CR_RST 0x00000100 |
| #define | PTSCR_EEBIST_FAIL 0x00000001 |
| #define | PTSCR_EEBIST_EN 0x00000002 |
| #define | PTSCR_EELOAD_EN 0x00000004 |
| #define | PTSCR_RBIST_FAIL 0x000001b8 |
| #define | PTSCR_RBIST_DONE 0x00000200 |
| #define | PTSCR_RBIST_EN 0x00000400 |
| #define | PTSCR_RBIST_RST 0x00002000 |
| #define | MEAR_EEDI 0x00000001 |
| #define | MEAR_EEDO 0x00000002 |
| #define | MEAR_EECLK 0x00000004 |
| #define | MEAR_EESEL 0x00000008 |
| #define | MEAR_MDIO 0x00000010 |
| #define | MEAR_MDDIR 0x00000020 |
| #define | MEAR_MDC 0x00000040 |
| #define | ISR_TXDESC3 0x40000000 |
| #define | ISR_TXDESC2 0x20000000 |
| #define | ISR_TXDESC1 0x10000000 |
| #define | ISR_TXDESC0 0x08000000 |
| #define | ISR_RXDESC3 0x04000000 |
| #define | ISR_RXDESC2 0x02000000 |
| #define | ISR_RXDESC1 0x01000000 |
| #define | ISR_RXDESC0 0x00800000 |
| #define | ISR_TXRCMP 0x00400000 |
| #define | ISR_RXRCMP 0x00200000 |
| #define | ISR_DPERR 0x00100000 |
| #define | ISR_SSERR 0x00080000 |
| #define | ISR_RMABT 0x00040000 |
| #define | ISR_RTABT 0x00020000 |
| #define | ISR_RXSOVR 0x00010000 |
| #define | ISR_HIBINT 0x00008000 |
| #define | ISR_PHY 0x00004000 |
| #define | ISR_PME 0x00002000 |
| #define | ISR_SWI 0x00001000 |
| #define | ISR_MIB 0x00000800 |
| #define | ISR_TXURN 0x00000400 |
| #define | ISR_TXIDLE 0x00000200 |
| #define | ISR_TXERR 0x00000100 |
| #define | ISR_TXDESC 0x00000080 |
| #define | ISR_TXOK 0x00000040 |
| #define | ISR_RXORN 0x00000020 |
| #define | ISR_RXIDLE 0x00000010 |
| #define | ISR_RXEARLY 0x00000008 |
| #define | ISR_RXERR 0x00000004 |
| #define | ISR_RXDESC 0x00000002 |
| #define | ISR_RXOK 0x00000001 |
| #define | TXCFG_CSI 0x80000000 |
| #define | TXCFG_HBI 0x40000000 |
| #define | TXCFG_MLB 0x20000000 |
| #define | TXCFG_ATP 0x10000000 |
| #define | TXCFG_ECRETRY 0x00800000 |
| #define | TXCFG_BRST_DIS 0x00080000 |
| #define | TXCFG_MXDMA1024 0x00000000 |
| #define | TXCFG_MXDMA512 0x00700000 |
| #define | TXCFG_MXDMA256 0x00600000 |
| #define | TXCFG_MXDMA128 0x00500000 |
| #define | TXCFG_MXDMA64 0x00400000 |
| #define | TXCFG_MXDMA32 0x00300000 |
| #define | TXCFG_MXDMA16 0x00200000 |
| #define | TXCFG_MXDMA8 0x00100000 |
| #define | CFG_LNKSTS 0x80000000 |
| #define | CFG_SPDSTS 0x60000000 |
| #define | CFG_SPDSTS1 0x40000000 |
| #define | CFG_SPDSTS0 0x20000000 |
| #define | CFG_DUPSTS 0x10000000 |
| #define | CFG_TBI_EN 0x01000000 |
| #define | CFG_MODE_1000 0x00400000 |
| #define | CFG_AUTO_1000 0x00200000 |
| #define | CFG_PINT_CTL 0x001c0000 |
| #define | CFG_PINT_DUPSTS 0x00100000 |
| #define | CFG_PINT_LNKSTS 0x00080000 |
| #define | CFG_PINT_SPDSTS 0x00040000 |
| #define | CFG_TMRTEST 0x00020000 |
| #define | CFG_MRM_DIS 0x00010000 |
| #define | CFG_MWI_DIS 0x00008000 |
| #define | CFG_T64ADDR 0x00004000 |
| #define | CFG_PCI64_DET 0x00002000 |
| #define | CFG_DATA64_EN 0x00001000 |
| #define | CFG_M64ADDR 0x00000800 |
| #define | CFG_PHY_RST 0x00000400 |
| #define | CFG_PHY_DIS 0x00000200 |
| #define | CFG_EXTSTS_EN 0x00000100 |
| #define | CFG_REQALG 0x00000080 |
| #define | CFG_SB 0x00000040 |
| #define | CFG_POW 0x00000020 |
| #define | CFG_EXD 0x00000010 |
| #define | CFG_PESEL 0x00000008 |
| #define | CFG_BROM_DIS 0x00000004 |
| #define | CFG_EXT_125 0x00000002 |
| #define | CFG_BEM 0x00000001 |
| #define | EXTSTS_UDPPKT 0x00200000 |
| #define | EXTSTS_TCPPKT 0x00080000 |
| #define | EXTSTS_IPPKT 0x00020000 |
| #define | SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) |
| #define | MIBC_MIBS 0x00000008 |
| #define | MIBC_ACLR 0x00000004 |
| #define | MIBC_FRZ 0x00000002 |
| #define | MIBC_WRN 0x00000001 |
| #define | PCR_PSEN (1 << 31) |
| #define | PCR_PS_MCAST (1 << 30) |
| #define | PCR_PS_DA (1 << 29) |
| #define | PCR_STHI_8 (3 << 23) |
| #define | PCR_STLO_4 (1 << 23) |
| #define | PCR_FFHI_8K (3 << 21) |
| #define | PCR_FFLO_4K (1 << 21) |
| #define | PCR_PAUSE_CNT 0xFFFE |
| #define | RXCFG_AEP 0x80000000 |
| #define | RXCFG_ARP 0x40000000 |
| #define | RXCFG_STRIPCRC 0x20000000 |
| #define | RXCFG_RX_FD 0x10000000 |
| #define | RXCFG_ALP 0x08000000 |
| #define | RXCFG_AIRL 0x04000000 |
| #define | RXCFG_MXDMA512 0x00700000 |
| #define | RXCFG_DRTH 0x0000003e |
| #define | RXCFG_DRTH0 0x00000002 |
| #define | RFCR_RFEN 0x80000000 |
| #define | RFCR_AAB 0x40000000 |
| #define | RFCR_AAM 0x20000000 |
| #define | RFCR_AAU 0x10000000 |
| #define | RFCR_APM 0x08000000 |
| #define | RFCR_APAT 0x07800000 |
| #define | RFCR_APAT3 0x04000000 |
| #define | RFCR_APAT2 0x02000000 |
| #define | RFCR_APAT1 0x01000000 |
| #define | RFCR_APAT0 0x00800000 |
| #define | RFCR_AARP 0x00400000 |
| #define | RFCR_MHEN 0x00200000 |
| #define | RFCR_UHEN 0x00100000 |
| #define | RFCR_ULM 0x00080000 |
| #define | VRCR_RUDPE 0x00000080 |
| #define | VRCR_RTCPE 0x00000040 |
| #define | VRCR_RIPE 0x00000020 |
| #define | VRCR_IPEN 0x00000010 |
| #define | VRCR_DUTF 0x00000008 |
| #define | VRCR_DVTF 0x00000004 |
| #define | VRCR_VTREN 0x00000002 |
| #define | VRCR_VTDEN 0x00000001 |
| #define | VTCR_PPCHK 0x00000008 |
| #define | VTCR_GCHK 0x00000004 |
| #define | VTCR_VPPTI 0x00000002 |
| #define | VTCR_VGTI 0x00000001 |
| #define | CR 0x00 |
| #define | CFG 0x04 |
| #define | MEAR 0x08 |
| #define | PTSCR 0x0c |
| #define | ISR 0x10 |
| #define | IMR 0x14 |
| #define | IER 0x18 |
| #define | IHR 0x1c |
| #define | TXDP 0x20 |
| #define | TXDP_HI 0x24 |
| #define | TXCFG 0x28 |
| #define | GPIOR 0x2c |
| #define | RXDP 0x30 |
| #define | RXDP_HI 0x34 |
| #define | RXCFG 0x38 |
| #define | PQCR 0x3c |
| #define | WCSR 0x40 |
| #define | PCR 0x44 |
| #define | RFCR 0x48 |
| #define | RFDR 0x4c |
| #define | SRR 0x58 |
| #define | VRCR 0xbc |
| #define | VTCR 0xc0 |
| #define | VDR 0xc4 |
| #define | CCSR 0xcc |
| #define | TBICR 0xe0 |
| #define | TBISR 0xe4 |
| #define | TANAR 0xe8 |
| #define | TANLPAR 0xec |
| #define | TANER 0xf0 |
| #define | TESR 0xf4 |
| #define | TBICR_MR_AN_ENABLE 0x00001000 |
| #define | TBICR_MR_RESTART_AN 0x00000200 |
| #define | TBISR_MR_LINK_STATUS 0x00000020 |
| #define | TBISR_MR_AN_COMPLETE 0x00000004 |
| #define | TANAR_PS2 0x00000100 |
| #define | TANAR_PS1 0x00000080 |
| #define | TANAR_HALF_DUP 0x00000040 |
| #define | TANAR_FULL_DUP 0x00000020 |
| #define | GPIOR_GP5_OE 0x00000200 |
| #define | GPIOR_GP4_OE 0x00000100 |
| #define | GPIOR_GP3_OE 0x00000080 |
| #define | GPIOR_GP2_OE 0x00000040 |
| #define | GPIOR_GP1_OE 0x00000020 |
| #define | GPIOR_GP3_OUT 0x00000004 |
| #define | GPIOR_GP1_OUT 0x00000001 |
| #define | LINK_AUTONEGOTIATE 0x01 |
| #define | LINK_DOWN 0x02 |
| #define | LINK_UP 0x04 |
| #define | __kick_rx() writel(CR_RXE, ns->base + CR) |
| #define | kick_rx() |
| #define | HW_ADDR_LEN 8 |
| #define | CMDSTS_OWN 0x80000000 |
| #define | CMDSTS_MORE 0x40000000 |
| #define | CMDSTS_INTR 0x20000000 |
| #define | CMDSTS_ERR 0x10000000 |
| #define | CMDSTS_OK 0x08000000 |
| #define | CMDSTS_LEN_MASK 0x0000ffff |
| #define | CMDSTS_DEST_MASK 0x01800000 |
| #define | CMDSTS_DEST_SELF 0x00800000 |
| #define | CMDSTS_DEST_MULTI 0x01000000 |
| #define | DESC_SIZE 8 |
| #define | tx_ring ns83820_bufs.tx_ring |
| #define | rx_ring ns83820_bufs.rx_ring |
| #define | txb ns83820_bufs.txb |
| #define | rxb ns83820_bufs.rxb |
| #define | board_found 1 |
| #define | valid_link 0 |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| static void | phy_intr (struct nic *nic __unused) |
| static void | ns83820_set_multicast (struct nic *nic __unused) |
| static void | ns83820_setup_rx (struct nic *nic) |
| static void | ns83820_do_reset (struct nic *nic __unused, u32 which) |
| static void | ns83820_reset (struct nic *nic) |
| static void | ns83820_getmac (struct nic *nic __unused, u8 *mac) |
| static void | ns83820_run_bist (struct nic *nic __unused, const char *name, u32 enable, u32 done, u32 fail) |
| static void | ns83820_check_intr (struct nic *nic) |
| static int | ns83820_poll (struct nic *nic, int retrieve) |
| static void | kick_tx (struct nic *nic __unused) |
| static void | ns83820_transmit (struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p) |
| static void | ns83820_disable (struct nic *nic) |
| static void | ns83820_irq (struct nic *nic __unused, irq_action_t action __unused) |
| PCI_DRIVER (ns83820_driver, ns83820_nics, PCI_NO_CLASS) | |
| static int | ns83820_probe (struct nic *nic, struct pci_device *pci) |
| DRIVER ("NS83820/PCI", nic_driver, pci_driver, ns83820_driver, ns83820_probe, ns83820_disable) | |
Variables | |
| static int | reset_phy = 0 |
| static int | lnksts = 0 |
| static struct ns83820_private | nsx |
| static struct ns83820_private * | ns |
| struct { | |
| struct ring_desc tx_ring [NR_TX_DESC] | |
| unsigned char txb [NR_TX_DESC *REAL_RX_BUF_SIZE] | |
| struct ring_desc rx_ring [NR_RX_DESC] | |
| unsigned char rxb [NR_RX_DESC *REAL_RX_BUF_SIZE] | |
| } | __shared |
| static struct nic_operations | ns83820_operations |
| static struct pci_device_id | ns83820_nics [] |
| #define virt_to_le32desc | ( | addr | ) | cpu_to_le32(virt_to_bus(addr)) |
| #define le32desc_to_virt | ( | addr | ) | bus_to_virt(le32_to_cpu(addr)) |
| #define NR_RX_DESC 64 |
Definition at line 85 of file ns83820.c.
Referenced by ns83820_check_intr(), ns83820_poll(), and ns83820_setup_rx().
| #define NR_TX_DESC 1 |
| #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14 + 6) |
Definition at line 89 of file ns83820.c.
Referenced by ns83820_check_intr(), ns83820_poll(), and ns83820_setup_rx().
| #define CR_RST 0x00000100 |
| #define PTSCR_EEBIST_FAIL 0x00000001 |
| #define PTSCR_EEBIST_EN 0x00000002 |
| #define PTSCR_EELOAD_EN 0x00000004 |
| #define PTSCR_RBIST_FAIL 0x000001b8 |
| #define PTSCR_RBIST_DONE 0x00000200 |
| #define PTSCR_RBIST_EN 0x00000400 |
| #define PTSCR_RBIST_RST 0x00002000 |
| #define ISR_RXRCMP 0x00200000 |
| #define ISR_RXSOVR 0x00010000 |
| #define ISR_PHY 0x00004000 |
Definition at line 140 of file ns83820.c.
Referenced by ns83820_check_intr(), and ns83820_setup_rx().
| #define ISR_TXIDLE 0x00000200 |
| #define ISR_TXDESC 0x00000080 |
| #define ISR_RXORN 0x00000020 |
| #define ISR_RXIDLE 0x00000010 |
Definition at line 150 of file ns83820.c.
Referenced by ns83820_check_intr(), ns83820_disable(), and ns83820_setup_rx().
| #define ISR_RXEARLY 0x00000008 |
| #define ISR_RXERR 0x00000004 |
Definition at line 152 of file ns83820.c.
Referenced by ns83820_check_intr(), and ns83820_disable().
| #define ISR_RXDESC 0x00000002 |
Definition at line 153 of file ns83820.c.
Referenced by ns83820_check_intr(), ns83820_disable(), and ns83820_setup_rx().
| #define ISR_RXOK 0x00000001 |
| #define TXCFG_CSI 0x80000000 |
| #define TXCFG_HBI 0x40000000 |
| #define TXCFG_ATP 0x10000000 |
| #define TXCFG_MXDMA512 0x00700000 |
| #define CFG_LNKSTS 0x80000000 |
| #define CFG_SPDSTS 0x60000000 |
| #define CFG_SPDSTS1 0x40000000 |
| #define CFG_SPDSTS0 0x20000000 |
| #define CFG_DUPSTS 0x10000000 |
| #define CFG_TBI_EN 0x01000000 |
| #define CFG_MODE_1000 0x00400000 |
| #define CFG_PINT_DUPSTS 0x00100000 |
| #define CFG_PINT_LNKSTS 0x00080000 |
| #define CFG_PINT_SPDSTS 0x00040000 |
| #define CFG_TMRTEST 0x00020000 |
| #define CFG_MRM_DIS 0x00010000 |
| #define CFG_MWI_DIS 0x00008000 |
| #define CFG_T64ADDR 0x00004000 |
| #define CFG_PCI64_DET 0x00002000 |
| #define CFG_DATA64_EN 0x00001000 |
| #define CFG_M64ADDR 0x00000800 |
| #define CFG_PHY_RST 0x00000400 |
| #define CFG_EXTSTS_EN 0x00000100 |
| #define CFG_REQALG 0x00000080 |
| #define CFG_SB 0x00000040 |
| #define CFG_POW 0x00000020 |
| #define CFG_EXD 0x00000010 |
| #define CFG_PESEL 0x00000008 |
| #define CFG_EXT_125 0x00000002 |
| #define CFG_BEM 0x00000001 |
| #define EXTSTS_UDPPKT 0x00200000 |
| #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) |
| #define PCR_PSEN (1 << 31) |
| #define PCR_PS_MCAST (1 << 30) |
| #define PCR_PS_DA (1 << 29) |
| #define PCR_STHI_8 (3 << 23) |
| #define PCR_STLO_4 (1 << 23) |
| #define PCR_FFHI_8K (3 << 21) |
| #define PCR_FFLO_4K (1 << 21) |
| #define PCR_PAUSE_CNT 0xFFFE |
| #define RXCFG_AEP 0x80000000 |
| #define RXCFG_ARP 0x40000000 |
| #define RXCFG_STRIPCRC 0x20000000 |
| #define RXCFG_RX_FD 0x10000000 |
| #define RXCFG_AIRL 0x04000000 |
| #define RXCFG_MXDMA512 0x00700000 |
| #define RFCR_RFEN 0x80000000 |
| #define RFCR_AAM 0x20000000 |
| #define RFCR_AAU 0x10000000 |
| #define VRCR_IPEN 0x00000010 |
| #define VRCR_VTDEN 0x00000001 |
| #define VTCR_PPCHK 0x00000008 |
| #define CR 0x00 |
Definition at line 263 of file ns83820.c.
Referenced by kick_tx(), main_loop(), ns83820_do_reset(), pxe_menu_select(), and readline().
| #define CFG 0x04 |
| #define PTSCR 0x0c |
| #define ISR 0x10 |
Definition at line 267 of file ns83820.c.
Referenced by mtd_reset(), ns83820_check_intr(), and ns83820_transmit().
| #define IMR 0x14 |
Definition at line 268 of file ns83820.c.
Referenced by mtd_reset(), ns83820_disable(), and ns83820_probe().
| #define IER 0x18 |
| #define TXDP 0x20 |
| #define TXDP_HI 0x24 |
| #define TXCFG 0x28 |
| #define GPIOR 0x2c |
| #define RXDP 0x30 |
| #define RXDP_HI 0x34 |
| #define RXCFG 0x38 |
| #define PQCR 0x3c |
| #define WCSR 0x40 |
| #define PCR 0x44 |
| #define RFCR 0x48 |
Definition at line 281 of file ns83820.c.
Referenced by ns83820_getmac(), ns83820_set_multicast(), and ns83820_setup_rx().
| #define RFDR 0x4c |
| #define SRR 0x58 |
| #define VRCR 0xbc |
| #define VTCR 0xc0 |
| #define CCSR 0xcc |
| #define TBICR 0xe0 |
| #define TBISR 0xe4 |
| #define TANAR 0xe8 |
| #define TANLPAR 0xec |
| #define TBICR_MR_AN_ENABLE 0x00001000 |
| #define TBICR_MR_RESTART_AN 0x00000200 |
| #define TANAR_HALF_DUP 0x00000040 |
| #define TANAR_FULL_DUP 0x00000020 |
| #define GPIOR_GP1_OUT 0x00000001 |
| #define LINK_AUTONEGOTIATE 0x01 |
| #define LINK_DOWN 0x02 |
| #define LINK_UP 0x04 |
| #define kick_rx | ( | ) |
Value:
do { \ dprintf(("kick_rx: maybe kicking\n")); \ writel(virt_to_le32desc(&rx_ring[ns->cur_rx]), ns->base + RXDP); \ if (ns->next_rx == ns->next_empty) \ printf("uh-oh: next_rx == next_empty???\n"); \ __kick_rx(); \ } while(0)
Definition at line 324 of file ns83820.c.
Referenced by ns83820_check_intr(), ns83820_poll(), and ns83820_setup_rx().
| #define CMDSTS_OWN 0x80000000 |
Definition at line 339 of file ns83820.c.
Referenced by ns83820_check_intr(), ns83820_poll(), and ns83820_transmit().
| #define CMDSTS_OK 0x08000000 |
| #define tx_ring ns83820_bufs.tx_ring |
| #define rx_ring ns83820_bufs.rx_ring |
| #define txb ns83820_bufs.txb |
| #define rxb ns83820_bufs.rxb |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
Definition at line 404 of file ns83820.c.
References ns83820_private::base, CFG, cfg, ns83820_private::CFG_cache, CFG_DUPSTS, CFG_LNKSTS, CFG_MODE_1000, CFG_SB, CFG_SPDSTS, CFG_SPDSTS0, CFG_SPDSTS1, CFG_TBI_EN, dprintf, GPIOR, GPIOR_GP1_OUT, LINK_DOWN, LINK_UP, ns83820_private::linkstate, printf(), readl, RXCFG, RXCFG_RX_FD, SPDSTS_POLARITY, TANAR, TANAR_FULL_DUP, TANAR_HALF_DUP, TANLPAR, TBISR, TXCFG, TXCFG_ATP, TXCFG_CSI, TXCFG_HBI, u32, and writel.
Referenced by ns83820_check_intr(), and ns83820_setup_rx().
00405 { 00406 static char *speeds[] = 00407 { "10", "100", "1000", "1000(?)", "1000F" }; 00408 u32 cfg, new_cfg; 00409 u32 tbisr, tanar, tanlpar; 00410 int speed, fullduplex, newlinkstate; 00411 00412 cfg = readl(ns->base + CFG) ^ SPDSTS_POLARITY; 00413 if (ns->CFG_cache & CFG_TBI_EN) { 00414 /* we have an optical transceiver */ 00415 tbisr = readl(ns->base + TBISR); 00416 tanar = readl(ns->base + TANAR); 00417 tanlpar = readl(ns->base + TANLPAR); 00418 dprintf(("phy_intr: tbisr=%hX, tanar=%hX, tanlpar=%hX\n", 00419 tbisr, tanar, tanlpar)); 00420 00421 if ((fullduplex = (tanlpar & TANAR_FULL_DUP) 00422 && (tanar & TANAR_FULL_DUP))) { 00423 00424 /* both of us are full duplex */ 00425 writel(readl(ns->base + TXCFG) 00426 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, 00427 ns->base + TXCFG); 00428 writel(readl(ns->base + RXCFG) | RXCFG_RX_FD, 00429 ns->base + RXCFG); 00430 /* Light up full duplex LED */ 00431 writel(readl(ns->base + GPIOR) | GPIOR_GP1_OUT, 00432 ns->base + GPIOR); 00433 00434 } else if (((tanlpar & TANAR_HALF_DUP) 00435 && (tanar & TANAR_HALF_DUP)) 00436 || ((tanlpar & TANAR_FULL_DUP) 00437 && (tanar & TANAR_HALF_DUP)) 00438 || ((tanlpar & TANAR_HALF_DUP) 00439 && (tanar & TANAR_FULL_DUP))) { 00440 00441 /* one or both of us are half duplex */ 00442 writel((readl(ns->base + TXCFG) 00443 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP, 00444 ns->base + TXCFG); 00445 writel(readl(ns->base + RXCFG) & ~RXCFG_RX_FD, 00446 ns->base + RXCFG); 00447 /* Turn off full duplex LED */ 00448 writel(readl(ns->base + GPIOR) & ~GPIOR_GP1_OUT, 00449 ns->base + GPIOR); 00450 } 00451 00452 speed = 4; /* 1000F */ 00453 00454 } else { 00455 /* we have a copper transceiver */ 00456 new_cfg = 00457 ns->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS); 00458 00459 if (cfg & CFG_SPDSTS1) 00460 new_cfg |= CFG_MODE_1000; 00461 else 00462 new_cfg &= ~CFG_MODE_1000; 00463 00464 speed = ((cfg / CFG_SPDSTS0) & 3); 00465 fullduplex = (cfg & CFG_DUPSTS); 00466 00467 if (fullduplex) 00468 new_cfg |= CFG_SB; 00469 00470 if ((cfg & CFG_LNKSTS) && 00471 ((new_cfg ^ ns->CFG_cache) & CFG_MODE_1000)) { 00472 writel(new_cfg, ns->base + CFG); 00473 ns->CFG_cache = new_cfg; 00474 } 00475 00476 ns->CFG_cache &= ~CFG_SPDSTS; 00477 ns->CFG_cache |= cfg & CFG_SPDSTS; 00478 } 00479 00480 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN; 00481 00482 if (newlinkstate & LINK_UP && ns->linkstate != newlinkstate) { 00483 printf("link now %s mbps, %s duplex and up.\n", 00484 speeds[speed], fullduplex ? "full" : "half"); 00485 } else if (newlinkstate & LINK_DOWN 00486 && ns->linkstate != newlinkstate) { 00487 printf("link now down.\n"); 00488 } 00489 ns->linkstate = newlinkstate; 00490 }
Definition at line 591 of file ns83820.c.
References ns83820_private::base, readl, RFCR, rfcr, RFCR_AAM, RFCR_AAU, RFCR_RFEN, u32, u8, and writel.
Referenced by ns83820_setup_rx().
00592 { 00593 u8 *rfcr = ns->base + RFCR; 00594 u32 and_mask = 0xffffffff; 00595 u32 or_mask = 0; 00596 u32 val; 00597 00598 /* Support Multicast */ 00599 and_mask &= ~(RFCR_AAU | RFCR_AAM); 00600 or_mask |= RFCR_AAM; 00601 val = (readl(rfcr) & and_mask) | or_mask; 00602 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */ 00603 writel(val & ~RFCR_RFEN, rfcr); 00604 writel(val, rfcr); 00605 00606 }
| static void ns83820_setup_rx | ( | struct nic * | nic | ) | [static] |
Definition at line 492 of file ns83820.c.
References ns83820_private::base, CCSR, cpu_to_le32, ns83820_private::cur_rx, ns83820_private::descs, dprintf, ns83820_private::idle, ns83820_private::IMR_cache, ISR_PHY, ISR_RXDESC, ISR_RXIDLE, ISR_RXORN, ISR_RXRCMP, ISR_RXSOVR, ISR_TXDESC, ISR_TXIDLE, kick_rx, ns83820_private::next_empty, ns83820_private::next_rx, ns83820_private::next_rx_desc, NR_RX_DESC, ns83820_set_multicast(), phy_intr(), REAL_RX_BUF_SIZE, RFCR, rx_ring, rxb, RXDP, RXDP_HI, ns83820_private::up, virt_to_le32desc, and writel.
Referenced by ns83820_reset().
00493 { 00494 unsigned i; 00495 ns->idle = 1; 00496 ns->next_rx = 0; 00497 ns->next_rx_desc = ns->descs; 00498 ns->next_empty = 0; 00499 ns->cur_rx = 0; 00500 00501 00502 for (i = 0; i < NR_RX_DESC; i++) { 00503 rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]); 00504 rx_ring[i].bufptr = 00505 virt_to_le32desc(&rxb[i * REAL_RX_BUF_SIZE]); 00506 rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE); 00507 rx_ring[i].extsts = cpu_to_le32(0); 00508 } 00509 // No need to wrap the ring 00510 // rx_ring[i].link = virt_to_le32desc(&rx_ring[0]); 00511 writel(0, ns->base + RXDP_HI); 00512 writel(virt_to_le32desc(&rx_ring[0]), ns->base + RXDP); 00513 00514 dprintf(("starting receiver\n")); 00515 00516 writel(0x0001, ns->base + CCSR); 00517 writel(0, ns->base + RFCR); 00518 writel(0x7fc00000, ns->base + RFCR); 00519 writel(0xffc00000, ns->base + RFCR); 00520 00521 ns->up = 1; 00522 00523 phy_intr(nic); 00524 00525 /* Okay, let it rip */ 00526 ns->IMR_cache |= ISR_PHY; 00527 ns->IMR_cache |= ISR_RXRCMP; 00528 //dev->IMR_cache |= ISR_RXERR; 00529 //dev->IMR_cache |= ISR_RXOK; 00530 ns->IMR_cache |= ISR_RXORN; 00531 ns->IMR_cache |= ISR_RXSOVR; 00532 ns->IMR_cache |= ISR_RXDESC; 00533 ns->IMR_cache |= ISR_RXIDLE; 00534 ns->IMR_cache |= ISR_TXDESC; 00535 ns->IMR_cache |= ISR_TXIDLE; 00536 00537 // No reason to enable interupts... 00538 // writel(ns->IMR_cache, ns->base + IMR); 00539 // writel(1, ns->base + IER); 00540 ns83820_set_multicast(nic); 00541 kick_rx(); 00542 }
Definition at line 545 of file ns83820.c.
References ns83820_private::base, CR, dprintf, readl, and writel.
Referenced by ns83820_disable(), and ns83820_probe().
00546 { 00547 dprintf(("resetting chip...\n")); 00548 writel(which, ns->base + CR); 00549 do { 00550 00551 } while (readl(ns->base + CR) & which); 00552 dprintf(("okay!\n")); 00553 }
| static void ns83820_reset | ( | struct nic * | nic | ) | [static] |
Definition at line 555 of file ns83820.c.
References ns83820_private::base, cpu_to_le32, dprintf, NR_TX_DESC, ns83820_setup_rx(), PQCR, ns83820_private::tx_done_idx, ns83820_private::tx_idx, tx_ring, TXDP_HI, and writel.
Referenced by ns83820_probe().
00556 { 00557 unsigned i; 00558 dprintf(("ns83820_reset\n")); 00559 00560 writel(0, ns->base + PQCR); 00561 00562 ns83820_setup_rx(nic); 00563 00564 for (i = 0; i < NR_TX_DESC; i++) { 00565 tx_ring[i].link = 0; 00566 tx_ring[i].bufptr = 0; 00567 tx_ring[i].cmdsts = cpu_to_le32(0); 00568 tx_ring[i].extsts = cpu_to_le32(0); 00569 } 00570 00571 ns->tx_idx = 0; 00572 ns->tx_done_idx = 0; 00573 writel(0, ns->base + TXDP_HI); 00574 return; 00575 }
Definition at line 576 of file ns83820.c.
References ns83820_private::base, readl, RFCR, RFDR, u32, and writel.
Referenced by ns83820_probe().
00577 { 00578 unsigned i; 00579 for (i = 0; i < 3; i++) { 00580 u32 data; 00581 /* Read from the perfect match memory: this is loaded by 00582 * the chip from the EEPROM via the EELOAD self test. 00583 */ 00584 writel(i * 2, ns->base + RFCR); 00585 data = readl(ns->base + RFDR); 00586 *mac++ = data; 00587 *mac++ = data >> 8; 00588 } 00589 }
| static void ns83820_run_bist | ( | struct nic *nic | __unused, | |
| const char * | name, | |||
| u32 | enable, | |||
| u32 | done, | |||
| u32 | fail | |||
| ) | [static] |
Definition at line 607 of file ns83820.c.
References ns83820_private::base, currticks(), dprintf, HZ, printf(), PTSCR, readl, u32, and writel.
Referenced by ns83820_probe().
00609 { 00610 int timed_out = 0; 00611 long start; 00612 u32 status; 00613 int loops = 0; 00614 00615 dprintf(("start %s\n", name)) 00616 00617 start = currticks(); 00618 00619 writel(enable, ns->base + PTSCR); 00620 for (;;) { 00621 loops++; 00622 status = readl(ns->base + PTSCR); 00623 if (!(status & enable)) 00624 break; 00625 if (status & done) 00626 break; 00627 if (status & fail) 00628 break; 00629 if ((currticks() - start) >= HZ) { 00630 timed_out = 1; 00631 break; 00632 } 00633 } 00634 00635 if (status & fail) 00636 printf("%s failed! (0x%hX & 0x%hX)\n", name, (unsigned int) status, 00637 (unsigned int) fail); 00638 else if (timed_out) 00639 printf("run_bist %s timed out! (%hX)\n", name, (unsigned int) status); 00640 dprintf(("done %s in %d loops\n", name, loops)); 00641 }
| static void ns83820_check_intr | ( | struct nic * | nic | ) | [static] |
Definition at line 646 of file ns83820.c.
References ns83820_private::base, ring_desc::cmdsts, CMDSTS_OWN, cpu_to_le32, ISR, isr, ISR_PHY, ISR_RXDESC, ISR_RXERR, ISR_RXIDLE, kick_rx, NR_RX_DESC, phy_intr(), readl, REAL_RX_BUF_SIZE, rx_ring, and u32.
Referenced by ns83820_poll().
00646 { 00647 int i; 00648 u32 isr = readl(ns->base + ISR); 00649 if(ISR_PHY & isr) 00650 phy_intr(nic); 00651 if(( ISR_RXIDLE | ISR_RXDESC | ISR_RXERR) & isr) 00652 kick_rx(); 00653 for (i = 0; i < NR_RX_DESC; i++) { 00654 if (rx_ring[i].cmdsts == CMDSTS_OWN) { 00655 // rx_ring[i].link = virt_to_le32desc(&rx_ring[i + 1]); 00656 rx_ring[i].cmdsts = cpu_to_le32(REAL_RX_BUF_SIZE); 00657 } 00658 } 00659 }
| static int ns83820_poll | ( | struct nic * | nic, | |
| int | retrieve | |||
| ) | [static] |
Definition at line 663 of file ns83820.c.
References ring_desc::cmdsts, CMDSTS_OK, CMDSTS_OWN, cpu_to_le32, ns83820_private::cur_rx, entry, kick_rx, le32_to_cpu, memcpy, NR_RX_DESC, ns83820_check_intr(), nic::packet, nic::packetlen, REAL_RX_BUF_SIZE, rx_ring, rxb, and u32.
00664 { 00665 /* return true if there's an ethernet packet ready to read */ 00666 /* nic->packet should contain data on return */ 00667 /* nic->packetlen should contain length of data */ 00668 u32 cmdsts; 00669 int entry = ns->cur_rx; 00670 00671 ns83820_check_intr(nic); 00672 00673 cmdsts = le32_to_cpu(rx_ring[entry].cmdsts); 00674 00675 if ( ! ( (CMDSTS_OWN & (cmdsts)) && (cmdsts != (CMDSTS_OWN)) ) ) 00676 return 0; 00677 00678 if ( ! retrieve ) return 1; 00679 00680 if (! (CMDSTS_OK & cmdsts) ) 00681 return 0; 00682 00683 nic->packetlen = cmdsts & 0xffff; 00684 memcpy(nic->packet, 00685 rxb + (entry * REAL_RX_BUF_SIZE), 00686 nic->packetlen); 00687 // rx_ring[entry].link = 0; 00688 rx_ring[entry].cmdsts = cpu_to_le32(CMDSTS_OWN); 00689 00690 ns->cur_rx = ++ns->cur_rx % NR_RX_DESC; 00691 00692 if (ns->cur_rx == 0) /* We have wrapped the ring */ 00693 kick_rx(); 00694 00695 return 1; 00696 }
| static void ns83820_transmit | ( | struct nic * | nic, | |
| const char * | d, | |||
| unsigned int | t, | |||
| unsigned int | s, | |||
| const char * | p | |||
| ) | [static] |
Definition at line 707 of file ns83820.c.
References ns83820_private::base, ring_desc::cmdsts, CMDSTS_OWN, cpu_to_le32, cur_tx, ETH_ALEN, ETH_HLEN, ETH_ZLEN, ring_desc::extsts, EXTSTS_UDPPKT, htons, ISR, isr, ISR_TXIDLE, kick_tx(), memcpy, nic::node_addr, readl, tx_ring, txb, TXDP, u16, u32, u8, virt_to_le32desc, and writel.
00711 { /* Packet */ 00712 /* send the packet to destination */ 00713 00714 u16 nstype; 00715 u32 cmdsts, extsts; 00716 int cur_tx = 0; 00717 u32 isr = readl(ns->base + ISR); 00718 if (ISR_TXIDLE & isr) 00719 kick_tx(nic); 00720 /* point to the current txb incase multiple tx_rings are used */ 00721 memcpy(txb, d, ETH_ALEN); 00722 memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN); 00723 nstype = htons((u16) t); 00724 memcpy(txb + 2 * ETH_ALEN, (u8 *) & nstype, 2); 00725 memcpy(txb + ETH_HLEN, p, s); 00726 s += ETH_HLEN; 00727 s &= 0x0FFF; 00728 while (s < ETH_ZLEN) 00729 txb[s++] = '\0'; 00730 00731 /* Setup the transmit descriptor */ 00732 extsts = 0; 00733 extsts |= EXTSTS_UDPPKT; 00734 00735 tx_ring[cur_tx].bufptr = virt_to_le32desc(&txb); 00736 tx_ring[cur_tx].extsts = cpu_to_le32(extsts); 00737 00738 cmdsts = cpu_to_le32(0); 00739 cmdsts |= cpu_to_le32(CMDSTS_OWN | s); 00740 tx_ring[cur_tx].cmdsts = cpu_to_le32(cmdsts); 00741 00742 writel(virt_to_le32desc(&tx_ring[0]), ns->base + TXDP); 00743 kick_tx(nic); 00744 }
| static void ns83820_disable | ( | struct nic * | nic | ) | [static] |
Definition at line 749 of file ns83820.c.
References ns83820_private::base, CR_RST, IER, IMR, ns83820_private::IMR_cache, ISR_RXDESC, ISR_RXEARLY, ISR_RXERR, ISR_RXIDLE, ISR_RXOK, ns83820_do_reset(), readl, RXDP, RXDP_HI, ns83820_private::up, and writel.
00749 { 00750 00751 /* put the card in its initial state */ 00752 /* This function serves 3 purposes. 00753 * This disables DMA and interrupts so we don't receive 00754 * unexpected packets or interrupts from the card after 00755 * etherboot has finished. 00756 * This frees resources so etherboot may use 00757 * this driver on another interface 00758 * This allows etherboot to reinitialize the interface 00759 * if something is something goes wrong. 00760 */ 00761 /* disable interrupts */ 00762 writel(0, ns->base + IMR); 00763 writel(0, ns->base + IER); 00764 readl(ns->base + IER); 00765 00766 ns->up = 0; 00767 00768 ns83820_do_reset(nic, CR_RST); 00769 00770 ns->IMR_cache &= 00771 ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | 00772 ISR_RXIDLE); 00773 writel(ns->IMR_cache, ns->base + IMR); 00774 00775 /* touch the pci bus... */ 00776 readl(ns->base + IMR); 00777 00778 /* assumes the transmitter is already disabled and reset */ 00779 writel(0, ns->base + RXDP_HI); 00780 writel(0, ns->base + RXDP); 00781 }
| static void ns83820_irq | ( | struct nic *nic | __unused, | |
| irq_action_t action | __unused | |||
| ) | [static] |
| PCI_DRIVER | ( | ns83820_driver | , | |
| ns83820_nics | , | |||
| PCI_NO_CLASS | ||||
| ) |
| static int ns83820_probe | ( | struct nic * | nic, | |
| struct pci_device * | pci | |||
| ) | [static] |
Definition at line 818 of file ns83820.c.
References adjust_pci_device(), ns83820_private::base, CFG, CFG_BEM, ns83820_private::CFG_cache, CFG_DATA64_EN, CFG_EXD, CFG_EXT_125, CFG_EXTSTS_EN, CFG_M64ADDR, CFG_MODE_1000, CFG_MRM_DIS, CFG_MWI_DIS, CFG_PCI64_DET, CFG_PESEL, CFG_PHY_RST, CFG_PINT_DUPSTS, CFG_PINT_LNKSTS, CFG_PINT_SPDSTS, CFG_POW, CFG_REQALG, CFG_T64ADDR, CFG_TBI_EN, CFG_TMRTEST, CR_RST, pci_device::device, dprintf, pci_device::driver_name, GPIOR, IER, IMR, ns83820_private::IMR_cache, nic::ioaddr, pci_device::ioaddr, ioremap(), nic::irqno, LINK_AUTONEGOTIATE, ns83820_private::linkstate, nic::nic_op, nic::node_addr, ns83820_do_reset(), ns83820_getmac(), ns83820_reset(), ns83820_run_bist(), nsx, pci_bar_start(), PCI_BASE_ADDRESS_1, PCR, PCR_FFHI_8K, PCR_FFLO_4K, PCR_PAUSE_CNT, PCR_PS_DA, PCR_PS_MCAST, PCR_PSEN, PCR_STHI_8, PCR_STLO_4, PQCR, printf(), PTSCR, PTSCR_EEBIST_EN, PTSCR_EEBIST_FAIL, PTSCR_EELOAD_EN, PTSCR_RBIST_DONE, PTSCR_RBIST_EN, PTSCR_RBIST_FAIL, PTSCR_RBIST_RST, readl, reset_phy, RXCFG, RXCFG_AEP, RXCFG_AIRL, RXCFG_ARP, RXCFG_MXDMA512, RXCFG_RX_FD, RXCFG_STRIPCRC, SRR, TANAR, TANAR_FULL_DUP, TANAR_HALF_DUP, TBICR, TBICR_MR_AN_ENABLE, TBICR_MR_RESTART_AN, TXCFG, TXCFG_ATP, TXCFG_CSI, TXCFG_HBI, TXCFG_MXDMA512, pci_device::vendor, VRCR, VRCR_IPEN, VRCR_VTDEN, VTCR, VTCR_PPCHK, WCSR, and writel.
00818 { 00819 00820 long addr; 00821 int using_dac = 0; 00822 00823 if (pci->ioaddr == 0) 00824 return 0; 00825 00826 printf("ns83820.c: Found %s, vendor=0x%hX, device=0x%hX\n", 00827 pci->driver_name, pci->vendor, pci->device); 00828 00829 /* point to private storage */ 00830 ns = &nsx; 00831 00832 adjust_pci_device(pci); 00833 00834 addr = pci_bar_start(pci, PCI_BASE_ADDRESS_1); 00835 00836 ns->base = ioremap(addr, (1UL << 12)); 00837 00838 if (!ns->base) 00839 return 0; 00840 00841 nic->irqno = 0; 00842 nic->ioaddr = pci->ioaddr & ~3; 00843 00844 /* disable interrupts */ 00845 writel(0, ns->base + IMR); 00846 writel(0, ns->base + IER); 00847 readl(ns->base + IER); 00848 00849 ns->IMR_cache = 0; 00850 00851 ns83820_do_reset(nic, CR_RST); 00852 00853 /* Must reset the ram bist before running it */ 00854 writel(PTSCR_RBIST_RST, ns->base + PTSCR); 00855 ns83820_run_bist(nic, "sram bist", PTSCR_RBIST_EN, 00856 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL); 00857 ns83820_run_bist(nic, "eeprom bist", PTSCR_EEBIST_EN, 0, 00858 PTSCR_EEBIST_FAIL); 00859 ns83820_run_bist(nic, "eeprom load", PTSCR_EELOAD_EN, 0, 0); 00860 00861 /* I love config registers */ 00862 ns->CFG_cache = readl(ns->base + CFG); 00863 00864 if ((ns->CFG_cache & CFG_PCI64_DET)) { 00865 printf("%s: detected 64 bit PCI data bus.\n", pci->driver_name); 00866 /*dev->CFG_cache |= CFG_DATA64_EN; */ 00867 if (!(ns->CFG_cache & CFG_DATA64_EN)) 00868 printf 00869 ("%s: EEPROM did not enable 64 bit bus. Disabled.\n", 00870 pci->driver_name); 00871 } else 00872 ns->CFG_cache &= ~(CFG_DATA64_EN); 00873 00874 ns->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS | 00875 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 | 00876 CFG_M64ADDR); 00877 ns->CFG_cache |= 00878 CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS | 00879 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL; 00880 ns->CFG_cache |= CFG_REQALG; 00881 ns->CFG_cache |= CFG_POW; 00882 ns->CFG_cache |= CFG_TMRTEST; 00883 00884 /* When compiled with 64 bit addressing, we must always enable 00885 * the 64 bit descriptor format. 00886 */ 00887 #ifdef USE_64BIT_ADDR 00888 ns->CFG_cache |= CFG_M64ADDR; 00889 #endif 00890 00891 //FIXME: Enable section on dac or remove this 00892 if (using_dac) 00893 ns->CFG_cache |= CFG_T64ADDR; 00894 00895 /* Big endian mode does not seem to do what the docs suggest */ 00896 ns->CFG_cache &= ~CFG_BEM; 00897 00898 /* setup optical transceiver if we have one */ 00899 if (ns->CFG_cache & CFG_TBI_EN) { 00900 dprintf(("%s: enabling optical transceiver\n", pci->driver_name)); 00901 writel(readl(ns->base + GPIOR) | 0x3e8, ns->base + GPIOR); 00902 00903 /* setup auto negotiation feature advertisement */ 00904 writel(readl(ns->base + TANAR) 00905 | TANAR_HALF_DUP | TANAR_FULL_DUP, 00906 ns->base + TANAR); 00907 00908 /* start auto negotiation */ 00909 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, 00910 ns->base + TBICR); 00911 writel(TBICR_MR_AN_ENABLE, ns->base + TBICR); 00912 ns->linkstate = LINK_AUTONEGOTIATE; 00913 00914 ns->CFG_cache |= CFG_MODE_1000; 00915 } 00916 writel(ns->CFG_cache, ns->base + CFG); 00917 dprintf(("CFG: %hX\n", ns->CFG_cache)); 00918 00919 /* FIXME: reset_phy is defaulted to 0, should we reset anyway? */ 00920 if (reset_phy) { 00921 dprintf(("%s: resetting phy\n", pci->driver_name)); 00922 writel(ns->CFG_cache | CFG_PHY_RST, ns->base + CFG); 00923 writel(ns->CFG_cache, ns->base + CFG); 00924 } 00925 #if 0 /* Huh? This sets the PCI latency register. Should be done via 00926 * the PCI layer. FIXME. 00927 */ 00928 if (readl(dev->base + SRR)) 00929 writel(readl(dev->base + 0x20c) | 0xfe00, 00930 dev->base + 0x20c); 00931 #endif 00932 00933 /* Note! The DMA burst size interacts with packet 00934 * transmission, such that the largest packet that 00935 * can be transmitted is 8192 - FLTH - burst size. 00936 * If only the transmit fifo was larger... 00937 */ 00938 /* Ramit : 1024 DMA is not a good idea, it ends up banging 00939 * some DELL and COMPAQ SMP systems */ 00940 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512 00941 | ((1600 / 32) * 0x100), ns->base + TXCFG); 00942 00943 /* Set Rx to full duplex, don't accept runt, errored, long or length 00944 * range errored packets. Use 512 byte DMA. 00945 */ 00946 /* Ramit : 1024 DMA is not a good idea, it ends up banging 00947 * some DELL and COMPAQ SMP systems 00948 * Turn on ALP, only we are accpeting Jumbo Packets */ 00949 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD 00950 | RXCFG_STRIPCRC 00951 //| RXCFG_ALP 00952 | (RXCFG_MXDMA512) | 0, ns->base + RXCFG); 00953 00954 /* Disable priority queueing */ 00955 writel(0, ns->base + PQCR); 00956 00957 /* Enable IP checksum validation and detetion of VLAN headers. 00958 * Note: do not set the reject options as at least the 0x102 00959 * revision of the chip does not properly accept IP fragments 00960 * at least for UDP. 00961 */ 00962 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since 00963 * the MAC it calculates the packetsize AFTER stripping the VLAN 00964 * header, and if a VLAN Tagged packet of 64 bytes is received (like 00965 * a ping with a VLAN header) then the card, strips the 4 byte VLAN 00966 * tag and then checks the packet size, so if RXCFG_ARP is not enabled, 00967 * it discrards it!. These guys...... 00968 */ 00969 writel(VRCR_IPEN | VRCR_VTDEN, ns->base + VRCR); 00970 00971 /* Enable per-packet TCP/UDP/IP checksumming */ 00972 writel(VTCR_PPCHK, ns->base + VTCR); 00973 00974 /* Ramit : Enable async and sync pause frames */ 00975 // writel(0, ns->base + PCR); 00976 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K | 00977 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT), 00978 ns->base + PCR); 00979 00980 /* Disable Wake On Lan */ 00981 writel(0, ns->base + WCSR); 00982 00983 ns83820_getmac(nic, nic->node_addr); 00984 00985 if (using_dac) { 00986 dprintf(("%s: using 64 bit addressing.\n", pci->driver_name)); 00987 } 00988 00989 dprintf(("%s: DP83820 %d.%d: %! io=0x%hX\n", 00990 pci->driver_name, 00991 (unsigned) readl(ns->base + SRR) >> 8, 00992 (unsigned) readl(ns->base + SRR) & 0xff, 00993 nic->node_addr, pci->ioaddr)); 00994 00995 #ifdef PHY_CODE_IS_FINISHED 00996 ns83820_probe_phy(dev); 00997 #endif 00998 00999 ns83820_reset(nic); 01000 /* point to NIC specific routines */ 01001 nic->nic_op = &ns83820_operations; 01002 return 1; 01003 }
| DRIVER | ( | "NS83820/PCI" | , | |
| nic_driver | , | |||
| pci_driver | , | |||
| ns83820_driver | , | |||
| ns83820_probe | , | |||
| ns83820_disable | ||||
| ) |
int reset_phy = 0 [static] |
struct ns83820_private nsx [static] |
Referenced by ns83820_probe().
struct ns83820_private* ns [static] |
| struct { ... } __shared |
struct nic_operations ns83820_operations [static] |
Initial value:
{
.connect = dummy_connect,
.poll = ns83820_poll,
.transmit = ns83820_transmit,
.irq = ns83820_irq,
}
struct pci_device_id ns83820_nics[] [static] |
1.5.7.1