natsemi.h File Reference

Go to the source code of this file.

Data Structures

struct  natsemi_tx
struct  natsemi_rx
struct  natsemi_private

Defines

#define NATSEMI_HW_TIMEOUT   400
#define TX_RING_SIZE   4
#define NUM_RX_DESC   4
#define RX_BUF_SIZE   1536
#define OWN   0x80000000
#define DSIZE   0x00000FFF
#define CRC_SIZE   4
#define PHYID_AM79C874   0x0022561b
#define SRR_DP83815_C   0x0302
#define SRR_DP83815_D   0x0403
#define SRR_DP83816_A4   0x0504
#define SRR_DP83816_A5   0x0505
#define PMDCSR_VAL   0x189c
#define TSTDAT_VAL   0x0
#define DSPCFG_VAL   0x5040
#define SDCFG_VAL   0x008c
#define DSPCFG_LOCK   0x20
#define DSPCFG_COEF   0x1000
#define TSTDAT_FIXED   0xe8
#define CFG_RESET_SAVE   0xfde000
#define WCSR_RESET_SAVE   0x61f
#define RFCR_RESET_SAVE   0xf8500000;
#define eeprom_delay(ee_addr)   inl(ee_addr)
#define EE_Write0   (EE_ChipSelect)
#define EE_Write1   (EE_ChipSelect | EE_DataIn)
#define EE_CS   0x08
#define EE_SK   0x04
#define EE_DI   0x01
#define EE_DO   0x02
#define EE_MAC   7
#define EE_REG   EECtrl

Enumerations

enum  { MII_MCTRL = 0x15, MII_FX_SEL = 0x0001, MII_EN_SCRM = 0x0004 }
enum  register_offsets {
  ChipCmd = 0x00, ChipConfig = 0x04, EECtrl = 0x08, PCIBusCfg = 0x0C,
  IntrStatus = 0x10, IntrMask = 0x14, IntrEnable = 0x18, TxRingPtr = 0x20,
  TxConfig = 0x24, RxRingPtr = 0x30, RxConfig = 0x34, ClkRun = 0x3C,
  WOLCmd = 0x40, PauseCmd = 0x44, RxFilterAddr = 0x48, RxFilterData = 0x4C,
  BootRomAddr = 0x50, BootRomData = 0x54, SiliconRev = 0x58, StatsCtrl = 0x5C,
  StatsData = 0x60, RxPktErrs = 0x60, RxMissed = 0x68, RxCRCErrs = 0x64,
  PCIPM = 0x44, PhyStatus = 0xC0, MIntrCtrl = 0xC4, MIntrStatus = 0xC8,
  PGSEL = 0xCC, PMDCSR = 0xE4, TSTDAT = 0xFC, DSPCFG = 0xF4,
  SDCFG = 0x8C, BasicControl = 0x80, BasicStatus = 0x84, StationAddr = 0x00,
  RxConfig = 0x06, TxConfig = 0x07, ChipCmd = 0x08, IntrStatus = 0x0C,
  IntrEnable = 0x0E, MulticastFilter0 = 0x10, MulticastFilter1 = 0x14, RxRingPtr = 0x18,
  TxRingPtr = 0x1C, GFIFOTest = 0x54, MIIPhyAddr = 0x6C, MIIStatus = 0x6D,
  PCIBusConfig = 0x6E, MIICmd = 0x70, MIIRegAddr = 0x71, MIIData = 0x72,
  MACRegEEcsr = 0x74, ConfigA = 0x78, ConfigB = 0x79, ConfigC = 0x7A,
  ConfigD = 0x7B, RxMissed = 0x7C, RxCRCErrs = 0x7E, MiscCmd = 0x81,
  StickyHW = 0x83, IntrStatus2 = 0x84, WOLcrClr = 0xA4, WOLcgClr = 0xA7,
  PwrcsrClr = 0xAC
}
enum  ChipCmdBits {
  ChipReset = 0x100, RxReset = 0x20, TxReset = 0x10, RxOff = 0x08,
  RxOn = 0x04, TxOff = 0x02, TxOn = 0x01, CmdReset = 0x10,
  CmdRxEnb = 0x08, CmdTxEnb = 0x04, RxBufEmpty = 0x01
}
enum  ChipConfig_bits {
  CfgPhyDis = 0x200, CfgPhyRst = 0x400, CfgExtPhy = 0x1000, CfgAnegEnable = 0x2000,
  CfgAneg100 = 0x4000, CfgAnegFull = 0x8000, CfgAnegDone = 0x8000000, CfgFullDuplex = 0x20000000,
  CfgSpeed100 = 0x40000000, CfgLink = 0x80000000
}
enum  rx_mode_bits {
  RxModeMask = 0xe0, AcceptAllPhys = 0x80, AcceptBroadcast = 0x40, AcceptMulticast = 0x20,
  AcceptRunt = 0x08, ALP = 0x04, AcceptErr = 0x02, AcceptMyPhys = 0x00000000,
  RxEnable = 0x00000001, RxFlowCtrl = 0x00002000, TxEnable = 0x00040000, TxModeFDX = 0x00100000,
  TxThreshold = 0x00e00000, PS1000 = 0x00010000, PS10 = 0x00080000, FD = 0x00100000,
  AcceptErr = 0x20, AcceptRunt = 0x10, AcceptBroadcast = 0xC0000000, AcceptMulticast = 0x00200000,
  AcceptAllMulticast = 0x20000000, AcceptAllPhys = 0x10000000, AcceptMyPhys = 0x08000000, RxFilterEnable = 0x80000000,
  AcceptAllIPMulti = 0x20, AcceptMultiHash = 0x10, AcceptAll = 0x08, AcceptBroadcast = 0x04,
  AcceptMulticast = 0x02, AcceptMyPhys, AcceptErr = 0x80, AcceptRunt = 0x40,
  AcceptBroadcast = 0x20, AcceptMulticast = 0x10, AcceptAllPhys = 0x08, AcceptMyPhys = 0x02
}
enum  desc_status_bits {
  DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000, DescNoCRC = 0x10000000,
  DescPktOK = 0x08000000, RxTooLong = 0x00400000, DescOwn = 0x8000, DescEndPacket = 0x4000,
  DescEndRing = 0x2000, LastFrag = 0x80000000, DescIntrOnTx = 0x8000, DescIntrOnDMADone = 0x80000000,
  DisableAlign = 0x00000001, DescOwnded = 0x80000000, RxDescFatalErr = 0x8000, RxWholePkt = 0x0300,
  DescOwn = 0x80000000, DescEndRing = 0x02000000, DescUseLink = 0x01000000, DescWholePkt = 0x60000000,
  DescStartPkt = 0x20000000, DescEndPkt = 0x40000000, DescIntr = 0x80000000
}
enum  Intr_mask_register_bits { RxOk = 0x001, RxErr = 0x004, TxOk = 0x040, TxErr = 0x100 }
enum  MIntrCtrl_bits { MICRIntEn = 0x2 }
enum  EEPROM_Ctrl_Bits {
  EE_ShiftClk = 0x04, EE_DataIn = 0x01, EE_ChipSelect = 0x08, EE_DataOut = 0x02,
  EE_ShiftClk = 0x02, EE_Write0 = 0x801, EE_Write1 = 0x805, EE_ChipSelect = 0x801,
  EE_DataIn = 0x08
}
enum  EEPROM_Cmds {
  EE_WriteCmd = (5 << 6), EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6), EE_WriteCmd = (5 << 6),
  EE_ReadCmd = (6 << 6), EE_EraseCmd = (7 << 6)
}

Functions

 FILE_LICENCE (GPL_ANY)

Variables

static const uint8_t natsemi_ee_bits []

Define Documentation

#define NATSEMI_HW_TIMEOUT   400

Definition at line 3 of file natsemi.h.

Referenced by natsemi_reset().

#define TX_RING_SIZE   4

Definition at line 5 of file natsemi.h.

#define NUM_RX_DESC   4

Definition at line 6 of file natsemi.h.

#define RX_BUF_SIZE   1536

Definition at line 7 of file natsemi.h.

#define OWN   0x80000000

Definition at line 8 of file natsemi.h.

Referenced by natsemi_poll(), natsemi_transmit(), sis900_poll(), and sis900_transmit().

#define DSIZE   0x00000FFF

Definition at line 9 of file natsemi.h.

Referenced by ce_loader(), natsemi_poll(), sis900_poll(), and sis900_transmit().

#define CRC_SIZE   4

Definition at line 10 of file natsemi.h.

Referenced by natsemi_poll(), and sis900_poll().

#define PHYID_AM79C874   0x0022561b

Definition at line 52 of file natsemi.h.

#define SRR_DP83815_C   0x0302

Definition at line 63 of file natsemi.h.

#define SRR_DP83815_D   0x0403

Definition at line 64 of file natsemi.h.

#define SRR_DP83816_A4   0x0504

Definition at line 65 of file natsemi.h.

#define SRR_DP83816_A5   0x0505

Definition at line 66 of file natsemi.h.

#define PMDCSR_VAL   0x189c

Definition at line 116 of file natsemi.h.

#define TSTDAT_VAL   0x0

Definition at line 117 of file natsemi.h.

#define DSPCFG_VAL   0x5040

Definition at line 118 of file natsemi.h.

#define SDCFG_VAL   0x008c

Definition at line 119 of file natsemi.h.

#define DSPCFG_LOCK   0x20

Definition at line 120 of file natsemi.h.

#define DSPCFG_COEF   0x1000

Definition at line 121 of file natsemi.h.

#define TSTDAT_FIXED   0xe8

Definition at line 122 of file natsemi.h.

#define CFG_RESET_SAVE   0xfde000

Definition at line 188 of file natsemi.h.

Referenced by natsemi_reset().

#define WCSR_RESET_SAVE   0x61f

Definition at line 190 of file natsemi.h.

Referenced by natsemi_reset().

#define RFCR_RESET_SAVE   0xf8500000;

Definition at line 192 of file natsemi.h.

Referenced by natsemi_reset().

#define eeprom_delay ( ee_addr   )     inl(ee_addr)

Definition at line 197 of file natsemi.h.

#define EE_Write0   (EE_ChipSelect)

Definition at line 206 of file natsemi.h.

Referenced by eeprom_read().

#define EE_Write1   (EE_ChipSelect | EE_DataIn)

Definition at line 207 of file natsemi.h.

Referenced by eeprom_read().

#define EE_CS   0x08

Definition at line 216 of file natsemi.h.

#define EE_SK   0x04

Definition at line 217 of file natsemi.h.

#define EE_DI   0x01

Definition at line 218 of file natsemi.h.

#define EE_DO   0x02

Definition at line 219 of file natsemi.h.

#define EE_MAC   7

Definition at line 223 of file natsemi.h.

Referenced by natsemi_probe(), and rtl_probe().

#define EE_REG   EECtrl

Definition at line 224 of file natsemi.h.

Referenced by natsemi_spi_read_bit(), and natsemi_spi_write_bit().

Enumeration Type Documentation

anonymous enum

Enumerator:
MII_MCTRL 
MII_FX_SEL 
MII_EN_SCRM 

Definition at line 54 of file natsemi.h.

00054      {
00055         MII_MCTRL       = 0x15,         /* mode control register */
00056         MII_FX_SEL      = 0x0001,       /* 100BASE-FX (fiber) */
00057         MII_EN_SCRM     = 0x0004,       /* enable scrambler (tp) */
00058 };

enum register_offsets

Enumerator:
ChipCmd 
ChipConfig 
EECtrl 
PCIBusCfg 
IntrStatus 
IntrMask 
IntrEnable 
TxRingPtr 
TxConfig 
RxRingPtr 
RxConfig 
ClkRun 
WOLCmd 
PauseCmd 
RxFilterAddr 
RxFilterData 
BootRomAddr 
BootRomData 
SiliconRev 
StatsCtrl 
StatsData 
RxPktErrs 
RxMissed 
RxCRCErrs 
PCIPM 
PhyStatus 
MIntrCtrl 
MIntrStatus 
PGSEL 
PMDCSR 
TSTDAT 
DSPCFG 
SDCFG 
BasicControl 
BasicStatus 
StationAddr 
RxConfig 
TxConfig 
ChipCmd 
IntrStatus 
IntrEnable 
MulticastFilter0 
MulticastFilter1 
RxRingPtr 
TxRingPtr 
GFIFOTest 
MIIPhyAddr 
MIIStatus 
PCIBusConfig 
MIICmd 
MIIRegAddr 
MIIData 
MACRegEEcsr 
ConfigA 
ConfigB 
ConfigC 
ConfigD 
RxMissed 
RxCRCErrs 
MiscCmd 
StickyHW 
IntrStatus2 
WOLcrClr 
WOLcgClr 
PwrcsrClr 

Definition at line 73 of file natsemi.h.

00073                       {
00074     ChipCmd      = 0x00, 
00075     ChipConfig   = 0x04, 
00076     EECtrl       = 0x08, 
00077     PCIBusCfg    = 0x0C,
00078     IntrStatus   = 0x10, 
00079     IntrMask     = 0x14, 
00080     IntrEnable   = 0x18,
00081     TxRingPtr    = 0x20, 
00082     TxConfig     = 0x24,
00083     RxRingPtr    = 0x30,
00084     RxConfig     = 0x34, 
00085     ClkRun       = 0x3C,
00086     WOLCmd       = 0x40, 
00087     PauseCmd     = 0x44,
00088     RxFilterAddr = 0x48, 
00089     RxFilterData = 0x4C,
00090     BootRomAddr  = 0x50, 
00091     BootRomData  = 0x54, 
00092     SiliconRev   = 0x58, 
00093     StatsCtrl    = 0x5C,
00094     StatsData    = 0x60, 
00095     RxPktErrs    = 0x60, 
00096     RxMissed     = 0x68, 
00097     RxCRCErrs    = 0x64,
00098     PCIPM        = 0x44,
00099     PhyStatus    = 0xC0, 
00100     MIntrCtrl    = 0xC4, 
00101     MIntrStatus  = 0xC8,
00102 
00103     /* These are from the spec, around page 78... on a separate table. 
00104      */
00105     PGSEL        = 0xCC, 
00106     PMDCSR       = 0xE4, 
00107     TSTDAT       = 0xFC, 
00108     DSPCFG       = 0xF4, 
00109     SDCFG        = 0x8C,
00110     BasicControl = 0x80,        
00111     BasicStatus  = 0x84
00112             
00113 };

enum ChipCmdBits

Enumerator:
ChipReset 
RxReset 
TxReset 
RxOff 
RxOn 
TxOff 
TxOn 
CmdReset 
CmdRxEnb 
CmdTxEnb 
RxBufEmpty 

Definition at line 126 of file natsemi.h.

00126                  {
00127     ChipReset = 0x100, 
00128     RxReset   = 0x20, 
00129     TxReset   = 0x10, 
00130     RxOff     = 0x08, 
00131     RxOn      = 0x04,
00132     TxOff     = 0x02, 
00133     TxOn      = 0x01
00134 };

enum ChipConfig_bits

Enumerator:
CfgPhyDis 
CfgPhyRst 
CfgExtPhy 
CfgAnegEnable 
CfgAneg100 
CfgAnegFull 
CfgAnegDone 
CfgFullDuplex 
CfgSpeed100 
CfgLink 

Definition at line 136 of file natsemi.h.

00136                      {
00137         CfgPhyDis               = 0x200,
00138         CfgPhyRst               = 0x400,
00139         CfgExtPhy               = 0x1000,
00140         CfgAnegEnable           = 0x2000,
00141         CfgAneg100              = 0x4000,
00142         CfgAnegFull             = 0x8000,
00143         CfgAnegDone             = 0x8000000,
00144         CfgFullDuplex           = 0x20000000,
00145         CfgSpeed100             = 0x40000000,
00146         CfgLink                 = 0x80000000,
00147 };

enum rx_mode_bits

Enumerator:
RxModeMask 
AcceptAllPhys 
AcceptBroadcast 
AcceptMulticast 
AcceptRunt 
ALP 
AcceptErr 
AcceptMyPhys 
RxEnable 
RxFlowCtrl 
TxEnable 
TxModeFDX 
TxThreshold 
PS1000 
PS10 
FD 
AcceptErr 
AcceptRunt 
AcceptBroadcast 
AcceptMulticast 
AcceptAllMulticast 
AcceptAllPhys 
AcceptMyPhys 
RxFilterEnable 
AcceptAllIPMulti 
AcceptMultiHash 
AcceptAll 
AcceptBroadcast 
AcceptMulticast 
AcceptMyPhys 
AcceptErr 
AcceptRunt 
AcceptBroadcast 
AcceptMulticast 
AcceptAllPhys 
AcceptMyPhys 

Definition at line 152 of file natsemi.h.

00152                   {
00153     AcceptErr          = 0x20,
00154     AcceptRunt         = 0x10,
00155     AcceptBroadcast    = 0xC0000000,
00156     AcceptMulticast    = 0x00200000, 
00157     AcceptAllMulticast = 0x20000000,
00158     AcceptAllPhys      = 0x10000000, 
00159     AcceptMyPhys       = 0x08000000,
00160     RxFilterEnable     = 0x80000000
00161 };

enum desc_status_bits

Enumerator:
DescOwn 
DescMore 
DescIntr 
DescNoCRC 
DescPktOK 
RxTooLong 
DescOwn 
DescEndPacket 
DescEndRing 
LastFrag 
DescIntrOnTx 
DescIntrOnDMADone 
DisableAlign 
DescOwnded 
RxDescFatalErr 
RxWholePkt 
DescOwn 
DescEndRing 
DescUseLink 
DescWholePkt 
DescStartPkt 
DescEndPkt 
DescIntr 

Definition at line 165 of file natsemi.h.

00165                       {
00166     DescOwn   = 0x80000000, 
00167     DescMore  = 0x40000000, 
00168     DescIntr  = 0x20000000,
00169     DescNoCRC = 0x10000000,
00170     DescPktOK = 0x08000000, 
00171     RxTooLong = 0x00400000
00172 };

enum Intr_mask_register_bits

Enumerator:
RxOk 
RxErr 
TxOk 
TxErr 

Definition at line 176 of file natsemi.h.

00176                              {
00177     RxOk       = 0x001,
00178     RxErr      = 0x004,
00179     TxOk       = 0x040,
00180     TxErr      = 0x100 
00181 };

enum MIntrCtrl_bits

Enumerator:
MICRIntEn 

Definition at line 183 of file natsemi.h.

00183                     {
00184   MICRIntEn               = 0x2,
00185 };

enum EEPROM_Ctrl_Bits

Enumerator:
EE_ShiftClk 
EE_DataIn 
EE_ChipSelect 
EE_DataOut 
EE_ShiftClk 
EE_Write0 
EE_Write1 
EE_ChipSelect 
EE_DataIn 

Definition at line 199 of file natsemi.h.

00199                       {
00200         EE_ShiftClk   = 0x04,
00201         EE_DataIn     = 0x01,
00202         EE_ChipSelect = 0x08,
00203         EE_DataOut    = 0x02
00204 };

enum EEPROM_Cmds

Enumerator:
EE_WriteCmd 
EE_ReadCmd 
EE_EraseCmd 
EE_WriteCmd 
EE_ReadCmd 
EE_EraseCmd 

Definition at line 210 of file natsemi.h.

00210                  {
00211   EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
00212 };

Function Documentation

FILE_LICENCE ( GPL_ANY   ) 

Variable Documentation

const uint8_t natsemi_ee_bits[] [static]

Initial value:

 {
        [SPI_BIT_SCLK]  = EE_SK,
        [SPI_BIT_MOSI]  = EE_DI,
        [SPI_BIT_MISO]  = EE_DO,
        [SPI_BIT_SS(0)] = EE_CS,
}

Definition at line 226 of file natsemi.h.

Referenced by natsemi_spi_read_bit(), and natsemi_spi_write_bit().

Generated on Tue Apr 6 20:01:36 2010 for gPXE by  doxygen 1.5.7.1