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| #define MXGEFW_VERSION_MAJOR 1 |
Definition at line 24 of file myri10ge_mcp.h.
| #define MXGEFW_VERSION_MINOR 4 |
Definition at line 25 of file myri10ge_mcp.h.
| #define MXGEFW_FLAGS_SMALL 0x1 |
| #define MXGEFW_FLAGS_TSO_HDR 0x1 |
Definition at line 113 of file myri10ge_mcp.h.
| #define MXGEFW_FLAGS_FIRST 0x2 |
| #define MXGEFW_FLAGS_ALIGN_ODD 0x4 |
Definition at line 115 of file myri10ge_mcp.h.
| #define MXGEFW_FLAGS_CKSUM 0x8 |
Definition at line 116 of file myri10ge_mcp.h.
| #define MXGEFW_FLAGS_TSO_LAST 0x8 |
Definition at line 117 of file myri10ge_mcp.h.
| #define MXGEFW_FLAGS_NO_TSO 0x10 |
| #define MXGEFW_FLAGS_TSO_CHOP 0x10 |
Definition at line 119 of file myri10ge_mcp.h.
| #define MXGEFW_FLAGS_TSO_PLD 0x20 |
Definition at line 120 of file myri10ge_mcp.h.
| #define MXGEFW_SEND_SMALL_SIZE 1520 |
Definition at line 122 of file myri10ge_mcp.h.
| #define MXGEFW_MAX_MTU 9400 |
Definition at line 123 of file myri10ge_mcp.h.
| #define MXGEFW_MAX_SEND_DESC 12 |
Definition at line 131 of file myri10ge_mcp.h.
| #define MXGEFW_PAD 2 |
Definition at line 132 of file myri10ge_mcp.h.
Referenced by myri10ge_net_open(), and myri10ge_net_poll().
| #define MXGEFW_BOOT_HANDOFF 0xfc0000 |
Definition at line 157 of file myri10ge_mcp.h.
| #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 |
Definition at line 158 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_CMD 0xf80000 |
| #define MXGEFW_ETH_SEND_4 0x200000 |
Definition at line 161 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_SEND_1 0x240000 |
Definition at line 162 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_SEND_2 0x280000 |
Definition at line 163 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_SEND_3 0x2c0000 |
Definition at line 164 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_RECV_SMALL 0x300000 |
Definition at line 165 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_RECV_BIG 0x340000 |
Definition at line 166 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_SEND_GO 0x380000 |
Definition at line 167 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_SEND_STOP 0x3C0000 |
Definition at line 168 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_SEND | ( | n | ) | (0x200000 + (((n) & 0x03) * 0x40000)) |
Definition at line 170 of file myri10ge_mcp.h.
| #define MXGEFW_ETH_SEND_OFFSET | ( | n | ) | (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) |
Definition at line 171 of file myri10ge_mcp.h.
| #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) |
Referenced by myri10ge_net_open().
| #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 |
| #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 |
| #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 |
| #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 |
| #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 |
| #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 |
| #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 |
| #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 |
| #define MXGEFW_TSO_MODE_LINUX 0 |
| #define MXGEFW_TSO_MODE_NDIS 1 |
| #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 |
| #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 |
| #define MXGEFW_OLD_IRQ_DATA_LEN 40 |
Definition at line 466 of file myri10ge_mcp.h.
| #define MXGEFW_LINK_DOWN 0 |
Definition at line 479 of file myri10ge_mcp.h.
| #define MXGEFW_LINK_UP 1 |
| #define MXGEFW_LINK_MYRINET 2 |
Definition at line 481 of file myri10ge_mcp.h.
| #define MXGEFW_LINK_UNKNOWN 3 |
Definition at line 482 of file myri10ge_mcp.h.
| #define MXGEFW_NETQ_FILTERTYPE_NONE 0 |
Definition at line 509 of file myri10ge_mcp.h.
| #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 |
Definition at line 510 of file myri10ge_mcp.h.
| #define MXGEFW_NETQ_FILTERTYPE_VLAN 2 |
Definition at line 511 of file myri10ge_mcp.h.
| #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 |
Definition at line 512 of file myri10ge_mcp.h.
| typedef struct mcp_dma_addr mcp_dma_addr_t |
Definition at line 45 of file myri10ge_mcp.h.
| typedef struct mcp_slot mcp_slot_t |
Definition at line 52 of file myri10ge_mcp.h.
Definition at line 85 of file myri10ge_mcp.h.
| typedef struct mcp_cmd_response mcp_cmd_response_t |
Definition at line 92 of file myri10ge_mcp.h.
| typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t |
Definition at line 129 of file myri10ge_mcp.h.
| typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t |
Definition at line 145 of file myri10ge_mcp.h.
| typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t |
Definition at line 152 of file myri10ge_mcp.h.
| typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t |
Definition at line 443 of file myri10ge_mcp.h.
| typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t |
Definition at line 463 of file myri10ge_mcp.h.
| typedef struct mcp_irq_data mcp_irq_data_t |
Definition at line 497 of file myri10ge_mcp.h.
Definition at line 173 of file myri10ge_mcp.h.
00173 { 00174 MXGEFW_CMD_NONE = 0, 00175 /* Reset the mcp, it is left in a safe state, waiting 00176 for the driver to set all its parameters */ 00177 MXGEFW_CMD_RESET = 1, 00178 00179 /* get the version number of the current firmware.. 00180 (may be available in the eeprom strings..? */ 00181 MXGEFW_GET_MCP_VERSION = 2, 00182 00183 00184 /* Parameters which must be set by the driver before it can 00185 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 00186 MXGEFW_CMD_RESET is issued */ 00187 00188 MXGEFW_CMD_SET_INTRQ_DMA = 3, 00189 /* data0 = LSW of the host address 00190 * data1 = MSW of the host address 00191 * data2 = slice number if multiple slices are used 00192 */ 00193 00194 MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 00195 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 00196 00197 00198 /* Parameters which refer to lanai SRAM addresses where the 00199 driver must issue PIO writes for various things */ 00200 00201 MXGEFW_CMD_GET_SEND_OFFSET = 6, 00202 MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 00203 MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 00204 /* data0 = slice number if multiple slices are used */ 00205 00206 MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 00207 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 00208 00209 /* Parameters which refer to rings stored on the MCP, 00210 and whose size is controlled by the mcp */ 00211 00212 MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 00213 MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 00214 00215 /* Parameters which refer to rings stored in the host, 00216 and whose size is controlled by the host. Note that 00217 all must be physically contiguous and must contain 00218 a power of 2 number of entries. */ 00219 00220 MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 00221 #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) 00222 00223 /* command to bring ethernet interface up. Above parameters 00224 (plus mtu & mac address) must have been exchanged prior 00225 to issuing this command */ 00226 MXGEFW_CMD_ETHERNET_UP = 14, 00227 00228 /* command to bring ethernet interface down. No further sends 00229 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 00230 is issued, and all interrupt queues must be flushed prior 00231 to ack'ing this command */ 00232 00233 MXGEFW_CMD_ETHERNET_DOWN = 15, 00234 00235 /* commands the driver may issue live, without resetting 00236 the nic. Note that increasing the mtu "live" should 00237 only be done if the driver has already supplied buffers 00238 sufficiently large to handle the new mtu. Decreasing 00239 the mtu live is safe */ 00240 00241 MXGEFW_CMD_SET_MTU = 16, 00242 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 00243 MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 00244 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 00245 00246 MXGEFW_ENABLE_PROMISC = 20, 00247 MXGEFW_DISABLE_PROMISC = 21, 00248 MXGEFW_SET_MAC_ADDRESS = 22, 00249 00250 MXGEFW_ENABLE_FLOW_CONTROL = 23, 00251 MXGEFW_DISABLE_FLOW_CONTROL = 24, 00252 00253 /* do a DMA test 00254 data0,data1 = DMA address 00255 data2 = RDMA length (MSH), WDMA length (LSH) 00256 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 00257 */ 00258 MXGEFW_DMA_TEST = 25, 00259 00260 MXGEFW_ENABLE_ALLMULTI = 26, 00261 MXGEFW_DISABLE_ALLMULTI = 27, 00262 00263 /* returns MXGEFW_CMD_ERROR_MULTICAST 00264 if there is no room in the cache 00265 data0,MSH(data1) = multicast group address */ 00266 MXGEFW_JOIN_MULTICAST_GROUP = 28, 00267 /* returns MXGEFW_CMD_ERROR_MULTICAST 00268 if the address is not in the cache, 00269 or is equal to FF-FF-FF-FF-FF-FF 00270 data0,MSH(data1) = multicast group address */ 00271 MXGEFW_LEAVE_MULTICAST_GROUP = 29, 00272 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 00273 00274 MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 00275 /* data0, data1 = bus addr, 00276 * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 00277 * adding new stuff to mcp_irq_data without changing the ABI 00278 * 00279 * If multiple slices are used, data2 contains both the size of the 00280 * structure (in the lower 16 bits) and the slice number 00281 * (in the upper 16 bits). 00282 */ 00283 00284 MXGEFW_CMD_UNALIGNED_TEST = 32, 00285 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 00286 chipset */ 00287 00288 MXGEFW_CMD_UNALIGNED_STATUS = 33, 00289 /* return data = boolean, true if the chipset is known to be unaligned */ 00290 00291 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 00292 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 00293 * 0 indicates that the NIC consumes as many buffers as they are required 00294 * for packet. This is the default behavior. 00295 * A power of 2 number indicates that the NIC always uses the specified 00296 * number of buffers for each big receive packet. 00297 * It is up to the driver to ensure that this value is big enough for 00298 * the NIC to be able to receive maximum-sized packets. 00299 */ 00300 00301 MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 00302 MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 00303 /* data0 = number of slices n (0, 1, ..., n-1) to enable 00304 * data1 = interrupt mode | use of multiple transmit queues. 00305 * 0=share one INTx/MSI. 00306 * 1=use one MSI-X per queue. 00307 * If all queues share one interrupt, the driver must have set 00308 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 00309 * 2=enable both receive and send queues. 00310 * Without this bit set, only one send queue (slice 0's send queue) 00311 * is enabled. The receive queues are always enabled. 00312 */ 00313 #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 00314 #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 00315 #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 00316 00317 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 00318 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 00319 /* data0, data1 = bus address lsw, msw */ 00320 MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 00321 /* get the offset of the indirection table */ 00322 MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 00323 /* set the size of the indirection table */ 00324 MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 00325 /* get the offset of the secret key */ 00326 MXGEFW_CMD_RSS_KEY_UPDATED = 42, 00327 /* tell nic that the secret key's been updated */ 00328 MXGEFW_CMD_SET_RSS_ENABLE = 43, 00329 /* data0 = enable/disable rss 00330 * 0: disable rss. nic does not distribute receive packets. 00331 * 1: enable rss. nic distributes receive packets among queues. 00332 * data1 = hash type 00333 * 1: IPV4 (required by RSS) 00334 * 2: TCP_IPV4 (required by RSS) 00335 * 3: IPV4 | TCP_IPV4 (required by RSS) 00336 * 4: source port 00337 * 5: source port + destination port 00338 */ 00339 #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 00340 #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 00341 #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 00342 #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 00343 #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 00344 00345 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 00346 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 00347 * If the header size of a IPv6 TSO packet is larger than the specified 00348 * value, then the driver must not use TSO. 00349 * This size restriction only applies to IPv6 TSO. 00350 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 00351 * always has enough header buffer to store maximum-sized headers. 00352 */ 00353 00354 MXGEFW_CMD_SET_TSO_MODE = 45, 00355 /* data0 = TSO mode. 00356 * 0: Linux/FreeBSD style (NIC default) 00357 * 1: NDIS/NetBSD style 00358 */ 00359 #define MXGEFW_TSO_MODE_LINUX 0 00360 #define MXGEFW_TSO_MODE_NDIS 1 00361 00362 MXGEFW_CMD_MDIO_READ = 46, 00363 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 00364 MXGEFW_CMD_MDIO_WRITE = 47, 00365 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 00366 00367 MXGEFW_CMD_I2C_READ = 48, 00368 /* Starts to get a fresh copy of one byte or of the module i2c table, the 00369 * obtained data is cached inside the xaui-xfi chip : 00370 * data0 : 0 => get one byte, 1=> get 256 bytes 00371 * data1 : If data0 == 0: location to refresh 00372 * bit 7:0 register location 00373 * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 00374 * bit 23:16 is the i2c bus number (for multi-port NICs) 00375 * If data0 == 1: unused 00376 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 00377 * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 00378 * will return MXGEFW_CMD_ERROR_BUSY 00379 */ 00380 MXGEFW_CMD_I2C_BYTE = 49, 00381 /* Return the last obtained copy of a given byte in the xfp i2c table 00382 * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 00383 * data0 : index of the desired table entry 00384 * Return data = the byte stored at the requested index in the table 00385 */ 00386 00387 MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 00388 /* Return data = NIC memory offset of mcp_vpump_public_global */ 00389 MXGEFW_CMD_RESET_VPUMP = 51, 00390 /* Resets the VPUMP state */ 00391 00392 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 00393 /* data0 = mcp_slot type to use. 00394 * 0 = the default 4B mcp_slot 00395 * 1 = 8B mcp_slot_8 00396 */ 00397 #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 00398 #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 00399 00400 MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 00401 /* set the throttle factor for ethp_z8e 00402 data0 = throttle_factor 00403 throttle_factor = 256 * pcie-raw-speed / tx_speed 00404 tx_speed = 256 * pcie-raw-speed / throttle_factor 00405 00406 For PCI-E x8: pcie-raw-speed == 16Gb/s 00407 For PCI-E x4: pcie-raw-speed == 8Gb/s 00408 00409 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 00410 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 00411 00412 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 00413 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 00414 */ 00415 00416 MXGEFW_CMD_VPUMP_UP = 54, 00417 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 00418 MXGEFW_CMD_GET_VPUMP_CLK = 55, 00419 /* Get the lanai clock */ 00420 00421 MXGEFW_CMD_GET_DCA_OFFSET = 56, 00422 /* offset of dca control for WDMAs */ 00423 00424 /* VMWare NetQueue commands */ 00425 MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 00426 MXGEFW_CMD_NETQ_ADD_FILTER = 58, 00427 /* data0 = filter_id << 16 | queue << 8 | type */ 00428 /* data1 = MS4 of MAC Addr */ 00429 /* data2 = LS2_MAC << 16 | VLAN_tag */ 00430 MXGEFW_CMD_NETQ_DEL_FILTER = 59, 00431 /* data0 = filter_id */ 00432 MXGEFW_CMD_NETQ_QUERY1 = 60, 00433 MXGEFW_CMD_NETQ_QUERY2 = 61, 00434 MXGEFW_CMD_NETQ_QUERY3 = 62, 00435 MXGEFW_CMD_NETQ_QUERY4 = 63, 00436 00437 MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 00438 /* When set, small receive buffers can cross page boundaries. 00439 * Both small and big receive buffers may start at any address. 00440 * This option has performance implications, so use with caution. 00441 */ 00442 };
Definition at line 446 of file myri10ge_mcp.h.
00446 { 00447 MXGEFW_CMD_OK = 0, 00448 MXGEFW_CMD_UNKNOWN = 1, 00449 MXGEFW_CMD_ERROR_RANGE = 2, 00450 MXGEFW_CMD_ERROR_BUSY = 3, 00451 MXGEFW_CMD_ERROR_EMPTY = 4, 00452 MXGEFW_CMD_ERROR_CLOSED = 5, 00453 MXGEFW_CMD_ERROR_HASH_ERROR = 6, 00454 MXGEFW_CMD_ERROR_BAD_PORT = 7, 00455 MXGEFW_CMD_ERROR_RESOURCES = 8, 00456 MXGEFW_CMD_ERROR_MULTICAST = 9, 00457 MXGEFW_CMD_ERROR_UNALIGNED = 10, 00458 MXGEFW_CMD_ERROR_NO_MDIO = 11, 00459 MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 00460 MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 00461 MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 00462 };
| FILE_LICENCE | ( | GPL2_ONLY | ) |
1.5.7.1