#include "etherboot.h"#include "nic.h"#include <gpxe/pci.h>#include <gpxe/ethernet.h>#include <mii.h>Go to the source code of this file.
Data Structures | |
| struct | mtd_desc |
| struct | mtd_private |
Defines | |
| #define | virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr)) |
| #define | le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr)) |
| #define | get_unaligned(ptr) (*(ptr)) |
| #define | TX_RING_SIZE 2 |
| #define | TX_QUEUE_LEN 10 |
| #define | RX_RING_SIZE 4 |
| #define | HZ 100 |
| #define | TX_TIME_OUT (6*HZ) |
| #define | PKT_BUF_SZ 1536 |
| #define | MASK_MIIR_MII_READ 0x00000000 |
| #define | MASK_MIIR_MII_WRITE 0x00000008 |
| #define | MASK_MIIR_MII_MDO 0x00000004 |
| #define | MASK_MIIR_MII_MDI 0x00000002 |
| #define | MASK_MIIR_MII_MDC 0x00000001 |
| #define | OP_READ 0x6000 |
| #define | OP_WRITE 0x5002 |
| #define | MysonPHYID 0xd0000302 |
| #define | MysonPHYID0 0x0302 |
| #define | StatusRegister 18 |
| #define | SPEED100 0x0400 |
| #define | FULLMODE 0x0800 |
| #define | SeeqPHYID0 0x0016 |
| #define | MIIRegister18 18 |
| #define | SPD_DET_100 0x80 |
| #define | DPLX_DET_FULL 0x40 |
| #define | AhdocPHYID0 0x0022 |
| #define | DiagnosticReg 18 |
| #define | DPLX_FULL 0x0800 |
| #define | Speed_100 0x0400 |
| #define | MarvellPHYID0 0x0141 |
| #define | LevelOnePHYID0 0x0013 |
| #define | MII1000BaseTControlReg 9 |
| #define | MII1000BaseTStatusReg 10 |
| #define | SpecificReg 17 |
| #define | PHYAbletoPerform1000FullDuplex 0x0200 |
| #define | PHYAbletoPerform1000HalfDuplex 0x0100 |
| #define | PHY1000AbilityMask 0x300 |
| #define | SpeedMask 0x0c000 |
| #define | Speed_1000M 0x08000 |
| #define | Speed_100M 0x4000 |
| #define | Speed_10M 0 |
| #define | Full_Duplex 0x2000 |
| #define | LXT1000_100M 0x08000 |
| #define | LXT1000_1000M 0x0c000 |
| #define | LXT1000_Full 0x200 |
| #define | LinkIsUp 0x0004 |
| #define | LinkIsUp2 0x00040000 |
| #define | txb mtd80x_bufs.txb |
| #define | rxb mtd80x_bufs.rxb |
Enumerations | |
| enum | phy_type_flags { MysonPHY = 1, AhdocPHY = 2, SeeqPHY = 3, MarvellPHY = 4, Myson981 = 5, LevelOnePHY = 6, OtherPHY = 10 } |
| enum | chip_capability_flags { HAS_MII_XCVR, HAS_CHIP_XCVR, CanHaveMII = 1, KendinPktDropBug = 2, CanHaveMII = 1, HasBrokenTx = 2 } |
| enum | mtd_offsets { PAR0 = 0x0, PAR1 = 0x04, MAR0 = 0x08, MAR1 = 0x0C, FAR0 = 0x10, FAR1 = 0x14, TCRRCR = 0x18, BCR = 0x1C, TXPDR = 0x20, RXPDR = 0x24, RXCWP = 0x28, TXLBA = 0x2C, RXLBA = 0x30, ISR = 0x34, IMR = 0x38, FTH = 0x3C, MANAGEMENT = 0x40, TALLY = 0x44, TSR = 0x48, BMCRSR = 0x4c, PHYIDENTIFIER = 0x50, ANARANLPAR = 0x54, ANEROCR = 0x58, BPREMRPSR = 0x5c } |
| enum | intr_status_bits { RFCON = 0x00020000, RFCOFF = 0x00010000, LSCStatus = 0x00008000, ANCStatus = 0x00004000, FBE = 0x00002000, FBEMask = 0x00001800, ParityErr = 0x00000000, TargetErr = 0x00001000, MasterErr = 0x00000800, TUNF = 0x00000400, ROVF = 0x00000200, ETI = 0x00000100, ERI = 0x00000080, CNTOVF = 0x00000040, RBU = 0x00000020, TBU = 0x00000010, TI = 0x00000008, RI = 0x00000004, RxErr = 0x00000002, IntrSummary = 0x0001, IntrPCIErr = 0x0002, IntrMACCtrl = 0x0008, IntrTxDone = 0x0004, IntrRxDone = 0x0010, IntrRxStart = 0x0020, IntrDrvRqst = 0x0040, StatsMax = 0x0080, LinkChange = 0x0100, IntrTxDMADone = 0x0200, IntrRxDMADone = 0x0400, IntrRxDone = 0x0001, IntrRxErr = 0x0004, IntrRxEmpty = 0x0020, IntrTxDone = 0x0002, IntrTxError = 0x0008, IntrTxUnderrun = 0x0210, IntrPCIErr = 0x0040, IntrStatsMax = 0x0080, IntrRxEarly = 0x0100, IntrRxOverflow = 0x0400, IntrRxDropped = 0x0800, IntrRxNoBuf = 0x1000, IntrTxAborted = 0x2000, IntrLinkChange = 0x4000, IntrRxWakeUp = 0x8000, IntrNormalSummary = 0x0003, IntrAbnormalSummary = 0xC260, IntrTxDescRace = 0x080000, IntrTxErrSummary = 0x082218, NormalIntr = 0x10000, AbnormalIntr = 0x8000, IntrPCIErr = 0x2000, TimerInt = 0x800, IntrRxDied = 0x100, RxNoBuf = 0x80, IntrRxDone = 0x40, TxFIFOUnderflow = 0x20, RxErrIntr = 0x10, TxIdle = 0x04, IntrTxStopped = 0x02, IntrTxDone = 0x01 } |
| enum | rx_mode_bits { RxModeMask = 0xe0, AcceptAllPhys = 0x80, AcceptBroadcast = 0x40, AcceptMulticast = 0x20, AcceptRunt = 0x08, ALP = 0x04, AcceptErr = 0x02, AcceptMyPhys = 0x00000000, RxEnable = 0x00000001, RxFlowCtrl = 0x00002000, TxEnable = 0x00040000, TxModeFDX = 0x00100000, TxThreshold = 0x00e00000, PS1000 = 0x00010000, PS10 = 0x00080000, FD = 0x00100000, AcceptErr = 0x20, AcceptRunt = 0x10, AcceptBroadcast = 0xC0000000, AcceptMulticast = 0x00200000, AcceptAllMulticast = 0x20000000, AcceptAllPhys = 0x10000000, AcceptMyPhys = 0x08000000, RxFilterEnable = 0x80000000, AcceptAllIPMulti = 0x20, AcceptMultiHash = 0x10, AcceptAll = 0x08, AcceptBroadcast = 0x04, AcceptMulticast = 0x02, AcceptMyPhys, AcceptErr = 0x80, AcceptRunt = 0x40, AcceptBroadcast = 0x20, AcceptMulticast = 0x10, AcceptAllPhys = 0x08, AcceptMyPhys = 0x02 } |
| enum | rx_desc_status_bits { RXOWN = 0x80000000, FLNGMASK = 0x0fff0000, FLNGShift = 16, MARSTATUS = 0x00004000, BARSTATUS = 0x00002000, PHYSTATUS = 0x00001000, RXFSD = 0x00000800, RXLSD = 0x00000400, ErrorSummary = 0x80, RUNT = 0x40, LONG = 0x20, FAE = 0x10, CRC = 0x08, RXER = 0x04 } |
| enum | rx_desc_control_bits { RXIC = 0x00800000, RBSShift = 0 } |
| enum | tx_desc_status_bits { TXOWN = 0x80000000, JABTO = 0x00004000, CSL = 0x00002000, LC = 0x00001000, EC = 0x00000800, UDF = 0x00000400, DFR = 0x00000200, HF = 0x00000100, NCRMask = 0x000000ff, NCRShift = 0 } |
| enum | tx_desc_control_bits { TXIC = 0x80000000, ETIControl = 0x40000000, TXLD = 0x20000000, TXFD = 0x10000000, CRCEnable = 0x08000000, PADEnable = 0x04000000, RetryTxLC = 0x02000000, PKTSMask = 0x3ff800, PKTSShift = 11, TBSMask = 0x000007ff, TBSShift = 0 } |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| static int | mdio_read (struct nic *, int phy_id, int location) |
| static void | getlinktype (struct nic *) |
| static void | getlinkstatus (struct nic *) |
| static void | set_rx_mode (struct nic *) |
| static void | init_ring (struct nic *nic __unused) |
| static void | mtd_reset (struct nic *nic) |
| static int | mtd_poll (struct nic *nic, __unused int retrieve) |
| static void | mtd_transmit (struct nic *nic, const char *dest, unsigned int type, unsigned int size, const char *data) |
| static void | mtd_disable (struct nic *nic) |
| PCI_DRIVER (mtd80x_driver, mtd80x_nics, PCI_NO_CLASS) | |
| static int | mtd_probe (struct nic *nic, struct pci_device *pci) |
| static void | set_rx_mode (struct nic *nic __unused) |
| static unsigned int | m80x_read_tick (void) |
| static void | m80x_delay (unsigned int interval) |
| static u32 | m80x_send_cmd_to_phy (long miiport, int opcode, int phyad, int regad) |
| static int | mdio_read (struct nic *nic __unused, int phyad, int regad) |
| DRIVER ("MTD80X", nic_driver, pci_driver, mtd80x_driver, mtd_probe, mtd_disable) | |
Variables | |
| struct { | |
| u8 txb [PKT_BUF_SZ *TX_RING_SIZE] | |
| u8 rxb [PKT_BUF_SZ *RX_RING_SIZE] | |
| } | __shared |
| static struct mtd_private | mtdx |
| static struct nic_operations | mtd_operations |
| static struct pci_device_id | mtd80x_nics [] |
| #define virt_to_le32desc | ( | addr | ) | cpu_to_le32(virt_to_bus(addr)) |
| #define le32desc_to_virt | ( | addr | ) | bus_to_virt(le32_to_cpu(addr)) |
| #define get_unaligned | ( | ptr | ) | (*(ptr)) |
| #define MASK_MIIR_MII_WRITE 0x00000008 |
| #define MASK_MIIR_MII_MDO 0x00000004 |
| #define MASK_MIIR_MII_MDI 0x00000002 |
| #define MASK_MIIR_MII_MDC 0x00000001 |
| #define OP_READ 0x6000 |
| #define MysonPHYID 0xd0000302 |
| #define MysonPHYID0 0x0302 |
| #define StatusRegister 18 |
| #define SPEED100 0x0400 |
| #define FULLMODE 0x0800 |
| #define SeeqPHYID0 0x0016 |
| #define MIIRegister18 18 |
| #define SPD_DET_100 0x80 |
| #define DPLX_DET_FULL 0x40 |
| #define AhdocPHYID0 0x0022 |
| #define DiagnosticReg 18 |
| #define DPLX_FULL 0x0800 |
| #define Speed_100 0x0400 |
| #define MarvellPHYID0 0x0141 |
| #define LevelOnePHYID0 0x0013 |
| #define SpecificReg 17 |
| #define SpeedMask 0x0c000 |
| #define Speed_1000M 0x08000 |
| #define Speed_100M 0x4000 |
| #define Full_Duplex 0x2000 |
| #define LXT1000_100M 0x08000 |
| #define LXT1000_1000M 0x0c000 |
| #define LXT1000_Full 0x200 |
| #define LinkIsUp2 0x00040000 |
| #define txb mtd80x_bufs.txb |
| #define rxb mtd80x_bufs.rxb |
| enum phy_type_flags |
Definition at line 66 of file mtd80x.c.
00066 { 00067 MysonPHY = 1, 00068 AhdocPHY = 2, 00069 SeeqPHY = 3, 00070 MarvellPHY = 4, 00071 Myson981 = 5, 00072 LevelOnePHY = 6, 00073 OtherPHY = 10, 00074 };
| enum mtd_offsets |
| PAR0 | |
| PAR1 | |
| MAR0 | |
| MAR1 | |
| FAR0 | |
| FAR1 | |
| TCRRCR | |
| BCR | |
| TXPDR | |
| RXPDR | |
| RXCWP | |
| TXLBA | |
| RXLBA | |
| ISR | |
| IMR | |
| FTH | |
| MANAGEMENT | |
| TALLY | |
| TSR | |
| BMCRSR | |
| PHYIDENTIFIER | |
| ANARANLPAR | |
| ANEROCR | |
| BPREMRPSR |
Definition at line 98 of file mtd80x.c.
00098 { 00099 PAR0 = 0x0, /* physical address 0-3 */ 00100 PAR1 = 0x04, /* physical address 4-5 */ 00101 MAR0 = 0x08, /* multicast address 0-3 */ 00102 MAR1 = 0x0C, /* multicast address 4-7 */ 00103 FAR0 = 0x10, /* flow-control address 0-3 */ 00104 FAR1 = 0x14, /* flow-control address 4-5 */ 00105 TCRRCR = 0x18, /* receive & transmit configuration */ 00106 BCR = 0x1C, /* bus command */ 00107 TXPDR = 0x20, /* transmit polling demand */ 00108 RXPDR = 0x24, /* receive polling demand */ 00109 RXCWP = 0x28, /* receive current word pointer */ 00110 TXLBA = 0x2C, /* transmit list base address */ 00111 RXLBA = 0x30, /* receive list base address */ 00112 ISR = 0x34, /* interrupt status */ 00113 IMR = 0x38, /* interrupt mask */ 00114 FTH = 0x3C, /* flow control high/low threshold */ 00115 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */ 00116 TALLY = 0x44, /* tally counters for crc and mpa */ 00117 TSR = 0x48, /* tally counter for transmit status */ 00118 BMCRSR = 0x4c, /* basic mode control and status */ 00119 PHYIDENTIFIER = 0x50, /* phy identifier */ 00120 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link 00121 partner ability */ 00122 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */ 00123 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */ 00124 };
| enum intr_status_bits |
Definition at line 128 of file mtd80x.c.
00128 { 00129 RFCON = 0x00020000, /* receive flow control xon packet */ 00130 RFCOFF = 0x00010000, /* receive flow control xoff packet */ 00131 LSCStatus = 0x00008000, /* link status change */ 00132 ANCStatus = 0x00004000, /* autonegotiation completed */ 00133 FBE = 0x00002000, /* fatal bus error */ 00134 FBEMask = 0x00001800, /* mask bit12-11 */ 00135 ParityErr = 0x00000000, /* parity error */ 00136 TargetErr = 0x00001000, /* target abort */ 00137 MasterErr = 0x00000800, /* master error */ 00138 TUNF = 0x00000400, /* transmit underflow */ 00139 ROVF = 0x00000200, /* receive overflow */ 00140 ETI = 0x00000100, /* transmit early int */ 00141 ERI = 0x00000080, /* receive early int */ 00142 CNTOVF = 0x00000040, /* counter overflow */ 00143 RBU = 0x00000020, /* receive buffer unavailable */ 00144 TBU = 0x00000010, /* transmit buffer unavilable */ 00145 TI = 0x00000008, /* transmit interrupt */ 00146 RI = 0x00000004, /* receive interrupt */ 00147 RxErr = 0x00000002, /* receive error */ 00148 };
| enum rx_mode_bits |
Definition at line 151 of file mtd80x.c.
00151 { 00152 RxModeMask = 0xe0, 00153 AcceptAllPhys = 0x80, /* promiscuous mode */ 00154 AcceptBroadcast = 0x40, /* accept broadcast */ 00155 AcceptMulticast = 0x20, /* accept mutlicast */ 00156 AcceptRunt = 0x08, /* receive runt pkt */ 00157 ALP = 0x04, /* receive long pkt */ 00158 AcceptErr = 0x02, /* receive error pkt */ 00159 00160 AcceptMyPhys = 0x00000000, 00161 RxEnable = 0x00000001, 00162 RxFlowCtrl = 0x00002000, 00163 TxEnable = 0x00040000, 00164 TxModeFDX = 0x00100000, 00165 TxThreshold = 0x00e00000, 00166 00167 PS1000 = 0x00010000, 00168 PS10 = 0x00080000, 00169 FD = 0x00100000, 00170 };
| enum rx_desc_status_bits |
| RXOWN | |
| FLNGMASK | |
| FLNGShift | |
| MARSTATUS | |
| BARSTATUS | |
| PHYSTATUS | |
| RXFSD | |
| RXLSD | |
| ErrorSummary | |
| RUNT | |
| LONG | |
| FAE | |
| CRC | |
| RXER |
Definition at line 173 of file mtd80x.c.
00173 { 00174 RXOWN = 0x80000000, /* own bit */ 00175 FLNGMASK = 0x0fff0000, /* frame length */ 00176 FLNGShift = 16, 00177 MARSTATUS = 0x00004000, /* multicast address received */ 00178 BARSTATUS = 0x00002000, /* broadcast address received */ 00179 PHYSTATUS = 0x00001000, /* physical address received */ 00180 RXFSD = 0x00000800, /* first descriptor */ 00181 RXLSD = 0x00000400, /* last descriptor */ 00182 ErrorSummary = 0x80, /* error summary */ 00183 RUNT = 0x40, /* runt packet received */ 00184 LONG = 0x20, /* long packet received */ 00185 FAE = 0x10, /* frame align error */ 00186 CRC = 0x08, /* crc error */ 00187 RXER = 0x04, /* receive error */ 00188 };
| enum rx_desc_control_bits |
| enum tx_desc_status_bits |
Definition at line 195 of file mtd80x.c.
00195 { 00196 TXOWN = 0x80000000, /* own bit */ 00197 JABTO = 0x00004000, /* jabber timeout */ 00198 CSL = 0x00002000, /* carrier sense lost */ 00199 LC = 0x00001000, /* late collision */ 00200 EC = 0x00000800, /* excessive collision */ 00201 UDF = 0x00000400, /* fifo underflow */ 00202 DFR = 0x00000200, /* deferred */ 00203 HF = 0x00000100, /* heartbeat fail */ 00204 NCRMask = 0x000000ff, /* collision retry count */ 00205 NCRShift = 0, 00206 };
| enum tx_desc_control_bits |
| TXIC | |
| ETIControl | |
| TXLD | |
| TXFD | |
| CRCEnable | |
| PADEnable | |
| RetryTxLC | |
| PKTSMask | |
| PKTSShift | |
| TBSMask | |
| TBSShift |
Definition at line 208 of file mtd80x.c.
00208 { 00209 TXIC = 0x80000000, /* interrupt control */ 00210 ETIControl = 0x40000000, /* early transmit interrupt */ 00211 TXLD = 0x20000000, /* last descriptor */ 00212 TXFD = 0x10000000, /* first descriptor */ 00213 CRCEnable = 0x08000000, /* crc control */ 00214 PADEnable = 0x04000000, /* padding control */ 00215 RetryTxLC = 0x02000000, /* retry late collision */ 00216 PKTSMask = 0x3ff800, /* packet size bit21-11 */ 00217 PKTSShift = 11, 00218 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */ 00219 TBSShift = 0, 00220 };
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
| static int mdio_read | ( | struct nic * | , | |
| int | phy_id, | |||
| int | location | |||
| ) | [static] |
Referenced by __mdio_read(), check_duplex(), getlinkstatus(), getlinktype(), init_media(), mdio_patch(), mdio_read_latched(), mtd_probe(), pcnet32_probe(), rtl8168d_hw_phy_config(), rtl8169_set_speed_xmii(), rtl8169_write_gmii_reg_bit(), rtl8169_xmii_reset_enable(), rtl8169_xmii_reset_pending(), rtl8169s_hw_phy_config(), sis190_default_phy(), sis190_init_phy(), sis190_phy_task(), sis190_set_speed_auto(), start_link(), sundance_probe(), tulip_check_duplex(), and w89c840_probe().
| static void getlinktype | ( | struct nic * | dev | ) | [static] |
Definition at line 918 of file mtd80x.c.
References AhdocPHY, mtd_private::crvalue, DiagnosticReg, DPLX_DET_FULL, DPLX_FULL, mtd_private::duplexmode, FD, Full_Duplex, FULLMODE, inl, mtd_private::ioaddr, LevelOnePHY, mtd_private::line_speed, LXT1000_1000M, LXT1000_100M, LXT1000_Full, MarvellPHY, mdio_read(), MIIRegister18, mtdx, Myson981, MysonPHY, mtd_private::phys, mtd_private::PHYType, PS10, PS1000, SeeqPHY, SPD_DET_100, SpecificReg, SPEED100, Speed_100, Speed_1000M, Speed_100M, SpeedMask, StatusRegister, and TCRRCR.
Referenced by mtd_reset().
00919 { 00920 if (mtdx.PHYType == MysonPHY) 00921 { /* 3-in-1 case */ 00922 if (inl(mtdx.ioaddr + TCRRCR) & FD) 00923 mtdx.duplexmode = 2; /* full duplex */ 00924 else 00925 mtdx.duplexmode = 1; /* half duplex */ 00926 if (inl(mtdx.ioaddr + TCRRCR) & PS10) 00927 mtdx.line_speed = 1; /* 10M */ 00928 else 00929 mtdx.line_speed = 2; /* 100M */ 00930 } else 00931 { 00932 if (mtdx.PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */ 00933 unsigned int data; 00934 00935 data = mdio_read(dev, mtdx.phys[0], MIIRegister18); 00936 if (data & SPD_DET_100) 00937 mtdx.line_speed = 2; /* 100M */ 00938 else 00939 mtdx.line_speed = 1; /* 10M */ 00940 if (data & DPLX_DET_FULL) 00941 mtdx.duplexmode = 2; /* full duplex mode */ 00942 else 00943 mtdx.duplexmode = 1; /* half duplex mode */ 00944 } else if (mtdx.PHYType == AhdocPHY) { 00945 unsigned int data; 00946 00947 data = mdio_read(dev, mtdx.phys[0], DiagnosticReg); 00948 if (data & Speed_100) 00949 mtdx.line_speed = 2; /* 100M */ 00950 else 00951 mtdx.line_speed = 1; /* 10M */ 00952 if (data & DPLX_FULL) 00953 mtdx.duplexmode = 2; /* full duplex mode */ 00954 else 00955 mtdx.duplexmode = 1; /* half duplex mode */ 00956 } 00957 /* 89/6/13 add, (begin) */ 00958 else if (mtdx.PHYType == MarvellPHY) { 00959 unsigned int data; 00960 00961 data = mdio_read(dev, mtdx.phys[0], SpecificReg); 00962 if (data & Full_Duplex) 00963 mtdx.duplexmode = 2; /* full duplex mode */ 00964 else 00965 mtdx.duplexmode = 1; /* half duplex mode */ 00966 data &= SpeedMask; 00967 if (data == Speed_1000M) 00968 mtdx.line_speed = 3; /* 1000M */ 00969 else if (data == Speed_100M) 00970 mtdx.line_speed = 2; /* 100M */ 00971 else 00972 mtdx.line_speed = 1; /* 10M */ 00973 } 00974 /* 89/6/13 add, (end) */ 00975 /* 89/7/27 add, (begin) */ 00976 else if (mtdx.PHYType == Myson981) { 00977 unsigned int data; 00978 00979 data = mdio_read(dev, mtdx.phys[0], StatusRegister); 00980 00981 if (data & SPEED100) 00982 mtdx.line_speed = 2; 00983 else 00984 mtdx.line_speed = 1; 00985 00986 if (data & FULLMODE) 00987 mtdx.duplexmode = 2; 00988 else 00989 mtdx.duplexmode = 1; 00990 } 00991 /* 89/7/27 add, (end) */ 00992 /* 89/12/29 add */ 00993 else if (mtdx.PHYType == LevelOnePHY) { 00994 unsigned int data; 00995 00996 data = mdio_read(dev, mtdx.phys[0], SpecificReg); 00997 if (data & LXT1000_Full) 00998 mtdx.duplexmode = 2; /* full duplex mode */ 00999 else 01000 mtdx.duplexmode = 1; /* half duplex mode */ 01001 data &= SpeedMask; 01002 if (data == LXT1000_1000M) 01003 mtdx.line_speed = 3; /* 1000M */ 01004 else if (data == LXT1000_100M) 01005 mtdx.line_speed = 2; /* 100M */ 01006 else 01007 mtdx.line_speed = 1; /* 10M */ 01008 } 01009 // chage crvalue 01010 // mtdx.crvalue&=(~PS10)&(~FD); 01011 mtdx.crvalue &= (~PS10) & (~FD) & (~PS1000); 01012 if (mtdx.line_speed == 1) 01013 mtdx.crvalue |= PS10; 01014 else if (mtdx.line_speed == 3) 01015 mtdx.crvalue |= PS1000; 01016 if (mtdx.duplexmode == 2) 01017 mtdx.crvalue |= FD; 01018 } 01019 }
| static void getlinkstatus | ( | struct nic * | nic | ) | [static] |
Definition at line 885 of file mtd80x.c.
References BMCRSR, BMSR_LSTATUS, inl, mtd_private::ioaddr, LinkIsUp2, mtd_private::linkok, m80x_delay(), mdio_read(), MII_BMSR, mtdx, MysonPHY, mtd_private::phys, and mtd_private::PHYType.
Referenced by mtd_probe(), and mtd_reset().
00886 : Routine will read MII Status Register to get link status. */ 00887 /* input : dev... pointer to the adapter block. */ 00888 /* output : none. */ 00889 { 00890 unsigned int i, DelayTime = 0x1000; 00891 00892 mtdx.linkok = 0; 00893 00894 if (mtdx.PHYType == MysonPHY) 00895 { 00896 for (i = 0; i < DelayTime; ++i) { 00897 if (inl(mtdx.ioaddr + BMCRSR) & LinkIsUp2) { 00898 mtdx.linkok = 1; 00899 return; 00900 } 00901 // delay 00902 m80x_delay(100); 00903 } 00904 } else 00905 { 00906 for (i = 0; i < DelayTime; ++i) { 00907 if (mdio_read(nic, mtdx.phys[0], MII_BMSR) & BMSR_LSTATUS) { 00908 mtdx.linkok = 1; 00909 return; 00910 } 00911 // delay 00912 m80x_delay(100); 00913 } 00914 } 00915 }
| static void set_rx_mode | ( | struct nic * | ) | [static] |
Definition at line 373 of file mtd80x.c.
References mtd_desc::buffer, mtd_desc::control, mtd_private::cur_rx, mtdx, mtd_desc::next_desc, mtd_desc::next_desc_logical, PKT_BUF_SZ, RBSShift, mtd_private::rx_buf_sz, mtd_private::rx_ring, RX_RING_SIZE, rxb, RXOWN, mtd_desc::skbuff, mtd_desc::status, mtd_private::tx_ring, txb, virt_to_bus(), and virt_to_le32desc.
00374 { 00375 int i; 00376 00377 mtdx.cur_rx = &mtdx.rx_ring[0]; 00378 00379 mtdx.rx_buf_sz = PKT_BUF_SZ; 00380 /*mtdx.rx_head_desc = &mtdx.rx_ring[0];*/ 00381 00382 /* Initialize all Rx descriptors. */ 00383 /* Fill in the Rx buffers. Handle allocation failure gracefully. */ 00384 for (i = 0; i < RX_RING_SIZE; i++) 00385 { 00386 mtdx.rx_ring[i].status = RXOWN; 00387 mtdx.rx_ring[i].control = mtdx.rx_buf_sz << RBSShift; 00388 mtdx.rx_ring[i].next_desc = virt_to_le32desc(&mtdx.rx_ring[i+1]); 00389 mtdx.rx_ring[i].next_desc_logical = &mtdx.rx_ring[i+1]; 00390 mtdx.rx_ring[i].buffer = virt_to_le32desc(&rxb[i * PKT_BUF_SZ]); 00391 mtdx.rx_ring[i].skbuff = &rxb[i * PKT_BUF_SZ]; 00392 } 00393 /* Mark the last entry as wrapping the ring. */ 00394 mtdx.rx_ring[i-1].next_desc = virt_to_le32desc(&mtdx.rx_ring[0]); 00395 mtdx.rx_ring[i-1].next_desc_logical = &mtdx.rx_ring[0]; 00396 00397 /* We only use one transmit buffer, but two 00398 * descriptors so transmit engines have somewhere 00399 * to point should they feel the need */ 00400 mtdx.tx_ring[0].status = 0x00000000; 00401 mtdx.tx_ring[0].buffer = virt_to_bus(&txb[0]); 00402 mtdx.tx_ring[0].next_desc = virt_to_le32desc(&mtdx.tx_ring[1]); 00403 00404 /* This descriptor is never used */ 00405 mtdx.tx_ring[1].status = 0x00000000; 00406 mtdx.tx_ring[1].buffer = 0; /*virt_to_bus(&txb[1]); */ 00407 mtdx.tx_ring[1].next_desc = virt_to_le32desc(&mtdx.tx_ring[0]); 00408 00409 return; 00410 }
| static void mtd_reset | ( | struct nic * | nic | ) | [static] |
Definition at line 415 of file mtd80x.c.
References BCR, mtd_private::bcrvalue, CNTOVF, mtd_private::crvalue, DBG, mtd_private::dev_id, mtd_private::duplexmode, FBE, getlinkstatus(), getlinktype(), IMR, init_ring(), mtd_private::ioaddr, ISR, mtd_private::line_speed, mtd_private::linkok, mtdx, outl, RBU, RI, mtd_private::rx_ring, RxEnable, RXLBA, RXPDR, set_rx_mode(), TI, TUNF, mtd_private::tx_ring, TXLBA, TxThreshold, and virt_to_bus().
Referenced by mtd_disable(), and mtd_probe().
00416 { 00417 /* Reset the chip to erase previous misconfiguration. */ 00418 outl(0x00000001, mtdx.ioaddr + BCR); 00419 00420 init_ring(nic); 00421 00422 outl(virt_to_bus(mtdx.rx_ring), mtdx.ioaddr + RXLBA); 00423 outl(virt_to_bus(mtdx.tx_ring), mtdx.ioaddr + TXLBA); 00424 00425 /* Initialize other registers. */ 00426 /* Configure the PCI bus bursts and FIFO thresholds. */ 00427 mtdx.bcrvalue = 0x10; /* little-endian, 8 burst length */ 00428 mtdx.crvalue = 0xa00; /* rx 128 burst length */ 00429 00430 if ( mtdx.dev_id == 0x891 ) { 00431 mtdx.bcrvalue |= 0x200; /* set PROG bit */ 00432 mtdx.crvalue |= 0x02000000; /* set enhanced bit */ 00433 } 00434 00435 outl( mtdx.bcrvalue, mtdx.ioaddr + BCR); 00436 00437 /* Restart Rx engine if stopped. */ 00438 outl(0, mtdx.ioaddr + RXPDR); 00439 00440 getlinkstatus(nic); 00441 if (mtdx.linkok) 00442 { 00443 static const char* texts[]={"half","full","10","100","1000"}; 00444 getlinktype(nic); 00445 DBG ( "Link is OK : %s %s\n", texts[mtdx.duplexmode-1], texts[mtdx.line_speed+1] ); 00446 } else 00447 { 00448 DBG ( "No link!!!\n" ); 00449 } 00450 00451 mtdx.crvalue |= /*TxEnable |*/ RxEnable | TxThreshold; 00452 set_rx_mode(nic); 00453 00454 /* Clear interrupts by setting the interrupt mask. */ 00455 outl(FBE | TUNF | CNTOVF | RBU | TI | RI, mtdx.ioaddr + ISR); 00456 outl( 0, mtdx.ioaddr + IMR); 00457 }
Definition at line 462 of file mtd80x.c.
References CRC, mtd_private::cur_rx, DBG, ErrorSummary, FLNGMASK, FLNGShift, mtd_private::ioaddr, LONG, memcpy, mtdx, mtd_desc::next_desc_logical, mtd_private::nic_name, outl, nic::packet, nic::packetlen, printf(), RUNT, RXER, RXFSD, RXLSD, RXOWN, RXPDR, mtd_desc::skbuff, and mtd_desc::status.
00463 { 00464 s32 rx_status = mtdx.cur_rx->status; 00465 int retval = 0; 00466 00467 if( ( rx_status & RXOWN ) != 0 ) 00468 { 00469 return 0; 00470 } 00471 00472 if (rx_status & ErrorSummary) 00473 { /* there was a fatal error */ 00474 printf( "%s: Receive error, Rx status %8.8x, Error(s) %s%s%s\n", 00475 mtdx.nic_name, (unsigned int) rx_status, 00476 (rx_status & (LONG | RUNT)) ? "length_error ":"", 00477 (rx_status & RXER) ? "frame_error ":"", 00478 (rx_status & CRC) ? "crc_error ":"" ); 00479 retval = 0; 00480 } else if( !((rx_status & RXFSD) && (rx_status & RXLSD)) ) 00481 { 00482 /* this pkt is too long, over one rx buffer */ 00483 printf("Pkt is too long, over one rx buffer.\n"); 00484 retval = 0; 00485 } else 00486 { /* this received pkt is ok */ 00487 /* Omit the four octet CRC from the length. */ 00488 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4; 00489 00490 DBG ( " netdev_rx() normal Rx pkt length %d" 00491 " status %x.\n", pkt_len, (unsigned int) rx_status ); 00492 00493 nic->packetlen = pkt_len; 00494 memcpy(nic->packet, mtdx.cur_rx->skbuff, pkt_len); 00495 00496 retval = 1; 00497 } 00498 00499 while( ( mtdx.cur_rx->status & RXOWN ) == 0 ) 00500 { 00501 mtdx.cur_rx->status = RXOWN; 00502 mtdx.cur_rx = mtdx.cur_rx->next_desc_logical; 00503 } 00504 00505 /* Restart Rx engine if stopped. */ 00506 outl(0, mtdx.ioaddr + RXPDR); 00507 00508 return retval; 00509 }
| static void mtd_transmit | ( | struct nic * | nic, | |
| const char * | dest, | |||
| unsigned int | type, | |||
| unsigned int | size, | |||
| const char * | data | |||
| ) | [static] |
Definition at line 514 of file mtd80x.c.
References mtd_desc::control, CRCEnable, mtd_private::crvalue, CSL, currticks(), DBG, EC, ETH_ALEN, ETH_HLEN, ETH_ZLEN, HF, htons, mtd_private::ioaddr, LC, memcpy, mtdx, nic::node_addr, outl, PADEnable, PKTSShift, printf(), mtd_desc::status, TBSShift, TCRRCR, mtd_private::tx_ring, TX_TIME_OUT, txb, TxEnable, TXFD, TXLBA, TXLD, TXOWN, TXPDR, u32, UDF, and virt_to_bus().
00520 { 00521 u32 to; 00522 u32 tx_status; 00523 unsigned int nstype = htons ( type ); 00524 00525 memcpy( txb, dest, ETH_ALEN ); 00526 memcpy( txb + ETH_ALEN, nic->node_addr, ETH_ALEN ); 00527 memcpy( txb + 2 * ETH_ALEN, &nstype, 2 ); 00528 memcpy( txb + ETH_HLEN, data, size ); 00529 00530 size += ETH_HLEN; 00531 size &= 0x0FFF; 00532 while( size < ETH_ZLEN ) 00533 { 00534 txb[size++] = '\0'; 00535 } 00536 00537 mtdx.tx_ring[0].control = TXLD | TXFD | CRCEnable | PADEnable; 00538 mtdx.tx_ring[0].control |= (size << PKTSShift); /* pkt size */ 00539 mtdx.tx_ring[0].control |= (size << TBSShift); /* buffer size */ 00540 mtdx.tx_ring[0].status = TXOWN; 00541 00542 /* Point to transmit descriptor */ 00543 outl(virt_to_bus(mtdx.tx_ring), mtdx.ioaddr + TXLBA); 00544 /* Enable Tx */ 00545 outl( mtdx.crvalue | TxEnable, mtdx.ioaddr + TCRRCR); 00546 /* Wake the potentially-idle transmit channel. */ 00547 outl(0, mtdx.ioaddr + TXPDR); 00548 00549 to = currticks() + TX_TIME_OUT; 00550 while(( mtdx.tx_ring[0].status & TXOWN) && (currticks() < to)); 00551 00552 /* Disable Tx */ 00553 outl( mtdx.crvalue & (~TxEnable), mtdx.ioaddr + TCRRCR); 00554 00555 tx_status = mtdx.tx_ring[0].status; 00556 if (currticks() >= to){ 00557 DBG ( "TX Time Out" ); 00558 } else if( tx_status & (CSL | LC | EC | UDF | HF)){ 00559 printf( "Transmit error: %8.8x %s %s %s %s %s\n", 00560 (unsigned int) tx_status, 00561 tx_status & EC ? "abort" : "", 00562 tx_status & CSL ? "carrier" : "", 00563 tx_status & LC ? "late" : "", 00564 tx_status & UDF ? "fifo" : "", 00565 tx_status & HF ? "heartbeat" : "" ); 00566 } 00567 00568 /*hex_dump( txb, size );*/ 00569 /*pause();*/ 00570 00571 DBG ( "TRANSMIT\n" ); 00572 }
| static void mtd_disable | ( | struct nic * | nic | ) | [static] |
Definition at line 577 of file mtd80x.c.
References mtd_private::crvalue, DBG, mtd_private::ioaddr, mtd_reset(), mtdx, outl, RxEnable, TCRRCR, and TxEnable.
00577 { 00578 00579 /* Disable Tx Rx*/ 00580 outl( mtdx.crvalue & (~TxEnable) & (~RxEnable), mtdx.ioaddr + TCRRCR ); 00581 00582 /* Reset the chip to erase previous misconfiguration. */ 00583 mtd_reset(nic); 00584 00585 DBG ( "DISABLE\n" ); 00586 }
| PCI_DRIVER | ( | mtd80x_driver | , | |
| mtd80x_nics | , | |||
| PCI_NO_CLASS | ||||
| ) |
| static int mtd_probe | ( | struct nic * | nic, | |
| struct pci_device * | pci | |||
| ) | [static] |
Definition at line 608 of file mtd80x.c.
References adjust_pci_device(), AhdocPHY, AhdocPHYID0, BCR, DBG, mtd_private::dev_id, pci_device::device, pci_device::driver_name, eth_ntoa(), getlinkstatus(), inb, inl, mtd_private::ioaddr, nic::ioaddr, pci_device::ioaddr, nic::irqno, LevelOnePHY, LevelOnePHYID0, mtd_private::linkok, MarvellPHY, MarvellPHYID0, mdio_read(), memcmp(), mtd_private::mii_cnt, mtd_reset(), mtdx, Myson981, MysonPHY, MysonPHYID, MysonPHYID0, mtd_private::nic_name, nic::nic_op, nic::node_addr, OtherPHY, outl, PAR0, PHYIDENTIFIER, mtd_private::phys, mtd_private::PHYType, printf(), SeeqPHY, and SeeqPHYID0.
00608 { 00609 00610 int i; 00611 00612 if (pci->ioaddr == 0) 00613 return 0; 00614 00615 adjust_pci_device(pci); 00616 00617 nic->ioaddr = pci->ioaddr; 00618 nic->irqno = 0; 00619 00620 mtdx.nic_name = pci->driver_name; 00621 mtdx.dev_id = pci->device; 00622 mtdx.ioaddr = nic->ioaddr; 00623 00624 /* read ethernet id */ 00625 for (i = 0; i < 6; ++i) 00626 { 00627 nic->node_addr[i] = inb(mtdx.ioaddr + PAR0 + i); 00628 } 00629 00630 if (memcmp(nic->node_addr, "\0\0\0\0\0\0", 6) == 0) 00631 { 00632 return 0; 00633 } 00634 00635 DBG ( "%s: ioaddr %4.4x MAC %s\n", mtdx.nic_name, mtdx.ioaddr, eth_ntoa ( nic->node_addr ) ); 00636 00637 /* Reset the chip to erase previous misconfiguration. */ 00638 outl(0x00000001, mtdx.ioaddr + BCR); 00639 00640 /* find the connected MII xcvrs */ 00641 00642 if( mtdx.dev_id != 0x803 ) 00643 { 00644 int phy, phy_idx = 0; 00645 00646 for (phy = 1; phy < 32 && phy_idx < 1; phy++) { 00647 int mii_status = mdio_read(nic, phy, 1); 00648 00649 if (mii_status != 0xffff && mii_status != 0x0000) { 00650 mtdx.phys[phy_idx] = phy; 00651 00652 DBG ( "%s: MII PHY found at address %d, status " 00653 "0x%4.4x.\n", mtdx.nic_name, phy, mii_status ); 00654 /* get phy type */ 00655 { 00656 unsigned int data; 00657 00658 data = mdio_read(nic, mtdx.phys[phy_idx], 2); 00659 if (data == SeeqPHYID0) 00660 mtdx.PHYType = SeeqPHY; 00661 else if (data == AhdocPHYID0) 00662 mtdx.PHYType = AhdocPHY; 00663 else if (data == MarvellPHYID0) 00664 mtdx.PHYType = MarvellPHY; 00665 else if (data == MysonPHYID0) 00666 mtdx.PHYType = Myson981; 00667 else if (data == LevelOnePHYID0) 00668 mtdx.PHYType = LevelOnePHY; 00669 else 00670 mtdx.PHYType = OtherPHY; 00671 } 00672 phy_idx++; 00673 } 00674 } 00675 00676 mtdx.mii_cnt = phy_idx; 00677 if (phy_idx == 0) { 00678 printf("%s: MII PHY not found -- this device may " 00679 "not operate correctly.\n", mtdx.nic_name); 00680 } 00681 } else { 00682 mtdx.phys[0] = 32; 00683 /* get phy type */ 00684 if (inl(mtdx.ioaddr + PHYIDENTIFIER) == MysonPHYID ) { 00685 mtdx.PHYType = MysonPHY; 00686 DBG ( "MysonPHY\n" ); 00687 } else { 00688 mtdx.PHYType = OtherPHY; 00689 DBG ( "OtherPHY\n" ); 00690 } 00691 } 00692 00693 getlinkstatus(nic); 00694 if( !mtdx.linkok ) 00695 { 00696 printf("No link!!!\n"); 00697 return 0; 00698 } 00699 00700 mtd_reset( nic ); 00701 00702 /* point to NIC specific routines */ 00703 nic->nic_op = &mtd_operations; 00704 return 1; 00705 }
Definition at line 709 of file mtd80x.c.
References AcceptBroadcast, AcceptMulticast, AcceptMyPhys, mtd_private::crvalue, mtd_private::ioaddr, MAR0, MAR1, mtdx, outb, outl, RxModeMask, TCRRCR, and u32.
00710 { 00711 u32 mc_filter[2]; /* Multicast hash filter */ 00712 u32 rx_mode; 00713 00714 /* Too many to match, or accept all multicasts. */ 00715 mc_filter[1] = mc_filter[0] = ~0; 00716 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 00717 00718 outl(mc_filter[0], mtdx.ioaddr + MAR0); 00719 outl(mc_filter[1], mtdx.ioaddr + MAR1); 00720 00721 mtdx.crvalue = ( mtdx.crvalue & ~RxModeMask ) | rx_mode; 00722 outb( mtdx.crvalue, mtdx.ioaddr + TCRRCR); 00723 }
| static unsigned int m80x_read_tick | ( | void | ) | [static] |
Definition at line 725 of file mtd80x.c.
Referenced by m80x_delay().
00726 : Reads the Timer tick count register which decrements by 2 from */ 00727 /* 65536 to 0 every 1/36.414 of a second. Each 2 decrements of the */ 00728 /* count represents 838 nsec's. */ 00729 /* input : none. */ 00730 /* output : none. */ 00731 { 00732 unsigned char tmp; 00733 int value; 00734 00735 outb((char) 0x06, 0x43); // Command 8254 to latch T0's count 00736 00737 // now read the count. 00738 tmp = (unsigned char) inb(0x40); 00739 value = ((int) tmp) << 8; 00740 tmp = (unsigned char) inb(0x40); 00741 value |= (((int) tmp) & 0xff); 00742 return (value); 00743 }
| static void m80x_delay | ( | unsigned int | interval | ) | [static] |
Definition at line 745 of file mtd80x.c.
References m80x_read_tick(), and u16.
Referenced by getlinkstatus(), m80x_send_cmd_to_phy(), and mdio_read().
00746 : to wait for a specified time. */ 00747 /* input : interval ... the specified time. */ 00748 /* output : none. */ 00749 { 00750 unsigned int interval1, interval2, i = 0; 00751 00752 interval1 = m80x_read_tick(); // get initial value 00753 do 00754 { 00755 interval2 = m80x_read_tick(); 00756 if (interval1 < interval2) 00757 interval1 += 65536; 00758 ++i; 00759 } while (((interval1 - interval2) < (u16) interval) && (i < 65535)); 00760 }
| static u32 m80x_send_cmd_to_phy | ( | long | miiport, | |
| int | opcode, | |||
| int | phyad, | |||
| int | regad | |||
| ) | [static] |
Definition at line 763 of file mtd80x.c.
References inl, m80x_delay(), MASK_MIIR_MII_MDC, MASK_MIIR_MII_MDO, MASK_MIIR_MII_WRITE, OP_READ, outl, and u32.
Referenced by mdio_read().
00764 { 00765 u32 miir; 00766 int i; 00767 unsigned int mask, data; 00768 00769 /* enable MII output */ 00770 miir = (u32) inl(miiport); 00771 miir &= 0xfffffff0; 00772 00773 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO; 00774 00775 /* send 32 1's preamble */ 00776 for (i = 0; i < 32; i++) { 00777 /* low MDC; MDO is already high (miir) */ 00778 miir &= ~MASK_MIIR_MII_MDC; 00779 outl(miir, miiport); 00780 00781 /* high MDC */ 00782 miir |= MASK_MIIR_MII_MDC; 00783 outl(miir, miiport); 00784 } 00785 00786 /* calculate ST+OP+PHYAD+REGAD+TA */ 00787 data = opcode | (phyad << 7) | (regad << 2); 00788 00789 /* sent out */ 00790 mask = 0x8000; 00791 while (mask) { 00792 /* low MDC, prepare MDO */ 00793 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO); 00794 if (mask & data) 00795 miir |= MASK_MIIR_MII_MDO; 00796 00797 outl(miir, miiport); 00798 /* high MDC */ 00799 miir |= MASK_MIIR_MII_MDC; 00800 outl(miir, miiport); 00801 m80x_delay(30); 00802 00803 /* next */ 00804 mask >>= 1; 00805 if (mask == 0x2 && opcode == OP_READ) 00806 miir &= ~MASK_MIIR_MII_WRITE; 00807 } 00808 return miir; 00809 }
Definition at line 811 of file mtd80x.c.
References inl, mtd_private::ioaddr, m80x_delay(), m80x_send_cmd_to_phy(), MANAGEMENT, MASK_MIIR_MII_MDC, MASK_MIIR_MII_MDI, mtdx, OP_READ, outl, and u32.
00812 { 00813 long miiport = mtdx.ioaddr + MANAGEMENT; 00814 u32 miir; 00815 unsigned int mask, data; 00816 00817 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad); 00818 00819 /* read data */ 00820 mask = 0x8000; 00821 data = 0; 00822 while (mask) 00823 { 00824 /* low MDC */ 00825 miir &= ~MASK_MIIR_MII_MDC; 00826 outl(miir, miiport); 00827 00828 /* read MDI */ 00829 miir = inl(miiport); 00830 if (miir & MASK_MIIR_MII_MDI) 00831 data |= mask; 00832 00833 /* high MDC, and wait */ 00834 miir |= MASK_MIIR_MII_MDC; 00835 outl(miir, miiport); 00836 m80x_delay((int) 30); 00837 00838 /* next */ 00839 mask >>= 1; 00840 } 00841 00842 /* low MDC */ 00843 miir &= ~MASK_MIIR_MII_MDC; 00844 outl(miir, miiport); 00845 00846 return data & 0xffff; 00847 }
| DRIVER | ( | "MTD80X" | , | |
| nic_driver | , | |||
| pci_driver | , | |||
| mtd80x_driver | , | |||
| mtd_probe | , | |||
| mtd_disable | ||||
| ) |
| struct { ... } __shared |
struct mtd_private mtdx [static] |
Definition at line 363 of file mtd80x.c.
Referenced by getlinkstatus(), getlinktype(), init_ring(), mdio_read(), mtd_disable(), mtd_poll(), mtd_probe(), mtd_reset(), mtd_transmit(), and set_rx_mode().
struct nic_operations mtd_operations [static] |
Initial value:
{
.connect = dummy_connect,
.poll = mtd_poll,
.transmit = mtd_transmit,
.irq = dummy_irq,
}
struct pci_device_id mtd80x_nics[] [static] |
1.5.7.1