#include "igb.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_ONLY) | |
| static s32 | igb_phy_setup_autoneg (struct e1000_hw *hw) |
| igb_phy_setup_autoneg - Configure PHY for auto-negotiation : pointer to the HW structure | |
| s32 | igb_check_reset_block_generic (struct e1000_hw *hw) |
| igb_check_reset_block_generic - Check if PHY reset is blocked : pointer to the HW structure | |
| s32 | igb_get_phy_id (struct e1000_hw *hw) |
| igb_get_phy_id - Retrieve the PHY ID and revision : pointer to the HW structure | |
| s32 | igb_phy_reset_dsp_generic (struct e1000_hw *hw) |
| igb_phy_reset_dsp_generic - Reset PHY DSP : pointer to the HW structure | |
| s32 | igb_read_phy_reg_mdic (struct e1000_hw *hw, u32 offset, u16 *data) |
| igb_read_phy_reg_mdic - Read MDI control register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | igb_write_phy_reg_mdic (struct e1000_hw *hw, u32 offset, u16 data) |
| igb_write_phy_reg_mdic - Write MDI control register : pointer to the HW structure : register offset to write to : data to write to register at offset | |
| s32 | igb_read_phy_reg_i2c (struct e1000_hw *hw, u32 offset, u16 *data) |
| igb_read_phy_reg_i2c - Read PHY register using i2c : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | igb_write_phy_reg_i2c (struct e1000_hw *hw, u32 offset, u16 data) |
| igb_write_phy_reg_i2c - Write PHY register using i2c : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | igb_read_phy_reg_m88 (struct e1000_hw *hw, u32 offset, u16 *data) |
| igb_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | igb_write_phy_reg_m88 (struct e1000_hw *hw, u32 offset, u16 data) |
| igb_write_phy_reg_m88 - Write m88 PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| static s32 | __igb_read_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 *data, bool locked) |
| __igb_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data : semaphore has already been acquired or not | |
| s32 | igb_read_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 *data) |
| igb_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | igb_read_phy_reg_igp_locked (struct e1000_hw *hw, u32 offset, u16 *data) |
| igb_read_phy_reg_igp_locked - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| static s32 | __igb_write_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 data, bool locked) |
| igb_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset : semaphore has already been acquired or not | |
| s32 | igb_write_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 data) |
| igb_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | igb_write_phy_reg_igp_locked (struct e1000_hw *hw, u32 offset, u16 data) |
| igb_write_phy_reg_igp_locked - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| static s32 | __igb_read_kmrn_reg (struct e1000_hw *hw, u32 offset, u16 *data, bool locked) |
| __igb_read_kmrn_reg - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data : semaphore has already been acquired or not | |
| s32 | igb_read_kmrn_reg_generic (struct e1000_hw *hw, u32 offset, u16 *data) |
| igb_read_kmrn_reg_generic - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | igb_read_kmrn_reg_locked (struct e1000_hw *hw, u32 offset, u16 *data) |
| igb_read_kmrn_reg_locked - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| static s32 | __igb_write_kmrn_reg (struct e1000_hw *hw, u32 offset, u16 data, bool locked) |
| __igb_write_kmrn_reg - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset : semaphore has already been acquired or not | |
| s32 | igb_write_kmrn_reg_generic (struct e1000_hw *hw, u32 offset, u16 data) |
| igb_write_kmrn_reg_generic - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | igb_write_kmrn_reg_locked (struct e1000_hw *hw, u32 offset, u16 data) |
| igb_write_kmrn_reg_locked - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | igb_copper_link_setup_m88 (struct e1000_hw *hw) |
| igb_copper_link_setup_m88 - Setup m88 PHY's for copper link : pointer to the HW structure | |
| s32 | igb_copper_link_setup_igp (struct e1000_hw *hw) |
| igb_copper_link_setup_igp - Setup igp PHY's for copper link : pointer to the HW structure | |
| s32 | igb_copper_link_autoneg (struct e1000_hw *hw) |
| igb_copper_link_autoneg - Setup/Enable autoneg for copper link : pointer to the HW structure | |
| s32 | igb_setup_copper_link_generic (struct e1000_hw *hw) |
| igb_setup_copper_link_generic - Configure copper link settings : pointer to the HW structure | |
| s32 | igb_set_d3_lplu_state_generic (struct e1000_hw *hw, bool active) |
| igb_set_d3_lplu_state_generic - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu | |
| s32 | igb_check_downshift_generic (struct e1000_hw *hw) |
| igb_check_downshift_generic - Checks whether a downshift in speed occurred : pointer to the HW structure | |
| s32 | igb_check_polarity_m88 (struct e1000_hw *hw) |
| igb_check_polarity_m88 - Checks the polarity. | |
| s32 | igb_check_polarity_igp (struct e1000_hw *hw) |
| igb_check_polarity_igp - Checks the polarity. | |
| s32 | igb_check_polarity_ife (struct e1000_hw *hw) |
| igb_check_polarity_ife - Check cable polarity for IFE PHY : pointer to the HW structure | |
| s32 | igb_wait_autoneg_generic (struct e1000_hw *hw) |
| igb_wait_autoneg_generic - Wait for auto-neg completion : pointer to the HW structure | |
| s32 | igb_phy_has_link_generic (struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success) |
| igb_phy_has_link_generic - Polls PHY for link : pointer to the HW structure : number of times to poll for link : delay between polling attempts : pointer to whether polling was successful or not | |
| s32 | igb_get_phy_info_m88 (struct e1000_hw *hw) |
| igb_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure | |
| s32 | igb_get_phy_info_igp (struct e1000_hw *hw) |
| igb_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure | |
| s32 | igb_phy_sw_reset_generic (struct e1000_hw *hw) |
| igb_phy_sw_reset_generic - PHY software reset : pointer to the HW structure | |
| s32 | igb_phy_hw_reset_generic (struct e1000_hw *hw) |
| igb_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure | |
| s32 | igb_get_cfg_done_generic (struct e1000_hw *hw __unused) |
| igb_get_cfg_done_generic - Generic configuration done : pointer to the HW structure | |
| s32 | igb_phy_init_script_igp3 (struct e1000_hw *hw) |
| igb_phy_init_script_igp3 - Inits the IGP3 PHY : pointer to the HW structure | |
| enum e1000_phy_type | igb_get_phy_type_from_id (u32 phy_id) |
| igb_get_phy_type_from_id - Get PHY type from id : phy_id read from the phy | |
| s32 | igb_determine_phy_address (struct e1000_hw *hw) |
| igb_determine_phy_address - Determines PHY address. | |
| void | igb_power_up_phy_copper (struct e1000_hw *hw) |
| igb_power_up_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure | |
| void | igb_power_down_phy_copper (struct e1000_hw *hw) |
| igb_power_down_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure | |
| FILE_LICENCE | ( | GPL2_ONLY | ) |
igb_phy_setup_autoneg - Configure PHY for auto-negotiation : pointer to the HW structure
Reads the MII auto-neg advertisement register and/or the 1000T control register and if the PHY is already setup for auto-negotiation, then return successful. Otherwise, setup advertisement and flow control to the appropriate values for the wanted auto-negotiation.
Definition at line 1026 of file igb_phy.c.
References ADVERTISE_1000_FULL, ADVERTISE_1000_HALF, ADVERTISE_100_FULL, ADVERTISE_100_HALF, ADVERTISE_10_FULL, ADVERTISE_10_HALF, e1000_phy_info::autoneg_advertised, e1000_phy_info::autoneg_mask, CR_1000T_FD_CAPS, CR_1000T_HD_CAPS, e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, DEBUGOUT1, E1000_ERR_CONFIG, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, e1000_hw::fc, NWAY_AR_100TX_FD_CAPS, NWAY_AR_100TX_HD_CAPS, NWAY_AR_10T_FD_CAPS, NWAY_AR_10T_HD_CAPS, NWAY_AR_ASM_DIR, NWAY_AR_PAUSE, e1000_phy_info::ops, e1000_hw::phy, PHY_1000T_CTRL, PHY_AUTONEG_ADV, e1000_phy_operations::read_reg, u16, and e1000_phy_operations::write_reg.
Referenced by igb_copper_link_autoneg().
01027 { 01028 struct e1000_phy_info *phy = &hw->phy; 01029 s32 ret_val; 01030 u16 mii_autoneg_adv_reg; 01031 u16 mii_1000t_ctrl_reg = 0; 01032 01033 DEBUGFUNC("igb_phy_setup_autoneg"); 01034 01035 phy->autoneg_advertised &= phy->autoneg_mask; 01036 01037 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 01038 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 01039 if (ret_val) 01040 goto out; 01041 01042 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 01043 /* Read the MII 1000Base-T Control Register (Address 9). */ 01044 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 01045 &mii_1000t_ctrl_reg); 01046 if (ret_val) 01047 goto out; 01048 } 01049 01050 /* 01051 * Need to parse both autoneg_advertised and fc and set up 01052 * the appropriate PHY registers. First we will parse for 01053 * autoneg_advertised software override. Since we can advertise 01054 * a plethora of combinations, we need to check each bit 01055 * individually. 01056 */ 01057 01058 /* 01059 * First we clear all the 10/100 mb speed bits in the Auto-Neg 01060 * Advertisement Register (Address 4) and the 1000 mb speed bits in 01061 * the 1000Base-T Control Register (Address 9). 01062 */ 01063 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 01064 NWAY_AR_100TX_HD_CAPS | 01065 NWAY_AR_10T_FD_CAPS | 01066 NWAY_AR_10T_HD_CAPS); 01067 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 01068 01069 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 01070 01071 /* Do we want to advertise 10 Mb Half Duplex? */ 01072 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 01073 DEBUGOUT("Advertise 10mb Half duplex\n"); 01074 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 01075 } 01076 01077 /* Do we want to advertise 10 Mb Full Duplex? */ 01078 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 01079 DEBUGOUT("Advertise 10mb Full duplex\n"); 01080 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 01081 } 01082 01083 /* Do we want to advertise 100 Mb Half Duplex? */ 01084 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 01085 DEBUGOUT("Advertise 100mb Half duplex\n"); 01086 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 01087 } 01088 01089 /* Do we want to advertise 100 Mb Full Duplex? */ 01090 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 01091 DEBUGOUT("Advertise 100mb Full duplex\n"); 01092 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 01093 } 01094 01095 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 01096 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) { 01097 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 01098 } 01099 /* Do we want to advertise 1000 Mb Full Duplex? */ 01100 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 01101 DEBUGOUT("Advertise 1000mb Full duplex\n"); 01102 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 01103 } 01104 01105 /* 01106 * Check for a software override of the flow control settings, and 01107 * setup the PHY advertisement registers accordingly. If 01108 * auto-negotiation is enabled, then software will have to set the 01109 * "PAUSE" bits to the correct value in the Auto-Negotiation 01110 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 01111 * negotiation. 01112 * 01113 * The possible values of the "fc" parameter are: 01114 * 0: Flow control is completely disabled 01115 * 1: Rx flow control is enabled (we can receive pause frames 01116 * but not send pause frames). 01117 * 2: Tx flow control is enabled (we can send pause frames 01118 * but we do not support receiving pause frames). 01119 * 3: Both Rx and Tx flow control (symmetric) are enabled. 01120 * other: No software override. The flow control configuration 01121 * in the EEPROM is used. 01122 */ 01123 switch (hw->fc.current_mode) { 01124 case e1000_fc_none: 01125 /* 01126 * Flow control (Rx & Tx) is completely disabled by a 01127 * software over-ride. 01128 */ 01129 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 01130 break; 01131 case e1000_fc_rx_pause: 01132 /* 01133 * Rx Flow control is enabled, and Tx Flow control is 01134 * disabled, by a software over-ride. 01135 * 01136 * Since there really isn't a way to advertise that we are 01137 * capable of Rx Pause ONLY, we will advertise that we 01138 * support both symmetric and asymmetric Rx PAUSE. Later 01139 * (in e1000_config_fc_after_link_up) we will disable the 01140 * hw's ability to send PAUSE frames. 01141 */ 01142 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 01143 break; 01144 case e1000_fc_tx_pause: 01145 /* 01146 * Tx Flow control is enabled, and Rx Flow control is 01147 * disabled, by a software over-ride. 01148 */ 01149 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 01150 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 01151 break; 01152 case e1000_fc_full: 01153 /* 01154 * Flow control (both Rx and Tx) is enabled by a software 01155 * over-ride. 01156 */ 01157 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 01158 break; 01159 default: 01160 DEBUGOUT("Flow control param set incorrectly\n"); 01161 ret_val = -E1000_ERR_CONFIG; 01162 goto out; 01163 } 01164 01165 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 01166 if (ret_val) 01167 goto out; 01168 01169 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 01170 01171 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 01172 ret_val = phy->ops.write_reg(hw, 01173 PHY_1000T_CTRL, 01174 mii_1000t_ctrl_reg); 01175 if (ret_val) 01176 goto out; 01177 } 01178 01179 out: 01180 return ret_val; 01181 }
igb_check_reset_block_generic - Check if PHY reset is blocked : pointer to the HW structure
Read the PHY management control register and check whether a PHY reset is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise return E1000_BLK_PHY_RESET (12).
Definition at line 64 of file igb_phy.c.
References DEBUGFUNC, E1000_BLK_PHY_RESET, E1000_MANC, E1000_MANC_BLK_PHY_RST_ON_IDE, E1000_READ_REG, E1000_SUCCESS, and u32.
Referenced by igb_init_phy_params_82575().
00065 { 00066 u32 manc; 00067 00068 DEBUGFUNC("igb_check_reset_block"); 00069 00070 manc = E1000_READ_REG(hw, E1000_MANC); 00071 00072 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 00073 E1000_BLK_PHY_RESET : E1000_SUCCESS; 00074 }
igb_get_phy_id - Retrieve the PHY ID and revision : pointer to the HW structure
Reads the PHY registers and stores the PHY ID and possibly the PHY revision in the hardware structure.
Definition at line 83 of file igb_phy.c.
References DEBUGFUNC, E1000_SUCCESS, e1000_phy_info::id, e1000_phy_info::ops, e1000_hw::phy, PHY_ID1, PHY_ID2, PHY_REVISION_MASK, e1000_phy_operations::read_reg, e1000_phy_info::revision, u16, u32, and usec_delay.
Referenced by igb_determine_phy_address(), and igb_get_phy_id_82575().
00084 { 00085 struct e1000_phy_info *phy = &hw->phy; 00086 s32 ret_val = E1000_SUCCESS; 00087 u16 phy_id; 00088 00089 DEBUGFUNC("igb_get_phy_id"); 00090 00091 if (!(phy->ops.read_reg)) 00092 goto out; 00093 00094 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 00095 if (ret_val) 00096 goto out; 00097 00098 phy->id = (u32)(phy_id << 16); 00099 usec_delay(20); 00100 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 00101 if (ret_val) 00102 goto out; 00103 00104 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 00105 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 00106 00107 out: 00108 return ret_val; 00109 }
igb_phy_reset_dsp_generic - Reset PHY DSP : pointer to the HW structure
Reset the digital signal processor.
Definition at line 117 of file igb_phy.c.
References DEBUGFUNC, E1000_SUCCESS, M88E1000_PHY_GEN_CONTROL, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::write_reg.
00118 { 00119 s32 ret_val = E1000_SUCCESS; 00120 00121 DEBUGFUNC("igb_phy_reset_dsp_generic"); 00122 00123 if (!(hw->phy.ops.write_reg)) 00124 goto out; 00125 00126 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 00127 if (ret_val) 00128 goto out; 00129 00130 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 00131 00132 out: 00133 return ret_val; 00134 }
igb_read_phy_reg_mdic - Read MDI control register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the MDI control register in the PHY at offset and stores the information read to data.
Definition at line 145 of file igb_phy.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT, E1000_ERR_PHY, E1000_GEN_POLL_TIMEOUT, E1000_MDIC, E1000_MDIC_ERROR, E1000_MDIC_OP_READ, E1000_MDIC_PHY_SHIFT, E1000_MDIC_READY, E1000_MDIC_REG_SHIFT, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::phy, u16, u32, and usec_delay.
Referenced by __igb_read_phy_reg_igp(), and igb_read_phy_reg_m88().
00146 { 00147 struct e1000_phy_info *phy = &hw->phy; 00148 u32 i, mdic = 0; 00149 s32 ret_val = E1000_SUCCESS; 00150 00151 DEBUGFUNC("igb_read_phy_reg_mdic"); 00152 00153 /* 00154 * Set up Op-code, Phy Address, and register offset in the MDI 00155 * Control register. The MAC will take care of interfacing with the 00156 * PHY to retrieve the desired data. 00157 */ 00158 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 00159 (phy->addr << E1000_MDIC_PHY_SHIFT) | 00160 (E1000_MDIC_OP_READ)); 00161 00162 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 00163 00164 /* 00165 * Poll the ready bit to see if the MDI read completed 00166 * Increasing the time out as testing showed failures with 00167 * the lower time out 00168 */ 00169 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 00170 usec_delay(50); 00171 mdic = E1000_READ_REG(hw, E1000_MDIC); 00172 if (mdic & E1000_MDIC_READY) 00173 break; 00174 } 00175 if (!(mdic & E1000_MDIC_READY)) { 00176 DEBUGOUT("MDI Read did not complete\n"); 00177 ret_val = -E1000_ERR_PHY; 00178 goto out; 00179 } 00180 if (mdic & E1000_MDIC_ERROR) { 00181 DEBUGOUT("MDI Error\n"); 00182 ret_val = -E1000_ERR_PHY; 00183 goto out; 00184 } 00185 *data = (u16) mdic; 00186 00187 out: 00188 return ret_val; 00189 }
igb_write_phy_reg_mdic - Write MDI control register : pointer to the HW structure : register offset to write to : data to write to register at offset
Writes data to MDI control register in the PHY at offset.
Definition at line 199 of file igb_phy.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT, E1000_ERR_PHY, E1000_GEN_POLL_TIMEOUT, E1000_MDIC, E1000_MDIC_ERROR, E1000_MDIC_OP_WRITE, E1000_MDIC_PHY_SHIFT, E1000_MDIC_READY, E1000_MDIC_REG_SHIFT, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::phy, u32, and usec_delay.
Referenced by __igb_read_phy_reg_igp(), __igb_write_phy_reg_igp(), and igb_write_phy_reg_m88().
00200 { 00201 struct e1000_phy_info *phy = &hw->phy; 00202 u32 i, mdic = 0; 00203 s32 ret_val = E1000_SUCCESS; 00204 00205 DEBUGFUNC("igb_write_phy_reg_mdic"); 00206 00207 /* 00208 * Set up Op-code, Phy Address, and register offset in the MDI 00209 * Control register. The MAC will take care of interfacing with the 00210 * PHY to retrieve the desired data. 00211 */ 00212 mdic = (((u32)data) | 00213 (offset << E1000_MDIC_REG_SHIFT) | 00214 (phy->addr << E1000_MDIC_PHY_SHIFT) | 00215 (E1000_MDIC_OP_WRITE)); 00216 00217 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 00218 00219 /* 00220 * Poll the ready bit to see if the MDI read completed 00221 * Increasing the time out as testing showed failures with 00222 * the lower time out 00223 */ 00224 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 00225 usec_delay(50); 00226 mdic = E1000_READ_REG(hw, E1000_MDIC); 00227 if (mdic & E1000_MDIC_READY) 00228 break; 00229 } 00230 if (!(mdic & E1000_MDIC_READY)) { 00231 DEBUGOUT("MDI Write did not complete\n"); 00232 ret_val = -E1000_ERR_PHY; 00233 goto out; 00234 } 00235 if (mdic & E1000_MDIC_ERROR) { 00236 DEBUGOUT("MDI Error\n"); 00237 ret_val = -E1000_ERR_PHY; 00238 goto out; 00239 } 00240 00241 out: 00242 return ret_val; 00243 }
igb_read_phy_reg_i2c - Read PHY register using i2c : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the PHY register at offset using the i2c interface and stores the retrieved information in data.
Definition at line 254 of file igb_phy.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT, E1000_ERR_PHY, E1000_I2CCMD, E1000_I2CCMD_ERROR, E1000_I2CCMD_OPCODE_READ, E1000_I2CCMD_PHY_ADDR_SHIFT, E1000_I2CCMD_PHY_TIMEOUT, E1000_I2CCMD_READY, E1000_I2CCMD_REG_ADDR_SHIFT, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::phy, u32, and usec_delay.
Referenced by igb_read_phy_reg_sgmii_82575().
00255 { 00256 struct e1000_phy_info *phy = &hw->phy; 00257 u32 i, i2ccmd = 0; 00258 00259 DEBUGFUNC("igb_read_phy_reg_i2c"); 00260 00261 /* 00262 * Set up Op-code, Phy Address, and register address in the I2CCMD 00263 * register. The MAC will take care of interfacing with the 00264 * PHY to retrieve the desired data. 00265 */ 00266 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 00267 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 00268 (E1000_I2CCMD_OPCODE_READ)); 00269 00270 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 00271 00272 /* Poll the ready bit to see if the I2C read completed */ 00273 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 00274 usec_delay(50); 00275 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 00276 if (i2ccmd & E1000_I2CCMD_READY) 00277 break; 00278 } 00279 if (!(i2ccmd & E1000_I2CCMD_READY)) { 00280 DEBUGOUT("I2CCMD Read did not complete\n"); 00281 return -E1000_ERR_PHY; 00282 } 00283 if (i2ccmd & E1000_I2CCMD_ERROR) { 00284 DEBUGOUT("I2CCMD Error bit set\n"); 00285 return -E1000_ERR_PHY; 00286 } 00287 00288 /* Need to byte-swap the 16-bit value. */ 00289 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 00290 00291 return E1000_SUCCESS; 00292 }
igb_write_phy_reg_i2c - Write PHY register using i2c : pointer to the HW structure : register offset to write to : data to write at register offset
Writes the data to PHY register at the offset using the i2c interface.
Definition at line 302 of file igb_phy.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT, E1000_ERR_PHY, E1000_I2CCMD, E1000_I2CCMD_ERROR, E1000_I2CCMD_OPCODE_WRITE, E1000_I2CCMD_PHY_ADDR_SHIFT, E1000_I2CCMD_PHY_TIMEOUT, E1000_I2CCMD_READY, E1000_I2CCMD_REG_ADDR_SHIFT, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::phy, u16, u32, and usec_delay.
Referenced by igb_write_phy_reg_sgmii_82575().
00303 { 00304 struct e1000_phy_info *phy = &hw->phy; 00305 u32 i, i2ccmd = 0; 00306 u16 phy_data_swapped; 00307 00308 DEBUGFUNC("igb_write_phy_reg_i2c"); 00309 00310 /* Swap the data bytes for the I2C interface */ 00311 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 00312 00313 /* 00314 * Set up Op-code, Phy Address, and register address in the I2CCMD 00315 * register. The MAC will take care of interfacing with the 00316 * PHY to retrieve the desired data. 00317 */ 00318 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 00319 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 00320 E1000_I2CCMD_OPCODE_WRITE | 00321 phy_data_swapped); 00322 00323 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 00324 00325 /* Poll the ready bit to see if the I2C read completed */ 00326 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 00327 usec_delay(50); 00328 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 00329 if (i2ccmd & E1000_I2CCMD_READY) 00330 break; 00331 } 00332 if (!(i2ccmd & E1000_I2CCMD_READY)) { 00333 DEBUGOUT("I2CCMD Write did not complete\n"); 00334 return -E1000_ERR_PHY; 00335 } 00336 if (i2ccmd & E1000_I2CCMD_ERROR) { 00337 DEBUGOUT("I2CCMD Error bit set\n"); 00338 return -E1000_ERR_PHY; 00339 } 00340 00341 return E1000_SUCCESS; 00342 }
igb_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 354 of file igb_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_SUCCESS, igb_read_phy_reg_mdic(), MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::release.
00355 { 00356 s32 ret_val = E1000_SUCCESS; 00357 00358 DEBUGFUNC("igb_read_phy_reg_m88"); 00359 00360 if (!(hw->phy.ops.acquire)) 00361 goto out; 00362 00363 ret_val = hw->phy.ops.acquire(hw); 00364 if (ret_val) 00365 goto out; 00366 00367 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00368 data); 00369 00370 hw->phy.ops.release(hw); 00371 00372 out: 00373 return ret_val; 00374 }
igb_write_phy_reg_m88 - Write m88 PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 385 of file igb_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_SUCCESS, igb_write_phy_reg_mdic(), MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::release.
00386 { 00387 s32 ret_val = E1000_SUCCESS; 00388 00389 DEBUGFUNC("igb_write_phy_reg_m88"); 00390 00391 if (!(hw->phy.ops.acquire)) 00392 goto out; 00393 00394 ret_val = hw->phy.ops.acquire(hw); 00395 if (ret_val) 00396 goto out; 00397 00398 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00399 data); 00400 00401 hw->phy.ops.release(hw); 00402 00403 out: 00404 return ret_val; 00405 }
| static s32 __igb_read_phy_reg_igp | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u16 * | data, | |||
| bool | locked | |||
| ) | [static] |
__igb_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data : semaphore has already been acquired or not
Acquires semaphore, if necessary, then reads the PHY register at offset and stores the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 418 of file igb_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_SUCCESS, igb_read_phy_reg_mdic(), igb_write_phy_reg_mdic(), IGP01E1000_PHY_PAGE_SELECT, MAX_PHY_MULTI_PAGE_REG, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, and u16.
Referenced by igb_read_phy_reg_igp(), and igb_read_phy_reg_igp_locked().
00420 { 00421 s32 ret_val = E1000_SUCCESS; 00422 00423 DEBUGFUNC("__igb_read_phy_reg_igp"); 00424 00425 if (!locked) { 00426 if (!(hw->phy.ops.acquire)) 00427 goto out; 00428 00429 ret_val = hw->phy.ops.acquire(hw); 00430 if (ret_val) 00431 goto out; 00432 } 00433 00434 if (offset > MAX_PHY_MULTI_PAGE_REG) { 00435 ret_val = igb_write_phy_reg_mdic(hw, 00436 IGP01E1000_PHY_PAGE_SELECT, 00437 (u16)offset); 00438 if (ret_val) 00439 goto release; 00440 } 00441 00442 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00443 data); 00444 00445 release: 00446 if (!locked) 00447 hw->phy.ops.release(hw); 00448 out: 00449 return ret_val; 00450 }
igb_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore then reads the PHY register at offset and stores the retrieved information in data. Release the acquired semaphore before exiting.
Definition at line 461 of file igb_phy.c.
References __igb_read_phy_reg_igp().
Referenced by igb_init_phy_params_82575().
00462 { 00463 return __igb_read_phy_reg_igp(hw, offset, data, false); 00464 }
igb_read_phy_reg_igp_locked - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the PHY register at offset and stores the retrieved information in data. Assumes semaphore already acquired.
Definition at line 475 of file igb_phy.c.
References __igb_read_phy_reg_igp().
00476 { 00477 return __igb_read_phy_reg_igp(hw, offset, data, true); 00478 }
| static s32 __igb_write_phy_reg_igp | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u16 | data, | |||
| bool | locked | |||
| ) | [static] |
igb_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset : semaphore has already been acquired or not
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 490 of file igb_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_SUCCESS, igb_write_phy_reg_mdic(), IGP01E1000_PHY_PAGE_SELECT, MAX_PHY_MULTI_PAGE_REG, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, and u16.
Referenced by igb_write_phy_reg_igp(), and igb_write_phy_reg_igp_locked().
00492 { 00493 s32 ret_val = E1000_SUCCESS; 00494 00495 DEBUGFUNC("igb_write_phy_reg_igp"); 00496 00497 if (!locked) { 00498 if (!(hw->phy.ops.acquire)) 00499 goto out; 00500 00501 ret_val = hw->phy.ops.acquire(hw); 00502 if (ret_val) 00503 goto out; 00504 } 00505 00506 if (offset > MAX_PHY_MULTI_PAGE_REG) { 00507 ret_val = igb_write_phy_reg_mdic(hw, 00508 IGP01E1000_PHY_PAGE_SELECT, 00509 (u16)offset); 00510 if (ret_val) 00511 goto release; 00512 } 00513 00514 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00515 data); 00516 00517 release: 00518 if (!locked) 00519 hw->phy.ops.release(hw); 00520 00521 out: 00522 return ret_val; 00523 }
igb_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 534 of file igb_phy.c.
References __igb_write_phy_reg_igp().
Referenced by igb_init_phy_params_82575().
00535 { 00536 return __igb_write_phy_reg_igp(hw, offset, data, false); 00537 }
igb_write_phy_reg_igp_locked - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Writes the data to PHY register at the offset. Assumes semaphore already acquired.
Definition at line 548 of file igb_phy.c.
References __igb_write_phy_reg_igp().
00549 { 00550 return __igb_write_phy_reg_igp(hw, offset, data, true); 00551 }
| static s32 __igb_read_kmrn_reg | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u16 * | data, | |||
| bool | locked | |||
| ) | [static] |
__igb_read_kmrn_reg - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data : semaphore has already been acquired or not
Acquires semaphore, if necessary. Then reads the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Release any acquired semaphores before exiting.
Definition at line 564 of file igb_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_KMRNCTRLSTA, E1000_KMRNCTRLSTA_OFFSET, E1000_KMRNCTRLSTA_OFFSET_SHIFT, E1000_KMRNCTRLSTA_REN, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, u16, u32, and usec_delay.
Referenced by igb_read_kmrn_reg_generic(), and igb_read_kmrn_reg_locked().
00566 { 00567 u32 kmrnctrlsta; 00568 s32 ret_val = E1000_SUCCESS; 00569 00570 DEBUGFUNC("__igb_read_kmrn_reg"); 00571 00572 if (!locked) { 00573 if (!(hw->phy.ops.acquire)) 00574 goto out; 00575 00576 ret_val = hw->phy.ops.acquire(hw); 00577 if (ret_val) 00578 goto out; 00579 } 00580 00581 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 00582 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 00583 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 00584 00585 usec_delay(2); 00586 00587 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 00588 *data = (u16)kmrnctrlsta; 00589 00590 if (!locked) 00591 hw->phy.ops.release(hw); 00592 00593 out: 00594 return ret_val; 00595 }
igb_read_kmrn_reg_generic - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore then reads the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Release the acquired semaphore before exiting.
Definition at line 607 of file igb_phy.c.
References __igb_read_kmrn_reg().
Referenced by igb_read_kmrn_reg().
00608 { 00609 return __igb_read_kmrn_reg(hw, offset, data, false); 00610 }
igb_read_kmrn_reg_locked - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Assumes semaphore already acquired.
Definition at line 622 of file igb_phy.c.
References __igb_read_kmrn_reg().
00623 { 00624 return __igb_read_kmrn_reg(hw, offset, data, true); 00625 }
| static s32 __igb_write_kmrn_reg | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u16 | data, | |||
| bool | locked | |||
| ) | [static] |
__igb_write_kmrn_reg - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset : semaphore has already been acquired or not
Acquires semaphore, if necessary. Then write the data to PHY register at the offset using the kumeran interface. Release any acquired semaphores before exiting.
Definition at line 638 of file igb_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_KMRNCTRLSTA, E1000_KMRNCTRLSTA_OFFSET, E1000_KMRNCTRLSTA_OFFSET_SHIFT, E1000_SUCCESS, E1000_WRITE_REG, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, u32, and usec_delay.
Referenced by igb_write_kmrn_reg_generic(), and igb_write_kmrn_reg_locked().
00640 { 00641 u32 kmrnctrlsta; 00642 s32 ret_val = E1000_SUCCESS; 00643 00644 DEBUGFUNC("igb_write_kmrn_reg_generic"); 00645 00646 if (!locked) { 00647 if (!(hw->phy.ops.acquire)) 00648 goto out; 00649 00650 ret_val = hw->phy.ops.acquire(hw); 00651 if (ret_val) 00652 goto out; 00653 } 00654 00655 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 00656 E1000_KMRNCTRLSTA_OFFSET) | data; 00657 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 00658 00659 usec_delay(2); 00660 00661 if (!locked) 00662 hw->phy.ops.release(hw); 00663 00664 out: 00665 return ret_val; 00666 }
igb_write_kmrn_reg_generic - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore then writes the data to the PHY register at the offset using the kumeran interface. Release the acquired semaphore before exiting.
Definition at line 677 of file igb_phy.c.
References __igb_write_kmrn_reg().
Referenced by igb_write_kmrn_reg().
00678 { 00679 return __igb_write_kmrn_reg(hw, offset, data, false); 00680 }
igb_write_kmrn_reg_locked - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset
Write the data to PHY register at the offset using the kumeran interface. Assumes semaphore already acquired.
Definition at line 691 of file igb_phy.c.
References __igb_write_kmrn_reg().
00692 { 00693 return __igb_write_kmrn_reg(hw, offset, data, true); 00694 }
igb_copper_link_setup_m88 - Setup m88 PHY's for copper link : pointer to the HW structure
Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock and downshift values are set also.
Definition at line 703 of file igb_phy.c.
References e1000_phy_operations::commit, DEBUGFUNC, DEBUGOUT, e1000_phy_info::disable_polarity_correction, E1000_REVISION_2, E1000_REVISION_4, E1000_SUCCESS, e1000_phy_info::id, M88E1000_EPSCR_MASTER_DOWNSHIFT_1X, M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK, M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X, M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK, M88E1000_EPSCR_TX_CLK_25, M88E1000_EXT_PHY_SPEC_CTRL, M88E1000_PHY_SPEC_CTRL, M88E1000_PSCR_ASSERT_CRS_ON_TX, M88E1000_PSCR_AUTO_X_1000T, M88E1000_PSCR_AUTO_X_MODE, M88E1000_PSCR_MDI_MANUAL_MODE, M88E1000_PSCR_MDIX_MANUAL_MODE, M88E1000_PSCR_POLARITY_REVERSAL, M88E1111_I_PHY_ID, M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X, M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK, e1000_phy_info::mdix, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::reset_disable, e1000_phy_info::revision, u16, and e1000_phy_operations::write_reg.
Referenced by igb_setup_copper_link_82575().
00704 { 00705 struct e1000_phy_info *phy = &hw->phy; 00706 s32 ret_val; 00707 u16 phy_data; 00708 00709 DEBUGFUNC("igb_copper_link_setup_m88"); 00710 00711 if (phy->reset_disable) { 00712 ret_val = E1000_SUCCESS; 00713 goto out; 00714 } 00715 00716 /* Enable CRS on TX. This must be set for half-duplex operation. */ 00717 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 00718 if (ret_val) 00719 goto out; 00720 00721 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 00722 00723 /* 00724 * Options: 00725 * MDI/MDI-X = 0 (default) 00726 * 0 - Auto for all speeds 00727 * 1 - MDI mode 00728 * 2 - MDI-X mode 00729 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 00730 */ 00731 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 00732 00733 switch (phy->mdix) { 00734 case 1: 00735 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 00736 break; 00737 case 2: 00738 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 00739 break; 00740 case 3: 00741 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 00742 break; 00743 case 0: 00744 default: 00745 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 00746 break; 00747 } 00748 00749 /* 00750 * Options: 00751 * disable_polarity_correction = 0 (default) 00752 * Automatic Correction for Reversed Cable Polarity 00753 * 0 - Disabled 00754 * 1 - Enabled 00755 */ 00756 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 00757 if (phy->disable_polarity_correction == 1) 00758 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 00759 00760 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 00761 if (ret_val) 00762 goto out; 00763 00764 if (phy->revision < E1000_REVISION_4) { 00765 /* 00766 * Force TX_CLK in the Extended PHY Specific Control Register 00767 * to 25MHz clock. 00768 */ 00769 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00770 &phy_data); 00771 if (ret_val) 00772 goto out; 00773 00774 phy_data |= M88E1000_EPSCR_TX_CLK_25; 00775 00776 if ((phy->revision == E1000_REVISION_2) && 00777 (phy->id == M88E1111_I_PHY_ID)) { 00778 /* 82573L PHY - set the downshift counter to 5x. */ 00779 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 00780 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 00781 } else { 00782 /* Configure Master and Slave downshift values */ 00783 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 00784 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 00785 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 00786 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 00787 } 00788 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00789 phy_data); 00790 if (ret_val) 00791 goto out; 00792 } 00793 00794 /* Commit the changes. */ 00795 ret_val = phy->ops.commit(hw); 00796 if (ret_val) { 00797 DEBUGOUT("Error committing the PHY changes\n"); 00798 goto out; 00799 } 00800 00801 out: 00802 return ret_val; 00803 }
igb_copper_link_setup_igp - Setup igp PHY's for copper link : pointer to the HW structure
Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for igp PHY's.
Definition at line 812 of file igb_phy.c.
References ADVERTISE_1000_FULL, e1000_mac_info::autoneg, e1000_phy_info::autoneg_advertised, CR_1000T_MS_ENABLE, CR_1000T_MS_VALUE, DEBUGFUNC, DEBUGOUT, e1000_ms_auto, e1000_ms_force_master, e1000_ms_force_slave, e1000_phy_igp, E1000_SUCCESS, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PHY_PORT_CTRL, IGP01E1000_PSCFR_SMART_SPEED, IGP01E1000_PSCR_AUTO_MDIX, IGP01E1000_PSCR_FORCE_MDI_MDIX, e1000_hw::mac, e1000_phy_info::mdix, e1000_phy_info::ms_type, msec_delay, e1000_phy_info::ops, e1000_phy_info::original_ms_type, e1000_hw::phy, PHY_1000T_CTRL, e1000_phy_operations::read_reg, e1000_phy_operations::reset, e1000_phy_info::reset_disable, e1000_phy_operations::set_d0_lplu_state, e1000_phy_operations::set_d3_lplu_state, e1000_phy_info::type, u16, and e1000_phy_operations::write_reg.
Referenced by igb_setup_copper_link_82575().
00813 { 00814 struct e1000_phy_info *phy = &hw->phy; 00815 s32 ret_val; 00816 u16 data; 00817 00818 DEBUGFUNC("igb_copper_link_setup_igp"); 00819 00820 if (phy->reset_disable) { 00821 ret_val = E1000_SUCCESS; 00822 goto out; 00823 } 00824 00825 ret_val = hw->phy.ops.reset(hw); 00826 if (ret_val) { 00827 DEBUGOUT("Error resetting the PHY.\n"); 00828 goto out; 00829 } 00830 00831 /* 00832 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 00833 * timeout issues when LFS is enabled. 00834 */ 00835 msec_delay(100); 00836 00837 /* 00838 * The NVM settings will configure LPLU in D3 for 00839 * non-IGP1 PHYs. 00840 */ 00841 if (phy->type == e1000_phy_igp) { 00842 /* disable lplu d3 during driver init */ 00843 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 00844 if (ret_val) { 00845 DEBUGOUT("Error Disabling LPLU D3\n"); 00846 goto out; 00847 } 00848 } 00849 00850 /* disable lplu d0 during driver init */ 00851 if (hw->phy.ops.set_d0_lplu_state) { 00852 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 00853 if (ret_val) { 00854 DEBUGOUT("Error Disabling LPLU D0\n"); 00855 goto out; 00856 } 00857 } 00858 /* Configure mdi-mdix settings */ 00859 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 00860 if (ret_val) 00861 goto out; 00862 00863 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 00864 00865 switch (phy->mdix) { 00866 case 1: 00867 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 00868 break; 00869 case 2: 00870 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 00871 break; 00872 case 0: 00873 default: 00874 data |= IGP01E1000_PSCR_AUTO_MDIX; 00875 break; 00876 } 00877 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 00878 if (ret_val) 00879 goto out; 00880 00881 /* set auto-master slave resolution settings */ 00882 if (hw->mac.autoneg) { 00883 /* 00884 * when autonegotiation advertisement is only 1000Mbps then we 00885 * should disable SmartSpeed and enable Auto MasterSlave 00886 * resolution as hardware default. 00887 */ 00888 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 00889 /* Disable SmartSpeed */ 00890 ret_val = phy->ops.read_reg(hw, 00891 IGP01E1000_PHY_PORT_CONFIG, 00892 &data); 00893 if (ret_val) 00894 goto out; 00895 00896 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 00897 ret_val = phy->ops.write_reg(hw, 00898 IGP01E1000_PHY_PORT_CONFIG, 00899 data); 00900 if (ret_val) 00901 goto out; 00902 00903 /* Set auto Master/Slave resolution process */ 00904 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 00905 if (ret_val) 00906 goto out; 00907 00908 data &= ~CR_1000T_MS_ENABLE; 00909 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 00910 if (ret_val) 00911 goto out; 00912 } 00913 00914 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 00915 if (ret_val) 00916 goto out; 00917 00918 /* load defaults for future use */ 00919 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 00920 ((data & CR_1000T_MS_VALUE) ? 00921 e1000_ms_force_master : 00922 e1000_ms_force_slave) : 00923 e1000_ms_auto; 00924 00925 switch (phy->ms_type) { 00926 case e1000_ms_force_master: 00927 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 00928 break; 00929 case e1000_ms_force_slave: 00930 data |= CR_1000T_MS_ENABLE; 00931 data &= ~(CR_1000T_MS_VALUE); 00932 break; 00933 case e1000_ms_auto: 00934 data &= ~CR_1000T_MS_ENABLE; 00935 default: 00936 break; 00937 } 00938 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 00939 if (ret_val) 00940 goto out; 00941 } 00942 00943 out: 00944 return ret_val; 00945 }
igb_copper_link_autoneg - Setup/Enable autoneg for copper link : pointer to the HW structure
Performs initial bounds checking on autoneg advertisement parameter, then configure to advertise the full capability. Setup the PHY to autoneg and restart the negotiation process between the link partner. If autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
Definition at line 956 of file igb_phy.c.
References e1000_phy_info::autoneg_advertised, e1000_phy_info::autoneg_mask, e1000_phy_info::autoneg_wait_to_complete, DEBUGFUNC, DEBUGOUT, e1000_mac_info::get_link_status, igb_phy_setup_autoneg(), e1000_hw::mac, MII_CR_AUTO_NEG_EN, MII_CR_RESTART_AUTO_NEG, e1000_mac_info::ops, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, e1000_mac_operations::wait_autoneg, and e1000_phy_operations::write_reg.
Referenced by igb_setup_copper_link_generic().
00957 { 00958 struct e1000_phy_info *phy = &hw->phy; 00959 s32 ret_val; 00960 u16 phy_ctrl; 00961 00962 DEBUGFUNC("igb_copper_link_autoneg"); 00963 00964 /* 00965 * Perform some bounds checking on the autoneg advertisement 00966 * parameter. 00967 */ 00968 phy->autoneg_advertised &= phy->autoneg_mask; 00969 00970 /* 00971 * If autoneg_advertised is zero, we assume it was not defaulted 00972 * by the calling code so we set to advertise full capability. 00973 */ 00974 if (phy->autoneg_advertised == 0) 00975 phy->autoneg_advertised = phy->autoneg_mask; 00976 00977 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 00978 ret_val = igb_phy_setup_autoneg(hw); 00979 if (ret_val) { 00980 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 00981 goto out; 00982 } 00983 DEBUGOUT("Restarting Auto-Neg\n"); 00984 00985 /* 00986 * Restart auto-negotiation by setting the Auto Neg Enable bit and 00987 * the Auto Neg Restart bit in the PHY control register. 00988 */ 00989 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 00990 if (ret_val) 00991 goto out; 00992 00993 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 00994 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 00995 if (ret_val) 00996 goto out; 00997 00998 /* 00999 * Does the user want to wait for Auto-Neg to complete here, or 01000 * check at a later time (for example, callback routine). 01001 */ 01002 if (phy->autoneg_wait_to_complete) { 01003 ret_val = hw->mac.ops.wait_autoneg(hw); 01004 if (ret_val) { 01005 DEBUGOUT("Error while waiting for " 01006 "autoneg to complete\n"); 01007 goto out; 01008 } 01009 } 01010 01011 hw->mac.get_link_status = true; 01012 01013 out: 01014 return ret_val; 01015 }
igb_setup_copper_link_generic - Configure copper link settings : pointer to the HW structure
Calls the appropriate function to configure the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called. If link is not established, we return -E1000_ERR_PHY (-2).
Definition at line 1192 of file igb_phy.c.
References e1000_mac_info::autoneg, COPPER_LINK_UP_LIMIT, DEBUGFUNC, DEBUGOUT, igb_config_collision_dist_generic(), igb_config_fc_after_link_up_generic(), igb_copper_link_autoneg(), igb_phy_has_link_generic(), e1000_hw::mac, e1000_phy_info::ops, and e1000_hw::phy.
Referenced by igb_setup_copper_link_82575().
01193 { 01194 s32 ret_val; 01195 bool link; 01196 01197 DEBUGFUNC("igb_setup_copper_link_generic"); 01198 01199 if (hw->mac.autoneg) { 01200 /* 01201 * Setup autoneg and flow control advertisement and perform 01202 * autonegotiation. 01203 */ 01204 ret_val = igb_copper_link_autoneg(hw); 01205 if (ret_val) 01206 goto out; 01207 } else { 01208 #if 0 01209 /* 01210 * PHY will be set to 10H, 10F, 100H or 100F 01211 * depending on user settings. 01212 */ 01213 DEBUGOUT("Forcing Speed and Duplex\n"); 01214 ret_val = hw->phy.ops.force_speed_duplex(hw); 01215 if (ret_val) { 01216 DEBUGOUT("Error Forcing Speed and Duplex\n"); 01217 goto out; 01218 } 01219 #endif 01220 } 01221 01222 /* 01223 * Check link status. Wait up to 100 microseconds for link to become 01224 * valid. 01225 */ 01226 ret_val = igb_phy_has_link_generic(hw, 01227 COPPER_LINK_UP_LIMIT, 01228 10, 01229 &link); 01230 if (ret_val) 01231 goto out; 01232 01233 if (link) { 01234 DEBUGOUT("Valid link established!!!\n"); 01235 igb_config_collision_dist_generic(hw); 01236 ret_val = igb_config_fc_after_link_up_generic(hw); 01237 } else { 01238 DEBUGOUT("Unable to establish link!!!\n"); 01239 } 01240 01241 out: 01242 return ret_val; 01243 }
igb_set_d3_lplu_state_generic - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu
Success returns 0, Failure returns 1
The low power link up (lplu) state is set to the power management level D3 and SmartSpeed is disabled when active is true, else clear lplu for D3 and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU is used during Dx states where the power conservation is most important. During driver activity, SmartSpeed should be enabled so performance is maintained.
Definition at line 1583 of file igb_phy.c.
References e1000_phy_info::autoneg_advertised, DEBUGFUNC, E1000_ALL_10_SPEED, E1000_ALL_NOT_GIG, E1000_ALL_SPEED_DUPLEX, e1000_smart_speed_off, e1000_smart_speed_on, E1000_SUCCESS, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PSCFR_SMART_SPEED, IGP02E1000_PHY_POWER_MGMT, IGP02E1000_PM_D3_LPLU, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::smart_speed, u16, and e1000_phy_operations::write_reg.
Referenced by igb_init_phy_params_82575().
01584 { 01585 struct e1000_phy_info *phy = &hw->phy; 01586 s32 ret_val = E1000_SUCCESS; 01587 u16 data; 01588 01589 DEBUGFUNC("igb_set_d3_lplu_state_generic"); 01590 01591 if (!(hw->phy.ops.read_reg)) 01592 goto out; 01593 01594 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 01595 if (ret_val) 01596 goto out; 01597 01598 if (!active) { 01599 data &= ~IGP02E1000_PM_D3_LPLU; 01600 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 01601 data); 01602 if (ret_val) 01603 goto out; 01604 /* 01605 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 01606 * during Dx states where the power conservation is most 01607 * important. During driver activity we should enable 01608 * SmartSpeed, so performance is maintained. 01609 */ 01610 if (phy->smart_speed == e1000_smart_speed_on) { 01611 ret_val = phy->ops.read_reg(hw, 01612 IGP01E1000_PHY_PORT_CONFIG, 01613 &data); 01614 if (ret_val) 01615 goto out; 01616 01617 data |= IGP01E1000_PSCFR_SMART_SPEED; 01618 ret_val = phy->ops.write_reg(hw, 01619 IGP01E1000_PHY_PORT_CONFIG, 01620 data); 01621 if (ret_val) 01622 goto out; 01623 } else if (phy->smart_speed == e1000_smart_speed_off) { 01624 ret_val = phy->ops.read_reg(hw, 01625 IGP01E1000_PHY_PORT_CONFIG, 01626 &data); 01627 if (ret_val) 01628 goto out; 01629 01630 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01631 ret_val = phy->ops.write_reg(hw, 01632 IGP01E1000_PHY_PORT_CONFIG, 01633 data); 01634 if (ret_val) 01635 goto out; 01636 } 01637 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 01638 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 01639 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 01640 data |= IGP02E1000_PM_D3_LPLU; 01641 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 01642 data); 01643 if (ret_val) 01644 goto out; 01645 01646 /* When LPLU is enabled, we should disable SmartSpeed */ 01647 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 01648 &data); 01649 if (ret_val) 01650 goto out; 01651 01652 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01653 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 01654 data); 01655 } 01656 01657 out: 01658 return ret_val; 01659 }
igb_check_downshift_generic - Checks whether a downshift in speed occurred : pointer to the HW structure
Success returns 0, Failure returns 1
A downshift is detected by querying the PHY link health.
Definition at line 1669 of file igb_phy.c.
References DEBUGFUNC, e1000_phy_gg82563, e1000_phy_igp, e1000_phy_igp_2, e1000_phy_igp_3, e1000_phy_m88, E1000_SUCCESS, IGP01E1000_PHY_LINK_HEALTH, IGP01E1000_PLHR_SS_DOWNGRADE, M88E1000_PHY_SPEC_STATUS, M88E1000_PSSR_DOWNSHIFT, offset, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::speed_downgraded, e1000_phy_info::type, and u16.
Referenced by igb_check_for_copper_link_generic().
01670 { 01671 struct e1000_phy_info *phy = &hw->phy; 01672 s32 ret_val; 01673 u16 phy_data, offset, mask; 01674 01675 DEBUGFUNC("igb_check_downshift_generic"); 01676 01677 switch (phy->type) { 01678 case e1000_phy_m88: 01679 case e1000_phy_gg82563: 01680 offset = M88E1000_PHY_SPEC_STATUS; 01681 mask = M88E1000_PSSR_DOWNSHIFT; 01682 break; 01683 case e1000_phy_igp_2: 01684 case e1000_phy_igp: 01685 case e1000_phy_igp_3: 01686 offset = IGP01E1000_PHY_LINK_HEALTH; 01687 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 01688 break; 01689 default: 01690 /* speed downshift not supported */ 01691 phy->speed_downgraded = false; 01692 ret_val = E1000_SUCCESS; 01693 goto out; 01694 } 01695 01696 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 01697 01698 if (!ret_val) 01699 phy->speed_downgraded = (phy_data & mask) ? true : false; 01700 01701 out: 01702 return ret_val; 01703 }
igb_check_polarity_m88 - Checks the polarity.
: pointer to the HW structure
Success returns 0, Failure returns -E1000_ERR_PHY (-2)
Polarity is determined based on the PHY specific status register.
Definition at line 1713 of file igb_phy.c.
References e1000_phy_info::cable_polarity, DEBUGFUNC, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, M88E1000_PHY_SPEC_STATUS, M88E1000_PSSR_REV_POLARITY, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, and u16.
Referenced by igb_get_phy_info_m88(), and igb_init_phy_params_82575().
01714 { 01715 struct e1000_phy_info *phy = &hw->phy; 01716 s32 ret_val; 01717 u16 data; 01718 01719 DEBUGFUNC("igb_check_polarity_m88"); 01720 01721 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 01722 01723 if (!ret_val) 01724 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 01725 ? e1000_rev_polarity_reversed 01726 : e1000_rev_polarity_normal; 01727 01728 return ret_val; 01729 }
igb_check_polarity_igp - Checks the polarity.
: pointer to the HW structure
Success returns 0, Failure returns -E1000_ERR_PHY (-2)
Polarity is determined based on the PHY port status register, and the current speed (since there is no polarity at 100Mbps).
Definition at line 1740 of file igb_phy.c.
References e1000_phy_info::cable_polarity, DEBUGFUNC, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, IGP01E1000_PHY_PCS_INIT_REG, IGP01E1000_PHY_POLARITY_MASK, IGP01E1000_PHY_PORT_STATUS, IGP01E1000_PSSR_POLARITY_REVERSED, IGP01E1000_PSSR_SPEED_1000MBPS, IGP01E1000_PSSR_SPEED_MASK, offset, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, and u16.
Referenced by igb_get_phy_info_igp(), and igb_init_phy_params_82575().
01741 { 01742 struct e1000_phy_info *phy = &hw->phy; 01743 s32 ret_val; 01744 u16 data, offset, mask; 01745 01746 DEBUGFUNC("igb_check_polarity_igp"); 01747 01748 /* 01749 * Polarity is determined based on the speed of 01750 * our connection. 01751 */ 01752 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 01753 if (ret_val) 01754 goto out; 01755 01756 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 01757 IGP01E1000_PSSR_SPEED_1000MBPS) { 01758 offset = IGP01E1000_PHY_PCS_INIT_REG; 01759 mask = IGP01E1000_PHY_POLARITY_MASK; 01760 } else { 01761 /* 01762 * This really only applies to 10Mbps since 01763 * there is no polarity for 100Mbps (always 0). 01764 */ 01765 offset = IGP01E1000_PHY_PORT_STATUS; 01766 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 01767 } 01768 01769 ret_val = phy->ops.read_reg(hw, offset, &data); 01770 01771 if (!ret_val) 01772 phy->cable_polarity = (data & mask) 01773 ? e1000_rev_polarity_reversed 01774 : e1000_rev_polarity_normal; 01775 01776 out: 01777 return ret_val; 01778 }
igb_check_polarity_ife - Check cable polarity for IFE PHY : pointer to the HW structure
Polarity is determined on the polarity reversal feature being enabled.
Definition at line 1786 of file igb_phy.c.
References e1000_phy_info::cable_polarity, DEBUGFUNC, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, IFE_PESC_POLARITY_REVERSED, IFE_PHY_EXTENDED_STATUS_CONTROL, IFE_PHY_SPECIAL_CONTROL, IFE_PSC_FORCE_POLARITY, offset, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_info::polarity_correction, e1000_phy_operations::read_reg, and u16.
01787 { 01788 struct e1000_phy_info *phy = &hw->phy; 01789 s32 ret_val; 01790 u16 phy_data, offset, mask; 01791 01792 DEBUGFUNC("igb_check_polarity_ife"); 01793 01794 /* 01795 * Polarity is determined based on the reversal feature being enabled. 01796 */ 01797 if (phy->polarity_correction) { 01798 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 01799 mask = IFE_PESC_POLARITY_REVERSED; 01800 } else { 01801 offset = IFE_PHY_SPECIAL_CONTROL; 01802 mask = IFE_PSC_FORCE_POLARITY; 01803 } 01804 01805 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 01806 01807 if (!ret_val) 01808 phy->cable_polarity = (phy_data & mask) 01809 ? e1000_rev_polarity_reversed 01810 : e1000_rev_polarity_normal; 01811 01812 return ret_val; 01813 }
igb_wait_autoneg_generic - Wait for auto-neg completion : pointer to the HW structure
Waits for auto-negotiation to complete or for the auto-negotiation time limit to expire, which ever happens first.
Definition at line 1822 of file igb_phy.c.
References DEBUGFUNC, E1000_SUCCESS, MII_SR_AUTONEG_COMPLETE, msec_delay, e1000_phy_info::ops, e1000_hw::phy, PHY_AUTO_NEG_LIMIT, PHY_STATUS, e1000_phy_operations::read_reg, and u16.
Referenced by igb_init_mac_ops_generic().
01823 { 01824 s32 ret_val = E1000_SUCCESS; 01825 u16 i, phy_status; 01826 01827 DEBUGFUNC("igb_wait_autoneg_generic"); 01828 01829 if (!(hw->phy.ops.read_reg)) 01830 return E1000_SUCCESS; 01831 01832 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 01833 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 01834 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 01835 if (ret_val) 01836 break; 01837 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 01838 if (ret_val) 01839 break; 01840 if (phy_status & MII_SR_AUTONEG_COMPLETE) 01841 break; 01842 msec_delay(100); 01843 } 01844 01845 /* 01846 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 01847 * has completed. 01848 */ 01849 return ret_val; 01850 }
| s32 igb_phy_has_link_generic | ( | struct e1000_hw * | hw, | |
| u32 | iterations, | |||
| u32 | usec_interval, | |||
| bool * | success | |||
| ) |
igb_phy_has_link_generic - Polls PHY for link : pointer to the HW structure : number of times to poll for link : delay between polling attempts : pointer to whether polling was successful or not
Polls the PHY status register for link, 'iterations' number of times.
Definition at line 1861 of file igb_phy.c.
References DEBUGFUNC, E1000_SUCCESS, MII_SR_LINK_STATUS, msec_delay_irq, e1000_phy_info::ops, e1000_hw::phy, PHY_STATUS, e1000_phy_operations::read_reg, u16, and usec_delay.
Referenced by igb_check_for_copper_link_generic(), igb_get_phy_info_igp(), igb_get_phy_info_m88(), and igb_setup_copper_link_generic().
01863 { 01864 s32 ret_val = E1000_SUCCESS; 01865 u16 i, phy_status; 01866 01867 DEBUGFUNC("igb_phy_has_link_generic"); 01868 01869 if (!(hw->phy.ops.read_reg)) 01870 return E1000_SUCCESS; 01871 01872 for (i = 0; i < iterations; i++) { 01873 /* 01874 * Some PHYs require the PHY_STATUS register to be read 01875 * twice due to the link bit being sticky. No harm doing 01876 * it across the board. 01877 */ 01878 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 01879 if (ret_val) { 01880 /* 01881 * If the first read fails, another entity may have 01882 * ownership of the resources, wait and try again to 01883 * see if they have relinquished the resources yet. 01884 */ 01885 usec_delay(usec_interval); 01886 } 01887 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 01888 if (ret_val) 01889 break; 01890 if (phy_status & MII_SR_LINK_STATUS) 01891 break; 01892 if (usec_interval >= 1000) 01893 msec_delay_irq(usec_interval/1000); 01894 else 01895 usec_delay(usec_interval); 01896 } 01897 01898 *success = (i < iterations) ? true : false; 01899 01900 return ret_val; 01901 }
igb_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure
Valid for only copper links. Read the PHY status register (sticky read) to verify that link is up. Read the PHY special control register to determine the polarity and 10base-T extended distance. Read the PHY special status register to determine MDI/MDIx and current speed. If speed is 1000, then determine cable length, local and remote receiver.
Definition at line 2032 of file igb_phy.c.
References e1000_phy_info::cable_length, DEBUGFUNC, DEBUGOUT, e1000_1000t_rx_status_not_ok, e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined, E1000_CABLE_LENGTH_UNDEFINED, E1000_ERR_CONFIG, e1000_media_type_copper, igb_check_polarity_m88(), igb_phy_has_link_generic(), e1000_phy_info::is_mdix, e1000_phy_info::local_rx, M88E1000_PHY_SPEC_CTRL, M88E1000_PHY_SPEC_STATUS, M88E1000_PSCR_POLARITY_REVERSAL, M88E1000_PSSR_1000MBS, M88E1000_PSSR_MDIX, M88E1000_PSSR_SPEED, e1000_phy_info::media_type, e1000_phy_info::ops, e1000_hw::phy, PHY_1000T_STATUS, e1000_phy_info::polarity_correction, e1000_phy_operations::read_reg, e1000_phy_info::remote_rx, SR_1000T_LOCAL_RX_STATUS, SR_1000T_REMOTE_RX_STATUS, and u16.
Referenced by igb_init_phy_params_82575().
02033 { 02034 struct e1000_phy_info *phy = &hw->phy; 02035 s32 ret_val; 02036 u16 phy_data; 02037 bool link; 02038 02039 DEBUGFUNC("igb_get_phy_info_m88"); 02040 02041 if (phy->media_type != e1000_media_type_copper) { 02042 DEBUGOUT("Phy info is only valid for copper media\n"); 02043 ret_val = -E1000_ERR_CONFIG; 02044 goto out; 02045 } 02046 02047 ret_val = igb_phy_has_link_generic(hw, 1, 0, &link); 02048 if (ret_val) 02049 goto out; 02050 02051 if (!link) { 02052 DEBUGOUT("Phy info is only valid if link is up\n"); 02053 ret_val = -E1000_ERR_CONFIG; 02054 goto out; 02055 } 02056 02057 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 02058 if (ret_val) 02059 goto out; 02060 02061 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 02062 ? true : false; 02063 02064 ret_val = igb_check_polarity_m88(hw); 02065 if (ret_val) 02066 goto out; 02067 02068 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 02069 if (ret_val) 02070 goto out; 02071 02072 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 02073 02074 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 02075 #if 0 02076 ret_val = hw->phy.ops.get_cable_length(hw); 02077 #endif 02078 ret_val = -E1000_ERR_CONFIG; 02079 if (ret_val) 02080 goto out; 02081 #if 0 02082 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 02083 if (ret_val) 02084 goto out; 02085 02086 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 02087 ? e1000_1000t_rx_status_ok 02088 : e1000_1000t_rx_status_not_ok; 02089 02090 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 02091 ? e1000_1000t_rx_status_ok 02092 : e1000_1000t_rx_status_not_ok; 02093 #endif 02094 } else { 02095 /* Set values to "undefined" */ 02096 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 02097 phy->local_rx = e1000_1000t_rx_status_undefined; 02098 phy->remote_rx = e1000_1000t_rx_status_undefined; 02099 } 02100 02101 out: 02102 return ret_val; 02103 }
igb_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure
Read PHY status to determine if link is up. If link is up, then set/determine 10base-T extended distance and polarity correction. Read PHY port status to determine MDI/MDIx and speed. Based on the speed, determine on the cable length, local and remote receiver.
Definition at line 2114 of file igb_phy.c.
References e1000_phy_info::cable_length, DEBUGFUNC, DEBUGOUT, e1000_1000t_rx_status_not_ok, e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined, E1000_CABLE_LENGTH_UNDEFINED, E1000_ERR_CONFIG, igb_check_polarity_igp(), igb_phy_has_link_generic(), IGP01E1000_PHY_PORT_STATUS, IGP01E1000_PSSR_MDIX, IGP01E1000_PSSR_SPEED_1000MBPS, IGP01E1000_PSSR_SPEED_MASK, e1000_phy_info::is_mdix, e1000_phy_info::local_rx, e1000_phy_info::ops, e1000_hw::phy, PHY_1000T_STATUS, e1000_phy_info::polarity_correction, e1000_phy_operations::read_reg, e1000_phy_info::remote_rx, SR_1000T_LOCAL_RX_STATUS, SR_1000T_REMOTE_RX_STATUS, and u16.
Referenced by igb_init_phy_params_82575().
02115 { 02116 struct e1000_phy_info *phy = &hw->phy; 02117 s32 ret_val; 02118 u16 data; 02119 bool link; 02120 02121 DEBUGFUNC("igb_get_phy_info_igp"); 02122 02123 ret_val = igb_phy_has_link_generic(hw, 1, 0, &link); 02124 if (ret_val) 02125 goto out; 02126 02127 if (!link) { 02128 DEBUGOUT("Phy info is only valid if link is up\n"); 02129 ret_val = -E1000_ERR_CONFIG; 02130 goto out; 02131 } 02132 02133 phy->polarity_correction = true; 02134 02135 ret_val = igb_check_polarity_igp(hw); 02136 if (ret_val) 02137 goto out; 02138 02139 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 02140 if (ret_val) 02141 goto out; 02142 02143 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 02144 02145 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 02146 IGP01E1000_PSSR_SPEED_1000MBPS) { 02147 #if 0 02148 ret_val = phy->ops.get_cable_length(hw); 02149 #endif 02150 ret_val = -E1000_ERR_CONFIG; 02151 if (ret_val) 02152 goto out; 02153 #if 0 02154 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 02155 if (ret_val) 02156 goto out; 02157 02158 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 02159 ? e1000_1000t_rx_status_ok 02160 : e1000_1000t_rx_status_not_ok; 02161 02162 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 02163 ? e1000_1000t_rx_status_ok 02164 : e1000_1000t_rx_status_not_ok; 02165 #endif 02166 } else { 02167 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 02168 phy->local_rx = e1000_1000t_rx_status_undefined; 02169 phy->remote_rx = e1000_1000t_rx_status_undefined; 02170 } 02171 02172 out: 02173 return ret_val; 02174 }
igb_phy_sw_reset_generic - PHY software reset : pointer to the HW structure
Does a software reset of the PHY by reading the PHY control register and setting/write the control register reset bit to the PHY.
Definition at line 2183 of file igb_phy.c.
References DEBUGFUNC, E1000_SUCCESS, MII_CR_RESET, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, usec_delay, and e1000_phy_operations::write_reg.
Referenced by igb_init_phy_params_82575().
02184 { 02185 s32 ret_val = E1000_SUCCESS; 02186 u16 phy_ctrl; 02187 02188 DEBUGFUNC("igb_phy_sw_reset_generic"); 02189 02190 if (!(hw->phy.ops.read_reg)) 02191 goto out; 02192 02193 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 02194 if (ret_val) 02195 goto out; 02196 02197 phy_ctrl |= MII_CR_RESET; 02198 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 02199 if (ret_val) 02200 goto out; 02201 02202 usec_delay(1); 02203 02204 out: 02205 return ret_val; 02206 }
igb_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure
Verify the reset block is not blocking us from resetting. Acquire semaphore (if necessary) and read/set/write the device control reset bit in the PHY. Wait the appropriate delay time for the device to reset and release the semaphore (if necessary).
Definition at line 2217 of file igb_phy.c.
References e1000_phy_operations::acquire, e1000_phy_operations::check_reset_block, DEBUGFUNC, E1000_CTRL, E1000_CTRL_PHY_RST, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_FLUSH, E1000_WRITE_REG, e1000_phy_operations::get_cfg_done, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, e1000_phy_info::reset_delay_us, u32, and usec_delay.
Referenced by igb_init_phy_params_82575().
02218 { 02219 struct e1000_phy_info *phy = &hw->phy; 02220 s32 ret_val = E1000_SUCCESS; 02221 u32 ctrl; 02222 02223 DEBUGFUNC("igb_phy_hw_reset_generic"); 02224 02225 ret_val = phy->ops.check_reset_block(hw); 02226 if (ret_val) { 02227 ret_val = E1000_SUCCESS; 02228 goto out; 02229 } 02230 02231 ret_val = phy->ops.acquire(hw); 02232 if (ret_val) 02233 goto out; 02234 02235 ctrl = E1000_READ_REG(hw, E1000_CTRL); 02236 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 02237 E1000_WRITE_FLUSH(hw); 02238 02239 usec_delay(phy->reset_delay_us); 02240 02241 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 02242 E1000_WRITE_FLUSH(hw); 02243 02244 usec_delay(150); 02245 02246 phy->ops.release(hw); 02247 02248 ret_val = phy->ops.get_cfg_done(hw); 02249 02250 out: 02251 return ret_val; 02252 }
igb_get_cfg_done_generic - Generic configuration done : pointer to the HW structure
Generic function to wait 10 milli-seconds for configuration to complete and return success.
Definition at line 2261 of file igb_phy.c.
References DEBUGFUNC, E1000_SUCCESS, and msec_delay_irq.
02262 { 02263 DEBUGFUNC("igb_get_cfg_done_generic"); 02264 02265 msec_delay_irq(10); 02266 02267 return E1000_SUCCESS; 02268 }
igb_phy_init_script_igp3 - Inits the IGP3 PHY : pointer to the HW structure
Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
Definition at line 2276 of file igb_phy.c.
References DEBUGOUT, E1000_SUCCESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::write_reg.
Referenced by igb_get_cfg_done_82575().
02277 { 02278 DEBUGOUT("Running IGP 3 PHY init script\n"); 02279 02280 /* PHY init IGP 3 */ 02281 /* Enable rise/fall, 10-mode work in class-A */ 02282 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 02283 /* Remove all caps from Replica path filter */ 02284 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 02285 /* Bias trimming for ADC, AFE and Driver (Default) */ 02286 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 02287 /* Increase Hybrid poly bias */ 02288 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 02289 /* Add 4% to Tx amplitude in Gig mode */ 02290 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 02291 /* Disable trimming (TTT) */ 02292 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 02293 /* Poly DC correction to 94.6% + 2% for all channels */ 02294 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 02295 /* ABS DC correction to 95.9% */ 02296 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 02297 /* BG temp curve trim */ 02298 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 02299 /* Increasing ADC OPAMP stage 1 currents to max */ 02300 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 02301 /* Force 1000 ( required for enabling PHY regs configuration) */ 02302 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 02303 /* Set upd_freq to 6 */ 02304 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 02305 /* Disable NPDFE */ 02306 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 02307 /* Disable adaptive fixed FFE (Default) */ 02308 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 02309 /* Enable FFE hysteresis */ 02310 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 02311 /* Fixed FFE for short cable lengths */ 02312 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 02313 /* Fixed FFE for medium cable lengths */ 02314 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 02315 /* Fixed FFE for long cable lengths */ 02316 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 02317 /* Enable Adaptive Clip Threshold */ 02318 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 02319 /* AHT reset limit to 1 */ 02320 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 02321 /* Set AHT master delay to 127 msec */ 02322 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 02323 /* Set scan bits for AHT */ 02324 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 02325 /* Set AHT Preset bits */ 02326 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 02327 /* Change integ_factor of channel A to 3 */ 02328 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 02329 /* Change prop_factor of channels BCD to 8 */ 02330 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 02331 /* Change cg_icount + enable integbp for channels BCD */ 02332 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 02333 /* 02334 * Change cg_icount + enable integbp + change prop_factor_master 02335 * to 8 for channel A 02336 */ 02337 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 02338 /* Disable AHT in Slave mode on channel A */ 02339 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 02340 /* 02341 * Enable LPLU and disable AN to 1000 in non-D0a states, 02342 * Enable SPD+B2B 02343 */ 02344 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 02345 /* Enable restart AN on an1000_dis change */ 02346 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 02347 /* Enable wh_fifo read clock in 10/100 modes */ 02348 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 02349 /* Restart AN, Speed selection is 1000 */ 02350 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 02351 02352 return E1000_SUCCESS; 02353 }
| enum e1000_phy_type igb_get_phy_type_from_id | ( | u32 | phy_id | ) |
igb_get_phy_type_from_id - Get PHY type from id : phy_id read from the phy
Returns the phy type from the id.
Definition at line 2361 of file igb_phy.c.
References e1000_phy_gg82563, e1000_phy_ife, e1000_phy_igp_2, e1000_phy_igp_3, e1000_phy_m88, e1000_phy_unknown, GG82563_E_PHY_ID, IFE_C_E_PHY_ID, IFE_E_PHY_ID, IFE_PLUS_E_PHY_ID, IGP01E1000_I_PHY_ID, IGP03E1000_E_PHY_ID, M88E1000_E_PHY_ID, M88E1000_I_PHY_ID, M88E1011_I_PHY_ID, and M88E1111_I_PHY_ID.
Referenced by igb_determine_phy_address().
02362 { 02363 enum e1000_phy_type phy_type = e1000_phy_unknown; 02364 02365 switch (phy_id) { 02366 case M88E1000_I_PHY_ID: 02367 case M88E1000_E_PHY_ID: 02368 case M88E1111_I_PHY_ID: 02369 case M88E1011_I_PHY_ID: 02370 phy_type = e1000_phy_m88; 02371 break; 02372 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 02373 phy_type = e1000_phy_igp_2; 02374 break; 02375 case GG82563_E_PHY_ID: 02376 phy_type = e1000_phy_gg82563; 02377 break; 02378 case IGP03E1000_E_PHY_ID: 02379 phy_type = e1000_phy_igp_3; 02380 break; 02381 case IFE_E_PHY_ID: 02382 case IFE_PLUS_E_PHY_ID: 02383 case IFE_C_E_PHY_ID: 02384 phy_type = e1000_phy_ife; 02385 break; 02386 default: 02387 phy_type = e1000_phy_unknown; 02388 break; 02389 } 02390 return phy_type; 02391 }
igb_determine_phy_address - Determines PHY address.
: pointer to the HW structure
This uses a trial and error method to loop through possible PHY addresses. It tests each by reading the PHY ID registers and checking for a match.
Definition at line 2401 of file igb_phy.c.
References e1000_phy_info::addr, E1000_ERR_PHY_TYPE, E1000_MAX_PHY_ADDR, e1000_phy_unknown, E1000_SUCCESS, e1000_phy_info::id, igb_get_phy_id(), igb_get_phy_type_from_id(), msec_delay, e1000_hw::phy, and u32.
02402 { 02403 s32 ret_val = -E1000_ERR_PHY_TYPE; 02404 u32 phy_addr = 0; 02405 u32 i; 02406 enum e1000_phy_type phy_type = e1000_phy_unknown; 02407 02408 hw->phy.id = phy_type; 02409 02410 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 02411 hw->phy.addr = phy_addr; 02412 i = 0; 02413 02414 do { 02415 igb_get_phy_id(hw); 02416 phy_type = igb_get_phy_type_from_id(hw->phy.id); 02417 02418 /* 02419 * If phy_type is valid, break - we found our 02420 * PHY address 02421 */ 02422 if (phy_type != e1000_phy_unknown) { 02423 ret_val = E1000_SUCCESS; 02424 goto out; 02425 } 02426 msec_delay(1); 02427 i++; 02428 } while (i < 10); 02429 } 02430 02431 out: 02432 return ret_val; 02433 }
| void igb_power_up_phy_copper | ( | struct e1000_hw * | hw | ) |
igb_power_up_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, restore the link to previous settings.
Definition at line 2443 of file igb_phy.c.
References MII_CR_POWER_DOWN, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, and e1000_phy_operations::write_reg.
Referenced by igb_init_phy_params_82575().
02444 { 02445 u16 mii_reg = 0; 02446 02447 /* The PHY will retain its settings across a power down/up cycle */ 02448 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 02449 mii_reg &= ~MII_CR_POWER_DOWN; 02450 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 02451 }
| void igb_power_down_phy_copper | ( | struct e1000_hw * | hw | ) |
igb_power_down_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, restore the link to previous settings.
Definition at line 2461 of file igb_phy.c.
References MII_CR_POWER_DOWN, msec_delay, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, and e1000_phy_operations::write_reg.
Referenced by igb_power_down_phy_copper_82575().
02462 { 02463 u16 mii_reg = 0; 02464 02465 /* The PHY will retain its settings across a power down/up cycle */ 02466 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 02467 mii_reg |= MII_CR_POWER_DOWN; 02468 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 02469 msec_delay(1); 02470 }
1.5.7.1