#include "igb.h"Go to the source code of this file.
Defines | |
| #define | PCI_CAP_ID_EXP 0x10 |
| #define | min(a, b) (((a)<(b))?(a):(b)) |
Functions | |
| FILE_LICENCE (GPL2_ONLY) | |
| int32_t | igb_read_pcie_cap_reg (struct e1000_hw *hw, uint32_t reg, uint16_t *value) |
| igb_read_pcie_cap_reg - retrieve PCIe capability register contents : address of board private structure : PCIe capability register requested : where to store requested value | |
| int32_t | igb_write_pcie_cap_reg (struct e1000_hw *hw, u32 reg, u16 *value) |
| igb_write_pcie_cap_reg - write value to PCIe capability register : address of board private structure : PCIe capability register to write to : value to store in given register | |
| static void | igb_irq_disable (struct igb_adapter *adapter) |
| igb_irq_disable - Mask off interrupt generation on the NIC : board private structure | |
| static void | igb_irq_enable (struct igb_adapter *adapter) |
| igb_irq_enable - Enable default interrupt generation settings : board private structure | |
| void | igb_get_hw_control (struct igb_adapter *adapter) |
| igb_get_hw_control - get control of the h/w from f/w : address of board private structure | |
| void | igb_reset (struct igb_adapter *adapter) |
| igb_reset - put adapter in known initial state : board private structure | |
| int | igb_sw_init (struct igb_adapter *adapter) |
| igb_sw_init - Initialize general software structures (struct igb_adapter) : board private structure to initialize | |
| static int | igb_setup_tx_resources (struct igb_adapter *adapter) |
| igb_setup_tx_resources - allocate Tx resources (Descriptors) | |
| static void | igb_process_tx_packets (struct net_device *netdev) |
| igb_process_tx_packets - process transmitted packets | |
| static void | igb_free_tx_resources (struct igb_adapter *adapter) |
| static void | igb_configure_tx (struct igb_adapter *adapter) |
| igb_configure_tx - Configure 8254x Transmit Unit after Reset : board private structure | |
| static void | igb_free_rx_resources (struct igb_adapter *adapter) |
| static int | igb_refill_rx_ring (struct igb_adapter *adapter) |
| igb_refill_rx_ring - allocate Rx io_buffers | |
| static int | igb_setup_rx_resources (struct igb_adapter *adapter) |
| igb_setup_rx_resources - allocate Rx resources (Descriptors) | |
| static void | igb_configure_rx (struct igb_adapter *adapter) |
| igb_configure_rx - Configure 8254x Receive Unit after Reset : board private structure | |
| static void | igb_process_rx_packets (struct net_device *netdev) |
| igb_process_rx_packets - process received packets | |
| static void | igb_close (struct net_device *netdev) |
| Functions that implement the gPXE driver API. | |
| static int | igb_transmit (struct net_device *netdev, struct io_buffer *iobuf) |
| igb_transmit - Transmit a packet | |
| static void | igb_poll (struct net_device *netdev) |
| igb_poll - Poll for received packets | |
| static void | igb_irq (struct net_device *netdev, int enable) |
| igb_irq - enable or Disable interrupts | |
| int | igb_probe (struct pci_device *pdev, const struct pci_device_id *ent __unused) |
| igb_probe - Initial configuration of NIC | |
| void | igb_remove (struct pci_device *pdev) |
| igb_remove - Device Removal Routine | |
| static int | igb_open (struct net_device *netdev) |
| igb_open - Called when a network interface is made active | |
Variables | |
| static struct net_device_operations | igb_operations |
| igb net device operations | |
| #define PCI_CAP_ID_EXP 0x10 |
| #define min | ( | a, | |||
| b | ) | (((a)<(b))?(a):(b)) |
| FILE_LICENCE | ( | GPL2_ONLY | ) |
igb_read_pcie_cap_reg - retrieve PCIe capability register contents : address of board private structure : PCIe capability register requested : where to store requested value
Definition at line 43 of file igb_main.c.
References e1000_hw::back, E1000_ERR_CONFIG, E1000_SUCCESS, PCI_CAP_ID_EXP, pci_find_capability(), pci_read_config_word(), and igb_adapter::pdev.
00044 { 00045 struct igb_adapter *adapter = hw->back; 00046 uint16_t cap_offset; 00047 00048 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 00049 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 00050 if (!cap_offset) 00051 return -E1000_ERR_CONFIG; 00052 00053 pci_read_config_word(adapter->pdev, cap_offset + reg, value); 00054 00055 return E1000_SUCCESS; 00056 }
igb_write_pcie_cap_reg - write value to PCIe capability register : address of board private structure : PCIe capability register to write to : value to store in given register
Definition at line 64 of file igb_main.c.
References e1000_hw::back, E1000_ERR_CONFIG, E1000_SUCCESS, PCI_CAP_ID_EXP, pci_find_capability(), pci_write_config_word(), igb_adapter::pdev, and u16.
Referenced by igb_set_pcie_completion_timeout().
00065 { 00066 struct igb_adapter *adapter = hw->back; 00067 u16 cap_offset; 00068 00069 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 00070 if (!cap_offset) 00071 return -E1000_ERR_CONFIG; 00072 00073 pci_write_config_word(adapter->pdev, cap_offset + reg, *value); 00074 00075 return E1000_SUCCESS; 00076 }
| static void igb_irq_disable | ( | struct igb_adapter * | adapter | ) | [static] |
igb_irq_disable - Mask off interrupt generation on the NIC : board private structure
Definition at line 82 of file igb_main.c.
References E1000_IAM, E1000_IMC, E1000_WRITE_FLUSH, E1000_WRITE_REG, and igb_adapter::hw.
Referenced by igb_close(), igb_irq(), and igb_sw_init().
00083 { 00084 struct e1000_hw *hw = &adapter->hw; 00085 00086 E1000_WRITE_REG(hw, E1000_IAM, 0); 00087 E1000_WRITE_REG(hw, E1000_IMC, ~0); 00088 E1000_WRITE_FLUSH(hw); 00089 }
| static void igb_irq_enable | ( | struct igb_adapter * | adapter | ) | [static] |
igb_irq_enable - Enable default interrupt generation settings : board private structure
Definition at line 95 of file igb_main.c.
References E1000_IAM, E1000_IMS, E1000_WRITE_FLUSH, E1000_WRITE_REG, igb_adapter::hw, and IMS_ENABLE_MASK.
Referenced by igb_irq().
00096 { 00097 struct e1000_hw *hw = &adapter->hw; 00098 00099 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 00100 E1000_WRITE_REG(hw, E1000_IAM, IMS_ENABLE_MASK); 00101 E1000_WRITE_FLUSH(hw); 00102 }
| void igb_get_hw_control | ( | struct igb_adapter * | adapter | ) |
igb_get_hw_control - get control of the h/w from f/w : address of board private structure
igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. For ASF and Pass Through versions of f/w this means that the driver is loaded.
Definition at line 113 of file igb_main.c.
References E1000_CTRL_EXT, E1000_CTRL_EXT_DRV_LOAD, E1000_READ_REG, E1000_WRITE_REG, igb_adapter::hw, and u32.
Referenced by igb_probe().
00114 { 00115 struct e1000_hw *hw = &adapter->hw; 00116 u32 ctrl_ext; 00117 00118 /* Let firmware know the driver has taken over */ 00119 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 00120 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 00121 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 00122 }
| void igb_reset | ( | struct igb_adapter * | adapter | ) |
igb_reset - put adapter in known initial state : board private structure
Definition at line 128 of file igb_main.c.
References e1000_fc_info::current_mode, DBG, e1000_82575, e1000_82576, E1000_PBA_34K, E1000_READ_REG, E1000_RXPBS, E1000_RXPBS_SIZE_MASK_82576, E1000_WRITE_REG, E1000_WUC, e1000_hw::fc, e1000_fc_info::high_water, igb_adapter::hw, igb_get_phy_info(), igb_init_hw(), igb_reset_hw(), e1000_fc_info::low_water, e1000_hw::mac, igb_adapter::max_frame_size, min, e1000_fc_info::pause_time, e1000_fc_info::requested_mode, e1000_fc_info::send_xon, e1000_mac_info::type, u16, and u32.
Referenced by igb_close(), igb_open(), igb_probe(), and igb_remove().
00129 { 00130 struct e1000_hw *hw = &adapter->hw; 00131 00132 struct e1000_mac_info *mac = &hw->mac; 00133 struct e1000_fc_info *fc = &hw->fc; 00134 u32 pba = 0; 00135 u16 hwm; 00136 00137 /* Repartition Pba for greater than 9k mtu 00138 * To take effect CTRL.RST is required. 00139 */ 00140 switch (mac->type) { 00141 case e1000_82576: 00142 pba = E1000_READ_REG(hw, E1000_RXPBS); 00143 pba &= E1000_RXPBS_SIZE_MASK_82576; 00144 break; 00145 case e1000_82575: 00146 default: 00147 pba = E1000_PBA_34K; 00148 break; 00149 } 00150 00151 /* flow control settings */ 00152 /* The high water mark must be low enough to fit one full frame 00153 * (or the size used for early receive) above it in the Rx FIFO. 00154 * Set it to the lower of: 00155 * - 90% of the Rx FIFO size, or 00156 * - the full Rx FIFO size minus one full frame */ 00157 #define min(a,b) (((a)<(b))?(a):(b)) 00158 hwm = min(((pba << 10) * 9 / 10), 00159 ((pba << 10) - 2 * adapter->max_frame_size)); 00160 00161 if (mac->type < e1000_82576) { 00162 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */ 00163 fc->low_water = fc->high_water - 8; 00164 } else { 00165 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ 00166 fc->low_water = fc->high_water - 16; 00167 } 00168 fc->pause_time = 0xFFFF; 00169 fc->send_xon = 1; 00170 fc->current_mode = fc->requested_mode; 00171 00172 /* Allow time for pending master requests to run */ 00173 igb_reset_hw(hw); 00174 E1000_WRITE_REG(hw, E1000_WUC, 0); 00175 00176 if (igb_init_hw(hw)) { 00177 DBG ("Hardware Error\n"); 00178 } 00179 00180 igb_get_phy_info(hw); 00181 }
| int igb_sw_init | ( | struct igb_adapter * | adapter | ) |
igb_sw_init - Initialize general software structures (struct igb_adapter) : board private structure to initialize
Definition at line 187 of file igb_main.c.
References e1000_hw::bus, DBG, pci_device::device, e1000_hw::device_id, EIO, ETH_FCS_LEN, ETH_HLEN, ETH_ZLEN, igb_adapter::hw, igb_irq_disable(), igb_setup_init_funcs(), igb_adapter::max_frame_size, MAXIMUM_ETHERNET_VLAN_SIZE, igb_adapter::min_frame_size, e1000_bus_info::pci_cmd_word, PCI_COMMAND, pci_read_config_byte(), pci_read_config_word(), PCI_REVISION_ID, igb_adapter::pdev, e1000_hw::revision_id, TRUE, pci_device::vendor, and e1000_hw::vendor_id.
Referenced by igb_probe().
00188 { 00189 struct e1000_hw *hw = &adapter->hw; 00190 struct pci_device *pdev = adapter->pdev; 00191 00192 /* PCI config space info */ 00193 00194 hw->vendor_id = pdev->vendor; 00195 hw->device_id = pdev->device; 00196 00197 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); 00198 00199 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 00200 00201 adapter->max_frame_size = MAXIMUM_ETHERNET_VLAN_SIZE + ETH_HLEN + ETH_FCS_LEN; 00202 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 00203 00204 /* Initialize the hardware-specific values */ 00205 if (igb_setup_init_funcs(hw, TRUE)) { 00206 DBG ("Hardware Initialization Failure\n"); 00207 return -EIO; 00208 } 00209 00210 /* Explicitly disable IRQ since the NIC can be in any state. */ 00211 igb_irq_disable(adapter); 00212 00213 return 0; 00214 }
| static int igb_setup_tx_resources | ( | struct igb_adapter * | adapter | ) | [static] |
igb_setup_tx_resources - allocate Tx resources (Descriptors)
| adapter | e1000 private structure |
| rc | Returns 0 on success, negative on failure |
Definition at line 225 of file igb_main.c.
References DBG, ENOMEM, malloc_dma(), memset(), igb_adapter::tx_base, igb_adapter::tx_ring_size, and virt_to_bus().
Referenced by igb_open().
00226 { 00227 DBG ( "igb_setup_tx_resources\n" ); 00228 00229 /* Allocate transmit descriptor ring memory. 00230 It must not cross a 64K boundary because of hardware errata #23 00231 so we use malloc_dma() requesting a 128 byte block that is 00232 128 byte aligned. This should guarantee that the memory 00233 allocated will not cross a 64K boundary, because 128 is an 00234 even multiple of 65536 ( 65536 / 128 == 512 ), so all possible 00235 allocations of 128 bytes on a 128 byte boundary will not 00236 cross 64K bytes. 00237 */ 00238 00239 adapter->tx_base = 00240 malloc_dma ( adapter->tx_ring_size, adapter->tx_ring_size ); 00241 00242 if ( ! adapter->tx_base ) { 00243 return -ENOMEM; 00244 } 00245 00246 memset ( adapter->tx_base, 0, adapter->tx_ring_size ); 00247 00248 DBG ( "adapter->tx_base = %#08lx\n", virt_to_bus ( adapter->tx_base ) ); 00249 00250 return 0; 00251 }
| static void igb_process_tx_packets | ( | struct net_device * | netdev | ) | [static] |
igb_process_tx_packets - process transmitted packets
Definition at line 258 of file igb_main.c.
References e1000_tx_desc::data, DBG, E1000_TXD_STAT_DD, E1000_TXD_STAT_EC, E1000_TXD_STAT_LC, E1000_TXD_STAT_TU, EINVAL, memset(), netdev_priv(), netdev_tx_complete(), netdev_tx_complete_err(), NUM_TX_DESC, igb_adapter::tx_base, igb_adapter::tx_fill_ctr, igb_adapter::tx_head, igb_adapter::tx_iobuf, igb_adapter::tx_tail, e1000_tx_desc::upper, and virt_to_bus().
Referenced by igb_poll().
00259 { 00260 struct igb_adapter *adapter = netdev_priv ( netdev ); 00261 uint32_t i; 00262 uint32_t tx_status; 00263 struct e1000_tx_desc *tx_curr_desc; 00264 00265 /* Check status of transmitted packets 00266 */ 00267 DBG ( "process_tx_packets: tx_head = %d, tx_tail = %d\n", adapter->tx_head, 00268 adapter->tx_tail ); 00269 00270 while ( ( i = adapter->tx_head ) != adapter->tx_tail ) { 00271 00272 tx_curr_desc = ( void * ) ( adapter->tx_base ) + 00273 ( i * sizeof ( *adapter->tx_base ) ); 00274 00275 tx_status = tx_curr_desc->upper.data; 00276 00277 DBG ( " tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) ); 00278 DBG ( " tx_status = %#08x\n", tx_status ); 00279 00280 /* if the packet at tx_head is not owned by hardware it is for us */ 00281 if ( ! ( tx_status & E1000_TXD_STAT_DD ) ) 00282 break; 00283 00284 DBG ( "Sent packet. tx_head: %d tx_tail: %d tx_status: %#08x\n", 00285 adapter->tx_head, adapter->tx_tail, tx_status ); 00286 00287 if ( tx_status & ( E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | 00288 E1000_TXD_STAT_TU ) ) { 00289 netdev_tx_complete_err ( netdev, adapter->tx_iobuf[i], -EINVAL ); 00290 DBG ( "Error transmitting packet, tx_status: %#08x\n", 00291 tx_status ); 00292 } else { 00293 netdev_tx_complete ( netdev, adapter->tx_iobuf[i] ); 00294 DBG ( "Success transmitting packet, tx_status: %#08x\n", 00295 tx_status ); 00296 } 00297 00298 /* Decrement count of used descriptors, clear this descriptor 00299 */ 00300 adapter->tx_fill_ctr--; 00301 memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) ); 00302 00303 adapter->tx_head = ( adapter->tx_head + 1 ) % NUM_TX_DESC; 00304 } 00305 }
| static void igb_free_tx_resources | ( | struct igb_adapter * | adapter | ) | [static] |
Definition at line 307 of file igb_main.c.
References DBG, free_dma(), igb_adapter::tx_base, and igb_adapter::tx_ring_size.
Referenced by igb_close(), and igb_open().
00308 { 00309 DBG ( "igb_free_tx_resources\n" ); 00310 00311 free_dma ( adapter->tx_base, adapter->tx_ring_size ); 00312 }
| static void igb_configure_tx | ( | struct igb_adapter * | adapter | ) | [static] |
igb_configure_tx - Configure 8254x Transmit Unit after Reset : board private structure
Configure the Tx unit of the MAC after a reset.
Definition at line 320 of file igb_main.c.
References DBG, E1000_COLLISION_THRESHOLD, E1000_CT_SHIFT, E1000_READ_REG, E1000_TCTL, E1000_TCTL_CT, E1000_TCTL_EN, E1000_TCTL_PSP, E1000_TCTL_RTLC, E1000_TDBAH, E1000_TDBAL, E1000_TDH, E1000_TDLEN, E1000_TDT, E1000_TXD_CMD_EOP, E1000_TXD_CMD_IFCS, E1000_TXD_CMD_RS, E1000_TXDCTL, E1000_TXDCTL_QUEUE_ENABLE, E1000_WRITE_FLUSH, E1000_WRITE_REG, igb_adapter::hw, igb_config_collision_dist(), mdelay(), igb_adapter::tx_base, igb_adapter::tx_fill_ctr, igb_adapter::tx_head, igb_adapter::tx_ring_size, igb_adapter::tx_tail, igb_adapter::txd_cmd, u32, and virt_to_bus().
Referenced by igb_open().
00321 { 00322 struct e1000_hw *hw = &adapter->hw; 00323 u32 tctl, txdctl; 00324 00325 DBG ( "igb_configure_tx\n" ); 00326 00327 /* disable transmits while setting up the descriptors */ 00328 tctl = E1000_READ_REG ( hw, E1000_TCTL ); 00329 E1000_WRITE_REG ( hw, E1000_TCTL, tctl & ~E1000_TCTL_EN ); 00330 E1000_WRITE_FLUSH(hw); 00331 mdelay(10); 00332 00333 E1000_WRITE_REG ( hw, E1000_TDBAH(0), 0 ); 00334 E1000_WRITE_REG ( hw, E1000_TDBAL(0), virt_to_bus ( adapter->tx_base ) ); 00335 E1000_WRITE_REG ( hw, E1000_TDLEN(0), adapter->tx_ring_size ); 00336 00337 DBG ( "E1000_TDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_TDBAL(0) ) ); 00338 DBG ( "E1000_TDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_TDLEN(0) ) ); 00339 00340 /* Setup the HW Tx Head and Tail descriptor pointers */ 00341 E1000_WRITE_REG ( hw, E1000_TDH(0), 0 ); 00342 E1000_WRITE_REG ( hw, E1000_TDT(0), 0 ); 00343 00344 adapter->tx_head = 0; 00345 adapter->tx_tail = 0; 00346 adapter->tx_fill_ctr = 0; 00347 00348 txdctl = E1000_READ_REG ( hw, E1000_TXDCTL(0) ); 00349 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 00350 E1000_WRITE_REG ( hw, E1000_TXDCTL(0), txdctl ); 00351 00352 /* Setup Transmit Descriptor Settings for eop descriptor */ 00353 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; 00354 00355 /* enable Report Status bit */ 00356 adapter->txd_cmd |= E1000_TXD_CMD_RS; 00357 00358 /* Program the Transmit Control Register */ 00359 tctl &= ~E1000_TCTL_CT; 00360 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 00361 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 00362 00363 igb_config_collision_dist(hw); 00364 00365 /* Enable transmits */ 00366 tctl |= E1000_TCTL_EN; 00367 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 00368 E1000_WRITE_FLUSH(hw); 00369 }
| static void igb_free_rx_resources | ( | struct igb_adapter * | adapter | ) | [static] |
Definition at line 373 of file igb_main.c.
References DBG, free_dma(), free_iob(), NUM_RX_DESC, igb_adapter::rx_base, igb_adapter::rx_iobuf, and igb_adapter::rx_ring_size.
Referenced by igb_close(), and igb_setup_rx_resources().
00374 { 00375 int i; 00376 00377 DBG ( "igb_free_rx_resources\n" ); 00378 00379 free_dma ( adapter->rx_base, adapter->rx_ring_size ); 00380 00381 for ( i = 0; i < NUM_RX_DESC; i++ ) { 00382 free_iob ( adapter->rx_iobuf[i] ); 00383 } 00384 }
| static int igb_refill_rx_ring | ( | struct igb_adapter * | adapter | ) | [static] |
igb_refill_rx_ring - allocate Rx io_buffers
| adapter | e1000 private structure |
| rc | Returns 0 on success, negative on failure |
Definition at line 393 of file igb_main.c.
References alloc_iob(), e1000_rx_desc::buffer_addr, io_buffer::data, DBG, DBG2, DBGP, E1000_RDT, E1000_RXD_STAT_DD, E1000_WRITE_REG, ENOMEM, igb_adapter::hw, MAXIMUM_ETHERNET_VLAN_SIZE, NULL, NUM_RX_DESC, igb_adapter::rx_base, igb_adapter::rx_curr, igb_adapter::rx_iobuf, e1000_rx_desc::status, and virt_to_bus().
Referenced by igb_poll(), and igb_setup_rx_resources().
00394 { 00395 int i, rx_curr; 00396 int rc = 0; 00397 struct e1000_rx_desc *rx_curr_desc; 00398 struct e1000_hw *hw = &adapter->hw; 00399 struct io_buffer *iob; 00400 00401 DBGP ("igb_refill_rx_ring\n"); 00402 00403 for ( i = 0; i < NUM_RX_DESC; i++ ) { 00404 rx_curr = ( ( adapter->rx_curr + i ) % NUM_RX_DESC ); 00405 rx_curr_desc = adapter->rx_base + rx_curr; 00406 00407 if ( rx_curr_desc->status & E1000_RXD_STAT_DD ) 00408 continue; 00409 00410 if ( adapter->rx_iobuf[rx_curr] != NULL ) 00411 continue; 00412 00413 DBG2 ( "Refilling rx desc %d\n", rx_curr ); 00414 00415 iob = alloc_iob ( MAXIMUM_ETHERNET_VLAN_SIZE ); 00416 adapter->rx_iobuf[rx_curr] = iob; 00417 00418 if ( ! iob ) { 00419 DBG ( "alloc_iob failed\n" ); 00420 rc = -ENOMEM; 00421 break; 00422 } else { 00423 rx_curr_desc->buffer_addr = virt_to_bus ( iob->data ); 00424 00425 E1000_WRITE_REG ( hw, E1000_RDT(0), rx_curr ); 00426 } 00427 } 00428 return rc; 00429 }
| static int igb_setup_rx_resources | ( | struct igb_adapter * | adapter | ) | [static] |
igb_setup_rx_resources - allocate Rx resources (Descriptors)
| adapter | e1000 private structure |
| rc | Returns 0 on success, negative on failure |
Definition at line 438 of file igb_main.c.
References DBGP, ENOMEM, igb_free_rx_resources(), igb_refill_rx_ring(), malloc_dma(), memset(), NULL, NUM_RX_DESC, igb_adapter::rx_base, igb_adapter::rx_iobuf, and igb_adapter::rx_ring_size.
Referenced by igb_open().
00439 { 00440 int i, rc = 0; 00441 00442 DBGP ( "igb_setup_rx_resources\n" ); 00443 00444 /* Allocate receive descriptor ring memory. 00445 It must not cross a 64K boundary because of hardware errata 00446 */ 00447 00448 adapter->rx_base = 00449 malloc_dma ( adapter->rx_ring_size, adapter->rx_ring_size ); 00450 00451 if ( ! adapter->rx_base ) { 00452 return -ENOMEM; 00453 } 00454 memset ( adapter->rx_base, 0, adapter->rx_ring_size ); 00455 00456 for ( i = 0; i < NUM_RX_DESC; i++ ) { 00457 /* let igb_refill_rx_ring() io_buffer allocations */ 00458 adapter->rx_iobuf[i] = NULL; 00459 } 00460 00461 /* allocate io_buffers */ 00462 rc = igb_refill_rx_ring ( adapter ); 00463 if ( rc < 0 ) 00464 igb_free_rx_resources ( adapter ); 00465 00466 return rc; 00467 }
| static void igb_configure_rx | ( | struct igb_adapter * | adapter | ) | [static] |
igb_configure_rx - Configure 8254x Receive Unit after Reset : board private structure
Configure the Rx unit of the MAC after a reset.
Definition at line 475 of file igb_main.c.
References DBG, DBGP, E1000_MRQC, E1000_MRQC_ENABLE_VMDQ, E1000_RCTL, E1000_RCTL_BAM, E1000_RCTL_EN, E1000_RCTL_LBM_MAC, E1000_RCTL_LBM_TCVR, E1000_RCTL_LPE, E1000_RCTL_MPE, E1000_RCTL_SBP, E1000_RCTL_SECRC, E1000_RCTL_SZ_2048, E1000_RCTL_UPE, E1000_RDBAH, E1000_RDBAL, E1000_RDH, E1000_RDLEN, E1000_RDT, E1000_READ_REG, E1000_RXCSUM, E1000_RXCSUM_IPPCSE, E1000_RXCSUM_TUOFL, E1000_RXDCTL, E1000_RXDCTL_QUEUE_ENABLE, E1000_WRITE_FLUSH, E1000_WRITE_REG, igb_adapter::hw, IGB_RX_HTHRESH, IGB_RX_PTHRESH, IGB_RX_WTHRESH, mdelay(), NUM_RX_DESC, igb_adapter::rx_base, igb_adapter::rx_curr, igb_adapter::rx_ring_size, and virt_to_bus().
Referenced by igb_open().
00476 { 00477 struct e1000_hw *hw = &adapter->hw; 00478 uint32_t rctl, rxdctl, rxcsum, mrqc; 00479 00480 DBGP ( "igb_configure_rx\n" ); 00481 00482 /* disable receives while setting up the descriptors */ 00483 rctl = E1000_READ_REG ( hw, E1000_RCTL ); 00484 E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN ); 00485 E1000_WRITE_FLUSH(hw); 00486 mdelay(10); 00487 00488 adapter->rx_curr = 0; 00489 00490 /* Setup the HW Rx Head and Tail Descriptor Pointers and 00491 * the Base and Length of the Rx Descriptor Ring */ 00492 00493 E1000_WRITE_REG ( hw, E1000_RDBAL(0), virt_to_bus ( adapter->rx_base ) ); 00494 E1000_WRITE_REG ( hw, E1000_RDBAH(0), 0 ); 00495 E1000_WRITE_REG ( hw, E1000_RDLEN(0), adapter->rx_ring_size ); 00496 00497 E1000_WRITE_REG ( hw, E1000_RDH(0), 0 ); 00498 E1000_WRITE_REG ( hw, E1000_RDT(0), 0 ); 00499 00500 DBG ( "E1000_RDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_RDBAL(0) ) ); 00501 DBG ( "E1000_RDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_RDLEN(0) ) ); 00502 DBG ( "E1000_RCTL: %#08x\n", E1000_READ_REG ( hw, E1000_RCTL ) ); 00503 00504 rxdctl = E1000_READ_REG ( hw, E1000_RXDCTL(0) ); 00505 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 00506 rxdctl &= 0xFFF00000; 00507 rxdctl |= IGB_RX_PTHRESH; 00508 rxdctl |= IGB_RX_HTHRESH << 8; 00509 rxdctl |= IGB_RX_WTHRESH << 16; 00510 E1000_WRITE_REG ( hw, E1000_RXDCTL(0), rxdctl ); 00511 E1000_WRITE_FLUSH ( hw ); 00512 00513 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 00514 rxcsum &= ~( E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE ); 00515 E1000_WRITE_REG ( hw, E1000_RXCSUM, 0 ); 00516 00517 /* The initial value for MRQC disables multiple receive 00518 * queues, however this setting is not recommended. 00519 * - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41 00520 * Section 8.10.9 Multiple Queues Command Register - MRQC 00521 */ 00522 mrqc = E1000_MRQC_ENABLE_VMDQ; 00523 E1000_WRITE_REG ( hw, E1000_MRQC, mrqc ); 00524 00525 /* Turn off loopback modes */ 00526 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 00527 00528 /* set maximum packet size */ 00529 rctl |= E1000_RCTL_SZ_2048; 00530 00531 /* Broadcast enable, multicast promisc, unicast promisc */ 00532 rctl |= E1000_RCTL_BAM | E1000_RCTL_MPE | E1000_RCTL_UPE; 00533 00534 /* Store bad packets */ 00535 rctl |= E1000_RCTL_SBP; 00536 00537 /* enable LPE to prevent packets larger than max_frame_size */ 00538 rctl |= E1000_RCTL_LPE; 00539 00540 /* enable stripping of CRC. */ 00541 rctl |= E1000_RCTL_SECRC; 00542 00543 /* enable receive control register */ 00544 rctl |= E1000_RCTL_EN; 00545 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 00546 E1000_WRITE_FLUSH(hw); 00547 00548 /* On the 82576, RDT([0]) must not be "bumped" before 00549 * the enable bit of RXDCTL([0]) is set. 00550 * - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41 00551 * Section 4.5.9 receive Initialization 00552 * 00553 * By observation I have found this to occur when the enable bit of 00554 * RCTL is set. The datasheet recommends polling for this bit, 00555 * however as I see no evidence of this in the Linux igb driver 00556 * I have omitted that step. 00557 * - Simon Horman, May 2009 00558 */ 00559 E1000_WRITE_REG ( hw, E1000_RDT(0), NUM_RX_DESC - 1 ); 00560 00561 DBG ( "RDBAH: %#08x\n", E1000_READ_REG ( hw, E1000_RDBAH(0) ) ); 00562 DBG ( "RDBAL: %#08x\n", E1000_READ_REG ( hw, E1000_RDBAL(0) ) ); 00563 DBG ( "RDLEN: %d\n", E1000_READ_REG ( hw, E1000_RDLEN(0) ) ); 00564 DBG ( "RCTL: %#08x\n", E1000_READ_REG ( hw, E1000_RCTL ) ); 00565 }
| static void igb_process_rx_packets | ( | struct net_device * | netdev | ) | [static] |
igb_process_rx_packets - process received packets
Definition at line 572 of file igb_main.c.
References DBG, DBG2, DBGP, E1000_RCTL, E1000_READ_REG, E1000_RXD_ERR_FRAME_ERR_MASK, E1000_RXD_STAT_DD, EINVAL, e1000_rx_desc::errors, igb_adapter::hw, iob_put, e1000_rx_desc::length, memset(), netdev_priv(), netdev_rx(), netdev_rx_err(), NULL, NUM_RX_DESC, igb_adapter::rx_base, igb_adapter::rx_curr, igb_adapter::rx_iobuf, and e1000_rx_desc::status.
Referenced by igb_poll().
00573 { 00574 struct igb_adapter *adapter = netdev_priv ( netdev ); 00575 uint32_t i; 00576 uint32_t rx_status; 00577 uint32_t rx_len; 00578 uint32_t rx_err; 00579 struct e1000_rx_desc *rx_curr_desc; 00580 00581 DBGP ( "igb_process_rx_packets\n" ); 00582 00583 /* Process received packets 00584 */ 00585 while ( 1 ) { 00586 00587 i = adapter->rx_curr; 00588 00589 rx_curr_desc = ( void * ) ( adapter->rx_base ) + 00590 ( i * sizeof ( *adapter->rx_base ) ); 00591 rx_status = rx_curr_desc->status; 00592 00593 DBG2 ( "Before DD Check RX_status: %#08x\n", rx_status ); 00594 00595 if ( ! ( rx_status & E1000_RXD_STAT_DD ) ) 00596 break; 00597 00598 if ( adapter->rx_iobuf[i] == NULL ) 00599 break; 00600 00601 DBG ( "E1000_RCTL = %#08x\n", E1000_READ_REG ( &adapter->hw, E1000_RCTL ) ); 00602 00603 rx_len = rx_curr_desc->length; 00604 00605 DBG ( "Received packet, rx_curr: %d rx_status: %#08x rx_len: %d\n", 00606 i, rx_status, rx_len ); 00607 00608 rx_err = rx_curr_desc->errors; 00609 00610 iob_put ( adapter->rx_iobuf[i], rx_len ); 00611 00612 if ( rx_err & E1000_RXD_ERR_FRAME_ERR_MASK ) { 00613 00614 netdev_rx_err ( netdev, adapter->rx_iobuf[i], -EINVAL ); 00615 DBG ( "igb_process_rx_packets: Corrupted packet received!" 00616 " rx_err: %#08x\n", rx_err ); 00617 } else { 00618 /* Add this packet to the receive queue. */ 00619 netdev_rx ( netdev, adapter->rx_iobuf[i] ); 00620 } 00621 adapter->rx_iobuf[i] = NULL; 00622 00623 memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) ); 00624 00625 adapter->rx_curr = ( adapter->rx_curr + 1 ) % NUM_RX_DESC; 00626 } 00627 }
| static void igb_close | ( | struct net_device * | netdev | ) | [static] |
Functions that implement the gPXE driver API.
igb_close - Disables a network interface
Definition at line 637 of file igb_main.c.
References DBGP, E1000_ICR, E1000_RCTL, E1000_RCTL_EN, E1000_READ_REG, E1000_WRITE_FLUSH, E1000_WRITE_REG, igb_adapter::hw, igb_free_rx_resources(), igb_free_tx_resources(), igb_irq_disable(), igb_reset(), and netdev_priv().
00638 { 00639 struct igb_adapter *adapter = netdev_priv ( netdev ); 00640 struct e1000_hw *hw = &adapter->hw; 00641 uint32_t rctl; 00642 uint32_t icr; 00643 00644 DBGP ( "igb_close\n" ); 00645 00646 /* Acknowledge interrupts */ 00647 icr = E1000_READ_REG ( hw, E1000_ICR ); 00648 00649 igb_irq_disable ( adapter ); 00650 00651 /* disable receives */ 00652 rctl = E1000_READ_REG ( hw, E1000_RCTL ); 00653 E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN ); 00654 E1000_WRITE_FLUSH(hw); 00655 00656 igb_reset ( adapter ); 00657 00658 igb_free_tx_resources ( adapter ); 00659 igb_free_rx_resources ( adapter ); 00660 }
| static int igb_transmit | ( | struct net_device * | netdev, | |
| struct io_buffer * | iobuf | |||
| ) | [static] |
igb_transmit - Transmit a packet
| netdev | Network device | |
| iobuf | I/O buffer |
| rc | Returns 0 on success, negative on failure |
Definition at line 670 of file igb_main.c.
References e1000_tx_desc::buffer_addr, e1000_tx_desc::data, io_buffer::data, DBG, DBGP, E1000_TDT, E1000_WRITE_FLUSH, E1000_WRITE_REG, ENOBUFS, igb_adapter::hw, iob_len(), e1000_tx_desc::lower, netdev_priv(), NUM_TX_DESC, igb_adapter::tx_base, igb_adapter::tx_fill_ctr, igb_adapter::tx_iobuf, igb_adapter::tx_tail, igb_adapter::txd_cmd, e1000_tx_desc::upper, and virt_to_bus().
00671 { 00672 struct igb_adapter *adapter = netdev_priv( netdev ); 00673 struct e1000_hw *hw = &adapter->hw; 00674 uint32_t tx_curr = adapter->tx_tail; 00675 struct e1000_tx_desc *tx_curr_desc; 00676 00677 DBGP ("igb_transmit\n"); 00678 00679 if ( adapter->tx_fill_ctr == NUM_TX_DESC ) { 00680 DBG ("TX overflow\n"); 00681 return -ENOBUFS; 00682 } 00683 00684 /* Save pointer to iobuf we have been given to transmit, 00685 netdev_tx_complete() will need it later 00686 */ 00687 adapter->tx_iobuf[tx_curr] = iobuf; 00688 00689 tx_curr_desc = ( void * ) ( adapter->tx_base ) + 00690 ( tx_curr * sizeof ( *adapter->tx_base ) ); 00691 00692 DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) ); 00693 DBG ( "tx_curr_desc + 16 = %#08lx\n", virt_to_bus ( tx_curr_desc ) + 16 ); 00694 DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) ); 00695 00696 /* Add the packet to TX ring 00697 */ 00698 tx_curr_desc->buffer_addr = virt_to_bus ( iobuf->data ); 00699 tx_curr_desc->upper.data = 0; 00700 tx_curr_desc->lower.data = adapter->txd_cmd | iob_len ( iobuf ); 00701 00702 DBG ( "TX fill: %d tx_curr: %d addr: %#08lx len: %zd\n", adapter->tx_fill_ctr, 00703 tx_curr, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) ); 00704 00705 /* Point to next free descriptor */ 00706 adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC; 00707 adapter->tx_fill_ctr++; 00708 00709 /* Write new tail to NIC, making packet available for transmit 00710 */ 00711 E1000_WRITE_REG ( hw, E1000_TDT(0), adapter->tx_tail ); 00712 E1000_WRITE_FLUSH(hw); 00713 00714 return 0; 00715 }
| static void igb_poll | ( | struct net_device * | netdev | ) | [static] |
igb_poll - Poll for received packets
| netdev | Network device |
Definition at line 722 of file igb_main.c.
References DBG, DBGP, E1000_ICR, E1000_READ_REG, igb_adapter::hw, igb_process_rx_packets(), igb_process_tx_packets(), igb_refill_rx_ring(), and netdev_priv().
00723 { 00724 struct igb_adapter *adapter = netdev_priv( netdev ); 00725 struct e1000_hw *hw = &adapter->hw; 00726 00727 uint32_t icr; 00728 00729 DBGP ( "igb_poll\n" ); 00730 00731 /* Acknowledge interrupts */ 00732 icr = E1000_READ_REG ( hw, E1000_ICR ); 00733 if ( ! icr ) 00734 return; 00735 00736 DBG ( "igb_poll: intr_status = %#08x\n", icr ); 00737 00738 igb_process_tx_packets ( netdev ); 00739 00740 igb_process_rx_packets ( netdev ); 00741 00742 igb_refill_rx_ring(adapter); 00743 }
| static void igb_irq | ( | struct net_device * | netdev, | |
| int | enable | |||
| ) | [static] |
igb_irq - enable or Disable interrupts
| adapter | e1000 adapter | |
| action | requested interrupt action |
Definition at line 751 of file igb_main.c.
References DBGP, igb_irq_disable(), igb_irq_enable(), and netdev_priv().
00752 { 00753 struct igb_adapter *adapter = netdev_priv ( netdev ); 00754 00755 DBGP ( "igb_irq\n" ); 00756 00757 if ( enable ) { 00758 igb_irq_enable ( adapter ); 00759 } else { 00760 igb_irq_disable ( adapter ); 00761 } 00762 }
| int igb_probe | ( | struct pci_device * | pdev, | |
| const struct pci_device_id *ent | __unused | |||
| ) |
igb_probe - Initial configuration of NIC
| pci | PCI device | |
| id | PCI IDs |
| rc | Return status code |
Definition at line 774 of file igb_main.c.
References e1000_mac_info::adaptive_ifs, adjust_pci_device(), alloc_etherdev(), AUTO_ALL_MODES, e1000_mac_info::autoneg, e1000_phy_info::autoneg_wait_to_complete, e1000_hw::back, e1000_fc_info::current_mode, DBG, DBGP, pci_device::dev, net_device::dev, pci_device::device, e1000_hw::device_id, e1000_phy_info::disable_polarity_correction, e1000_fc_default, e1000_media_type_copper, e1000_ms_hw_default, EIO, ENOMEM, ETH_ALEN, ETH_FCS_LEN, ETH_FRAME_LEN, ETH_ZLEN, e1000_hw::fc, igb_adapter::fc_autoneg, igb_adapter::hw, net_device::hw_addr, e1000_hw::hw_addr, igb_get_bus_info(), igb_get_hw_control(), igb_operations, igb_read_mac_addr(), igb_reset(), igb_reset_hw(), igb_sw_init(), igb_validate_mdi_setting(), igb_validate_nvm_checksum(), e1000_hw::io_base, pci_device::ioaddr, igb_adapter::ioaddr, ioremap(), iounmap(), pci_device::irq, igb_adapter::irqno, net_device::ll_addr, e1000_hw::mac, igb_adapter::max_hw_frame_size, e1000_phy_info::mdix, e1000_phy_info::media_type, memcpy, memset(), igb_adapter::min_frame_size, e1000_phy_info::ms_type, igb_adapter::netdev, netdev, netdev_init(), netdev_link_up(), netdev_priv(), netdev_put(), NUM_RX_DESC, NUM_TX_DESC, pci_bar_size(), pci_bar_start(), PCI_BASE_ADDRESS_0, pci_set_drvdata(), igb_adapter::pdev, e1000_mac_info::perm_addr, e1000_hw::phy, register_netdev(), e1000_fc_info::requested_mode, igb_adapter::rx_base, igb_adapter::rx_ring_size, igb_adapter::tx_base, igb_adapter::tx_ring_size, e1000_mac_info::type, pci_device::vendor, and e1000_hw::vendor_id.
00776 { 00777 int i, err; 00778 struct net_device *netdev; 00779 struct igb_adapter *adapter; 00780 unsigned long mmio_start, mmio_len; 00781 struct e1000_hw *hw; 00782 00783 DBGP ( "igb_probe\n" ); 00784 00785 err = -ENOMEM; 00786 00787 /* Allocate net device ( also allocates memory for netdev->priv 00788 and makes netdev-priv point to it ) */ 00789 netdev = alloc_etherdev ( sizeof ( struct igb_adapter ) ); 00790 if ( ! netdev ) { 00791 DBG ( "err_alloc_etherdev\n" ); 00792 goto err_alloc_etherdev; 00793 } 00794 00795 /* Associate igb-specific network operations operations with 00796 * generic network device layer */ 00797 netdev_init ( netdev, &igb_operations ); 00798 00799 /* Associate this network device with given PCI device */ 00800 pci_set_drvdata ( pdev, netdev ); 00801 netdev->dev = &pdev->dev; 00802 00803 /* Initialize driver private storage */ 00804 adapter = netdev_priv ( netdev ); 00805 memset ( adapter, 0, ( sizeof ( *adapter ) ) ); 00806 00807 adapter->pdev = pdev; 00808 00809 adapter->ioaddr = pdev->ioaddr; 00810 adapter->hw.io_base = pdev->ioaddr; 00811 00812 hw = &adapter->hw; 00813 hw->vendor_id = pdev->vendor; 00814 hw->device_id = pdev->device; 00815 00816 adapter->irqno = pdev->irq; 00817 adapter->netdev = netdev; 00818 adapter->hw.back = adapter; 00819 00820 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 00821 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; 00822 00823 adapter->tx_ring_size = sizeof ( *adapter->tx_base ) * NUM_TX_DESC; 00824 adapter->rx_ring_size = sizeof ( *adapter->rx_base ) * NUM_RX_DESC; 00825 00826 /* Fix up PCI device */ 00827 adjust_pci_device ( pdev ); 00828 00829 err = -EIO; 00830 00831 mmio_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_0 ); 00832 mmio_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_0 ); 00833 00834 DBG ( "mmio_start: %#08lx\n", mmio_start ); 00835 DBG ( "mmio_len: %#08lx\n", mmio_len ); 00836 00837 adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len ); 00838 DBG ( "adapter->hw.hw_addr: %p\n", adapter->hw.hw_addr ); 00839 00840 if ( ! adapter->hw.hw_addr ) { 00841 DBG ( "err_ioremap\n" ); 00842 goto err_ioremap; 00843 } 00844 00845 /* setup adapter struct */ 00846 err = igb_sw_init ( adapter ); 00847 if (err) { 00848 DBG ( "err_sw_init\n" ); 00849 goto err_sw_init; 00850 } 00851 00852 igb_get_bus_info(hw); 00853 00854 /* Copper options */ 00855 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 00856 adapter->hw.phy.mdix = AUTO_ALL_MODES; 00857 adapter->hw.phy.disable_polarity_correction = 0; 00858 adapter->hw.phy.ms_type = e1000_ms_hw_default; 00859 } 00860 00861 DBG ( "adapter->hw.mac.type: %#08x\n", adapter->hw.mac.type ); 00862 00863 /* Force auto-negotiation */ 00864 adapter->hw.mac.autoneg = 1; 00865 adapter->fc_autoneg = 1; 00866 adapter->hw.phy.autoneg_wait_to_complete = true; 00867 adapter->hw.mac.adaptive_ifs = true; 00868 adapter->hw.fc.requested_mode = e1000_fc_default; 00869 adapter->hw.fc.current_mode = e1000_fc_default; 00870 00871 igb_validate_mdi_setting(hw); 00872 00873 /* 00874 * before reading the NVM, reset the controller to 00875 * put the device in a known good starting state 00876 */ 00877 igb_reset_hw(hw); 00878 00879 /* 00880 * systems with ASPM and others may see the checksum fail on the first 00881 * attempt. Let's give it a few tries 00882 */ 00883 for (i = 0;; i++) { 00884 if (igb_validate_nvm_checksum(&adapter->hw) >= 0) 00885 break; 00886 if (i == 2) { 00887 err = -EIO; 00888 DBG ( "The NVM Checksum Is Not Valid\n" ); 00889 DBG ( "err_eeprom\n" ); 00890 goto err_eeprom; 00891 } 00892 } 00893 00894 /* copy the MAC address out of the EEPROM */ 00895 if ( igb_read_mac_addr ( &adapter->hw ) ) { 00896 DBG ( "EEPROM Read Error\n" ); 00897 } 00898 00899 memcpy ( netdev->hw_addr, adapter->hw.mac.perm_addr, ETH_ALEN ); 00900 00901 /* reset the hardware with the new settings */ 00902 igb_reset ( adapter ); 00903 00904 /* let the f/w know that the h/w is now under the control of the 00905 * driver. */ 00906 igb_get_hw_control(adapter); 00907 00908 /* Mark as link up; we don't yet handle link state */ 00909 netdev_link_up ( netdev ); 00910 00911 if ( ( err = register_netdev ( netdev ) ) != 0) { 00912 DBG ( "err_register\n" ); 00913 goto err_register; 00914 } 00915 00916 for (i = 0; i < 6; i++) { 00917 DBG ("%02x%s", netdev->ll_addr[i], i == 5 ? "\n" : ":"); 00918 } 00919 00920 DBG ( "igb_probe succeeded!\n" ); 00921 00922 /* No errors, return success */ 00923 return 0; 00924 00925 /* Error return paths */ 00926 err_register: 00927 err_eeprom: 00928 err_sw_init: 00929 iounmap ( adapter->hw.hw_addr ); 00930 err_ioremap: 00931 netdev_put ( netdev ); 00932 err_alloc_etherdev: 00933 return err; 00934 }
| void igb_remove | ( | struct pci_device * | pdev | ) |
igb_remove - Device Removal Routine
| pdev | PCI device information struct |
Definition at line 942 of file igb_main.c.
References DBGP, e1000_hw::flash_address, igb_adapter::hw, e1000_hw::hw_addr, igb_reset(), iounmap(), netdev, netdev_nullify(), netdev_priv(), netdev_put(), pci_get_drvdata(), and unregister_netdev().
00943 { 00944 struct net_device *netdev = pci_get_drvdata ( pdev ); 00945 struct igb_adapter *adapter = netdev_priv ( netdev ); 00946 00947 DBGP ( "igb_remove\n" ); 00948 00949 if ( adapter->hw.flash_address ) 00950 iounmap ( adapter->hw.flash_address ); 00951 if ( adapter->hw.hw_addr ) 00952 iounmap ( adapter->hw.hw_addr ); 00953 00954 unregister_netdev ( netdev ); 00955 igb_reset ( adapter ); 00956 netdev_nullify ( netdev ); 00957 netdev_put ( netdev ); 00958 }
| static int igb_open | ( | struct net_device * | netdev | ) | [static] |
igb_open - Called when a network interface is made active
| rc | Return status code, 0 on success, negative value on failure |
Definition at line 967 of file igb_main.c.
References DBG, DBGP, E1000_READ_REG, E1000_RXDCTL, igb_adapter::hw, igb_configure_rx(), igb_configure_tx(), igb_free_tx_resources(), igb_reset(), igb_setup_rx_resources(), igb_setup_tx_resources(), and netdev_priv().
00968 { 00969 struct igb_adapter *adapter = netdev_priv(netdev); 00970 int err; 00971 00972 DBGP ( "igb_open\n" ); 00973 00974 /* allocate transmit descriptors */ 00975 err = igb_setup_tx_resources ( adapter ); 00976 if ( err ) { 00977 DBG ( "Error setting up TX resources!\n" ); 00978 goto err_setup_tx; 00979 } 00980 00981 /* allocate receive descriptors */ 00982 err = igb_setup_rx_resources ( adapter ); 00983 if ( err ) { 00984 DBG ( "Error setting up RX resources!\n" ); 00985 goto err_setup_rx; 00986 } 00987 00988 igb_configure_tx ( adapter ); 00989 00990 igb_configure_rx ( adapter ); 00991 00992 DBG ( "E1000_RXDCTL(0): %#08x\n", E1000_READ_REG ( &adapter->hw, E1000_RXDCTL(0) ) ); 00993 00994 return 0; 00995 00996 err_setup_rx: 00997 DBG ( "err_setup_rx\n" ); 00998 igb_free_tx_resources ( adapter ); 00999 err_setup_tx: 01000 DBG ( "err_setup_tx\n" ); 01001 igb_reset ( adapter ); 01002 01003 return err; 01004 }
static struct net_device_operations igb_operations [static, read] |
Initial value:
{
.open = igb_open,
.close = igb_close,
.transmit = igb_transmit,
.poll = igb_poll,
.irq = igb_irq,
}
Definition at line 764 of file igb_main.c.
Referenced by igb_probe().
1.5.7.1