#include "igb.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_ONLY) | |
| static s32 | igb_set_default_fc_generic (struct e1000_hw *hw) |
| igb_set_default_fc_generic - Set flow control default values : pointer to the HW structure | |
| static s32 | igb_commit_fc_settings_generic (struct e1000_hw *hw) |
| igb_commit_fc_settings_generic - Configure flow control : pointer to the HW structure | |
| static s32 | igb_poll_fiber_serdes_link_generic (struct e1000_hw *hw) |
| igb_poll_fiber_serdes_link_generic - Poll for link up : pointer to the HW structure | |
| static s32 | igb_validate_mdi_setting_generic (struct e1000_hw *hw) |
| igb_validate_mdi_setting_generic - Verify MDI/MDIx settings : pointer to the HW structure | |
| static void | igb_set_lan_id_multi_port_pcie (struct e1000_hw *hw) |
| igb_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices | |
| void | igb_init_mac_ops_generic (struct e1000_hw *hw) |
| igb_init_mac_ops_generic - Initialize MAC function pointers : pointer to the HW structure | |
| s32 | igb_get_bus_info_pcie_generic (struct e1000_hw *hw) |
| igb_get_bus_info_pcie_generic - Get PCIe bus information : pointer to the HW structure | |
| void | igb_set_lan_id_single_port (struct e1000_hw *hw) |
| igb_set_lan_id_single_port - Set LAN id for a single port device : pointer to the HW structure | |
| void | igb_clear_vfta_generic (struct e1000_hw *hw) |
| igb_clear_vfta_generic - Clear VLAN filter table : pointer to the HW structure | |
| void | igb_write_vfta_generic (struct e1000_hw *hw, u32 offset, u32 value) |
| igb_write_vfta_generic - Write value to VLAN filter table : pointer to the HW structure : register offset in VLAN filter table : register value written to VLAN filter table | |
| void | igb_init_rx_addrs_generic (struct e1000_hw *hw, u16 rar_count) |
| igb_init_rx_addrs_generic - Initialize receive address's : pointer to the HW structure : receive address registers | |
| s32 | igb_check_alt_mac_addr_generic (struct e1000_hw *hw) |
| igb_check_alt_mac_addr_generic - Check for alternate MAC addr : pointer to the HW structure | |
| void | igb_rar_set_generic (struct e1000_hw *hw, u8 *addr, u32 index) |
| igb_rar_set_generic - Set receive address register : pointer to the HW structure : pointer to the receive address : receive address array register | |
| void | igb_mta_set_generic (struct e1000_hw *hw, u32 hash_value) |
| igb_mta_set_generic - Set multicast filter table address : pointer to the HW structure : determines the MTA register and bit to set | |
| void | igb_update_mc_addr_list_generic (struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count) |
| igb_update_mc_addr_list_generic - Update Multicast addresses : pointer to the HW structure : array of multicast addresses to program : number of multicast addresses to program | |
| u32 | igb_hash_mc_addr_generic (struct e1000_hw *hw, u8 *mc_addr) |
| igb_hash_mc_addr_generic - Generate a multicast hash value : pointer to the HW structure : pointer to a multicast address | |
| void | igb_clear_hw_cntrs_base_generic (struct e1000_hw *hw) |
| igb_clear_hw_cntrs_base_generic - Clear base hardware counters : pointer to the HW structure | |
| s32 | igb_check_for_copper_link_generic (struct e1000_hw *hw) |
| igb_check_for_copper_link_generic - Check for link (Copper) : pointer to the HW structure | |
| s32 | igb_check_for_fiber_link_generic (struct e1000_hw *hw) |
| igb_check_for_fiber_link_generic - Check for link (Fiber) : pointer to the HW structure | |
| s32 | igb_check_for_serdes_link_generic (struct e1000_hw *hw) |
| igb_check_for_serdes_link_generic - Check for link (Serdes) : pointer to the HW structure | |
| s32 | igb_setup_link_generic (struct e1000_hw *hw) |
| igb_setup_link_generic - Setup flow control and link settings : pointer to the HW structure | |
| s32 | igb_setup_fiber_serdes_link_generic (struct e1000_hw *hw) |
| igb_setup_fiber_serdes_link_generic - Setup link for fiber/serdes : pointer to the HW structure | |
| void | igb_config_collision_dist_generic (struct e1000_hw *hw) |
| igb_config_collision_dist_generic - Configure collision distance : pointer to the HW structure | |
| s32 | igb_set_fc_watermarks_generic (struct e1000_hw *hw) |
| igb_set_fc_watermarks_generic - Set flow control high/low watermarks : pointer to the HW structure | |
| s32 | igb_force_mac_fc_generic (struct e1000_hw *hw) |
| igb_force_mac_fc_generic - Force the MAC's flow control settings : pointer to the HW structure | |
| s32 | igb_config_fc_after_link_up_generic (struct e1000_hw *hw) |
| igb_config_fc_after_link_up_generic - Configures flow control after link : pointer to the HW structure | |
| s32 | igb_get_speed_and_duplex_copper_generic (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| igb_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex | |
| s32 | igb_get_speed_and_duplex_fiber_serdes_generic (struct e1000_hw *hw __unused, u16 *speed, u16 *duplex) |
| igb_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex | |
| s32 | igb_get_hw_semaphore_generic (struct e1000_hw *hw) |
| igb_get_hw_semaphore_generic - Acquire hardware semaphore : pointer to the HW structure | |
| void | igb_put_hw_semaphore_generic (struct e1000_hw *hw) |
| igb_put_hw_semaphore_generic - Release hardware semaphore : pointer to the HW structure | |
| s32 | igb_get_auto_rd_done_generic (struct e1000_hw *hw) |
| igb_get_auto_rd_done_generic - Check for auto read completion : pointer to the HW structure | |
| s32 | igb_valid_led_default_generic (struct e1000_hw *hw, u16 *data) |
| igb_valid_led_default_generic - Verify a valid default LED config : pointer to the HW structure : pointer to the NVM (EEPROM) | |
| s32 | igb_id_led_init_generic (struct e1000_hw *hw) |
| e1000_id_led_init_generic - : pointer to the HW structure | |
| void | igb_set_pcie_no_snoop_generic (struct e1000_hw *hw, u32 no_snoop) |
| igb_set_pcie_no_snoop_generic - Set PCI-express capabilities : pointer to the HW structure : bitmap of snoop events | |
| s32 | igb_disable_pcie_master_generic (struct e1000_hw *hw) |
| igb_disable_pcie_master_generic - Disables PCI-express master access : pointer to the HW structure | |
| void | igb_reset_adaptive_generic (struct e1000_hw *hw) |
| igb_reset_adaptive_generic - Reset Adaptive Interframe Spacing : pointer to the HW structure | |
| void | igb_update_adaptive_generic (struct e1000_hw *hw) |
| igb_update_adaptive_generic - Update Adaptive Interframe Spacing : pointer to the HW structure | |
| s32 | igb_write_8bit_ctrl_reg_generic (struct e1000_hw *hw, u32 reg, u32 offset, u8 data) |
| igb_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register : pointer to the HW structure : 32bit register offset such as E1000_SCTL : register offset to write to : data to write at register offset | |
| FILE_LICENCE | ( | GPL2_ONLY | ) |
igb_set_default_fc_generic - Set flow control default values : pointer to the HW structure
Read the EEPROM for the default values for flow control and store the values.
Definition at line 1076 of file igb_mac.c.
References DEBUGFUNC, DEBUGOUT, e1000_fc_full, e1000_fc_none, e1000_fc_tx_pause, E1000_SUCCESS, e1000_hw::fc, e1000_hw::nvm, NVM_INIT_CONTROL2_REG, NVM_WORD0F_ASM_DIR, NVM_WORD0F_PAUSE_MASK, e1000_nvm_info::ops, e1000_nvm_operations::read, e1000_fc_info::requested_mode, and u16.
Referenced by igb_setup_link_generic().
01077 { 01078 s32 ret_val = E1000_SUCCESS; 01079 u16 nvm_data; 01080 01081 DEBUGFUNC("igb_set_default_fc_generic"); 01082 01083 /* 01084 * Read and store word 0x0F of the EEPROM. This word contains bits 01085 * that determine the hardware's default PAUSE (flow control) mode, 01086 * a bit that determines whether the HW defaults to enabling or 01087 * disabling auto-negotiation, and the direction of the 01088 * SW defined pins. If there is no SW over-ride of the flow 01089 * control setting, then the variable hw->fc will 01090 * be initialized based on a value in the EEPROM. 01091 */ 01092 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 01093 01094 if (ret_val) { 01095 DEBUGOUT("NVM Read Error\n"); 01096 goto out; 01097 } 01098 01099 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 01100 hw->fc.requested_mode = e1000_fc_none; 01101 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 01102 NVM_WORD0F_ASM_DIR) 01103 hw->fc.requested_mode = e1000_fc_tx_pause; 01104 else 01105 hw->fc.requested_mode = e1000_fc_full; 01106 01107 out: 01108 return ret_val; 01109 }
igb_commit_fc_settings_generic - Configure flow control : pointer to the HW structure
Write the flow control settings to the Transmit Config Word Register (TXCW) base on the flow control settings in e1000_mac_info.
Definition at line 960 of file igb_mac.c.
References e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, E1000_ERR_CONFIG, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, E1000_SUCCESS, E1000_TXCW, E1000_TXCW_ANE, E1000_TXCW_ASM_DIR, E1000_TXCW_FD, E1000_TXCW_PAUSE_MASK, E1000_WRITE_REG, e1000_hw::fc, e1000_hw::mac, e1000_mac_info::txcw, and u32.
Referenced by igb_setup_fiber_serdes_link_generic().
00961 { 00962 struct e1000_mac_info *mac = &hw->mac; 00963 u32 txcw; 00964 s32 ret_val = E1000_SUCCESS; 00965 00966 DEBUGFUNC("igb_commit_fc_settings_generic"); 00967 00968 /* 00969 * Check for a software override of the flow control settings, and 00970 * setup the device accordingly. If auto-negotiation is enabled, then 00971 * software will have to set the "PAUSE" bits to the correct value in 00972 * the Transmit Config Word Register (TXCW) and re-start auto- 00973 * negotiation. However, if auto-negotiation is disabled, then 00974 * software will have to manually configure the two flow control enable 00975 * bits in the CTRL register. 00976 * 00977 * The possible values of the "fc" parameter are: 00978 * 0: Flow control is completely disabled 00979 * 1: Rx flow control is enabled (we can receive pause frames, 00980 * but not send pause frames). 00981 * 2: Tx flow control is enabled (we can send pause frames but we 00982 * do not support receiving pause frames). 00983 * 3: Both Rx and Tx flow control (symmetric) are enabled. 00984 */ 00985 switch (hw->fc.current_mode) { 00986 case e1000_fc_none: 00987 /* Flow control completely disabled by a software over-ride. */ 00988 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 00989 break; 00990 case e1000_fc_rx_pause: 00991 /* 00992 * Rx Flow control is enabled and Tx Flow control is disabled 00993 * by a software over-ride. Since there really isn't a way to 00994 * advertise that we are capable of Rx Pause ONLY, we will 00995 * advertise that we support both symmetric and asymmetric RX 00996 * PAUSE. Later, we will disable the adapter's ability to send 00997 * PAUSE frames. 00998 */ 00999 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 01000 break; 01001 case e1000_fc_tx_pause: 01002 /* 01003 * Tx Flow control is enabled, and Rx Flow control is disabled, 01004 * by a software over-ride. 01005 */ 01006 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 01007 break; 01008 case e1000_fc_full: 01009 /* 01010 * Flow control (both Rx and Tx) is enabled by a software 01011 * over-ride. 01012 */ 01013 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 01014 break; 01015 default: 01016 DEBUGOUT("Flow control param set incorrectly\n"); 01017 ret_val = -E1000_ERR_CONFIG; 01018 goto out; 01019 break; 01020 } 01021 01022 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 01023 mac->txcw = txcw; 01024 01025 out: 01026 return ret_val; 01027 }
igb_poll_fiber_serdes_link_generic - Poll for link up : pointer to the HW structure
Polls for link up by reading the status register, if link fails to come up with auto-negotiation, then the link is forced if a signal is detected.
Definition at line 908 of file igb_mac.c.
References e1000_mac_info::autoneg_failed, e1000_mac_operations::check_for_link, DEBUGFUNC, DEBUGOUT, E1000_READ_REG, E1000_STATUS, E1000_STATUS_LU, E1000_SUCCESS, FIBER_LINK_UP_LIMIT, e1000_hw::mac, msec_delay, e1000_mac_info::ops, and u32.
Referenced by igb_setup_fiber_serdes_link_generic().
00909 { 00910 struct e1000_mac_info *mac = &hw->mac; 00911 u32 i, status; 00912 s32 ret_val = E1000_SUCCESS; 00913 00914 DEBUGFUNC("igb_poll_fiber_serdes_link_generic"); 00915 00916 /* 00917 * If we have a signal (the cable is plugged in, or assumed true for 00918 * serdes media) then poll for a "Link-Up" indication in the Device 00919 * Status Register. Time-out if a link isn't seen in 500 milliseconds 00920 * seconds (Auto-negotiation should complete in less than 500 00921 * milliseconds even if the other end is doing it in SW). 00922 */ 00923 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 00924 msec_delay(10); 00925 status = E1000_READ_REG(hw, E1000_STATUS); 00926 if (status & E1000_STATUS_LU) 00927 break; 00928 } 00929 if (i == FIBER_LINK_UP_LIMIT) { 00930 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 00931 mac->autoneg_failed = 1; 00932 /* 00933 * AutoNeg failed to achieve a link, so we'll call 00934 * mac->check_for_link. This routine will force the 00935 * link up if we detect a signal. This will allow us to 00936 * communicate with non-autonegotiating link partners. 00937 */ 00938 ret_val = hw->mac.ops.check_for_link(hw); 00939 if (ret_val) { 00940 DEBUGOUT("Error while checking for link\n"); 00941 goto out; 00942 } 00943 mac->autoneg_failed = 0; 00944 } else { 00945 mac->autoneg_failed = 0; 00946 DEBUGOUT("Valid Link Found\n"); 00947 } 00948 00949 out: 00950 return ret_val; 00951 }
igb_validate_mdi_setting_generic - Verify MDI/MDIx settings : pointer to the HW structure
Verify that when not using auto-negotiation that MDI/MDIx is correctly set, which is forced to MDI mode only.
Definition at line 1936 of file igb_mac.c.
References e1000_mac_info::autoneg, DEBUGFUNC, DEBUGOUT, E1000_ERR_CONFIG, E1000_SUCCESS, e1000_hw::mac, e1000_phy_info::mdix, and e1000_hw::phy.
Referenced by igb_init_mac_ops_generic().
01937 { 01938 s32 ret_val = E1000_SUCCESS; 01939 01940 DEBUGFUNC("igb_validate_mdi_setting_generic"); 01941 01942 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 01943 DEBUGOUT("Invalid MDI setting detected\n"); 01944 hw->phy.mdix = 1; 01945 ret_val = -E1000_ERR_CONFIG; 01946 goto out; 01947 } 01948 01949 out: 01950 return ret_val; 01951 }
| static void igb_set_lan_id_multi_port_pcie | ( | struct e1000_hw * | hw | ) | [static] |
igb_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
: pointer to the HW structure
Determines the LAN function id by reading memory-mapped registers and swaps the port value if requested.
Definition at line 110 of file igb_mac.c.
References e1000_hw::bus, E1000_READ_REG, E1000_STATUS, E1000_STATUS_FUNC_MASK, E1000_STATUS_FUNC_SHIFT, e1000_bus_info::func, and u32.
Referenced by igb_init_mac_ops_generic().
00111 { 00112 struct e1000_bus_info *bus = &hw->bus; 00113 u32 reg; 00114 00115 /* 00116 * The status register reports the correct function number 00117 * for the device regardless of function swap state. 00118 */ 00119 reg = E1000_READ_REG(hw, E1000_STATUS); 00120 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 00121 }
| void igb_init_mac_ops_generic | ( | struct e1000_hw * | hw | ) |
igb_init_mac_ops_generic - Initialize MAC function pointers : pointer to the HW structure
Setups up the function pointers to no-op functions
Definition at line 44 of file igb_mac.c.
References e1000_mac_operations::config_collision_dist, DEBUGFUNC, igb_config_collision_dist_generic(), igb_rar_set_generic(), igb_read_mac_addr_generic(), igb_set_lan_id_multi_port_pcie(), igb_validate_mdi_setting_generic(), igb_wait_autoneg_generic(), e1000_hw::mac, e1000_mac_operations::mng_enable_host_if, e1000_mac_operations::mng_host_if_write, e1000_mac_operations::mng_write_cmd_header, e1000_mac_info::ops, e1000_mac_operations::rar_set, e1000_mac_operations::read_mac_addr, e1000_mac_operations::set_lan_id, e1000_mac_operations::validate_mdi_setting, and e1000_mac_operations::wait_autoneg.
Referenced by igb_setup_init_funcs().
00045 { 00046 struct e1000_mac_info *mac = &hw->mac; 00047 DEBUGFUNC("igb_init_mac_ops_generic"); 00048 00049 /* General Setup */ 00050 mac->ops.set_lan_id = igb_set_lan_id_multi_port_pcie; 00051 mac->ops.read_mac_addr = igb_read_mac_addr_generic; 00052 mac->ops.config_collision_dist = igb_config_collision_dist_generic; 00053 /* LINK */ 00054 mac->ops.wait_autoneg = igb_wait_autoneg_generic; 00055 /* Management */ 00056 #if 0 00057 mac->ops.mng_host_if_write = igb_mng_host_if_write_generic; 00058 mac->ops.mng_write_cmd_header = igb_mng_write_cmd_header_generic; 00059 mac->ops.mng_enable_host_if = igb_mng_enable_host_if_generic; 00060 #endif 00061 /* VLAN, MC, etc. */ 00062 mac->ops.rar_set = igb_rar_set_generic; 00063 mac->ops.validate_mdi_setting = igb_validate_mdi_setting_generic; 00064 }
igb_get_bus_info_pcie_generic - Get PCIe bus information : pointer to the HW structure
Determines and stores the system bus information for a particular network interface. The following bus information is determined and stored: bus speed, bus width, type (PCIe), and PCIe function.
Definition at line 74 of file igb_mac.c.
References e1000_hw::bus, DEBUGFUNC, e1000_bus_speed_2500, e1000_bus_type_pci_express, e1000_bus_width_unknown, E1000_SUCCESS, igb_read_pcie_cap_reg(), e1000_hw::mac, e1000_mac_info::ops, PCIE_LINK_STATUS, PCIE_LINK_WIDTH_MASK, PCIE_LINK_WIDTH_SHIFT, e1000_mac_operations::set_lan_id, e1000_bus_info::speed, e1000_bus_info::type, u16, and e1000_bus_info::width.
Referenced by igb_init_mac_params_82575().
00075 { 00076 struct e1000_mac_info *mac = &hw->mac; 00077 struct e1000_bus_info *bus = &hw->bus; 00078 00079 s32 ret_val; 00080 u16 pcie_link_status; 00081 00082 DEBUGFUNC("igb_get_bus_info_pcie_generic"); 00083 00084 bus->type = e1000_bus_type_pci_express; 00085 bus->speed = e1000_bus_speed_2500; 00086 00087 ret_val = igb_read_pcie_cap_reg(hw, 00088 PCIE_LINK_STATUS, 00089 &pcie_link_status); 00090 if (ret_val) 00091 bus->width = e1000_bus_width_unknown; 00092 else 00093 bus->width = (enum e1000_bus_width)((pcie_link_status & 00094 PCIE_LINK_WIDTH_MASK) >> 00095 PCIE_LINK_WIDTH_SHIFT); 00096 00097 mac->ops.set_lan_id(hw); 00098 00099 return E1000_SUCCESS; 00100 }
| void igb_set_lan_id_single_port | ( | struct e1000_hw * | hw | ) |
igb_set_lan_id_single_port - Set LAN id for a single port device : pointer to the HW structure
Sets the LAN function id to zero for a single port device.
Definition at line 129 of file igb_mac.c.
References e1000_hw::bus, and e1000_bus_info::func.
00130 { 00131 struct e1000_bus_info *bus = &hw->bus; 00132 00133 bus->func = 0; 00134 }
| void igb_clear_vfta_generic | ( | struct e1000_hw * | hw | ) |
igb_clear_vfta_generic - Clear VLAN filter table : pointer to the HW structure
Clears the register array which contains the VLAN filter table by setting all the values to 0.
Definition at line 143 of file igb_mac.c.
References DEBUGFUNC, E1000_VFTA, E1000_VLAN_FILTER_TBL_SIZE, E1000_WRITE_FLUSH, E1000_WRITE_REG_ARRAY, offset, and u32.
Referenced by igb_init_mac_params_82575().
00144 { 00145 u32 offset; 00146 00147 DEBUGFUNC("igb_clear_vfta_generic"); 00148 00149 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 00150 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 00151 E1000_WRITE_FLUSH(hw); 00152 } 00153 }
igb_write_vfta_generic - Write value to VLAN filter table : pointer to the HW structure : register offset in VLAN filter table : register value written to VLAN filter table
Writes value at the given offset in the register array which stores the VLAN filter table.
Definition at line 164 of file igb_mac.c.
References DEBUGFUNC, E1000_VFTA, E1000_WRITE_FLUSH, and E1000_WRITE_REG_ARRAY.
Referenced by igb_init_mac_params_82575().
00165 { 00166 DEBUGFUNC("igb_write_vfta_generic"); 00167 00168 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 00169 E1000_WRITE_FLUSH(hw); 00170 }
igb_init_rx_addrs_generic - Initialize receive address's : pointer to the HW structure : receive address registers
Setups the receive address registers by setting the base receive address register to the devices MAC address and clearing all the other receive address registers to 0.
Definition at line 181 of file igb_mac.c.
References e1000_mac_info::addr, DEBUGFUNC, DEBUGOUT, DEBUGOUT1, ETH_ADDR_LEN, e1000_hw::mac, e1000_mac_info::ops, e1000_mac_operations::rar_set, u32, and u8.
Referenced by igb_init_hw_82575().
00182 { 00183 u32 i; 00184 u8 mac_addr[ETH_ADDR_LEN] = {0}; 00185 00186 DEBUGFUNC("igb_init_rx_addrs_generic"); 00187 00188 /* Setup the receive address */ 00189 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 00190 00191 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 00192 00193 /* Zero out the other (rar_entry_count - 1) receive addresses */ 00194 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 00195 for (i = 1; i < rar_count; i++) 00196 hw->mac.ops.rar_set(hw, mac_addr, i); 00197 }
igb_check_alt_mac_addr_generic - Check for alternate MAC addr : pointer to the HW structure
Checks the nvm for an alternate MAC address. An alternate MAC address can be setup by pre-boot software and must be treated like a permanent address and must override the actual permanent MAC address. If an alternate MAC address is found it is programmed into RAR0, replacing the permanent address that was installed into RAR0 by the Si on reset. This function will return SUCCESS unless it encounters an error while reading the EEPROM.
Definition at line 211 of file igb_mac.c.
References e1000_hw::bus, DEBUGFUNC, DEBUGOUT, E1000_ALT_MAC_ADDRESS_OFFSET_LAN1, E1000_FUNC_1, E1000_SUCCESS, ETH_ADDR_LEN, e1000_bus_info::func, e1000_hw::mac, e1000_hw::nvm, NVM_ALT_MAC_ADDR_PTR, offset, e1000_mac_info::ops, e1000_nvm_info::ops, e1000_mac_operations::rar_set, e1000_nvm_operations::read, u16, u32, and u8.
Referenced by igb_read_mac_addr_82575(), and igb_reset_hw_82575().
00212 { 00213 u32 i; 00214 s32 ret_val = E1000_SUCCESS; 00215 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 00216 u8 alt_mac_addr[ETH_ADDR_LEN]; 00217 00218 DEBUGFUNC("igb_check_alt_mac_addr_generic"); 00219 00220 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 00221 &nvm_alt_mac_addr_offset); 00222 if (ret_val) { 00223 DEBUGOUT("NVM Read Error\n"); 00224 goto out; 00225 } 00226 00227 if (nvm_alt_mac_addr_offset == 0xFFFF) { 00228 /* There is no Alternate MAC Address */ 00229 goto out; 00230 } 00231 00232 if (hw->bus.func == E1000_FUNC_1) 00233 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 00234 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 00235 offset = nvm_alt_mac_addr_offset + (i >> 1); 00236 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 00237 if (ret_val) { 00238 DEBUGOUT("NVM Read Error\n"); 00239 goto out; 00240 } 00241 00242 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 00243 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 00244 } 00245 00246 /* if multicast bit is set, the alternate address will not be used */ 00247 if (alt_mac_addr[0] & 0x01) { 00248 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 00249 goto out; 00250 } 00251 00252 /* 00253 * We have a valid alternate MAC address, and we want to treat it the 00254 * same as the normal permanent MAC address stored by the HW into the 00255 * RAR. Do this by mapping this address into RAR0. 00256 */ 00257 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 00258 00259 out: 00260 return ret_val; 00261 }
igb_rar_set_generic - Set receive address register : pointer to the HW structure : pointer to the receive address : receive address array register
Sets the receive address array register at index to the address passed in by addr.
Definition at line 272 of file igb_mac.c.
References DEBUGFUNC, E1000_RAH, E1000_RAH_AV, E1000_RAL, E1000_WRITE_FLUSH, E1000_WRITE_REG, and u32.
Referenced by igb_init_mac_ops_generic(), and igb_init_mac_params_82575().
00273 { 00274 u32 rar_low, rar_high; 00275 00276 DEBUGFUNC("igb_rar_set_generic"); 00277 00278 /* 00279 * HW expects these in little endian so we reverse the byte order 00280 * from network order (big endian) to little endian 00281 */ 00282 rar_low = ((u32) addr[0] | 00283 ((u32) addr[1] << 8) | 00284 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 00285 00286 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 00287 00288 /* If MAC address zero, no need to set the AV bit */ 00289 if (rar_low || rar_high) 00290 rar_high |= E1000_RAH_AV; 00291 00292 /* 00293 * Some bridges will combine consecutive 32-bit writes into 00294 * a single burst write, which will malfunction on some parts. 00295 * The flushes avoid this. 00296 */ 00297 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 00298 E1000_WRITE_FLUSH(hw); 00299 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 00300 E1000_WRITE_FLUSH(hw); 00301 }
igb_mta_set_generic - Set multicast filter table address : pointer to the HW structure : determines the MTA register and bit to set
The multicast table address is a register array of 32-bit registers. The hash_value is used to determine what register the bit is in, the current value is read, the new bit is OR'd in and the new value is written back into the register.
Definition at line 313 of file igb_mac.c.
References DEBUGFUNC, E1000_MTA, E1000_READ_REG_ARRAY, E1000_WRITE_FLUSH, E1000_WRITE_REG_ARRAY, e1000_hw::mac, e1000_mac_info::mta_reg_count, and u32.
Referenced by igb_init_mac_params_82575().
00314 { 00315 u32 hash_bit, hash_reg, mta; 00316 00317 DEBUGFUNC("igb_mta_set_generic"); 00318 /* 00319 * The MTA is a register array of 32-bit registers. It is 00320 * treated like an array of (32*mta_reg_count) bits. We want to 00321 * set bit BitArray[hash_value]. So we figure out what register 00322 * the bit is in, read it, OR in the new bit, then write 00323 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 00324 * mask to bits 31:5 of the hash value which gives us the 00325 * register we're modifying. The hash bit within that register 00326 * is determined by the lower 5 bits of the hash value. 00327 */ 00328 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 00329 hash_bit = hash_value & 0x1F; 00330 00331 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 00332 00333 mta |= (1 << hash_bit); 00334 00335 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 00336 E1000_WRITE_FLUSH(hw); 00337 }
igb_update_mc_addr_list_generic - Update Multicast addresses : pointer to the HW structure : array of multicast addresses to program : number of multicast addresses to program
Updates entire Multicast Table Array. The caller must have a packed mc_addr_list of multicast addresses.
Definition at line 348 of file igb_mac.c.
References DEBUGFUNC, E1000_MTA, E1000_WRITE_FLUSH, E1000_WRITE_REG_ARRAY, ETH_ADDR_LEN, igb_hash_mc_addr_generic(), e1000_hw::mac, memset(), e1000_mac_info::mta_reg_count, e1000_mac_info::mta_shadow, and u32.
Referenced by igb_init_mac_params_82575().
00350 { 00351 u32 hash_value, hash_bit, hash_reg; 00352 int i; 00353 00354 DEBUGFUNC("igb_update_mc_addr_list_generic"); 00355 00356 /* clear mta_shadow */ 00357 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 00358 00359 /* update mta_shadow from mc_addr_list */ 00360 for (i = 0; (u32) i < mc_addr_count; i++) { 00361 hash_value = igb_hash_mc_addr_generic(hw, mc_addr_list); 00362 00363 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 00364 hash_bit = hash_value & 0x1F; 00365 00366 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 00367 mc_addr_list += (ETH_ADDR_LEN); 00368 } 00369 00370 /* replace the entire MTA table */ 00371 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 00372 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 00373 E1000_WRITE_FLUSH(hw); 00374 }
igb_hash_mc_addr_generic - Generate a multicast hash value : pointer to the HW structure : pointer to a multicast address
Generates a multicast address hash value which is used to determine the multicast filter table array address and new table value. See igb_mta_set_generic()
Definition at line 385 of file igb_mac.c.
References DEBUGFUNC, e1000_hw::mac, e1000_mac_info::mc_filter_type, e1000_mac_info::mta_reg_count, u16, u32, and u8.
Referenced by igb_hash_mc_addr(), and igb_update_mc_addr_list_generic().
00386 { 00387 u32 hash_value, hash_mask; 00388 u8 bit_shift = 0; 00389 00390 DEBUGFUNC("igb_hash_mc_addr_generic"); 00391 00392 /* Register count multiplied by bits per register */ 00393 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 00394 00395 /* 00396 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 00397 * where 0xFF would still fall within the hash mask. 00398 */ 00399 while (hash_mask >> bit_shift != 0xFF) 00400 bit_shift++; 00401 00402 /* 00403 * The portion of the address that is used for the hash table 00404 * is determined by the mc_filter_type setting. 00405 * The algorithm is such that there is a total of 8 bits of shifting. 00406 * The bit_shift for a mc_filter_type of 0 represents the number of 00407 * left-shifts where the MSB of mc_addr[5] would still fall within 00408 * the hash_mask. Case 0 does this exactly. Since there are a total 00409 * of 8 bits of shifting, then mc_addr[4] will shift right the 00410 * remaining number of bits. Thus 8 - bit_shift. The rest of the 00411 * cases are a variation of this algorithm...essentially raising the 00412 * number of bits to shift mc_addr[5] left, while still keeping the 00413 * 8-bit shifting total. 00414 * 00415 * For example, given the following Destination MAC Address and an 00416 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 00417 * we can see that the bit_shift for case 0 is 4. These are the hash 00418 * values resulting from each mc_filter_type... 00419 * [0] [1] [2] [3] [4] [5] 00420 * 01 AA 00 12 34 56 00421 * LSB MSB 00422 * 00423 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 00424 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 00425 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 00426 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 00427 */ 00428 switch (hw->mac.mc_filter_type) { 00429 default: 00430 case 0: 00431 break; 00432 case 1: 00433 bit_shift += 1; 00434 break; 00435 case 2: 00436 bit_shift += 2; 00437 break; 00438 case 3: 00439 bit_shift += 4; 00440 break; 00441 } 00442 00443 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 00444 (((u16) mc_addr[5]) << bit_shift))); 00445 00446 return hash_value; 00447 }
| void igb_clear_hw_cntrs_base_generic | ( | struct e1000_hw * | hw | ) |
igb_clear_hw_cntrs_base_generic - Clear base hardware counters : pointer to the HW structure
Clears the base hardware counters by reading the counter registers.
Definition at line 455 of file igb_mac.c.
References DEBUGFUNC, E1000_BPRC, E1000_BPTC, E1000_COLC, E1000_CRCERRS, E1000_DC, E1000_ECOL, E1000_FCRUC, E1000_GORCH, E1000_GORCL, E1000_GOTCH, E1000_GOTCL, E1000_GPRC, E1000_GPTC, E1000_LATECOL, E1000_MCC, E1000_MPC, E1000_MPRC, E1000_MPTC, E1000_READ_REG, E1000_RFC, E1000_RJC, E1000_RLEC, E1000_RNBC, E1000_ROC, E1000_RUC, E1000_SCC, E1000_SEC, E1000_SYMERRS, E1000_TORH, E1000_TORL, E1000_TOTH, E1000_TOTL, E1000_TPR, E1000_TPT, E1000_XOFFRXC, E1000_XOFFTXC, E1000_XONRXC, and E1000_XONTXC.
Referenced by igb_clear_hw_cntrs_82575().
00456 { 00457 DEBUGFUNC("igb_clear_hw_cntrs_base_generic"); 00458 00459 E1000_READ_REG(hw, E1000_CRCERRS); 00460 E1000_READ_REG(hw, E1000_SYMERRS); 00461 E1000_READ_REG(hw, E1000_MPC); 00462 E1000_READ_REG(hw, E1000_SCC); 00463 E1000_READ_REG(hw, E1000_ECOL); 00464 E1000_READ_REG(hw, E1000_MCC); 00465 E1000_READ_REG(hw, E1000_LATECOL); 00466 E1000_READ_REG(hw, E1000_COLC); 00467 E1000_READ_REG(hw, E1000_DC); 00468 E1000_READ_REG(hw, E1000_SEC); 00469 E1000_READ_REG(hw, E1000_RLEC); 00470 E1000_READ_REG(hw, E1000_XONRXC); 00471 E1000_READ_REG(hw, E1000_XONTXC); 00472 E1000_READ_REG(hw, E1000_XOFFRXC); 00473 E1000_READ_REG(hw, E1000_XOFFTXC); 00474 E1000_READ_REG(hw, E1000_FCRUC); 00475 E1000_READ_REG(hw, E1000_GPRC); 00476 E1000_READ_REG(hw, E1000_BPRC); 00477 E1000_READ_REG(hw, E1000_MPRC); 00478 E1000_READ_REG(hw, E1000_GPTC); 00479 E1000_READ_REG(hw, E1000_GORCL); 00480 E1000_READ_REG(hw, E1000_GORCH); 00481 E1000_READ_REG(hw, E1000_GOTCL); 00482 E1000_READ_REG(hw, E1000_GOTCH); 00483 E1000_READ_REG(hw, E1000_RNBC); 00484 E1000_READ_REG(hw, E1000_RUC); 00485 E1000_READ_REG(hw, E1000_RFC); 00486 E1000_READ_REG(hw, E1000_ROC); 00487 E1000_READ_REG(hw, E1000_RJC); 00488 E1000_READ_REG(hw, E1000_TORL); 00489 E1000_READ_REG(hw, E1000_TORH); 00490 E1000_READ_REG(hw, E1000_TOTL); 00491 E1000_READ_REG(hw, E1000_TOTH); 00492 E1000_READ_REG(hw, E1000_TPR); 00493 E1000_READ_REG(hw, E1000_TPT); 00494 E1000_READ_REG(hw, E1000_MPTC); 00495 E1000_READ_REG(hw, E1000_BPTC); 00496 }
igb_check_for_copper_link_generic - Check for link (Copper) : pointer to the HW structure
Checks to see of the link status of the hardware has changed. If a change in link status has been detected, then we read the PHY registers to get the current speed/duplex if link exists.
Definition at line 506 of file igb_mac.c.
References e1000_mac_info::autoneg, DEBUGFUNC, DEBUGOUT, E1000_ERR_CONFIG, E1000_SUCCESS, e1000_mac_info::get_link_status, igb_check_downshift_generic(), igb_config_collision_dist_generic(), igb_config_fc_after_link_up_generic(), igb_phy_has_link_generic(), and e1000_hw::mac.
Referenced by igb_check_for_link_82575().
00507 { 00508 struct e1000_mac_info *mac = &hw->mac; 00509 s32 ret_val; 00510 bool link; 00511 00512 DEBUGFUNC("igb_check_for_copper_link"); 00513 00514 /* 00515 * We only want to go out to the PHY registers to see if Auto-Neg 00516 * has completed and/or if our link status has changed. The 00517 * get_link_status flag is set upon receiving a Link Status 00518 * Change or Rx Sequence Error interrupt. 00519 */ 00520 if (!mac->get_link_status) { 00521 ret_val = E1000_SUCCESS; 00522 goto out; 00523 } 00524 00525 /* 00526 * First we want to see if the MII Status Register reports 00527 * link. If so, then we want to get the current speed/duplex 00528 * of the PHY. 00529 */ 00530 ret_val = igb_phy_has_link_generic(hw, 1, 0, &link); 00531 if (ret_val) 00532 goto out; 00533 00534 if (!link) 00535 goto out; /* No link detected */ 00536 00537 mac->get_link_status = false; 00538 00539 /* 00540 * Check if there was DownShift, must be checked 00541 * immediately after link-up 00542 */ 00543 igb_check_downshift_generic(hw); 00544 00545 /* 00546 * If we are forcing speed/duplex, then we simply return since 00547 * we have already determined whether we have link or not. 00548 */ 00549 if (!mac->autoneg) { 00550 ret_val = -E1000_ERR_CONFIG; 00551 goto out; 00552 } 00553 00554 /* 00555 * Auto-Neg is enabled. Auto Speed Detection takes care 00556 * of MAC speed/duplex configuration. So we only need to 00557 * configure Collision Distance in the MAC. 00558 */ 00559 igb_config_collision_dist_generic(hw); 00560 00561 /* 00562 * Configure Flow Control now that Auto-Neg has completed. 00563 * First, we need to restore the desired flow control 00564 * settings because we may have had to re-autoneg with a 00565 * different link partner. 00566 */ 00567 ret_val = igb_config_fc_after_link_up_generic(hw); 00568 if (ret_val) { 00569 DEBUGOUT("Error configuring flow control\n"); 00570 } 00571 out: 00572 return ret_val; 00573 }
igb_check_for_fiber_link_generic - Check for link (Fiber) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 582 of file igb_mac.c.
References e1000_mac_info::autoneg_failed, DEBUGFUNC, DEBUGOUT, E1000_CTRL, E1000_CTRL_FD, E1000_CTRL_SLU, E1000_CTRL_SWDPIN1, E1000_READ_REG, E1000_RXCW, E1000_RXCW_C, E1000_STATUS, E1000_STATUS_LU, E1000_SUCCESS, E1000_TXCW, E1000_TXCW_ANE, E1000_WRITE_REG, igb_config_fc_after_link_up_generic(), e1000_hw::mac, e1000_mac_info::serdes_has_link, e1000_mac_info::txcw, and u32.
00583 { 00584 struct e1000_mac_info *mac = &hw->mac; 00585 u32 rxcw; 00586 u32 ctrl; 00587 u32 status; 00588 s32 ret_val = E1000_SUCCESS; 00589 00590 DEBUGFUNC("igb_check_for_fiber_link_generic"); 00591 00592 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00593 status = E1000_READ_REG(hw, E1000_STATUS); 00594 rxcw = E1000_READ_REG(hw, E1000_RXCW); 00595 00596 /* 00597 * If we don't have link (auto-negotiation failed or link partner 00598 * cannot auto-negotiate), the cable is plugged in (we have signal), 00599 * and our link partner is not trying to auto-negotiate with us (we 00600 * are receiving idles or data), we need to force link up. We also 00601 * need to give auto-negotiation time to complete, in case the cable 00602 * was just plugged in. The autoneg_failed flag does this. 00603 */ 00604 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 00605 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 00606 (!(rxcw & E1000_RXCW_C))) { 00607 if (mac->autoneg_failed == 0) { 00608 mac->autoneg_failed = 1; 00609 goto out; 00610 } 00611 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 00612 00613 /* Disable auto-negotiation in the TXCW register */ 00614 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 00615 00616 /* Force link-up and also force full-duplex. */ 00617 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00618 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 00619 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 00620 00621 /* Configure Flow Control after forcing link up. */ 00622 ret_val = igb_config_fc_after_link_up_generic(hw); 00623 if (ret_val) { 00624 DEBUGOUT("Error configuring flow control\n"); 00625 goto out; 00626 } 00627 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 00628 /* 00629 * If we are forcing link and we are receiving /C/ ordered 00630 * sets, re-enable auto-negotiation in the TXCW register 00631 * and disable forced link in the Device Control register 00632 * in an attempt to auto-negotiate with our link partner. 00633 */ 00634 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 00635 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 00636 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 00637 00638 mac->serdes_has_link = true; 00639 } 00640 00641 out: 00642 return ret_val; 00643 }
igb_check_for_serdes_link_generic - Check for link (Serdes) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 652 of file igb_mac.c.
References e1000_mac_info::autoneg_failed, DEBUGFUNC, DEBUGOUT, E1000_CTRL, E1000_CTRL_FD, E1000_CTRL_SLU, E1000_READ_REG, E1000_RXCW, E1000_RXCW_C, E1000_RXCW_IV, E1000_RXCW_SYNCH, E1000_STATUS, E1000_STATUS_LU, E1000_SUCCESS, E1000_TXCW, E1000_TXCW_ANE, E1000_WRITE_REG, igb_config_fc_after_link_up_generic(), e1000_hw::mac, e1000_mac_info::serdes_has_link, e1000_mac_info::txcw, u32, and usec_delay.
00653 { 00654 struct e1000_mac_info *mac = &hw->mac; 00655 u32 rxcw; 00656 u32 ctrl; 00657 u32 status; 00658 s32 ret_val = E1000_SUCCESS; 00659 00660 DEBUGFUNC("igb_check_for_serdes_link_generic"); 00661 00662 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00663 status = E1000_READ_REG(hw, E1000_STATUS); 00664 rxcw = E1000_READ_REG(hw, E1000_RXCW); 00665 00666 /* 00667 * If we don't have link (auto-negotiation failed or link partner 00668 * cannot auto-negotiate), and our link partner is not trying to 00669 * auto-negotiate with us (we are receiving idles or data), 00670 * we need to force link up. We also need to give auto-negotiation 00671 * time to complete. 00672 */ 00673 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 00674 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 00675 if (mac->autoneg_failed == 0) { 00676 mac->autoneg_failed = 1; 00677 goto out; 00678 } 00679 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 00680 00681 /* Disable auto-negotiation in the TXCW register */ 00682 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 00683 00684 /* Force link-up and also force full-duplex. */ 00685 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00686 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 00687 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 00688 00689 /* Configure Flow Control after forcing link up. */ 00690 ret_val = igb_config_fc_after_link_up_generic(hw); 00691 if (ret_val) { 00692 DEBUGOUT("Error configuring flow control\n"); 00693 goto out; 00694 } 00695 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 00696 /* 00697 * If we are forcing link and we are receiving /C/ ordered 00698 * sets, re-enable auto-negotiation in the TXCW register 00699 * and disable forced link in the Device Control register 00700 * in an attempt to auto-negotiate with our link partner. 00701 */ 00702 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 00703 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 00704 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 00705 00706 mac->serdes_has_link = true; 00707 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 00708 /* 00709 * If we force link for non-auto-negotiation switch, check 00710 * link status based on MAC synchronization for internal 00711 * serdes media type. 00712 */ 00713 /* SYNCH bit and IV bit are sticky. */ 00714 usec_delay(10); 00715 rxcw = E1000_READ_REG(hw, E1000_RXCW); 00716 if (rxcw & E1000_RXCW_SYNCH) { 00717 if (!(rxcw & E1000_RXCW_IV)) { 00718 mac->serdes_has_link = true; 00719 DEBUGOUT("SERDES: Link up - forced.\n"); 00720 } 00721 } else { 00722 mac->serdes_has_link = false; 00723 DEBUGOUT("SERDES: Link down - force failed.\n"); 00724 } 00725 } 00726 00727 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 00728 status = E1000_READ_REG(hw, E1000_STATUS); 00729 if (status & E1000_STATUS_LU) { 00730 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 00731 usec_delay(10); 00732 rxcw = E1000_READ_REG(hw, E1000_RXCW); 00733 if (rxcw & E1000_RXCW_SYNCH) { 00734 if (!(rxcw & E1000_RXCW_IV)) { 00735 mac->serdes_has_link = true; 00736 DEBUGOUT("SERDES: Link up - autoneg " 00737 "completed sucessfully.\n"); 00738 } else { 00739 mac->serdes_has_link = false; 00740 DEBUGOUT("SERDES: Link down - invalid" 00741 "codewords detected in autoneg.\n"); 00742 } 00743 } else { 00744 mac->serdes_has_link = false; 00745 DEBUGOUT("SERDES: Link down - no sync.\n"); 00746 } 00747 } else { 00748 mac->serdes_has_link = false; 00749 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 00750 } 00751 } 00752 00753 out: 00754 return ret_val; 00755 }
igb_setup_link_generic - Setup flow control and link settings : pointer to the HW structure
Determines which flow control settings to use, then configures flow control. Calls the appropriate media-specific link configuration function. Assuming the adapter has a valid link partner, a valid link should be established. Assumes the hardware has previously been reset and the transmitter and receiver are not enabled.
Definition at line 767 of file igb_mac.c.
References e1000_phy_operations::check_reset_block, e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, DEBUGOUT1, e1000_fc_default, E1000_FCAH, E1000_FCAL, E1000_FCT, E1000_FCTTV, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::fc, FLOW_CONTROL_ADDRESS_HIGH, FLOW_CONTROL_ADDRESS_LOW, FLOW_CONTROL_TYPE, igb_set_default_fc_generic(), igb_set_fc_watermarks_generic(), e1000_hw::mac, e1000_mac_info::ops, e1000_phy_info::ops, e1000_fc_info::pause_time, e1000_hw::phy, e1000_fc_info::requested_mode, and e1000_mac_operations::setup_physical_interface.
Referenced by igb_init_mac_params_82575().
00768 { 00769 s32 ret_val = E1000_SUCCESS; 00770 00771 DEBUGFUNC("igb_setup_link_generic"); 00772 00773 /* 00774 * In the case of the phy reset being blocked, we already have a link. 00775 * We do not need to set it up again. 00776 */ 00777 if (hw->phy.ops.check_reset_block) 00778 if (hw->phy.ops.check_reset_block(hw)) 00779 goto out; 00780 00781 /* 00782 * If requested flow control is set to default, set flow control 00783 * based on the EEPROM flow control settings. 00784 */ 00785 if (hw->fc.requested_mode == e1000_fc_default) { 00786 ret_val = igb_set_default_fc_generic(hw); 00787 if (ret_val) 00788 goto out; 00789 } 00790 00791 /* 00792 * Save off the requested flow control mode for use later. Depending 00793 * on the link partner's capabilities, we may or may not use this mode. 00794 */ 00795 hw->fc.current_mode = hw->fc.requested_mode; 00796 00797 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 00798 hw->fc.current_mode); 00799 00800 /* Call the necessary media_type subroutine to configure the link. */ 00801 ret_val = hw->mac.ops.setup_physical_interface(hw); 00802 if (ret_val) 00803 goto out; 00804 00805 /* 00806 * Initialize the flow control address, type, and PAUSE timer 00807 * registers to their default values. This is done even if flow 00808 * control is disabled, because it does not hurt anything to 00809 * initialize these registers. 00810 */ 00811 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 00812 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 00813 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 00814 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 00815 00816 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 00817 00818 ret_val = igb_set_fc_watermarks_generic(hw); 00819 00820 out: 00821 return ret_val; 00822 }
igb_setup_fiber_serdes_link_generic - Setup link for fiber/serdes : pointer to the HW structure
Configures collision distance and flow control for fiber and serdes links. Upon successful setup, poll for link.
Definition at line 831 of file igb_mac.c.
References DEBUGFUNC, DEBUGOUT, E1000_CTRL, E1000_CTRL_LRST, E1000_CTRL_SWDPIN1, e1000_media_type_internal_serdes, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_FLUSH, E1000_WRITE_REG, igb_commit_fc_settings_generic(), igb_config_collision_dist_generic(), igb_poll_fiber_serdes_link_generic(), e1000_phy_info::media_type, msec_delay, e1000_hw::phy, and u32.
00832 { 00833 u32 ctrl; 00834 s32 ret_val = E1000_SUCCESS; 00835 00836 DEBUGFUNC("igb_setup_fiber_serdes_link_generic"); 00837 00838 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00839 00840 /* Take the link out of reset */ 00841 ctrl &= ~E1000_CTRL_LRST; 00842 00843 igb_config_collision_dist_generic(hw); 00844 00845 ret_val = igb_commit_fc_settings_generic(hw); 00846 if (ret_val) 00847 goto out; 00848 00849 /* 00850 * Since auto-negotiation is enabled, take the link out of reset (the 00851 * link will be in reset, because we previously reset the chip). This 00852 * will restart auto-negotiation. If auto-negotiation is successful 00853 * then the link-up status bit will be set and the flow control enable 00854 * bits (RFCE and TFCE) will be set according to their negotiated value. 00855 */ 00856 DEBUGOUT("Auto-negotiation enabled\n"); 00857 00858 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 00859 E1000_WRITE_FLUSH(hw); 00860 msec_delay(1); 00861 00862 /* 00863 * For these adapters, the SW definable pin 1 is set when the optics 00864 * detect a signal. If we have a signal, then poll for a "Link-Up" 00865 * indication. 00866 */ 00867 if (hw->phy.media_type == e1000_media_type_internal_serdes || 00868 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 00869 ret_val = igb_poll_fiber_serdes_link_generic(hw); 00870 } else { 00871 DEBUGOUT("No signal detected\n"); 00872 } 00873 00874 out: 00875 return ret_val; 00876 }
| void igb_config_collision_dist_generic | ( | struct e1000_hw * | hw | ) |
igb_config_collision_dist_generic - Configure collision distance : pointer to the HW structure
Configures the collision distance to the default value and is used during link setup. Currently no func pointer exists and all implementations are handled in the generic version of this function.
Definition at line 886 of file igb_mac.c.
References DEBUGFUNC, E1000_COLD_SHIFT, E1000_COLLISION_DISTANCE, E1000_READ_REG, E1000_TCTL, E1000_TCTL_COLD, E1000_WRITE_FLUSH, E1000_WRITE_REG, and u32.
Referenced by igb_check_for_copper_link_generic(), igb_init_mac_ops_generic(), igb_setup_copper_link_generic(), and igb_setup_fiber_serdes_link_generic().
00887 { 00888 u32 tctl; 00889 00890 DEBUGFUNC("igb_config_collision_dist_generic"); 00891 00892 tctl = E1000_READ_REG(hw, E1000_TCTL); 00893 00894 tctl &= ~E1000_TCTL_COLD; 00895 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 00896 00897 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 00898 E1000_WRITE_FLUSH(hw); 00899 }
igb_set_fc_watermarks_generic - Set flow control high/low watermarks : pointer to the HW structure
Sets the flow control high/low threshold (watermark) registers. If flow control XON frame transmission is enabled, then set XON frame transmission as well.
Definition at line 1037 of file igb_mac.c.
References e1000_fc_info::current_mode, DEBUGFUNC, e1000_fc_tx_pause, E1000_FCRTH, E1000_FCRTL, E1000_FCRTL_XONE, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::fc, e1000_fc_info::high_water, e1000_fc_info::low_water, e1000_fc_info::send_xon, and u32.
Referenced by igb_setup_link_generic().
01038 { 01039 s32 ret_val = E1000_SUCCESS; 01040 u32 fcrtl = 0, fcrth = 0; 01041 01042 DEBUGFUNC("igb_set_fc_watermarks_generic"); 01043 01044 /* 01045 * Set the flow control receive threshold registers. Normally, 01046 * these registers will be set to a default threshold that may be 01047 * adjusted later by the driver's runtime code. However, if the 01048 * ability to transmit pause frames is not enabled, then these 01049 * registers will be set to 0. 01050 */ 01051 if (hw->fc.current_mode & e1000_fc_tx_pause) { 01052 /* 01053 * We need to set up the Receive Threshold high and low water 01054 * marks as well as (optionally) enabling the transmission of 01055 * XON frames. 01056 */ 01057 fcrtl = hw->fc.low_water; 01058 if (hw->fc.send_xon) 01059 fcrtl |= E1000_FCRTL_XONE; 01060 01061 fcrth = hw->fc.high_water; 01062 } 01063 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 01064 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 01065 01066 return ret_val; 01067 }
igb_force_mac_fc_generic - Force the MAC's flow control settings : pointer to the HW structure
Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the device control register to reflect the adapter settings. TFCE and RFCE need to be explicitly set by software when a copper PHY is used because autonegotiation is managed by the PHY rather than the MAC. Software must also configure these bits when link is forced on a fiber connection.
Definition at line 1121 of file igb_mac.c.
References e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, DEBUGOUT1, E1000_CTRL, E1000_CTRL_RFCE, E1000_CTRL_TFCE, E1000_ERR_CONFIG, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::fc, and u32.
Referenced by igb_config_fc_after_link_up_generic(), igb_force_mac_fc(), and igb_setup_serdes_link_82575().
01122 { 01123 u32 ctrl; 01124 s32 ret_val = E1000_SUCCESS; 01125 01126 DEBUGFUNC("igb_force_mac_fc_generic"); 01127 01128 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01129 01130 /* 01131 * Because we didn't get link via the internal auto-negotiation 01132 * mechanism (we either forced link or we got link via PHY 01133 * auto-neg), we have to manually enable/disable transmit an 01134 * receive flow control. 01135 * 01136 * The "Case" statement below enables/disable flow control 01137 * according to the "hw->fc.current_mode" parameter. 01138 * 01139 * The possible values of the "fc" parameter are: 01140 * 0: Flow control is completely disabled 01141 * 1: Rx flow control is enabled (we can receive pause 01142 * frames but not send pause frames). 01143 * 2: Tx flow control is enabled (we can send pause frames 01144 * frames but we do not receive pause frames). 01145 * 3: Both Rx and Tx flow control (symmetric) is enabled. 01146 * other: No other values should be possible at this point. 01147 */ 01148 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 01149 01150 switch (hw->fc.current_mode) { 01151 case e1000_fc_none: 01152 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 01153 break; 01154 case e1000_fc_rx_pause: 01155 ctrl &= (~E1000_CTRL_TFCE); 01156 ctrl |= E1000_CTRL_RFCE; 01157 break; 01158 case e1000_fc_tx_pause: 01159 ctrl &= (~E1000_CTRL_RFCE); 01160 ctrl |= E1000_CTRL_TFCE; 01161 break; 01162 case e1000_fc_full: 01163 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 01164 break; 01165 default: 01166 DEBUGOUT("Flow control param set incorrectly\n"); 01167 ret_val = -E1000_ERR_CONFIG; 01168 goto out; 01169 } 01170 01171 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01172 01173 out: 01174 return ret_val; 01175 }
igb_config_fc_after_link_up_generic - Configures flow control after link : pointer to the HW structure
Checks the status of auto-negotiation after link up to ensure that the speed and duplex were not forced. If the link needed to be forced, then flow control needs to be forced also. If auto-negotiation is enabled and did not fail, then we configure flow control based on our link partner.
Definition at line 1187 of file igb_mac.c.
References e1000_mac_info::autoneg, e1000_mac_info::autoneg_failed, e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, e1000_media_type_copper, e1000_media_type_fiber, e1000_media_type_internal_serdes, E1000_SUCCESS, e1000_hw::fc, e1000_mac_operations::get_link_up_info, HALF_DUPLEX, igb_force_mac_fc_generic(), e1000_hw::mac, e1000_phy_info::media_type, MII_SR_AUTONEG_COMPLETE, NWAY_AR_ASM_DIR, NWAY_AR_PAUSE, NWAY_LPAR_ASM_DIR, NWAY_LPAR_PAUSE, e1000_mac_info::ops, e1000_phy_info::ops, e1000_hw::phy, PHY_AUTONEG_ADV, PHY_LP_ABILITY, PHY_STATUS, e1000_phy_operations::read_reg, e1000_fc_info::requested_mode, and u16.
Referenced by igb_check_for_copper_link_generic(), igb_check_for_fiber_link_generic(), igb_check_for_serdes_link_generic(), and igb_setup_copper_link_generic().
01188 { 01189 struct e1000_mac_info *mac = &hw->mac; 01190 s32 ret_val = E1000_SUCCESS; 01191 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 01192 u16 speed, duplex; 01193 01194 DEBUGFUNC("igb_config_fc_after_link_up_generic"); 01195 01196 /* 01197 * Check for the case where we have fiber media and auto-neg failed 01198 * so we had to force link. In this case, we need to force the 01199 * configuration of the MAC to match the "fc" parameter. 01200 */ 01201 if (mac->autoneg_failed) { 01202 if (hw->phy.media_type == e1000_media_type_fiber || 01203 hw->phy.media_type == e1000_media_type_internal_serdes) 01204 ret_val = igb_force_mac_fc_generic(hw); 01205 } else { 01206 if (hw->phy.media_type == e1000_media_type_copper) 01207 ret_val = igb_force_mac_fc_generic(hw); 01208 } 01209 01210 if (ret_val) { 01211 DEBUGOUT("Error forcing flow control settings\n"); 01212 goto out; 01213 } 01214 01215 /* 01216 * Check for the case where we have copper media and auto-neg is 01217 * enabled. In this case, we need to check and see if Auto-Neg 01218 * has completed, and if so, how the PHY and link partner has 01219 * flow control configured. 01220 */ 01221 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 01222 /* 01223 * Read the MII Status Register and check to see if AutoNeg 01224 * has completed. We read this twice because this reg has 01225 * some "sticky" (latched) bits. 01226 */ 01227 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 01228 if (ret_val) 01229 goto out; 01230 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 01231 if (ret_val) 01232 goto out; 01233 01234 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 01235 DEBUGOUT("Copper PHY and Auto Neg " 01236 "has not completed.\n"); 01237 goto out; 01238 } 01239 01240 /* 01241 * The AutoNeg process has completed, so we now need to 01242 * read both the Auto Negotiation Advertisement 01243 * Register (Address 4) and the Auto_Negotiation Base 01244 * Page Ability Register (Address 5) to determine how 01245 * flow control was negotiated. 01246 */ 01247 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 01248 &mii_nway_adv_reg); 01249 if (ret_val) 01250 goto out; 01251 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 01252 &mii_nway_lp_ability_reg); 01253 if (ret_val) 01254 goto out; 01255 01256 /* 01257 * Two bits in the Auto Negotiation Advertisement Register 01258 * (Address 4) and two bits in the Auto Negotiation Base 01259 * Page Ability Register (Address 5) determine flow control 01260 * for both the PHY and the link partner. The following 01261 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 01262 * 1999, describes these PAUSE resolution bits and how flow 01263 * control is determined based upon these settings. 01264 * NOTE: DC = Don't Care 01265 * 01266 * LOCAL DEVICE | LINK PARTNER 01267 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 01268 *-------|---------|-------|---------|-------------------- 01269 * 0 | 0 | DC | DC | e1000_fc_none 01270 * 0 | 1 | 0 | DC | e1000_fc_none 01271 * 0 | 1 | 1 | 0 | e1000_fc_none 01272 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 01273 * 1 | 0 | 0 | DC | e1000_fc_none 01274 * 1 | DC | 1 | DC | e1000_fc_full 01275 * 1 | 1 | 0 | 0 | e1000_fc_none 01276 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 01277 * 01278 * Are both PAUSE bits set to 1? If so, this implies 01279 * Symmetric Flow Control is enabled at both ends. The 01280 * ASM_DIR bits are irrelevant per the spec. 01281 * 01282 * For Symmetric Flow Control: 01283 * 01284 * LOCAL DEVICE | LINK PARTNER 01285 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01286 *-------|---------|-------|---------|-------------------- 01287 * 1 | DC | 1 | DC | E1000_fc_full 01288 * 01289 */ 01290 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 01291 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 01292 /* 01293 * Now we need to check if the user selected Rx ONLY 01294 * of pause frames. In this case, we had to advertise 01295 * FULL flow control because we could not advertise RX 01296 * ONLY. Hence, we must now check to see if we need to 01297 * turn OFF the TRANSMISSION of PAUSE frames. 01298 */ 01299 if (hw->fc.requested_mode == e1000_fc_full) { 01300 hw->fc.current_mode = e1000_fc_full; 01301 DEBUGOUT("Flow Control = FULL.\r\n"); 01302 } else { 01303 hw->fc.current_mode = e1000_fc_rx_pause; 01304 DEBUGOUT("Flow Control = " 01305 "RX PAUSE frames only.\r\n"); 01306 } 01307 } 01308 /* 01309 * For receiving PAUSE frames ONLY. 01310 * 01311 * LOCAL DEVICE | LINK PARTNER 01312 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01313 *-------|---------|-------|---------|-------------------- 01314 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 01315 */ 01316 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 01317 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 01318 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 01319 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 01320 hw->fc.current_mode = e1000_fc_tx_pause; 01321 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 01322 } 01323 /* 01324 * For transmitting PAUSE frames ONLY. 01325 * 01326 * LOCAL DEVICE | LINK PARTNER 01327 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01328 *-------|---------|-------|---------|-------------------- 01329 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 01330 */ 01331 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 01332 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 01333 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 01334 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 01335 hw->fc.current_mode = e1000_fc_rx_pause; 01336 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 01337 } else { 01338 /* 01339 * Per the IEEE spec, at this point flow control 01340 * should be disabled. 01341 */ 01342 hw->fc.current_mode = e1000_fc_none; 01343 DEBUGOUT("Flow Control = NONE.\r\n"); 01344 } 01345 01346 /* 01347 * Now we need to do one last check... If we auto- 01348 * negotiated to HALF DUPLEX, flow control should not be 01349 * enabled per IEEE 802.3 spec. 01350 */ 01351 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 01352 if (ret_val) { 01353 DEBUGOUT("Error getting link speed and duplex\n"); 01354 goto out; 01355 } 01356 01357 if (duplex == HALF_DUPLEX) 01358 hw->fc.current_mode = e1000_fc_none; 01359 01360 /* 01361 * Now we call a subroutine to actually force the MAC 01362 * controller to use the correct flow control settings. 01363 */ 01364 ret_val = igb_force_mac_fc_generic(hw); 01365 if (ret_val) { 01366 DEBUGOUT("Error forcing flow control settings\n"); 01367 goto out; 01368 } 01369 } 01370 01371 out: 01372 return ret_val; 01373 }
igb_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex
Read the status register for the current speed/duplex and store the current speed and duplex for copper connections.
Definition at line 1384 of file igb_mac.c.
References DEBUGFUNC, DEBUGOUT, E1000_READ_REG, E1000_STATUS, E1000_STATUS_FD, E1000_STATUS_SPEED_100, E1000_STATUS_SPEED_1000, E1000_SUCCESS, FULL_DUPLEX, HALF_DUPLEX, SPEED_10, SPEED_100, SPEED_1000, and u32.
Referenced by igb_get_link_up_info_82575().
01386 { 01387 u32 status; 01388 01389 DEBUGFUNC("igb_get_speed_and_duplex_copper_generic"); 01390 01391 status = E1000_READ_REG(hw, E1000_STATUS); 01392 if (status & E1000_STATUS_SPEED_1000) { 01393 *speed = SPEED_1000; 01394 DEBUGOUT("1000 Mbs, "); 01395 } else if (status & E1000_STATUS_SPEED_100) { 01396 *speed = SPEED_100; 01397 DEBUGOUT("100 Mbs, "); 01398 } else { 01399 *speed = SPEED_10; 01400 DEBUGOUT("10 Mbs, "); 01401 } 01402 01403 if (status & E1000_STATUS_FD) { 01404 *duplex = FULL_DUPLEX; 01405 DEBUGOUT("Full Duplex\n"); 01406 } else { 01407 *duplex = HALF_DUPLEX; 01408 DEBUGOUT("Half Duplex\n"); 01409 } 01410 01411 return E1000_SUCCESS; 01412 }
| s32 igb_get_speed_and_duplex_fiber_serdes_generic | ( | struct e1000_hw *hw | __unused, | |
| u16 * | speed, | |||
| u16 * | duplex | |||
| ) |
igb_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex
Sets the speed and duplex to gigabit full duplex (the only possible option) for fiber/serdes links.
Definition at line 1423 of file igb_mac.c.
References DEBUGFUNC, E1000_SUCCESS, FULL_DUPLEX, and SPEED_1000.
01425 { 01426 DEBUGFUNC("igb_get_speed_and_duplex_fiber_serdes_generic"); 01427 01428 *speed = SPEED_1000; 01429 *duplex = FULL_DUPLEX; 01430 01431 return E1000_SUCCESS; 01432 }
igb_get_hw_semaphore_generic - Acquire hardware semaphore : pointer to the HW structure
Acquire the HW semaphore to access the PHY or NVM
Definition at line 1440 of file igb_mac.c.
References DEBUGFUNC, DEBUGOUT, E1000_ERR_NVM, E1000_READ_REG, E1000_SUCCESS, E1000_SWSM, E1000_SWSM_SMBI, E1000_SWSM_SWESMBI, E1000_WRITE_REG, igb_put_hw_semaphore_generic(), e1000_hw::nvm, timeout(), u32, usec_delay, and e1000_nvm_info::word_size.
Referenced by igb_acquire_swfw_sync_82575(), and igb_release_swfw_sync_82575().
01441 { 01442 u32 swsm; 01443 s32 ret_val = E1000_SUCCESS; 01444 s32 timeout = hw->nvm.word_size + 1; 01445 s32 i = 0; 01446 01447 DEBUGFUNC("igb_get_hw_semaphore_generic"); 01448 01449 /* Get the SW semaphore */ 01450 while (i < timeout) { 01451 swsm = E1000_READ_REG(hw, E1000_SWSM); 01452 if (!(swsm & E1000_SWSM_SMBI)) 01453 break; 01454 01455 usec_delay(50); 01456 i++; 01457 } 01458 01459 if (i == timeout) { 01460 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 01461 ret_val = -E1000_ERR_NVM; 01462 goto out; 01463 } 01464 01465 /* Get the FW semaphore. */ 01466 for (i = 0; i < timeout; i++) { 01467 swsm = E1000_READ_REG(hw, E1000_SWSM); 01468 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 01469 01470 /* Semaphore acquired if bit latched */ 01471 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 01472 break; 01473 01474 usec_delay(50); 01475 } 01476 01477 if (i == timeout) { 01478 /* Release semaphores */ 01479 igb_put_hw_semaphore_generic(hw); 01480 DEBUGOUT("Driver can't access the NVM\n"); 01481 ret_val = -E1000_ERR_NVM; 01482 goto out; 01483 } 01484 01485 out: 01486 return ret_val; 01487 }
| void igb_put_hw_semaphore_generic | ( | struct e1000_hw * | hw | ) |
igb_put_hw_semaphore_generic - Release hardware semaphore : pointer to the HW structure
Release hardware semaphore used to access the PHY or NVM
Definition at line 1495 of file igb_mac.c.
References DEBUGFUNC, E1000_READ_REG, E1000_SWSM, E1000_SWSM_SMBI, E1000_SWSM_SWESMBI, E1000_WRITE_REG, and u32.
Referenced by igb_acquire_swfw_sync_82575(), igb_get_hw_semaphore_generic(), and igb_release_swfw_sync_82575().
01496 { 01497 u32 swsm; 01498 01499 DEBUGFUNC("igb_put_hw_semaphore_generic"); 01500 01501 swsm = E1000_READ_REG(hw, E1000_SWSM); 01502 01503 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 01504 01505 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 01506 }
igb_get_auto_rd_done_generic - Check for auto read completion : pointer to the HW structure
Check EEPROM for Auto Read done bit.
Definition at line 1514 of file igb_mac.c.
References AUTO_READ_DONE_TIMEOUT, DEBUGFUNC, DEBUGOUT, E1000_EECD, E1000_EECD_AUTO_RD, E1000_ERR_RESET, E1000_READ_REG, E1000_SUCCESS, and msec_delay.
Referenced by igb_reset_hw_82575().
01515 { 01516 s32 i = 0; 01517 s32 ret_val = E1000_SUCCESS; 01518 01519 DEBUGFUNC("igb_get_auto_rd_done_generic"); 01520 01521 while (i < AUTO_READ_DONE_TIMEOUT) { 01522 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 01523 break; 01524 msec_delay(1); 01525 i++; 01526 } 01527 01528 if (i == AUTO_READ_DONE_TIMEOUT) { 01529 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 01530 ret_val = -E1000_ERR_RESET; 01531 goto out; 01532 } 01533 01534 out: 01535 return ret_val; 01536 }
igb_valid_led_default_generic - Verify a valid default LED config : pointer to the HW structure : pointer to the NVM (EEPROM)
Read the EEPROM for the current default LED configuration. If the LED configuration is not valid, set to a valid LED configuration.
Definition at line 1546 of file igb_mac.c.
References DEBUGFUNC, DEBUGOUT, ID_LED_DEFAULT, ID_LED_RESERVED_0000, ID_LED_RESERVED_FFFF, e1000_hw::nvm, NVM_ID_LED_SETTINGS, e1000_nvm_info::ops, and e1000_nvm_operations::read.
01547 { 01548 s32 ret_val; 01549 01550 DEBUGFUNC("igb_valid_led_default_generic"); 01551 01552 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 01553 if (ret_val) { 01554 DEBUGOUT("NVM Read Error\n"); 01555 goto out; 01556 } 01557 01558 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 01559 *data = ID_LED_DEFAULT; 01560 01561 out: 01562 return ret_val; 01563 }
e1000_id_led_init_generic - : pointer to the HW structure
Definition at line 1570 of file igb_mac.c.
References DEBUGFUNC, E1000_LEDCTL, E1000_LEDCTL_MODE_LED_OFF, E1000_LEDCTL_MODE_LED_ON, E1000_READ_REG, ID_LED_DEF1_OFF2, ID_LED_DEF1_ON2, ID_LED_OFF1_DEF2, ID_LED_OFF1_OFF2, ID_LED_OFF1_ON2, ID_LED_ON1_DEF2, ID_LED_ON1_OFF2, ID_LED_ON1_ON2, e1000_mac_info::ledctl_default, e1000_mac_info::ledctl_mode1, e1000_mac_info::ledctl_mode2, e1000_hw::mac, e1000_hw::nvm, e1000_nvm_info::ops, u16, u32, and e1000_nvm_operations::valid_led_default.
Referenced by igb_init_mac_params_82575().
01571 { 01572 struct e1000_mac_info *mac = &hw->mac; 01573 s32 ret_val; 01574 const u32 ledctl_mask = 0x000000FF; 01575 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 01576 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 01577 u16 data, i, temp; 01578 const u16 led_mask = 0x0F; 01579 01580 DEBUGFUNC("igb_id_led_init_generic"); 01581 01582 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 01583 if (ret_val) 01584 goto out; 01585 01586 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 01587 mac->ledctl_mode1 = mac->ledctl_default; 01588 mac->ledctl_mode2 = mac->ledctl_default; 01589 01590 for (i = 0; i < 4; i++) { 01591 temp = (data >> (i << 2)) & led_mask; 01592 switch (temp) { 01593 case ID_LED_ON1_DEF2: 01594 case ID_LED_ON1_ON2: 01595 case ID_LED_ON1_OFF2: 01596 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 01597 mac->ledctl_mode1 |= ledctl_on << (i << 3); 01598 break; 01599 case ID_LED_OFF1_DEF2: 01600 case ID_LED_OFF1_ON2: 01601 case ID_LED_OFF1_OFF2: 01602 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 01603 mac->ledctl_mode1 |= ledctl_off << (i << 3); 01604 break; 01605 default: 01606 /* Do nothing */ 01607 break; 01608 } 01609 switch (temp) { 01610 case ID_LED_DEF1_ON2: 01611 case ID_LED_ON1_ON2: 01612 case ID_LED_OFF1_ON2: 01613 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 01614 mac->ledctl_mode2 |= ledctl_on << (i << 3); 01615 break; 01616 case ID_LED_DEF1_OFF2: 01617 case ID_LED_ON1_OFF2: 01618 case ID_LED_OFF1_OFF2: 01619 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 01620 mac->ledctl_mode2 |= ledctl_off << (i << 3); 01621 break; 01622 default: 01623 /* Do nothing */ 01624 break; 01625 } 01626 } 01627 01628 out: 01629 return ret_val; 01630 }
igb_set_pcie_no_snoop_generic - Set PCI-express capabilities : pointer to the HW structure : bitmap of snoop events
Set the PCI-express register to snoop for events enabled in 'no_snoop'.
Definition at line 1795 of file igb_mac.c.
References e1000_hw::bus, DEBUGFUNC, e1000_bus_type_pci_express, E1000_GCR, E1000_READ_REG, E1000_WRITE_REG, PCIE_NO_SNOOP_ALL, e1000_bus_info::type, and u32.
01796 { 01797 u32 gcr; 01798 01799 DEBUGFUNC("igb_set_pcie_no_snoop_generic"); 01800 01801 if (hw->bus.type != e1000_bus_type_pci_express) 01802 goto out; 01803 01804 if (no_snoop) { 01805 gcr = E1000_READ_REG(hw, E1000_GCR); 01806 gcr &= ~(PCIE_NO_SNOOP_ALL); 01807 gcr |= no_snoop; 01808 E1000_WRITE_REG(hw, E1000_GCR, gcr); 01809 } 01810 out: 01811 return; 01812 }
igb_disable_pcie_master_generic - Disables PCI-express master access : pointer to the HW structure
Returns 0 (E1000_SUCCESS) if successful, else returns -10 (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused the master requests to be disabled.
Disables PCI-Express master access and verifies there are no pending requests.
Definition at line 1825 of file igb_mac.c.
References e1000_hw::bus, DEBUGFUNC, DEBUGOUT, e1000_bus_type_pci_express, E1000_CTRL, E1000_CTRL_GIO_MASTER_DISABLE, E1000_ERR_MASTER_REQUESTS_PENDING, E1000_READ_REG, E1000_STATUS, E1000_STATUS_GIO_MASTER_ENABLE, E1000_SUCCESS, E1000_WRITE_REG, MASTER_DISABLE_TIMEOUT, timeout(), e1000_bus_info::type, u32, and usec_delay.
Referenced by igb_disable_pcie_master(), and igb_reset_hw_82575().
01826 { 01827 u32 ctrl; 01828 s32 timeout = MASTER_DISABLE_TIMEOUT; 01829 s32 ret_val = E1000_SUCCESS; 01830 01831 DEBUGFUNC("igb_disable_pcie_master_generic"); 01832 01833 if (hw->bus.type != e1000_bus_type_pci_express) 01834 goto out; 01835 01836 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01837 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 01838 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01839 01840 while (timeout) { 01841 if (!(E1000_READ_REG(hw, E1000_STATUS) & 01842 E1000_STATUS_GIO_MASTER_ENABLE)) 01843 break; 01844 usec_delay(100); 01845 timeout--; 01846 } 01847 01848 if (!timeout) { 01849 DEBUGOUT("Master requests are pending.\n"); 01850 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 01851 goto out; 01852 } 01853 01854 out: 01855 return ret_val; 01856 }
| void igb_reset_adaptive_generic | ( | struct e1000_hw * | hw | ) |
igb_reset_adaptive_generic - Reset Adaptive Interframe Spacing : pointer to the HW structure
Reset the Adaptive Interframe Spacing throttle to default values.
Definition at line 1864 of file igb_mac.c.
References e1000_mac_info::adaptive_ifs, e1000_mac_info::current_ifs_val, DEBUGFUNC, DEBUGOUT, E1000_AIT, E1000_WRITE_REG, IFS_MAX, e1000_mac_info::ifs_max_val, IFS_MIN, e1000_mac_info::ifs_min_val, IFS_RATIO, e1000_mac_info::ifs_ratio, IFS_STEP, e1000_mac_info::ifs_step_size, e1000_mac_info::in_ifs_mode, and e1000_hw::mac.
Referenced by igb_reset_adaptive().
01865 { 01866 struct e1000_mac_info *mac = &hw->mac; 01867 01868 DEBUGFUNC("igb_reset_adaptive_generic"); 01869 01870 if (!mac->adaptive_ifs) { 01871 DEBUGOUT("Not in Adaptive IFS mode!\n"); 01872 goto out; 01873 } 01874 01875 mac->current_ifs_val = 0; 01876 mac->ifs_min_val = IFS_MIN; 01877 mac->ifs_max_val = IFS_MAX; 01878 mac->ifs_step_size = IFS_STEP; 01879 mac->ifs_ratio = IFS_RATIO; 01880 01881 mac->in_ifs_mode = false; 01882 E1000_WRITE_REG(hw, E1000_AIT, 0); 01883 out: 01884 return; 01885 }
| void igb_update_adaptive_generic | ( | struct e1000_hw * | hw | ) |
igb_update_adaptive_generic - Update Adaptive Interframe Spacing : pointer to the HW structure
Update the Adaptive Interframe Spacing Throttle value based on the time between transmitted packets and time between collisions.
Definition at line 1894 of file igb_mac.c.
References e1000_mac_info::adaptive_ifs, e1000_mac_info::collision_delta, e1000_mac_info::current_ifs_val, DEBUGFUNC, DEBUGOUT, E1000_AIT, E1000_WRITE_REG, e1000_mac_info::ifs_max_val, e1000_mac_info::ifs_min_val, e1000_mac_info::ifs_ratio, e1000_mac_info::ifs_step_size, e1000_mac_info::in_ifs_mode, e1000_hw::mac, MIN_NUM_XMITS, and e1000_mac_info::tx_packet_delta.
Referenced by igb_update_adaptive().
01895 { 01896 struct e1000_mac_info *mac = &hw->mac; 01897 01898 DEBUGFUNC("igb_update_adaptive_generic"); 01899 01900 if (!mac->adaptive_ifs) { 01901 DEBUGOUT("Not in Adaptive IFS mode!\n"); 01902 goto out; 01903 } 01904 01905 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 01906 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 01907 mac->in_ifs_mode = true; 01908 if (mac->current_ifs_val < mac->ifs_max_val) { 01909 if (!mac->current_ifs_val) 01910 mac->current_ifs_val = mac->ifs_min_val; 01911 else 01912 mac->current_ifs_val += 01913 mac->ifs_step_size; 01914 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 01915 } 01916 } 01917 } else { 01918 if (mac->in_ifs_mode && 01919 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 01920 mac->current_ifs_val = 0; 01921 mac->in_ifs_mode = false; 01922 E1000_WRITE_REG(hw, E1000_AIT, 0); 01923 } 01924 } 01925 out: 01926 return; 01927 }
igb_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register : pointer to the HW structure : 32bit register offset such as E1000_SCTL : register offset to write to : data to write at register offset
Writes an address/data control type register. There are several of these and they all have the format address << 8 | data and bit 31 is polled for completion.
Definition at line 1964 of file igb_mac.c.
References DEBUGFUNC, DEBUGOUT1, E1000_ERR_PHY, E1000_GEN_CTL_ADDRESS_SHIFT, E1000_GEN_CTL_READY, E1000_GEN_POLL_TIMEOUT, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, u32, and usec_delay.
Referenced by igb_reset_init_script_82575(), and igb_write_8bit_ctrl_reg().
01966 { 01967 u32 i, regvalue = 0; 01968 s32 ret_val = E1000_SUCCESS; 01969 01970 DEBUGFUNC("igb_write_8bit_ctrl_reg_generic"); 01971 01972 /* Set up the address and data */ 01973 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 01974 E1000_WRITE_REG(hw, reg, regvalue); 01975 01976 /* Poll the ready bit to see if the MDI read completed */ 01977 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 01978 usec_delay(5); 01979 regvalue = E1000_READ_REG(hw, reg); 01980 if (regvalue & E1000_GEN_CTL_READY) 01981 break; 01982 } 01983 if (!(regvalue & E1000_GEN_CTL_READY)) { 01984 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 01985 ret_val = -E1000_ERR_PHY; 01986 goto out; 01987 } 01988 01989 out: 01990 return ret_val; 01991 }
1.5.7.1