#include "igb_osdep.h"#include "igb_regs.h"#include "igb_defines.h"#include "igb_mac.h"#include "igb_phy.h"#include "igb_nvm.h"#include "igb_manage.h"#include "igb_82575.h"Go to the source code of this file.
| #define E1000_DEV_ID_82576 0x10C9 |
| #define E1000_DEV_ID_82576_FIBER 0x10E6 |
| #define E1000_DEV_ID_82576_SERDES 0x10E7 |
| #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 |
| #define E1000_DEV_ID_82576_NS 0x150A |
| #define E1000_DEV_ID_82576_NS_SERDES 0x1518 |
| #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D |
| #define E1000_DEV_ID_82575EB_COPPER 0x10A7 |
| #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 |
| #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 |
| enum e1000_mac_type |
Definition at line 61 of file igb_hw.h.
00061 { 00062 e1000_undefined = 0, 00063 e1000_82575, 00064 e1000_82576, 00065 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 00066 };
| enum e1000_media_type |
Definition at line 68 of file igb_hw.h.
00068 { 00069 e1000_media_type_unknown = 0, 00070 e1000_media_type_copper = 1, 00071 e1000_media_type_fiber = 2, 00072 e1000_media_type_internal_serdes = 3, 00073 e1000_num_media_types 00074 };
| enum e1000_nvm_type |
Definition at line 76 of file igb_hw.h.
00076 { 00077 e1000_nvm_unknown = 0, 00078 e1000_nvm_none, 00079 e1000_nvm_eeprom_spi, 00080 e1000_nvm_flash_hw, 00081 e1000_nvm_flash_sw 00082 };
| enum e1000_nvm_override |
Definition at line 84 of file igb_hw.h.
00084 { 00085 e1000_nvm_override_none = 0, 00086 e1000_nvm_override_spi_small, 00087 e1000_nvm_override_spi_large, 00088 };
| enum e1000_phy_type |
Definition at line 90 of file igb_hw.h.
00090 { 00091 e1000_phy_unknown = 0, 00092 e1000_phy_none, 00093 e1000_phy_m88, 00094 e1000_phy_igp, 00095 e1000_phy_igp_2, 00096 e1000_phy_gg82563, 00097 e1000_phy_igp_3, 00098 e1000_phy_ife, 00099 e1000_phy_vf, 00100 };
| enum e1000_bus_type |
Definition at line 102 of file igb_hw.h.
00102 { 00103 e1000_bus_type_unknown = 0, 00104 e1000_bus_type_pci, 00105 e1000_bus_type_pcix, 00106 e1000_bus_type_pci_express, 00107 e1000_bus_type_reserved 00108 };
| enum e1000_bus_speed |
Definition at line 110 of file igb_hw.h.
00110 { 00111 e1000_bus_speed_unknown = 0, 00112 e1000_bus_speed_33, 00113 e1000_bus_speed_66, 00114 e1000_bus_speed_100, 00115 e1000_bus_speed_120, 00116 e1000_bus_speed_133, 00117 e1000_bus_speed_2500, 00118 e1000_bus_speed_5000, 00119 e1000_bus_speed_reserved 00120 };
| enum e1000_bus_width |
Definition at line 122 of file igb_hw.h.
00122 { 00123 e1000_bus_width_unknown = 0, 00124 e1000_bus_width_pcie_x1, 00125 e1000_bus_width_pcie_x2, 00126 e1000_bus_width_pcie_x4 = 4, 00127 e1000_bus_width_pcie_x8 = 8, 00128 e1000_bus_width_32, 00129 e1000_bus_width_64, 00130 e1000_bus_width_reserved 00131 };
Definition at line 133 of file igb_hw.h.
00133 { 00134 e1000_1000t_rx_status_not_ok = 0, 00135 e1000_1000t_rx_status_ok, 00136 e1000_1000t_rx_status_undefined = 0xFF 00137 };
| enum e1000_rev_polarity |
Definition at line 139 of file igb_hw.h.
00139 { 00140 e1000_rev_polarity_normal = 0, 00141 e1000_rev_polarity_reversed, 00142 e1000_rev_polarity_undefined = 0xFF 00143 };
| enum e1000_fc_mode |
Definition at line 145 of file igb_hw.h.
00145 { 00146 e1000_fc_none = 0, 00147 e1000_fc_rx_pause, 00148 e1000_fc_tx_pause, 00149 e1000_fc_full, 00150 e1000_fc_default = 0xFF 00151 };
| enum e1000_ms_type |
Definition at line 153 of file igb_hw.h.
00153 { 00154 e1000_ms_hw_default = 0, 00155 e1000_ms_force_master, 00156 e1000_ms_force_slave, 00157 e1000_ms_auto 00158 };
| enum e1000_smart_speed |
Definition at line 160 of file igb_hw.h.
00160 { 00161 e1000_smart_speed_default = 0, 00162 e1000_smart_speed_on, 00163 e1000_smart_speed_off 00164 };
Definition at line 166 of file igb_hw.h.
00166 { 00167 e1000_serdes_link_down = 0, 00168 e1000_serdes_link_autoneg_progress, 00169 e1000_serdes_link_autoneg_complete, 00170 e1000_serdes_link_forced_up 00171 };
| FILE_LICENCE | ( | GPL2_ONLY | ) |
Referenced by igb_get_bus_info_pcie_generic(), and igb_set_pcie_completion_timeout().
igb_write_pcie_cap_reg - write value to PCIe capability register : address of board private structure : PCIe capability register to write to : value to store in given register
Definition at line 64 of file igb_main.c.
References e1000_hw::back, E1000_ERR_CONFIG, E1000_SUCCESS, PCI_CAP_ID_EXP, pci_find_capability(), pci_write_config_word(), igb_adapter::pdev, and u16.
Referenced by igb_set_pcie_completion_timeout().
00065 { 00066 struct igb_adapter *adapter = hw->back; 00067 u16 cap_offset; 00068 00069 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP); 00070 if (!cap_offset) 00071 return -E1000_ERR_CONFIG; 00072 00073 pci_write_config_word(adapter->pdev, cap_offset + reg, *value); 00074 00075 return E1000_SUCCESS; 00076 }
1.5.7.1