#include "igb.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_ONLY) | |
| static s32 | igb_init_phy_params_82575 (struct e1000_hw *hw) |
| igb_init_phy_params_82575 - Init PHY func ptrs. | |
| static s32 | igb_init_nvm_params_82575 (struct e1000_hw *hw) |
| igb_init_nvm_params_82575 - Init NVM func ptrs. | |
| static s32 | igb_init_mac_params_82575 (struct e1000_hw *hw) |
| igb_init_mac_params_82575 - Init MAC func ptrs. | |
| static s32 | igb_acquire_phy_82575 (struct e1000_hw *hw) |
| igb_acquire_phy_82575 - Acquire rights to access PHY : pointer to the HW structure | |
| static void | igb_release_phy_82575 (struct e1000_hw *hw) |
| igb_release_phy_82575 - Release rights to access PHY : pointer to the HW structure | |
| static s32 | igb_acquire_nvm_82575 (struct e1000_hw *hw) |
| igb_acquire_nvm_82575 - Request for access to EEPROM : pointer to the HW structure | |
| static void | igb_release_nvm_82575 (struct e1000_hw *hw) |
| igb_release_nvm_82575 - Release exclusive access to EEPROM : pointer to the HW structure | |
| static s32 | igb_check_for_link_82575 (struct e1000_hw *hw) |
| igb_check_for_link_82575 - Check for link : pointer to the HW structure | |
| static s32 | igb_get_cfg_done_82575 (struct e1000_hw *hw) |
| igb_get_cfg_done_82575 - Read config done bit : pointer to the HW structure | |
| static s32 | igb_get_link_up_info_82575 (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| igb_get_link_up_info_82575 - Get link speed/duplex info : pointer to the HW structure : stores the current speed : stores the current duplex | |
| static s32 | igb_init_hw_82575 (struct e1000_hw *hw) |
| igb_init_hw_82575 - Initialize hardware : pointer to the HW structure | |
| static s32 | igb_phy_hw_reset_sgmii_82575 (struct e1000_hw *hw) |
| igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset : pointer to the HW structure | |
| static s32 | igb_read_phy_reg_sgmii_82575 (struct e1000_hw *hw, u32 offset, u16 *data) |
| igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii : pointer to the HW structure : register offset to be read : pointer to the read data | |
| static s32 | igb_reset_hw_82575 (struct e1000_hw *hw) |
| igb_reset_hw_82575 - Reset hardware : pointer to the HW structure | |
| static s32 | igb_set_d0_lplu_state_82575 (struct e1000_hw *hw, bool active) |
| igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state : pointer to the HW structure : true to enable LPLU, false to disable | |
| static s32 | igb_setup_copper_link_82575 (struct e1000_hw *hw) |
| igb_setup_copper_link_82575 - Configure copper link settings : pointer to the HW structure | |
| static s32 | igb_setup_serdes_link_82575 (struct e1000_hw *hw) |
| igb_setup_serdes_link_82575 - Setup link for serdes : pointer to the HW structure | |
| static s32 | igb_valid_led_default_82575 (struct e1000_hw *hw, u16 *data) |
| igb_valid_led_default_82575 - Verify a valid default LED config : pointer to the HW structure : pointer to the NVM (EEPROM) | |
| static s32 | igb_write_phy_reg_sgmii_82575 (struct e1000_hw *hw, u32 offset, u16 data) |
| igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii : pointer to the HW structure : register offset to write to : data to write at register offset | |
| static void | igb_clear_hw_cntrs_82575 (struct e1000_hw *hw) |
| igb_clear_hw_cntrs_82575 - Clear device specific hardware counters : pointer to the HW structure | |
| static s32 | igb_acquire_swfw_sync_82575 (struct e1000_hw *hw, u16 mask) |
| igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore : pointer to the HW structure : specifies which semaphore to acquire | |
| static s32 | igb_get_pcs_speed_and_duplex_82575 (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex | |
| static s32 | igb_get_phy_id_82575 (struct e1000_hw *hw) |
| igb_get_phy_id_82575 - Retrieve PHY addr and id : pointer to the HW structure | |
| static void | igb_release_swfw_sync_82575 (struct e1000_hw *hw, u16 mask) |
| igb_release_swfw_sync_82575 - Release SW/FW semaphore : pointer to the HW structure : specifies which semaphore to acquire | |
| static bool | igb_sgmii_active_82575 (struct e1000_hw *hw) |
| igb_sgmii_active_82575 - Return sgmii state : pointer to the HW structure | |
| static s32 | igb_reset_init_script_82575 (struct e1000_hw *hw) |
| igb_reset_init_script_82575 - Inits HW defaults after reset : pointer to the HW structure | |
| static s32 | igb_read_mac_addr_82575 (struct e1000_hw *hw) |
| igb_read_mac_addr_82575 - Read device MAC address : pointer to the HW structure | |
| static void | igb_power_down_phy_copper_82575 (struct e1000_hw *hw) |
| igb_power_down_phy_copper_82575 - Remove link during PHY power down : pointer to the HW structure | |
| static void | igb_shutdown_serdes_link_82575 (struct e1000_hw *hw) |
| igb_shutdown_serdes_link_82575 - Remove link during power down : pointer to the HW structure | |
| static s32 | igb_set_pcie_completion_timeout (struct e1000_hw *hw) |
| igb_set_pcie_completion_timeout - set pci-e completion timeout : pointer to the HW structure | |
| void | igb_init_function_pointers_82575 (struct e1000_hw *hw) |
| igb_init_function_pointers_82575 - Init func ptrs. | |
| void | igb_rx_fifo_flush_82575 (struct e1000_hw *hw) |
| igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable : pointer to the HW structure | |
| void | igb_vmdq_set_loopback_pf (struct e1000_hw *hw, bool enable) |
| igb_vmdq_set_loopback_pf - enable or disable vmdq loopback : pointer to the hardware struct : state to enter, either enabled or disabled | |
| void | igb_vmdq_set_replication_pf (struct e1000_hw *hw, bool enable) |
| igb_vmdq_set_replication_pf - enable or disable vmdq replication : pointer to the hardware struct : state to enter, either enabled or disabled | |
Variables | |
| static struct pci_device_id | igb_82575_nics [] |
| struct pci_driver igb_82575_driver | __pci_driver |
| FILE_LICENCE | ( | GPL2_ONLY | ) |
igb_init_phy_params_82575 - Init PHY func ptrs.
: pointer to the HW structure
Definition at line 80 of file igb_82575.c.
References e1000_phy_operations::acquire, AUTONEG_ADVERTISE_SPEED_DEFAULT, e1000_phy_info::autoneg_mask, e1000_phy_operations::check_polarity, e1000_phy_operations::check_reset_block, e1000_phy_operations::commit, DEBUGFUNC, E1000_ERR_PHY, e1000_media_type_copper, e1000_phy_igp_3, e1000_phy_m88, e1000_phy_none, E1000_SUCCESS, e1000_phy_operations::get_cfg_done, e1000_phy_operations::get_info, e1000_phy_info::id, igb_acquire_phy_82575(), igb_check_polarity_igp(), igb_check_polarity_m88(), igb_check_reset_block_generic(), igb_get_cfg_done_82575(), igb_get_phy_id_82575(), igb_get_phy_info_igp(), igb_get_phy_info_m88(), igb_phy_hw_reset_generic(), igb_phy_hw_reset_sgmii_82575(), igb_phy_sw_reset_generic(), igb_power_down_phy_copper_82575(), igb_power_up_phy_copper(), igb_read_phy_reg_igp(), igb_read_phy_reg_sgmii_82575(), igb_release_phy_82575(), igb_set_d0_lplu_state_82575(), igb_set_d3_lplu_state_generic(), igb_sgmii_active_82575(), igb_write_phy_reg_igp(), igb_write_phy_reg_sgmii_82575(), IGP03E1000_E_PHY_ID, IGP04E1000_E_PHY_ID, M88E1111_I_PHY_ID, e1000_phy_info::media_type, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_down, e1000_phy_operations::power_up, e1000_phy_operations::read_reg, e1000_phy_operations::release, e1000_phy_operations::reset, e1000_phy_info::reset_delay_us, e1000_phy_operations::set_d0_lplu_state, e1000_phy_operations::set_d3_lplu_state, e1000_phy_info::type, and e1000_phy_operations::write_reg.
Referenced by igb_init_function_pointers_82575().
00081 { 00082 struct e1000_phy_info *phy = &hw->phy; 00083 s32 ret_val = E1000_SUCCESS; 00084 00085 DEBUGFUNC("igb_init_phy_params_82575"); 00086 00087 if (hw->phy.media_type != e1000_media_type_copper) { 00088 phy->type = e1000_phy_none; 00089 goto out; 00090 } 00091 00092 phy->ops.power_up = igb_power_up_phy_copper; 00093 phy->ops.power_down = igb_power_down_phy_copper_82575; 00094 00095 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 00096 phy->reset_delay_us = 100; 00097 00098 phy->ops.acquire = igb_acquire_phy_82575; 00099 phy->ops.check_reset_block = igb_check_reset_block_generic; 00100 phy->ops.commit = igb_phy_sw_reset_generic; 00101 phy->ops.get_cfg_done = igb_get_cfg_done_82575; 00102 phy->ops.release = igb_release_phy_82575; 00103 00104 if (igb_sgmii_active_82575(hw)) { 00105 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; 00106 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 00107 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 00108 } else { 00109 phy->ops.reset = igb_phy_hw_reset_generic; 00110 phy->ops.read_reg = igb_read_phy_reg_igp; 00111 phy->ops.write_reg = igb_write_phy_reg_igp; 00112 } 00113 00114 /* Set phy->phy_addr and phy->id. */ 00115 ret_val = igb_get_phy_id_82575(hw); 00116 00117 /* Verify phy id and set remaining function pointers */ 00118 switch (phy->id) { 00119 case M88E1111_I_PHY_ID: 00120 phy->type = e1000_phy_m88; 00121 phy->ops.check_polarity = igb_check_polarity_m88; 00122 phy->ops.get_info = igb_get_phy_info_m88; 00123 #if 0 00124 phy->ops.get_cable_length = igb_get_cable_length_m88; 00125 #endif 00126 #if 0 00127 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 00128 #endif 00129 break; 00130 case IGP03E1000_E_PHY_ID: 00131 case IGP04E1000_E_PHY_ID: 00132 phy->type = e1000_phy_igp_3; 00133 phy->ops.check_polarity = igb_check_polarity_igp; 00134 phy->ops.get_info = igb_get_phy_info_igp; 00135 #if 0 00136 phy->ops.get_cable_length = igb_get_cable_length_igp_2; 00137 #endif 00138 #if 0 00139 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; 00140 #endif 00141 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; 00142 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_generic; 00143 break; 00144 default: 00145 ret_val = -E1000_ERR_PHY; 00146 goto out; 00147 } 00148 00149 out: 00150 return ret_val; 00151 }
igb_init_nvm_params_82575 - Init NVM func ptrs.
: pointer to the HW structure
Definition at line 157 of file igb_82575.c.
References e1000_nvm_operations::acquire, e1000_nvm_info::address_bits, DEBUGFUNC, e1000_nvm_info::delay_usec, E1000_EECD, E1000_EECD_ADDR_BITS, E1000_EECD_SIZE_EX_MASK, E1000_EECD_SIZE_EX_SHIFT, e1000_nvm_eeprom_spi, e1000_nvm_override_spi_large, e1000_nvm_override_spi_small, E1000_READ_REG, E1000_SUCCESS, igb_acquire_nvm_82575(), igb_read_nvm_eerd(), igb_release_nvm_82575(), igb_update_nvm_checksum_generic(), igb_valid_led_default_82575(), igb_validate_nvm_checksum_generic(), igb_write_nvm_spi(), e1000_hw::nvm, NVM_WORD_SIZE_BASE_SHIFT, e1000_nvm_info::opcode_bits, e1000_nvm_info::ops, e1000_nvm_info::override, e1000_nvm_info::page_size, e1000_nvm_operations::read, e1000_nvm_operations::release, size, e1000_nvm_info::type, u16, u32, e1000_nvm_operations::update, e1000_nvm_operations::valid_led_default, e1000_nvm_operations::validate, e1000_nvm_info::word_size, and e1000_nvm_operations::write.
Referenced by igb_init_function_pointers_82575().
00158 { 00159 struct e1000_nvm_info *nvm = &hw->nvm; 00160 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 00161 u16 size; 00162 00163 DEBUGFUNC("igb_init_nvm_params_82575"); 00164 00165 nvm->opcode_bits = 8; 00166 nvm->delay_usec = 1; 00167 switch (nvm->override) { 00168 case e1000_nvm_override_spi_large: 00169 nvm->page_size = 32; 00170 nvm->address_bits = 16; 00171 break; 00172 case e1000_nvm_override_spi_small: 00173 nvm->page_size = 8; 00174 nvm->address_bits = 8; 00175 break; 00176 default: 00177 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 00178 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 00179 break; 00180 } 00181 00182 nvm->type = e1000_nvm_eeprom_spi; 00183 00184 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 00185 E1000_EECD_SIZE_EX_SHIFT); 00186 00187 /* 00188 * Added to a constant, "size" becomes the left-shift value 00189 * for setting word_size. 00190 */ 00191 size += NVM_WORD_SIZE_BASE_SHIFT; 00192 00193 /* EEPROM access above 16k is unsupported */ 00194 if (size > 14) 00195 size = 14; 00196 nvm->word_size = 1 << size; 00197 00198 /* Function Pointers */ 00199 nvm->ops.acquire = igb_acquire_nvm_82575; 00200 nvm->ops.read = igb_read_nvm_eerd; 00201 nvm->ops.release = igb_release_nvm_82575; 00202 nvm->ops.update = igb_update_nvm_checksum_generic; 00203 nvm->ops.valid_led_default = igb_valid_led_default_82575; 00204 nvm->ops.validate = igb_validate_nvm_checksum_generic; 00205 nvm->ops.write = igb_write_nvm_spi; 00206 00207 return E1000_SUCCESS; 00208 }
igb_init_mac_params_82575 - Init MAC func ptrs.
: pointer to the HW structure
Definition at line 214 of file igb_82575.c.
References e1000_hw::_82575, e1000_mac_info::arc_subsystem_valid, e1000_mac_info::asf_firmware_present, e1000_mac_operations::blink_led, e1000_mac_operations::check_for_link, e1000_mac_operations::cleanup_led, e1000_mac_operations::clear_hw_cntrs, e1000_mac_operations::clear_vfta, DEBUGFUNC, e1000_hw::dev_spec, e1000_82575, e1000_82576, E1000_CTRL_EXT, E1000_CTRL_EXT_LINK_MODE_MASK, E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES, E1000_CTRL_EXT_LINK_MODE_SGMII, E1000_CTRL_I2C_ENA, E1000_FWSM, E1000_FWSM_MODE_MASK, e1000_media_type_copper, e1000_media_type_internal_serdes, E1000_RAR_ENTRIES_82575, E1000_RAR_ENTRIES_82576, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_mac_operations::get_bus_info, e1000_mac_operations::get_link_up_info, e1000_mac_operations::id_led_init, igb_blink_led_generic(), igb_check_for_link_82575(), igb_cleanup_led_generic(), igb_clear_hw_cntrs_82575(), igb_clear_vfta_generic(), igb_get_bus_info_pcie_generic(), igb_get_link_up_info_82575(), igb_id_led_init_generic(), igb_init_hw_82575(), igb_led_off_generic(), igb_led_on_generic(), igb_mta_set_generic(), igb_rar_set_generic(), igb_read_mac_addr_82575(), igb_reset_hw_82575(), igb_setup_copper_link_82575(), igb_setup_led_generic(), igb_setup_link_generic(), igb_setup_serdes_link_82575(), igb_shutdown_serdes_link_82575(), igb_update_mc_addr_list_generic(), igb_write_vfta_generic(), e1000_mac_operations::init_hw, e1000_mac_operations::led_off, e1000_mac_operations::led_on, e1000_hw::mac, e1000_phy_info::media_type, e1000_mac_info::mta_reg_count, e1000_mac_operations::mta_set, e1000_mac_info::ops, e1000_hw::phy, e1000_mac_info::rar_entry_count, e1000_mac_operations::rar_set, e1000_mac_operations::read_mac_addr, e1000_mac_operations::reset_hw, e1000_mac_operations::set_lan_id, e1000_mac_operations::setup_led, e1000_mac_operations::setup_link, e1000_mac_operations::setup_physical_interface, e1000_dev_spec_82575::sgmii_active, e1000_mac_operations::shutdown_serdes, e1000_mac_info::type, u32, e1000_mac_operations::update_mc_addr_list, e1000_mac_info::uta_reg_count, and e1000_mac_operations::write_vfta.
Referenced by igb_init_function_pointers_82575().
00215 { 00216 struct e1000_mac_info *mac = &hw->mac; 00217 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 00218 u32 ctrl_ext = 0; 00219 00220 DEBUGFUNC("igb_init_mac_params_82575"); 00221 00222 /* Set media type */ 00223 /* 00224 * The 82575 uses bits 22:23 for link mode. The mode can be changed 00225 * based on the EEPROM. We cannot rely upon device ID. There 00226 * is no distinguishable difference between fiber and internal 00227 * SerDes mode on the 82575. There can be an external PHY attached 00228 * on the SGMII interface. For this, we'll set sgmii_active to true. 00229 */ 00230 hw->phy.media_type = e1000_media_type_copper; 00231 dev_spec->sgmii_active = false; 00232 00233 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 00234 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 00235 case E1000_CTRL_EXT_LINK_MODE_SGMII: 00236 dev_spec->sgmii_active = true; 00237 ctrl_ext |= E1000_CTRL_I2C_ENA; 00238 break; 00239 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 00240 hw->phy.media_type = e1000_media_type_internal_serdes; 00241 ctrl_ext |= E1000_CTRL_I2C_ENA; 00242 break; 00243 default: 00244 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 00245 break; 00246 } 00247 00248 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 00249 00250 /* Set mta register count */ 00251 mac->mta_reg_count = 128; 00252 /* Set uta register count */ 00253 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 00254 /* Set rar entry count */ 00255 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 00256 if (mac->type == e1000_82576) 00257 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 00258 /* Set if part includes ASF firmware */ 00259 mac->asf_firmware_present = true; 00260 /* Set if manageability features are enabled. */ 00261 mac->arc_subsystem_valid = 00262 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 00263 ? true : false; 00264 00265 /* Function pointers */ 00266 00267 /* bus type/speed/width */ 00268 mac->ops.get_bus_info = igb_get_bus_info_pcie_generic; 00269 /* reset */ 00270 mac->ops.reset_hw = igb_reset_hw_82575; 00271 /* hw initialization */ 00272 mac->ops.init_hw = igb_init_hw_82575; 00273 /* link setup */ 00274 mac->ops.setup_link = igb_setup_link_generic; 00275 /* physical interface link setup */ 00276 mac->ops.setup_physical_interface = 00277 (hw->phy.media_type == e1000_media_type_copper) 00278 ? igb_setup_copper_link_82575 00279 : igb_setup_serdes_link_82575; 00280 /* physical interface shutdown */ 00281 mac->ops.shutdown_serdes = igb_shutdown_serdes_link_82575; 00282 /* check for link */ 00283 mac->ops.check_for_link = igb_check_for_link_82575; 00284 /* receive address register setting */ 00285 mac->ops.rar_set = igb_rar_set_generic; 00286 /* read mac address */ 00287 mac->ops.read_mac_addr = igb_read_mac_addr_82575; 00288 /* multicast address update */ 00289 mac->ops.update_mc_addr_list = igb_update_mc_addr_list_generic; 00290 /* writing VFTA */ 00291 mac->ops.write_vfta = igb_write_vfta_generic; 00292 /* clearing VFTA */ 00293 mac->ops.clear_vfta = igb_clear_vfta_generic; 00294 /* setting MTA */ 00295 #if 0 00296 mac->ops.mta_set = igb_mta_set_generic; 00297 /* ID LED init */ 00298 mac->ops.id_led_init = igb_id_led_init_generic; 00299 /* blink LED */ 00300 mac->ops.blink_led = igb_blink_led_generic; 00301 /* setup LED */ 00302 mac->ops.setup_led = igb_setup_led_generic; 00303 /* cleanup LED */ 00304 mac->ops.cleanup_led = igb_cleanup_led_generic; 00305 /* turn on/off LED */ 00306 mac->ops.led_on = igb_led_on_generic; 00307 mac->ops.led_off = igb_led_off_generic; 00308 #endif 00309 /* clear hardware counters */ 00310 mac->ops.clear_hw_cntrs = igb_clear_hw_cntrs_82575; 00311 /* link info */ 00312 mac->ops.get_link_up_info = igb_get_link_up_info_82575; 00313 00314 /* set lan id for port to determine which phy lock to use */ 00315 hw->mac.ops.set_lan_id(hw); 00316 00317 return E1000_SUCCESS; 00318 }
igb_acquire_phy_82575 - Acquire rights to access PHY : pointer to the HW structure
Acquire access rights to the correct PHY.
Definition at line 344 of file igb_82575.c.
References e1000_hw::bus, DEBUGFUNC, E1000_FUNC_1, E1000_SWFW_PHY0_SM, E1000_SWFW_PHY1_SM, e1000_bus_info::func, igb_acquire_swfw_sync_82575(), and u16.
Referenced by igb_init_phy_params_82575().
00345 { 00346 u16 mask = E1000_SWFW_PHY0_SM; 00347 00348 DEBUGFUNC("igb_acquire_phy_82575"); 00349 00350 if (hw->bus.func == E1000_FUNC_1) 00351 mask = E1000_SWFW_PHY1_SM; 00352 00353 return igb_acquire_swfw_sync_82575(hw, mask); 00354 }
| static void igb_release_phy_82575 | ( | struct e1000_hw * | hw | ) | [static] |
igb_release_phy_82575 - Release rights to access PHY : pointer to the HW structure
A wrapper to release access rights to the correct PHY.
Definition at line 362 of file igb_82575.c.
References e1000_hw::bus, DEBUGFUNC, E1000_FUNC_1, E1000_SWFW_PHY0_SM, E1000_SWFW_PHY1_SM, e1000_bus_info::func, igb_release_swfw_sync_82575(), and u16.
Referenced by igb_init_phy_params_82575().
00363 { 00364 u16 mask = E1000_SWFW_PHY0_SM; 00365 00366 DEBUGFUNC("igb_release_phy_82575"); 00367 00368 if (hw->bus.func == E1000_FUNC_1) 00369 mask = E1000_SWFW_PHY1_SM; 00370 00371 igb_release_swfw_sync_82575(hw, mask); 00372 }
igb_acquire_nvm_82575 - Request for access to EEPROM : pointer to the HW structure
Acquire the necessary semaphores for exclusive access to the EEPROM. Set the EEPROM access request bit and wait for EEPROM access grant bit. Return successful if access grant bit set, else clear the request for EEPROM access and return -E1000_ERR_NVM (-1).
Definition at line 644 of file igb_82575.c.
References DEBUGFUNC, E1000_SWFW_EEP_SM, igb_acquire_nvm_generic(), igb_acquire_swfw_sync_82575(), and igb_release_swfw_sync_82575().
Referenced by igb_init_nvm_params_82575().
00645 { 00646 s32 ret_val; 00647 00648 DEBUGFUNC("igb_acquire_nvm_82575"); 00649 00650 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 00651 if (ret_val) 00652 goto out; 00653 00654 ret_val = igb_acquire_nvm_generic(hw); 00655 00656 if (ret_val) 00657 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 00658 00659 out: 00660 return ret_val; 00661 }
| static void igb_release_nvm_82575 | ( | struct e1000_hw * | hw | ) | [static] |
igb_release_nvm_82575 - Release exclusive access to EEPROM : pointer to the HW structure
Stop any current commands to the EEPROM and clear the EEPROM request bit, then release the semaphores acquired.
Definition at line 670 of file igb_82575.c.
References DEBUGFUNC, E1000_SWFW_EEP_SM, igb_release_nvm_generic(), and igb_release_swfw_sync_82575().
Referenced by igb_init_nvm_params_82575().
00671 { 00672 DEBUGFUNC("igb_release_nvm_82575"); 00673 00674 igb_release_nvm_generic(hw); 00675 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 00676 }
igb_check_for_link_82575 - Check for link : pointer to the HW structure
If sgmii is enabled, then use the pcs register to determine link, otherwise use the generic interface for determining link.
Definition at line 826 of file igb_82575.c.
References DEBUGFUNC, e1000_media_type_copper, e1000_mac_info::get_link_status, igb_check_for_copper_link_generic(), igb_get_pcs_speed_and_duplex_82575(), e1000_hw::mac, e1000_phy_info::media_type, e1000_hw::phy, e1000_mac_info::serdes_has_link, and u16.
Referenced by igb_init_mac_params_82575().
00827 { 00828 s32 ret_val; 00829 u16 speed, duplex; 00830 00831 DEBUGFUNC("igb_check_for_link_82575"); 00832 00833 if (hw->phy.media_type != e1000_media_type_copper) { 00834 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 00835 &duplex); 00836 /* 00837 * Use this flag to determine if link needs to be checked or 00838 * not. If we have link clear the flag so that we do not 00839 * continue to check for link. 00840 */ 00841 hw->mac.get_link_status = !hw->mac.serdes_has_link; 00842 } else { 00843 ret_val = igb_check_for_copper_link_generic(hw); 00844 } 00845 00846 return ret_val; 00847 }
igb_get_cfg_done_82575 - Read config done bit : pointer to the HW structure
Read the management control register for the config done bit for completion status. NOTE: silicon which is EEPROM-less will fail trying to read the config done bit, so an error is *ONLY* logged and returns E1000_SUCCESS. If we were to return with error, EEPROM-less silicon would not be able to be reset or change link.
Definition at line 764 of file igb_82575.c.
References e1000_hw::bus, DEBUGFUNC, DEBUGOUT, E1000_EECD, E1000_EECD_PRES, E1000_EEMNGCTL, E1000_FUNC_1, E1000_NVM_CFG_DONE_PORT_0, E1000_NVM_CFG_DONE_PORT_1, e1000_phy_igp_3, E1000_READ_REG, E1000_SUCCESS, e1000_bus_info::func, igb_phy_init_script_igp3(), msec_delay, e1000_hw::phy, PHY_CFG_TIMEOUT, timeout(), e1000_phy_info::type, and u32.
Referenced by igb_init_phy_params_82575().
00765 { 00766 s32 timeout = PHY_CFG_TIMEOUT; 00767 s32 ret_val = E1000_SUCCESS; 00768 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 00769 00770 DEBUGFUNC("igb_get_cfg_done_82575"); 00771 00772 if (hw->bus.func == E1000_FUNC_1) 00773 mask = E1000_NVM_CFG_DONE_PORT_1; 00774 while (timeout) { 00775 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 00776 break; 00777 msec_delay(1); 00778 timeout--; 00779 } 00780 if (!timeout) { 00781 DEBUGOUT("MNG configuration cycle has not completed.\n"); 00782 } 00783 00784 /* If EEPROM is not marked present, init the PHY manually */ 00785 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) && 00786 (hw->phy.type == e1000_phy_igp_3)) 00787 igb_phy_init_script_igp3(hw); 00788 00789 return ret_val; 00790 }
igb_get_link_up_info_82575 - Get link speed/duplex info : pointer to the HW structure : stores the current speed : stores the current duplex
This is a wrapper function, if using the serial gigabit media independent interface, use PCS to retrieve the link speed and duplex information. Otherwise, use the generic function to get the link speed and duplex info.
Definition at line 802 of file igb_82575.c.
References DEBUGFUNC, e1000_media_type_copper, igb_get_pcs_speed_and_duplex_82575(), igb_get_speed_and_duplex_copper_generic(), e1000_phy_info::media_type, and e1000_hw::phy.
Referenced by igb_init_mac_params_82575().
00804 { 00805 s32 ret_val; 00806 00807 DEBUGFUNC("igb_get_link_up_info_82575"); 00808 00809 if (hw->phy.media_type != e1000_media_type_copper) 00810 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, 00811 duplex); 00812 else 00813 ret_val = igb_get_speed_and_duplex_copper_generic(hw, speed, 00814 duplex); 00815 00816 return ret_val; 00817 }
igb_init_hw_82575 - Initialize hardware : pointer to the HW structure
This inits the hardware readying it for operation.
Definition at line 1026 of file igb_82575.c.
References e1000_mac_operations::clear_vfta, DEBUGFUNC, DEBUGOUT, E1000_MTA, E1000_UTA, E1000_WRITE_REG_ARRAY, e1000_mac_operations::id_led_init, igb_clear_hw_cntrs_82575(), igb_init_rx_addrs_generic(), e1000_hw::mac, e1000_mac_info::mta_reg_count, e1000_mac_info::ops, e1000_mac_info::rar_entry_count, e1000_mac_operations::setup_link, u16, and e1000_mac_info::uta_reg_count.
Referenced by igb_init_mac_params_82575().
01027 { 01028 struct e1000_mac_info *mac = &hw->mac; 01029 s32 ret_val; 01030 u16 i, rar_count = mac->rar_entry_count; 01031 01032 DEBUGFUNC("igb_init_hw_82575"); 01033 01034 /* Initialize identification LED */ 01035 ret_val = mac->ops.id_led_init(hw); 01036 if (ret_val) { 01037 DEBUGOUT("Error initializing identification LED\n"); 01038 /* This is not fatal and we should not stop init due to this */ 01039 } 01040 01041 /* Disabling VLAN filtering */ 01042 DEBUGOUT("Initializing the IEEE VLAN\n"); 01043 mac->ops.clear_vfta(hw); 01044 01045 /* Setup the receive address */ 01046 igb_init_rx_addrs_generic(hw, rar_count); 01047 01048 /* Zero out the Multicast HASH table */ 01049 DEBUGOUT("Zeroing the MTA\n"); 01050 for (i = 0; i < mac->mta_reg_count; i++) 01051 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 01052 01053 /* Zero out the Unicast HASH table */ 01054 DEBUGOUT("Zeroing the UTA\n"); 01055 for (i = 0; i < mac->uta_reg_count; i++) 01056 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); 01057 01058 /* Setup link and flow control */ 01059 ret_val = mac->ops.setup_link(hw); 01060 01061 /* 01062 * Clear all of the statistics registers (clear on read). It is 01063 * important that we do this after we have tried to establish link 01064 * because the symbol error count will increment wildly if there 01065 * is no link. 01066 */ 01067 igb_clear_hw_cntrs_82575(hw); 01068 01069 return ret_val; 01070 }
igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset : pointer to the HW structure
Resets the PHY using the serial gigabit media independent interface.
Definition at line 519 of file igb_82575.c.
References e1000_phy_operations::commit, DEBUGFUNC, DEBUGOUT, E1000_SUCCESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::write_reg.
Referenced by igb_init_phy_params_82575().
00520 { 00521 s32 ret_val = E1000_SUCCESS; 00522 00523 DEBUGFUNC("igb_phy_hw_reset_sgmii_82575"); 00524 00525 /* 00526 * This isn't a true "hard" reset, but is the only reset 00527 * available to us at this time. 00528 */ 00529 00530 DEBUGOUT("Soft resetting SGMII attached PHY...\n"); 00531 00532 if (!(hw->phy.ops.write_reg)) 00533 goto out; 00534 00535 /* 00536 * SFP documentation requires the following to configure the SPF module 00537 * to work on SGMII. No further documentation is given. 00538 */ 00539 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 00540 if (ret_val) 00541 goto out; 00542 00543 ret_val = hw->phy.ops.commit(hw); 00544 00545 out: 00546 return ret_val; 00547 }
igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the PHY register at offset using the serial gigabit media independent interface and stores the retrieved information in data.
Definition at line 383 of file igb_82575.c.
References e1000_phy_operations::acquire, DEBUGFUNC, DEBUGOUT1, E1000_ERR_PARAM, E1000_MAX_SGMII_PHY_REG_ADDR, igb_read_phy_reg_i2c(), e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::release.
Referenced by igb_get_phy_id_82575(), and igb_init_phy_params_82575().
00385 { 00386 s32 ret_val = -E1000_ERR_PARAM; 00387 00388 DEBUGFUNC("igb_read_phy_reg_sgmii_82575"); 00389 00390 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 00391 DEBUGOUT1("PHY Address %u is out of range\n", offset); 00392 goto out; 00393 } 00394 00395 ret_val = hw->phy.ops.acquire(hw); 00396 if (ret_val) 00397 goto out; 00398 00399 ret_val = igb_read_phy_reg_i2c(hw, offset, data); 00400 00401 hw->phy.ops.release(hw); 00402 00403 out: 00404 return ret_val; 00405 }
igb_reset_hw_82575 - Reset hardware : pointer to the HW structure
This resets the hardware into a known state.
Definition at line 960 of file igb_82575.c.
References DEBUGFUNC, DEBUGOUT, E1000_CTRL, E1000_CTRL_RST, E1000_EECD, E1000_EECD_PRES, E1000_ICR, E1000_IMC, E1000_RCTL, E1000_READ_REG, E1000_TCTL, E1000_TCTL_PSP, E1000_WRITE_FLUSH, E1000_WRITE_REG, igb_check_alt_mac_addr_generic(), igb_disable_pcie_master_generic(), igb_get_auto_rd_done_generic(), igb_reset_init_script_82575(), igb_set_pcie_completion_timeout(), msec_delay, and u32.
Referenced by igb_init_mac_params_82575().
00961 { 00962 u32 ctrl, icr; 00963 s32 ret_val; 00964 00965 DEBUGFUNC("igb_reset_hw_82575"); 00966 00967 /* 00968 * Prevent the PCI-E bus from sticking if there is no TLP connection 00969 * on the last TLP read/write transaction when MAC is reset. 00970 */ 00971 ret_val = igb_disable_pcie_master_generic(hw); 00972 if (ret_val) { 00973 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 00974 } 00975 00976 /* set the completion timeout for interface */ 00977 ret_val = igb_set_pcie_completion_timeout(hw); 00978 if (ret_val) { 00979 DEBUGOUT("PCI-E Set completion timeout has failed.\n"); 00980 } 00981 00982 DEBUGOUT("Masking off all interrupts\n"); 00983 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 00984 00985 E1000_WRITE_REG(hw, E1000_RCTL, 0); 00986 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 00987 E1000_WRITE_FLUSH(hw); 00988 00989 msec_delay(10); 00990 00991 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00992 00993 DEBUGOUT("Issuing a global reset to MAC\n"); 00994 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 00995 00996 ret_val = igb_get_auto_rd_done_generic(hw); 00997 if (ret_val) { 00998 /* 00999 * When auto config read does not complete, do not 01000 * return with an error. This can happen in situations 01001 * where there is no eeprom and prevents getting link. 01002 */ 01003 DEBUGOUT("Auto Read Done did not complete\n"); 01004 } 01005 01006 /* If EEPROM is not present, run manual init scripts */ 01007 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) 01008 igb_reset_init_script_82575(hw); 01009 01010 /* Clear any pending interrupt events. */ 01011 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 01012 icr = E1000_READ_REG(hw, E1000_ICR); 01013 01014 /* Install any alternate MAC address into RAR0 */ 01015 ret_val = igb_check_alt_mac_addr_generic(hw); 01016 01017 return ret_val; 01018 }
igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state : pointer to the HW structure : true to enable LPLU, false to disable
Sets the LPLU D0 state according to the active flag. When activating LPLU this function also disables smart speed and vice versa. LPLU will not be activated unless the device autonegotiation advertisement meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function pointer entry point only called by PHY setup routines.
Definition at line 562 of file igb_82575.c.
References DEBUGFUNC, e1000_smart_speed_off, e1000_smart_speed_on, E1000_SUCCESS, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PSCFR_SMART_SPEED, IGP02E1000_PHY_POWER_MGMT, IGP02E1000_PM_D0_LPLU, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::smart_speed, u16, and e1000_phy_operations::write_reg.
Referenced by igb_init_phy_params_82575().
00563 { 00564 struct e1000_phy_info *phy = &hw->phy; 00565 s32 ret_val = E1000_SUCCESS; 00566 u16 data; 00567 00568 DEBUGFUNC("igb_set_d0_lplu_state_82575"); 00569 00570 if (!(hw->phy.ops.read_reg)) 00571 goto out; 00572 00573 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 00574 if (ret_val) 00575 goto out; 00576 00577 if (active) { 00578 data |= IGP02E1000_PM_D0_LPLU; 00579 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 00580 data); 00581 if (ret_val) 00582 goto out; 00583 00584 /* When LPLU is enabled, we should disable SmartSpeed */ 00585 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 00586 &data); 00587 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 00588 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 00589 data); 00590 if (ret_val) 00591 goto out; 00592 } else { 00593 data &= ~IGP02E1000_PM_D0_LPLU; 00594 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 00595 data); 00596 /* 00597 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 00598 * during Dx states where the power conservation is most 00599 * important. During driver activity we should enable 00600 * SmartSpeed, so performance is maintained. 00601 */ 00602 if (phy->smart_speed == e1000_smart_speed_on) { 00603 ret_val = phy->ops.read_reg(hw, 00604 IGP01E1000_PHY_PORT_CONFIG, 00605 &data); 00606 if (ret_val) 00607 goto out; 00608 00609 data |= IGP01E1000_PSCFR_SMART_SPEED; 00610 ret_val = phy->ops.write_reg(hw, 00611 IGP01E1000_PHY_PORT_CONFIG, 00612 data); 00613 if (ret_val) 00614 goto out; 00615 } else if (phy->smart_speed == e1000_smart_speed_off) { 00616 ret_val = phy->ops.read_reg(hw, 00617 IGP01E1000_PHY_PORT_CONFIG, 00618 &data); 00619 if (ret_val) 00620 goto out; 00621 00622 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 00623 ret_val = phy->ops.write_reg(hw, 00624 IGP01E1000_PHY_PORT_CONFIG, 00625 data); 00626 if (ret_val) 00627 goto out; 00628 } 00629 } 00630 00631 out: 00632 return ret_val; 00633 }
igb_setup_copper_link_82575 - Configure copper link settings : pointer to the HW structure
Configures the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called.
Definition at line 1080 of file igb_82575.c.
References DEBUGFUNC, DEBUGOUT, E1000_CTRL, E1000_CTRL_FRCDPX, E1000_CTRL_FRCSPD, E1000_CTRL_SLU, E1000_ERR_PHY, e1000_phy_igp_3, e1000_phy_m88, E1000_READ_REG, E1000_WRITE_REG, igb_copper_link_setup_igp(), igb_copper_link_setup_m88(), igb_setup_copper_link_generic(), igb_setup_serdes_link_82575(), igb_sgmii_active_82575(), e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::reset, e1000_phy_info::reset_disable, e1000_phy_info::type, and u32.
Referenced by igb_init_mac_params_82575().
01081 { 01082 u32 ctrl; 01083 s32 ret_val; 01084 01085 DEBUGFUNC("igb_setup_copper_link_82575"); 01086 01087 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01088 ctrl |= E1000_CTRL_SLU; 01089 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 01090 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01091 01092 ret_val = igb_setup_serdes_link_82575(hw); 01093 if (ret_val) 01094 goto out; 01095 01096 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 01097 ret_val = hw->phy.ops.reset(hw); 01098 if (ret_val) { 01099 DEBUGOUT("Error resetting the PHY.\n"); 01100 goto out; 01101 } 01102 } 01103 switch (hw->phy.type) { 01104 case e1000_phy_m88: 01105 ret_val = igb_copper_link_setup_m88(hw); 01106 break; 01107 case e1000_phy_igp_3: 01108 ret_val = igb_copper_link_setup_igp(hw); 01109 break; 01110 default: 01111 ret_val = -E1000_ERR_PHY; 01112 break; 01113 } 01114 01115 if (ret_val) 01116 goto out; 01117 01118 ret_val = igb_setup_copper_link_generic(hw); 01119 out: 01120 return ret_val; 01121 }
igb_setup_serdes_link_82575 - Setup link for serdes : pointer to the HW structure
Configure the physical coding sub-layer (PCS) link. The PCS link is used on copper connections where the serialized gigabit media independent interface (sgmii), or serdes fiber is being used. Configures the link for auto-negotiation or forces speed/duplex.
Definition at line 1132 of file igb_82575.c.
References e1000_mac_info::autoneg, DEBUGFUNC, DEBUGOUT1, e1000_82575, e1000_82576, E1000_ALL_100_SPEED, E1000_ALL_FULL_DUPLEX, E1000_CONNSW, E1000_CONNSW_ENRGSRC, E1000_CTRL, E1000_CTRL_EXT, E1000_CTRL_EXT_SDP3_DATA, E1000_CTRL_FD, E1000_CTRL_FRCDPX, E1000_CTRL_FRCSPD, E1000_CTRL_SLU, E1000_CTRL_SPD_1000, E1000_CTRL_SWDPIN0, E1000_CTRL_SWDPIN1, e1000_media_type_internal_serdes, E1000_PCS_LCTL, E1000_PCS_LCTL_AN_ENABLE, E1000_PCS_LCTL_AN_RESTART, E1000_PCS_LCTL_AN_TIMEOUT, E1000_PCS_LCTL_FDV_FULL, E1000_PCS_LCTL_FLV_LINK_UP, E1000_PCS_LCTL_FORCE_FCTRL, E1000_PCS_LCTL_FORCE_LINK, E1000_PCS_LCTL_FSD, E1000_PCS_LCTL_FSV_100, E1000_PCS_LCTL_FSV_1000, E1000_READ_REG, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK, E1000_SUCCESS, E1000_WRITE_REG, e1000_mac_info::forced_speed_duplex, igb_force_mac_fc_generic(), igb_sgmii_active_82575(), e1000_hw::mac, e1000_phy_info::media_type, msec_delay, e1000_hw::phy, e1000_mac_info::type, and u32.
Referenced by igb_init_mac_params_82575(), and igb_setup_copper_link_82575().
01133 { 01134 u32 ctrl_reg, reg; 01135 01136 DEBUGFUNC("igb_setup_serdes_link_82575"); 01137 01138 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 01139 !igb_sgmii_active_82575(hw)) 01140 return E1000_SUCCESS; 01141 01142 /* 01143 * On the 82575, SerDes loopback mode persists until it is 01144 * explicitly turned off or a power cycle is performed. A read to 01145 * the register does not indicate its status. Therefore, we ensure 01146 * loopback mode is disabled during initialization. 01147 */ 01148 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 01149 01150 /* power on the sfp cage if present */ 01151 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 01152 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 01153 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 01154 01155 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL); 01156 ctrl_reg |= E1000_CTRL_SLU; 01157 01158 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 01159 /* set both sw defined pins */ 01160 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 01161 01162 /* Set switch control to serdes energy detect */ 01163 reg = E1000_READ_REG(hw, E1000_CONNSW); 01164 reg |= E1000_CONNSW_ENRGSRC; 01165 E1000_WRITE_REG(hw, E1000_CONNSW, reg); 01166 } 01167 01168 reg = E1000_READ_REG(hw, E1000_PCS_LCTL); 01169 01170 if (igb_sgmii_active_82575(hw)) { 01171 /* allow time for SFP cage to power up phy */ 01172 msec_delay(300); 01173 01174 /* AN time out should be disabled for SGMII mode */ 01175 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 01176 } else { 01177 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 01178 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 01179 } 01180 01181 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg); 01182 01183 /* 01184 * New SerDes mode allows for forcing speed or autonegotiating speed 01185 * at 1gb. Autoneg should be default set by most drivers. This is the 01186 * mode that will be compatible with older link partners and switches. 01187 * However, both are supported by the hardware and some drivers/tools. 01188 */ 01189 01190 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 01191 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 01192 01193 /* 01194 * We force flow control to prevent the CTRL register values from being 01195 * overwritten by the autonegotiated flow control values 01196 */ 01197 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 01198 01199 /* 01200 * we always set sgmii to autoneg since it is the phy that will be 01201 * forcing the link and the serdes is just a go-between 01202 */ 01203 if (hw->mac.autoneg || igb_sgmii_active_82575(hw)) { 01204 /* Set PCS register for autoneg */ 01205 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 01206 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full dplx */ 01207 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 01208 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 01209 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 01210 } else { 01211 /* Check for duplex first */ 01212 if (hw->mac.forced_speed_duplex & E1000_ALL_FULL_DUPLEX) 01213 reg |= E1000_PCS_LCTL_FDV_FULL; 01214 01215 /* No need to check for 1000/full since the spec states that 01216 * it requires autoneg to be enabled */ 01217 /* Now set speed */ 01218 if (hw->mac.forced_speed_duplex & E1000_ALL_100_SPEED) 01219 reg |= E1000_PCS_LCTL_FSV_100; 01220 01221 /* Force speed and force link */ 01222 reg |= E1000_PCS_LCTL_FSD | 01223 E1000_PCS_LCTL_FORCE_LINK | 01224 E1000_PCS_LCTL_FLV_LINK_UP; 01225 01226 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 01227 } 01228 01229 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg); 01230 01231 if (!igb_sgmii_active_82575(hw)) 01232 igb_force_mac_fc_generic(hw); 01233 01234 return E1000_SUCCESS; 01235 }
igb_valid_led_default_82575 - Verify a valid default LED config : pointer to the HW structure : pointer to the NVM (EEPROM)
Read the EEPROM for the current default LED configuration. If the LED configuration is not valid, set to a valid LED configuration.
Definition at line 1245 of file igb_82575.c.
References DEBUGFUNC, DEBUGOUT, e1000_media_type_copper, e1000_media_type_internal_serdes, ID_LED_DEFAULT, ID_LED_DEFAULT_82575_SERDES, ID_LED_RESERVED_0000, ID_LED_RESERVED_FFFF, e1000_phy_info::media_type, e1000_hw::nvm, NVM_ID_LED_SETTINGS, e1000_nvm_info::ops, e1000_hw::phy, and e1000_nvm_operations::read.
Referenced by igb_init_nvm_params_82575().
01246 { 01247 s32 ret_val; 01248 01249 DEBUGFUNC("igb_valid_led_default_82575"); 01250 01251 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 01252 if (ret_val) { 01253 DEBUGOUT("NVM Read Error\n"); 01254 goto out; 01255 } 01256 01257 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) { 01258 switch(hw->phy.media_type) { 01259 case e1000_media_type_internal_serdes: 01260 *data = ID_LED_DEFAULT_82575_SERDES; 01261 break; 01262 case e1000_media_type_copper: 01263 default: 01264 *data = ID_LED_DEFAULT; 01265 break; 01266 } 01267 } 01268 out: 01269 return ret_val; 01270 }
igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii : pointer to the HW structure : register offset to write to : data to write at register offset
Writes the data to PHY register at the offset using the serial gigabit media independent interface.
Definition at line 416 of file igb_82575.c.
References e1000_phy_operations::acquire, DEBUGFUNC, DEBUGOUT1, E1000_ERR_PARAM, E1000_MAX_SGMII_PHY_REG_ADDR, igb_write_phy_reg_i2c(), e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::release.
Referenced by igb_init_phy_params_82575().
00418 { 00419 s32 ret_val = -E1000_ERR_PARAM; 00420 00421 DEBUGFUNC("igb_write_phy_reg_sgmii_82575"); 00422 00423 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 00424 DEBUGOUT1("PHY Address %d is out of range\n", offset); 00425 goto out; 00426 } 00427 00428 ret_val = hw->phy.ops.acquire(hw); 00429 if (ret_val) 00430 goto out; 00431 00432 ret_val = igb_write_phy_reg_i2c(hw, offset, data); 00433 00434 hw->phy.ops.release(hw); 00435 00436 out: 00437 return ret_val; 00438 }
| static void igb_clear_hw_cntrs_82575 | ( | struct e1000_hw * | hw | ) | [static] |
igb_clear_hw_cntrs_82575 - Clear device specific hardware counters : pointer to the HW structure
Clears the hardware counters by reading the counter registers.
Definition at line 1377 of file igb_82575.c.
References DEBUGFUNC, E1000_ALGNERRC, E1000_CBRMPC, E1000_CBTMPC, E1000_CEXTERR, E1000_HGORCH, E1000_HGORCL, E1000_HGOTCH, E1000_HGOTCL, E1000_HGPTC, E1000_HTCBDPC, E1000_HTDPMC, E1000_IAC, E1000_ICRXATC, E1000_ICRXDMTC, E1000_ICRXOC, E1000_ICRXPTC, E1000_ICTXATC, E1000_ICTXPTC, E1000_ICTXQEC, E1000_ICTXQMTC, E1000_LENERRS, e1000_media_type_internal_serdes, E1000_MGTPDC, E1000_MGTPRC, E1000_MGTPTC, E1000_PRC1023, E1000_PRC127, E1000_PRC1522, E1000_PRC255, E1000_PRC511, E1000_PRC64, E1000_PTC1023, E1000_PTC127, E1000_PTC1522, E1000_PTC255, E1000_PTC511, E1000_PTC64, E1000_READ_REG, E1000_RPTHC, E1000_RXERRC, E1000_SCVPC, E1000_TNCRS, E1000_TSCTC, E1000_TSCTFC, igb_clear_hw_cntrs_base_generic(), igb_sgmii_active_82575(), e1000_phy_info::media_type, and e1000_hw::phy.
Referenced by igb_init_hw_82575(), and igb_init_mac_params_82575().
01378 { 01379 DEBUGFUNC("igb_clear_hw_cntrs_82575"); 01380 01381 igb_clear_hw_cntrs_base_generic(hw); 01382 01383 E1000_READ_REG(hw, E1000_PRC64); 01384 E1000_READ_REG(hw, E1000_PRC127); 01385 E1000_READ_REG(hw, E1000_PRC255); 01386 E1000_READ_REG(hw, E1000_PRC511); 01387 E1000_READ_REG(hw, E1000_PRC1023); 01388 E1000_READ_REG(hw, E1000_PRC1522); 01389 E1000_READ_REG(hw, E1000_PTC64); 01390 E1000_READ_REG(hw, E1000_PTC127); 01391 E1000_READ_REG(hw, E1000_PTC255); 01392 E1000_READ_REG(hw, E1000_PTC511); 01393 E1000_READ_REG(hw, E1000_PTC1023); 01394 E1000_READ_REG(hw, E1000_PTC1522); 01395 01396 E1000_READ_REG(hw, E1000_ALGNERRC); 01397 E1000_READ_REG(hw, E1000_RXERRC); 01398 E1000_READ_REG(hw, E1000_TNCRS); 01399 E1000_READ_REG(hw, E1000_CEXTERR); 01400 E1000_READ_REG(hw, E1000_TSCTC); 01401 E1000_READ_REG(hw, E1000_TSCTFC); 01402 01403 E1000_READ_REG(hw, E1000_MGTPRC); 01404 E1000_READ_REG(hw, E1000_MGTPDC); 01405 E1000_READ_REG(hw, E1000_MGTPTC); 01406 01407 E1000_READ_REG(hw, E1000_IAC); 01408 E1000_READ_REG(hw, E1000_ICRXOC); 01409 01410 E1000_READ_REG(hw, E1000_ICRXPTC); 01411 E1000_READ_REG(hw, E1000_ICRXATC); 01412 E1000_READ_REG(hw, E1000_ICTXPTC); 01413 E1000_READ_REG(hw, E1000_ICTXATC); 01414 E1000_READ_REG(hw, E1000_ICTXQEC); 01415 E1000_READ_REG(hw, E1000_ICTXQMTC); 01416 E1000_READ_REG(hw, E1000_ICRXDMTC); 01417 01418 E1000_READ_REG(hw, E1000_CBTMPC); 01419 E1000_READ_REG(hw, E1000_HTDPMC); 01420 E1000_READ_REG(hw, E1000_CBRMPC); 01421 E1000_READ_REG(hw, E1000_RPTHC); 01422 E1000_READ_REG(hw, E1000_HGPTC); 01423 E1000_READ_REG(hw, E1000_HTCBDPC); 01424 E1000_READ_REG(hw, E1000_HGORCL); 01425 E1000_READ_REG(hw, E1000_HGORCH); 01426 E1000_READ_REG(hw, E1000_HGOTCL); 01427 E1000_READ_REG(hw, E1000_HGOTCH); 01428 E1000_READ_REG(hw, E1000_LENERRS); 01429 01430 /* This register should not be read in copper configurations */ 01431 if ((hw->phy.media_type == e1000_media_type_internal_serdes) || 01432 igb_sgmii_active_82575(hw)) 01433 E1000_READ_REG(hw, E1000_SCVPC); 01434 }
igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore : pointer to the HW structure : specifies which semaphore to acquire
Acquire the SW/FW semaphore to access the PHY or NVM. The mask will also specify which port we're acquiring the lock for.
Definition at line 686 of file igb_82575.c.
References DEBUGFUNC, DEBUGOUT, E1000_ERR_SWFW_SYNC, E1000_READ_REG, E1000_SUCCESS, E1000_SW_FW_SYNC, E1000_WRITE_REG, igb_get_hw_semaphore_generic(), igb_put_hw_semaphore_generic(), msec_delay_irq, timeout(), and u32.
Referenced by igb_acquire_nvm_82575(), and igb_acquire_phy_82575().
00687 { 00688 u32 swfw_sync; 00689 u32 swmask = mask; 00690 u32 fwmask = mask << 16; 00691 s32 ret_val = E1000_SUCCESS; 00692 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 00693 00694 DEBUGFUNC("igb_acquire_swfw_sync_82575"); 00695 00696 while (i < timeout) { 00697 if (igb_get_hw_semaphore_generic(hw)) { 00698 ret_val = -E1000_ERR_SWFW_SYNC; 00699 goto out; 00700 } 00701 00702 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 00703 if (!(swfw_sync & (fwmask | swmask))) 00704 break; 00705 00706 /* 00707 * Firmware currently using resource (fwmask) 00708 * or other software thread using resource (swmask) 00709 */ 00710 igb_put_hw_semaphore_generic(hw); 00711 msec_delay_irq(5); 00712 i++; 00713 } 00714 00715 if (i == timeout) { 00716 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 00717 ret_val = -E1000_ERR_SWFW_SYNC; 00718 goto out; 00719 } 00720 00721 swfw_sync |= swmask; 00722 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 00723 00724 igb_put_hw_semaphore_generic(hw); 00725 00726 out: 00727 return ret_val; 00728 }
| static s32 igb_get_pcs_speed_and_duplex_82575 | ( | struct e1000_hw * | hw, | |
| u16 * | speed, | |||
| u16 * | duplex | |||
| ) | [static] |
igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex
Using the physical coding sub-layer (PCS), retrieve the current speed and duplex, then store the values in the pointers provided.
Definition at line 858 of file igb_82575.c.
References DEBUGFUNC, E1000_PCS_LSTAT, E1000_PCS_LSTS_DUPLEX_FULL, E1000_PCS_LSTS_LINK_OK, E1000_PCS_LSTS_SPEED_100, E1000_PCS_LSTS_SPEED_1000, E1000_PCS_LSTS_SYNK_OK, E1000_READ_REG, E1000_SUCCESS, FULL_DUPLEX, HALF_DUPLEX, e1000_hw::mac, e1000_mac_info::serdes_has_link, SPEED_10, SPEED_100, SPEED_1000, and u32.
Referenced by igb_check_for_link_82575(), and igb_get_link_up_info_82575().
00860 { 00861 struct e1000_mac_info *mac = &hw->mac; 00862 u32 pcs; 00863 00864 DEBUGFUNC("igb_get_pcs_speed_and_duplex_82575"); 00865 00866 /* Set up defaults for the return values of this function */ 00867 mac->serdes_has_link = false; 00868 *speed = 0; 00869 *duplex = 0; 00870 00871 /* 00872 * Read the PCS Status register for link state. For non-copper mode, 00873 * the status register is not accurate. The PCS status register is 00874 * used instead. 00875 */ 00876 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT); 00877 00878 /* 00879 * The link up bit determines when link is up on autoneg. The sync ok 00880 * gets set once both sides sync up and agree upon link. Stable link 00881 * can be determined by checking for both link up and link sync ok 00882 */ 00883 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 00884 mac->serdes_has_link = true; 00885 00886 /* Detect and store PCS speed */ 00887 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 00888 *speed = SPEED_1000; 00889 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 00890 *speed = SPEED_100; 00891 } else { 00892 *speed = SPEED_10; 00893 } 00894 00895 /* Detect and store PCS duplex */ 00896 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 00897 *duplex = FULL_DUPLEX; 00898 } else { 00899 *duplex = HALF_DUPLEX; 00900 } 00901 } 00902 00903 return E1000_SUCCESS; 00904 }
igb_get_phy_id_82575 - Retrieve PHY addr and id : pointer to the HW structure
Retrieves the PHY address and ID for both PHY's which do and do not use sgmi interface.
Definition at line 447 of file igb_82575.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT1, DEBUGOUT2, E1000_CTRL_EXT, E1000_CTRL_EXT_SDP3_DATA, E1000_ERR_PHY, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_FLUSH, E1000_WRITE_REG, igb_get_phy_id(), igb_read_phy_reg_sgmii_82575(), igb_sgmii_active_82575(), M88_VENDOR, msec_delay, e1000_hw::phy, PHY_ID1, u16, and u32.
Referenced by igb_init_phy_params_82575().
00448 { 00449 struct e1000_phy_info *phy = &hw->phy; 00450 s32 ret_val = E1000_SUCCESS; 00451 u16 phy_id; 00452 u32 ctrl_ext; 00453 00454 DEBUGFUNC("igb_get_phy_id_82575"); 00455 00456 /* 00457 * For SGMII PHYs, we try the list of possible addresses until 00458 * we find one that works. For non-SGMII PHYs 00459 * (e.g. integrated copper PHYs), an address of 1 should 00460 * work. The result of this function should mean phy->phy_addr 00461 * and phy->id are set correctly. 00462 */ 00463 if (!igb_sgmii_active_82575(hw)) { 00464 phy->addr = 1; 00465 ret_val = igb_get_phy_id(hw); 00466 goto out; 00467 } 00468 00469 /* Power on sgmii phy if it is disabled */ 00470 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 00471 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 00472 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 00473 E1000_WRITE_FLUSH(hw); 00474 msec_delay(300); 00475 00476 /* 00477 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 00478 * Therefore, we need to test 1-7 00479 */ 00480 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 00481 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 00482 if (ret_val == E1000_SUCCESS) { 00483 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n", 00484 phy_id, 00485 phy->addr); 00486 /* 00487 * At the time of this writing, The M88 part is 00488 * the only supported SGMII PHY product. 00489 */ 00490 if (phy_id == M88_VENDOR) 00491 break; 00492 } else { 00493 DEBUGOUT1("PHY address %u was unreadable\n", 00494 phy->addr); 00495 } 00496 } 00497 00498 /* A valid PHY type couldn't be found. */ 00499 if (phy->addr == 8) { 00500 phy->addr = 0; 00501 ret_val = -E1000_ERR_PHY; 00502 } else { 00503 ret_val = igb_get_phy_id(hw); 00504 } 00505 00506 /* restore previous sfp cage power state */ 00507 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 00508 00509 out: 00510 return ret_val; 00511 }
igb_release_swfw_sync_82575 - Release SW/FW semaphore : pointer to the HW structure : specifies which semaphore to acquire
Release the SW/FW semaphore used to access the PHY or NVM. The mask will also specify which port we're releasing the lock for.
Definition at line 738 of file igb_82575.c.
References DEBUGFUNC, E1000_READ_REG, E1000_SUCCESS, E1000_SW_FW_SYNC, E1000_WRITE_REG, igb_get_hw_semaphore_generic(), igb_put_hw_semaphore_generic(), and u32.
Referenced by igb_acquire_nvm_82575(), igb_release_nvm_82575(), and igb_release_phy_82575().
00739 { 00740 u32 swfw_sync; 00741 00742 DEBUGFUNC("igb_release_swfw_sync_82575"); 00743 00744 while (igb_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 00745 /* Empty */ 00746 00747 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 00748 swfw_sync &= ~mask; 00749 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 00750 00751 igb_put_hw_semaphore_generic(hw); 00752 }
igb_sgmii_active_82575 - Return sgmii state : pointer to the HW structure
82575 silicon has a serialized gigabit media independent interface (sgmii) which can be enabled for use in the embedded applications. Simply return the current state of the sgmii interface.
Definition at line 1280 of file igb_82575.c.
References e1000_hw::_82575, e1000_hw::dev_spec, and e1000_dev_spec_82575::sgmii_active.
Referenced by igb_clear_hw_cntrs_82575(), igb_get_phy_id_82575(), igb_init_phy_params_82575(), igb_setup_copper_link_82575(), igb_setup_serdes_link_82575(), and igb_shutdown_serdes_link_82575().
01281 { 01282 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 01283 return dev_spec->sgmii_active; 01284 }
igb_reset_init_script_82575 - Inits HW defaults after reset : pointer to the HW structure
Inits recommended HW defaults after a reset when there is no EEPROM detected. This is only for the 82575.
Definition at line 1293 of file igb_82575.c.
References DEBUGFUNC, DEBUGOUT, e1000_82575, E1000_CCMCTL, E1000_GIOCTL, E1000_SCCTL, E1000_SCTL, E1000_SUCCESS, igb_write_8bit_ctrl_reg_generic(), e1000_hw::mac, and e1000_mac_info::type.
Referenced by igb_reset_hw_82575().
01294 { 01295 DEBUGFUNC("igb_reset_init_script_82575"); 01296 01297 if (hw->mac.type == e1000_82575) { 01298 DEBUGOUT("Running reset init script for 82575\n"); 01299 /* SerDes configuration via SERDESCTRL */ 01300 igb_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C); 01301 igb_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78); 01302 igb_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23); 01303 igb_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15); 01304 01305 /* CCM configuration via CCMCTL register */ 01306 igb_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00); 01307 igb_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00); 01308 01309 /* PCIe lanes configuration */ 01310 igb_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC); 01311 igb_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF); 01312 igb_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05); 01313 igb_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81); 01314 01315 /* PCIe PLL Configuration */ 01316 igb_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47); 01317 igb_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00); 01318 igb_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00); 01319 } 01320 01321 return E1000_SUCCESS; 01322 }
igb_read_mac_addr_82575 - Read device MAC address : pointer to the HW structure
Definition at line 1328 of file igb_82575.c.
References DEBUGFUNC, E1000_SUCCESS, igb_check_alt_mac_addr_generic(), and igb_read_mac_addr_generic().
Referenced by igb_init_mac_params_82575().
01329 { 01330 s32 ret_val = E1000_SUCCESS; 01331 01332 DEBUGFUNC("igb_read_mac_addr_82575"); 01333 01334 /* 01335 * If there's an alternate MAC address place it in RAR0 01336 * so that it will override the Si installed default perm 01337 * address. 01338 */ 01339 ret_val = igb_check_alt_mac_addr_generic(hw); 01340 if (ret_val) 01341 goto out; 01342 01343 ret_val = igb_read_mac_addr_generic(hw); 01344 01345 out: 01346 return ret_val; 01347 }
| static void igb_power_down_phy_copper_82575 | ( | struct e1000_hw * | hw | ) | [static] |
igb_power_down_phy_copper_82575 - Remove link during PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, remove the link.
Definition at line 1356 of file igb_82575.c.
References e1000_mac_operations::check_mng_mode, e1000_phy_operations::check_reset_block, igb_power_down_phy_copper(), e1000_hw::mac, e1000_mac_info::ops, e1000_phy_info::ops, and e1000_hw::phy.
Referenced by igb_init_phy_params_82575().
01357 { 01358 struct e1000_phy_info *phy = &hw->phy; 01359 struct e1000_mac_info *mac = &hw->mac; 01360 01361 if (!(phy->ops.check_reset_block)) 01362 return; 01363 01364 /* If the management interface is not enabled, then power down */ 01365 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) 01366 igb_power_down_phy_copper(hw); 01367 01368 return; 01369 }
| void igb_shutdown_serdes_link_82575 | ( | struct e1000_hw * | hw | ) | [static] |
igb_shutdown_serdes_link_82575 - Remove link during power down : pointer to the HW structure
In the case of serdes shut down sfp and PCS on driver unload when management pass thru is not enabled.
Definition at line 913 of file igb_82575.c.
References e1000_hw::bus, E1000_CTRL_EXT, E1000_CTRL_EXT_SDP3_DATA, E1000_FUNC_0, E1000_FUNC_1, e1000_media_type_internal_serdes, E1000_NVM_APME_82575, E1000_PCS_CFG0, E1000_PCS_CFG_PCS_EN, E1000_READ_REG, E1000_WRITE_FLUSH, E1000_WRITE_REG, e1000_bus_info::func, igb_sgmii_active_82575(), e1000_phy_info::media_type, msec_delay, e1000_hw::nvm, NVM_INIT_CONTROL3_PORT_A, NVM_INIT_CONTROL3_PORT_B, e1000_nvm_info::ops, e1000_hw::phy, e1000_nvm_operations::read, u16, and u32.
Referenced by igb_init_mac_params_82575().
00914 { 00915 #if 0 00916 u32 reg; 00917 #endif 00918 u16 eeprom_data = 0; 00919 00920 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 00921 !igb_sgmii_active_82575(hw)) 00922 return; 00923 00924 if (hw->bus.func == E1000_FUNC_0) 00925 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 00926 else if (hw->bus.func == E1000_FUNC_1) 00927 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 00928 00929 /* 00930 * If APM is not enabled in the EEPROM and management interface is 00931 * not enabled, then power down. 00932 */ 00933 #if 0 00934 if (!(eeprom_data & E1000_NVM_APME_82575) && 00935 !igb_enable_mng_pass_thru(hw)) { 00936 /* Disable PCS to turn off link */ 00937 reg = E1000_READ_REG(hw, E1000_PCS_CFG0); 00938 reg &= ~E1000_PCS_CFG_PCS_EN; 00939 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg); 00940 00941 /* shutdown the laser */ 00942 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 00943 reg |= E1000_CTRL_EXT_SDP3_DATA; 00944 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 00945 00946 /* flush the write to verify completion */ 00947 E1000_WRITE_FLUSH(hw); 00948 msec_delay(1); 00949 } 00950 #endif 00951 return; 00952 }
igb_set_pcie_completion_timeout - set pci-e completion timeout : pointer to the HW structure
The defaults for 82575 and 82576 should be in the range of 50us to 50ms, however the hardware default for these parts is 500us to 1ms which is less than the 10ms recommended by the pci-e spec. To address this we need to increase the value to either 10ms to 200ms for capability version 1 config, or 16ms to 55ms for version 2.
Definition at line 1520 of file igb_82575.c.
References E1000_GCR, E1000_GCR_CAP_VER2, E1000_GCR_CMPL_TMOUT_10ms, E1000_GCR_CMPL_TMOUT_MASK, E1000_GCR_CMPL_TMOUT_RESEND, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, igb_read_pcie_cap_reg(), igb_write_pcie_cap_reg(), PCIE_DEVICE_CONTROL2, PCIE_DEVICE_CONTROL2_16ms, u16, and u32.
Referenced by igb_reset_hw_82575().
01521 { 01522 u32 gcr = E1000_READ_REG(hw, E1000_GCR); 01523 s32 ret_val = E1000_SUCCESS; 01524 u16 pcie_devctl2; 01525 01526 /* only take action if timeout value is defaulted to 0 */ 01527 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 01528 goto out; 01529 01530 /* 01531 * if capababilities version is type 1 we can write the 01532 * timeout of 10ms to 200ms through the GCR register 01533 */ 01534 if (!(gcr & E1000_GCR_CAP_VER2)) { 01535 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 01536 goto out; 01537 } 01538 01539 /* 01540 * for version 2 capabilities we need to write the config space 01541 * directly in order to set the completion timeout value for 01542 * 16ms to 55ms 01543 */ 01544 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 01545 &pcie_devctl2); 01546 if (ret_val) 01547 goto out; 01548 01549 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 01550 01551 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 01552 &pcie_devctl2); 01553 out: 01554 /* disable completion timeout resend */ 01555 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 01556 01557 E1000_WRITE_REG(hw, E1000_GCR, gcr); 01558 return ret_val; 01559 }
| void igb_init_function_pointers_82575 | ( | struct e1000_hw * | hw | ) |
igb_init_function_pointers_82575 - Init func ptrs.
: pointer to the HW structure
Called to initialize all function pointers and parameters.
Definition at line 326 of file igb_82575.c.
References DEBUGFUNC, igb_init_mac_params_82575(), igb_init_nvm_params_82575(), igb_init_phy_params_82575(), e1000_mbx_operations::init_params, e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::mbx, e1000_hw::nvm, e1000_mbx_info::ops, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, and e1000_hw::phy.
Referenced by igb_setup_init_funcs().
00327 { 00328 DEBUGFUNC("igb_init_function_pointers_82575"); 00329 00330 hw->mac.ops.init_params = igb_init_mac_params_82575; 00331 hw->nvm.ops.init_params = igb_init_nvm_params_82575; 00332 hw->phy.ops.init_params = igb_init_phy_params_82575; 00333 #if 0 00334 hw->mbx.ops.init_params = igb_init_mbx_params_pf; 00335 #endif 00336 }
| void igb_rx_fifo_flush_82575 | ( | struct e1000_hw * | hw | ) |
igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable : pointer to the HW structure
After rx enable if managability is enabled then there is likely some bad data at the start of the fifo and possibly in the DMA fifo. This function clears the fifos and flushes any packets that came in as rx was being enabled.
Definition at line 1445 of file igb_82575.c.
References DEBUGFUNC, DEBUGOUT, e1000_82575, E1000_MANC, E1000_MANC_RCV_TCO_EN, E1000_MPC, E1000_RCTL, E1000_RCTL_EN, E1000_RCTL_LPE, E1000_RCTL_SBP, E1000_READ_REG, E1000_RFCTL, E1000_RFCTL_LEF, E1000_RLPML, E1000_RNBC, E1000_ROC, E1000_RXDCTL, E1000_RXDCTL_QUEUE_ENABLE, E1000_WRITE_FLUSH, E1000_WRITE_REG, e1000_hw::mac, msec_delay, e1000_mac_info::type, and u32.
01446 { 01447 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 01448 int i, ms_wait; 01449 01450 DEBUGFUNC("igb_rx_fifo_workaround_82575"); 01451 if (hw->mac.type != e1000_82575 || 01452 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 01453 return; 01454 01455 /* Disable all RX queues */ 01456 for (i = 0; i < 4; i++) { 01457 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); 01458 E1000_WRITE_REG(hw, E1000_RXDCTL(i), 01459 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 01460 } 01461 /* Poll all queues to verify they have shut down */ 01462 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 01463 msec_delay(1); 01464 rx_enabled = 0; 01465 for (i = 0; i < 4; i++) 01466 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); 01467 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 01468 break; 01469 } 01470 01471 if (ms_wait == 10) { 01472 DEBUGOUT("Queue disable timed out after 10ms\n"); 01473 } 01474 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 01475 * incoming packets are rejected. Set enable and wait 2ms so that 01476 * any packet that was coming in as RCTL.EN was set is flushed 01477 */ 01478 rfctl = E1000_READ_REG(hw, E1000_RFCTL); 01479 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 01480 01481 rlpml = E1000_READ_REG(hw, E1000_RLPML); 01482 E1000_WRITE_REG(hw, E1000_RLPML, 0); 01483 01484 rctl = E1000_READ_REG(hw, E1000_RCTL); 01485 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 01486 temp_rctl |= E1000_RCTL_LPE; 01487 01488 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); 01489 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); 01490 E1000_WRITE_FLUSH(hw); 01491 msec_delay(2); 01492 01493 /* Enable RX queues that were previously enabled and restore our 01494 * previous state 01495 */ 01496 for (i = 0; i < 4; i++) 01497 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); 01498 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 01499 E1000_WRITE_FLUSH(hw); 01500 01501 E1000_WRITE_REG(hw, E1000_RLPML, rlpml); 01502 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); 01503 01504 /* Flush receive errors generated by workaround */ 01505 E1000_READ_REG(hw, E1000_ROC); 01506 E1000_READ_REG(hw, E1000_RNBC); 01507 E1000_READ_REG(hw, E1000_MPC); 01508 }
igb_vmdq_set_loopback_pf - enable or disable vmdq loopback : pointer to the hardware struct : state to enter, either enabled or disabled
enables/disables L2 switch loopback functionality.
Definition at line 1568 of file igb_82575.c.
References E1000_DTXSWC, E1000_DTXSWC_VMDQ_LOOPBACK_EN, E1000_READ_REG, E1000_WRITE_REG, and u32.
01569 { 01570 u32 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC); 01571 01572 if (enable) 01573 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 01574 else 01575 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 01576 01577 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc); 01578 }
igb_vmdq_set_replication_pf - enable or disable vmdq replication : pointer to the hardware struct : state to enter, either enabled or disabled
enables/disables replication of packets across multiple pools.
Definition at line 1587 of file igb_82575.c.
References E1000_READ_REG, E1000_VT_CTL, E1000_VT_CTL_VM_REPL_EN, E1000_WRITE_REG, and u32.
01588 { 01589 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL); 01590 01591 if (enable) 01592 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 01593 else 01594 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 01595 01596 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl); 01597 }
struct pci_device_id igb_82575_nics[] [static] |
Initial value:
{
PCI_ROM(0x8086, 0x10C9, "E1000_DEV_ID_82576", "E1000_DEV_ID_82576", 0),
PCI_ROM(0x8086, 0x150A, "E1000_DEV_ID_82576_NS", "E1000_DEV_ID_82576_NS", 0),
PCI_ROM(0x8086, 0x1518, "E1000_DEV_ID_82576_NS_SERDES", "E1000_DEV_ID_82576_NS_SERDES", 0),
PCI_ROM(0x8086, 0x10E6, "E1000_DEV_ID_82576_FIBER", "E1000_DEV_ID_82576_FIBER", 0),
PCI_ROM(0x8086, 0x10E7, "E1000_DEV_ID_82576_SERDES", "E1000_DEV_ID_82576_SERDES", 0),
PCI_ROM(0x8086, 0x150D, "E1000_DEV_ID_82576_SERDES_QUAD", "E1000_DEV_ID_82576_SERDES_QUAD", 0),
PCI_ROM(0x8086, 0x10E8, "E1000_DEV_ID_82576_QUAD_COPPER", "E1000_DEV_ID_82576_QUAD_COPPER", 0),
PCI_ROM(0x8086, 0x10A7, "E1000_DEV_ID_82575EB_COPPER", "E1000_DEV_ID_82575EB_COPPER", 0),
PCI_ROM(0x8086, 0x10A9, "E1000_DEV_ID_82575EB_FIBER_SERDES", "E1000_DEV_ID_82575EB_FIBER_SERDES", 0),
PCI_ROM(0x8086, 0x10D6, "E1000_DEV_ID_82575GB_QUAD_COPPER", "E1000_DEV_ID_82575GB_QUAD_COPPER", 0),
}
Definition at line 1599 of file igb_82575.c.
| struct pci_driver igb_82575_driver __pci_driver |
Initial value:
{
.ids = igb_82575_nics,
.id_count = (sizeof (igb_82575_nics) / sizeof (igb_82575_nics[0])),
.probe = igb_probe,
.remove = igb_remove,
}
Definition at line 1612 of file igb_82575.c.
1.5.7.1