epic100.h File Reference

Go to the source code of this file.

Defines

#define PCI_VENDOR_SMC   0x10B8

#define PCI_DEVICE_SMC_EPIC100   0x0005

#define PCI_DEVICE_ID_NONE   0xFFFF

#define CR_STOP_RX   (0x00000001)

#define CR_START_RX   (0x00000002)

#define CR_QUEUE_TX   (0x00000004)

#define CR_QUEUE_RX   (0x00000008)

#define CR_NEXTFRAME   (0x00000010)

#define CR_STOP_TX_DMA   (0x00000020)

#define CR_STOP_RX_DMA   (0x00000040)

#define CR_TX_UGO   (0x00000080)

#define INTR_RX_THR_STA   (0x00400000)

#define INTR_RX_BUFF_EMPTY   (0x00200000)

#define INTR_TX_IN_PROG   (0x00100000)

#define INTR_RX_IN_PROG   (0x00080000)

#define INTR_TXIDLE   (0x00040000)

#define INTR_RXIDLE   (0x00020000)

#define INTR_INTR_ACTIVE   (0x00010000)

#define INTR_RX_STATUS_OK   (0x00008000)

#define INTR_PCI_TGT_ABT   (0x00004000)

#define INTR_PCI_MASTER_ABT   (0x00002000)

#define INTR_PCI_PARITY_ERR   (0x00001000)

#define INTR_PCI_DATA_ERR   (0x00000800)

#define INTR_RX_THR_CROSSED   (0x00000400)

#define INTR_CNTFULL   (0x00000200)

#define INTR_TXUNDERRUN   (0x00000100)

#define INTR_TXEMPTY   (0x00000080)

#define INTR_TX_CH_COMPLETE   (0x00000040)

#define INTR_TXDONE   (0x00000020)

#define INTR_RXERROR   (0x00000010)

#define INTR_RXOVERFLOW   (0x00000008)

#define INTR_RX_QUEUE_EMPTY   (0x00000004)

#define INTR_RXHEADER   (0x00000002)

#define INTR_RXDONE   (0x00000001)

#define INTR_CLEARINTR   (0x00007FFF)

#define INTR_VALIDBITS   (0x007FFFFF)

#define INTR_DISABLE   (0x00000000)

#define INTR_CLEARERRS   (0x00007F18)

#define INTR_ABNINTR   (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW)

#define GC_SOFT_RESET   (0x00000001)

#define GC_INTR_ENABLE   (0x00000002)

#define GC_SOFT_INTR   (0x00000004)

#define GC_POWER_DOWN   (0x00000008)

#define GC_ONE_COPY   (0x00000010)

#define GC_BIG_ENDIAN   (0x00000020)

#define GC_RX_PREEMPT_TX   (0x00000040)

#define GC_TX_PREEMPT_RX   (0x00000080)

#define GC_RX_FIFO_THR_32   (0x00000000)

#define GC_RX_FIFO_THR_64   (0x00000100)

#define GC_RX_FIFO_THR_96   (0x00000200)

#define GC_RX_FIFO_THR_128   (0x00000300)

#define GC_MRC_MEM_READ   (0x00000000)

#define GC_MRC_READ_MULT   (0x00000400)

#define GC_MRC_READ_LINE   (0x00000800)

#define GC_SOFTBIT0   (0x00001000)

#define GC_SOFTBIT1   (0x00002000)

#define GC_RESET_PHY   (0x00004000)

#define RC_SAVE_ERRORED_PKT   (0x00000001)

#define RC_SAVE_RUNT_FRAMES   (0x00000002)

#define RC_RCV_BROADCAST   (0x00000004)

#define RC_RCV_MULTICAST   (0x00000008)

#define RC_RCV_INVERSE_PKT   (0x00000010)

#define RC_PROMISCUOUS_MODE   (0x00000020)

#define RC_MONITOR_MODE   (0x00000040)

#define RC_EARLY_RCV_ENABLE   (0x00000080)

#define RD_FRAGLIST   (0x0001)

#define RD_LLFORM   (0x0002)

#define RD_HDR_CPY   (0x0004)

#define TC_EARLY_TX_ENABLE   (0x00000001)

#define TC_LM_NORMAL   (0x00000000)

#define TC_LM_INTERNAL   (0x00000002)

#define TC_LM_EXTERNAL   (0x00000004)

#define TC_LM_FULL_DPX   (0x00000006)

#define TX_SLOT_TIME   (0x00000078)

#define TX_FIFO_THRESH   128

#define RRING_PKT_INTACT   (0x0001)

#define RRING_ALIGN_ERR   (0x0002)

#define RRING_CRC_ERR   (0x0004)

#define RRING_MISSED_PKT   (0x0008)

#define RRING_MULTICAST   (0x0010)

#define RRING_BROADCAST   (0x0020)

#define RRING_RECEIVER_DISABLE   (0x0040)

#define RRING_STATUS_VALID   (0x1000)

#define RRING_FRAGLIST_ERR   (0x2000)

#define RRING_HDR_COPIED   (0x4000)

#define RRING_OWN   (0x8000)

#define RRING_ERROR   (RRING_ALIGN_ERR|RRING_CRC_ERR)

#define TRING_PKT_INTACT   (0x0001)

#define TRING_PKT_NONDEFER   (0x0002)

#define TRING_COLL   (0x0004)

#define TRING_CARR   (0x0008)

#define TRING_UNDERRUN   (0x0010)

#define TRING_HB_COLL   (0x0020)

#define TRING_WIN_COLL   (0x0040)

#define TRING_DEFERRED   (0x0080)

#define TRING_COLL_COUNT   (0x0F00)

#define TRING_COLL_EXCESS   (0x1000)

#define TRING_OWN   (0x8000)

#define TRING_ABORT   (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN)

#define TRING_ERROR   (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR/*|TRING_COLL*/ )

#define TD_FRAGLIST   (0x0001)

#define TD_LLFORM   (0x0002)

#define TD_IAF   (0x0004)

#define TD_NOCRC   (0x0008)

#define TD_LASTDESC   (0x0010)

Enumerations

enum epic100_registers {
  COMMAND = 0, INTSTAT = 4, INTMASK = 8, GENCTL = 0x0C,
  NVCTL = 0x10, EECTL = 0x14, TEST = 0x1C, CRCCNT = 0x20,
  ALICNT = 0x24, MPCNT = 0x28, MMCTL = 0x30, MMDATA = 0x34,
  MIICFG = 0x38, IPG = 0x3C, LAN0 = 0x40, IDCHK = 0x4C,
  MC0 = 0x50, RXCON = 0x60, TXCON = 0x70, TXSTAT = 0x74,
  PRCDAR = 0x84, PRSTAT = 0xA4, PRCPTHR = 0xB0, PTCDAR = 0xC4,
  ETHTHR = 0xDC
}

Functions

FILE_LICENCE (GPL2_OR_LATER)

Define Documentation

#define PCI_VENDOR_SMC 0x10B8

Definition at line 7 of file epic100.h.

#define PCI_DEVICE_SMC_EPIC100 0x0005

Definition at line 11 of file epic100.h.

#define PCI_DEVICE_ID_NONE 0xFFFF

Definition at line 14 of file epic100.h.

#define CR_STOP_RX (0x00000001)

Definition at line 46 of file epic100.h.

#define CR_START_RX (0x00000002)

Definition at line 47 of file epic100.h.

Referenced by epic100_open(), and epic100_poll().

#define CR_QUEUE_TX (0x00000004)

Definition at line 48 of file epic100.h.

Referenced by epic100_transmit().

#define CR_QUEUE_RX (0x00000008)

Definition at line 49 of file epic100.h.

Referenced by epic100_open(), and epic100_poll().

#define CR_NEXTFRAME (0x00000010)

Definition at line 50 of file epic100.h.

#define CR_STOP_TX_DMA (0x00000020)

Definition at line 51 of file epic100.h.

#define CR_STOP_RX_DMA (0x00000040)

Definition at line 52 of file epic100.h.

#define CR_TX_UGO (0x00000080)

Definition at line 53 of file epic100.h.

#define INTR_RX_THR_STA (0x00400000)

Definition at line 57 of file epic100.h.

#define INTR_RX_BUFF_EMPTY (0x00200000)

Definition at line 58 of file epic100.h.

#define INTR_TX_IN_PROG (0x00100000)

Definition at line 59 of file epic100.h.

#define INTR_RX_IN_PROG (0x00080000)

Definition at line 60 of file epic100.h.

#define INTR_TXIDLE (0x00040000)

Definition at line 61 of file epic100.h.

#define INTR_RXIDLE (0x00020000)

Definition at line 62 of file epic100.h.

#define INTR_INTR_ACTIVE (0x00010000)

Definition at line 63 of file epic100.h.

#define INTR_RX_STATUS_OK (0x00008000)

Definition at line 64 of file epic100.h.

#define INTR_PCI_TGT_ABT (0x00004000)

Definition at line 65 of file epic100.h.

#define INTR_PCI_MASTER_ABT (0x00002000)

Definition at line 66 of file epic100.h.

#define INTR_PCI_PARITY_ERR (0x00001000)

Definition at line 67 of file epic100.h.

#define INTR_PCI_DATA_ERR (0x00000800)

Definition at line 68 of file epic100.h.

#define INTR_RX_THR_CROSSED (0x00000400)

Definition at line 69 of file epic100.h.

#define INTR_CNTFULL (0x00000200)

Definition at line 70 of file epic100.h.

#define INTR_TXUNDERRUN (0x00000100)

Definition at line 71 of file epic100.h.

#define INTR_TXEMPTY (0x00000080)

Definition at line 72 of file epic100.h.

#define INTR_TX_CH_COMPLETE (0x00000040)

Definition at line 73 of file epic100.h.

#define INTR_TXDONE (0x00000020)

Definition at line 74 of file epic100.h.

#define INTR_RXERROR (0x00000010)

Definition at line 75 of file epic100.h.

#define INTR_RXOVERFLOW (0x00000008)

Definition at line 76 of file epic100.h.

#define INTR_RX_QUEUE_EMPTY (0x00000004)

Definition at line 77 of file epic100.h.

#define INTR_RXHEADER (0x00000002)

Definition at line 78 of file epic100.h.

#define INTR_RXDONE (0x00000001)

Definition at line 79 of file epic100.h.

#define INTR_CLEARINTR (0x00007FFF)

Definition at line 81 of file epic100.h.

#define INTR_VALIDBITS (0x007FFFFF)

Definition at line 82 of file epic100.h.

#define INTR_DISABLE (0x00000000)

Definition at line 83 of file epic100.h.

Referenced by epic100_probe().

#define INTR_CLEARERRS (0x00007F18)

Definition at line 84 of file epic100.h.

Referenced by epic100_poll().

#define INTR_ABNINTR (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW)

Definition at line 85 of file epic100.h.

#define GC_SOFT_RESET (0x00000001)

Definition at line 89 of file epic100.h.

Referenced by epic100_disable(), and epic100_probe().

#define GC_INTR_ENABLE (0x00000002)

Definition at line 90 of file epic100.h.

#define GC_SOFT_INTR (0x00000004)

Definition at line 91 of file epic100.h.

#define GC_POWER_DOWN (0x00000008)

Definition at line 92 of file epic100.h.

#define GC_ONE_COPY (0x00000010)

Definition at line 93 of file epic100.h.

Referenced by epic100_open().

#define GC_BIG_ENDIAN (0x00000020)

Definition at line 94 of file epic100.h.

#define GC_RX_PREEMPT_TX (0x00000040)

Definition at line 95 of file epic100.h.

#define GC_TX_PREEMPT_RX (0x00000080)

Definition at line 96 of file epic100.h.

#define GC_RX_FIFO_THR_32 (0x00000000)

Definition at line 105 of file epic100.h.

#define GC_RX_FIFO_THR_64 (0x00000100)

Definition at line 106 of file epic100.h.

Referenced by epic100_open().

#define GC_RX_FIFO_THR_96 (0x00000200)

Definition at line 107 of file epic100.h.

#define GC_RX_FIFO_THR_128 (0x00000300)

Definition at line 108 of file epic100.h.

#define GC_MRC_MEM_READ (0x00000000)

Definition at line 111 of file epic100.h.

#define GC_MRC_READ_MULT (0x00000400)

Definition at line 112 of file epic100.h.

Referenced by epic100_open().

#define GC_MRC_READ_LINE (0x00000800)

Definition at line 113 of file epic100.h.

#define GC_SOFTBIT0 (0x00001000)

Definition at line 115 of file epic100.h.

#define GC_SOFTBIT1 (0x00002000)

Definition at line 116 of file epic100.h.

#define GC_RESET_PHY (0x00004000)

Definition at line 117 of file epic100.h.

#define RC_SAVE_ERRORED_PKT (0x00000001)

Definition at line 121 of file epic100.h.

#define RC_SAVE_RUNT_FRAMES (0x00000002)

Definition at line 122 of file epic100.h.

#define RC_RCV_BROADCAST (0x00000004)

Definition at line 123 of file epic100.h.

#define RC_RCV_MULTICAST (0x00000008)

Definition at line 124 of file epic100.h.

#define RC_RCV_INVERSE_PKT (0x00000010)

Definition at line 125 of file epic100.h.

#define RC_PROMISCUOUS_MODE (0x00000020)

Definition at line 126 of file epic100.h.

#define RC_MONITOR_MODE (0x00000040)

Definition at line 127 of file epic100.h.

#define RC_EARLY_RCV_ENABLE (0x00000080)

Definition at line 128 of file epic100.h.

#define RD_FRAGLIST (0x0001)

Definition at line 131 of file epic100.h.

#define RD_LLFORM (0x0002)

Definition at line 132 of file epic100.h.

#define RD_HDR_CPY (0x0004)

Definition at line 133 of file epic100.h.

#define TC_EARLY_TX_ENABLE (0x00000001)

Definition at line 137 of file epic100.h.

Referenced by epic100_open().

#define TC_LM_NORMAL (0x00000000)

Definition at line 140 of file epic100.h.

Referenced by epic100_open().

#define TC_LM_INTERNAL (0x00000002)

Definition at line 141 of file epic100.h.

#define TC_LM_EXTERNAL (0x00000004)

Definition at line 142 of file epic100.h.

#define TC_LM_FULL_DPX (0x00000006)

Definition at line 143 of file epic100.h.

Referenced by epic100_open().

#define TX_SLOT_TIME (0x00000078)

Definition at line 145 of file epic100.h.

Referenced by epic100_open().

#define TX_FIFO_THRESH 128

Definition at line 148 of file epic100.h.

Referenced by epic100_open(), and rtl_transmit().

#define RRING_PKT_INTACT (0x0001)

Definition at line 151 of file epic100.h.

#define RRING_ALIGN_ERR (0x0002)

Definition at line 152 of file epic100.h.

#define RRING_CRC_ERR (0x0004)

Definition at line 153 of file epic100.h.

#define RRING_MISSED_PKT (0x0008)

Definition at line 154 of file epic100.h.

#define RRING_MULTICAST (0x0010)

Definition at line 155 of file epic100.h.

#define RRING_BROADCAST (0x0020)

Definition at line 156 of file epic100.h.

#define RRING_RECEIVER_DISABLE (0x0040)

Definition at line 157 of file epic100.h.

#define RRING_STATUS_VALID (0x1000)

Definition at line 158 of file epic100.h.

#define RRING_FRAGLIST_ERR (0x2000)

Definition at line 159 of file epic100.h.

#define RRING_HDR_COPIED (0x4000)

Definition at line 160 of file epic100.h.

#define RRING_OWN (0x8000)

Definition at line 161 of file epic100.h.

Referenced by epic100_init_ring(), and epic100_poll().

#define RRING_ERROR (RRING_ALIGN_ERR|RRING_CRC_ERR)

Definition at line 164 of file epic100.h.

#define TRING_PKT_INTACT (0x0001)

Definition at line 167 of file epic100.h.

#define TRING_PKT_NONDEFER (0x0002)

Definition at line 168 of file epic100.h.

#define TRING_COLL (0x0004)

Definition at line 169 of file epic100.h.

#define TRING_CARR (0x0008)

Definition at line 170 of file epic100.h.

#define TRING_UNDERRUN (0x0010)

Definition at line 171 of file epic100.h.

#define TRING_HB_COLL (0x0020)

Definition at line 172 of file epic100.h.

#define TRING_WIN_COLL (0x0040)

Definition at line 173 of file epic100.h.

#define TRING_DEFERRED (0x0080)

Definition at line 174 of file epic100.h.

#define TRING_COLL_COUNT (0x0F00)

Definition at line 175 of file epic100.h.

#define TRING_COLL_EXCESS (0x1000)

Definition at line 176 of file epic100.h.

#define TRING_OWN (0x8000)

Definition at line 177 of file epic100.h.

Referenced by epic100_transmit().

#define TRING_ABORT (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN)

Definition at line 180 of file epic100.h.

#define TRING_ERROR (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR/*|TRING_COLL*/ )

Definition at line 181 of file epic100.h.

#define TD_FRAGLIST (0x0001)

Definition at line 184 of file epic100.h.

#define TD_LLFORM (0x0002)

Definition at line 185 of file epic100.h.

#define TD_IAF (0x0004)

Definition at line 186 of file epic100.h.

#define TD_NOCRC (0x0008)

Definition at line 187 of file epic100.h.

#define TD_LASTDESC (0x0010)

Definition at line 188 of file epic100.h.

Enumeration Type Documentation

enum epic100_registers

Enumerator:

COMMAND
INTSTAT
INTMASK
GENCTL
NVCTL
EECTL
TEST
CRCCNT
ALICNT
MPCNT
MMCTL
MMDATA
MIICFG
IPG
LAN0
IDCHK
MC0
RXCON
TXCON
TXSTAT
PRCDAR
PRSTAT
PRCPTHR
PTCDAR
ETHTHR

Definition at line 17 of file epic100.h.

00017                        {
00018     COMMAND= 0,         /* Control Register */
00019     INTSTAT= 4,         /* Interrupt Status */
00020     INTMASK= 8,         /* Interrupt Mask */
00021     GENCTL = 0x0C,      /* General Control */
00022     NVCTL  = 0x10,      /* Non Volatile Control */
00023     EECTL  = 0x14,      /* EEPROM Control  */
00024     TEST   = 0x1C,      /* Test register: marked as reserved (see in source code) */
00025     CRCCNT = 0x20,      /* CRC Error Counter */
00026     ALICNT = 0x24,      /* Frame Alignment Error Counter */
00027     MPCNT  = 0x28,      /* Missed Packet Counter */
00028     MMCTL  = 0x30,      /* MII Management Interface Control */
00029     MMDATA = 0x34,      /* MII Management Interface Data */
00030     MIICFG = 0x38,      /* MII Configuration */
00031     IPG    = 0x3C,      /* InterPacket Gap */
00032     LAN0   = 0x40,      /* MAC address. (0x40-0x48) */
00033     IDCHK  = 0x4C,      /* BoardID/ Checksum */
00034     MC0    = 0x50,      /* Multicast filter table. (0x50-0x5c) */
00035     RXCON  = 0x60,      /* Receive Control */
00036     TXCON  = 0x70,      /* Transmit Control */
00037     TXSTAT = 0x74,      /* Transmit Status */
00038     PRCDAR = 0x84,      /* PCI Receive Current Descriptor Address */
00039     PRSTAT = 0xA4,      /* PCI Receive DMA Status */
00040     PRCPTHR= 0xB0,      /* PCI Receive Copy Threshold */
00041     PTCDAR = 0xC4,      /* PCI Transmit Current Descriptor Address */
00042     ETHTHR = 0xDC       /* Early Transmit Threshold */
00043 };

Function Documentation

FILE_LICENCE ( GPL2_OR_LATER )


Defines
#define	PCI_VENDOR_SMC 0x10B8
#define	PCI_DEVICE_SMC_EPIC100 0x0005
#define	PCI_DEVICE_ID_NONE 0xFFFF
#define	CR_STOP_RX (0x00000001)
#define	CR_START_RX (0x00000002)
#define	CR_QUEUE_TX (0x00000004)
#define	CR_QUEUE_RX (0x00000008)
#define	CR_NEXTFRAME (0x00000010)
#define	CR_STOP_TX_DMA (0x00000020)
#define	CR_STOP_RX_DMA (0x00000040)
#define	CR_TX_UGO (0x00000080)
#define	INTR_RX_THR_STA (0x00400000)
#define	INTR_RX_BUFF_EMPTY (0x00200000)
#define	INTR_TX_IN_PROG (0x00100000)
#define	INTR_RX_IN_PROG (0x00080000)
#define	INTR_TXIDLE (0x00040000)
#define	INTR_RXIDLE (0x00020000)
#define	INTR_INTR_ACTIVE (0x00010000)
#define	INTR_RX_STATUS_OK (0x00008000)
#define	INTR_PCI_TGT_ABT (0x00004000)
#define	INTR_PCI_MASTER_ABT (0x00002000)
#define	INTR_PCI_PARITY_ERR (0x00001000)
#define	INTR_PCI_DATA_ERR (0x00000800)
#define	INTR_RX_THR_CROSSED (0x00000400)
#define	INTR_CNTFULL (0x00000200)
#define	INTR_TXUNDERRUN (0x00000100)
#define	INTR_TXEMPTY (0x00000080)
#define	INTR_TX_CH_COMPLETE (0x00000040)
#define	INTR_TXDONE (0x00000020)
#define	INTR_RXERROR (0x00000010)
#define	INTR_RXOVERFLOW (0x00000008)
#define	INTR_RX_QUEUE_EMPTY (0x00000004)
#define	INTR_RXHEADER (0x00000002)
#define	INTR_RXDONE (0x00000001)
#define	INTR_CLEARINTR (0x00007FFF)
#define	INTR_VALIDBITS (0x007FFFFF)
#define	INTR_DISABLE (0x00000000)
#define	INTR_CLEARERRS (0x00007F18)
#define	INTR_ABNINTR (INTR_CNTFULL \| INTR_TXUNDERRUN \| INTR_RXOVERFLOW)
#define	GC_SOFT_RESET (0x00000001)
#define	GC_INTR_ENABLE (0x00000002)
#define	GC_SOFT_INTR (0x00000004)
#define	GC_POWER_DOWN (0x00000008)
#define	GC_ONE_COPY (0x00000010)
#define	GC_BIG_ENDIAN (0x00000020)
#define	GC_RX_PREEMPT_TX (0x00000040)
#define	GC_TX_PREEMPT_RX (0x00000080)
#define	GC_RX_FIFO_THR_32 (0x00000000)
#define	GC_RX_FIFO_THR_64 (0x00000100)
#define	GC_RX_FIFO_THR_96 (0x00000200)
#define	GC_RX_FIFO_THR_128 (0x00000300)
#define	GC_MRC_MEM_READ (0x00000000)
#define	GC_MRC_READ_MULT (0x00000400)
#define	GC_MRC_READ_LINE (0x00000800)
#define	GC_SOFTBIT0 (0x00001000)
#define	GC_SOFTBIT1 (0x00002000)
#define	GC_RESET_PHY (0x00004000)
#define	RC_SAVE_ERRORED_PKT (0x00000001)
#define	RC_SAVE_RUNT_FRAMES (0x00000002)
#define	RC_RCV_BROADCAST (0x00000004)
#define	RC_RCV_MULTICAST (0x00000008)
#define	RC_RCV_INVERSE_PKT (0x00000010)
#define	RC_PROMISCUOUS_MODE (0x00000020)
#define	RC_MONITOR_MODE (0x00000040)
#define	RC_EARLY_RCV_ENABLE (0x00000080)
#define	RD_FRAGLIST (0x0001)
#define	RD_LLFORM (0x0002)
#define	RD_HDR_CPY (0x0004)
#define	TC_EARLY_TX_ENABLE (0x00000001)
#define	TC_LM_NORMAL (0x00000000)
#define	TC_LM_INTERNAL (0x00000002)
#define	TC_LM_EXTERNAL (0x00000004)
#define	TC_LM_FULL_DPX (0x00000006)
#define	TX_SLOT_TIME (0x00000078)
#define	TX_FIFO_THRESH 128
#define	RRING_PKT_INTACT (0x0001)
#define	RRING_ALIGN_ERR (0x0002)
#define	RRING_CRC_ERR (0x0004)
#define	RRING_MISSED_PKT (0x0008)
#define	RRING_MULTICAST (0x0010)
#define	RRING_BROADCAST (0x0020)
#define	RRING_RECEIVER_DISABLE (0x0040)
#define	RRING_STATUS_VALID (0x1000)
#define	RRING_FRAGLIST_ERR (0x2000)
#define	RRING_HDR_COPIED (0x4000)
#define	RRING_OWN (0x8000)
#define	RRING_ERROR (RRING_ALIGN_ERR\|RRING_CRC_ERR)
#define	TRING_PKT_INTACT (0x0001)
#define	TRING_PKT_NONDEFER (0x0002)
#define	TRING_COLL (0x0004)
#define	TRING_CARR (0x0008)
#define	TRING_UNDERRUN (0x0010)
#define	TRING_HB_COLL (0x0020)
#define	TRING_WIN_COLL (0x0040)
#define	TRING_DEFERRED (0x0080)
#define	TRING_COLL_COUNT (0x0F00)
#define	TRING_COLL_EXCESS (0x1000)
#define	TRING_OWN (0x8000)
#define	TRING_ABORT (TRING_COLL_EXCESS\|TRING_WIN_COLL\|TRING_UNDERRUN)
#define	TRING_ERROR (TRING_DEFERRED\|TRING_WIN_COLL\|TRING_UNDERRUN\|TRING_CARR/\|TRING_COLL/ )
#define	TD_FRAGLIST (0x0001)
#define	TD_LLFORM (0x0002)
#define	TD_IAF (0x0004)
#define	TD_NOCRC (0x0008)
#define	TD_LASTDESC (0x0010)
Enumerations
enum	epic100_registers { COMMAND = 0, INTSTAT = 4, INTMASK = 8, GENCTL = 0x0C, NVCTL = 0x10, EECTL = 0x14, TEST = 0x1C, CRCCNT = 0x20, ALICNT = 0x24, MPCNT = 0x28, MMCTL = 0x30, MMDATA = 0x34, MIICFG = 0x38, IPG = 0x3C, LAN0 = 0x40, IDCHK = 0x4C, MC0 = 0x50, RXCON = 0x60, TXCON = 0x70, TXSTAT = 0x74, PRCDAR = 0x84, PRSTAT = 0xA4, PRCPTHR = 0xB0, PTCDAR = 0xC4, ETHTHR = 0xDC }
Functions
	FILE_LICENCE (GPL2_OR_LATER)