|
Defines |
| #define | LAN595 0 |
| #define | LAN595TX 1 |
| #define | LAN595FX 2 |
| #define | LAN595FX_10ISA 3 |
| #define | SLOW_DOWN inb(0x80); |
| #define | SA_ADDR0 0x00 |
| #define | SA_ADDR1 0xaa |
| #define | SA_ADDR2 0x00 |
| #define | GetBit(x, y) ((x & (1<<y))>>y) |
| #define | ee_PnP 0 |
| #define | ee_Word1 1 |
| #define | ee_BusWidth 2 |
| #define | ee_FlashAddr 3 |
| #define | ee_FlashMask 0x7 |
| #define | ee_AutoIO 6 |
| #define | ee_reserved0 7 |
| #define | ee_Flash 8 |
| #define | ee_AutoNeg 9 |
| #define | ee_IO0 10 |
| #define | ee_IO0Mask 0x |
| #define | ee_IO1 15 |
| #define | ee_IntSel 0 |
| #define | ee_IntMask 0x7 |
| #define | ee_LI 3 |
| #define | ee_PC 4 |
| #define | ee_TPE_AUI 5 |
| #define | ee_Jabber 6 |
| #define | ee_AutoPort 7 |
| #define | ee_SMOUT 8 |
| #define | ee_PROM 9 |
| #define | ee_reserved1 10 |
| #define | ee_AltReady 13 |
| #define | ee_reserved2 14 |
| #define | ee_Duplex 15 |
| #define | ee_IA5 0 |
| #define | ee_IA4 8 |
| #define | ee_IA3 0 |
| #define | ee_IA2 8 |
| #define | ee_IA1 0 |
| #define | ee_IA0 8 |
| #define | ee_BNC_TPE 0 |
| #define | ee_BootType 1 |
| #define | ee_BootTypeMask 0x3 |
| #define | ee_NumConn 3 |
| #define | ee_FlashSock 4 |
| #define | ee_PortTPE 5 |
| #define | ee_PortBNC 6 |
| #define | ee_PortAUI 7 |
| #define | ee_PowerMgt 10 |
| #define | ee_CP 13 |
| #define | ee_CPMask 0x7 |
| #define | ee_Stepping 0 |
| #define | ee_StepMask 0x0F |
| #define | ee_BoardID 4 |
| #define | ee_BoardMask 0x0FFF |
| #define | ee_INT_TO_IRQ 0 |
| #define | ee_FX_INT2IRQ 0x1EB8 |
| #define | ee_SIZE 0x40 |
| #define | ee_Checksum 0xBABA |
| #define | ee_addr_vendor 0x10 |
| #define | ee_addr_id 0x11 |
| #define | ee_addr_SN 0x12 |
| #define | ee_addr_CRC_8 0x14 |
| #define | ee_vendor_intel0 0x25 |
| #define | ee_vendor_intel1 0xD4 |
| #define | ee_id_eepro10p0 0x10 |
| #define | ee_id_eepro10p1 0x31 |
| #define | RAM_SIZE 0x8000 |
| #define | RCV_HEADER 8 |
| #define | RCV_DEFAULT_RAM 0x6000 |
| #define | RCV_RAM rcv_ram |
| #define | XMT_HEADER 8 |
| #define | XMT_RAM (RAM_SIZE - RCV_RAM) |
| #define | XMT_START ((rcv_start + RCV_RAM) % RAM_SIZE) |
| #define | RCV_LOWER_LIMIT (rcv_start >> 8) |
| #define | RCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8) |
| #define | XMT_LOWER_LIMIT (XMT_START >> 8) |
| #define | XMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8) |
| #define | RCV_START_PRO 0x00 |
| #define | RCV_START_10 XMT_RAM |
| #define | RCV_DONE 0x0008 |
| #define | RX_OK 0x2000 |
| #define | RX_ERROR 0x0d81 |
| #define | TX_DONE_BIT 0x0080 |
| #define | CHAIN_BIT 0x8000 |
| #define | XMT_STATUS 0x02 |
| #define | XMT_CHAIN 0x04 |
| #define | XMT_COUNT 0x06 |
| #define | BANK0_SELECT 0x00 |
| #define | BANK1_SELECT 0x40 |
| #define | BANK2_SELECT 0x80 |
| #define | COMMAND_REG 0x00 |
| #define | MC_SETUP 0x03 |
| #define | XMT_CMD 0x04 |
| #define | DIAGNOSE_CMD 0x07 |
| #define | RCV_ENABLE_CMD 0x08 |
| #define | RCV_DISABLE_CMD 0x0a |
| #define | STOP_RCV_CMD 0x0b |
| #define | RESET_CMD 0x0e |
| #define | POWER_DOWN_CMD 0x18 |
| #define | RESUME_XMT_CMD 0x1c |
| #define | SEL_RESET_CMD 0x1e |
| #define | STATUS_REG 0x01 |
| #define | RX_INT 0x02 |
| #define | TX_INT 0x04 |
| #define | EXEC_STATUS 0x30 |
| #define | ID_REG 0x02 |
| #define | R_ROBIN_BITS 0xc0 |
| #define | ID_REG_MASK 0x2c |
| #define | ID_REG_SIG 0x24 |
| #define | AUTO_ENABLE 0x10 |
| #define | INT_MASK_REG 0x03 |
| #define | RX_STOP_MASK 0x01 |
| #define | RX_MASK 0x02 |
| #define | TX_MASK 0x04 |
| #define | EXEC_MASK 0x08 |
| #define | ALL_MASK 0x0f |
| #define | IO_32_BIT 0x10 |
| #define | RCV_BAR 0x04 |
| #define | RCV_STOP 0x06 |
| #define | XMT_BAR_PRO 0x0a |
| #define | XMT_BAR_10 0x0b |
| #define | HOST_ADDRESS_REG 0x0c |
| #define | IO_PORT 0x0e |
| #define | IO_PORT_32_BIT 0x0c |
| #define | REG1 0x01 |
| #define | WORD_WIDTH 0x02 |
| #define | INT_ENABLE 0x80 |
| #define | INT_NO_REG 0x02 |
| #define | RCV_LOWER_LIMIT_REG 0x08 |
| #define | RCV_UPPER_LIMIT_REG 0x09 |
| #define | XMT_LOWER_LIMIT_REG_PRO 0x0a |
| #define | XMT_UPPER_LIMIT_REG_PRO 0x0b |
| #define | XMT_LOWER_LIMIT_REG_10 0x0b |
| #define | XMT_UPPER_LIMIT_REG_10 0x0a |
| #define | XMT_Chain_Int 0x20 |
| #define | XMT_Chain_ErrStop 0x40 |
| #define | RCV_Discard_BadFrame 0x80 |
| #define | REG2 0x02 |
| #define | PRMSC_Mode 0x01 |
| #define | Multi_IA 0x20 |
| #define | REG3 0x03 |
| #define | TPE_BIT 0x04 |
| #define | BNC_BIT 0x20 |
| #define | REG13 0x0d |
| #define | FDX 0x00 |
| #define | A_N_ENABLE 0x02 |
| #define | I_ADD_REG0 0x04 |
| #define | I_ADD_REG1 0x05 |
| #define | I_ADD_REG2 0x06 |
| #define | I_ADD_REG3 0x07 |
| #define | I_ADD_REG4 0x08 |
| #define | I_ADD_REG5 0x09 |
| #define | EEPROM_REG_PRO 0x0a |
| #define | EEPROM_REG_10 0x0b |
| #define | EESK 0x01 |
| #define | EECS 0x02 |
| #define | EEDI 0x04 |
| #define | EEDO 0x08 |
| #define | eeprom_delay() { udelay(40); } |
| #define | EE_READ_CMD (6 << 6) |
| #define | eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(255); |
| #define | eepro_sel_reset(ioaddr) |
| #define | eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG) |
| #define | eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr) |
| #define | eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr) |
| #define | eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr) |
| #define | eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr) |
| #define | eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr) |
Functions |
| | FILE_LICENCE (GPL2_OR_LATER) |
| static void | eepro_reset (struct nic *nic) |
| static int | eepro_poll (struct nic *nic, int retrieve) |
| static void | eepro_transmit (struct nic *nic, const char *d, unsigned int t, unsigned int s, const char *p) |
| static void | eepro_disable (struct nic *nic, struct isa_device *isa __unused) |
| static void | eepro_irq (struct nic *nic __unused, irq_action_t action __unused) |
| static int | read_eeprom (uint16_t ioaddr, int location) |
| static int | eepro_probe1 (isa_probe_addr_t ioaddr) |
| static int | eepro_probe (struct nic *nic, struct isa_device *isa) |
| | ISA_DRIVER (eepro_driver, eepro_probe_addrs, eepro_probe1, GENERIC_ISAPNP_VENDOR, 0x828a) |
| | DRIVER ("eepro", nic_driver, isa_driver, eepro_driver, eepro_probe, eepro_disable) |
| | ISA_ROM ("eepro","Intel Etherexpress Pro/10") |
Variables |
| static unsigned | rcv_ram = RCV_DEFAULT_RAM |
| static unsigned | rcv_start = RCV_START_PRO |
| static unsigned | xmt_bar = XMT_BAR_PRO |
| static unsigned | xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_PRO |
| static unsigned | xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_PRO |
| static unsigned | eeprom_reg = EEPROM_REG_PRO |
| static unsigned int | rx_start |
| static unsigned int | tx_start |
| static int | tx_last |
| static unsigned int | tx_end |
| static int | eepro = 0 |
| static unsigned int | mem_start |
| static unsigned int | mem_end = RCV_DEFAULT_RAM / 1024 |
| static struct nic_operations | eepro_operations |
| static isa_probe_addr_t | eepro_probe_addrs [] |
| static void eepro_reset |
( |
struct nic * |
nic |
) |
[static] |
Definition at line 300 of file eepro.c.
References DBG, eepro_clear_int, eepro_en_rx, eepro_sel_reset, eepro_sw2bank0, eepro_sw2bank1, eepro_sw2bank2, eeprom_reg, ETH_ALEN, HOST_ADDRESS_REG, I_ADD_REG0, inb, IO_PORT, nic::ioaddr, nic::node_addr, outb, outw, RCV_BAR, RCV_Discard_BadFrame, RCV_LOWER_LIMIT, RCV_LOWER_LIMIT_REG, RCV_STOP, RCV_UPPER_LIMIT, RCV_UPPER_LIMIT_REG, REG1, REG2, REG3, rx_start, tx_end, tx_last, tx_start, xmt_bar, XMT_Chain_ErrStop, XMT_Chain_Int, XMT_LOWER_LIMIT, xmt_lower_limit_reg, XMT_UPPER_LIMIT, and xmt_upper_limit_reg.
Referenced by eepro_probe().
00301 {
00302 int temp_reg, i;
00303
00304
00305 eepro_sw2bank2(nic->ioaddr);
00306 temp_reg = inb(nic->ioaddr + eeprom_reg);
00307 DBG("Stepping %d\n", temp_reg >> 5);
00308 if (temp_reg & 0x10)
00309 outb(temp_reg & 0xEF, nic->ioaddr + eeprom_reg);
00310 for (i = 0; i < ETH_ALEN; i++)
00311 outb(nic->node_addr[i], nic->ioaddr + I_ADD_REG0 + i);
00312 temp_reg = inb(nic->ioaddr + REG1);
00313
00314 outb(temp_reg | XMT_Chain_Int | XMT_Chain_ErrStop
00315 | RCV_Discard_BadFrame, nic->ioaddr + REG1);
00316 temp_reg = inb(nic->ioaddr + REG2);
00317 outb(temp_reg | 0x14, nic->ioaddr + REG2);
00318 temp_reg = inb(nic->ioaddr + REG3);
00319 outb(temp_reg & 0x3F, nic->ioaddr + REG3);
00320
00321 eepro_sw2bank1(nic->ioaddr);
00322
00323 outb(RCV_LOWER_LIMIT, nic->ioaddr + RCV_LOWER_LIMIT_REG);
00324 outb(RCV_UPPER_LIMIT, nic->ioaddr + RCV_UPPER_LIMIT_REG);
00325 outb(XMT_LOWER_LIMIT, nic->ioaddr + xmt_lower_limit_reg);
00326 outb(XMT_UPPER_LIMIT, nic->ioaddr + xmt_upper_limit_reg);
00327 eepro_sw2bank0(nic->ioaddr);
00328 eepro_clear_int(nic->ioaddr);
00329
00330 outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR);
00331 outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP);
00332
00333 outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG);
00334 outw(0, nic->ioaddr + IO_PORT);
00335
00336 outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar);
00337 eepro_sel_reset(nic->ioaddr);
00338 tx_start = tx_end = (unsigned int) (XMT_LOWER_LIMIT << 8);
00339 tx_last = 0;
00340 eepro_en_rx(nic->ioaddr);
00341 }
| static int eepro_poll |
( |
struct nic * |
nic, |
|
|
int |
retrieve | |
|
) |
| | [static] |
Definition at line 346 of file eepro.c.
References HOST_ADDRESS_REG, inb, insw, inw, IO_PORT, nic::ioaddr, outb, outw, nic::packet, nic::packetlen, printf(), putchar(), RCV_DONE, RCV_HEADER, RCV_STOP, RCV_UPPER_LIMIT, RX_ERROR, RX_OK, rx_start, and STATUS_REG.
00347 {
00348 unsigned int rcv_car = rx_start;
00349 unsigned int rcv_event, rcv_status, rcv_next_frame, rcv_size;
00350
00351
00352
00353
00354 #if 0
00355 if ((inb(nic->ioaddr + STATUS_REG) & 0x40) == 0)
00356 return (0);
00357 outb(0x40, nic->ioaddr + STATUS_REG);
00358 #endif
00359 outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG);
00360 rcv_event = inw(nic->ioaddr + IO_PORT);
00361 if (rcv_event != RCV_DONE)
00362 return (0);
00363
00364
00365
00366
00367 if ( ! retrieve ) return 1;
00368
00369 rcv_status = inw(nic->ioaddr + IO_PORT);
00370 rcv_next_frame = inw(nic->ioaddr + IO_PORT);
00371 rcv_size = inw(nic->ioaddr + IO_PORT);
00372 #if 0
00373 printf("%hX %hX %d %hhX\n", rcv_status, rcv_next_frame, rcv_size,
00374 inb(nic->ioaddr + STATUS_REG));
00375 #endif
00376 if ((rcv_status & (RX_OK|RX_ERROR)) != RX_OK) {
00377 printf("Receive error %hX\n", rcv_status);
00378 return (0);
00379 }
00380 rcv_size &= 0x3FFF;
00381 insw(nic->ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1));
00382 #if 0
00383 {
00384 int i;
00385 for (i = 0; i < 48; i++) {
00386 printf("%hhX", nic->packet[i]);
00387 putchar(i % 16 == 15 ? '\n' : ' ');
00388 }
00389 }
00390 #endif
00391 nic->packetlen = rcv_size;
00392 rcv_car = (rx_start + RCV_HEADER + rcv_size);
00393 rx_start = rcv_next_frame;
00394
00395
00396
00397
00398 if (rcv_car == 0)
00399 rcv_car = ((RCV_UPPER_LIMIT << 8) | 0xff);
00400 outw(rcv_car - 1, nic->ioaddr + RCV_STOP);
00401 return (1);
00402 }
| static void eepro_transmit |
( |
struct nic * |
nic, |
|
|
const char * |
d, |
|
|
unsigned int |
t, |
|
|
unsigned int |
s, |
|
|
const char * |
p | |
|
) |
| | [static] |
Definition at line 407 of file eepro.c.
References DBG, ETH_ALEN, ETH_HLEN, HOST_ADDRESS_REG, htons, inw, IO_PORT, nic::ioaddr, nic::node_addr, outb, outsw, outw, printf(), TX_DONE_BIT, tx_end, tx_last, tx_start, e1000_phy_info::type, udelay(), xmt_bar, XMT_CMD, XMT_HEADER, XMT_LOWER_LIMIT, XMT_RAM, and XMT_UPPER_LIMIT.
00413 {
00414 unsigned int status, tx_available, last, end, length;
00415 unsigned short type;
00416 int boguscount = 20;
00417
00418 length = s + ETH_HLEN;
00419 if (tx_end > tx_start)
00420 tx_available = XMT_RAM - (tx_end - tx_start);
00421 else if (tx_end < tx_start)
00422 tx_available = tx_start - tx_end;
00423 else
00424 tx_available = XMT_RAM;
00425 last = tx_end;
00426 end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
00427 if (end >= (XMT_UPPER_LIMIT << 8)) {
00428 last = (XMT_LOWER_LIMIT << 8);
00429 end = last + (((length + 3) >> 1) << 1) + XMT_HEADER;
00430 }
00431 outw(last, nic->ioaddr + HOST_ADDRESS_REG);
00432 outw(XMT_CMD, nic->ioaddr + IO_PORT);
00433 outw(0, nic->ioaddr + IO_PORT);
00434 outw(end, nic->ioaddr + IO_PORT);
00435 outw(length, nic->ioaddr + IO_PORT);
00436 outsw(nic->ioaddr + IO_PORT, d, ETH_ALEN / 2);
00437 outsw(nic->ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2);
00438 type = htons(t);
00439 outsw(nic->ioaddr + IO_PORT, &type, sizeof(type) / 2);
00440 outsw(nic->ioaddr + IO_PORT, p, (s + 3) >> 1);
00441
00442 status = inw(nic->ioaddr + IO_PORT);
00443 outw(last, nic->ioaddr + xmt_bar);
00444 outb(XMT_CMD, nic->ioaddr);
00445 tx_start = last;
00446 tx_last = last;
00447 tx_end = end;
00448 #if 0
00449 printf("%d %d\n", tx_start, tx_end);
00450 #endif
00451 while (boguscount > 0) {
00452 if (((status = inw(nic->ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
00453 udelay(40);
00454 boguscount--;
00455 continue;
00456 }
00457 if ((status & 0x2000) == 0) {
00458 DBG("Transmit status %hX\n", status);
00459 }
00460 }
00461 }
| static int read_eeprom |
( |
uint16_t |
ioaddr, |
|
|
int |
location | |
|
) |
| | [static] |
Definition at line 491 of file eepro.c.
References EE_READ_CMD, EECS, EEDI, EEDO, eepro, eepro_sw2bank0, eepro_sw2bank1, eepro_sw2bank2, eeprom_delay, eeprom_reg, EESK, inb, LAN595FX_10ISA, outb, and STATUS_REG.
00492 {
00493 int i;
00494 unsigned short retval = 0;
00495 int ee_addr = ioaddr + eeprom_reg;
00496 int read_cmd = location | EE_READ_CMD;
00497 int ctrl_val = EECS;
00498
00499 if (eepro == LAN595FX_10ISA) {
00500 eepro_sw2bank1(ioaddr);
00501 outb(0x00, ioaddr + STATUS_REG);
00502 }
00503 eepro_sw2bank2(ioaddr);
00504 outb(ctrl_val, ee_addr);
00505
00506 for (i = 8; i >= 0; i--) {
00507 short outval = (read_cmd & (1 << i)) ? ctrl_val | EEDI : ctrl_val;
00508 outb(outval, ee_addr);
00509 outb(outval | EESK, ee_addr);
00510 eeprom_delay();
00511 outb(outval, ee_addr);
00512 eeprom_delay();
00513 }
00514 outb(ctrl_val, ee_addr);
00515 for (i = 16; i > 0; i--) {
00516 outb(ctrl_val | EESK, ee_addr);
00517 eeprom_delay();
00518 retval = (retval << 1) | ((inb(ee_addr) & EEDO) ? 1 : 0);
00519 outb(ctrl_val, ee_addr);
00520 eeprom_delay();
00521 }
00522
00523 ctrl_val &= ~EECS;
00524 outb(ctrl_val | EESK, ee_addr);
00525 eeprom_delay();
00526 outb(ctrl_val, ee_addr);
00527 eeprom_delay();
00528 eepro_sw2bank0(ioaddr);
00529 return (retval);
00530 }
| static int eepro_probe |
( |
struct nic * |
nic, |
|
|
struct isa_device * |
isa | |
|
) |
| | [static] |
Definition at line 556 of file eepro.c.
References DBG, ee_BNC_TPE, ee_FX_INT2IRQ, eepro, eepro_reset(), eeprom_reg, EEPROM_REG_10, ETH_ALEN, eth_ntoa(), GetBit, isa_device::ioaddr, nic::ioaddr, nic::irqno, LAN595FX_10ISA, mem_end, mem_start, name, nic::nic_op, nic::node_addr, printf(), RCV_LOWER_LIMIT, rcv_ram, rcv_start, RCV_START_10, RCV_UPPER_LIMIT, read_eeprom(), SA_ADDR1, swap16, xmt_lower_limit_reg, XMT_LOWER_LIMIT_REG_10, xmt_upper_limit_reg, and XMT_UPPER_LIMIT_REG_10.
00556 {
00557
00558 int i, l_eepro = 0;
00559 union {
00560 unsigned char caddr[ETH_ALEN];
00561 unsigned short saddr[ETH_ALEN/2];
00562 } station_addr;
00563 const char *name;
00564
00565 nic->irqno = 0;
00566 nic->ioaddr = isa->ioaddr;
00567
00568 station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
00569 if ( ( station_addr.saddr[2] == 0x0000 ) ||
00570 ( station_addr.saddr[2] == 0xFFFF ) ) {
00571 l_eepro = 3;
00572 eepro = LAN595FX_10ISA;
00573 eeprom_reg= EEPROM_REG_10;
00574 rcv_start = RCV_START_10;
00575 xmt_lower_limit_reg = XMT_LOWER_LIMIT_REG_10;
00576 xmt_upper_limit_reg = XMT_UPPER_LIMIT_REG_10;
00577 station_addr.saddr[2] = read_eeprom(nic->ioaddr,2);
00578 }
00579 station_addr.saddr[1] = read_eeprom(nic->ioaddr,3);
00580 station_addr.saddr[0] = read_eeprom(nic->ioaddr,4);
00581 if (l_eepro)
00582 name = "Intel EtherExpress 10 ISA";
00583 else if (read_eeprom(nic->ioaddr,7) == ee_FX_INT2IRQ) {
00584 name = "Intel EtherExpress Pro/10+ ISA";
00585 l_eepro = 2;
00586 } else if (station_addr.saddr[0] == SA_ADDR1) {
00587 name = "Intel EtherExpress Pro/10 ISA";
00588 l_eepro = 1;
00589 } else {
00590 l_eepro = 0;
00591 name = "Intel 82595-based LAN card";
00592 }
00593 station_addr.saddr[0] = swap16(station_addr.saddr[0]);
00594 station_addr.saddr[1] = swap16(station_addr.saddr[1]);
00595 station_addr.saddr[2] = swap16(station_addr.saddr[2]);
00596 for (i = 0; i < ETH_ALEN; i++) {
00597 nic->node_addr[i] = station_addr.caddr[i];
00598 }
00599
00600 DBG ( "%s ioaddr %#hX, addr %s", name, nic->ioaddr, eth_ntoa ( nic->node_addr ) );
00601
00602 mem_start = RCV_LOWER_LIMIT << 8;
00603 if ((mem_end & 0x3F) < 3 || (mem_end & 0x3F) > 29)
00604 mem_end = RCV_UPPER_LIMIT << 8;
00605 else {
00606 mem_end = mem_end * 1024 + (RCV_LOWER_LIMIT << 8);
00607 rcv_ram = mem_end - (RCV_LOWER_LIMIT << 8);
00608 }
00609 printf(", Rx mem %dK, if %s\n", (mem_end - mem_start) >> 10,
00610 GetBit(read_eeprom(nic->ioaddr,5), ee_BNC_TPE) ? "BNC" : "TP");
00611
00612 eepro_reset(nic);
00613
00614
00615 nic->nic_op = &eepro_operations;
00616 return 1;
00617 }
