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Defines | |
| #define | E1000_MAX_PHY_ADDR 4 |
| #define | IGP01E1000_PHY_PORT_CONFIG 0x10 |
| #define | IGP01E1000_PHY_PORT_STATUS 0x11 |
| #define | IGP01E1000_PHY_PORT_CTRL 0x12 |
| #define | IGP01E1000_PHY_LINK_HEALTH 0x13 |
| #define | IGP01E1000_GMII_FIFO 0x14 |
| #define | IGP01E1000_PHY_CHANNEL_QUALITY 0x15 |
| #define | IGP02E1000_PHY_POWER_MGMT 0x19 |
| #define | IGP01E1000_PHY_PAGE_SELECT 0x1F |
| #define | BM_PHY_PAGE_SELECT 22 |
| #define | IGP_PAGE_SHIFT 5 |
| #define | PHY_REG_MASK 0x1F |
| #define | BM_PORT_CTRL_PAGE 769 |
| #define | BM_PCIE_PAGE 770 |
| #define | BM_WUC_PAGE 800 |
| #define | BM_WUC_ADDRESS_OPCODE 0x11 |
| #define | BM_WUC_DATA_OPCODE 0x12 |
| #define | BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE |
| #define | BM_WUC_ENABLE_REG 17 |
| #define | BM_WUC_ENABLE_BIT (1 << 2) |
| #define | BM_WUC_HOST_WU_BIT (1 << 4) |
| #define | PHY_UPPER_SHIFT 21 |
| #define | BM_PHY_REG(page, reg) |
| #define | BM_PHY_REG_PAGE(offset) ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) |
| #define | BM_PHY_REG_NUM(offset) |
| #define | HV_INTC_FC_PAGE_START 768 |
| #define | I82578_ADDR_REG 29 |
| #define | I82577_ADDR_REG 16 |
| #define | I82577_CFG_REG 22 |
| #define | I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
| #define | I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) |
| #define | I82577_CTRL_REG 23 |
| #define | I82577_PHY_CTRL_2 18 |
| #define | I82577_PHY_LBK_CTRL 19 |
| #define | I82577_PHY_STATUS_2 26 |
| #define | I82577_PHY_DIAG_STATUS 31 |
| #define | I82577_PHY_STATUS2_REV_POLARITY 0x0400 |
| #define | I82577_PHY_STATUS2_MDIX 0x0800 |
| #define | I82577_PHY_STATUS2_SPEED_MASK 0x0300 |
| #define | I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 |
| #define | I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 |
| #define | I82577_PHY_CTRL2_AUTO_MDIX 0x0400 |
| #define | I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 |
| #define | I82577_DSTATUS_CABLE_LENGTH 0x03FC |
| #define | I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 |
| #define | BM_CS_CTRL1 16 |
| #define | BM_CS_CTRL1_ENERGY_DETECT 0x0300 |
| #define | BM_CS_STATUS 17 |
| #define | BM_CS_STATUS_ENERGY_DETECT 0x0010 |
| #define | BM_CS_STATUS_LINK_UP 0x0400 |
| #define | BM_CS_STATUS_RESOLVED 0x0800 |
| #define | BM_CS_STATUS_SPEED_MASK 0xC000 |
| #define | BM_CS_STATUS_SPEED_1000 0x8000 |
| #define | HV_M_STATUS 26 |
| #define | HV_M_STATUS_AUTONEG_COMPLETE 0x1000 |
| #define | HV_M_STATUS_SPEED_MASK 0x0300 |
| #define | HV_M_STATUS_SPEED_1000 0x0200 |
| #define | HV_M_STATUS_LINK_UP 0x0040 |
| #define | IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
| #define | IGP01E1000_PHY_POLARITY_MASK 0x0078 |
| #define | IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
| #define | IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 |
| #define | IGP01E1000_PSCFR_SMART_SPEED 0x0080 |
| #define | IGP01E1000_GMII_FLEX_SPD 0x0010 |
| #define | IGP01E1000_GMII_SPD 0x0020 |
| #define | IGP02E1000_PM_SPD 0x0001 |
| #define | IGP02E1000_PM_D0_LPLU 0x0002 |
| #define | IGP02E1000_PM_D3_LPLU 0x0004 |
| #define | IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 |
| #define | IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 |
| #define | IGP01E1000_PSSR_MDIX 0x0800 |
| #define | IGP01E1000_PSSR_SPEED_MASK 0xC000 |
| #define | IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 |
| #define | IGP02E1000_PHY_CHANNEL_NUM 4 |
| #define | IGP02E1000_PHY_AGC_A 0x11B1 |
| #define | IGP02E1000_PHY_AGC_B 0x12B1 |
| #define | IGP02E1000_PHY_AGC_C 0x14B1 |
| #define | IGP02E1000_PHY_AGC_D 0x18B1 |
| #define | IGP02E1000_AGC_LENGTH_SHIFT 9 |
| #define | IGP02E1000_AGC_LENGTH_MASK 0x7F |
| #define | IGP02E1000_AGC_RANGE 15 |
| #define | IGP03E1000_PHY_MISC_CTRL 0x1B |
| #define | IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 |
| #define | E1000_CABLE_LENGTH_UNDEFINED 0xFF |
| #define | E1000_KMRNCTRLSTA_OFFSET 0x001F0000 |
| #define | E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 |
| #define | E1000_KMRNCTRLSTA_REN 0x00200000 |
| #define | E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 |
| #define | E1000_KMRNCTRLSTA_TIMEOUTS 0x4 |
| #define | E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 |
| #define | E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 |
| #define | E1000_KMRNCTRLSTA_K1_CONFIG 0x7 |
| #define | E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 |
| #define | IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 |
| #define | IFE_PHY_SPECIAL_CONTROL 0x11 |
| #define | IFE_PHY_SPECIAL_CONTROL_LED 0x1B |
| #define | IFE_PHY_MDIX_CONTROL 0x1C |
| #define | IFE_PESC_POLARITY_REVERSED 0x0100 |
| #define | IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 |
| #define | IFE_PSC_FORCE_POLARITY 0x0020 |
| #define | IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 |
| #define | IFE_PSCL_PROBE_MODE 0x0020 |
| #define | IFE_PSCL_PROBE_LEDS_OFF 0x0006 |
| #define | IFE_PSCL_PROBE_LEDS_ON 0x0007 |
| #define | IFE_PMC_MDIX_STATUS 0x0020 |
| #define | IFE_PMC_FORCE_MDIX 0x0040 |
| #define | IFE_PMC_AUTO_MDIX 0x0080 |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| void | e1000e_init_phy_ops_generic (struct e1000_hw *hw) |
| s32 | e1000e_check_downshift (struct e1000_hw *hw) |
| e1000e_check_downshift - Checks whether a downshift in speed occurred : pointer to the HW structure | |
| s32 | e1000e_check_polarity_m88 (struct e1000_hw *hw) |
| e1000e_check_polarity_m88 - Checks the polarity. | |
| s32 | e1000e_check_polarity_igp (struct e1000_hw *hw) |
| e1000e_check_polarity_igp - Checks the polarity. | |
| s32 | e1000e_check_polarity_ife (struct e1000_hw *hw) |
| e1000e_check_polarity_ife - Check cable polarity for IFE PHY : pointer to the HW structure | |
| s32 | e1000e_check_reset_block_generic (struct e1000_hw *hw) |
| e1000e_check_reset_block_generic - Check if PHY reset is blocked : pointer to the HW structure | |
| s32 | e1000e_copper_link_setup_igp (struct e1000_hw *hw) |
| e1000e_copper_link_setup_igp - Setup igp PHY's for copper link : pointer to the HW structure | |
| s32 | e1000e_copper_link_setup_m88 (struct e1000_hw *hw) |
| e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link : pointer to the HW structure | |
| s32 | e1000e_get_cfg_done (struct e1000_hw *hw) |
| s32 | e1000e_get_phy_id (struct e1000_hw *hw) |
| e1000e_get_phy_id - Retrieve the PHY ID and revision : pointer to the HW structure | |
| s32 | e1000e_get_phy_info_igp (struct e1000_hw *hw) |
| e1000e_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure | |
| s32 | e1000e_get_phy_info_m88 (struct e1000_hw *hw) |
| e1000e_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure | |
| s32 | e1000e_phy_sw_reset (struct e1000_hw *hw) |
| e1000e_phy_sw_reset - PHY software reset : pointer to the HW structure | |
| s32 | e1000e_phy_hw_reset_generic (struct e1000_hw *hw) |
| e1000e_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure | |
| s32 | e1000e_phy_reset_dsp (struct e1000_hw *hw) |
| e1000e_phy_reset_dsp - Reset PHY DSP : pointer to the HW structure | |
| s32 | e1000e_read_kmrn_reg (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_kmrn_reg - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_read_kmrn_reg_locked (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_kmrn_reg_locked - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_read_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_read_phy_reg_igp_locked (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_igp_locked - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_read_phy_reg_m88 (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_set_d3_lplu_state (struct e1000_hw *hw, bool active) |
| e1000e_set_d3_lplu_state - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu | |
| s32 | e1000e_setup_copper_link (struct e1000_hw *hw) |
| e1000e_setup_copper_link - Configure copper link settings : pointer to the HW structure | |
| s32 | e1000e_wait_autoneg (struct e1000_hw *hw) |
| e1000e_wait_autoneg - Wait for auto-neg completion : pointer to the HW structure | |
| s32 | e1000e_write_kmrn_reg (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_kmrn_reg - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_write_kmrn_reg_locked (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_kmrn_reg_locked - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_write_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_write_phy_reg_igp_locked (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_igp_locked - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_write_phy_reg_m88 (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_m88 - Write m88 PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_phy_has_link_generic (struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success) |
| e1000e_phy_has_link_generic - Polls PHY for link : pointer to the HW structure : number of times to poll for link : delay between polling attempts : pointer to whether polling was successful or not | |
| s32 | e1000e_phy_init_script_igp3 (struct e1000_hw *hw) |
| e1000e_phy_init_script_igp3 - Inits the IGP3 PHY : pointer to the HW structure | |
| enum e1000_phy_type | e1000e_get_phy_type_from_id (u32 phy_id) |
| e1000e_get_phy_type_from_id - Get PHY type from id : phy_id read from the phy | |
| s32 | e1000e_determine_phy_address (struct e1000_hw *hw) |
| e1000e_determine_phy_address - Determines PHY address. | |
| s32 | e1000e_write_phy_reg_bm (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_bm - Write BM PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_read_phy_reg_bm (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_bm - Read BM PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_read_phy_reg_bm2 (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_bm2 - Read BM PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_write_phy_reg_bm2 (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_bm2 - Write BM PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| void | e1000e_power_up_phy_copper (struct e1000_hw *hw) |
| e1000e_power_up_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure | |
| void | e1000e_power_down_phy_copper (struct e1000_hw *hw) |
| e1000e_power_down_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure | |
| s32 | e1000e_read_phy_reg_mdic (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_mdic - Read MDI control register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_write_phy_reg_mdic (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_mdic - Write MDI control register : pointer to the HW structure : register offset to write to : data to write to register at offset | |
| s32 | e1000e_read_phy_reg_hv (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_hv - Read HV PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_read_phy_reg_hv_locked (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_hv_locked - Read HV PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_write_phy_reg_hv (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_hv - Write HV PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_write_phy_reg_hv_locked (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_hv_locked - Write HV PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_set_mdio_slow_mode_hv (struct e1000_hw *hw, bool slow) |
| e1000e_set_mdio_slow_mode_hv - Set slow MDIO access mode : pointer to the HW structure : true for slow mode, false for normal mode | |
| s32 | e1000e_link_stall_workaround_hv (struct e1000_hw *hw) |
| e1000e_link_stall_workaround_hv - Si workaround : pointer to the HW structure | |
| s32 | e1000e_copper_link_setup_82577 (struct e1000_hw *hw) |
| e1000e_copper_link_setup_82577 - Setup 82577 PHY for copper link : pointer to the HW structure | |
| s32 | e1000e_check_polarity_82577 (struct e1000_hw *hw) |
| e1000e_check_polarity_82577 - Checks the polarity. | |
| s32 | e1000e_get_phy_info_82577 (struct e1000_hw *hw) |
| e1000e_get_phy_info_82577 - Retrieve I82577 PHY information : pointer to the HW structure | |
| #define E1000_MAX_PHY_ADDR 4 |
Definition at line 104 of file e1000e_phy.h.
| #define IGP01E1000_PHY_PORT_CONFIG 0x10 |
Definition at line 107 of file e1000e_phy.h.
| #define IGP01E1000_PHY_PORT_STATUS 0x11 |
Definition at line 108 of file e1000e_phy.h.
| #define IGP01E1000_PHY_PORT_CTRL 0x12 |
Definition at line 109 of file e1000e_phy.h.
| #define IGP01E1000_PHY_LINK_HEALTH 0x13 |
Definition at line 110 of file e1000e_phy.h.
| #define IGP01E1000_GMII_FIFO 0x14 |
Definition at line 111 of file e1000e_phy.h.
| #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 |
Definition at line 112 of file e1000e_phy.h.
| #define IGP02E1000_PHY_POWER_MGMT 0x19 |
Definition at line 113 of file e1000e_phy.h.
| #define IGP01E1000_PHY_PAGE_SELECT 0x1F |
Definition at line 114 of file e1000e_phy.h.
| #define BM_PHY_PAGE_SELECT 22 |
Definition at line 115 of file e1000e_phy.h.
| #define IGP_PAGE_SHIFT 5 |
Definition at line 116 of file e1000e_phy.h.
| #define PHY_REG_MASK 0x1F |
Definition at line 117 of file e1000e_phy.h.
| #define BM_PORT_CTRL_PAGE 769 |
Definition at line 120 of file e1000e_phy.h.
Referenced by e1000e_set_mdio_slow_mode_hv(), and e1000e_setup_link_ich8lan().
| #define BM_PCIE_PAGE 770 |
Definition at line 121 of file e1000e_phy.h.
| #define BM_WUC_PAGE 800 |
Definition at line 122 of file e1000e_phy.h.
Referenced by __e1000e_read_phy_reg_hv(), __e1000e_write_phy_reg_hv(), e1000e_access_phy_wakeup_reg_bm(), e1000e_read_phy_reg_bm(), e1000e_read_phy_reg_bm2(), e1000e_write_phy_reg_bm(), and e1000e_write_phy_reg_bm2().
| #define BM_WUC_ADDRESS_OPCODE 0x11 |
| #define BM_WUC_DATA_OPCODE 0x12 |
| #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE |
| #define BM_WUC_ENABLE_REG 17 |
| #define BM_WUC_ENABLE_BIT (1 << 2) |
| #define BM_WUC_HOST_WU_BIT (1 << 4) |
| #define PHY_UPPER_SHIFT 21 |
Definition at line 130 of file e1000e_phy.h.
| #define BM_PHY_REG | ( | page, | |||
| reg | ) |
Value:
(((reg) & MAX_PHY_REG_ADDRESS) |\ (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
Definition at line 131 of file e1000e_phy.h.
Definition at line 135 of file e1000e_phy.h.
Referenced by __e1000e_read_phy_reg_hv(), and __e1000e_write_phy_reg_hv().
| #define BM_PHY_REG_NUM | ( | offset | ) |
Value:
((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ ~MAX_PHY_REG_ADDRESS)))
Definition at line 137 of file e1000e_phy.h.
Referenced by __e1000e_read_phy_reg_hv(), __e1000e_write_phy_reg_hv(), and e1000e_access_phy_wakeup_reg_bm().
| #define HV_INTC_FC_PAGE_START 768 |
Definition at line 142 of file e1000e_phy.h.
Referenced by __e1000e_read_phy_reg_hv(), __e1000e_write_phy_reg_hv(), and e1000e_get_phy_addr_for_hv_page().
| #define I82578_ADDR_REG 29 |
| #define I82577_ADDR_REG 16 |
| #define I82577_CFG_REG 22 |
| #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) |
| #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) |
| #define I82577_CTRL_REG 23 |
Definition at line 148 of file e1000e_phy.h.
| #define I82577_PHY_CTRL_2 18 |
Definition at line 151 of file e1000e_phy.h.
| #define I82577_PHY_LBK_CTRL 19 |
Definition at line 152 of file e1000e_phy.h.
| #define I82577_PHY_STATUS_2 26 |
Definition at line 153 of file e1000e_phy.h.
Referenced by e1000e_check_polarity_82577(), and e1000e_get_phy_info_82577().
| #define I82577_PHY_DIAG_STATUS 31 |
Definition at line 154 of file e1000e_phy.h.
| #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 |
| #define I82577_PHY_STATUS2_MDIX 0x0800 |
| #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 |
| #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 |
| #define I82577_PHY_STATUS2_SPEED_100MBPS 0x0100 |
Definition at line 161 of file e1000e_phy.h.
| #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 |
Definition at line 164 of file e1000e_phy.h.
| #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 |
Definition at line 165 of file e1000e_phy.h.
| #define I82577_DSTATUS_CABLE_LENGTH 0x03FC |
Definition at line 168 of file e1000e_phy.h.
| #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 |
Definition at line 169 of file e1000e_phy.h.
| #define BM_CS_CTRL1 16 |
| #define BM_CS_CTRL1_ENERGY_DETECT 0x0300 |
Definition at line 173 of file e1000e_phy.h.
| #define BM_CS_STATUS 17 |
Definition at line 176 of file e1000e_phy.h.
Referenced by e1000e_k1_gig_workaround_hv(), and e1000e_link_stall_workaround_hv().
| #define BM_CS_STATUS_ENERGY_DETECT 0x0010 |
Definition at line 177 of file e1000e_phy.h.
| #define BM_CS_STATUS_LINK_UP 0x0400 |
Definition at line 178 of file e1000e_phy.h.
Referenced by e1000e_k1_gig_workaround_hv(), and e1000e_link_stall_workaround_hv().
| #define BM_CS_STATUS_RESOLVED 0x0800 |
Definition at line 179 of file e1000e_phy.h.
Referenced by e1000e_k1_gig_workaround_hv(), and e1000e_link_stall_workaround_hv().
| #define BM_CS_STATUS_SPEED_MASK 0xC000 |
Definition at line 180 of file e1000e_phy.h.
Referenced by e1000e_k1_gig_workaround_hv(), and e1000e_link_stall_workaround_hv().
| #define BM_CS_STATUS_SPEED_1000 0x8000 |
Definition at line 181 of file e1000e_phy.h.
Referenced by e1000e_k1_gig_workaround_hv(), and e1000e_link_stall_workaround_hv().
| #define HV_M_STATUS 26 |
| #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 |
| #define HV_M_STATUS_SPEED_MASK 0x0300 |
| #define HV_M_STATUS_SPEED_1000 0x0200 |
| #define HV_M_STATUS_LINK_UP 0x0040 |
| #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 |
Definition at line 190 of file e1000e_phy.h.
| #define IGP01E1000_PHY_POLARITY_MASK 0x0078 |
Definition at line 191 of file e1000e_phy.h.
| #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 |
Definition at line 193 of file e1000e_phy.h.
| #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 |
Definition at line 194 of file e1000e_phy.h.
| #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 |
Definition at line 196 of file e1000e_phy.h.
| #define IGP01E1000_GMII_FLEX_SPD 0x0010 |
Definition at line 199 of file e1000e_phy.h.
| #define IGP01E1000_GMII_SPD 0x0020 |
Definition at line 200 of file e1000e_phy.h.
| #define IGP02E1000_PM_SPD 0x0001 |
Definition at line 202 of file e1000e_phy.h.
| #define IGP02E1000_PM_D0_LPLU 0x0002 |
Definition at line 203 of file e1000e_phy.h.
| #define IGP02E1000_PM_D3_LPLU 0x0004 |
Definition at line 204 of file e1000e_phy.h.
| #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 |
Definition at line 206 of file e1000e_phy.h.
| #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 |
Definition at line 208 of file e1000e_phy.h.
| #define IGP01E1000_PSSR_MDIX 0x0800 |
Definition at line 209 of file e1000e_phy.h.
| #define IGP01E1000_PSSR_SPEED_MASK 0xC000 |
Definition at line 210 of file e1000e_phy.h.
| #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 |
Definition at line 211 of file e1000e_phy.h.
| #define IGP02E1000_PHY_CHANNEL_NUM 4 |
Definition at line 213 of file e1000e_phy.h.
| #define IGP02E1000_PHY_AGC_A 0x11B1 |
Definition at line 214 of file e1000e_phy.h.
| #define IGP02E1000_PHY_AGC_B 0x12B1 |
Definition at line 215 of file e1000e_phy.h.
| #define IGP02E1000_PHY_AGC_C 0x14B1 |
Definition at line 216 of file e1000e_phy.h.
| #define IGP02E1000_PHY_AGC_D 0x18B1 |
Definition at line 217 of file e1000e_phy.h.
| #define IGP02E1000_AGC_LENGTH_SHIFT 9 |
Definition at line 219 of file e1000e_phy.h.
| #define IGP02E1000_AGC_LENGTH_MASK 0x7F |
Definition at line 220 of file e1000e_phy.h.
| #define IGP02E1000_AGC_RANGE 15 |
Definition at line 221 of file e1000e_phy.h.
| #define IGP03E1000_PHY_MISC_CTRL 0x1B |
Definition at line 223 of file e1000e_phy.h.
| #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 |
Definition at line 224 of file e1000e_phy.h.
| #define E1000_CABLE_LENGTH_UNDEFINED 0xFF |
Definition at line 226 of file e1000e_phy.h.
| #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 |
Definition at line 228 of file e1000e_phy.h.
| #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 |
Definition at line 229 of file e1000e_phy.h.
| #define E1000_KMRNCTRLSTA_REN 0x00200000 |
Definition at line 230 of file e1000e_phy.h.
| #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 |
Definition at line 231 of file e1000e_phy.h.
| #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 |
Definition at line 232 of file e1000e_phy.h.
| #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 |
Definition at line 233 of file e1000e_phy.h.
| #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 |
Definition at line 234 of file e1000e_phy.h.
| #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 |
| #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 |
| #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 |
Definition at line 238 of file e1000e_phy.h.
| #define IFE_PHY_SPECIAL_CONTROL 0x11 |
Definition at line 239 of file e1000e_phy.h.
| #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B |
Definition at line 240 of file e1000e_phy.h.
| #define IFE_PHY_MDIX_CONTROL 0x1C |
Definition at line 241 of file e1000e_phy.h.
| #define IFE_PESC_POLARITY_REVERSED 0x0100 |
Definition at line 244 of file e1000e_phy.h.
| #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 |
Definition at line 247 of file e1000e_phy.h.
| #define IFE_PSC_FORCE_POLARITY 0x0020 |
Definition at line 248 of file e1000e_phy.h.
| #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 |
Definition at line 249 of file e1000e_phy.h.
| #define IFE_PSCL_PROBE_MODE 0x0020 |
Definition at line 252 of file e1000e_phy.h.
| #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 |
Definition at line 253 of file e1000e_phy.h.
| #define IFE_PSCL_PROBE_LEDS_ON 0x0007 |
Definition at line 254 of file e1000e_phy.h.
| #define IFE_PMC_MDIX_STATUS 0x0020 |
Definition at line 257 of file e1000e_phy.h.
| #define IFE_PMC_FORCE_MDIX 0x0040 |
Definition at line 258 of file e1000e_phy.h.
| #define IFE_PMC_AUTO_MDIX 0x0080 |
Definition at line 259 of file e1000e_phy.h.
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
| void e1000e_init_phy_ops_generic | ( | struct e1000_hw * | hw | ) |
e1000e_check_downshift - Checks whether a downshift in speed occurred : pointer to the HW structure
Success returns 0, Failure returns 1
A downshift is detected by querying the PHY link health.
Definition at line 1634 of file e1000e_phy.c.
References e1000_phy_82578, e1000_phy_bm, e1000_phy_gg82563, e1000_phy_igp, e1000_phy_igp_2, e1000_phy_igp_3, e1000_phy_m88, E1000_SUCCESS, e1e_rphy(), IGP01E1000_PHY_LINK_HEALTH, IGP01E1000_PLHR_SS_DOWNGRADE, M88E1000_PHY_SPEC_STATUS, M88E1000_PSSR_DOWNSHIFT, offset, e1000_hw::phy, e1000_phy_info::speed_downgraded, e1000_phy_info::type, and u16.
01635 { 01636 struct e1000_phy_info *phy = &hw->phy; 01637 s32 ret_val; 01638 u16 phy_data, offset, mask; 01639 01640 switch (phy->type) { 01641 case e1000_phy_m88: 01642 case e1000_phy_gg82563: 01643 case e1000_phy_bm: 01644 case e1000_phy_82578: 01645 offset = M88E1000_PHY_SPEC_STATUS; 01646 mask = M88E1000_PSSR_DOWNSHIFT; 01647 break; 01648 case e1000_phy_igp_2: 01649 case e1000_phy_igp: 01650 case e1000_phy_igp_3: 01651 offset = IGP01E1000_PHY_LINK_HEALTH; 01652 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 01653 break; 01654 default: 01655 /* speed downshift not supported */ 01656 phy->speed_downgraded = false; 01657 ret_val = E1000_SUCCESS; 01658 goto out; 01659 } 01660 01661 ret_val = e1e_rphy(hw, offset, &phy_data); 01662 01663 if (!ret_val) 01664 phy->speed_downgraded = (phy_data & mask) ? true : false; 01665 01666 out: 01667 return ret_val; 01668 }
e1000e_check_polarity_m88 - Checks the polarity.
: pointer to the HW structure
Success returns 0, Failure returns -E1000_ERR_PHY (-2)
Polarity is determined based on the PHY specific status register.
Definition at line 1678 of file e1000e_phy.c.
References e1000_phy_info::cable_polarity, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, e1e_rphy(), M88E1000_PHY_SPEC_STATUS, M88E1000_PSSR_REV_POLARITY, e1000_hw::phy, and u16.
Referenced by e1000e_get_phy_info_m88(), and e1000e_init_phy_params_80003es2lan().
01679 { 01680 struct e1000_phy_info *phy = &hw->phy; 01681 s32 ret_val; 01682 u16 data; 01683 01684 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); 01685 01686 if (!ret_val) 01687 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 01688 ? e1000_rev_polarity_reversed 01689 : e1000_rev_polarity_normal; 01690 01691 return ret_val; 01692 }
e1000e_check_polarity_igp - Checks the polarity.
: pointer to the HW structure
Success returns 0, Failure returns -E1000_ERR_PHY (-2)
Polarity is determined based on the PHY port status register, and the current speed (since there is no polarity at 100Mbps).
Definition at line 1703 of file e1000e_phy.c.
References e1000_phy_info::cable_polarity, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, e1e_rphy(), IGP01E1000_PHY_PCS_INIT_REG, IGP01E1000_PHY_POLARITY_MASK, IGP01E1000_PHY_PORT_STATUS, IGP01E1000_PSSR_POLARITY_REVERSED, IGP01E1000_PSSR_SPEED_1000MBPS, IGP01E1000_PSSR_SPEED_MASK, offset, e1000_hw::phy, and u16.
Referenced by e1000e_get_phy_info_igp(), and e1000e_init_phy_params_82571().
01704 { 01705 struct e1000_phy_info *phy = &hw->phy; 01706 s32 ret_val; 01707 u16 data, offset, mask; 01708 01709 /* 01710 * Polarity is determined based on the speed of 01711 * our connection. 01712 */ 01713 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 01714 if (ret_val) 01715 goto out; 01716 01717 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 01718 IGP01E1000_PSSR_SPEED_1000MBPS) { 01719 offset = IGP01E1000_PHY_PCS_INIT_REG; 01720 mask = IGP01E1000_PHY_POLARITY_MASK; 01721 } else { 01722 /* 01723 * This really only applies to 10Mbps since 01724 * there is no polarity for 100Mbps (always 0). 01725 */ 01726 offset = IGP01E1000_PHY_PORT_STATUS; 01727 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 01728 } 01729 01730 ret_val = e1e_rphy(hw, offset, &data); 01731 01732 if (!ret_val) 01733 phy->cable_polarity = (data & mask) 01734 ? e1000_rev_polarity_reversed 01735 : e1000_rev_polarity_normal; 01736 01737 out: 01738 return ret_val; 01739 }
e1000e_check_polarity_ife - Check cable polarity for IFE PHY : pointer to the HW structure
Polarity is determined on the polarity reversal feature being enabled.
Definition at line 1747 of file e1000e_phy.c.
References e1000_phy_info::cable_polarity, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, e1e_rphy(), IFE_PESC_POLARITY_REVERSED, IFE_PHY_EXTENDED_STATUS_CONTROL, IFE_PHY_SPECIAL_CONTROL, IFE_PSC_FORCE_POLARITY, offset, e1000_hw::phy, e1000_phy_info::polarity_correction, and u16.
Referenced by e1000e_get_phy_info_ife_ich8lan(), e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
01748 { 01749 struct e1000_phy_info *phy = &hw->phy; 01750 s32 ret_val; 01751 u16 phy_data, offset, mask; 01752 01753 /* 01754 * Polarity is determined based on the reversal feature being enabled. 01755 */ 01756 if (phy->polarity_correction) { 01757 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 01758 mask = IFE_PESC_POLARITY_REVERSED; 01759 } else { 01760 offset = IFE_PHY_SPECIAL_CONTROL; 01761 mask = IFE_PSC_FORCE_POLARITY; 01762 } 01763 01764 ret_val = e1e_rphy(hw, offset, &phy_data); 01765 01766 if (!ret_val) 01767 phy->cable_polarity = (phy_data & mask) 01768 ? e1000_rev_polarity_reversed 01769 : e1000_rev_polarity_normal; 01770 01771 return ret_val; 01772 }
e1000e_check_reset_block_generic - Check if PHY reset is blocked : pointer to the HW structure
Read the PHY management control register and check whether a PHY reset is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise return E1000_BLK_PHY_RESET (12).
Definition at line 71 of file e1000e_phy.c.
References E1000_BLK_PHY_RESET, E1000_MANC_BLK_PHY_RST_ON_IDE, E1000_SUCCESS, er32, and u32.
00072 { 00073 u32 manc; 00074 00075 manc = er32(MANC); 00076 00077 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 00078 E1000_BLK_PHY_RESET : E1000_SUCCESS; 00079 }
e1000e_copper_link_setup_igp - Setup igp PHY's for copper link : pointer to the HW structure
Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for igp PHY's.
Definition at line 795 of file e1000e_phy.c.
References ADVERTISE_1000_FULL, e1000_mac_info::autoneg, e1000_phy_info::autoneg_advertised, CR_1000T_MS_ENABLE, CR_1000T_MS_VALUE, e1000_ms_auto, e1000_ms_force_master, e1000_ms_force_slave, e1000_phy_igp, E1000_SUCCESS, e1000e_phy_hw_reset(), e1e_rphy(), e1e_wphy(), e_dbg, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PHY_PORT_CTRL, IGP01E1000_PSCFR_SMART_SPEED, IGP01E1000_PSCR_AUTO_MDIX, IGP01E1000_PSCR_FORCE_MDI_MDIX, e1000_hw::mac, e1000_phy_info::mdix, e1000_phy_info::ms_type, msleep, e1000_phy_info::ops, e1000_phy_info::original_ms_type, e1000_hw::phy, PHY_1000T_CTRL, e1000_phy_info::reset_disable, e1000_phy_operations::set_d0_lplu_state, e1000_phy_operations::set_d3_lplu_state, e1000_phy_info::type, and u16.
00796 { 00797 struct e1000_phy_info *phy = &hw->phy; 00798 s32 ret_val; 00799 u16 data; 00800 00801 if (phy->reset_disable) { 00802 ret_val = E1000_SUCCESS; 00803 goto out; 00804 } 00805 00806 ret_val = e1000e_phy_hw_reset(hw); 00807 if (ret_val) { 00808 e_dbg("Error resetting the PHY.\n"); 00809 goto out; 00810 } 00811 00812 /* 00813 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 00814 * timeout issues when LFS is enabled. 00815 */ 00816 msleep(100); 00817 00818 /* 00819 * The NVM settings will configure LPLU in D3 for 00820 * non-IGP1 PHYs. 00821 */ 00822 if (phy->type == e1000_phy_igp) { 00823 /* disable lplu d3 during driver init */ 00824 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 00825 if (ret_val) { 00826 e_dbg("Error Disabling LPLU D3\n"); 00827 goto out; 00828 } 00829 } 00830 00831 /* disable lplu d0 during driver init */ 00832 if (hw->phy.ops.set_d0_lplu_state) { 00833 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 00834 if (ret_val) { 00835 e_dbg("Error Disabling LPLU D0\n"); 00836 goto out; 00837 } 00838 } 00839 /* Configure mdi-mdix settings */ 00840 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); 00841 if (ret_val) 00842 goto out; 00843 00844 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 00845 00846 switch (phy->mdix) { 00847 case 1: 00848 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 00849 break; 00850 case 2: 00851 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 00852 break; 00853 case 0: 00854 default: 00855 data |= IGP01E1000_PSCR_AUTO_MDIX; 00856 break; 00857 } 00858 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); 00859 if (ret_val) 00860 goto out; 00861 00862 /* set auto-master slave resolution settings */ 00863 if (hw->mac.autoneg) { 00864 /* 00865 * when autonegotiation advertisement is only 1000Mbps then we 00866 * should disable SmartSpeed and enable Auto MasterSlave 00867 * resolution as hardware default. 00868 */ 00869 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 00870 /* Disable SmartSpeed */ 00871 ret_val = e1e_rphy(hw, 00872 IGP01E1000_PHY_PORT_CONFIG, 00873 &data); 00874 if (ret_val) 00875 goto out; 00876 00877 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 00878 ret_val = e1e_wphy(hw, 00879 IGP01E1000_PHY_PORT_CONFIG, 00880 data); 00881 if (ret_val) 00882 goto out; 00883 00884 /* Set auto Master/Slave resolution process */ 00885 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 00886 if (ret_val) 00887 goto out; 00888 00889 data &= ~CR_1000T_MS_ENABLE; 00890 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 00891 if (ret_val) 00892 goto out; 00893 } 00894 00895 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 00896 if (ret_val) 00897 goto out; 00898 00899 /* load defaults for future use */ 00900 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 00901 ((data & CR_1000T_MS_VALUE) ? 00902 e1000_ms_force_master : 00903 e1000_ms_force_slave) : 00904 e1000_ms_auto; 00905 00906 switch (phy->ms_type) { 00907 case e1000_ms_force_master: 00908 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 00909 break; 00910 case e1000_ms_force_slave: 00911 data |= CR_1000T_MS_ENABLE; 00912 data &= ~(CR_1000T_MS_VALUE); 00913 break; 00914 case e1000_ms_auto: 00915 data &= ~CR_1000T_MS_ENABLE; 00916 default: 00917 break; 00918 } 00919 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 00920 if (ret_val) 00921 goto out; 00922 } 00923 00924 out: 00925 return ret_val; 00926 }
e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link : pointer to the HW structure
Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock and downshift values are set also.
Definition at line 653 of file e1000e_phy.c.
References BME1000_E_PHY_ID_R2, BME1000_PSCR_ENABLE_DOWNSHIFT, e1000_phy_info::disable_polarity_correction, e1000_phy_82578, e1000_phy_bm, e1000_phy_m88, E1000_REVISION_2, E1000_REVISION_4, E1000_SUCCESS, e1000e_commit_phy(), e1e_rphy(), e1e_wphy(), e_dbg, I82578_EPSCR_DOWNSHIFT_COUNTER_MASK, I82578_EPSCR_DOWNSHIFT_ENABLE, e1000_phy_info::id, M88E1000_EPSCR_MASTER_DOWNSHIFT_1X, M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK, M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X, M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK, M88E1000_EPSCR_TX_CLK_25, M88E1000_EXT_PHY_SPEC_CTRL, M88E1000_PHY_SPEC_CTRL, M88E1000_PSCR_ASSERT_CRS_ON_TX, M88E1000_PSCR_AUTO_X_1000T, M88E1000_PSCR_AUTO_X_MODE, M88E1000_PSCR_MDI_MANUAL_MODE, M88E1000_PSCR_MDIX_MANUAL_MODE, M88E1000_PSCR_POLARITY_REVERSAL, M88E1111_I_PHY_ID, M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X, M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK, e1000_phy_info::mdix, e1000_hw::phy, e1000_phy_info::reset_disable, e1000_phy_info::revision, e1000_phy_info::type, and u16.
00654 { 00655 struct e1000_phy_info *phy = &hw->phy; 00656 s32 ret_val; 00657 u16 phy_data; 00658 00659 if (phy->reset_disable) { 00660 ret_val = E1000_SUCCESS; 00661 goto out; 00662 } 00663 00664 /* Enable CRS on TX. This must be set for half-duplex operation. */ 00665 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 00666 if (ret_val) 00667 goto out; 00668 00669 /* For BM PHY this bit is downshift enable */ 00670 if (phy->type != e1000_phy_bm) 00671 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 00672 00673 /* 00674 * Options: 00675 * MDI/MDI-X = 0 (default) 00676 * 0 - Auto for all speeds 00677 * 1 - MDI mode 00678 * 2 - MDI-X mode 00679 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 00680 */ 00681 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 00682 00683 switch (phy->mdix) { 00684 case 1: 00685 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 00686 break; 00687 case 2: 00688 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 00689 break; 00690 case 3: 00691 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 00692 break; 00693 case 0: 00694 default: 00695 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 00696 break; 00697 } 00698 00699 /* 00700 * Options: 00701 * disable_polarity_correction = 0 (default) 00702 * Automatic Correction for Reversed Cable Polarity 00703 * 0 - Disabled 00704 * 1 - Enabled 00705 */ 00706 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 00707 if (phy->disable_polarity_correction == 1) 00708 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 00709 00710 /* Enable downshift on BM (disabled by default) */ 00711 if (phy->type == e1000_phy_bm) 00712 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 00713 00714 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 00715 if (ret_val) 00716 goto out; 00717 00718 if ((phy->type == e1000_phy_m88) && 00719 (phy->revision < E1000_REVISION_4) && 00720 (phy->id != BME1000_E_PHY_ID_R2)) { 00721 /* 00722 * Force TX_CLK in the Extended PHY Specific Control Register 00723 * to 25MHz clock. 00724 */ 00725 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00726 &phy_data); 00727 if (ret_val) 00728 goto out; 00729 00730 phy_data |= M88E1000_EPSCR_TX_CLK_25; 00731 00732 if ((phy->revision == E1000_REVISION_2) && 00733 (phy->id == M88E1111_I_PHY_ID)) { 00734 /* 82573L PHY - set the downshift counter to 5x. */ 00735 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 00736 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 00737 } else { 00738 /* Configure Master and Slave downshift values */ 00739 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 00740 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 00741 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 00742 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 00743 } 00744 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00745 phy_data); 00746 if (ret_val) 00747 goto out; 00748 } 00749 00750 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 00751 /* Set PHY page 0, register 29 to 0x0003 */ 00752 ret_val = e1e_wphy(hw, 29, 0x0003); 00753 if (ret_val) 00754 goto out; 00755 00756 /* Set PHY page 0, register 30 to 0x0000 */ 00757 ret_val = e1e_wphy(hw, 30, 0x0000); 00758 if (ret_val) 00759 goto out; 00760 } 00761 00762 /* Commit the changes. */ 00763 ret_val = e1000e_commit_phy(hw); 00764 if (ret_val) { 00765 e_dbg("Error committing the PHY changes\n"); 00766 goto out; 00767 } 00768 00769 if (phy->type == e1000_phy_82578) { 00770 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00771 &phy_data); 00772 if (ret_val) 00773 goto out; 00774 00775 /* 82578 PHY - set the downshift count to 1x. */ 00776 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 00777 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 00778 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00779 phy_data); 00780 if (ret_val) 00781 goto out; 00782 } 00783 00784 out: 00785 return ret_val; 00786 }
e1000e_get_phy_id - Retrieve the PHY ID and revision : pointer to the HW structure
Reads the PHY registers and stores the PHY ID and possibly the PHY revision in the hardware structure.
Definition at line 88 of file e1000e_phy.c.
References e1000_phy_operations::acquire, E1000_SUCCESS, e1000e_set_mdio_slow_mode_hv(), e1e_rphy(), e1000_phy_info::id, e1000_phy_info::ops, e1000_hw::phy, PHY_ID1, PHY_ID2, PHY_REVISION_MASK, e1000_phy_operations::read_reg, e1000_phy_operations::release, e1000_phy_info::revision, u16, u32, and udelay().
Referenced by e1000e_determine_phy_address(), e1000e_get_phy_id_82571(), e1000e_init_phy_params_80003es2lan(), e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
00089 { 00090 struct e1000_phy_info *phy = &hw->phy; 00091 s32 ret_val = E1000_SUCCESS; 00092 u16 phy_id; 00093 u16 retry_count = 0; 00094 00095 if (!(phy->ops.read_reg)) 00096 goto out; 00097 00098 while (retry_count < 2) { 00099 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); 00100 if (ret_val) 00101 goto out; 00102 00103 phy->id = (u32)(phy_id << 16); 00104 udelay(20); 00105 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); 00106 if (ret_val) 00107 goto out; 00108 00109 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 00110 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 00111 00112 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 00113 goto out; 00114 00115 /* 00116 * If the PHY ID is still unknown, we may have an 82577 00117 * without link. We will try again after setting Slow MDIC 00118 * mode. No harm in trying again in this case since the PHY 00119 * ID is unknown at this point anyway. 00120 */ 00121 ret_val = phy->ops.acquire(hw); 00122 if (ret_val) 00123 goto out; 00124 ret_val = e1000e_set_mdio_slow_mode_hv(hw, true); 00125 if (ret_val) 00126 goto out; 00127 phy->ops.release(hw); 00128 00129 retry_count++; 00130 } 00131 out: 00132 /* Revert to MDIO fast mode, if applicable */ 00133 if (retry_count) { 00134 ret_val = phy->ops.acquire(hw); 00135 if (ret_val) 00136 return ret_val; 00137 ret_val = e1000e_set_mdio_slow_mode_hv(hw, false); 00138 phy->ops.release(hw); 00139 } 00140 00141 return ret_val; 00142 }
e1000e_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure
Read PHY status to determine if link is up. If link is up, then set/determine 10base-T extended distance and polarity correction. Read PHY port status to determine MDI/MDIx and speed. Based on the speed, determine on the cable length, local and remote receiver.
Definition at line 2062 of file e1000e_phy.c.
References e1000_phy_info::cable_length, e1000_1000t_rx_status_not_ok, e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined, E1000_CABLE_LENGTH_UNDEFINED, E1000_ERR_CONFIG, e1000e_check_polarity_igp(), e1000e_phy_has_link_generic(), e1e_rphy(), e_dbg, IGP01E1000_PHY_PORT_STATUS, IGP01E1000_PSSR_MDIX, IGP01E1000_PSSR_SPEED_1000MBPS, IGP01E1000_PSSR_SPEED_MASK, e1000_phy_info::is_mdix, e1000_phy_info::local_rx, e1000_phy_info::ops, e1000_hw::phy, PHY_1000T_STATUS, e1000_phy_info::polarity_correction, e1000_phy_info::remote_rx, SR_1000T_LOCAL_RX_STATUS, SR_1000T_REMOTE_RX_STATUS, and u16.
02063 { 02064 struct e1000_phy_info *phy = &hw->phy; 02065 s32 ret_val; 02066 u16 data; 02067 bool link; 02068 02069 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 02070 if (ret_val) 02071 goto out; 02072 02073 if (!link) { 02074 e_dbg("Phy info is only valid if link is up\n"); 02075 ret_val = -E1000_ERR_CONFIG; 02076 goto out; 02077 } 02078 02079 phy->polarity_correction = true; 02080 02081 ret_val = e1000e_check_polarity_igp(hw); 02082 if (ret_val) 02083 goto out; 02084 02085 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 02086 if (ret_val) 02087 goto out; 02088 02089 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 02090 02091 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 02092 IGP01E1000_PSSR_SPEED_1000MBPS) { 02093 #if 0 02094 ret_val = phy->ops.get_cable_length(hw); 02095 #endif 02096 ret_val = -E1000_ERR_CONFIG; 02097 if (ret_val) 02098 goto out; 02099 #if 0 02100 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 02101 if (ret_val) 02102 goto out; 02103 02104 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 02105 ? e1000_1000t_rx_status_ok 02106 : e1000_1000t_rx_status_not_ok; 02107 02108 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 02109 ? e1000_1000t_rx_status_ok 02110 : e1000_1000t_rx_status_not_ok; 02111 #endif 02112 } else { 02113 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 02114 phy->local_rx = e1000_1000t_rx_status_undefined; 02115 phy->remote_rx = e1000_1000t_rx_status_undefined; 02116 } 02117 out: 02118 return ret_val; 02119 }
e1000e_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure
Valid for only copper links. Read the PHY status register (sticky read) to verify that link is up. Read the PHY special control register to determine the polarity and 10base-T extended distance. Read the PHY special status register to determine MDI/MDIx and current speed. If speed is 1000, then determine cable length, local and remote receiver.
Definition at line 1983 of file e1000e_phy.c.
References e1000_phy_info::cable_length, e1000_1000t_rx_status_not_ok, e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined, E1000_CABLE_LENGTH_UNDEFINED, E1000_ERR_CONFIG, e1000_media_type_copper, e1000e_check_polarity_m88(), e1000e_phy_has_link_generic(), e1e_rphy(), e_dbg, e1000_phy_info::is_mdix, e1000_phy_info::local_rx, M88E1000_PHY_SPEC_CTRL, M88E1000_PHY_SPEC_STATUS, M88E1000_PSCR_POLARITY_REVERSAL, M88E1000_PSSR_1000MBS, M88E1000_PSSR_MDIX, M88E1000_PSSR_SPEED, e1000_phy_info::media_type, e1000_hw::phy, PHY_1000T_STATUS, e1000_phy_info::polarity_correction, e1000_phy_info::remote_rx, SR_1000T_LOCAL_RX_STATUS, SR_1000T_REMOTE_RX_STATUS, and u16.
01984 { 01985 struct e1000_phy_info *phy = &hw->phy; 01986 s32 ret_val; 01987 u16 phy_data; 01988 bool link; 01989 01990 if (phy->media_type != e1000_media_type_copper) { 01991 e_dbg("Phy info is only valid for copper media\n"); 01992 ret_val = -E1000_ERR_CONFIG; 01993 goto out; 01994 } 01995 01996 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 01997 if (ret_val) 01998 goto out; 01999 02000 if (!link) { 02001 e_dbg("Phy info is only valid if link is up\n"); 02002 ret_val = -E1000_ERR_CONFIG; 02003 goto out; 02004 } 02005 02006 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 02007 if (ret_val) 02008 goto out; 02009 02010 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 02011 ? true : false; 02012 02013 ret_val = e1000e_check_polarity_m88(hw); 02014 if (ret_val) 02015 goto out; 02016 02017 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 02018 if (ret_val) 02019 goto out; 02020 02021 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 02022 02023 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 02024 #if 0 02025 ret_val = e1000e_get_cable_length(hw); 02026 #endif 02027 ret_val = -E1000_ERR_CONFIG; 02028 if (ret_val) 02029 goto out; 02030 #if 0 02031 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); 02032 if (ret_val) 02033 goto out; 02034 02035 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 02036 ? e1000_1000t_rx_status_ok 02037 : e1000_1000t_rx_status_not_ok; 02038 02039 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 02040 ? e1000_1000t_rx_status_ok 02041 : e1000_1000t_rx_status_not_ok; 02042 #endif 02043 } else { 02044 /* Set values to "undefined" */ 02045 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 02046 phy->local_rx = e1000_1000t_rx_status_undefined; 02047 phy->remote_rx = e1000_1000t_rx_status_undefined; 02048 } 02049 out: 02050 return ret_val; 02051 }
e1000e_phy_sw_reset - PHY software reset : pointer to the HW structure
Does a software reset of the PHY by reading the PHY control register and setting/write the control register reset bit to the PHY.
Definition at line 2128 of file e1000e_phy.c.
References E1000_SUCCESS, e1e_rphy(), e1e_wphy(), MII_CR_RESET, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, and udelay().
02129 { 02130 s32 ret_val = E1000_SUCCESS; 02131 u16 phy_ctrl; 02132 02133 if (!(hw->phy.ops.read_reg)) 02134 goto out; 02135 02136 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 02137 if (ret_val) 02138 goto out; 02139 02140 phy_ctrl |= MII_CR_RESET; 02141 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); 02142 if (ret_val) 02143 goto out; 02144 02145 udelay(1); 02146 02147 out: 02148 return ret_val; 02149 }
e1000e_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure
Verify the reset block is not blocking us from resetting. Acquire semaphore (if necessary) and read/set/write the device control reset bit in the PHY. Wait the appropriate delay time for the device to reset and release the semaphore (if necessary).
Definition at line 2160 of file e1000e_phy.c.
References e1000_phy_operations::acquire, E1000_CTRL_PHY_RST, E1000_SUCCESS, e1000e_check_reset_block(), e1e_flush, er32, ew32, e1000_phy_operations::get_cfg_done, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, e1000_phy_info::reset_delay_us, u32, and udelay().
02161 { 02162 struct e1000_phy_info *phy = &hw->phy; 02163 s32 ret_val = E1000_SUCCESS; 02164 u32 ctrl; 02165 02166 ret_val = e1000e_check_reset_block(hw); 02167 if (ret_val) { 02168 ret_val = E1000_SUCCESS; 02169 goto out; 02170 } 02171 02172 ret_val = phy->ops.acquire(hw); 02173 if (ret_val) 02174 goto out; 02175 02176 ctrl = er32(CTRL); 02177 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 02178 e1e_flush(); 02179 02180 udelay(phy->reset_delay_us); 02181 02182 ew32(CTRL, ctrl); 02183 e1e_flush(); 02184 02185 udelay(150); 02186 02187 phy->ops.release(hw); 02188 02189 ret_val = phy->ops.get_cfg_done(hw); 02190 02191 out: 02192 return ret_val; 02193 }
e1000e_phy_reset_dsp - Reset PHY DSP : pointer to the HW structure
Reset the digital signal processor.
Definition at line 150 of file e1000e_phy.c.
References E1000_SUCCESS, e1e_wphy(), M88E1000_PHY_GEN_CONTROL, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::write_reg.
00151 { 00152 s32 ret_val = E1000_SUCCESS; 00153 00154 if (!(hw->phy.ops.write_reg)) 00155 goto out; 00156 00157 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 00158 if (ret_val) 00159 goto out; 00160 00161 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); 00162 00163 out: 00164 return ret_val; 00165 }
e1000e_read_kmrn_reg - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore then reads the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Release the acquired semaphore before exiting.
Definition at line 526 of file e1000e_phy.c.
References __e1000e_read_kmrn_reg().
00527 { 00528 return __e1000e_read_kmrn_reg(hw, offset, data, false); 00529 }
e1000e_read_kmrn_reg_locked - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Assumes semaphore already acquired.
Definition at line 541 of file e1000e_phy.c.
References __e1000e_read_kmrn_reg().
Referenced by e1000e_configure_k1_ich8lan().
00542 { 00543 return __e1000e_read_kmrn_reg(hw, offset, data, true); 00544 }
e1000e_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore then reads the PHY register at offset and stores the retrieved information in data. Release the acquired semaphore before exiting.
Definition at line 384 of file e1000e_phy.c.
References __e1000e_read_phy_reg_igp().
00385 { 00386 return __e1000e_read_phy_reg_igp(hw, offset, data, false); 00387 }
e1000e_read_phy_reg_igp_locked - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the PHY register at offset and stores the retrieved information in data. Assumes semaphore already acquired.
Definition at line 398 of file e1000e_phy.c.
References __e1000e_read_phy_reg_igp().
Referenced by e1000e_init_phy_params_ich8lan().
00399 { 00400 return __e1000e_read_phy_reg_igp(hw, offset, data, true); 00401 }
e1000e_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 282 of file e1000e_phy.c.
References e1000_phy_operations::acquire, E1000_SUCCESS, e1000e_read_phy_reg_mdic(), MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::release.
00283 { 00284 s32 ret_val = E1000_SUCCESS; 00285 00286 if (!(hw->phy.ops.acquire)) 00287 goto out; 00288 00289 ret_val = hw->phy.ops.acquire(hw); 00290 if (ret_val) 00291 goto out; 00292 00293 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00294 data); 00295 00296 hw->phy.ops.release(hw); 00297 00298 out: 00299 return ret_val; 00300 }
e1000e_set_d3_lplu_state - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu
Success returns 0, Failure returns 1
The low power link up (lplu) state is set to the power management level D3 and SmartSpeed is disabled when active is true, else clear lplu for D3 and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU is used during Dx states where the power conservation is most important. During driver activity, SmartSpeed should be enabled so performance is maintained.
Definition at line 1550 of file e1000e_phy.c.
References e1000_phy_info::autoneg_advertised, E1000_ALL_10_SPEED, E1000_ALL_NOT_GIG, E1000_ALL_SPEED_DUPLEX, e1000_smart_speed_off, e1000_smart_speed_on, E1000_SUCCESS, e1e_rphy(), e1e_wphy(), IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PSCFR_SMART_SPEED, IGP02E1000_PHY_POWER_MGMT, IGP02E1000_PM_D3_LPLU, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::smart_speed, and u16.
01551 { 01552 struct e1000_phy_info *phy = &hw->phy; 01553 s32 ret_val = E1000_SUCCESS; 01554 u16 data; 01555 01556 if (!(hw->phy.ops.read_reg)) 01557 goto out; 01558 01559 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 01560 if (ret_val) 01561 goto out; 01562 01563 if (!active) { 01564 data &= ~IGP02E1000_PM_D3_LPLU; 01565 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, 01566 data); 01567 if (ret_val) 01568 goto out; 01569 /* 01570 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 01571 * during Dx states where the power conservation is most 01572 * important. During driver activity we should enable 01573 * SmartSpeed, so performance is maintained. 01574 */ 01575 if (phy->smart_speed == e1000_smart_speed_on) { 01576 ret_val = e1e_rphy(hw, 01577 IGP01E1000_PHY_PORT_CONFIG, 01578 &data); 01579 if (ret_val) 01580 goto out; 01581 01582 data |= IGP01E1000_PSCFR_SMART_SPEED; 01583 ret_val = e1e_wphy(hw, 01584 IGP01E1000_PHY_PORT_CONFIG, 01585 data); 01586 if (ret_val) 01587 goto out; 01588 } else if (phy->smart_speed == e1000_smart_speed_off) { 01589 ret_val = e1e_rphy(hw, 01590 IGP01E1000_PHY_PORT_CONFIG, 01591 &data); 01592 if (ret_val) 01593 goto out; 01594 01595 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01596 ret_val = e1e_wphy(hw, 01597 IGP01E1000_PHY_PORT_CONFIG, 01598 data); 01599 if (ret_val) 01600 goto out; 01601 } 01602 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 01603 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 01604 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 01605 data |= IGP02E1000_PM_D3_LPLU; 01606 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, 01607 data); 01608 if (ret_val) 01609 goto out; 01610 01611 /* When LPLU is enabled, we should disable SmartSpeed */ 01612 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 01613 &data); 01614 if (ret_val) 01615 goto out; 01616 01617 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01618 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 01619 data); 01620 } 01621 01622 out: 01623 return ret_val; 01624 }
e1000e_setup_copper_link - Configure copper link settings : pointer to the HW structure
Calls the appropriate function to configure the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called. If link is not established, we return -E1000_ERR_PHY (-2).
Definition at line 1169 of file e1000e_phy.c.
References e1000_mac_info::autoneg, COPPER_LINK_UP_LIMIT, e1000e_config_collision_dist(), e1000e_config_fc_after_link_up(), e1000e_copper_link_autoneg(), e1000e_phy_has_link_generic(), e_dbg, e1000_hw::mac, e1000_phy_info::ops, and e1000_hw::phy.
01170 { 01171 s32 ret_val; 01172 bool link; 01173 01174 if (hw->mac.autoneg) { 01175 /* 01176 * Setup autoneg and flow control advertisement and perform 01177 * autonegotiation. 01178 */ 01179 ret_val = e1000e_copper_link_autoneg(hw); 01180 if (ret_val) 01181 goto out; 01182 } else { 01183 #if 0 01184 /* 01185 * PHY will be set to 10H, 10F, 100H or 100F 01186 * depending on user settings. 01187 */ 01188 e_dbg("Forcing Speed and Duplex\n"); 01189 ret_val = hw->phy.ops.force_speed_duplex(hw); 01190 if (ret_val) { 01191 e_dbg("Error Forcing Speed and Duplex\n"); 01192 goto out; 01193 } 01194 #endif 01195 } 01196 01197 /* 01198 * Check link status. Wait up to 100 microseconds for link to become 01199 * valid. 01200 */ 01201 ret_val = e1000e_phy_has_link_generic(hw, 01202 COPPER_LINK_UP_LIMIT, 01203 10, 01204 &link); 01205 if (ret_val) 01206 goto out; 01207 01208 if (link) { 01209 e_dbg("Valid link established!!!\n"); 01210 e1000e_config_collision_dist(hw); 01211 ret_val = e1000e_config_fc_after_link_up(hw); 01212 } else { 01213 e_dbg("Unable to establish link!!!\n"); 01214 } 01215 01216 out: 01217 return ret_val; 01218 }
e1000e_wait_autoneg - Wait for auto-neg completion : pointer to the HW structure
Waits for auto-negotiation to complete or for the auto-negotiation time limit to expire, which ever happens first.
Definition at line 1781 of file e1000e_phy.c.
References E1000_SUCCESS, e1e_rphy(), MII_SR_AUTONEG_COMPLETE, msleep, e1000_phy_info::ops, e1000_hw::phy, PHY_AUTO_NEG_LIMIT, PHY_STATUS, e1000_phy_operations::read_reg, and u16.
Referenced by e1000e_init_mac_ops_generic().
01782 { 01783 s32 ret_val = E1000_SUCCESS; 01784 u16 i, phy_status; 01785 01786 if (!(hw->phy.ops.read_reg)) 01787 return E1000_SUCCESS; 01788 01789 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 01790 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 01791 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 01792 if (ret_val) 01793 break; 01794 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 01795 if (ret_val) 01796 break; 01797 if (phy_status & MII_SR_AUTONEG_COMPLETE) 01798 break; 01799 msleep(100); 01800 } 01801 01802 /* 01803 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 01804 * has completed. 01805 */ 01806 return ret_val; 01807 }
e1000e_write_kmrn_reg - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore then writes the data to the PHY register at the offset using the kumeran interface. Release the acquired semaphore before exiting.
Definition at line 594 of file e1000e_phy.c.
References __e1000e_write_kmrn_reg().
00595 { 00596 return __e1000e_write_kmrn_reg(hw, offset, data, false); 00597 }
e1000e_write_kmrn_reg_locked - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset
Write the data to PHY register at the offset using the kumeran interface. Assumes semaphore already acquired.
Definition at line 608 of file e1000e_phy.c.
References __e1000e_write_kmrn_reg().
Referenced by e1000e_configure_k1_ich8lan().
00609 { 00610 return __e1000e_write_kmrn_reg(hw, offset, data, true); 00611 }
e1000e_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 455 of file e1000e_phy.c.
References __e1000e_write_phy_reg_igp().
00456 { 00457 return __e1000e_write_phy_reg_igp(hw, offset, data, false); 00458 }
e1000e_write_phy_reg_igp_locked - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Writes the data to PHY register at the offset. Assumes semaphore already acquired.
Definition at line 469 of file e1000e_phy.c.
References __e1000e_write_phy_reg_igp().
Referenced by e1000e_init_phy_params_ich8lan().
00470 { 00471 return __e1000e_write_phy_reg_igp(hw, offset, data, true); 00472 }
e1000e_write_phy_reg_m88 - Write m88 PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 311 of file e1000e_phy.c.
References e1000_phy_operations::acquire, E1000_SUCCESS, e1000e_write_phy_reg_mdic(), MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::release.
00312 { 00313 s32 ret_val = E1000_SUCCESS; 00314 00315 if (!(hw->phy.ops.acquire)) 00316 goto out; 00317 00318 ret_val = hw->phy.ops.acquire(hw); 00319 if (ret_val) 00320 goto out; 00321 00322 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00323 data); 00324 00325 hw->phy.ops.release(hw); 00326 00327 out: 00328 return ret_val; 00329 }
| s32 e1000e_phy_has_link_generic | ( | struct e1000_hw * | hw, | |
| u32 | iterations, | |||
| u32 | usec_interval, | |||
| bool * | success | |||
| ) |
e1000e_phy_has_link_generic - Polls PHY for link : pointer to the HW structure : number of times to poll for link : delay between polling attempts : pointer to whether polling was successful or not
Polls the PHY status register for link, 'iterations' number of times.
Definition at line 1818 of file e1000e_phy.c.
References E1000_SUCCESS, e1e_rphy(), mdelay(), MII_SR_LINK_STATUS, e1000_phy_info::ops, e1000_hw::phy, PHY_STATUS, e1000_phy_operations::read_reg, u16, and udelay().
01820 { 01821 s32 ret_val = E1000_SUCCESS; 01822 u16 i, phy_status; 01823 01824 if (!(hw->phy.ops.read_reg)) 01825 return E1000_SUCCESS; 01826 01827 for (i = 0; i < iterations; i++) { 01828 /* 01829 * Some PHYs require the PHY_STATUS register to be read 01830 * twice due to the link bit being sticky. No harm doing 01831 * it across the board. 01832 */ 01833 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 01834 if (ret_val) { 01835 /* 01836 * If the first read fails, another entity may have 01837 * ownership of the resources, wait and try again to 01838 * see if they have relinquished the resources yet. 01839 */ 01840 udelay(usec_interval); 01841 } 01842 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 01843 if (ret_val) 01844 break; 01845 if (phy_status & MII_SR_LINK_STATUS) 01846 break; 01847 if (usec_interval >= 1000) 01848 mdelay(usec_interval/1000); 01849 else 01850 udelay(usec_interval); 01851 } 01852 01853 *success = (i < iterations) ? true : false; 01854 01855 return ret_val; 01856 }
e1000e_phy_init_script_igp3 - Inits the IGP3 PHY : pointer to the HW structure
Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
Definition at line 2215 of file e1000e_phy.c.
References E1000_SUCCESS, e1e_wphy(), and e_dbg.
Referenced by e1000e_get_cfg_done_ich8lan().
02216 { 02217 e_dbg("Running IGP 3 PHY init script\n"); 02218 02219 /* PHY init IGP 3 */ 02220 /* Enable rise/fall, 10-mode work in class-A */ 02221 e1e_wphy(hw, 0x2F5B, 0x9018); 02222 /* Remove all caps from Replica path filter */ 02223 e1e_wphy(hw, 0x2F52, 0x0000); 02224 /* Bias trimming for ADC, AFE and Driver (Default) */ 02225 e1e_wphy(hw, 0x2FB1, 0x8B24); 02226 /* Increase Hybrid poly bias */ 02227 e1e_wphy(hw, 0x2FB2, 0xF8F0); 02228 /* Add 4% to Tx amplitude in Gig mode */ 02229 e1e_wphy(hw, 0x2010, 0x10B0); 02230 /* Disable trimming (TTT) */ 02231 e1e_wphy(hw, 0x2011, 0x0000); 02232 /* Poly DC correction to 94.6% + 2% for all channels */ 02233 e1e_wphy(hw, 0x20DD, 0x249A); 02234 /* ABS DC correction to 95.9% */ 02235 e1e_wphy(hw, 0x20DE, 0x00D3); 02236 /* BG temp curve trim */ 02237 e1e_wphy(hw, 0x28B4, 0x04CE); 02238 /* Increasing ADC OPAMP stage 1 currents to max */ 02239 e1e_wphy(hw, 0x2F70, 0x29E4); 02240 /* Force 1000 ( required for enabling PHY regs configuration) */ 02241 e1e_wphy(hw, 0x0000, 0x0140); 02242 /* Set upd_freq to 6 */ 02243 e1e_wphy(hw, 0x1F30, 0x1606); 02244 /* Disable NPDFE */ 02245 e1e_wphy(hw, 0x1F31, 0xB814); 02246 /* Disable adaptive fixed FFE (Default) */ 02247 e1e_wphy(hw, 0x1F35, 0x002A); 02248 /* Enable FFE hysteresis */ 02249 e1e_wphy(hw, 0x1F3E, 0x0067); 02250 /* Fixed FFE for short cable lengths */ 02251 e1e_wphy(hw, 0x1F54, 0x0065); 02252 /* Fixed FFE for medium cable lengths */ 02253 e1e_wphy(hw, 0x1F55, 0x002A); 02254 /* Fixed FFE for long cable lengths */ 02255 e1e_wphy(hw, 0x1F56, 0x002A); 02256 /* Enable Adaptive Clip Threshold */ 02257 e1e_wphy(hw, 0x1F72, 0x3FB0); 02258 /* AHT reset limit to 1 */ 02259 e1e_wphy(hw, 0x1F76, 0xC0FF); 02260 /* Set AHT master delay to 127 msec */ 02261 e1e_wphy(hw, 0x1F77, 0x1DEC); 02262 /* Set scan bits for AHT */ 02263 e1e_wphy(hw, 0x1F78, 0xF9EF); 02264 /* Set AHT Preset bits */ 02265 e1e_wphy(hw, 0x1F79, 0x0210); 02266 /* Change integ_factor of channel A to 3 */ 02267 e1e_wphy(hw, 0x1895, 0x0003); 02268 /* Change prop_factor of channels BCD to 8 */ 02269 e1e_wphy(hw, 0x1796, 0x0008); 02270 /* Change cg_icount + enable integbp for channels BCD */ 02271 e1e_wphy(hw, 0x1798, 0xD008); 02272 /* 02273 * Change cg_icount + enable integbp + change prop_factor_master 02274 * to 8 for channel A 02275 */ 02276 e1e_wphy(hw, 0x1898, 0xD918); 02277 /* Disable AHT in Slave mode on channel A */ 02278 e1e_wphy(hw, 0x187A, 0x0800); 02279 /* 02280 * Enable LPLU and disable AN to 1000 in non-D0a states, 02281 * Enable SPD+B2B 02282 */ 02283 e1e_wphy(hw, 0x0019, 0x008D); 02284 /* Enable restart AN on an1000_dis change */ 02285 e1e_wphy(hw, 0x001B, 0x2080); 02286 /* Enable wh_fifo read clock in 10/100 modes */ 02287 e1e_wphy(hw, 0x0014, 0x0045); 02288 /* Restart AN, Speed selection is 1000 */ 02289 e1e_wphy(hw, 0x0000, 0x1340); 02290 02291 return E1000_SUCCESS; 02292 }
| enum e1000_phy_type e1000e_get_phy_type_from_id | ( | u32 | phy_id | ) |
e1000e_get_phy_type_from_id - Get PHY type from id : phy_id read from the phy
Returns the phy type from the id.
Definition at line 2300 of file e1000e_phy.c.
References BME1000_E_PHY_ID, BME1000_E_PHY_ID_R2, e1000_phy_82577, e1000_phy_82578, e1000_phy_bm, e1000_phy_gg82563, e1000_phy_ife, e1000_phy_igp_2, e1000_phy_igp_3, e1000_phy_m88, e1000_phy_unknown, GG82563_E_PHY_ID, I82577_E_PHY_ID, I82578_E_PHY_ID, IFE_C_E_PHY_ID, IFE_E_PHY_ID, IFE_PLUS_E_PHY_ID, IGP01E1000_I_PHY_ID, IGP03E1000_E_PHY_ID, M88E1000_E_PHY_ID, M88E1000_I_PHY_ID, M88E1011_I_PHY_ID, and M88E1111_I_PHY_ID.
02301 { 02302 enum e1000_phy_type phy_type = e1000_phy_unknown; 02303 02304 switch (phy_id) { 02305 case M88E1000_I_PHY_ID: 02306 case M88E1000_E_PHY_ID: 02307 case M88E1111_I_PHY_ID: 02308 case M88E1011_I_PHY_ID: 02309 phy_type = e1000_phy_m88; 02310 break; 02311 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 02312 phy_type = e1000_phy_igp_2; 02313 break; 02314 case GG82563_E_PHY_ID: 02315 phy_type = e1000_phy_gg82563; 02316 break; 02317 case IGP03E1000_E_PHY_ID: 02318 phy_type = e1000_phy_igp_3; 02319 break; 02320 case IFE_E_PHY_ID: 02321 case IFE_PLUS_E_PHY_ID: 02322 case IFE_C_E_PHY_ID: 02323 phy_type = e1000_phy_ife; 02324 break; 02325 case BME1000_E_PHY_ID: 02326 case BME1000_E_PHY_ID_R2: 02327 phy_type = e1000_phy_bm; 02328 break; 02329 case I82578_E_PHY_ID: 02330 phy_type = e1000_phy_82578; 02331 break; 02332 case I82577_E_PHY_ID: 02333 phy_type = e1000_phy_82577; 02334 break; 02335 default: 02336 phy_type = e1000_phy_unknown; 02337 break; 02338 } 02339 return phy_type; 02340 }
e1000e_determine_phy_address - Determines PHY address.
: pointer to the HW structure
This uses a trial and error method to loop through possible PHY addresses. It tests each by reading the PHY ID registers and checking for a match.
Definition at line 2350 of file e1000e_phy.c.
References e1000_phy_info::addr, E1000_ERR_PHY_TYPE, E1000_MAX_PHY_ADDR, e1000_phy_unknown, E1000_SUCCESS, e1000e_get_phy_id(), e1000e_get_phy_type_from_id(), e1000_phy_info::id, msleep, e1000_hw::phy, and u32.
02351 { 02352 s32 ret_val = -E1000_ERR_PHY_TYPE; 02353 u32 phy_addr = 0; 02354 u32 i; 02355 enum e1000_phy_type phy_type = e1000_phy_unknown; 02356 02357 hw->phy.id = phy_type; 02358 02359 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 02360 hw->phy.addr = phy_addr; 02361 i = 0; 02362 02363 do { 02364 e1000e_get_phy_id(hw); 02365 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 02366 02367 /* 02368 * If phy_type is valid, break - we found our 02369 * PHY address 02370 */ 02371 if (phy_type != e1000_phy_unknown) { 02372 ret_val = E1000_SUCCESS; 02373 goto out; 02374 } 02375 msleep(1); 02376 i++; 02377 } while (i < 10); 02378 } 02379 02380 out: 02381 return ret_val; 02382 }
e1000e_write_phy_reg_bm - Write BM PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 2409 of file e1000e_phy.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, BM_PHY_PAGE_SELECT, BM_WUC_PAGE, e1000e_access_phy_wakeup_reg_bm(), e1000e_get_phy_addr_for_bm_page(), e1000e_write_phy_reg_mdic(), IGP01E1000_PHY_PAGE_SELECT, IGP_PAGE_SHIFT, MAX_PHY_MULTI_PAGE_REG, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, and u32.
02410 { 02411 s32 ret_val; 02412 u32 page_select = 0; 02413 u32 page = offset >> IGP_PAGE_SHIFT; 02414 u32 page_shift = 0; 02415 02416 ret_val = hw->phy.ops.acquire(hw); 02417 if (ret_val) 02418 return ret_val; 02419 02420 /* Page 800 works differently than the rest so it has its own func */ 02421 if (page == BM_WUC_PAGE) { 02422 ret_val = e1000e_access_phy_wakeup_reg_bm(hw, offset, &data, 02423 false); 02424 goto out; 02425 } 02426 02427 hw->phy.addr = e1000e_get_phy_addr_for_bm_page(page, offset); 02428 02429 if (offset > MAX_PHY_MULTI_PAGE_REG) { 02430 /* 02431 * Page select is register 31 for phy address 1 and 22 for 02432 * phy address 2 and 3. Page select is shifted only for 02433 * phy address 1. 02434 */ 02435 if (hw->phy.addr == 1) { 02436 page_shift = IGP_PAGE_SHIFT; 02437 page_select = IGP01E1000_PHY_PAGE_SELECT; 02438 } else { 02439 page_shift = 0; 02440 page_select = BM_PHY_PAGE_SELECT; 02441 } 02442 02443 /* Page is shifted left, PHY expects (page x 32) */ 02444 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 02445 (page << page_shift)); 02446 if (ret_val) 02447 goto out; 02448 } 02449 02450 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 02451 data); 02452 02453 out: 02454 hw->phy.ops.release(hw); 02455 return ret_val; 02456 }
e1000e_read_phy_reg_bm - Read BM PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 2468 of file e1000e_phy.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, BM_PHY_PAGE_SELECT, BM_WUC_PAGE, e1000e_access_phy_wakeup_reg_bm(), e1000e_get_phy_addr_for_bm_page(), e1000e_read_phy_reg_mdic(), e1000e_write_phy_reg_mdic(), IGP01E1000_PHY_PAGE_SELECT, IGP_PAGE_SHIFT, MAX_PHY_MULTI_PAGE_REG, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, and u32.
02469 { 02470 s32 ret_val; 02471 u32 page_select = 0; 02472 u32 page = offset >> IGP_PAGE_SHIFT; 02473 u32 page_shift = 0; 02474 02475 ret_val = hw->phy.ops.acquire(hw); 02476 if (ret_val) 02477 return ret_val; 02478 02479 /* Page 800 works differently than the rest so it has its own func */ 02480 if (page == BM_WUC_PAGE) { 02481 ret_val = e1000e_access_phy_wakeup_reg_bm(hw, offset, data, 02482 true); 02483 goto out; 02484 } 02485 02486 hw->phy.addr = e1000e_get_phy_addr_for_bm_page(page, offset); 02487 02488 if (offset > MAX_PHY_MULTI_PAGE_REG) { 02489 /* 02490 * Page select is register 31 for phy address 1 and 22 for 02491 * phy address 2 and 3. Page select is shifted only for 02492 * phy address 1. 02493 */ 02494 if (hw->phy.addr == 1) { 02495 page_shift = IGP_PAGE_SHIFT; 02496 page_select = IGP01E1000_PHY_PAGE_SELECT; 02497 } else { 02498 page_shift = 0; 02499 page_select = BM_PHY_PAGE_SELECT; 02500 } 02501 02502 /* Page is shifted left, PHY expects (page x 32) */ 02503 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 02504 (page << page_shift)); 02505 if (ret_val) 02506 goto out; 02507 } 02508 02509 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 02510 data); 02511 out: 02512 hw->phy.ops.release(hw); 02513 return ret_val; 02514 }
e1000e_read_phy_reg_bm2 - Read BM PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 2526 of file e1000e_phy.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, BM_PHY_PAGE_SELECT, BM_WUC_PAGE, e1000e_access_phy_wakeup_reg_bm(), e1000e_read_phy_reg_mdic(), e1000e_write_phy_reg_mdic(), IGP_PAGE_SHIFT, MAX_PHY_MULTI_PAGE_REG, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, and u16.
Referenced by e1000e_init_phy_params_82571().
02527 { 02528 s32 ret_val; 02529 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 02530 02531 ret_val = hw->phy.ops.acquire(hw); 02532 if (ret_val) 02533 return ret_val; 02534 02535 /* Page 800 works differently than the rest so it has its own func */ 02536 if (page == BM_WUC_PAGE) { 02537 ret_val = e1000e_access_phy_wakeup_reg_bm(hw, offset, data, 02538 true); 02539 goto out; 02540 } 02541 02542 hw->phy.addr = 1; 02543 02544 if (offset > MAX_PHY_MULTI_PAGE_REG) { 02545 02546 /* Page is shifted left, PHY expects (page x 32) */ 02547 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 02548 page); 02549 02550 if (ret_val) 02551 goto out; 02552 } 02553 02554 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 02555 data); 02556 out: 02557 hw->phy.ops.release(hw); 02558 return ret_val; 02559 }
e1000e_write_phy_reg_bm2 - Write BM PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 2570 of file e1000e_phy.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, BM_PHY_PAGE_SELECT, BM_WUC_PAGE, e1000e_access_phy_wakeup_reg_bm(), e1000e_write_phy_reg_mdic(), IGP_PAGE_SHIFT, MAX_PHY_MULTI_PAGE_REG, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, and u16.
Referenced by e1000e_init_phy_params_82571().
02571 { 02572 s32 ret_val; 02573 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 02574 02575 ret_val = hw->phy.ops.acquire(hw); 02576 if (ret_val) 02577 return ret_val; 02578 02579 /* Page 800 works differently than the rest so it has its own func */ 02580 if (page == BM_WUC_PAGE) { 02581 ret_val = e1000e_access_phy_wakeup_reg_bm(hw, offset, &data, 02582 false); 02583 goto out; 02584 } 02585 02586 hw->phy.addr = 1; 02587 02588 if (offset > MAX_PHY_MULTI_PAGE_REG) { 02589 /* Page is shifted left, PHY expects (page x 32) */ 02590 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 02591 page); 02592 02593 if (ret_val) 02594 goto out; 02595 } 02596 02597 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 02598 data); 02599 02600 out: 02601 hw->phy.ops.release(hw); 02602 return ret_val; 02603 }
| void e1000e_power_up_phy_copper | ( | struct e1000_hw * | hw | ) |
e1000e_power_up_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, restore the link to previous settings.
Definition at line 2718 of file e1000e_phy.c.
References e1e_rphy(), e1e_wphy(), MII_CR_POWER_DOWN, PHY_CONTROL, and u16.
Referenced by e1000e_init_phy_params_80003es2lan(), e1000e_init_phy_params_82571(), e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
02719 { 02720 u16 mii_reg = 0; 02721 02722 /* The PHY will retain its settings across a power down/up cycle */ 02723 e1e_rphy(hw, PHY_CONTROL, &mii_reg); 02724 mii_reg &= ~MII_CR_POWER_DOWN; 02725 e1e_wphy(hw, PHY_CONTROL, mii_reg); 02726 }
| void e1000e_power_down_phy_copper | ( | struct e1000_hw * | hw | ) |
e1000e_power_down_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, restore the link to previous settings.
Definition at line 2736 of file e1000e_phy.c.
References e1e_rphy(), e1e_wphy(), MII_CR_POWER_DOWN, msleep, PHY_CONTROL, and u16.
Referenced by e1000e_power_down_phy_copper_80003es2lan(), e1000e_power_down_phy_copper_82571(), and e1000e_power_down_phy_copper_ich8lan().
02737 { 02738 u16 mii_reg = 0; 02739 02740 /* The PHY will retain its settings across a power down/up cycle */ 02741 e1e_rphy(hw, PHY_CONTROL, &mii_reg); 02742 mii_reg |= MII_CR_POWER_DOWN; 02743 e1e_wphy(hw, PHY_CONTROL, mii_reg); 02744 msleep(1); 02745 }
e1000e_read_phy_reg_mdic - Read MDI control register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the MDI control register in the PHY at offset and stores the information read to data.
Definition at line 176 of file e1000e_phy.c.
References e1000_phy_info::addr, E1000_ERR_PHY, E1000_GEN_POLL_TIMEOUT, E1000_MDIC_ERROR, E1000_MDIC_OP_READ, E1000_MDIC_PHY_SHIFT, E1000_MDIC_READY, E1000_MDIC_REG_SHIFT, E1000_SUCCESS, e_dbg, er32, ew32, e1000_hw::phy, u16, u32, and udelay().
00177 { 00178 struct e1000_phy_info *phy = &hw->phy; 00179 u32 i, mdic = 0; 00180 s32 ret_val = E1000_SUCCESS; 00181 00182 /* 00183 * Set up Op-code, Phy Address, and register offset in the MDI 00184 * Control register. The MAC will take care of interfacing with the 00185 * PHY to retrieve the desired data. 00186 */ 00187 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 00188 (phy->addr << E1000_MDIC_PHY_SHIFT) | 00189 (E1000_MDIC_OP_READ)); 00190 00191 ew32(MDIC, mdic); 00192 00193 /* 00194 * Poll the ready bit to see if the MDI read completed 00195 * Increasing the time out as testing showed failures with 00196 * the lower time out 00197 */ 00198 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 00199 udelay(50); 00200 mdic = er32(MDIC); 00201 if (mdic & E1000_MDIC_READY) 00202 break; 00203 } 00204 if (!(mdic & E1000_MDIC_READY)) { 00205 e_dbg("MDI Read did not complete\n"); 00206 ret_val = -E1000_ERR_PHY; 00207 goto out; 00208 } 00209 if (mdic & E1000_MDIC_ERROR) { 00210 e_dbg("MDI Error\n"); 00211 ret_val = -E1000_ERR_PHY; 00212 goto out; 00213 } 00214 *data = (u16) mdic; 00215 00216 out: 00217 return ret_val; 00218 }
e1000e_write_phy_reg_mdic - Write MDI control register : pointer to the HW structure : register offset to write to : data to write to register at offset
Writes data to MDI control register in the PHY at offset.
Definition at line 228 of file e1000e_phy.c.
References e1000_phy_info::addr, E1000_ERR_PHY, E1000_GEN_POLL_TIMEOUT, E1000_MDIC_ERROR, E1000_MDIC_OP_WRITE, E1000_MDIC_PHY_SHIFT, E1000_MDIC_READY, E1000_MDIC_REG_SHIFT, E1000_SUCCESS, e_dbg, er32, ew32, e1000_hw::phy, u32, and udelay().
00229 { 00230 struct e1000_phy_info *phy = &hw->phy; 00231 u32 i, mdic = 0; 00232 s32 ret_val = E1000_SUCCESS; 00233 00234 /* 00235 * Set up Op-code, Phy Address, and register offset in the MDI 00236 * Control register. The MAC will take care of interfacing with the 00237 * PHY to retrieve the desired data. 00238 */ 00239 mdic = (((u32)data) | 00240 (offset << E1000_MDIC_REG_SHIFT) | 00241 (phy->addr << E1000_MDIC_PHY_SHIFT) | 00242 (E1000_MDIC_OP_WRITE)); 00243 00244 ew32(MDIC, mdic); 00245 00246 /* 00247 * Poll the ready bit to see if the MDI read completed 00248 * Increasing the time out as testing showed failures with 00249 * the lower time out 00250 */ 00251 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 00252 udelay(50); 00253 mdic = er32(MDIC); 00254 if (mdic & E1000_MDIC_READY) 00255 break; 00256 } 00257 if (!(mdic & E1000_MDIC_READY)) { 00258 e_dbg("MDI Write did not complete\n"); 00259 ret_val = -E1000_ERR_PHY; 00260 goto out; 00261 } 00262 if (mdic & E1000_MDIC_ERROR) { 00263 e_dbg("MDI Error\n"); 00264 ret_val = -E1000_ERR_PHY; 00265 goto out; 00266 } 00267 00268 out: 00269 return ret_val; 00270 }
e1000e_read_phy_reg_hv - Read HV PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore then reads the PHY register at offset and stores the retrieved information in data. Release the acquired semaphore before exiting.
Definition at line 2870 of file e1000e_phy.c.
References __e1000e_read_phy_reg_hv().
Referenced by e1000e_init_phy_params_pchlan().
02871 { 02872 return __e1000e_read_phy_reg_hv(hw, offset, data, false); 02873 }
e1000e_read_phy_reg_hv_locked - Read HV PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the PHY register at offset and stores the retrieved information in data. Assumes semaphore already acquired.
Definition at line 2884 of file e1000e_phy.c.
References __e1000e_read_phy_reg_hv().
Referenced by e1000e_init_phy_params_pchlan().
02885 { 02886 return __e1000e_read_phy_reg_hv(hw, offset, data, true); 02887 }
e1000e_write_phy_reg_hv - Write HV PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore then writes the data to PHY register at the offset. Release the acquired semaphores before exiting.
Definition at line 2995 of file e1000e_phy.c.
References __e1000e_write_phy_reg_hv().
Referenced by e1000e_init_phy_params_pchlan().
02996 { 02997 return __e1000e_write_phy_reg_hv(hw, offset, data, false); 02998 }
e1000e_write_phy_reg_hv_locked - Write HV PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Writes the data to PHY register at the offset. Assumes semaphore already acquired.
Definition at line 3009 of file e1000e_phy.c.
References __e1000e_write_phy_reg_hv().
Referenced by e1000e_init_phy_params_pchlan(), and e1000e_sw_lcd_config_ich8lan().
03010 { 03011 return __e1000e_write_phy_reg_hv(hw, offset, data, true); 03012 }
e1000e_set_mdio_slow_mode_hv - Set slow MDIO access mode : pointer to the HW structure : true for slow mode, false for normal mode
Assumes semaphore already acquired.
Definition at line 2754 of file e1000e_phy.c.
References e1000_phy_info::addr, BM_CS_CTRL1, BM_PORT_CTRL_PAGE, E1000_SUCCESS, e1000e_read_phy_reg_mdic(), e1000e_write_phy_reg_mdic(), IGP01E1000_PHY_PAGE_SELECT, IGP_PAGE_SHIFT, e1000_hw::phy, and u16.
Referenced by __e1000e_read_phy_reg_hv(), __e1000e_write_phy_reg_hv(), and e1000e_get_phy_id().
02755 { 02756 s32 ret_val = E1000_SUCCESS; 02757 u16 data = 0; 02758 02759 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */ 02760 hw->phy.addr = 1; 02761 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 02762 (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 02763 if (ret_val) 02764 goto out; 02765 02766 ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1, 02767 (0x2180 | (slow << 10))); 02768 if (ret_val) 02769 goto out; 02770 02771 /* dummy read when reverting to fast mode - throw away result */ 02772 if (!slow) 02773 ret_val = e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data); 02774 02775 out: 02776 return ret_val; 02777 }
e1000e_link_stall_workaround_hv - Si workaround : pointer to the HW structure
This function works around a Si bug where the link partner can get a link up indication before the PHY does. If small packets are sent by the link partner they can be placed in the packet buffer without being properly accounted for by the PHY and will stall preventing further packets from being received. The workaround is to clear the packet buffer after the PHY detects link up.
Definition at line 3087 of file e1000e_phy.c.
References BM_CS_STATUS, BM_CS_STATUS_LINK_UP, BM_CS_STATUS_RESOLVED, BM_CS_STATUS_SPEED_1000, BM_CS_STATUS_SPEED_MASK, e1000_phy_82578, E1000_SUCCESS, e1e_rphy(), e1e_wphy(), HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_FORCE_SPEED, HV_MUX_DATA_CTRL_GEN_TO_MAC, msleep, e1000_hw::phy, PHY_CONTROL, PHY_CONTROL_LB, e1000_phy_info::type, and u16.
Referenced by e1000e_check_for_copper_link_ich8lan().
03088 { 03089 s32 ret_val = E1000_SUCCESS; 03090 u16 data; 03091 03092 if (hw->phy.type != e1000_phy_82578) 03093 goto out; 03094 03095 /* Do not apply workaround if in PHY loopback bit 14 set */ 03096 e1e_rphy(hw, PHY_CONTROL, &data); 03097 if (data & PHY_CONTROL_LB) 03098 goto out; 03099 03100 /* check if link is up and at 1Gbps */ 03101 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); 03102 if (ret_val) 03103 goto out; 03104 03105 data &= BM_CS_STATUS_LINK_UP | 03106 BM_CS_STATUS_RESOLVED | 03107 BM_CS_STATUS_SPEED_MASK; 03108 03109 if (data != (BM_CS_STATUS_LINK_UP | 03110 BM_CS_STATUS_RESOLVED | 03111 BM_CS_STATUS_SPEED_1000)) 03112 goto out; 03113 03114 msleep(200); 03115 03116 /* flush the packets in the fifo buffer */ 03117 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, 03118 HV_MUX_DATA_CTRL_GEN_TO_MAC | 03119 HV_MUX_DATA_CTRL_FORCE_SPEED); 03120 if (ret_val) 03121 goto out; 03122 03123 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, 03124 HV_MUX_DATA_CTRL_GEN_TO_MAC); 03125 03126 out: 03127 return ret_val; 03128 }
e1000e_copper_link_setup_82577 - Setup 82577 PHY for copper link : pointer to the HW structure
Sets up Carrier-sense on Transmit and downshift values.
Definition at line 619 of file e1000e_phy.c.
References E1000_SUCCESS, e1e_rphy(), e1e_wphy(), I82577_CFG_ASSERT_CRS_ON_TX, I82577_CFG_ENABLE_DOWNSHIFT, I82577_CFG_REG, e1000_hw::phy, e1000_phy_info::reset_disable, and u16.
Referenced by e1000e_setup_copper_link_ich8lan().
00620 { 00621 struct e1000_phy_info *phy = &hw->phy; 00622 s32 ret_val; 00623 u16 phy_data; 00624 00625 if (phy->reset_disable) { 00626 ret_val = E1000_SUCCESS; 00627 goto out; 00628 } 00629 00630 /* Enable CRS on TX. This must be set for half-duplex operation. */ 00631 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); 00632 if (ret_val) 00633 goto out; 00634 00635 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 00636 00637 /* Enable downshift */ 00638 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 00639 00640 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); 00641 00642 out: 00643 return ret_val; 00644 }
e1000e_check_polarity_82577 - Checks the polarity.
: pointer to the HW structure
Success returns 0, Failure returns -E1000_ERR_PHY (-2)
Polarity is determined based on the PHY specific status register.
Definition at line 3138 of file e1000e_phy.c.
References e1000_phy_info::cable_polarity, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, e1e_rphy(), I82577_PHY_STATUS2_REV_POLARITY, I82577_PHY_STATUS_2, e1000_hw::phy, and u16.
Referenced by e1000e_get_phy_info_82577(), and e1000e_init_phy_params_pchlan().
03139 { 03140 struct e1000_phy_info *phy = &hw->phy; 03141 s32 ret_val; 03142 u16 data; 03143 03144 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 03145 03146 if (!ret_val) 03147 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) 03148 ? e1000_rev_polarity_reversed 03149 : e1000_rev_polarity_normal; 03150 03151 return ret_val; 03152 }
e1000e_get_phy_info_82577 - Retrieve I82577 PHY information : pointer to the HW structure
Read PHY status to determine if link is up. If link is up, then set/determine 10base-T extended distance and polarity correction. Read PHY port status to determine MDI/MDIx and speed. Based on the speed, determine on the cable length, local and remote receiver.
Definition at line 3235 of file e1000e_phy.c.
References e1000_phy_info::cable_length, e1000_1000t_rx_status_not_ok, e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined, E1000_CABLE_LENGTH_UNDEFINED, E1000_ERR_CONFIG, e1000e_check_polarity_82577(), e1000e_phy_has_link_generic(), e1e_rphy(), e_dbg, I82577_PHY_STATUS2_MDIX, I82577_PHY_STATUS2_SPEED_1000MBPS, I82577_PHY_STATUS2_SPEED_MASK, I82577_PHY_STATUS_2, e1000_phy_info::is_mdix, e1000_phy_info::local_rx, e1000_hw::phy, PHY_1000T_STATUS, e1000_phy_info::polarity_correction, e1000_phy_info::remote_rx, SR_1000T_LOCAL_RX_STATUS, SR_1000T_REMOTE_RX_STATUS, and u16.
Referenced by e1000e_init_phy_params_pchlan().
03236 { 03237 struct e1000_phy_info *phy = &hw->phy; 03238 s32 ret_val; 03239 u16 data; 03240 bool link; 03241 03242 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 03243 if (ret_val) 03244 goto out; 03245 03246 if (!link) { 03247 e_dbg("Phy info is only valid if link is up\n"); 03248 ret_val = -E1000_ERR_CONFIG; 03249 goto out; 03250 } 03251 03252 phy->polarity_correction = true; 03253 03254 ret_val = e1000e_check_polarity_82577(hw); 03255 if (ret_val) 03256 goto out; 03257 03258 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); 03259 if (ret_val) 03260 goto out; 03261 03262 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; 03263 03264 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 03265 I82577_PHY_STATUS2_SPEED_1000MBPS) { 03266 #if 0 03267 ret_val = e1000e_get_cable_length(hw); 03268 #endif 03269 ret_val = -E1000_ERR_CONFIG; 03270 if (ret_val) 03271 goto out; 03272 #if 0 03273 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 03274 if (ret_val) 03275 goto out; 03276 03277 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 03278 ? e1000_1000t_rx_status_ok 03279 : e1000_1000t_rx_status_not_ok; 03280 03281 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 03282 ? e1000_1000t_rx_status_ok 03283 : e1000_1000t_rx_status_not_ok; 03284 #endif 03285 } else { 03286 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 03287 phy->local_rx = e1000_1000t_rx_status_undefined; 03288 phy->remote_rx = e1000_1000t_rx_status_undefined; 03289 } 03290 out: 03291 return ret_val; 03292 }
1.5.7.1