00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033 FILE_LICENCE ( GPL2_OR_LATER );
00034
00035 #include "e1000e.h"
00036
00037 static s32 e1000e_get_variants_82571(struct e1000_adapter *adapter)
00038 {
00039 struct e1000_hw *hw = &adapter->hw;
00040 static int global_quad_port_a;
00041 struct pci_device *pdev = adapter->pdev;
00042 u16 eeprom_data = 0;
00043 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
00044
00045
00046 switch (pdev->device) {
00047 case E1000_DEV_ID_82571EB_QUAD_COPPER:
00048 case E1000_DEV_ID_82571EB_QUAD_FIBER:
00049 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
00050 case E1000_DEV_ID_82571PT_QUAD_COPPER:
00051 adapter->flags |= FLAG_IS_QUAD_PORT;
00052
00053 if (global_quad_port_a == 0)
00054 adapter->flags |= FLAG_IS_QUAD_PORT_A;
00055
00056 global_quad_port_a++;
00057 if (global_quad_port_a == 4)
00058 global_quad_port_a = 0;
00059 break;
00060 default:
00061 break;
00062 }
00063
00064 switch (adapter->hw.mac.type) {
00065 case e1000_82571:
00066
00067 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
00068 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
00069 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
00070 (is_port_b))
00071 adapter->flags &= ~FLAG_HAS_WOL;
00072
00073 if (adapter->flags & FLAG_IS_QUAD_PORT &&
00074 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
00075 adapter->flags &= ~FLAG_HAS_WOL;
00076
00077 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
00078 adapter->flags &= ~FLAG_HAS_WOL;
00079 break;
00080
00081 case e1000_82573:
00082 if (pdev->device == E1000_DEV_ID_82573L) {
00083 if (e1000e_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1,
00084 &eeprom_data) < 0)
00085 break;
00086 if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) {
00087 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
00088 adapter->max_hw_frame_size = DEFAULT_JUMBO;
00089 }
00090 }
00091 break;
00092
00093 default:
00094 break;
00095 }
00096
00097 return 0;
00098 }
00099
00100 static struct e1000_info e1000_82571_info = {
00101 .mac = e1000_82571,
00102 .flags = FLAG_HAS_HW_VLAN_FILTER
00103 | FLAG_HAS_JUMBO_FRAMES
00104 | FLAG_HAS_WOL
00105 | FLAG_APME_IN_CTRL3
00106 | FLAG_RX_CSUM_ENABLED
00107 | FLAG_HAS_CTRLEXT_ON_LOAD
00108 | FLAG_HAS_SMART_POWER_DOWN
00109 | FLAG_RESET_OVERWRITES_LAA
00110 | FLAG_TARC_SPEED_MODE_BIT
00111 | FLAG_APME_CHECK_PORT_B,
00112 .pba = 38,
00113 .max_hw_frame_size = DEFAULT_JUMBO,
00114 .init_ops = e1000e_init_function_pointers_82571,
00115 .get_variants = e1000e_get_variants_82571,
00116 };
00117
00118 static struct e1000_info e1000_82572_info = {
00119 .mac = e1000_82572,
00120 .flags = FLAG_HAS_HW_VLAN_FILTER
00121 | FLAG_HAS_JUMBO_FRAMES
00122 | FLAG_HAS_WOL
00123 | FLAG_APME_IN_CTRL3
00124 | FLAG_RX_CSUM_ENABLED
00125 | FLAG_HAS_CTRLEXT_ON_LOAD
00126 | FLAG_TARC_SPEED_MODE_BIT,
00127 .pba = 38,
00128 .max_hw_frame_size = DEFAULT_JUMBO,
00129 .init_ops = e1000e_init_function_pointers_82571,
00130 .get_variants = e1000e_get_variants_82571,
00131 };
00132
00133 static struct e1000_info e1000_82573_info = {
00134 .mac = e1000_82573,
00135 .flags = FLAG_HAS_HW_VLAN_FILTER
00136 | FLAG_HAS_WOL
00137 | FLAG_APME_IN_CTRL3
00138 | FLAG_RX_CSUM_ENABLED
00139 | FLAG_HAS_SMART_POWER_DOWN
00140 | FLAG_HAS_AMT
00141 | FLAG_HAS_ERT
00142 | FLAG_HAS_SWSM_ON_LOAD,
00143 .pba = 20,
00144 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
00145 .init_ops = e1000e_init_function_pointers_82571,
00146 .get_variants = e1000e_get_variants_82571,
00147 };
00148
00149 static struct e1000_info e1000_82574_info = {
00150 .mac = e1000_82574,
00151 .flags = FLAG_HAS_HW_VLAN_FILTER
00152 #ifdef CONFIG_E1000E_MSIX
00153 | FLAG_HAS_MSIX
00154 #endif
00155 | FLAG_HAS_JUMBO_FRAMES
00156 | FLAG_HAS_WOL
00157 | FLAG_APME_IN_CTRL3
00158 | FLAG_RX_CSUM_ENABLED
00159 | FLAG_HAS_SMART_POWER_DOWN
00160 | FLAG_HAS_AMT
00161 | FLAG_HAS_CTRLEXT_ON_LOAD,
00162 .pba = 20,
00163 .max_hw_frame_size = DEFAULT_JUMBO,
00164 .init_ops = e1000e_init_function_pointers_82571,
00165 .get_variants = e1000e_get_variants_82571,
00166 };
00167
00168 static struct e1000_info e1000_82583_info = {
00169 .mac = e1000_82583,
00170 .flags = FLAG_HAS_HW_VLAN_FILTER
00171 | FLAG_HAS_WOL
00172 | FLAG_APME_IN_CTRL3
00173 | FLAG_RX_CSUM_ENABLED
00174 | FLAG_HAS_SMART_POWER_DOWN
00175 | FLAG_HAS_AMT
00176 | FLAG_HAS_CTRLEXT_ON_LOAD,
00177 .pba = 20,
00178 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
00179 .init_ops = e1000e_init_function_pointers_82571,
00180 .get_variants = e1000e_get_variants_82571,
00181 };
00182
00183 static struct e1000_info e1000_es2_info = {
00184 .mac = e1000_80003es2lan,
00185 .flags = FLAG_HAS_HW_VLAN_FILTER
00186 | FLAG_HAS_JUMBO_FRAMES
00187 | FLAG_HAS_WOL
00188 | FLAG_APME_IN_CTRL3
00189 | FLAG_RX_CSUM_ENABLED
00190 | FLAG_HAS_CTRLEXT_ON_LOAD
00191 | FLAG_RX_NEEDS_RESTART
00192 | FLAG_TARC_SET_BIT_ZERO
00193 | FLAG_APME_CHECK_PORT_B
00194 | FLAG_DISABLE_FC_PAUSE_TIME
00195 | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
00196 .pba = 38,
00197 .max_hw_frame_size = DEFAULT_JUMBO,
00198 .init_ops = e1000e_init_function_pointers_80003es2lan,
00199 .get_variants = NULL,
00200 };
00201
00202 static s32 e1000e_get_variants_ich8lan(struct e1000_adapter *adapter)
00203 {
00204 if (adapter->hw.phy.type == e1000_phy_ife) {
00205 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
00206 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
00207 }
00208
00209 if ((adapter->hw.mac.type == e1000_ich8lan) &&
00210 (adapter->hw.phy.type == e1000_phy_igp_3))
00211 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
00212
00213 return 0;
00214 }
00215
00216 static struct e1000_info e1000_ich8_info = {
00217 .mac = e1000_ich8lan,
00218 .flags = FLAG_HAS_WOL
00219 | FLAG_IS_ICH
00220 | FLAG_RX_CSUM_ENABLED
00221 | FLAG_HAS_CTRLEXT_ON_LOAD
00222 | FLAG_HAS_AMT
00223 | FLAG_HAS_FLASH
00224 | FLAG_APME_IN_WUC,
00225 .pba = 8,
00226 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
00227 .init_ops = e1000e_init_function_pointers_ich8lan,
00228 .get_variants = e1000e_get_variants_ich8lan,
00229 };
00230
00231 static struct e1000_info e1000_ich9_info = {
00232 .mac = e1000_ich9lan,
00233 .flags = FLAG_HAS_JUMBO_FRAMES
00234 | FLAG_IS_ICH
00235 | FLAG_HAS_WOL
00236 | FLAG_RX_CSUM_ENABLED
00237 | FLAG_HAS_CTRLEXT_ON_LOAD
00238 | FLAG_HAS_AMT
00239 | FLAG_HAS_ERT
00240 | FLAG_HAS_FLASH
00241 | FLAG_APME_IN_WUC,
00242 .pba = 10,
00243 .max_hw_frame_size = DEFAULT_JUMBO,
00244 .init_ops = e1000e_init_function_pointers_ich8lan,
00245 .get_variants = e1000e_get_variants_ich8lan,
00246 };
00247
00248 static struct e1000_info e1000_ich10_info = {
00249 .mac = e1000_ich10lan,
00250 .flags = FLAG_HAS_JUMBO_FRAMES
00251 | FLAG_IS_ICH
00252 | FLAG_HAS_WOL
00253 | FLAG_RX_CSUM_ENABLED
00254 | FLAG_HAS_CTRLEXT_ON_LOAD
00255 | FLAG_HAS_AMT
00256 | FLAG_HAS_ERT
00257 | FLAG_HAS_FLASH
00258 | FLAG_APME_IN_WUC,
00259 .pba = 10,
00260 .max_hw_frame_size = DEFAULT_JUMBO,
00261 .init_ops = e1000e_init_function_pointers_ich8lan,
00262 .get_variants = e1000e_get_variants_ich8lan,
00263 };
00264
00265 static struct e1000_info e1000_pch_info = {
00266 .mac = e1000_pchlan,
00267 .flags = FLAG_IS_ICH
00268 | FLAG_HAS_WOL
00269 | FLAG_RX_CSUM_ENABLED
00270 | FLAG_HAS_CTRLEXT_ON_LOAD
00271 | FLAG_HAS_AMT
00272 | FLAG_HAS_FLASH
00273 | FLAG_HAS_JUMBO_FRAMES
00274 | FLAG_DISABLE_FC_PAUSE_TIME
00275 | FLAG_APME_IN_WUC,
00276 .pba = 26,
00277 .max_hw_frame_size = 4096,
00278 .init_ops = e1000e_init_function_pointers_ich8lan,
00279 .get_variants = e1000e_get_variants_ich8lan,
00280 };
00281
00282 static const struct e1000_info *e1000_info_tbl[] = {
00283 [board_82571] = &e1000_82571_info,
00284 [board_82572] = &e1000_82572_info,
00285 [board_82573] = &e1000_82573_info,
00286 [board_82574] = &e1000_82574_info,
00287 [board_82583] = &e1000_82583_info,
00288 [board_80003es2lan] = &e1000_es2_info,
00289 [board_ich8lan] = &e1000_ich8_info,
00290 [board_ich9lan] = &e1000_ich9_info,
00291 [board_ich10lan] = &e1000_ich10_info,
00292 [board_pchlan] = &e1000_pch_info,
00293 };
00294
00295
00296
00297 s32 e1000e_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
00298 {
00299 u16 cap_offset;
00300
00301 cap_offset = pci_find_capability(hw->adapter->pdev, PCI_CAP_ID_EXP);
00302 if (!cap_offset)
00303 return -E1000_ERR_CONFIG;
00304
00305 pci_read_config_word(hw->adapter->pdev, cap_offset + reg, value);
00306
00307 return E1000_SUCCESS;
00308 }
00309
00310
00311
00312
00313 static void e1000e_irq_disable(struct e1000_adapter *adapter)
00314 {
00315 struct e1000_hw *hw = &adapter->hw;
00316
00317 ew32(IMC, ~0);
00318 e1e_flush();
00319 }
00320
00321
00322
00323
00324 static void e1000e_irq_enable(struct e1000_adapter *adapter)
00325 {
00326 struct e1000_hw *hw = &adapter->hw;
00327
00328 ew32(IMS, IMS_ENABLE_MASK);
00329 e1e_flush();
00330 }
00331
00332
00333
00334
00335
00336
00337
00338
00339
00340
00341 static void e1000e_get_hw_control(struct e1000_adapter *adapter)
00342 {
00343 struct e1000_hw *hw = &adapter->hw;
00344 u32 ctrl_ext;
00345 u32 swsm;
00346
00347
00348 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
00349 swsm = er32(SWSM);
00350 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
00351 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
00352 ctrl_ext = er32(CTRL_EXT);
00353 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
00354 }
00355 }
00356
00357
00358
00359
00360
00361
00362
00363
00364
00365 void e1000e_power_up_phy(struct e1000_adapter *adapter)
00366 {
00367 if (adapter->hw.phy.ops.power_up)
00368 adapter->hw.phy.ops.power_up(&adapter->hw);
00369
00370 adapter->hw.mac.ops.setup_link(&adapter->hw);
00371 }
00372
00373
00374
00375
00376
00377
00378
00379 void e1000e_power_down_phy(struct e1000_adapter *adapter)
00380 {
00381
00382 if (adapter->wol)
00383 return;
00384
00385 if (adapter->hw.phy.ops.power_down)
00386 adapter->hw.phy.ops.power_down(&adapter->hw);
00387 }
00388
00389
00390
00391
00392
00393
00394
00395
00396
00397 void e1000e_reset(struct e1000_adapter *adapter)
00398 {
00399 struct e1000_mac_info *mac = &adapter->hw.mac;
00400 struct e1000_fc_info *fc = &adapter->hw.fc;
00401 u32 pba = adapter->pba;
00402 struct e1000_hw *hw = &adapter->hw;
00403
00404
00405 ew32(PBA, pba);
00406
00407 hw->fc.requested_mode = e1000_fc_none;
00408 fc->current_mode = fc->requested_mode;
00409
00410
00411 mac->ops.reset_hw(hw);
00412
00413
00414
00415
00416
00417 if (adapter->flags & FLAG_HAS_AMT)
00418 e1000e_get_hw_control(adapter);
00419
00420 ew32(WUC, 0);
00421 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)
00422 e1e_wphy(&adapter->hw, BM_WUC, 0);
00423
00424 if (mac->ops.init_hw(hw))
00425 DBG("Hardware Error\n");
00426
00427
00428 if (hw->mac.type == e1000_pchlan)
00429 ew32(FCRTV_PCH, 0x1000);
00430
00431 e1000e_reset_adaptive(hw);
00432
00433 e1000e_get_phy_info(hw);
00434
00435 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
00436 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
00437 u16 phy_data = 0;
00438
00439
00440
00441
00442
00443 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
00444 phy_data &= ~IGP02E1000_PM_SPD;
00445 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
00446 }
00447 }
00448
00449 static int e1000e_sw_init(struct e1000_adapter *adapter)
00450 {
00451 s32 rc;
00452
00453
00454 adapter->ei->init_ops(&adapter->hw);
00455
00456 rc = adapter->hw.mac.ops.init_params(&adapter->hw);
00457 if (rc)
00458 return rc;
00459
00460 rc = adapter->hw.nvm.ops.init_params(&adapter->hw);
00461 if (rc)
00462 return rc;
00463
00464 rc = adapter->hw.phy.ops.init_params(&adapter->hw);
00465 if (rc)
00466 return rc;
00467
00468
00469 e1000e_irq_disable(adapter);
00470
00471 return E1000_SUCCESS;
00472 }
00473
00474
00475
00476
00477
00478
00479
00480
00481
00482
00483 static int e1000e_setup_tx_resources ( struct e1000_adapter *adapter )
00484 {
00485 DBGP ( "e1000_setup_tx_resources\n" );
00486
00487
00488
00489
00490
00491
00492
00493
00494
00495
00496
00497 adapter->tx_base =
00498 malloc_dma ( adapter->tx_ring_size, adapter->tx_ring_size );
00499
00500 if ( ! adapter->tx_base ) {
00501 return -ENOMEM;
00502 }
00503
00504 memset ( adapter->tx_base, 0, adapter->tx_ring_size );
00505
00506 DBG ( "adapter->tx_base = %#08lx\n", virt_to_bus ( adapter->tx_base ) );
00507
00508 return 0;
00509 }
00510
00511
00512
00513
00514
00515
00516 static void e1000e_process_tx_packets ( struct net_device *netdev )
00517 {
00518 struct e1000_adapter *adapter = netdev_priv ( netdev );
00519 uint32_t i;
00520 uint32_t tx_status;
00521 struct e1000_tx_desc *tx_curr_desc;
00522
00523
00524
00525 DBG ( "process_tx_packets: tx_head = %d, tx_tail = %d\n", adapter->tx_head,
00526 adapter->tx_tail );
00527
00528 while ( ( i = adapter->tx_head ) != adapter->tx_tail ) {
00529
00530 tx_curr_desc = ( void * ) ( adapter->tx_base ) +
00531 ( i * sizeof ( *adapter->tx_base ) );
00532
00533 tx_status = tx_curr_desc->upper.data;
00534
00535 DBG ( " tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) );
00536 DBG ( " tx_status = %#08x\n", tx_status );
00537
00538
00539 if ( ! ( tx_status & E1000_TXD_STAT_DD ) )
00540 break;
00541
00542 DBG ( "Sent packet. tx_head: %d tx_tail: %d tx_status: %#08x\n",
00543 adapter->tx_head, adapter->tx_tail, tx_status );
00544
00545 if ( tx_status & ( E1000_TXD_STAT_EC | E1000_TXD_STAT_LC |
00546 E1000_TXD_STAT_TU ) ) {
00547 netdev_tx_complete_err ( netdev, adapter->tx_iobuf[i], -EINVAL );
00548 DBG ( "Error transmitting packet, tx_status: %#08x\n",
00549 tx_status );
00550 } else {
00551 netdev_tx_complete ( netdev, adapter->tx_iobuf[i] );
00552 DBG ( "Success transmitting packet, tx_status: %#08x\n",
00553 tx_status );
00554 }
00555
00556
00557
00558 adapter->tx_fill_ctr--;
00559 memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) );
00560
00561 adapter->tx_head = ( adapter->tx_head + 1 ) % NUM_TX_DESC;
00562 }
00563 }
00564
00565 static void e1000e_free_tx_resources ( struct e1000_adapter *adapter )
00566 {
00567 DBGP ( "e1000_free_tx_resources\n" );
00568
00569 free_dma ( adapter->tx_base, adapter->tx_ring_size );
00570 }
00571
00572
00573
00574
00575
00576
00577
00578 static void e1000e_configure_tx ( struct e1000_adapter *adapter )
00579 {
00580 struct e1000_hw *hw = &adapter->hw;
00581 u32 tctl, tipg, tarc;
00582 u32 ipgr1, ipgr2;
00583
00584 DBGP ( "e1000_configure_tx\n" );
00585
00586
00587 tctl = E1000_READ_REG ( hw, E1000_TCTL );
00588 E1000_WRITE_REG ( hw, E1000_TCTL, tctl & ~E1000_TCTL_EN );
00589 e1e_flush();
00590 mdelay(10);
00591
00592 E1000_WRITE_REG ( hw, E1000_TDBAH(0), 0 );
00593 E1000_WRITE_REG ( hw, E1000_TDBAL(0), virt_to_bus ( adapter->tx_base ) );
00594 E1000_WRITE_REG ( hw, E1000_TDLEN(0), adapter->tx_ring_size );
00595
00596 DBG ( "E1000_TDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_TDBAL(0) ) );
00597 DBG ( "E1000_TDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_TDLEN(0) ) );
00598
00599
00600 E1000_WRITE_REG ( hw, E1000_TDH(0), 0 );
00601 E1000_WRITE_REG ( hw, E1000_TDT(0), 0 );
00602
00603 adapter->tx_head = 0;
00604 adapter->tx_tail = 0;
00605 adapter->tx_fill_ctr = 0;
00606
00607
00608 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
00609 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
00610 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
00611
00612 if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN)
00613 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
00614
00615 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
00616 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
00617 ew32(TIPG, tipg);
00618
00619
00620 tctl = er32(TCTL);
00621 tctl &= ~E1000_TCTL_CT;
00622 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
00623 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
00624
00625 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
00626 tarc = er32(TARC(0));
00627
00628
00629
00630
00631 #define SPEED_MODE_BIT (1 << 21)
00632 tarc |= SPEED_MODE_BIT;
00633 ew32(TARC(0), tarc);
00634 }
00635
00636
00637 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
00638 tarc = er32(TARC(0));
00639 tarc |= 1;
00640 ew32(TARC(0), tarc);
00641 tarc = er32(TARC(1));
00642 tarc |= 1;
00643 ew32(TARC(1), tarc);
00644 }
00645
00646
00647 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
00648
00649
00650 adapter->txd_cmd |= E1000_TXD_CMD_RS;
00651
00652
00653
00654
00655
00656 tctl |= E1000_TCTL_EN;
00657 ew32(TCTL, tctl);
00658 e1e_flush();
00659
00660 e1000e_config_collision_dist(hw);
00661 }
00662
00663
00664
00665 static void e1000e_free_rx_resources ( struct e1000_adapter *adapter )
00666 {
00667 int i;
00668
00669 DBGP ( "e1000_free_rx_resources\n" );
00670
00671 free_dma ( adapter->rx_base, adapter->rx_ring_size );
00672
00673 for ( i = 0; i < NUM_RX_DESC; i++ ) {
00674 free_iob ( adapter->rx_iobuf[i] );
00675 }
00676 }
00677
00678
00679
00680
00681
00682
00683
00684
00685 static int e1000e_refill_rx_ring ( struct e1000_adapter *adapter )
00686 {
00687 int i, rx_curr;
00688 int rc = 0;
00689 struct e1000_rx_desc *rx_curr_desc;
00690 struct e1000_hw *hw = &adapter->hw;
00691 struct io_buffer *iob;
00692
00693 DBGP ("e1000_refill_rx_ring\n");
00694
00695 for ( i = 0; i < NUM_RX_DESC; i++ ) {
00696 rx_curr = ( ( adapter->rx_curr + i ) % NUM_RX_DESC );
00697 rx_curr_desc = adapter->rx_base + rx_curr;
00698
00699 if ( rx_curr_desc->status & E1000_RXD_STAT_DD )
00700 continue;
00701
00702 if ( adapter->rx_iobuf[rx_curr] != NULL )
00703 continue;
00704
00705 DBG2 ( "Refilling rx desc %d\n", rx_curr );
00706
00707 iob = alloc_iob ( MAXIMUM_ETHERNET_VLAN_SIZE );
00708 adapter->rx_iobuf[rx_curr] = iob;
00709
00710 if ( ! iob ) {
00711 DBG ( "alloc_iob failed\n" );
00712 rc = -ENOMEM;
00713 break;
00714 } else {
00715 rx_curr_desc->buffer_addr = virt_to_bus ( iob->data );
00716
00717 E1000_WRITE_REG ( hw, E1000_RDT(0), rx_curr );
00718 }
00719 }
00720 return rc;
00721 }
00722
00723
00724
00725
00726
00727
00728
00729
00730 static int e1000e_setup_rx_resources ( struct e1000_adapter *adapter )
00731 {
00732 int i, rc = 0;
00733
00734 DBGP ( "e1000_setup_rx_resources\n" );
00735
00736
00737
00738
00739
00740 adapter->rx_base =
00741 malloc_dma ( adapter->rx_ring_size, adapter->rx_ring_size );
00742
00743 if ( ! adapter->rx_base ) {
00744 return -ENOMEM;
00745 }
00746 memset ( adapter->rx_base, 0, adapter->rx_ring_size );
00747
00748 for ( i = 0; i < NUM_RX_DESC; i++ ) {
00749
00750 adapter->rx_iobuf[i] = NULL;
00751 }
00752
00753
00754 rc = e1000e_refill_rx_ring ( adapter );
00755 if ( rc < 0 )
00756 e1000e_free_rx_resources ( adapter );
00757
00758 return rc;
00759 }
00760
00761
00762
00763
00764
00765
00766
00767 static void e1000e_configure_rx ( struct e1000_adapter *adapter )
00768 {
00769 struct e1000_hw *hw = &adapter->hw;
00770 uint32_t rctl;
00771
00772 DBGP ( "e1000_configure_rx\n" );
00773
00774
00775 rctl = E1000_READ_REG ( hw, E1000_RCTL );
00776 E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );
00777 e1e_flush();
00778 mdelay(10);
00779
00780 adapter->rx_curr = 0;
00781
00782
00783
00784
00785 E1000_WRITE_REG ( hw, E1000_RDBAL(0), virt_to_bus ( adapter->rx_base ) );
00786 E1000_WRITE_REG ( hw, E1000_RDBAH(0), 0 );
00787 E1000_WRITE_REG ( hw, E1000_RDLEN(0), adapter->rx_ring_size );
00788
00789 E1000_WRITE_REG ( hw, E1000_RDH(0), 0 );
00790 E1000_WRITE_REG ( hw, E1000_RDT(0), NUM_RX_DESC - 1 );
00791
00792
00793 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
00794 E1000_RCTL_MPE;
00795 E1000_WRITE_REG ( hw, E1000_RCTL, rctl );
00796 e1e_flush();
00797
00798 DBG ( "E1000_RDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_RDBAL(0) ) );
00799 DBG ( "E1000_RDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_RDLEN(0) ) );
00800 DBG ( "E1000_RCTL: %#08x\n", E1000_READ_REG ( hw, E1000_RCTL ) );
00801 }
00802
00803
00804
00805
00806
00807
00808 static void e1000e_process_rx_packets ( struct net_device *netdev )
00809 {
00810 struct e1000_adapter *adapter = netdev_priv ( netdev );
00811 uint32_t i;
00812 uint32_t rx_status;
00813 uint32_t rx_len;
00814 uint32_t rx_err;
00815 struct e1000_rx_desc *rx_curr_desc;
00816
00817
00818
00819 while ( 1 ) {
00820
00821 i = adapter->rx_curr;
00822
00823 rx_curr_desc = ( void * ) ( adapter->rx_base ) +
00824 ( i * sizeof ( *adapter->rx_base ) );
00825 rx_status = rx_curr_desc->status;
00826
00827 DBG2 ( "Before DD Check RX_status: %#08x\n", rx_status );
00828
00829 if ( ! ( rx_status & E1000_RXD_STAT_DD ) )
00830 break;
00831
00832 if ( adapter->rx_iobuf[i] == NULL )
00833 break;
00834
00835 DBG ( "E1000_RCTL = %#08x\n", E1000_READ_REG ( &adapter->hw, E1000_RCTL ) );
00836
00837 rx_len = rx_curr_desc->length;
00838
00839 DBG ( "Received packet, rx_curr: %d rx_status: %#08x rx_len: %d\n",
00840 i, rx_status, rx_len );
00841
00842 rx_err = rx_curr_desc->errors;
00843
00844 iob_put ( adapter->rx_iobuf[i], rx_len );
00845
00846 if ( rx_err & E1000_RXD_ERR_FRAME_ERR_MASK ) {
00847
00848 netdev_rx_err ( netdev, adapter->rx_iobuf[i], -EINVAL );
00849 DBG ( "e1000_poll: Corrupted packet received!"
00850 " rx_err: %#08x\n", rx_err );
00851 } else {
00852
00853 netdev_rx ( netdev, adapter->rx_iobuf[i] );
00854 }
00855 adapter->rx_iobuf[i] = NULL;
00856
00857 memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) );
00858
00859 adapter->rx_curr = ( adapter->rx_curr + 1 ) % NUM_RX_DESC;
00860 }
00861 }
00862
00863
00864
00865
00866
00867
00868
00869
00870
00871 static void e1000e_close ( struct net_device *netdev )
00872 {
00873 struct e1000_adapter *adapter = netdev_priv ( netdev );
00874 struct e1000_hw *hw = &adapter->hw;
00875 uint32_t rctl;
00876 uint32_t icr;
00877
00878 DBGP ( "e1000_close\n" );
00879
00880
00881 icr = E1000_READ_REG ( hw, E1000_ICR );
00882
00883 e1000e_irq_disable ( adapter );
00884
00885
00886 rctl = E1000_READ_REG ( hw, E1000_RCTL );
00887 E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );
00888 e1e_flush();
00889
00890 e1000e_reset ( adapter );
00891
00892 e1000e_free_tx_resources ( adapter );
00893 e1000e_free_rx_resources ( adapter );
00894 }
00895
00896
00897
00898
00899
00900
00901
00902
00903
00904 static int e1000e_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
00905 {
00906 struct e1000_adapter *adapter = netdev_priv( netdev );
00907 struct e1000_hw *hw = &adapter->hw;
00908 uint32_t tx_curr = adapter->tx_tail;
00909 struct e1000_tx_desc *tx_curr_desc;
00910
00911 DBGP ("e1000_transmit\n");
00912
00913 if ( adapter->tx_fill_ctr == NUM_TX_DESC ) {
00914 DBG ("TX overflow\n");
00915 return -ENOBUFS;
00916 }
00917
00918
00919
00920
00921 adapter->tx_iobuf[tx_curr] = iobuf;
00922
00923 tx_curr_desc = ( void * ) ( adapter->tx_base ) +
00924 ( tx_curr * sizeof ( *adapter->tx_base ) );
00925
00926 DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) );
00927 DBG ( "tx_curr_desc + 16 = %#08lx\n", virt_to_bus ( tx_curr_desc ) + 16 );
00928 DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) );
00929
00930
00931
00932 tx_curr_desc->buffer_addr = virt_to_bus ( iobuf->data );
00933 tx_curr_desc->upper.data = 0;
00934 tx_curr_desc->lower.data = adapter->txd_cmd | iob_len ( iobuf );
00935
00936 DBG ( "TX fill: %d tx_curr: %d addr: %#08lx len: %zd\n", adapter->tx_fill_ctr,
00937 tx_curr, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) );
00938
00939
00940 adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC;
00941 adapter->tx_fill_ctr++;
00942
00943
00944
00945 E1000_WRITE_REG ( hw, E1000_TDT(0), adapter->tx_tail );
00946 e1e_flush();
00947
00948 return 0;
00949 }
00950
00951
00952
00953
00954
00955
00956 static void e1000e_poll ( struct net_device *netdev )
00957 {
00958 struct e1000_adapter *adapter = netdev_priv( netdev );
00959 struct e1000_hw *hw = &adapter->hw;
00960
00961 uint32_t icr;
00962
00963 DBGP ( "e1000_poll\n" );
00964
00965
00966 icr = E1000_READ_REG ( hw, E1000_ICR );
00967 if ( ! icr )
00968 return;
00969
00970 DBG ( "e1000_poll: intr_status = %#08x\n", icr );
00971
00972 e1000e_process_tx_packets ( netdev );
00973
00974 e1000e_process_rx_packets ( netdev );
00975
00976 e1000e_refill_rx_ring(adapter);
00977 }
00978
00979
00980
00981
00982
00983
00984
00985 static void e1000e_irq ( struct net_device *netdev, int enable )
00986 {
00987 struct e1000_adapter *adapter = netdev_priv ( netdev );
00988
00989 DBGP ( "e1000_irq\n" );
00990
00991 if ( enable ) {
00992 e1000e_irq_enable ( adapter );
00993 } else {
00994 e1000e_irq_disable ( adapter );
00995 }
00996 }
00997
00998 static struct net_device_operations e1000e_operations;
00999
01000
01001
01002
01003
01004
01005
01006
01007
01008 int e1000e_probe ( struct pci_device *pdev,
01009 const struct pci_device_id *ent)
01010 {
01011 int i, err;
01012 struct net_device *netdev;
01013 struct e1000_adapter *adapter;
01014 unsigned long mmio_start, mmio_len;
01015 unsigned long flash_start, flash_len;
01016 struct e1000_hw *hw;
01017 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
01018
01019 DBGP ( "e1000_probe\n" );
01020
01021 err = -ENOMEM;
01022
01023
01024
01025 netdev = alloc_etherdev ( sizeof ( struct e1000_adapter ) );
01026 if ( ! netdev ) {
01027 DBG ( "err_alloc_etherdev\n" );
01028 goto err_alloc_etherdev;
01029 }
01030
01031
01032
01033 netdev_init ( netdev, &e1000e_operations );
01034
01035
01036 pci_set_drvdata ( pdev, netdev );
01037 netdev->dev = &pdev->dev;
01038
01039
01040 adapter = netdev_priv ( netdev );
01041 memset ( adapter, 0, ( sizeof ( *adapter ) ) );
01042
01043 adapter->pdev = pdev;
01044
01045 adapter->ioaddr = pdev->ioaddr;
01046 adapter->hw.io_base = pdev->ioaddr;
01047
01048 hw = &adapter->hw;
01049 hw->device_id = pdev->device;
01050
01051 adapter->irqno = pdev->irq;
01052 adapter->netdev = netdev;
01053 adapter->hw.back = adapter;
01054
01055 adapter->ei = ei;
01056 adapter->pba = ei->pba;
01057 adapter->flags = ei->flags;
01058 adapter->flags2 = ei->flags2;
01059
01060 adapter->hw.adapter = adapter;
01061 adapter->hw.mac.type = ei->mac;
01062 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
01063
01064 adapter->tx_ring_size = sizeof ( *adapter->tx_base ) * NUM_TX_DESC;
01065 adapter->rx_ring_size = sizeof ( *adapter->rx_base ) * NUM_RX_DESC;
01066
01067
01068 adjust_pci_device ( pdev );
01069
01070 err = -EIO;
01071
01072 mmio_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_0 );
01073 mmio_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_0 );
01074
01075 DBG ( "mmio_start: %#08lx\n", mmio_start );
01076 DBG ( "mmio_len: %#08lx\n", mmio_len );
01077
01078 adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len );
01079 DBG ( "adapter->hw.hw_addr: %p\n", adapter->hw.hw_addr );
01080
01081 if ( ! adapter->hw.hw_addr ) {
01082 DBG ( "err_ioremap\n" );
01083 goto err_ioremap;
01084 }
01085
01086
01087 if ( ( adapter->flags & FLAG_HAS_FLASH) && ( pdev->ioaddr ) ) {
01088 flash_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_1 );
01089 flash_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_1 );
01090 adapter->hw.flash_address = ioremap ( flash_start, flash_len );
01091 if ( ! adapter->hw.flash_address ) {
01092 DBG ( "err_flashmap\n" );
01093 goto err_flashmap;
01094 }
01095 }
01096
01097
01098 err = e1000e_sw_init ( adapter );
01099 if (err) {
01100 DBG ( "err_sw_init\n" );
01101 goto err_sw_init;
01102 }
01103
01104 if (ei->get_variants) {
01105 err = ei->get_variants(adapter);
01106 if (err) {
01107 DBG ( "err_hw_initr\n" );
01108 goto err_hw_init;
01109 }
01110 }
01111
01112
01113 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
01114 adapter->hw.phy.mdix = AUTO_ALL_MODES;
01115 adapter->hw.phy.disable_polarity_correction = 0;
01116 adapter->hw.phy.ms_type = e1000_ms_hw_default;
01117 }
01118
01119 DBG ( "adapter->hw.mac.type: %#08x\n", adapter->hw.mac.type );
01120
01121
01122 adapter->hw.mac.autoneg = 1;
01123 adapter->fc_autoneg = 1;
01124 adapter->hw.phy.autoneg_wait_to_complete = true;
01125 adapter->hw.mac.adaptive_ifs = true;
01126 adapter->hw.fc.requested_mode = e1000_fc_default;
01127 adapter->hw.fc.current_mode = e1000_fc_default;
01128
01129
01130
01131
01132
01133 adapter->hw.mac.ops.reset_hw(&adapter->hw);
01134
01135
01136
01137
01138
01139 for (i = 0;; i++) {
01140 if (e1000e_validate_nvm_checksum(&adapter->hw) >= 0)
01141 break;
01142 if (i == 2) {
01143 DBG("The NVM Checksum Is Not Valid\n");
01144 err = -EIO;
01145 goto err_eeprom;
01146 }
01147 }
01148
01149
01150 if ( e1000e_read_mac_addr ( &adapter->hw ) )
01151 DBG ( "EEPROM Read Error\n" );
01152
01153 memcpy ( netdev->hw_addr, adapter->hw.mac.perm_addr, ETH_ALEN );
01154
01155
01156 e1000e_reset ( adapter );
01157
01158
01159 netdev_link_up ( netdev );
01160
01161 if ( ( err = register_netdev ( netdev ) ) != 0) {
01162 DBG ( "err_register\n" );
01163 goto err_register;
01164 }
01165
01166 for (i = 0; i < 6; i++)
01167 DBG ("%02x%s", netdev->ll_addr[i], i == 5 ? "\n" : ":");
01168
01169 DBG ( "e1000e_probe succeeded!\n" );
01170
01171
01172 return 0;
01173
01174
01175 err_register:
01176 err_hw_init:
01177 err_eeprom:
01178 err_flashmap:
01179 if (!e1000e_check_reset_block(&adapter->hw))
01180 e1000e_phy_hw_reset(&adapter->hw);
01181 if (adapter->hw.flash_address)
01182 iounmap(adapter->hw.flash_address);
01183 err_sw_init:
01184 iounmap ( adapter->hw.hw_addr );
01185 err_ioremap:
01186 netdev_put ( netdev );
01187 err_alloc_etherdev:
01188 return err;
01189 }
01190
01191
01192
01193
01194
01195
01196
01197 void e1000e_remove ( struct pci_device *pdev )
01198 {
01199 struct net_device *netdev = pci_get_drvdata ( pdev );
01200 struct e1000_adapter *adapter = netdev_priv ( netdev );
01201
01202 DBGP ( "e1000e_remove\n" );
01203
01204 if ( adapter->hw.flash_address )
01205 iounmap ( adapter->hw.flash_address );
01206 if ( adapter->hw.hw_addr )
01207 iounmap ( adapter->hw.hw_addr );
01208
01209 unregister_netdev ( netdev );
01210 e1000e_reset ( adapter );
01211 netdev_nullify ( netdev );
01212 netdev_put ( netdev );
01213 }
01214
01215
01216
01217
01218
01219
01220
01221
01222 static int e1000e_open ( struct net_device *netdev )
01223 {
01224 struct e1000_adapter *adapter = netdev_priv(netdev);
01225 int err;
01226
01227 DBGP ( "e1000e_open\n" );
01228
01229
01230 err = e1000e_setup_tx_resources ( adapter );
01231 if ( err ) {
01232 DBG ( "Error setting up TX resources!\n" );
01233 goto err_setup_tx;
01234 }
01235
01236
01237 err = e1000e_setup_rx_resources ( adapter );
01238 if ( err ) {
01239 DBG ( "Error setting up RX resources!\n" );
01240 goto err_setup_rx;
01241 }
01242
01243 e1000e_configure_tx ( adapter );
01244
01245 e1000e_configure_rx ( adapter );
01246
01247 DBG ( "E1000_RXDCTL(0): %#08x\n", E1000_READ_REG ( &adapter->hw, E1000_RXDCTL(0) ) );
01248
01249 return 0;
01250
01251 err_setup_rx:
01252 DBG ( "err_setup_rx\n" );
01253 e1000e_free_tx_resources ( adapter );
01254 err_setup_tx:
01255 DBG ( "err_setup_tx\n" );
01256 e1000e_reset ( adapter );
01257
01258 return err;
01259 }
01260
01261
01262 static struct net_device_operations e1000e_operations = {
01263 .open = e1000e_open,
01264 .close = e1000e_close,
01265 .transmit = e1000e_transmit,
01266 .poll = e1000e_poll,
01267 .irq = e1000e_irq,
01268 };