Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| void | e1000e_init_mac_ops_generic (struct e1000_hw *hw) |
| e1000e_init_mac_ops_generic - Initialize MAC function pointers : pointer to the HW structure | |
| s32 | e1000e_blink_led (struct e1000_hw *hw) |
| s32 | e1000e_check_for_copper_link (struct e1000_hw *hw) |
| e1000e_check_for_copper_link - Check for link (Copper) : pointer to the HW structure | |
| s32 | e1000e_check_for_fiber_link (struct e1000_hw *hw) |
| e1000e_check_for_fiber_link - Check for link (Fiber) : pointer to the HW structure | |
| s32 | e1000e_check_for_serdes_link (struct e1000_hw *hw) |
| e1000e_check_for_serdes_link - Check for link (Serdes) : pointer to the HW structure | |
| s32 | e1000e_cleanup_led_generic (struct e1000_hw *hw) |
| s32 | e1000e_config_fc_after_link_up (struct e1000_hw *hw) |
| e1000e_config_fc_after_link_up - Configures flow control after link : pointer to the HW structure | |
| s32 | e1000e_disable_pcie_master (struct e1000_hw *hw) |
| e1000e_disable_pcie_master - Disables PCI-express master access : pointer to the HW structure | |
| s32 | e1000e_force_mac_fc (struct e1000_hw *hw) |
| e1000e_force_mac_fc - Force the MAC's flow control settings : pointer to the HW structure | |
| s32 | e1000e_get_auto_rd_done (struct e1000_hw *hw) |
| e1000e_get_auto_rd_done - Check for auto read completion : pointer to the HW structure | |
| s32 | e1000e_get_bus_info_pcie (struct e1000_hw *hw) |
| e1000e_get_bus_info_pcie - Get PCIe bus information : pointer to the HW structure | |
| void | e1000e_set_lan_id_single_port (struct e1000_hw *hw) |
| e1000e_set_lan_id_single_port - Set LAN id for a single port device : pointer to the HW structure | |
| s32 | e1000e_get_hw_semaphore (struct e1000_hw *hw) |
| e1000e_get_hw_semaphore - Acquire hardware semaphore : pointer to the HW structure | |
| s32 | e1000e_get_speed_and_duplex_copper (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex | |
| s32 | e1000e_get_speed_and_duplex_fiber_serdes (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| s32 | e1000e_id_led_init (struct e1000_hw *hw) |
| s32 | e1000e_led_on_generic (struct e1000_hw *hw) |
| s32 | e1000e_led_off_generic (struct e1000_hw *hw) |
| void | e1000e_update_mc_addr_list_generic (struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count) |
| e1000e_update_mc_addr_list_generic - Update Multicast addresses : pointer to the HW structure : array of multicast addresses to program : number of multicast addresses to program | |
| s32 | e1000e_set_fc_watermarks (struct e1000_hw *hw) |
| e1000e_set_fc_watermarks - Set flow control high/low watermarks : pointer to the HW structure | |
| s32 | e1000e_setup_fiber_serdes_link (struct e1000_hw *hw) |
| e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes : pointer to the HW structure | |
| s32 | e1000e_setup_led_generic (struct e1000_hw *hw) |
| s32 | e1000e_setup_link (struct e1000_hw *hw) |
| e1000e_setup_link - Setup flow control and link settings : pointer to the HW structure | |
| void | e1000e_clear_hw_cntrs_base (struct e1000_hw *hw) |
| void | e1000e_clear_vfta_generic (struct e1000_hw *hw) |
| e1000e_clear_vfta_generic - Clear VLAN filter table : pointer to the HW structure | |
| void | e1000e_config_collision_dist (struct e1000_hw *hw) |
| e1000e_config_collision_dist - Configure collision distance : pointer to the HW structure | |
| void | e1000e_init_rx_addrs (struct e1000_hw *hw, u16 rar_count) |
| e1000e_init_rx_addrs - Initialize receive address's : pointer to the HW structure : receive address registers | |
| void | e1000e_mta_set_generic (struct e1000_hw *hw, u32 hash_value) |
| e1000e_mta_set_generic - Set multicast filter table address : pointer to the HW structure : determines the MTA register and bit to set | |
| void | e1000e_pcix_mmrbc_workaround_generic (struct e1000_hw *hw) |
| void | e1000e_put_hw_semaphore (struct e1000_hw *hw) |
| e1000e_put_hw_semaphore - Release hardware semaphore : pointer to the HW structure | |
| void | e1000e_rar_set (struct e1000_hw *hw, u8 *addr, u32 index) |
| e1000e_rar_set - Set receive address register : pointer to the HW structure : pointer to the receive address : receive address array register | |
| s32 | e1000e_check_alt_mac_addr_generic (struct e1000_hw *hw) |
| e1000e_check_alt_mac_addr_generic - Check for alternate MAC addr : pointer to the HW structure | |
| void | e1000e_reset_adaptive (struct e1000_hw *hw) |
| e1000e_reset_adaptive - Reset Adaptive Interframe Spacing : pointer to the HW structure | |
| void | e1000e_set_pcie_no_snoop (struct e1000_hw *hw, u32 no_snoop) |
| e1000e_set_pcie_no_snoop - Set PCI-express capabilities : pointer to the HW structure : bitmap of snoop events | |
| void | e1000e_update_adaptive (struct e1000_hw *hw) |
| e1000e_update_adaptive - Update Adaptive Interframe Spacing : pointer to the HW structure | |
| void | e1000e_write_vfta_generic (struct e1000_hw *hw, u32 offset, u32 value) |
| e1000e_write_vfta_generic - Write value to VLAN filter table : pointer to the HW structure : register offset in VLAN filter table : register value written to VLAN filter table | |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
| void e1000e_init_mac_ops_generic | ( | struct e1000_hw * | hw | ) |
e1000e_init_mac_ops_generic - Initialize MAC function pointers : pointer to the HW structure
Setups up the function pointers to no-op functions
Definition at line 46 of file e1000e_mac.c.
References e1000_mac_operations::config_collision_dist, e1000e_config_collision_dist(), e1000e_mng_enable_host_if_generic(), e1000e_mng_host_if_write_generic(), e1000e_mng_write_cmd_header_generic(), e1000e_rar_set(), e1000e_read_mac_addr_generic(), e1000e_set_lan_id_multi_port_pcie(), e1000e_validate_mdi_setting_generic(), e1000e_wait_autoneg(), e1000_hw::mac, e1000_mac_operations::mng_enable_host_if, e1000_mac_operations::mng_host_if_write, e1000_mac_operations::mng_write_cmd_header, e1000_mac_info::ops, e1000_mac_operations::rar_set, e1000_mac_operations::read_mac_addr, e1000_mac_operations::set_lan_id, e1000_mac_operations::validate_mdi_setting, and e1000_mac_operations::wait_autoneg.
Referenced by e1000e_init_function_pointers_80003es2lan(), e1000e_init_function_pointers_82571(), and e1000e_init_function_pointers_ich8lan().
00047 { 00048 struct e1000_mac_info *mac = &hw->mac; 00049 /* General Setup */ 00050 mac->ops.set_lan_id = e1000e_set_lan_id_multi_port_pcie; 00051 mac->ops.read_mac_addr = e1000e_read_mac_addr_generic; 00052 mac->ops.config_collision_dist = e1000e_config_collision_dist; 00053 /* LINK */ 00054 mac->ops.wait_autoneg = e1000e_wait_autoneg; 00055 /* Management */ 00056 #if 0 00057 mac->ops.mng_host_if_write = e1000e_mng_host_if_write_generic; 00058 mac->ops.mng_write_cmd_header = e1000e_mng_write_cmd_header_generic; 00059 mac->ops.mng_enable_host_if = e1000e_mng_enable_host_if_generic; 00060 #endif 00061 /* VLAN, MC, etc. */ 00062 mac->ops.rar_set = e1000e_rar_set; 00063 mac->ops.validate_mdi_setting = e1000e_validate_mdi_setting_generic; 00064 }
e1000e_check_for_copper_link - Check for link (Copper) : pointer to the HW structure
Checks to see of the link status of the hardware has changed. If a change in link status has been detected, then we read the PHY registers to get the current speed/duplex if link exists.
Definition at line 489 of file e1000e_mac.c.
References e1000_mac_info::autoneg, E1000_ERR_CONFIG, E1000_SUCCESS, e1000e_check_downshift(), e1000e_config_collision_dist(), e1000e_config_fc_after_link_up(), e1000e_phy_has_link_generic(), e_dbg, e1000_mac_info::get_link_status, and e1000_hw::mac.
00490 { 00491 struct e1000_mac_info *mac = &hw->mac; 00492 s32 ret_val; 00493 bool link; 00494 00495 /* 00496 * We only want to go out to the PHY registers to see if Auto-Neg 00497 * has completed and/or if our link status has changed. The 00498 * get_link_status flag is set upon receiving a Link Status 00499 * Change or Rx Sequence Error interrupt. 00500 */ 00501 if (!mac->get_link_status) { 00502 ret_val = E1000_SUCCESS; 00503 goto out; 00504 } 00505 00506 /* 00507 * First we want to see if the MII Status Register reports 00508 * link. If so, then we want to get the current speed/duplex 00509 * of the PHY. 00510 */ 00511 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 00512 if (ret_val) 00513 goto out; 00514 00515 if (!link) 00516 goto out; /* No link detected */ 00517 00518 mac->get_link_status = false; 00519 00520 /* 00521 * Check if there was DownShift, must be checked 00522 * immediately after link-up 00523 */ 00524 e1000e_check_downshift(hw); 00525 00526 /* 00527 * If we are forcing speed/duplex, then we simply return since 00528 * we have already determined whether we have link or not. 00529 */ 00530 if (!mac->autoneg) { 00531 ret_val = -E1000_ERR_CONFIG; 00532 goto out; 00533 } 00534 00535 /* 00536 * Auto-Neg is enabled. Auto Speed Detection takes care 00537 * of MAC speed/duplex configuration. So we only need to 00538 * configure Collision Distance in the MAC. 00539 */ 00540 e1000e_config_collision_dist(hw); 00541 00542 /* 00543 * Configure Flow Control now that Auto-Neg has completed. 00544 * First, we need to restore the desired flow control 00545 * settings because we may have had to re-autoneg with a 00546 * different link partner. 00547 */ 00548 ret_val = e1000e_config_fc_after_link_up(hw); 00549 if (ret_val) 00550 e_dbg("Error configuring flow control\n"); 00551 00552 out: 00553 return ret_val; 00554 }
e1000e_check_for_fiber_link - Check for link (Fiber) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 563 of file e1000e_mac.c.
References e1000_mac_info::autoneg_failed, E1000_CTRL_FD, E1000_CTRL_SLU, E1000_CTRL_SWDPIN1, E1000_RXCW_C, E1000_STATUS_LU, E1000_SUCCESS, E1000_TXCW_ANE, e1000e_config_fc_after_link_up(), e_dbg, er32, ew32, e1000_hw::mac, e1000_mac_info::serdes_has_link, e1000_mac_info::txcw, and u32.
00564 { 00565 struct e1000_mac_info *mac = &hw->mac; 00566 u32 rxcw; 00567 u32 ctrl; 00568 u32 status; 00569 s32 ret_val = E1000_SUCCESS; 00570 00571 ctrl = er32(CTRL); 00572 status = er32(STATUS); 00573 rxcw = er32(RXCW); 00574 00575 /* 00576 * If we don't have link (auto-negotiation failed or link partner 00577 * cannot auto-negotiate), the cable is plugged in (we have signal), 00578 * and our link partner is not trying to auto-negotiate with us (we 00579 * are receiving idles or data), we need to force link up. We also 00580 * need to give auto-negotiation time to complete, in case the cable 00581 * was just plugged in. The autoneg_failed flag does this. 00582 */ 00583 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 00584 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 00585 (!(rxcw & E1000_RXCW_C))) { 00586 if (mac->autoneg_failed == 0) { 00587 mac->autoneg_failed = 1; 00588 goto out; 00589 } 00590 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 00591 00592 /* Disable auto-negotiation in the TXCW register */ 00593 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 00594 00595 /* Force link-up and also force full-duplex. */ 00596 ctrl = er32(CTRL); 00597 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 00598 ew32(CTRL, ctrl); 00599 00600 /* Configure Flow Control after forcing link up. */ 00601 ret_val = e1000e_config_fc_after_link_up(hw); 00602 if (ret_val) { 00603 e_dbg("Error configuring flow control\n"); 00604 goto out; 00605 } 00606 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 00607 /* 00608 * If we are forcing link and we are receiving /C/ ordered 00609 * sets, re-enable auto-negotiation in the TXCW register 00610 * and disable forced link in the Device Control register 00611 * in an attempt to auto-negotiate with our link partner. 00612 */ 00613 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 00614 ew32(TXCW, mac->txcw); 00615 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 00616 00617 mac->serdes_has_link = true; 00618 } 00619 00620 out: 00621 return ret_val; 00622 }
e1000e_check_for_serdes_link - Check for link (Serdes) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 631 of file e1000e_mac.c.
References e1000_mac_info::autoneg_failed, E1000_CTRL_FD, E1000_CTRL_SLU, E1000_RXCW_C, E1000_RXCW_IV, E1000_RXCW_SYNCH, E1000_STATUS_LU, E1000_SUCCESS, E1000_TXCW_ANE, e1000e_config_fc_after_link_up(), e_dbg, er32, ew32, e1000_hw::mac, e1000_mac_info::serdes_has_link, e1000_mac_info::txcw, u32, and udelay().
00632 { 00633 struct e1000_mac_info *mac = &hw->mac; 00634 u32 rxcw; 00635 u32 ctrl; 00636 u32 status; 00637 s32 ret_val = E1000_SUCCESS; 00638 00639 ctrl = er32(CTRL); 00640 status = er32(STATUS); 00641 rxcw = er32(RXCW); 00642 00643 /* 00644 * If we don't have link (auto-negotiation failed or link partner 00645 * cannot auto-negotiate), and our link partner is not trying to 00646 * auto-negotiate with us (we are receiving idles or data), 00647 * we need to force link up. We also need to give auto-negotiation 00648 * time to complete. 00649 */ 00650 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 00651 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 00652 if (mac->autoneg_failed == 0) { 00653 mac->autoneg_failed = 1; 00654 goto out; 00655 } 00656 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 00657 00658 /* Disable auto-negotiation in the TXCW register */ 00659 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 00660 00661 /* Force link-up and also force full-duplex. */ 00662 ctrl = er32(CTRL); 00663 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 00664 ew32(CTRL, ctrl); 00665 00666 /* Configure Flow Control after forcing link up. */ 00667 ret_val = e1000e_config_fc_after_link_up(hw); 00668 if (ret_val) { 00669 e_dbg("Error configuring flow control\n"); 00670 goto out; 00671 } 00672 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 00673 /* 00674 * If we are forcing link and we are receiving /C/ ordered 00675 * sets, re-enable auto-negotiation in the TXCW register 00676 * and disable forced link in the Device Control register 00677 * in an attempt to auto-negotiate with our link partner. 00678 */ 00679 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 00680 ew32(TXCW, mac->txcw); 00681 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 00682 00683 mac->serdes_has_link = true; 00684 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 00685 /* 00686 * If we force link for non-auto-negotiation switch, check 00687 * link status based on MAC synchronization for internal 00688 * serdes media type. 00689 */ 00690 /* SYNCH bit and IV bit are sticky. */ 00691 udelay(10); 00692 rxcw = er32(RXCW); 00693 if (rxcw & E1000_RXCW_SYNCH) { 00694 if (!(rxcw & E1000_RXCW_IV)) { 00695 mac->serdes_has_link = true; 00696 e_dbg("SERDES: Link up - forced.\n"); 00697 } 00698 } else { 00699 mac->serdes_has_link = false; 00700 e_dbg("SERDES: Link down - force failed.\n"); 00701 } 00702 } 00703 00704 if (E1000_TXCW_ANE & er32(TXCW)) { 00705 status = er32(STATUS); 00706 if (status & E1000_STATUS_LU) { 00707 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 00708 udelay(10); 00709 rxcw = er32(RXCW); 00710 if (rxcw & E1000_RXCW_SYNCH) { 00711 if (!(rxcw & E1000_RXCW_IV)) { 00712 mac->serdes_has_link = true; 00713 e_dbg("SERDES: Link up - autoneg " 00714 "completed sucessfully.\n"); 00715 } else { 00716 mac->serdes_has_link = false; 00717 e_dbg("SERDES: Link down - invalid" 00718 "codewords detected in autoneg.\n"); 00719 } 00720 } else { 00721 mac->serdes_has_link = false; 00722 e_dbg("SERDES: Link down - no sync.\n"); 00723 } 00724 } else { 00725 mac->serdes_has_link = false; 00726 e_dbg("SERDES: Link down - autoneg failed\n"); 00727 } 00728 } 00729 00730 out: 00731 return ret_val; 00732 }
e1000e_config_fc_after_link_up - Configures flow control after link : pointer to the HW structure
Checks the status of auto-negotiation after link up to ensure that the speed and duplex were not forced. If the link needed to be forced, then flow control needs to be forced also. If auto-negotiation is enabled and did not fail, then we configure flow control based on our link partner.
Definition at line 1148 of file e1000e_mac.c.
References e1000_mac_info::autoneg, e1000_mac_info::autoneg_failed, e1000_fc_info::current_mode, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, e1000_media_type_copper, e1000_media_type_fiber, e1000_media_type_internal_serdes, E1000_SUCCESS, e1000e_force_mac_fc(), e1e_rphy(), e_dbg, e1000_hw::fc, e1000_mac_operations::get_link_up_info, HALF_DUPLEX, e1000_hw::mac, e1000_phy_info::media_type, MII_SR_AUTONEG_COMPLETE, NWAY_AR_ASM_DIR, NWAY_AR_PAUSE, NWAY_LPAR_ASM_DIR, NWAY_LPAR_PAUSE, e1000_mac_info::ops, e1000_hw::phy, PHY_AUTONEG_ADV, PHY_LP_ABILITY, PHY_STATUS, e1000_fc_info::requested_mode, and u16.
01149 { 01150 struct e1000_mac_info *mac = &hw->mac; 01151 s32 ret_val = E1000_SUCCESS; 01152 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 01153 u16 speed, duplex; 01154 01155 /* 01156 * Check for the case where we have fiber media and auto-neg failed 01157 * so we had to force link. In this case, we need to force the 01158 * configuration of the MAC to match the "fc" parameter. 01159 */ 01160 if (mac->autoneg_failed) { 01161 if (hw->phy.media_type == e1000_media_type_fiber || 01162 hw->phy.media_type == e1000_media_type_internal_serdes) 01163 ret_val = e1000e_force_mac_fc(hw); 01164 } else { 01165 if (hw->phy.media_type == e1000_media_type_copper) 01166 ret_val = e1000e_force_mac_fc(hw); 01167 } 01168 01169 if (ret_val) { 01170 e_dbg("Error forcing flow control settings\n"); 01171 goto out; 01172 } 01173 01174 /* 01175 * Check for the case where we have copper media and auto-neg is 01176 * enabled. In this case, we need to check and see if Auto-Neg 01177 * has completed, and if so, how the PHY and link partner has 01178 * flow control configured. 01179 */ 01180 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 01181 /* 01182 * Read the MII Status Register and check to see if AutoNeg 01183 * has completed. We read this twice because this reg has 01184 * some "sticky" (latched) bits. 01185 */ 01186 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 01187 if (ret_val) 01188 goto out; 01189 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 01190 if (ret_val) 01191 goto out; 01192 01193 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 01194 e_dbg("Copper PHY and Auto Neg " 01195 "has not completed.\n"); 01196 goto out; 01197 } 01198 01199 /* 01200 * The AutoNeg process has completed, so we now need to 01201 * read both the Auto Negotiation Advertisement 01202 * Register (Address 4) and the Auto_Negotiation Base 01203 * Page Ability Register (Address 5) to determine how 01204 * flow control was negotiated. 01205 */ 01206 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, 01207 &mii_nway_adv_reg); 01208 if (ret_val) 01209 goto out; 01210 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, 01211 &mii_nway_lp_ability_reg); 01212 if (ret_val) 01213 goto out; 01214 01215 /* 01216 * Two bits in the Auto Negotiation Advertisement Register 01217 * (Address 4) and two bits in the Auto Negotiation Base 01218 * Page Ability Register (Address 5) determine flow control 01219 * for both the PHY and the link partner. The following 01220 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 01221 * 1999, describes these PAUSE resolution bits and how flow 01222 * control is determined based upon these settings. 01223 * NOTE: DC = Don't Care 01224 * 01225 * LOCAL DEVICE | LINK PARTNER 01226 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 01227 *-------|---------|-------|---------|-------------------- 01228 * 0 | 0 | DC | DC | e1000_fc_none 01229 * 0 | 1 | 0 | DC | e1000_fc_none 01230 * 0 | 1 | 1 | 0 | e1000_fc_none 01231 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 01232 * 1 | 0 | 0 | DC | e1000_fc_none 01233 * 1 | DC | 1 | DC | e1000_fc_full 01234 * 1 | 1 | 0 | 0 | e1000_fc_none 01235 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 01236 * 01237 * Are both PAUSE bits set to 1? If so, this implies 01238 * Symmetric Flow Control is enabled at both ends. The 01239 * ASM_DIR bits are irrelevant per the spec. 01240 * 01241 * For Symmetric Flow Control: 01242 * 01243 * LOCAL DEVICE | LINK PARTNER 01244 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01245 *-------|---------|-------|---------|-------------------- 01246 * 1 | DC | 1 | DC | E1000_fc_full 01247 * 01248 */ 01249 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 01250 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 01251 /* 01252 * Now we need to check if the user selected Rx ONLY 01253 * of pause frames. In this case, we had to advertise 01254 * FULL flow control because we could not advertise RX 01255 * ONLY. Hence, we must now check to see if we need to 01256 * turn OFF the TRANSMISSION of PAUSE frames. 01257 */ 01258 if (hw->fc.requested_mode == e1000_fc_full) { 01259 hw->fc.current_mode = e1000_fc_full; 01260 e_dbg("Flow Control = FULL.\r\n"); 01261 } else { 01262 hw->fc.current_mode = e1000_fc_rx_pause; 01263 e_dbg("Flow Control = " 01264 "RX PAUSE frames only.\r\n"); 01265 } 01266 } 01267 /* 01268 * For receiving PAUSE frames ONLY. 01269 * 01270 * LOCAL DEVICE | LINK PARTNER 01271 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01272 *-------|---------|-------|---------|-------------------- 01273 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 01274 */ 01275 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 01276 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 01277 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 01278 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 01279 hw->fc.current_mode = e1000_fc_tx_pause; 01280 e_dbg("Flow Control = TX PAUSE frames only.\r\n"); 01281 } 01282 /* 01283 * For transmitting PAUSE frames ONLY. 01284 * 01285 * LOCAL DEVICE | LINK PARTNER 01286 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01287 *-------|---------|-------|---------|-------------------- 01288 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 01289 */ 01290 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 01291 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 01292 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 01293 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 01294 hw->fc.current_mode = e1000_fc_rx_pause; 01295 e_dbg("Flow Control = RX PAUSE frames only.\r\n"); 01296 } else { 01297 /* 01298 * Per the IEEE spec, at this point flow control 01299 * should be disabled. 01300 */ 01301 hw->fc.current_mode = e1000_fc_none; 01302 e_dbg("Flow Control = NONE.\r\n"); 01303 } 01304 01305 /* 01306 * Now we need to do one last check... If we auto- 01307 * negotiated to HALF DUPLEX, flow control should not be 01308 * enabled per IEEE 802.3 spec. 01309 */ 01310 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 01311 if (ret_val) { 01312 e_dbg("Error getting link speed and duplex\n"); 01313 goto out; 01314 } 01315 01316 if (duplex == HALF_DUPLEX) 01317 hw->fc.current_mode = e1000_fc_none; 01318 01319 /* 01320 * Now we call a subroutine to actually force the MAC 01321 * controller to use the correct flow control settings. 01322 */ 01323 ret_val = e1000e_force_mac_fc(hw); 01324 if (ret_val) { 01325 e_dbg("Error forcing flow control settings\n"); 01326 goto out; 01327 } 01328 } 01329 01330 out: 01331 return ret_val; 01332 }
e1000e_disable_pcie_master - Disables PCI-express master access : pointer to the HW structure
Returns 0 (E1000_SUCCESS) if successful, else returns -10 (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused the master requests to be disabled.
Disables PCI-Express master access and verifies there are no pending requests.
Definition at line 1765 of file e1000e_mac.c.
References e1000_hw::bus, e1000_bus_type_pci_express, E1000_CTRL_GIO_MASTER_DISABLE, E1000_ERR_MASTER_REQUESTS_PENDING, E1000_STATUS_GIO_MASTER_ENABLE, E1000_SUCCESS, e_dbg, er32, ew32, MASTER_DISABLE_TIMEOUT, timeout(), e1000_bus_info::type, u32, and udelay().
01766 { 01767 u32 ctrl; 01768 s32 timeout = MASTER_DISABLE_TIMEOUT; 01769 s32 ret_val = E1000_SUCCESS; 01770 01771 if (hw->bus.type != e1000_bus_type_pci_express) 01772 goto out; 01773 01774 ctrl = er32(CTRL); 01775 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 01776 ew32(CTRL, ctrl); 01777 01778 while (timeout) { 01779 if (!(er32(STATUS) & 01780 E1000_STATUS_GIO_MASTER_ENABLE)) 01781 break; 01782 udelay(100); 01783 timeout--; 01784 } 01785 01786 if (!timeout) { 01787 e_dbg("Master requests are pending.\n"); 01788 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 01789 goto out; 01790 } 01791 01792 out: 01793 return ret_val; 01794 }
e1000e_force_mac_fc - Force the MAC's flow control settings : pointer to the HW structure
Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the device control register to reflect the adapter settings. TFCE and RFCE need to be explicitly set by software when a copper PHY is used because autonegotiation is managed by the PHY rather than the MAC. Software must also configure these bits when link is forced on a fiber connection.
Definition at line 1084 of file e1000e_mac.c.
References e1000_fc_info::current_mode, E1000_CTRL_RFCE, E1000_CTRL_TFCE, E1000_ERR_CONFIG, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, E1000_SUCCESS, e_dbg, er32, ew32, e1000_hw::fc, and u32.
01085 { 01086 u32 ctrl; 01087 s32 ret_val = E1000_SUCCESS; 01088 01089 ctrl = er32(CTRL); 01090 01091 /* 01092 * Because we didn't get link via the internal auto-negotiation 01093 * mechanism (we either forced link or we got link via PHY 01094 * auto-neg), we have to manually enable/disable transmit an 01095 * receive flow control. 01096 * 01097 * The "Case" statement below enables/disable flow control 01098 * according to the "hw->fc.current_mode" parameter. 01099 * 01100 * The possible values of the "fc" parameter are: 01101 * 0: Flow control is completely disabled 01102 * 1: Rx flow control is enabled (we can receive pause 01103 * frames but not send pause frames). 01104 * 2: Tx flow control is enabled (we can send pause frames 01105 * frames but we do not receive pause frames). 01106 * 3: Both Rx and Tx flow control (symmetric) is enabled. 01107 * other: No other values should be possible at this point. 01108 */ 01109 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 01110 01111 switch (hw->fc.current_mode) { 01112 case e1000_fc_none: 01113 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 01114 break; 01115 case e1000_fc_rx_pause: 01116 ctrl &= (~E1000_CTRL_TFCE); 01117 ctrl |= E1000_CTRL_RFCE; 01118 break; 01119 case e1000_fc_tx_pause: 01120 ctrl &= (~E1000_CTRL_RFCE); 01121 ctrl |= E1000_CTRL_TFCE; 01122 break; 01123 case e1000_fc_full: 01124 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 01125 break; 01126 default: 01127 e_dbg("Flow control param set incorrectly\n"); 01128 ret_val = -E1000_ERR_CONFIG; 01129 goto out; 01130 } 01131 01132 ew32(CTRL, ctrl); 01133 01134 out: 01135 return ret_val; 01136 }
e1000e_get_auto_rd_done - Check for auto read completion : pointer to the HW structure
Check EEPROM for Auto Read done bit.
Definition at line 1462 of file e1000e_mac.c.
References AUTO_READ_DONE_TIMEOUT, E1000_EECD_AUTO_RD, E1000_ERR_RESET, E1000_SUCCESS, e_dbg, er32, and msleep.
01463 { 01464 s32 i = 0; 01465 s32 ret_val = E1000_SUCCESS; 01466 01467 while (i < AUTO_READ_DONE_TIMEOUT) { 01468 if (er32(EECD) & E1000_EECD_AUTO_RD) 01469 break; 01470 msleep(1); 01471 i++; 01472 } 01473 01474 if (i == AUTO_READ_DONE_TIMEOUT) { 01475 e_dbg("Auto read by HW from NVM has not completed.\n"); 01476 ret_val = -E1000_ERR_RESET; 01477 goto out; 01478 } 01479 01480 out: 01481 return ret_val; 01482 }
e1000e_get_bus_info_pcie - Get PCIe bus information : pointer to the HW structure
Determines and stores the system bus information for a particular network interface. The following bus information is determined and stored: bus speed, bus width, type (PCIe), and PCIe function.
Definition at line 74 of file e1000e_mac.c.
References e1000_hw::bus, e1000_bus_speed_2500, e1000_bus_type_pci_express, e1000_bus_width_unknown, E1000_SUCCESS, e1000e_read_pcie_cap_reg(), e1000_hw::mac, e1000_mac_info::ops, PCIE_LINK_STATUS, PCIE_LINK_WIDTH_MASK, PCIE_LINK_WIDTH_SHIFT, e1000_mac_operations::set_lan_id, e1000_bus_info::speed, e1000_bus_info::type, u16, and e1000_bus_info::width.
00075 { 00076 struct e1000_mac_info *mac = &hw->mac; 00077 struct e1000_bus_info *bus = &hw->bus; 00078 00079 s32 ret_val; 00080 u16 pcie_link_status; 00081 00082 bus->type = e1000_bus_type_pci_express; 00083 bus->speed = e1000_bus_speed_2500; 00084 00085 ret_val = e1000e_read_pcie_cap_reg(hw, 00086 PCIE_LINK_STATUS, 00087 &pcie_link_status); 00088 if (ret_val) 00089 bus->width = e1000_bus_width_unknown; 00090 else 00091 bus->width = (enum e1000_bus_width)((pcie_link_status & 00092 PCIE_LINK_WIDTH_MASK) >> 00093 PCIE_LINK_WIDTH_SHIFT); 00094 00095 mac->ops.set_lan_id(hw); 00096 00097 return E1000_SUCCESS; 00098 }
| void e1000e_set_lan_id_single_port | ( | struct e1000_hw * | hw | ) |
e1000e_set_lan_id_single_port - Set LAN id for a single port device : pointer to the HW structure
Sets the LAN function id to zero for a single port device.
Definition at line 127 of file e1000e_mac.c.
References e1000_hw::bus, and e1000_bus_info::func.
Referenced by e1000e_init_mac_params_82571(), and e1000e_init_mac_params_ich8lan().
00128 { 00129 struct e1000_bus_info *bus = &hw->bus; 00130 00131 bus->func = 0; 00132 }
e1000e_get_hw_semaphore - Acquire hardware semaphore : pointer to the HW structure
Acquire the HW semaphore to access the PHY or NVM
Definition at line 1395 of file e1000e_mac.c.
References E1000_ERR_NVM, E1000_SUCCESS, E1000_SWSM_SMBI, E1000_SWSM_SWESMBI, e1000e_put_hw_semaphore(), e_dbg, er32, ew32, e1000_hw::nvm, timeout(), u32, udelay(), and e1000_nvm_info::word_size.
01396 { 01397 u32 swsm; 01398 s32 ret_val = E1000_SUCCESS; 01399 s32 timeout = hw->nvm.word_size + 1; 01400 s32 i = 0; 01401 01402 /* Get the SW semaphore */ 01403 while (i < timeout) { 01404 swsm = er32(SWSM); 01405 if (!(swsm & E1000_SWSM_SMBI)) 01406 break; 01407 01408 udelay(50); 01409 i++; 01410 } 01411 01412 if (i == timeout) { 01413 e_dbg("Driver can't access device - SMBI bit is set.\n"); 01414 ret_val = -E1000_ERR_NVM; 01415 goto out; 01416 } 01417 01418 /* Get the FW semaphore. */ 01419 for (i = 0; i < timeout; i++) { 01420 swsm = er32(SWSM); 01421 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 01422 01423 /* Semaphore acquired if bit latched */ 01424 if (er32(SWSM) & E1000_SWSM_SWESMBI) 01425 break; 01426 01427 udelay(50); 01428 } 01429 01430 if (i == timeout) { 01431 /* Release semaphores */ 01432 e1000e_put_hw_semaphore(hw); 01433 e_dbg("Driver can't access the NVM\n"); 01434 ret_val = -E1000_ERR_NVM; 01435 goto out; 01436 } 01437 01438 out: 01439 return ret_val; 01440 }
e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex
Read the status register for the current speed/duplex and store the current speed and duplex for copper connections.
Definition at line 1343 of file e1000e_mac.c.
References E1000_STATUS_FD, E1000_STATUS_SPEED_100, E1000_STATUS_SPEED_1000, E1000_SUCCESS, e_dbg, er32, FULL_DUPLEX, HALF_DUPLEX, SPEED_10, SPEED_100, SPEED_1000, and u32.
01345 { 01346 u32 status; 01347 01348 status = er32(STATUS); 01349 if (status & E1000_STATUS_SPEED_1000) { 01350 *speed = SPEED_1000; 01351 e_dbg("1000 Mbs, "); 01352 } else if (status & E1000_STATUS_SPEED_100) { 01353 *speed = SPEED_100; 01354 e_dbg("100 Mbs, "); 01355 } else { 01356 *speed = SPEED_10; 01357 e_dbg("10 Mbs, "); 01358 } 01359 01360 if (status & E1000_STATUS_FD) { 01361 *duplex = FULL_DUPLEX; 01362 e_dbg("Full Duplex\n"); 01363 } else { 01364 *duplex = HALF_DUPLEX; 01365 e_dbg("Half Duplex\n"); 01366 } 01367 01368 return E1000_SUCCESS; 01369 }
| void e1000e_update_mc_addr_list_generic | ( | struct e1000_hw * | hw, | |
| u8 * | mc_addr_list, | |||
| u32 | mc_addr_count | |||
| ) |
e1000e_update_mc_addr_list_generic - Update Multicast addresses : pointer to the HW structure : array of multicast addresses to program : number of multicast addresses to program
Updates entire Multicast Table Array. The caller must have a packed mc_addr_list of multicast addresses.
Definition at line 335 of file e1000e_mac.c.
References E1000_MTA, E1000_WRITE_REG_ARRAY, e1000e_hash_mc_addr_generic(), e1e_flush, ETH_ADDR_LEN, e1000_hw::mac, memset(), e1000_mac_info::mta_reg_count, e1000_mac_info::mta_shadow, and u32.
00337 { 00338 u32 hash_value, hash_bit, hash_reg; 00339 int i; 00340 00341 /* clear mta_shadow */ 00342 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 00343 00344 /* update mta_shadow from mc_addr_list */ 00345 for (i = 0; (u32) i < mc_addr_count; i++) { 00346 hash_value = e1000e_hash_mc_addr_generic(hw, mc_addr_list); 00347 00348 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 00349 hash_bit = hash_value & 0x1F; 00350 00351 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 00352 mc_addr_list += (ETH_ADDR_LEN); 00353 } 00354 00355 /* replace the entire MTA table */ 00356 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 00357 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 00358 e1e_flush(); 00359 }
e1000e_set_fc_watermarks - Set flow control high/low watermarks : pointer to the HW structure
Sets the flow control high/low threshold (watermark) registers. If flow control XON frame transmission is enabled, then set XON frame transmission as well.
Definition at line 1004 of file e1000e_mac.c.
References e1000_fc_info::current_mode, e1000_fc_tx_pause, E1000_FCRTL_XONE, E1000_SUCCESS, ew32, e1000_hw::fc, e1000_fc_info::high_water, e1000_fc_info::low_water, e1000_fc_info::send_xon, and u32.
01005 { 01006 s32 ret_val = E1000_SUCCESS; 01007 u32 fcrtl = 0, fcrth = 0; 01008 01009 /* 01010 * Set the flow control receive threshold registers. Normally, 01011 * these registers will be set to a default threshold that may be 01012 * adjusted later by the driver's runtime code. However, if the 01013 * ability to transmit pause frames is not enabled, then these 01014 * registers will be set to 0. 01015 */ 01016 if (hw->fc.current_mode & e1000_fc_tx_pause) { 01017 /* 01018 * We need to set up the Receive Threshold high and low water 01019 * marks as well as (optionally) enabling the transmission of 01020 * XON frames. 01021 */ 01022 fcrtl = hw->fc.low_water; 01023 if (hw->fc.send_xon) 01024 fcrtl |= E1000_FCRTL_XONE; 01025 01026 fcrth = hw->fc.high_water; 01027 } 01028 ew32(FCRTL, fcrtl); 01029 ew32(FCRTH, fcrth); 01030 01031 return ret_val; 01032 }
e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes : pointer to the HW structure
Configures collision distance and flow control for fiber and serdes links. Upon successful setup, poll for link.
Definition at line 806 of file e1000e_mac.c.
References E1000_CTRL_LRST, E1000_CTRL_SWDPIN1, e1000_media_type_internal_serdes, E1000_SUCCESS, e1000e_commit_fc_settings_generic(), e1000e_config_collision_dist(), e1000e_poll_fiber_serdes_link_generic(), e1e_flush, e_dbg, er32, ew32, e1000_phy_info::media_type, msleep, e1000_hw::phy, and u32.
00807 { 00808 u32 ctrl; 00809 s32 ret_val = E1000_SUCCESS; 00810 00811 ctrl = er32(CTRL); 00812 00813 /* Take the link out of reset */ 00814 ctrl &= ~E1000_CTRL_LRST; 00815 00816 e1000e_config_collision_dist(hw); 00817 00818 ret_val = e1000e_commit_fc_settings_generic(hw); 00819 if (ret_val) 00820 goto out; 00821 00822 /* 00823 * Since auto-negotiation is enabled, take the link out of reset (the 00824 * link will be in reset, because we previously reset the chip). This 00825 * will restart auto-negotiation. If auto-negotiation is successful 00826 * then the link-up status bit will be set and the flow control enable 00827 * bits (RFCE and TFCE) will be set according to their negotiated value. 00828 */ 00829 e_dbg("Auto-negotiation enabled\n"); 00830 00831 ew32(CTRL, ctrl); 00832 e1e_flush(); 00833 msleep(1); 00834 00835 /* 00836 * For these adapters, the SW definable pin 1 is set when the optics 00837 * detect a signal. If we have a signal, then poll for a "Link-Up" 00838 * indication. 00839 */ 00840 if (hw->phy.media_type == e1000_media_type_internal_serdes || 00841 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { 00842 ret_val = e1000e_poll_fiber_serdes_link_generic(hw); 00843 } else { 00844 e_dbg("No signal detected\n"); 00845 } 00846 00847 out: 00848 return ret_val; 00849 }
e1000e_setup_link - Setup flow control and link settings : pointer to the HW structure
Determines which flow control settings to use, then configures flow control. Calls the appropriate media-specific link configuration function. Assuming the adapter has a valid link partner, a valid link should be established. Assumes the hardware has previously been reset and the transmitter and receiver are not enabled.
Definition at line 744 of file e1000e_mac.c.
References e1000_phy_operations::check_reset_block, e1000_fc_info::current_mode, e1000_fc_default, E1000_SUCCESS, e1000e_check_reset_block(), e1000e_set_default_fc_generic(), e1000e_set_fc_watermarks(), e_dbg, ew32, e1000_hw::fc, FLOW_CONTROL_ADDRESS_HIGH, FLOW_CONTROL_ADDRESS_LOW, FLOW_CONTROL_TYPE, e1000_hw::mac, e1000_mac_info::ops, e1000_phy_info::ops, e1000_fc_info::pause_time, e1000_hw::phy, e1000_fc_info::requested_mode, and e1000_mac_operations::setup_physical_interface.
00745 { 00746 s32 ret_val = E1000_SUCCESS; 00747 00748 /* 00749 * In the case of the phy reset being blocked, we already have a link. 00750 * We do not need to set it up again. 00751 */ 00752 if (hw->phy.ops.check_reset_block) 00753 if (e1000e_check_reset_block(hw)) 00754 goto out; 00755 00756 /* 00757 * If requested flow control is set to default, set flow control 00758 * based on the EEPROM flow control settings. 00759 */ 00760 if (hw->fc.requested_mode == e1000_fc_default) { 00761 ret_val = e1000e_set_default_fc_generic(hw); 00762 if (ret_val) 00763 goto out; 00764 } 00765 00766 /* 00767 * Save off the requested flow control mode for use later. Depending 00768 * on the link partner's capabilities, we may or may not use this mode. 00769 */ 00770 hw->fc.current_mode = hw->fc.requested_mode; 00771 00772 e_dbg("After fix-ups FlowControl is now = %x\n", 00773 hw->fc.current_mode); 00774 00775 /* Call the necessary media_type subroutine to configure the link. */ 00776 ret_val = hw->mac.ops.setup_physical_interface(hw); 00777 if (ret_val) 00778 goto out; 00779 00780 /* 00781 * Initialize the flow control address, type, and PAUSE timer 00782 * registers to their default values. This is done even if flow 00783 * control is disabled, because it does not hurt anything to 00784 * initialize these registers. 00785 */ 00786 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 00787 ew32(FCT, FLOW_CONTROL_TYPE); 00788 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 00789 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 00790 00791 ew32(FCTTV, hw->fc.pause_time); 00792 00793 ret_val = e1000e_set_fc_watermarks(hw); 00794 00795 out: 00796 return ret_val; 00797 }
| void e1000e_clear_hw_cntrs_base | ( | struct e1000_hw * | hw | ) |
| void e1000e_clear_vfta_generic | ( | struct e1000_hw * | hw | ) |
e1000e_clear_vfta_generic - Clear VLAN filter table : pointer to the HW structure
Clears the register array which contains the VLAN filter table by setting all the values to 0.
Definition at line 141 of file e1000e_mac.c.
References E1000_VFTA, E1000_VLAN_FILTER_TBL_SIZE, E1000_WRITE_REG_ARRAY, e1e_flush, offset, and u32.
Referenced by e1000e_init_mac_params_80003es2lan().
00142 { 00143 u32 offset; 00144 00145 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 00146 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 00147 e1e_flush(); 00148 } 00149 }
| void e1000e_config_collision_dist | ( | struct e1000_hw * | hw | ) |
e1000e_config_collision_dist - Configure collision distance : pointer to the HW structure
Configures the collision distance to the default value and is used during link setup. Currently no func pointer exists and all implementations are handled in the generic version of this function.
Definition at line 859 of file e1000e_mac.c.
References E1000_COLD_SHIFT, E1000_COLLISION_DISTANCE, E1000_TCTL_COLD, e1e_flush, er32, ew32, and u32.
00860 { 00861 u32 tctl; 00862 00863 tctl = er32(TCTL); 00864 00865 tctl &= ~E1000_TCTL_COLD; 00866 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 00867 00868 ew32(TCTL, tctl); 00869 e1e_flush(); 00870 }
e1000e_init_rx_addrs - Initialize receive address's : pointer to the HW structure : receive address registers
Setups the receive address registers by setting the base receive address register to the devices MAC address and clearing all the other receive address registers to 0.
Definition at line 175 of file e1000e_mac.c.
References e1000_mac_info::addr, e_dbg, ETH_ADDR_LEN, e1000_hw::mac, e1000_mac_info::ops, e1000_mac_operations::rar_set, u32, and u8.
00176 { 00177 u32 i; 00178 u8 mac_addr[ETH_ADDR_LEN] = {0}; 00179 00180 /* Setup the receive address */ 00181 e_dbg("Programming MAC Address into RAR[0]\n"); 00182 00183 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 00184 00185 /* Zero out the other (rar_entry_count - 1) receive addresses */ 00186 e_dbg("Clearing RAR[1-%u]\n", rar_count-1); 00187 for (i = 1; i < rar_count; i++) 00188 hw->mac.ops.rar_set(hw, mac_addr, i); 00189 }
e1000e_mta_set_generic - Set multicast filter table address : pointer to the HW structure : determines the MTA register and bit to set
The multicast table address is a register array of 32-bit registers. The hash_value is used to determine what register the bit is in, the current value is read, the new bit is OR'd in and the new value is written back into the register.
Definition at line 301 of file e1000e_mac.c.
References E1000_MTA, E1000_READ_REG_ARRAY, E1000_WRITE_REG_ARRAY, e1e_flush, e1000_hw::mac, e1000_mac_info::mta_reg_count, and u32.
Referenced by e1000e_init_mac_params_80003es2lan(), e1000e_init_mac_params_82571(), and e1000e_init_mac_params_ich8lan().
00302 { 00303 u32 hash_bit, hash_reg, mta; 00304 00305 /* 00306 * The MTA is a register array of 32-bit registers. It is 00307 * treated like an array of (32*mta_reg_count) bits. We want to 00308 * set bit BitArray[hash_value]. So we figure out what register 00309 * the bit is in, read it, OR in the new bit, then write 00310 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 00311 * mask to bits 31:5 of the hash value which gives us the 00312 * register we're modifying. The hash bit within that register 00313 * is determined by the lower 5 bits of the hash value. 00314 */ 00315 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 00316 hash_bit = hash_value & 0x1F; 00317 00318 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 00319 00320 mta |= (1 << hash_bit); 00321 00322 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 00323 e1e_flush(); 00324 }
| void e1000e_pcix_mmrbc_workaround_generic | ( | struct e1000_hw * | hw | ) |
| void e1000e_put_hw_semaphore | ( | struct e1000_hw * | hw | ) |
e1000e_put_hw_semaphore - Release hardware semaphore : pointer to the HW structure
Release hardware semaphore used to access the PHY or NVM
Definition at line 1448 of file e1000e_mac.c.
References E1000_SWSM_SMBI, E1000_SWSM_SWESMBI, er32, ew32, and u32.
01449 { 01450 u32 swsm; 01451 01452 swsm = er32(SWSM); 01453 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 01454 ew32(SWSM, swsm); 01455 }
e1000e_rar_set - Set receive address register : pointer to the HW structure : pointer to the receive address : receive address array register
Sets the receive address array register at index to the address passed in by addr.
Definition at line 262 of file e1000e_mac.c.
References E1000_RAH_AV, e1e_flush, ew32, and u32.
00263 { 00264 u32 rar_low, rar_high; 00265 00266 /* 00267 * HW expects these in little endian so we reverse the byte order 00268 * from network order (big endian) to little endian 00269 */ 00270 rar_low = ((u32) addr[0] | 00271 ((u32) addr[1] << 8) | 00272 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 00273 00274 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 00275 00276 /* If MAC address zero, no need to set the AV bit */ 00277 if (rar_low || rar_high) 00278 rar_high |= E1000_RAH_AV; 00279 00280 /* 00281 * Some bridges will combine consecutive 32-bit writes into 00282 * a single burst write, which will malfunction on some parts. 00283 * The flushes avoid this. 00284 */ 00285 ew32(RAL(index), rar_low); 00286 e1e_flush(); 00287 ew32(RAH(index), rar_high); 00288 e1e_flush(); 00289 }
e1000e_check_alt_mac_addr_generic - Check for alternate MAC addr : pointer to the HW structure
Checks the nvm for an alternate MAC address. An alternate MAC address can be setup by pre-boot software and must be treated like a permanent address and must override the actual permanent MAC address. If an alternate MAC address is found it is programmed into RAR0, replacing the permanent address that was installed into RAR0 by the Si on reset. This function will return SUCCESS unless it encounters an error while reading the EEPROM.
Definition at line 203 of file e1000e_mac.c.
References e1000_hw::bus, E1000_ALT_MAC_ADDRESS_OFFSET_LAN1, E1000_FUNC_1, E1000_SUCCESS, e1000e_read_nvm(), e_dbg, ETH_ADDR_LEN, e1000_bus_info::func, e1000_hw::mac, NVM_ALT_MAC_ADDR_PTR, offset, e1000_mac_info::ops, e1000_mac_operations::rar_set, u16, u32, and u8.
Referenced by e1000e_read_mac_addr_80003es2lan(), e1000e_read_mac_addr_82571(), e1000e_reset_hw_80003es2lan(), and e1000e_reset_hw_82571().
00204 { 00205 u32 i; 00206 s32 ret_val = E1000_SUCCESS; 00207 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 00208 u8 alt_mac_addr[ETH_ADDR_LEN]; 00209 00210 ret_val = e1000e_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 00211 &nvm_alt_mac_addr_offset); 00212 if (ret_val) { 00213 e_dbg("NVM Read Error\n"); 00214 goto out; 00215 } 00216 00217 if (nvm_alt_mac_addr_offset == 0xFFFF) { 00218 /* There is no Alternate MAC Address */ 00219 goto out; 00220 } 00221 00222 if (hw->bus.func == E1000_FUNC_1) 00223 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 00224 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 00225 offset = nvm_alt_mac_addr_offset + (i >> 1); 00226 ret_val = e1000e_read_nvm(hw, offset, 1, &nvm_data); 00227 if (ret_val) { 00228 e_dbg("NVM Read Error\n"); 00229 goto out; 00230 } 00231 00232 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 00233 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 00234 } 00235 00236 /* if multicast bit is set, the alternate address will not be used */ 00237 if (alt_mac_addr[0] & 0x01) { 00238 e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); 00239 goto out; 00240 } 00241 00242 /* 00243 * We have a valid alternate MAC address, and we want to treat it the 00244 * same as the normal permanent MAC address stored by the HW into the 00245 * RAR. Do this by mapping this address into RAR0. 00246 */ 00247 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 00248 00249 out: 00250 return ret_val; 00251 }
| void e1000e_reset_adaptive | ( | struct e1000_hw * | hw | ) |
e1000e_reset_adaptive - Reset Adaptive Interframe Spacing : pointer to the HW structure
Reset the Adaptive Interframe Spacing throttle to default values.
Definition at line 1802 of file e1000e_mac.c.
References e1000_mac_info::adaptive_ifs, e1000_mac_info::current_ifs_val, e_dbg, ew32, IFS_MAX, e1000_mac_info::ifs_max_val, IFS_MIN, e1000_mac_info::ifs_min_val, IFS_RATIO, e1000_mac_info::ifs_ratio, IFS_STEP, e1000_mac_info::ifs_step_size, e1000_mac_info::in_ifs_mode, and e1000_hw::mac.
01803 { 01804 struct e1000_mac_info *mac = &hw->mac; 01805 01806 if (!mac->adaptive_ifs) { 01807 e_dbg("Not in Adaptive IFS mode!\n"); 01808 goto out; 01809 } 01810 01811 mac->current_ifs_val = 0; 01812 mac->ifs_min_val = IFS_MIN; 01813 mac->ifs_max_val = IFS_MAX; 01814 mac->ifs_step_size = IFS_STEP; 01815 mac->ifs_ratio = IFS_RATIO; 01816 01817 mac->in_ifs_mode = false; 01818 ew32(AIT, 0); 01819 out: 01820 return; 01821 }
e1000e_set_pcie_no_snoop - Set PCI-express capabilities : pointer to the HW structure : bitmap of snoop events
Set the PCI-express register to snoop for events enabled in 'no_snoop'.
Definition at line 1737 of file e1000e_mac.c.
References e1000_hw::bus, e1000_bus_type_pci_express, er32, ew32, PCIE_NO_SNOOP_ALL, e1000_bus_info::type, and u32.
01738 { 01739 u32 gcr; 01740 01741 if (hw->bus.type != e1000_bus_type_pci_express) 01742 goto out; 01743 01744 if (no_snoop) { 01745 gcr = er32(GCR); 01746 gcr &= ~(PCIE_NO_SNOOP_ALL); 01747 gcr |= no_snoop; 01748 ew32(GCR, gcr); 01749 } 01750 out: 01751 return; 01752 }
| void e1000e_update_adaptive | ( | struct e1000_hw * | hw | ) |
e1000e_update_adaptive - Update Adaptive Interframe Spacing : pointer to the HW structure
Update the Adaptive Interframe Spacing Throttle value based on the time between transmitted packets and time between collisions.
Definition at line 1830 of file e1000e_mac.c.
References e1000_mac_info::adaptive_ifs, e1000_mac_info::collision_delta, e1000_mac_info::current_ifs_val, e_dbg, ew32, e1000_mac_info::ifs_max_val, e1000_mac_info::ifs_min_val, e1000_mac_info::ifs_ratio, e1000_mac_info::ifs_step_size, e1000_mac_info::in_ifs_mode, e1000_hw::mac, MIN_NUM_XMITS, and e1000_mac_info::tx_packet_delta.
01831 { 01832 struct e1000_mac_info *mac = &hw->mac; 01833 01834 if (!mac->adaptive_ifs) { 01835 e_dbg("Not in Adaptive IFS mode!\n"); 01836 goto out; 01837 } 01838 01839 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 01840 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 01841 mac->in_ifs_mode = true; 01842 if (mac->current_ifs_val < mac->ifs_max_val) { 01843 if (!mac->current_ifs_val) 01844 mac->current_ifs_val = mac->ifs_min_val; 01845 else 01846 mac->current_ifs_val += 01847 mac->ifs_step_size; 01848 ew32(AIT, mac->current_ifs_val); 01849 } 01850 } 01851 } else { 01852 if (mac->in_ifs_mode && 01853 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 01854 mac->current_ifs_val = 0; 01855 mac->in_ifs_mode = false; 01856 ew32(AIT, 0); 01857 } 01858 } 01859 out: 01860 return; 01861 }
e1000e_write_vfta_generic - Write value to VLAN filter table : pointer to the HW structure : register offset in VLAN filter table : register value written to VLAN filter table
Writes value at the given offset in the register array which stores the VLAN filter table.
Definition at line 160 of file e1000e_mac.c.
References E1000_VFTA, E1000_WRITE_REG_ARRAY, and e1e_flush.
00161 { 00162 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 00163 e1e_flush(); 00164 }
1.5.7.1