e1000e_ich8lan.h File Reference

((ID_LED_DEF1_DEF2 << 12) | \
                                 (ID_LED_OFF1_OFF2 <<  8) | \
                                 (ID_LED_OFF1_ON2  <<  4) | \
                                 (ID_LED_DEF1_DEF2))

Definition at line 69 of file e1000e_ich8lan.h.

Referenced by e1000e_valid_led_default_ich8lan().

#define E1000_ICH_NVM_SIG_WORD 0x13

Definition at line 74 of file e1000e_ich8lan.h.

Referenced by e1000e_update_nvm_checksum_ich8lan(), and e1000e_valid_nvm_bank_detect_ich8lan().

#define E1000_ICH_NVM_SIG_MASK 0xC000

Definition at line 75 of file e1000e_ich8lan.h.

Referenced by e1000e_update_nvm_checksum_ich8lan().

#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0

Definition at line 76 of file e1000e_ich8lan.h.

Referenced by e1000e_valid_nvm_bank_detect_ich8lan().

#define E1000_ICH_NVM_SIG_VALUE 0x80

Definition at line 77 of file e1000e_ich8lan.h.

Referenced by e1000e_valid_nvm_bank_detect_ich8lan().

#define E1000_ICH8_LAN_INIT_TIMEOUT 1500

Definition at line 79 of file e1000e_ich8lan.h.

Referenced by e1000e_lan_init_done_ich8lan().

#define E1000_FEXTNVM_SW_CONFIG 1

Definition at line 81 of file e1000e_ich8lan.h.

Referenced by e1000e_sw_lcd_config_ich8lan().

#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27)

Definition at line 82 of file e1000e_ich8lan.h.

Referenced by e1000e_oem_bits_config_ich8lan(), and e1000e_sw_lcd_config_ich8lan().

#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL

Definition at line 84 of file e1000e_ich8lan.h.

Referenced by e1000e_init_hw_ich8lan().

#define E1000_ICH_RAR_ENTRIES 7

Definition at line 86 of file e1000e_ich8lan.h.

Referenced by e1000e_init_mac_params_ich8lan().

#define PHY_PAGE_SHIFT 5

Definition at line 88 of file e1000e_ich8lan.h.

#define PHY_REG	(	page,
		reg		)

Value:

(((page) << PHY_PAGE_SHIFT) | \
                           ((reg) & MAX_PHY_REG_ADDRESS))

Definition at line 89 of file e1000e_ich8lan.h.

Referenced by e1000e_hv_phy_workarounds_ich8lan(), e1000e_k1_gig_workaround_hv(), and e1000e_setup_link_ich8lan().

#define IGP3_KMRN_DIAG PHY_REG(770, 19)

Definition at line 91 of file e1000e_ich8lan.h.

Referenced by e1000e_kmrn_lock_loss_workaround_ich8lan().

#define IGP3_VR_CTRL PHY_REG(776, 18)

Definition at line 92 of file e1000e_ich8lan.h.

Referenced by e1000e_igp3_phy_powerdown_workaround_ich8lan().

#define IGP3_CAPABILITY PHY_REG(776, 19)

Definition at line 93 of file e1000e_ich8lan.h.

#define IGP3_PM_CTRL PHY_REG(769, 20)

Definition at line 94 of file e1000e_ich8lan.h.

#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002

Definition at line 96 of file e1000e_ich8lan.h.

Referenced by e1000e_kmrn_lock_loss_workaround_ich8lan().

#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300

Definition at line 97 of file e1000e_ich8lan.h.

Referenced by e1000e_igp3_phy_powerdown_workaround_ich8lan().

#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200

Definition at line 98 of file e1000e_ich8lan.h.

Referenced by e1000e_igp3_phy_powerdown_workaround_ich8lan().

#define IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020

Definition at line 99 of file e1000e_ich8lan.h.

#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)

Definition at line 102 of file e1000e_ich8lan.h.

#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)

Definition at line 103 of file e1000e_ich8lan.h.

Referenced by e1000e_init_hw_ich8lan(), e1000e_phy_hw_reset_ich8lan(), e1000e_reset(), and e1000e_reset_hw_ich8lan().

#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)

Definition at line 104 of file e1000e_ich8lan.h.

#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)

Definition at line 105 of file e1000e_ich8lan.h.

#define BM_RAR_L ( _i ) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))

Definition at line 106 of file e1000e_ich8lan.h.

#define BM_RAR_M ( _i ) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))

Definition at line 107 of file e1000e_ich8lan.h.

#define BM_RAR_H ( _i ) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))

Definition at line 108 of file e1000e_ich8lan.h.

#define BM_RAR_CTRL ( _i ) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))

Definition at line 109 of file e1000e_ich8lan.h.

#define BM_MTA ( _i ) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))

Definition at line 110 of file e1000e_ich8lan.h.

#define BM_RCTL_UPE 0x0001

Definition at line 112 of file e1000e_ich8lan.h.

#define BM_RCTL_MPE 0x0002

Definition at line 113 of file e1000e_ich8lan.h.

#define BM_RCTL_MO_SHIFT 3

Definition at line 114 of file e1000e_ich8lan.h.

#define BM_RCTL_MO_MASK (3 << 3)

Definition at line 115 of file e1000e_ich8lan.h.

#define BM_RCTL_BAM 0x0020

Definition at line 116 of file e1000e_ich8lan.h.

#define BM_RCTL_PMCF 0x0040

Definition at line 117 of file e1000e_ich8lan.h.

#define BM_RCTL_RFCE 0x0080

Definition at line 118 of file e1000e_ich8lan.h.

#define HV_LED_CONFIG PHY_REG(768, 30)

Definition at line 120 of file e1000e_ich8lan.h.

Referenced by e1000e_cleanup_led_pchlan(), e1000e_led_off_pchlan(), e1000e_led_on_pchlan(), e1000e_setup_led_pchlan(), and e1000e_sw_lcd_config_ich8lan().

#define HV_MUX_DATA_CTRL PHY_REG(776, 16)

Definition at line 121 of file e1000e_ich8lan.h.

Referenced by e1000e_link_stall_workaround_hv().

#define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400

Definition at line 122 of file e1000e_ich8lan.h.

Referenced by e1000e_link_stall_workaround_hv().

#define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004

Definition at line 123 of file e1000e_ich8lan.h.

Referenced by e1000e_link_stall_workaround_hv().

#define HV_SCC_UPPER PHY_REG(778, 16)

Definition at line 124 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_SCC_LOWER PHY_REG(778, 17)

Definition at line 125 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_ECOL_UPPER PHY_REG(778, 18)

Definition at line 126 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_ECOL_LOWER PHY_REG(778, 19)

Definition at line 127 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_MCC_UPPER PHY_REG(778, 20)

Definition at line 128 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_MCC_LOWER PHY_REG(778, 21)

Definition at line 129 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_LATECOL_UPPER PHY_REG(778, 23)

Definition at line 130 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_LATECOL_LOWER PHY_REG(778, 24)

Definition at line 131 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_COLC_UPPER PHY_REG(778, 25)

Definition at line 132 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_COLC_LOWER PHY_REG(778, 26)

Definition at line 133 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_DC_UPPER PHY_REG(778, 27)

Definition at line 134 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_DC_LOWER PHY_REG(778, 28)

Definition at line 135 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_TNCRS_UPPER PHY_REG(778, 29)

Definition at line 136 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define HV_TNCRS_LOWER PHY_REG(778, 30)

Definition at line 137 of file e1000e_ich8lan.h.

Referenced by e1000e_clear_hw_cntrs_ich8lan().

#define E1000_FCRTV_PCH 0x05F40

Definition at line 139 of file e1000e_ich8lan.h.

#define E1000_NVM_K1_CONFIG 0x1B

Definition at line 141 of file e1000e_ich8lan.h.

Referenced by e1000e_reset_hw_ich8lan().

#define E1000_NVM_K1_ENABLE 0x1

Definition at line 142 of file e1000e_ich8lan.h.

Referenced by e1000e_reset_hw_ich8lan().

#define HV_SMB_ADDR PHY_REG(768, 26)

Definition at line 145 of file e1000e_ich8lan.h.

Referenced by e1000e_sw_lcd_config_ich8lan().

#define HV_SMB_ADDR_PEC_EN 0x0200

Definition at line 146 of file e1000e_ich8lan.h.

Referenced by e1000e_sw_lcd_config_ich8lan().

#define HV_SMB_ADDR_VALID 0x0080

Definition at line 147 of file e1000e_ich8lan.h.

Referenced by e1000e_sw_lcd_config_ich8lan().

#define E1000_STRAP 0x0000C

Definition at line 150 of file e1000e_ich8lan.h.

#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000

Definition at line 151 of file e1000e_ich8lan.h.

Referenced by e1000e_sw_lcd_config_ich8lan().

#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17

Definition at line 152 of file e1000e_ich8lan.h.

Referenced by e1000e_sw_lcd_config_ich8lan().

#define HV_OEM_BITS PHY_REG(768, 25)

Definition at line 155 of file e1000e_ich8lan.h.

Referenced by e1000e_oem_bits_config_ich8lan(), and e1000e_set_lplu_state_pchlan().

#define HV_OEM_BITS_LPLU 0x0004

Definition at line 156 of file e1000e_ich8lan.h.

Referenced by e1000e_oem_bits_config_ich8lan(), and e1000e_set_lplu_state_pchlan().

#define HV_OEM_BITS_GBE_DIS 0x0040

Definition at line 157 of file e1000e_ich8lan.h.

Referenced by e1000e_oem_bits_config_ich8lan().

#define HV_OEM_BITS_RESTART_AN 0x0400

Definition at line 158 of file e1000e_ich8lan.h.

Referenced by e1000e_oem_bits_config_ich8lan(), and e1000e_set_lplu_state_pchlan().

#define LCD_CFG_PHY_ADDR_BIT 0x0020

Definition at line 160 of file e1000e_ich8lan.h.

#define SW_FLAG_TIMEOUT 1000

Definition at line 162 of file e1000e_ich8lan.h.

Referenced by e1000e_acquire_swflag_ich8lan().

#define IMS_ICH_ENABLE_MASK

Value:

(\
    E1000_IMS_DSW   | \
    E1000_IMS_PHYINT | \
    E1000_IMS_EPRST)

Definition at line 170 of file e1000e_ich8lan.h.

#define E1000_ICR_LSECPNC 0x00004000

Definition at line 176 of file e1000e_ich8lan.h.

#define E1000_IMS_LSECPNC E1000_ICR_LSECPNC

Definition at line 177 of file e1000e_ich8lan.h.

#define E1000_ICS_LSECPNC E1000_ICR_LSECPNC

Definition at line 178 of file e1000e_ich8lan.h.

#define E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000

Definition at line 181 of file e1000e_ich8lan.h.

#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000

Definition at line 182 of file e1000e_ich8lan.h.

#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000

Definition at line 183 of file e1000e_ich8lan.h.

#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000

Definition at line 184 of file e1000e_ich8lan.h.

#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000

Definition at line 185 of file e1000e_ich8lan.h.

Function Documentation

FILE_LICENCE ( GPL2_OR_LATER )

void e1000e_set_kmrn_lock_loss_workaround_ich8lan	(	struct e1000_hw *	hw,
		bool	state
	)

e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state : pointer to the HW structure : boolean value used to set the current Kumeran workaround state

If ICH8, set the current Kumeran workaround state (enabled - true /disabled - false).

Definition at line 3013 of file e1000e_ich8lan.c.

References e1000_hw::dev_spec, e1000_ich8lan, e_dbg, e1000_hw::ich8lan, e1000_dev_spec_ich8lan::kmrn_lock_loss_workaround_enabled, e1000_hw::mac, and e1000_mac_info::type.

03015 {
03016         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
03017 
03018         if (hw->mac.type != e1000_ich8lan) {
03019                 e_dbg("Workaround applies to ICH8 only.\n");
03020                 return;
03021         }
03022 
03023         dev_spec->kmrn_lock_loss_workaround_enabled = state;
03024 
03025         return;
03026 }

void e1000e_igp3_phy_powerdown_workaround_ich8lan ( struct e1000_hw * hw )

e1000e_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 : pointer to the HW structure

Workaround for 82566 power-down on D3 entry: 1) disable gigabit link 2) write VR power-down enable 3) read it back Continue if successful, else issue LCD reset and repeat

Definition at line 3038 of file e1000e_ich8lan.c.

References E1000_CTRL_PHY_RST, e1000_ich8lan, E1000_PHY_CTRL_GBE_DISABLE, E1000_PHY_CTRL_NOND0A_GBE_DISABLE, e1000_phy_igp_3, e1000e_gig_downshift_workaround_ich8lan(), e1e_rphy(), e1e_wphy(), er32, ew32, IGP3_VR_CTRL, IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK, IGP3_VR_CTRL_MODE_SHUTDOWN, e1000_hw::mac, e1000_hw::phy, e1000_mac_info::type, e1000_phy_info::type, u16, u32, and u8.

03039 {
03040         u32 reg;
03041         u16 data;
03042         u8  retry = 0;
03043 
03044         if (hw->phy.type != e1000_phy_igp_3)
03045                 goto out;
03046 
03047         /* Try the workaround twice (if needed) */
03048         do {
03049                 /* Disable link */
03050                 reg = er32(PHY_CTRL);
03051                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
03052                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
03053                 ew32(PHY_CTRL, reg);
03054 
03055                 /*
03056                  * Call gig speed drop workaround on Gig disable before
03057                  * accessing any PHY registers
03058                  */
03059                 if (hw->mac.type == e1000_ich8lan)
03060                         e1000e_gig_downshift_workaround_ich8lan(hw);
03061 
03062                 /* Write VR power-down enable */
03063                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
03064                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
03065                 e1e_wphy(hw, IGP3_VR_CTRL,
03066                                    data | IGP3_VR_CTRL_MODE_SHUTDOWN);
03067 
03068                 /* Read it back and test */
03069                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
03070                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
03071                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
03072                         break;
03073 
03074                 /* Issue PHY reset and repeat at most one more time */
03075                 reg = er32(CTRL);
03076                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
03077                 retry++;
03078         } while (retry);
03079 
03080 out:
03081         return;
03082 }

void e1000e_gig_downshift_workaround_ich8lan ( struct e1000_hw * hw )

e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working : pointer to the HW structure

Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), LPLU, Gig disable, MDIC PHY reset): 1) Set Kumeran Near-end loopback 2) Clear Kumeran Near-end loopback Should only be called for ICH8[m] devices with IGP_3 Phy.

Definition at line 3094 of file e1000e_ich8lan.c.

References e1000_ich8lan, E1000_KMRNCTRLSTA_DIAG_NELPBK, E1000_KMRNCTRLSTA_DIAG_OFFSET, e1000_phy_igp_3, E1000_SUCCESS, e1000e_read_kmrn_reg(), e1000e_write_kmrn_reg(), e1000_hw::mac, e1000_hw::phy, e1000_phy_info::type, e1000_mac_info::type, and u16.

03095 {
03096         s32 ret_val = E1000_SUCCESS;
03097         u16 reg_data;
03098 
03099         if ((hw->mac.type != e1000_ich8lan) ||
03100             (hw->phy.type != e1000_phy_igp_3))
03101                 goto out;
03102 
03103         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
03104                                               &reg_data);
03105         if (ret_val)
03106                 goto out;
03107         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
03108         ret_val = e1000e_write_kmrn_reg(hw,
03109                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
03110                                                reg_data);
03111         if (ret_val)
03112                 goto out;
03113         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
03114         ret_val = e1000e_write_kmrn_reg(hw,
03115                                                E1000_KMRNCTRLSTA_DIAG_OFFSET,
03116                                                reg_data);
03117 out:
03118         return;
03119 }

void e1000e_disable_gig_wol_ich8lan ( struct e1000_hw * hw )

e1000e_disable_gig_wol_ich8lan - disable gig during WoL : pointer to the HW structure

During S0 to Sx transition, it is possible the link remains at gig instead of negotiating to a lower speed. Before going to Sx, set 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation to a lower speed.

Should only be called for applicable parts.

Definition at line 3132 of file e1000e_ich8lan.c.

References e1000_ich10lan, e1000_ich8lan, e1000_ich9lan, e1000_pchlan, E1000_PHY_CTRL_D0A_LPLU, E1000_PHY_CTRL_GBE_DISABLE, e1000e_phy_hw_reset_ich8lan(), er32, ew32, e1000_hw::mac, e1000_mac_info::type, and u32.

03133 {
03134         u32 phy_ctrl;
03135 
03136         switch (hw->mac.type) {
03137         case e1000_ich8lan:
03138         case e1000_ich9lan:
03139         case e1000_ich10lan:
03140         case e1000_pchlan:
03141                 phy_ctrl = er32(PHY_CTRL);
03142                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
03143                             E1000_PHY_CTRL_GBE_DISABLE;
03144                 ew32(PHY_CTRL, phy_ctrl);
03145 
03146                 if (hw->mac.type == e1000_pchlan)
03147                         e1000e_phy_hw_reset_ich8lan(hw);
03148         default:
03149                 break;
03150         }
03151 
03152         return;
03153 }

s32 e1000e_configure_k1_ich8lan	(	struct e1000_hw *	hw,
		bool	k1_enable
	)

e1000e_configure_k1_ich8lan - Configure K1 power state : pointer to the HW structure : K1 state to configure

Configure the K1 power state based on the provided parameter. Assumes semaphore already acquired.

Success returns 0, Failure returns -E1000_ERR_PHY (-2)

Definition at line 949 of file e1000e_ich8lan.c.

References E1000_CTRL_EXT, E1000_CTRL_EXT_SPD_BYPS, E1000_CTRL_FRCSPD, E1000_CTRL_SPD_100, E1000_CTRL_SPD_1000, E1000_KMRNCTRLSTA_K1_CONFIG, E1000_KMRNCTRLSTA_K1_ENABLE, E1000_SUCCESS, E1000_WRITE_REG, e1000e_read_kmrn_reg_locked(), e1000e_write_kmrn_reg_locked(), er32, ew32, u16, u32, and udelay().

Referenced by e1000e_k1_gig_workaround_hv().

00950 {
00951         s32 ret_val = E1000_SUCCESS;
00952         u32 ctrl_reg = 0;
00953         u32 ctrl_ext = 0;
00954         u32 reg = 0;
00955         u16 kmrn_reg = 0;
00956 
00957         ret_val = e1000e_read_kmrn_reg_locked(hw,
00958                                              E1000_KMRNCTRLSTA_K1_CONFIG,
00959                                              &kmrn_reg);
00960         if (ret_val)
00961                 goto out;
00962 
00963         if (k1_enable)
00964                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
00965         else
00966                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
00967 
00968         ret_val = e1000e_write_kmrn_reg_locked(hw,
00969                                               E1000_KMRNCTRLSTA_K1_CONFIG,
00970                                               kmrn_reg);
00971         if (ret_val)
00972                 goto out;
00973 
00974         udelay(20);
00975         ctrl_ext = er32(CTRL_EXT);
00976         ctrl_reg = er32(CTRL);
00977 
00978         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
00979         reg |= E1000_CTRL_FRCSPD;
00980         ew32(CTRL, reg);
00981 
00982         E1000_WRITE_REG(hw,
00983                         E1000_CTRL_EXT,
00984                         ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
00985         udelay(20);
00986         ew32(CTRL, ctrl_reg);
00987         ew32(CTRL_EXT, ctrl_ext);
00988         udelay(20);
00989 
00990 out:
00991         return ret_val;
00992 }

s32 e1000e_oem_bits_config_ich8lan	(	struct e1000_hw *	hw,
		bool	d0_state
	)

e1000e_oem_bits_config_ich8lan - SW-based LCD Configuration : pointer to the HW structure : boolean if entering d0 or d3 device state

SW will configure Gbe Disable and LPLU based on the NVM. The four bits are collectively called OEM bits. The OEM Write Enable bit and SW Config bit in NVM determines whether HW should configure LPLU and Gbe Disable.

Definition at line 1003 of file e1000e_ich8lan.c.

References e1000_phy_operations::acquire, E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE, E1000_FEXTNVM_SW_CONFIG_ICH8M, e1000_pchlan, E1000_PHY_CTRL_D0A_LPLU, E1000_PHY_CTRL_GBE_DISABLE, E1000_PHY_CTRL_NOND0A_GBE_DISABLE, E1000_PHY_CTRL_NOND0A_LPLU, e1000e_check_reset_block(), er32, HV_OEM_BITS, HV_OEM_BITS_GBE_DIS, HV_OEM_BITS_LPLU, HV_OEM_BITS_RESTART_AN, e1000_hw::mac, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg_locked, e1000_phy_operations::release, e1000_mac_info::type, u16, u32, and e1000_phy_operations::write_reg_locked.

Referenced by e1000e_phy_hw_reset_ich8lan(), and e1000e_reset_hw_ich8lan().

01004 {
01005         s32 ret_val = 0;
01006         u32 mac_reg;
01007         u16 oem_reg;
01008 
01009         if (hw->mac.type != e1000_pchlan)
01010                 return ret_val;
01011 
01012         ret_val = hw->phy.ops.acquire(hw);
01013         if (ret_val)
01014                 return ret_val;
01015 
01016         mac_reg = er32(EXTCNF_CTRL);
01017         if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
01018                 goto out;
01019 
01020         mac_reg = er32(FEXTNVM);
01021         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
01022                 goto out;
01023 
01024         mac_reg = er32(PHY_CTRL);
01025 
01026         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
01027         if (ret_val)
01028                 goto out;
01029 
01030         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
01031 
01032         if (d0_state) {
01033                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
01034                         oem_reg |= HV_OEM_BITS_GBE_DIS;
01035 
01036                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
01037                         oem_reg |= HV_OEM_BITS_LPLU;
01038         } else {
01039                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
01040                         oem_reg |= HV_OEM_BITS_GBE_DIS;
01041 
01042                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
01043                         oem_reg |= HV_OEM_BITS_LPLU;
01044         }
01045         /* Restart auto-neg to activate the bits */
01046         if (!e1000e_check_reset_block(hw))
01047                 oem_reg |= HV_OEM_BITS_RESTART_AN;
01048         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
01049 
01050 out:
01051         hw->phy.ops.release(hw);
01052 
01053         return ret_val;
01054 }


Defines
#define	ICH_FLASH_GFPREG 0x0000
#define	ICH_FLASH_HSFSTS 0x0004
#define	ICH_FLASH_HSFCTL 0x0006
#define	ICH_FLASH_FADDR 0x0008
#define	ICH_FLASH_FDATA0 0x0010
#define	ICH_FLASH_READ_COMMAND_TIMEOUT 10000000
#define	ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000
#define	ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000
#define	ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
#define	ICH_FLASH_CYCLE_REPEAT_COUNT 10
#define	ICH_CYCLE_READ 0
#define	ICH_CYCLE_WRITE 2
#define	ICH_CYCLE_ERASE 3
#define	FLASH_GFPREG_BASE_MASK 0x1FFF
#define	FLASH_SECTOR_ADDR_SHIFT 12
#define	ICH_FLASH_SEG_SIZE_256 256
#define	ICH_FLASH_SEG_SIZE_4K 4096
#define	ICH_FLASH_SEG_SIZE_8K 8192
#define	ICH_FLASH_SEG_SIZE_64K 65536
#define	ICH_FLASH_SECTOR_SIZE 4096
#define	ICH_FLASH_REG_MAPSIZE 0x00A0
#define	E1000_ICH_FWSM_RSPCIPHY 0x00000040
#define	E1000_ICH_FWSM_DISSW 0x10000000
#define	E1000_ICH_FWSM_FW_VALID 0x00008000
#define	E1000_ICH_MNG_IAMT_MODE 0x2
#define	ID_LED_DEFAULT_ICH8LAN
#define	E1000_ICH_NVM_SIG_WORD 0x13
#define	E1000_ICH_NVM_SIG_MASK 0xC000
#define	E1000_ICH_NVM_VALID_SIG_MASK 0xC0
#define	E1000_ICH_NVM_SIG_VALUE 0x80
#define	E1000_ICH8_LAN_INIT_TIMEOUT 1500
#define	E1000_FEXTNVM_SW_CONFIG 1
#define	E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27)
#define	PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
#define	E1000_ICH_RAR_ENTRIES 7
#define	PHY_PAGE_SHIFT 5
#define	PHY_REG(page, reg)
#define	IGP3_KMRN_DIAG PHY_REG(770, 19)
#define	IGP3_VR_CTRL PHY_REG(776, 18)
#define	IGP3_CAPABILITY PHY_REG(776, 19)
#define	IGP3_PM_CTRL PHY_REG(769, 20)
#define	IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
#define	IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
#define	IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
#define	IGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020
#define	BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
#define	BM_WUC PHY_REG(BM_WUC_PAGE, 1)
#define	BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
#define	BM_WUS PHY_REG(BM_WUC_PAGE, 3)
#define	BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
#define	BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
#define	BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
#define	BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
#define	BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
#define	BM_RCTL_UPE 0x0001
#define	BM_RCTL_MPE 0x0002
#define	BM_RCTL_MO_SHIFT 3
#define	BM_RCTL_MO_MASK (3 << 3)
#define	BM_RCTL_BAM 0x0020
#define	BM_RCTL_PMCF 0x0040
#define	BM_RCTL_RFCE 0x0080
#define	HV_LED_CONFIG PHY_REG(768, 30)
#define	HV_MUX_DATA_CTRL PHY_REG(776, 16)
#define	HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
#define	HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
#define	HV_SCC_UPPER PHY_REG(778, 16)
#define	HV_SCC_LOWER PHY_REG(778, 17)
#define	HV_ECOL_UPPER PHY_REG(778, 18)
#define	HV_ECOL_LOWER PHY_REG(778, 19)
#define	HV_MCC_UPPER PHY_REG(778, 20)
#define	HV_MCC_LOWER PHY_REG(778, 21)
#define	HV_LATECOL_UPPER PHY_REG(778, 23)
#define	HV_LATECOL_LOWER PHY_REG(778, 24)
#define	HV_COLC_UPPER PHY_REG(778, 25)
#define	HV_COLC_LOWER PHY_REG(778, 26)
#define	HV_DC_UPPER PHY_REG(778, 27)
#define	HV_DC_LOWER PHY_REG(778, 28)
#define	HV_TNCRS_UPPER PHY_REG(778, 29)
#define	HV_TNCRS_LOWER PHY_REG(778, 30)
#define	E1000_FCRTV_PCH 0x05F40
#define	E1000_NVM_K1_CONFIG 0x1B
#define	E1000_NVM_K1_ENABLE 0x1
#define	HV_SMB_ADDR PHY_REG(768, 26)
#define	HV_SMB_ADDR_PEC_EN 0x0200
#define	HV_SMB_ADDR_VALID 0x0080
#define	E1000_STRAP 0x0000C
#define	E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
#define	E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
#define	HV_OEM_BITS PHY_REG(768, 25)
#define	HV_OEM_BITS_LPLU 0x0004
#define	HV_OEM_BITS_GBE_DIS 0x0040
#define	HV_OEM_BITS_RESTART_AN 0x0400
#define	LCD_CFG_PHY_ADDR_BIT 0x0020
#define	SW_FLAG_TIMEOUT 1000
#define	IMS_ICH_ENABLE_MASK
#define	E1000_ICR_LSECPNC 0x00004000
#define	E1000_IMS_LSECPNC E1000_ICR_LSECPNC
#define	E1000_ICS_LSECPNC E1000_ICR_LSECPNC
#define	E1000_RXDEXT_LINKSEC_STATUS_LSECH 0x01000000
#define	E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK 0x60000000
#define	E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH 0x20000000
#define	E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
#define	E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG 0x60000000
Functions
	FILE_LICENCE (GPL2_OR_LATER)
void	e1000e_set_kmrn_lock_loss_workaround_ich8lan (struct e1000_hw *hw, bool state)
	e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state : pointer to the HW structure : boolean value used to set the current Kumeran workaround state
void	e1000e_igp3_phy_powerdown_workaround_ich8lan (struct e1000_hw *hw)
	e1000e_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 : pointer to the HW structure
void	e1000e_gig_downshift_workaround_ich8lan (struct e1000_hw *hw)
	e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working : pointer to the HW structure
void	e1000e_disable_gig_wol_ich8lan (struct e1000_hw *hw)
	e1000e_disable_gig_wol_ich8lan - disable gig during WoL : pointer to the HW structure
s32	e1000e_configure_k1_ich8lan (struct e1000_hw *hw, bool k1_enable)
	e1000e_configure_k1_ich8lan - Configure K1 power state : pointer to the HW structure : K1 state to configure
s32	e1000e_oem_bits_config_ich8lan (struct e1000_hw *hw, bool d0_config)
	e1000e_oem_bits_config_ich8lan - SW-based LCD Configuration : pointer to the HW structure : boolean if entering d0 or d3 device state