#include "e1000e.h"Go to the source code of this file.
Data Structures | |
| union | ich8_hws_flash_status |
| struct | ich8_hws_flash_status::ich8_hsfsts |
| union | ich8_hws_flash_ctrl |
| struct | ich8_hws_flash_ctrl::ich8_hsflctl |
| union | ich8_hws_flash_regacc |
| struct | ich8_hws_flash_regacc::ich8_flracc |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| static s32 | e1000e_init_phy_params_ich8lan (struct e1000_hw *hw) |
| e1000e_init_phy_params_ich8lan - Initialize PHY function pointers : pointer to the HW structure | |
| static s32 | e1000e_init_phy_params_pchlan (struct e1000_hw *hw) |
| e1000e_init_phy_params_pchlan - Initialize PHY function pointers : pointer to the HW structure | |
| static s32 | e1000e_init_nvm_params_ich8lan (struct e1000_hw *hw) |
| e1000e_init_nvm_params_ich8lan - Initialize NVM function pointers : pointer to the HW structure | |
| static s32 | e1000e_init_mac_params_ich8lan (struct e1000_hw *hw) |
| e1000e_init_mac_params_ich8lan - Initialize MAC function pointers : pointer to the HW structure | |
| static s32 | e1000e_acquire_swflag_ich8lan (struct e1000_hw *hw) |
| e1000e_acquire_swflag_ich8lan - Acquire software control flag : pointer to the HW structure | |
| static void | e1000e_release_swflag_ich8lan (struct e1000_hw *hw) |
| e1000e_release_swflag_ich8lan - Release software control flag : pointer to the HW structure | |
| static s32 | e1000e_acquire_nvm_ich8lan (struct e1000_hw *hw) |
| static void | e1000e_release_nvm_ich8lan (struct e1000_hw *hw) |
| static bool | e1000e_check_mng_mode_ich8lan (struct e1000_hw *hw) |
| e1000e_check_mng_mode_ich8lan - Checks management mode : pointer to the HW structure | |
| static s32 | e1000e_check_reset_block_ich8lan (struct e1000_hw *hw) |
| e1000e_check_reset_block_ich8lan - Check if PHY reset is blocked : pointer to the HW structure | |
| static s32 | e1000e_phy_hw_reset_ich8lan (struct e1000_hw *hw) |
| e1000e_phy_hw_reset_ich8lan - Performs a PHY reset : pointer to the HW structure | |
| static s32 | e1000e_get_phy_info_ich8lan (struct e1000_hw *hw) |
| e1000e_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info : pointer to the HW structure | |
| static s32 | e1000e_set_lplu_state_pchlan (struct e1000_hw *hw, bool active) |
| e1000e_set_lplu_state_pchlan - Set Low Power Link Up state : pointer to the HW structure : true to enable LPLU, false to disable | |
| static s32 | e1000e_set_d0_lplu_state_ich8lan (struct e1000_hw *hw, bool active) |
| e1000e_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state : pointer to the HW structure : true to enable LPLU, false to disable | |
| static s32 | e1000e_set_d3_lplu_state_ich8lan (struct e1000_hw *hw, bool active) |
| e1000e_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state : pointer to the HW structure : true to enable LPLU, false to disable | |
| static s32 | e1000e_read_nvm_ich8lan (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| e1000e_read_nvm_ich8lan - Read word(s) from the NVM : pointer to the HW structure : The offset (in bytes) of the word(s) to read. | |
| static s32 | e1000e_write_nvm_ich8lan (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| e1000e_write_nvm_ich8lan - Write word(s) to the NVM : pointer to the HW structure : The offset (in bytes) of the word(s) to write. | |
| static s32 | e1000e_validate_nvm_checksum_ich8lan (struct e1000_hw *hw) |
| e1000e_validate_nvm_checksum_ich8lan - Validate EEPROM checksum : pointer to the HW structure | |
| static s32 | e1000e_update_nvm_checksum_ich8lan (struct e1000_hw *hw) |
| e1000e_update_nvm_checksum_ich8lan - Update the checksum for NVM : pointer to the HW structure | |
| static s32 | e1000e_valid_led_default_ich8lan (struct e1000_hw *hw, u16 *data) |
| e1000e_valid_led_default_ich8lan - Set the default LED settings : pointer to the HW structure : Pointer to the LED settings | |
| static s32 | e1000e_id_led_init_pchlan (struct e1000_hw *hw) |
| e1000e_id_led_init_pchlan - store LED configurations : pointer to the HW structure | |
| static s32 | e1000e_get_bus_info_ich8lan (struct e1000_hw *hw) |
| e1000e_get_bus_info_ich8lan - Get/Set the bus type and width : pointer to the HW structure | |
| static s32 | e1000e_reset_hw_ich8lan (struct e1000_hw *hw) |
| e1000e_reset_hw_ich8lan - Reset the hardware : pointer to the HW structure | |
| static s32 | e1000e_init_hw_ich8lan (struct e1000_hw *hw) |
| e1000e_init_hw_ich8lan - Initialize the hardware : pointer to the HW structure | |
| static s32 | e1000e_setup_link_ich8lan (struct e1000_hw *hw) |
| e1000e_setup_link_ich8lan - Setup flow control and link settings : pointer to the HW structure | |
| static s32 | e1000e_setup_copper_link_ich8lan (struct e1000_hw *hw) |
| e1000e_setup_copper_link_ich8lan - Configure MAC/PHY interface : pointer to the HW structure | |
| static s32 | e1000e_get_link_up_info_ich8lan (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| e1000e_get_link_up_info_ich8lan - Get current link speed and duplex : pointer to the HW structure : pointer to store current link speed : pointer to store the current link duplex | |
| static s32 | e1000e_cleanup_led_ich8lan (struct e1000_hw *hw) |
| e1000e_cleanup_led_ich8lan - Restore the default LED operation : pointer to the HW structure | |
| static s32 | e1000e_led_on_ich8lan (struct e1000_hw *hw) |
| e1000e_led_on_ich8lan - Turn LEDs on : pointer to the HW structure | |
| static s32 | e1000e_led_off_ich8lan (struct e1000_hw *hw) |
| e1000e_led_off_ich8lan - Turn LEDs off : pointer to the HW structure | |
| static s32 | e1000e_k1_gig_workaround_hv (struct e1000_hw *hw, bool link) |
| e1000e_k1_gig_workaround_hv - K1 Si workaround : pointer to the HW structure link up bool flag | |
| static s32 | e1000e_setup_led_pchlan (struct e1000_hw *hw) |
| e1000e_setup_led_pchlan - Configures SW controllable LED : pointer to the HW structure | |
| static s32 | e1000e_cleanup_led_pchlan (struct e1000_hw *hw) |
| e1000e_cleanup_led_pchlan - Restore the default LED operation : pointer to the HW structure | |
| static s32 | e1000e_led_on_pchlan (struct e1000_hw *hw) |
| e1000e_led_on_pchlan - Turn LEDs on : pointer to the HW structure | |
| static s32 | e1000e_led_off_pchlan (struct e1000_hw *hw) |
| e1000e_led_off_pchlan - Turn LEDs off : pointer to the HW structure | |
| static void | e1000e_clear_hw_cntrs_ich8lan (struct e1000_hw *hw) |
| static s32 | e1000e_erase_flash_bank_ich8lan (struct e1000_hw *hw, u32 bank) |
| e1000e_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM : pointer to the HW structure : 0 for first bank, 1 for second bank, etc. | |
| static s32 | e1000e_flash_cycle_ich8lan (struct e1000_hw *hw, u32 timeout) |
| e1000e_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) : pointer to the HW structure : maximum time to wait for completion | |
| static s32 | e1000e_flash_cycle_init_ich8lan (struct e1000_hw *hw) |
| e1000e_flash_cycle_init_ich8lan - Initialize flash : pointer to the HW structure | |
| static s32 | e1000e_get_phy_info_ife_ich8lan (struct e1000_hw *hw) |
| e1000e_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states : pointer to the HW structure | |
| static void | e1000e_initialize_hw_bits_ich8lan (struct e1000_hw *hw) |
| e1000e_initialize_hw_bits_ich8lan - Initialize required hardware bits : pointer to the HW structure | |
| static s32 | e1000e_kmrn_lock_loss_workaround_ich8lan (struct e1000_hw *hw) |
| e1000e_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround : pointer to the HW structure | |
| static s32 | e1000e_read_flash_byte_ich8lan (struct e1000_hw *hw, u32 offset, u8 *data) |
| e1000e_read_flash_byte_ich8lan - Read byte from flash : pointer to the HW structure : The offset of the byte to read. | |
| static s32 | e1000e_read_flash_data_ich8lan (struct e1000_hw *hw, u32 offset, u8 size, u16 *data) |
| e1000e_read_flash_data_ich8lan - Read byte or word from NVM : pointer to the HW structure : The offset (in bytes) of the byte or word to read. | |
| static s32 | e1000e_read_flash_word_ich8lan (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_flash_word_ich8lan - Read word from flash : pointer to the HW structure : offset to data location : pointer to the location for storing the data | |
| static s32 | e1000e_retry_write_flash_byte_ich8lan (struct e1000_hw *hw, u32 offset, u8 byte) |
| e1000e_retry_write_flash_byte_ich8lan - Writes a single byte to NVM : pointer to the HW structure : The offset of the byte to write. | |
| static s32 | e1000e_write_flash_byte_ich8lan (struct e1000_hw *hw, u32 offset, u8 data) |
| e1000e_write_flash_byte_ich8lan - Write a single byte to NVM : pointer to the HW structure : The index of the byte to read. | |
| static s32 | e1000e_write_flash_data_ich8lan (struct e1000_hw *hw, u32 offset, u8 size, u16 data) |
| e1000e_write_flash_data_ich8lan - Writes bytes to the NVM : pointer to the HW structure : The offset (in bytes) of the byte/word to read. | |
| static s32 | e1000e_get_cfg_done_ich8lan (struct e1000_hw *hw) |
| e1000e_get_cfg_done_ich8lan - Read config done bit : pointer to the HW structure | |
| static void | e1000e_power_down_phy_copper_ich8lan (struct e1000_hw *hw) |
| e1000e_power_down_phy_copper_ich8lan - Remove link during PHY power down : pointer to the HW structure | |
| static s32 | e1000e_check_for_copper_link_ich8lan (struct e1000_hw *hw) |
| e1000e_check_for_copper_link_ich8lan - Check for link (Copper) : pointer to the HW structure | |
| static void | e1000e_lan_init_done_ich8lan (struct e1000_hw *hw) |
| e1000e_lan_init_done_ich8lan - Check for PHY config completion : pointer to the HW structure | |
| static s32 | e1000e_sw_lcd_config_ich8lan (struct e1000_hw *hw) |
| e1000e_sw_lcd_config_ich8lan - SW-based LCD Configuration : pointer to the HW structure | |
| void | e1000e_init_function_pointers_ich8lan (struct e1000_hw *hw) |
| e1000e_init_function_pointers_ich8lan - Initialize ICH8 function pointers : pointer to the HW structure | |
| static s32 | e1000e_acquire_nvm_ich8lan (struct e1000_hw *hw __unused) |
| e1000e_acquire_nvm_ich8lan - Acquire NVM mutex : pointer to the HW structure | |
| static void | e1000e_release_nvm_ich8lan (struct e1000_hw *hw __unused) |
| e1000e_release_nvm_ich8lan - Release NVM mutex : pointer to the HW structure | |
| s32 | e1000e_configure_k1_ich8lan (struct e1000_hw *hw, bool k1_enable) |
| e1000e_configure_k1_ich8lan - Configure K1 power state : pointer to the HW structure : K1 state to configure | |
| s32 | e1000e_oem_bits_config_ich8lan (struct e1000_hw *hw, bool d0_state) |
| e1000e_oem_bits_config_ich8lan - SW-based LCD Configuration : pointer to the HW structure : boolean if entering d0 or d3 device state | |
| static s32 | e1000e_hv_phy_workarounds_ich8lan (struct e1000_hw *hw) |
| e1000e_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be done after every PHY reset. | |
| static s32 | e1000e_valid_nvm_bank_detect_ich8lan (struct e1000_hw *hw, u32 *bank) |
| e1000e_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 : pointer to the HW structure : pointer to the variable that returns the active bank | |
| void | e1000e_set_kmrn_lock_loss_workaround_ich8lan (struct e1000_hw *hw, bool state) |
| e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state : pointer to the HW structure : boolean value used to set the current Kumeran workaround state | |
| void | e1000e_igp3_phy_powerdown_workaround_ich8lan (struct e1000_hw *hw) |
| e1000e_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 : pointer to the HW structure | |
| void | e1000e_gig_downshift_workaround_ich8lan (struct e1000_hw *hw) |
| e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working : pointer to the HW structure | |
| void | e1000e_disable_gig_wol_ich8lan (struct e1000_hw *hw) |
| e1000e_disable_gig_wol_ich8lan - disable gig during WoL : pointer to the HW structure | |
| static void | e1000e_clear_hw_cntrs_ich8lan (struct e1000_hw *hw __unused) |
| e1000e_clear_hw_cntrs_ich8lan - Clear statistical counters : pointer to the HW structure | |
Variables | |
| static struct pci_device_id | e1000e_ich8lan_nics [] |
| struct pci_driver e1000e_ich8lan_driver | __pci_driver |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
e1000e_init_phy_params_ich8lan - Initialize PHY function pointers : pointer to the HW structure
Initialize family-specific PHY parameters and function pointers.
Definition at line 231 of file e1000e_ich8lan.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, AUTONEG_ADVERTISE_SPEED_DEFAULT, e1000_phy_info::autoneg_mask, BME1000_E_PHY_ID, e1000_phy_operations::check_polarity, e1000_phy_operations::check_reset_block, e1000_phy_operations::commit, DBG, E1000_ALL_NOT_GIG, E1000_ERR_PHY, e1000_phy_bm, e1000_phy_ife, e1000_phy_igp_3, e1000_phy_unknown, E1000_SUCCESS, e1000e_acquire_swflag_ich8lan(), e1000e_check_polarity_ife(), e1000e_check_reset_block_ich8lan(), e1000e_determine_phy_address(), e1000e_get_cfg_done_ich8lan(), e1000e_get_phy_id(), e1000e_get_phy_info_ich8lan(), e1000e_get_phy_type_from_id(), e1000e_phy_hw_reset_ich8lan(), e1000e_phy_sw_reset(), e1000e_power_down_phy_copper_ich8lan(), e1000e_power_up_phy_copper(), e1000e_read_phy_reg_bm(), e1000e_read_phy_reg_igp(), e1000e_read_phy_reg_igp_locked(), e1000e_release_swflag_ich8lan(), e1000e_set_d0_lplu_state_ich8lan(), e1000e_set_d3_lplu_state_ich8lan(), e1000e_write_phy_reg_bm(), e1000e_write_phy_reg_igp(), e1000e_write_phy_reg_igp_locked(), e1000_phy_operations::get_cfg_done, e1000_phy_operations::get_info, e1000_phy_info::id, IFE_C_E_PHY_ID, IFE_E_PHY_ID, IFE_PLUS_E_PHY_ID, IGP03E1000_E_PHY_ID, msleep, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_down, e1000_phy_operations::power_up, e1000_phy_operations::read_reg, e1000_phy_operations::read_reg_locked, e1000_phy_operations::release, e1000_phy_operations::reset, e1000_phy_info::reset_delay_us, e1000_phy_operations::set_d0_lplu_state, e1000_phy_operations::set_d3_lplu_state, e1000_phy_info::type, u16, e1000_phy_operations::write_reg, and e1000_phy_operations::write_reg_locked.
Referenced by e1000e_init_function_pointers_ich8lan().
00232 { 00233 struct e1000_phy_info *phy = &hw->phy; 00234 s32 ret_val = E1000_SUCCESS; 00235 u16 i = 0; 00236 00237 phy->addr = 1; 00238 phy->reset_delay_us = 100; 00239 00240 phy->ops.acquire = e1000e_acquire_swflag_ich8lan; 00241 phy->ops.check_polarity = e1000e_check_polarity_ife; 00242 phy->ops.check_reset_block = e1000e_check_reset_block_ich8lan; 00243 #if 0 00244 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_ife; 00245 #endif 00246 #if 0 00247 phy->ops.get_cable_length = e1000e_get_cable_length_igp_2; 00248 #endif 00249 phy->ops.get_cfg_done = e1000e_get_cfg_done_ich8lan; 00250 phy->ops.get_info = e1000e_get_phy_info_ich8lan; 00251 phy->ops.read_reg = e1000e_read_phy_reg_igp; 00252 phy->ops.release = e1000e_release_swflag_ich8lan; 00253 phy->ops.reset = e1000e_phy_hw_reset_ich8lan; 00254 phy->ops.set_d0_lplu_state = e1000e_set_d0_lplu_state_ich8lan; 00255 phy->ops.set_d3_lplu_state = e1000e_set_d3_lplu_state_ich8lan; 00256 phy->ops.write_reg = e1000e_write_phy_reg_igp; 00257 phy->ops.power_up = e1000e_power_up_phy_copper; 00258 phy->ops.power_down = e1000e_power_down_phy_copper_ich8lan; 00259 00260 /* 00261 * We may need to do this twice - once for IGP and if that fails, 00262 * we'll set BM func pointers and try again 00263 */ 00264 ret_val = e1000e_determine_phy_address(hw); 00265 if (ret_val) { 00266 phy->ops.write_reg = e1000e_write_phy_reg_bm; 00267 phy->ops.read_reg = e1000e_read_phy_reg_bm; 00268 ret_val = e1000e_determine_phy_address(hw); 00269 if (ret_val) { 00270 DBG("Cannot determine PHY addr. Erroring out\n"); 00271 goto out; 00272 } 00273 } 00274 00275 phy->id = 0; 00276 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && 00277 (i++ < 100)) { 00278 msleep(1); 00279 ret_val = e1000e_get_phy_id(hw); 00280 if (ret_val) 00281 goto out; 00282 } 00283 00284 /* Verify phy id */ 00285 switch (phy->id) { 00286 case IGP03E1000_E_PHY_ID: 00287 phy->type = e1000_phy_igp_3; 00288 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 00289 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; 00290 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; 00291 break; 00292 case IFE_E_PHY_ID: 00293 case IFE_PLUS_E_PHY_ID: 00294 case IFE_C_E_PHY_ID: 00295 phy->type = e1000_phy_ife; 00296 phy->autoneg_mask = E1000_ALL_NOT_GIG; 00297 break; 00298 case BME1000_E_PHY_ID: 00299 phy->type = e1000_phy_bm; 00300 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 00301 phy->ops.read_reg = e1000e_read_phy_reg_bm; 00302 phy->ops.write_reg = e1000e_write_phy_reg_bm; 00303 phy->ops.commit = e1000e_phy_sw_reset; 00304 break; 00305 default: 00306 ret_val = -E1000_ERR_PHY; 00307 goto out; 00308 } 00309 00310 out: 00311 return ret_val; 00312 }
e1000e_init_phy_params_pchlan - Initialize PHY function pointers : pointer to the HW structure
Initialize family-specific PHY parameters and function pointers.
Definition at line 174 of file e1000e_ich8lan.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, AUTONEG_ADVERTISE_SPEED_DEFAULT, e1000_phy_info::autoneg_mask, e1000_phy_operations::check_polarity, e1000_phy_operations::check_reset_block, e1000_phy_operations::commit, e1000_phy_82577, e1000_phy_unknown, E1000_SUCCESS, e1000e_acquire_swflag_ich8lan(), e1000e_check_polarity_82577(), e1000e_check_polarity_ife(), e1000e_check_reset_block_ich8lan(), e1000e_get_cfg_done_ich8lan(), e1000e_get_phy_id(), e1000e_get_phy_info_82577(), e1000e_get_phy_info_ich8lan(), e1000e_get_phy_type_from_id(), e1000e_phy_hw_reset_ich8lan(), e1000e_phy_sw_reset(), e1000e_power_down_phy_copper_ich8lan(), e1000e_power_up_phy_copper(), e1000e_read_phy_reg_hv(), e1000e_read_phy_reg_hv_locked(), e1000e_release_swflag_ich8lan(), e1000e_set_lplu_state_pchlan(), e1000e_write_phy_reg_hv(), e1000e_write_phy_reg_hv_locked(), e1000_phy_operations::get_cfg_done, e1000_phy_operations::get_info, e1000_phy_info::id, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_down, e1000_phy_operations::power_up, e1000_phy_operations::read_reg, e1000_phy_operations::read_reg_locked, e1000_phy_operations::release, e1000_phy_operations::reset, e1000_phy_info::reset_delay_us, e1000_phy_operations::set_d0_lplu_state, e1000_phy_operations::set_d3_lplu_state, e1000_phy_info::type, e1000_phy_operations::write_reg, and e1000_phy_operations::write_reg_locked.
Referenced by e1000e_init_function_pointers_ich8lan().
00175 { 00176 struct e1000_phy_info *phy = &hw->phy; 00177 s32 ret_val = E1000_SUCCESS; 00178 00179 phy->addr = 1; 00180 phy->reset_delay_us = 100; 00181 00182 phy->ops.acquire = e1000e_acquire_swflag_ich8lan; 00183 phy->ops.check_polarity = e1000e_check_polarity_ife; 00184 phy->ops.check_reset_block = e1000e_check_reset_block_ich8lan; 00185 #if 0 00186 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_ife; 00187 #endif 00188 #if 0 00189 phy->ops.get_cable_length = e1000e_get_cable_length_igp_2; 00190 #endif 00191 phy->ops.get_cfg_done = e1000e_get_cfg_done_ich8lan; 00192 phy->ops.get_info = e1000e_get_phy_info_ich8lan; 00193 phy->ops.read_reg = e1000e_read_phy_reg_hv; 00194 phy->ops.read_reg_locked = e1000e_read_phy_reg_hv_locked; 00195 phy->ops.release = e1000e_release_swflag_ich8lan; 00196 phy->ops.reset = e1000e_phy_hw_reset_ich8lan; 00197 phy->ops.set_d0_lplu_state = e1000e_set_lplu_state_pchlan; 00198 phy->ops.set_d3_lplu_state = e1000e_set_lplu_state_pchlan; 00199 phy->ops.write_reg = e1000e_write_phy_reg_hv; 00200 phy->ops.write_reg_locked = e1000e_write_phy_reg_hv_locked; 00201 phy->ops.power_up = e1000e_power_up_phy_copper; 00202 phy->ops.power_down = e1000e_power_down_phy_copper_ich8lan; 00203 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 00204 00205 phy->id = e1000_phy_unknown; 00206 e1000e_get_phy_id(hw); 00207 phy->type = e1000e_get_phy_type_from_id(phy->id); 00208 00209 if (phy->type == e1000_phy_82577) { 00210 phy->ops.check_polarity = e1000e_check_polarity_82577; 00211 #if 0 00212 phy->ops.force_speed_duplex = 00213 e1000e_phy_force_speed_duplex_82577; 00214 #endif 00215 #if 0 00216 phy->ops.get_cable_length = e1000e_get_cable_length_82577; 00217 #endif 00218 phy->ops.get_info = e1000e_get_phy_info_82577; 00219 phy->ops.commit = e1000e_phy_sw_reset; 00220 } 00221 00222 return ret_val; 00223 }
e1000e_init_nvm_params_ich8lan - Initialize NVM function pointers : pointer to the HW structure
Initialize family-specific NVM parameters and function pointers.
Definition at line 321 of file e1000e_ich8lan.c.
References e1000_nvm_operations::acquire, e1000_hw::dev_spec, E1000_ERR_CONFIG, E1000_ICH8_SHADOW_RAM_WORDS, e1000_nvm_flash_sw, E1000_SUCCESS, e1000e_acquire_nvm_ich8lan(), e1000e_read_nvm_ich8lan(), e1000e_release_nvm_ich8lan(), e1000e_update_nvm_checksum_ich8lan(), e1000e_valid_led_default_ich8lan(), e1000e_validate_nvm_checksum_ich8lan(), e1000e_write_nvm_ich8lan(), e_dbg, er32flash, e1000_hw::flash_address, e1000_nvm_info::flash_bank_size, e1000_nvm_info::flash_base_addr, FLASH_GFPREG_BASE_MASK, FLASH_SECTOR_ADDR_SHIFT, e1000_hw::ich8lan, ICH_FLASH_GFPREG, e1000_shadow_ram::modified, e1000_hw::nvm, e1000_nvm_info::ops, e1000_nvm_operations::read, e1000_nvm_operations::release, e1000_dev_spec_ich8lan::shadow_ram, e1000_nvm_info::type, u16, u32, e1000_nvm_operations::update, e1000_nvm_operations::valid_led_default, e1000_nvm_operations::validate, e1000_shadow_ram::value, e1000_nvm_info::word_size, and e1000_nvm_operations::write.
Referenced by e1000e_init_function_pointers_ich8lan().
00322 { 00323 struct e1000_nvm_info *nvm = &hw->nvm; 00324 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 00325 u32 gfpreg, sector_base_addr, sector_end_addr; 00326 s32 ret_val = E1000_SUCCESS; 00327 u16 i; 00328 00329 /* Can't read flash registers if the register set isn't mapped. */ 00330 if (!hw->flash_address) { 00331 e_dbg("ERROR: Flash registers not mapped\n"); 00332 ret_val = -E1000_ERR_CONFIG; 00333 goto out; 00334 } 00335 00336 nvm->type = e1000_nvm_flash_sw; 00337 00338 gfpreg = er32flash(ICH_FLASH_GFPREG); 00339 00340 /* 00341 * sector_X_addr is a "sector"-aligned address (4096 bytes) 00342 * Add 1 to sector_end_addr since this sector is included in 00343 * the overall size. 00344 */ 00345 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; 00346 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; 00347 00348 /* flash_base_addr is byte-aligned */ 00349 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; 00350 00351 /* 00352 * find total size of the NVM, then cut in half since the total 00353 * size represents two separate NVM banks. 00354 */ 00355 nvm->flash_bank_size = (sector_end_addr - sector_base_addr) 00356 << FLASH_SECTOR_ADDR_SHIFT; 00357 nvm->flash_bank_size /= 2; 00358 /* Adjust to word count */ 00359 nvm->flash_bank_size /= sizeof(u16); 00360 00361 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; 00362 00363 /* Clear shadow ram */ 00364 for (i = 0; i < nvm->word_size; i++) { 00365 dev_spec->shadow_ram[i].modified = false; 00366 dev_spec->shadow_ram[i].value = 0xFFFF; 00367 } 00368 00369 /* Function Pointers */ 00370 nvm->ops.acquire = e1000e_acquire_nvm_ich8lan; 00371 nvm->ops.release = e1000e_release_nvm_ich8lan; 00372 nvm->ops.read = e1000e_read_nvm_ich8lan; 00373 nvm->ops.update = e1000e_update_nvm_checksum_ich8lan; 00374 nvm->ops.valid_led_default = e1000e_valid_led_default_ich8lan; 00375 nvm->ops.validate = e1000e_validate_nvm_checksum_ich8lan; 00376 nvm->ops.write = e1000e_write_nvm_ich8lan; 00377 00378 out: 00379 return ret_val; 00380 }
e1000e_init_mac_params_ich8lan - Initialize MAC function pointers : pointer to the HW structure
Initialize family-specific MAC parameters and function pointers.
Definition at line 389 of file e1000e_ich8lan.c.
References e1000_mac_info::arc_subsystem_valid, e1000_mac_info::asf_firmware_present, e1000_mac_operations::blink_led, e1000_mac_operations::check_for_link, e1000_mac_operations::check_mng_mode, e1000_mac_operations::cleanup_led, e1000_mac_operations::clear_hw_cntrs, e1000_ich10lan, e1000_ich8lan, e1000_ich9lan, E1000_ICH_RAR_ENTRIES, e1000_media_type_copper, e1000_pchlan, E1000_SUCCESS, e1000e_blink_led(), e1000e_check_for_copper_link_ich8lan(), e1000e_check_mng_mode_ich8lan(), e1000e_cleanup_led_ich8lan(), e1000e_cleanup_led_pchlan(), e1000e_clear_hw_cntrs_ich8lan(), e1000e_get_bus_info_ich8lan(), e1000e_get_link_up_info_ich8lan(), e1000e_id_led_init(), e1000e_id_led_init_pchlan(), e1000e_init_hw_ich8lan(), e1000e_led_off_ich8lan(), e1000e_led_off_pchlan(), e1000e_led_on_ich8lan(), e1000e_led_on_pchlan(), e1000e_mta_set_generic(), e1000e_reset_hw_ich8lan(), e1000e_set_kmrn_lock_loss_workaround_ich8lan(), e1000e_set_lan_id_single_port(), e1000e_setup_copper_link_ich8lan(), e1000e_setup_led_generic(), e1000e_setup_led_pchlan(), e1000e_setup_link_ich8lan(), e1000e_update_mc_addr_list_generic(), e1000_mac_operations::get_bus_info, e1000_mac_operations::get_link_up_info, e1000_mac_operations::id_led_init, e1000_mac_operations::init_hw, e1000_mac_operations::led_off, e1000_mac_operations::led_on, e1000_hw::mac, e1000_phy_info::media_type, e1000_mac_info::mta_reg_count, e1000_mac_operations::mta_set, e1000_mac_info::ops, e1000_hw::phy, e1000_mac_info::rar_entry_count, e1000_mac_operations::reset_hw, e1000_mac_operations::set_lan_id, e1000_mac_operations::setup_led, e1000_mac_operations::setup_link, e1000_mac_operations::setup_physical_interface, e1000_mac_info::type, and e1000_mac_operations::update_mc_addr_list.
Referenced by e1000e_init_function_pointers_ich8lan().
00390 { 00391 struct e1000_mac_info *mac = &hw->mac; 00392 00393 /* Set media type function pointer */ 00394 hw->phy.media_type = e1000_media_type_copper; 00395 00396 /* Set mta register count */ 00397 mac->mta_reg_count = 32; 00398 /* Set rar entry count */ 00399 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; 00400 if (mac->type == e1000_ich8lan) 00401 mac->rar_entry_count--; 00402 /* Set if part includes ASF firmware */ 00403 mac->asf_firmware_present = true; 00404 /* Set if manageability features are enabled. */ 00405 mac->arc_subsystem_valid = true; 00406 00407 /* Function pointers */ 00408 00409 /* bus type/speed/width */ 00410 mac->ops.get_bus_info = e1000e_get_bus_info_ich8lan; 00411 /* function id */ 00412 mac->ops.set_lan_id = e1000e_set_lan_id_single_port; 00413 /* reset */ 00414 mac->ops.reset_hw = e1000e_reset_hw_ich8lan; 00415 /* hw initialization */ 00416 mac->ops.init_hw = e1000e_init_hw_ich8lan; 00417 /* link setup */ 00418 mac->ops.setup_link = e1000e_setup_link_ich8lan; 00419 /* physical interface setup */ 00420 mac->ops.setup_physical_interface = e1000e_setup_copper_link_ich8lan; 00421 /* check for link */ 00422 mac->ops.check_for_link = e1000e_check_for_copper_link_ich8lan; 00423 /* check management mode */ 00424 mac->ops.check_mng_mode = e1000e_check_mng_mode_ich8lan; 00425 /* link info */ 00426 mac->ops.get_link_up_info = e1000e_get_link_up_info_ich8lan; 00427 /* multicast address update */ 00428 mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic; 00429 /* setting MTA */ 00430 mac->ops.mta_set = e1000e_mta_set_generic; 00431 /* clear hardware counters */ 00432 mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_ich8lan; 00433 00434 /* LED operations */ 00435 switch (mac->type) { 00436 case e1000_ich8lan: 00437 case e1000_ich9lan: 00438 case e1000_ich10lan: 00439 /* ID LED init */ 00440 mac->ops.id_led_init = e1000e_id_led_init; 00441 /* blink LED */ 00442 mac->ops.blink_led = e1000e_blink_led; 00443 /* setup LED */ 00444 mac->ops.setup_led = e1000e_setup_led_generic; 00445 /* cleanup LED */ 00446 mac->ops.cleanup_led = e1000e_cleanup_led_ich8lan; 00447 /* turn on/off LED */ 00448 mac->ops.led_on = e1000e_led_on_ich8lan; 00449 mac->ops.led_off = e1000e_led_off_ich8lan; 00450 break; 00451 case e1000_pchlan: 00452 /* ID LED init */ 00453 mac->ops.id_led_init = e1000e_id_led_init_pchlan; 00454 /* setup LED */ 00455 mac->ops.setup_led = e1000e_setup_led_pchlan; 00456 /* cleanup LED */ 00457 mac->ops.cleanup_led = e1000e_cleanup_led_pchlan; 00458 /* turn on/off LED */ 00459 mac->ops.led_on = e1000e_led_on_pchlan; 00460 mac->ops.led_off = e1000e_led_off_pchlan; 00461 break; 00462 default: 00463 break; 00464 } 00465 00466 /* Enable PCS Lock-loss workaround for ICH8 */ 00467 if (mac->type == e1000_ich8lan) 00468 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); 00469 00470 00471 return E1000_SUCCESS; 00472 }
e1000e_acquire_swflag_ich8lan - Acquire software control flag : pointer to the HW structure
Acquires the software control flag for performing PHY and select MAC CSR accesses.
Definition at line 630 of file e1000e_ich8lan.c.
References E1000_ERR_CONFIG, E1000_EXTCNF_CTRL_SWFLAG, E1000_SUCCESS, e_dbg, er32, ew32, mdelay(), PHY_CFG_TIMEOUT, SW_FLAG_TIMEOUT, timeout(), and u32.
Referenced by e1000e_init_phy_params_ich8lan(), e1000e_init_phy_params_pchlan(), and e1000e_reset_hw_ich8lan().
00631 { 00632 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; 00633 s32 ret_val = E1000_SUCCESS; 00634 00635 #if 0 00636 mutex_lock(&swflag_mutex); 00637 #endif 00638 00639 while (timeout) { 00640 extcnf_ctrl = er32(EXTCNF_CTRL); 00641 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) 00642 break; 00643 00644 mdelay(1); 00645 timeout--; 00646 } 00647 00648 if (!timeout) { 00649 e_dbg("SW/FW/HW has locked the resource for too long.\n"); 00650 ret_val = -E1000_ERR_CONFIG; 00651 goto out; 00652 } 00653 00654 timeout = SW_FLAG_TIMEOUT; 00655 00656 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; 00657 ew32(EXTCNF_CTRL, extcnf_ctrl); 00658 00659 while (timeout) { 00660 extcnf_ctrl = er32(EXTCNF_CTRL); 00661 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) 00662 break; 00663 00664 mdelay(1); 00665 timeout--; 00666 } 00667 00668 if (!timeout) { 00669 e_dbg("Failed to acquire the semaphore.\n"); 00670 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 00671 ew32(EXTCNF_CTRL, extcnf_ctrl); 00672 ret_val = -E1000_ERR_CONFIG; 00673 goto out; 00674 } 00675 00676 out: 00677 #if 0 00678 if (ret_val) 00679 mutex_unlock(&swflag_mutex); 00680 #endif 00681 return ret_val; 00682 }
| static void e1000e_release_swflag_ich8lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_release_swflag_ich8lan - Release software control flag : pointer to the HW structure
Releases the software control flag for performing PHY and select MAC CSR accesses.
Definition at line 691 of file e1000e_ich8lan.c.
References E1000_EXTCNF_CTRL_SWFLAG, er32, ew32, and u32.
Referenced by e1000e_init_phy_params_ich8lan(), e1000e_init_phy_params_pchlan(), and e1000e_reset_hw_ich8lan().
00692 { 00693 u32 extcnf_ctrl; 00694 00695 extcnf_ctrl = er32(EXTCNF_CTRL); 00696 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; 00697 ew32(EXTCNF_CTRL, extcnf_ctrl); 00698 00699 #if 0 00700 mutex_unlock(&swflag_mutex); 00701 #endif 00702 return; 00703 }
Referenced by e1000e_init_nvm_params_ich8lan().
| static void e1000e_release_nvm_ich8lan | ( | struct e1000_hw * | hw | ) | [static] |
Referenced by e1000e_init_nvm_params_ich8lan().
e1000e_check_mng_mode_ich8lan - Checks management mode : pointer to the HW structure
This checks if the adapter has manageability enabled. This is a function pointer entry point only called by read/write routines for the PHY and NVM parts.
Definition at line 713 of file e1000e_ich8lan.c.
References E1000_FWSM_MODE_MASK, E1000_FWSM_MODE_SHIFT, E1000_ICH_MNG_IAMT_MODE, er32, and u32.
Referenced by e1000e_init_mac_params_ich8lan().
00714 { 00715 u32 fwsm; 00716 00717 fwsm = er32(FWSM); 00718 return (fwsm & E1000_FWSM_MODE_MASK) == 00719 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT); 00720 }
e1000e_check_reset_block_ich8lan - Check if PHY reset is blocked : pointer to the HW structure
Checks if firmware is blocking the reset of the PHY. This is a function pointer entry point only called by reset routines.
Definition at line 729 of file e1000e_ich8lan.c.
References E1000_BLK_PHY_RESET, E1000_ICH_FWSM_RSPCIPHY, E1000_SUCCESS, er32, and u32.
Referenced by e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
00730 { 00731 u32 fwsm; 00732 00733 fwsm = er32(FWSM); 00734 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? E1000_SUCCESS 00735 : E1000_BLK_PHY_RESET; 00736 }
e1000e_phy_hw_reset_ich8lan - Performs a PHY reset : pointer to the HW structure
Resets the PHY This is a function pointer entry point called by drivers or other shared routines.
Definition at line 1154 of file e1000e_ich8lan.c.
References BM_WUC, e1000_pchlan, E1000_SUCCESS, e1000e_hv_phy_workarounds_ich8lan(), e1000e_oem_bits_config_ich8lan(), e1000e_phy_hw_reset_generic(), e1000e_sw_lcd_config_ich8lan(), e1e_rphy(), e1000_hw::mac, msleep, e1000_mac_info::type, and u16.
Referenced by e1000e_disable_gig_wol_ich8lan(), e1000e_init_hw_ich8lan(), e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
01155 { 01156 s32 ret_val = E1000_SUCCESS; 01157 u16 reg; 01158 01159 ret_val = e1000e_phy_hw_reset_generic(hw); 01160 if (ret_val) 01161 goto out; 01162 01163 /* Allow time for h/w to get to a quiescent state after reset */ 01164 msleep(10); 01165 01166 if (hw->mac.type == e1000_pchlan) { 01167 ret_val = e1000e_hv_phy_workarounds_ich8lan(hw); 01168 if (ret_val) 01169 goto out; 01170 } 01171 01172 /* Dummy read to clear the phy wakeup bit after lcd reset */ 01173 if (hw->mac.type == e1000_pchlan) 01174 e1e_rphy(hw, BM_WUC, ®); 01175 01176 /* Configure the LCD with the extended configuration region in NVM */ 01177 ret_val = e1000e_sw_lcd_config_ich8lan(hw); 01178 if (ret_val) 01179 goto out; 01180 01181 /* Configure the LCD with the OEM bits in NVM */ 01182 if (hw->mac.type == e1000_pchlan) 01183 ret_val = e1000e_oem_bits_config_ich8lan(hw, true); 01184 01185 out: 01186 return ret_val; 01187 }
e1000e_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info : pointer to the HW structure
Wrapper for calling the get_phy_info routines for the appropriate phy type.
Definition at line 1195 of file e1000e_ich8lan.c.
References E1000_ERR_PHY_TYPE, e1000_phy_82577, e1000_phy_82578, e1000_phy_bm, e1000_phy_ife, e1000_phy_igp_3, e1000e_get_phy_info_ife_ich8lan(), e1000e_get_phy_info_igp(), e1000_hw::phy, and e1000_phy_info::type.
Referenced by e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
01196 { 01197 s32 ret_val = -E1000_ERR_PHY_TYPE; 01198 01199 switch (hw->phy.type) { 01200 case e1000_phy_ife: 01201 ret_val = e1000e_get_phy_info_ife_ich8lan(hw); 01202 break; 01203 case e1000_phy_igp_3: 01204 case e1000_phy_bm: 01205 case e1000_phy_82578: 01206 case e1000_phy_82577: 01207 ret_val = e1000e_get_phy_info_igp(hw); 01208 break; 01209 default: 01210 break; 01211 } 01212 01213 return ret_val; 01214 }
e1000e_set_lplu_state_pchlan - Set Low Power Link Up state : pointer to the HW structure : true to enable LPLU, false to disable
Sets the LPLU state according to the active flag. For PCH, if OEM write bit are disabled in the NVM, writing the LPLU bits in the MAC will not set the phy speed. This function will manually set the LPLU bit and restart auto-neg as hw would do. D3 and D0 LPLU will call the same function since it configures the same bit.
Definition at line 1284 of file e1000e_ich8lan.c.
References E1000_SUCCESS, e1e_rphy(), e1e_wphy(), HV_OEM_BITS, HV_OEM_BITS_LPLU, HV_OEM_BITS_RESTART_AN, and u16.
Referenced by e1000e_init_phy_params_pchlan().
01285 { 01286 s32 ret_val = E1000_SUCCESS; 01287 u16 oem_reg; 01288 01289 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); 01290 if (ret_val) 01291 goto out; 01292 01293 if (active) 01294 oem_reg |= HV_OEM_BITS_LPLU; 01295 else 01296 oem_reg &= ~HV_OEM_BITS_LPLU; 01297 01298 oem_reg |= HV_OEM_BITS_RESTART_AN; 01299 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg); 01300 01301 out: 01302 return ret_val; 01303 }
e1000e_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state : pointer to the HW structure : true to enable LPLU, false to disable
Sets the LPLU D0 state according to the active flag. When activating LPLU this function also disables smart speed and vice versa. LPLU will not be activated unless the device autonegotiation advertisement meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function pointer entry point only called by PHY setup routines.
Definition at line 1318 of file e1000e_ich8lan.c.
References e1000_ich8lan, E1000_PHY_CTRL_D0A_LPLU, e1000_phy_ife, e1000_phy_igp_3, e1000_smart_speed_off, e1000_smart_speed_on, E1000_SUCCESS, e1000e_gig_downshift_workaround_ich8lan(), e1e_rphy(), e1e_wphy(), er32, ew32, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PSCFR_SMART_SPEED, e1000_hw::mac, e1000_hw::phy, e1000_phy_info::smart_speed, e1000_mac_info::type, e1000_phy_info::type, u16, and u32.
Referenced by e1000e_init_phy_params_ich8lan().
01319 { 01320 struct e1000_phy_info *phy = &hw->phy; 01321 u32 phy_ctrl; 01322 s32 ret_val = E1000_SUCCESS; 01323 u16 data; 01324 01325 if (phy->type == e1000_phy_ife) 01326 goto out; 01327 01328 phy_ctrl = er32(PHY_CTRL); 01329 01330 if (active) { 01331 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; 01332 ew32(PHY_CTRL, phy_ctrl); 01333 01334 if (phy->type != e1000_phy_igp_3) 01335 goto out; 01336 01337 /* 01338 * Call gig speed drop workaround on LPLU before accessing 01339 * any PHY registers 01340 */ 01341 if (hw->mac.type == e1000_ich8lan) 01342 e1000e_gig_downshift_workaround_ich8lan(hw); 01343 01344 /* When LPLU is enabled, we should disable SmartSpeed */ 01345 ret_val = e1e_rphy(hw, 01346 IGP01E1000_PHY_PORT_CONFIG, 01347 &data); 01348 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01349 ret_val = e1e_wphy(hw, 01350 IGP01E1000_PHY_PORT_CONFIG, 01351 data); 01352 if (ret_val) 01353 goto out; 01354 } else { 01355 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; 01356 ew32(PHY_CTRL, phy_ctrl); 01357 01358 if (phy->type != e1000_phy_igp_3) 01359 goto out; 01360 01361 /* 01362 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 01363 * during Dx states where the power conservation is most 01364 * important. During driver activity we should enable 01365 * SmartSpeed, so performance is maintained. 01366 */ 01367 if (phy->smart_speed == e1000_smart_speed_on) { 01368 ret_val = e1e_rphy(hw, 01369 IGP01E1000_PHY_PORT_CONFIG, 01370 &data); 01371 if (ret_val) 01372 goto out; 01373 01374 data |= IGP01E1000_PSCFR_SMART_SPEED; 01375 ret_val = e1e_wphy(hw, 01376 IGP01E1000_PHY_PORT_CONFIG, 01377 data); 01378 if (ret_val) 01379 goto out; 01380 } else if (phy->smart_speed == e1000_smart_speed_off) { 01381 ret_val = e1e_rphy(hw, 01382 IGP01E1000_PHY_PORT_CONFIG, 01383 &data); 01384 if (ret_val) 01385 goto out; 01386 01387 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01388 ret_val = e1e_wphy(hw, 01389 IGP01E1000_PHY_PORT_CONFIG, 01390 data); 01391 if (ret_val) 01392 goto out; 01393 } 01394 } 01395 01396 out: 01397 return ret_val; 01398 }
e1000e_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state : pointer to the HW structure : true to enable LPLU, false to disable
Sets the LPLU D3 state according to the active flag. When activating LPLU this function also disables smart speed and vice versa. LPLU will not be activated unless the device autonegotiation advertisement meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function pointer entry point only called by PHY setup routines.
Definition at line 1413 of file e1000e_ich8lan.c.
References e1000_phy_info::autoneg_advertised, E1000_ALL_10_SPEED, E1000_ALL_NOT_GIG, E1000_ALL_SPEED_DUPLEX, e1000_ich8lan, E1000_PHY_CTRL_NOND0A_LPLU, e1000_phy_igp_3, e1000_smart_speed_off, e1000_smart_speed_on, E1000_SUCCESS, e1000e_gig_downshift_workaround_ich8lan(), e1e_rphy(), e1e_wphy(), er32, ew32, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PSCFR_SMART_SPEED, e1000_hw::mac, e1000_hw::phy, e1000_phy_info::smart_speed, e1000_mac_info::type, e1000_phy_info::type, u16, and u32.
Referenced by e1000e_init_phy_params_ich8lan().
01414 { 01415 struct e1000_phy_info *phy = &hw->phy; 01416 u32 phy_ctrl; 01417 s32 ret_val = E1000_SUCCESS; 01418 u16 data; 01419 01420 phy_ctrl = er32(PHY_CTRL); 01421 01422 if (!active) { 01423 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; 01424 ew32(PHY_CTRL, phy_ctrl); 01425 01426 if (phy->type != e1000_phy_igp_3) 01427 goto out; 01428 01429 /* 01430 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 01431 * during Dx states where the power conservation is most 01432 * important. During driver activity we should enable 01433 * SmartSpeed, so performance is maintained. 01434 */ 01435 if (phy->smart_speed == e1000_smart_speed_on) { 01436 ret_val = e1e_rphy(hw, 01437 IGP01E1000_PHY_PORT_CONFIG, 01438 &data); 01439 if (ret_val) 01440 goto out; 01441 01442 data |= IGP01E1000_PSCFR_SMART_SPEED; 01443 ret_val = e1e_wphy(hw, 01444 IGP01E1000_PHY_PORT_CONFIG, 01445 data); 01446 if (ret_val) 01447 goto out; 01448 } else if (phy->smart_speed == e1000_smart_speed_off) { 01449 ret_val = e1e_rphy(hw, 01450 IGP01E1000_PHY_PORT_CONFIG, 01451 &data); 01452 if (ret_val) 01453 goto out; 01454 01455 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01456 ret_val = e1e_wphy(hw, 01457 IGP01E1000_PHY_PORT_CONFIG, 01458 data); 01459 if (ret_val) 01460 goto out; 01461 } 01462 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 01463 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 01464 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 01465 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; 01466 ew32(PHY_CTRL, phy_ctrl); 01467 01468 if (phy->type != e1000_phy_igp_3) 01469 goto out; 01470 01471 /* 01472 * Call gig speed drop workaround on LPLU before accessing 01473 * any PHY registers 01474 */ 01475 if (hw->mac.type == e1000_ich8lan) 01476 e1000e_gig_downshift_workaround_ich8lan(hw); 01477 01478 /* When LPLU is enabled, we should disable SmartSpeed */ 01479 ret_val = e1e_rphy(hw, 01480 IGP01E1000_PHY_PORT_CONFIG, 01481 &data); 01482 if (ret_val) 01483 goto out; 01484 01485 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01486 ret_val = e1e_wphy(hw, 01487 IGP01E1000_PHY_PORT_CONFIG, 01488 data); 01489 } 01490 01491 out: 01492 return ret_val; 01493 }
| static s32 e1000e_read_nvm_ich8lan | ( | struct e1000_hw * | hw, | |
| u16 | offset, | |||
| u16 | words, | |||
| u16 * | data | |||
| ) | [static] |
e1000e_read_nvm_ich8lan - Read word(s) from the NVM : pointer to the HW structure : The offset (in bytes) of the word(s) to read.
: Size of data to read in words : Pointer to the word(s) to read at offset.
Reads a word(s) from the NVM using the flash access registers.
Definition at line 1572 of file e1000e_ich8lan.c.
References e1000_nvm_operations::acquire, e1000_hw::dev_spec, E1000_ERR_NVM, E1000_SUCCESS, e1000e_read_flash_word_ich8lan(), e1000e_valid_nvm_bank_detect_ich8lan(), e_dbg, e1000_nvm_info::flash_bank_size, e1000_hw::ich8lan, e1000_shadow_ram::modified, e1000_hw::nvm, e1000_nvm_info::ops, e1000_nvm_operations::release, e1000_dev_spec_ich8lan::shadow_ram, u16, u32, e1000_shadow_ram::value, and e1000_nvm_info::word_size.
Referenced by e1000e_init_nvm_params_ich8lan().
01574 { 01575 struct e1000_nvm_info *nvm = &hw->nvm; 01576 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 01577 u32 act_offset; 01578 s32 ret_val = E1000_SUCCESS; 01579 u32 bank = 0; 01580 u16 i, word; 01581 01582 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 01583 (words == 0)) { 01584 e_dbg("nvm parameter(s) out of bounds\n"); 01585 ret_val = -E1000_ERR_NVM; 01586 goto out; 01587 } 01588 01589 nvm->ops.acquire(hw); 01590 01591 ret_val = e1000e_valid_nvm_bank_detect_ich8lan(hw, &bank); 01592 if (ret_val != E1000_SUCCESS) { 01593 e_dbg("Could not detect valid bank, assuming bank 0\n"); 01594 bank = 0; 01595 } 01596 01597 act_offset = (bank) ? nvm->flash_bank_size : 0; 01598 act_offset += offset; 01599 01600 ret_val = E1000_SUCCESS; 01601 for (i = 0; i < words; i++) { 01602 if ((dev_spec->shadow_ram) && 01603 (dev_spec->shadow_ram[offset+i].modified)) { 01604 data[i] = dev_spec->shadow_ram[offset+i].value; 01605 } else { 01606 ret_val = e1000e_read_flash_word_ich8lan(hw, 01607 act_offset + i, 01608 &word); 01609 if (ret_val) 01610 break; 01611 data[i] = word; 01612 } 01613 } 01614 01615 nvm->ops.release(hw); 01616 01617 out: 01618 if (ret_val) 01619 e_dbg("NVM read error: %d\n", ret_val); 01620 01621 return ret_val; 01622 }
| static s32 e1000e_write_nvm_ich8lan | ( | struct e1000_hw * | hw, | |
| u16 | offset, | |||
| u16 | words, | |||
| u16 * | data | |||
| ) | [static] |
e1000e_write_nvm_ich8lan - Write word(s) to the NVM : pointer to the HW structure : The offset (in bytes) of the word(s) to write.
: Size of data to write in words : Pointer to the word(s) to write at offset.
Writes a byte or word to the NVM using the flash access registers.
Definition at line 1874 of file e1000e_ich8lan.c.
References e1000_nvm_operations::acquire, e1000_hw::dev_spec, E1000_ERR_NVM, E1000_SUCCESS, e_dbg, e1000_hw::ich8lan, e1000_shadow_ram::modified, e1000_hw::nvm, e1000_nvm_info::ops, e1000_nvm_operations::release, e1000_dev_spec_ich8lan::shadow_ram, u16, e1000_shadow_ram::value, and e1000_nvm_info::word_size.
Referenced by e1000e_init_nvm_params_ich8lan().
01876 { 01877 struct e1000_nvm_info *nvm = &hw->nvm; 01878 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 01879 s32 ret_val = E1000_SUCCESS; 01880 u16 i; 01881 01882 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || 01883 (words == 0)) { 01884 e_dbg("nvm parameter(s) out of bounds\n"); 01885 ret_val = -E1000_ERR_NVM; 01886 goto out; 01887 } 01888 01889 nvm->ops.acquire(hw); 01890 01891 for (i = 0; i < words; i++) { 01892 dev_spec->shadow_ram[offset+i].modified = true; 01893 dev_spec->shadow_ram[offset+i].value = data[i]; 01894 } 01895 01896 nvm->ops.release(hw); 01897 01898 out: 01899 return ret_val; 01900 }
e1000e_validate_nvm_checksum_ich8lan - Validate EEPROM checksum : pointer to the HW structure
Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. If the bit is 0, that the EEPROM had been modified, but the checksum was not calculated, in which case we need to calculate the checksum and set bit 6.
Definition at line 2080 of file e1000e_ich8lan.c.
References E1000_SUCCESS, e1000e_read_nvm(), e1000e_update_nvm_checksum(), e1000e_validate_nvm_checksum_generic(), e1000e_write_nvm(), and u16.
Referenced by e1000e_init_nvm_params_ich8lan().
02081 { 02082 s32 ret_val = E1000_SUCCESS; 02083 u16 data; 02084 02085 /* 02086 * Read 0x19 and check bit 6. If this bit is 0, the checksum 02087 * needs to be fixed. This bit is an indication that the NVM 02088 * was prepared by OEM software and did not calculate the 02089 * checksum...a likely scenario. 02090 */ 02091 ret_val = e1000e_read_nvm(hw, 0x19, 1, &data); 02092 if (ret_val) 02093 goto out; 02094 02095 if ((data & 0x40) == 0) { 02096 data |= 0x40; 02097 ret_val = e1000e_write_nvm(hw, 0x19, 1, &data); 02098 if (ret_val) 02099 goto out; 02100 ret_val = e1000e_update_nvm_checksum(hw); 02101 if (ret_val) 02102 goto out; 02103 } 02104 02105 ret_val = e1000e_validate_nvm_checksum_generic(hw); 02106 02107 out: 02108 return ret_val; 02109 }
e1000e_update_nvm_checksum_ich8lan - Update the checksum for NVM : pointer to the HW structure
The NVM checksum is updated by calling the generic update_nvm_checksum, which writes the checksum to the shadow ram. The changes in the shadow ram are then committed to the EEPROM by processing each bank at a time checking for the modified bit and writing only the pending changes. After a successful commit, the shadow ram is cleared and is ready for future writes.
Definition at line 1913 of file e1000e_ich8lan.c.
References e1000_nvm_operations::acquire, e1000_hw::dev_spec, E1000_ICH8_SHADOW_RAM_WORDS, E1000_ICH_NVM_SIG_MASK, E1000_ICH_NVM_SIG_WORD, e1000_nvm_flash_sw, E1000_SUCCESS, e1000e_erase_flash_bank_ich8lan(), e1000e_read_flash_word_ich8lan(), e1000e_retry_write_flash_byte_ich8lan(), e1000e_update_nvm_checksum_generic(), e1000e_valid_nvm_bank_detect_ich8lan(), e_dbg, e1000_nvm_info::flash_bank_size, e1000_hw::ich8lan, e1000_shadow_ram::modified, msleep, e1000_hw::nvm, e1000_nvm_info::ops, e1000_nvm_operations::release, e1000_nvm_operations::reload, e1000_dev_spec_ich8lan::shadow_ram, e1000_nvm_info::type, u16, u32, u8, udelay(), and e1000_shadow_ram::value.
Referenced by e1000e_init_nvm_params_ich8lan().
01914 { 01915 struct e1000_nvm_info *nvm = &hw->nvm; 01916 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 01917 u32 i, act_offset, new_bank_offset, old_bank_offset, bank; 01918 s32 ret_val; 01919 u16 data; 01920 01921 ret_val = e1000e_update_nvm_checksum_generic(hw); 01922 if (ret_val) 01923 goto out; 01924 01925 if (nvm->type != e1000_nvm_flash_sw) 01926 goto out; 01927 01928 nvm->ops.acquire(hw); 01929 01930 /* 01931 * We're writing to the opposite bank so if we're on bank 1, 01932 * write to bank 0 etc. We also need to erase the segment that 01933 * is going to be written 01934 */ 01935 ret_val = e1000e_valid_nvm_bank_detect_ich8lan(hw, &bank); 01936 if (ret_val != E1000_SUCCESS) { 01937 e_dbg("Could not detect valid bank, assuming bank 0\n"); 01938 bank = 0; 01939 } 01940 01941 if (bank == 0) { 01942 new_bank_offset = nvm->flash_bank_size; 01943 old_bank_offset = 0; 01944 ret_val = e1000e_erase_flash_bank_ich8lan(hw, 1); 01945 if (ret_val) { 01946 nvm->ops.release(hw); 01947 goto out; 01948 } 01949 } else { 01950 old_bank_offset = nvm->flash_bank_size; 01951 new_bank_offset = 0; 01952 ret_val = e1000e_erase_flash_bank_ich8lan(hw, 0); 01953 if (ret_val) { 01954 nvm->ops.release(hw); 01955 goto out; 01956 } 01957 } 01958 01959 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 01960 /* 01961 * Determine whether to write the value stored 01962 * in the other NVM bank or a modified value stored 01963 * in the shadow RAM 01964 */ 01965 if (dev_spec->shadow_ram[i].modified) { 01966 data = dev_spec->shadow_ram[i].value; 01967 } else { 01968 ret_val = e1000e_read_flash_word_ich8lan(hw, i + 01969 old_bank_offset, 01970 &data); 01971 if (ret_val) 01972 break; 01973 } 01974 01975 /* 01976 * If the word is 0x13, then make sure the signature bits 01977 * (15:14) are 11b until the commit has completed. 01978 * This will allow us to write 10b which indicates the 01979 * signature is valid. We want to do this after the write 01980 * has completed so that we don't mark the segment valid 01981 * while the write is still in progress 01982 */ 01983 if (i == E1000_ICH_NVM_SIG_WORD) 01984 data |= E1000_ICH_NVM_SIG_MASK; 01985 01986 /* Convert offset to bytes. */ 01987 act_offset = (i + new_bank_offset) << 1; 01988 01989 udelay(100); 01990 /* Write the bytes to the new bank. */ 01991 ret_val = e1000e_retry_write_flash_byte_ich8lan(hw, 01992 act_offset, 01993 (u8)data); 01994 if (ret_val) 01995 break; 01996 01997 udelay(100); 01998 ret_val = e1000e_retry_write_flash_byte_ich8lan(hw, 01999 act_offset + 1, 02000 (u8)(data >> 8)); 02001 if (ret_val) 02002 break; 02003 } 02004 02005 /* 02006 * Don't bother writing the segment valid bits if sector 02007 * programming failed. 02008 */ 02009 if (ret_val) { 02010 e_dbg("Flash commit failed.\n"); 02011 nvm->ops.release(hw); 02012 goto out; 02013 } 02014 02015 /* 02016 * Finally validate the new segment by setting bit 15:14 02017 * to 10b in word 0x13 , this can be done without an 02018 * erase as well since these bits are 11 to start with 02019 * and we need to change bit 14 to 0b 02020 */ 02021 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; 02022 ret_val = e1000e_read_flash_word_ich8lan(hw, act_offset, &data); 02023 if (ret_val) { 02024 nvm->ops.release(hw); 02025 goto out; 02026 } 02027 02028 data &= 0xBFFF; 02029 ret_val = e1000e_retry_write_flash_byte_ich8lan(hw, 02030 act_offset * 2 + 1, 02031 (u8)(data >> 8)); 02032 if (ret_val) { 02033 nvm->ops.release(hw); 02034 goto out; 02035 } 02036 02037 /* 02038 * And invalidate the previously valid segment by setting 02039 * its signature word (0x13) high_byte to 0b. This can be 02040 * done without an erase because flash erase sets all bits 02041 * to 1's. We can write 1's to 0's without an erase 02042 */ 02043 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; 02044 ret_val = e1000e_retry_write_flash_byte_ich8lan(hw, act_offset, 0); 02045 if (ret_val) { 02046 nvm->ops.release(hw); 02047 goto out; 02048 } 02049 02050 /* Great! Everything worked, we can now clear the cached entries. */ 02051 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { 02052 dev_spec->shadow_ram[i].modified = false; 02053 dev_spec->shadow_ram[i].value = 0xFFFF; 02054 } 02055 02056 nvm->ops.release(hw); 02057 02058 /* 02059 * Reload the EEPROM, or else modifications will not appear 02060 * until after the next adapter reset. 02061 */ 02062 nvm->ops.reload(hw); 02063 msleep(10); 02064 02065 out: 02066 if (ret_val) 02067 e_dbg("NVM update error: %d\n", ret_val); 02068 02069 return ret_val; 02070 }
e1000e_valid_led_default_ich8lan - Set the default LED settings : pointer to the HW structure : Pointer to the LED settings
Reads the LED default settings from the NVM to data. If the NVM LED settings is all 0's or F's, set the LED default to a valid LED default setting.
Definition at line 2361 of file e1000e_ich8lan.c.
References e1000e_read_nvm(), e_dbg, ID_LED_DEFAULT_ICH8LAN, ID_LED_RESERVED_0000, ID_LED_RESERVED_FFFF, and NVM_ID_LED_SETTINGS.
Referenced by e1000e_init_nvm_params_ich8lan().
02362 { 02363 s32 ret_val; 02364 02365 ret_val = e1000e_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 02366 if (ret_val) { 02367 e_dbg("NVM Read Error\n"); 02368 goto out; 02369 } 02370 02371 if (*data == ID_LED_RESERVED_0000 || 02372 *data == ID_LED_RESERVED_FFFF) 02373 *data = ID_LED_DEFAULT_ICH8LAN; 02374 02375 out: 02376 return ret_val; 02377 }
e1000e_id_led_init_pchlan - store LED configurations : pointer to the HW structure
PCH does not control LEDs via the LEDCTL register, rather it uses the PHY LED configuration register.
PCH also does not have an "always on" or "always off" mode which complicates the ID feature. Instead of using the "on" mode to indicate in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()), use "link_up" mode. The LEDs will still ID on request if there is no link based on logic in e1000e_led_[on|off]_pchlan().
Definition at line 2392 of file e1000e_ich8lan.c.
References E1000_LEDCTL_LED0_MODE_MASK, E1000_LEDCTL_MODE_LINK_UP, E1000_PHY_LED0_IVRT, E1000_PHY_LED0_MASK, er32, ID_LED_DEF1_OFF2, ID_LED_DEF1_ON2, ID_LED_OFF1_DEF2, ID_LED_OFF1_OFF2, ID_LED_OFF1_ON2, ID_LED_ON1_DEF2, ID_LED_ON1_OFF2, ID_LED_ON1_ON2, e1000_mac_info::ledctl_default, e1000_mac_info::ledctl_mode1, e1000_mac_info::ledctl_mode2, e1000_hw::mac, e1000_hw::nvm, e1000_nvm_info::ops, u16, u32, and e1000_nvm_operations::valid_led_default.
Referenced by e1000e_init_mac_params_ich8lan().
02393 { 02394 struct e1000_mac_info *mac = &hw->mac; 02395 s32 ret_val; 02396 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; 02397 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; 02398 u16 data, i, temp, shift; 02399 02400 /* Get default ID LED modes */ 02401 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 02402 if (ret_val) 02403 goto out; 02404 02405 mac->ledctl_default = er32(LEDCTL); 02406 mac->ledctl_mode1 = mac->ledctl_default; 02407 mac->ledctl_mode2 = mac->ledctl_default; 02408 02409 for (i = 0; i < 4; i++) { 02410 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; 02411 shift = (i * 5); 02412 switch (temp) { 02413 case ID_LED_ON1_DEF2: 02414 case ID_LED_ON1_ON2: 02415 case ID_LED_ON1_OFF2: 02416 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 02417 mac->ledctl_mode1 |= (ledctl_on << shift); 02418 break; 02419 case ID_LED_OFF1_DEF2: 02420 case ID_LED_OFF1_ON2: 02421 case ID_LED_OFF1_OFF2: 02422 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); 02423 mac->ledctl_mode1 |= (ledctl_off << shift); 02424 break; 02425 default: 02426 /* Do nothing */ 02427 break; 02428 } 02429 switch (temp) { 02430 case ID_LED_DEF1_ON2: 02431 case ID_LED_ON1_ON2: 02432 case ID_LED_OFF1_ON2: 02433 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 02434 mac->ledctl_mode2 |= (ledctl_on << shift); 02435 break; 02436 case ID_LED_DEF1_OFF2: 02437 case ID_LED_ON1_OFF2: 02438 case ID_LED_OFF1_OFF2: 02439 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); 02440 mac->ledctl_mode2 |= (ledctl_off << shift); 02441 break; 02442 default: 02443 /* Do nothing */ 02444 break; 02445 } 02446 } 02447 02448 out: 02449 return ret_val; 02450 }
e1000e_get_bus_info_ich8lan - Get/Set the bus type and width : pointer to the HW structure
ICH8 use the PCI Express bus, but does not contain a PCI Express Capability register, so the the bus width is hard coded.
Definition at line 2459 of file e1000e_ich8lan.c.
References e1000_hw::bus, e1000_bus_width_pcie_x1, e1000_bus_width_unknown, e1000e_get_bus_info_pcie(), and e1000_bus_info::width.
Referenced by e1000e_init_mac_params_ich8lan().
02460 { 02461 struct e1000_bus_info *bus = &hw->bus; 02462 s32 ret_val; 02463 02464 ret_val = e1000e_get_bus_info_pcie(hw); 02465 02466 /* 02467 * ICH devices are "PCI Express"-ish. They have 02468 * a configuration space, but do not contain 02469 * PCI Express Capability registers, so bus width 02470 * must be hardcoded. 02471 */ 02472 if (bus->width == e1000_bus_width_unknown) 02473 bus->width = e1000_bus_width_pcie_x1; 02474 02475 return ret_val; 02476 }
e1000e_reset_hw_ich8lan - Reset the hardware : pointer to the HW structure
Does a full reset of the hardware which includes a reset of the PHY and MAC.
Definition at line 2485 of file e1000e_ich8lan.c.
References BM_WUC, e1000_hw::dev_spec, E1000_CTRL_PHY_RST, E1000_CTRL_RST, e1000_ich10lan, e1000_ich8lan, E1000_KABGTXD_BGSQLBIAS, E1000_NVM_K1_CONFIG, E1000_NVM_K1_ENABLE, E1000_PBA_8K, E1000_PBS_16K, e1000_pchlan, E1000_STATUS_PHYRA, E1000_TCTL_PSP, e1000e_acquire_swflag_ich8lan(), e1000e_check_reset_block(), e1000e_disable_pcie_master(), e1000e_get_auto_rd_done(), e1000e_hv_phy_workarounds_ich8lan(), e1000e_lan_init_done_ich8lan(), e1000e_oem_bits_config_ich8lan(), e1000e_read_nvm(), e1000e_release_swflag_ich8lan(), e1000e_sw_lcd_config_ich8lan(), e1e_flush, e1e_rphy(), e_dbg, er32, ew32, e1000_phy_operations::get_cfg_done, e1000_hw::ich8lan, e1000_hw::mac, msleep, e1000_dev_spec_ich8lan::nvm_k1_enabled, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_info::reset_disable, e1000_mac_info::type, u16, and u32.
Referenced by e1000e_init_mac_params_ich8lan().
02486 { 02487 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 02488 u16 reg; 02489 u32 ctrl, icr, kab; 02490 s32 ret_val; 02491 02492 /* 02493 * Prevent the PCI-E bus from sticking if there is no TLP connection 02494 * on the last TLP read/write transaction when MAC is reset. 02495 */ 02496 ret_val = e1000e_disable_pcie_master(hw); 02497 if (ret_val) 02498 e_dbg("PCI-E Master disable polling has failed.\n"); 02499 02500 e_dbg("Masking off all interrupts\n"); 02501 ew32(IMC, 0xffffffff); 02502 02503 /* 02504 * Disable the Transmit and Receive units. Then delay to allow 02505 * any pending transactions to complete before we hit the MAC 02506 * with the global reset. 02507 */ 02508 ew32(RCTL, 0); 02509 ew32(TCTL, E1000_TCTL_PSP); 02510 e1e_flush(); 02511 02512 msleep(10); 02513 02514 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 02515 if (hw->mac.type == e1000_ich8lan) { 02516 /* Set Tx and Rx buffer allocation to 8k apiece. */ 02517 ew32(PBA, E1000_PBA_8K); 02518 /* Set Packet Buffer Size to 16k. */ 02519 ew32(PBS, E1000_PBS_16K); 02520 } 02521 02522 if (hw->mac.type == e1000_pchlan) { 02523 /* Save the NVM K1 bit setting*/ 02524 ret_val = e1000e_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®); 02525 if (ret_val) 02526 return ret_val; 02527 02528 if (reg & E1000_NVM_K1_ENABLE) 02529 dev_spec->nvm_k1_enabled = true; 02530 else 02531 dev_spec->nvm_k1_enabled = false; 02532 } 02533 02534 ctrl = er32(CTRL); 02535 02536 if (!e1000e_check_reset_block(hw) && !hw->phy.reset_disable) { 02537 /* Clear PHY Reset Asserted bit */ 02538 if (hw->mac.type >= e1000_pchlan) { 02539 u32 status = er32(STATUS); 02540 ew32(STATUS, status & 02541 ~E1000_STATUS_PHYRA); 02542 } 02543 02544 /* 02545 * PHY HW reset requires MAC CORE reset at the same 02546 * time to make sure the interface between MAC and the 02547 * external PHY is reset. 02548 */ 02549 ctrl |= E1000_CTRL_PHY_RST; 02550 } 02551 ret_val = e1000e_acquire_swflag_ich8lan(hw); 02552 e_dbg("Issuing a global reset to ich8lan\n"); 02553 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 02554 msleep(20); 02555 02556 if (!ret_val) 02557 e1000e_release_swflag_ich8lan(hw); 02558 02559 if (ctrl & E1000_CTRL_PHY_RST) 02560 ret_val = hw->phy.ops.get_cfg_done(hw); 02561 02562 if (hw->mac.type >= e1000_ich10lan) { 02563 e1000e_lan_init_done_ich8lan(hw); 02564 } else { 02565 ret_val = e1000e_get_auto_rd_done(hw); 02566 if (ret_val) { 02567 /* 02568 * When auto config read does not complete, do not 02569 * return with an error. This can happen in situations 02570 * where there is no eeprom and prevents getting link. 02571 */ 02572 e_dbg("Auto Read Done did not complete\n"); 02573 } 02574 } 02575 /* Dummy read to clear the phy wakeup bit after lcd reset */ 02576 if (hw->mac.type == e1000_pchlan) 02577 e1e_rphy(hw, BM_WUC, ®); 02578 02579 ret_val = e1000e_sw_lcd_config_ich8lan(hw); 02580 if (ret_val) 02581 goto out; 02582 02583 if (hw->mac.type == e1000_pchlan) { 02584 ret_val = e1000e_oem_bits_config_ich8lan(hw, true); 02585 if (ret_val) 02586 goto out; 02587 } 02588 /* 02589 * For PCH, this write will make sure that any noise 02590 * will be detected as a CRC error and be dropped rather than show up 02591 * as a bad packet to the DMA engine. 02592 */ 02593 if (hw->mac.type == e1000_pchlan) 02594 ew32(CRC_OFFSET, 0x65656565); 02595 02596 ew32(IMC, 0xffffffff); 02597 icr = er32(ICR); 02598 02599 kab = er32(KABGTXD); 02600 kab |= E1000_KABGTXD_BGSQLBIAS; 02601 ew32(KABGTXD, kab); 02602 02603 if (hw->mac.type == e1000_pchlan) 02604 ret_val = e1000e_hv_phy_workarounds_ich8lan(hw); 02605 02606 out: 02607 return ret_val; 02608 }
e1000e_init_hw_ich8lan - Initialize the hardware : pointer to the HW structure
Prepares the hardware for transmit and receive by doing the following:
Definition at line 2622 of file e1000e_ich8lan.c.
References BM_WUC, E1000_CTRL_EXT_RO_DIS, e1000_ich8lan, E1000_MTA, e1000_phy_82578, E1000_TXDCTL_FULL_TX_DESC_WB, E1000_TXDCTL_MAX_TX_DESC_PREFETCH, E1000_TXDCTL_PTHRESH, E1000_TXDCTL_WTHRESH, E1000_WRITE_REG_ARRAY, e1000e_clear_hw_cntrs_ich8lan(), e1000e_init_rx_addrs(), e1000e_initialize_hw_bits_ich8lan(), e1000e_phy_hw_reset_ich8lan(), e1000e_set_pcie_no_snoop(), e1e_rphy(), e_dbg, er32, ew32, e1000_mac_operations::id_led_init, e1000_hw::mac, e1000_mac_info::mta_reg_count, e1000_mac_info::ops, PCIE_ICH8_SNOOP_ALL, PCIE_NO_SNOOP_ALL, e1000_hw::phy, e1000_mac_info::rar_entry_count, e1000_mac_operations::setup_link, e1000_mac_info::type, e1000_phy_info::type, u16, and u32.
Referenced by e1000e_init_mac_params_ich8lan().
02623 { 02624 struct e1000_mac_info *mac = &hw->mac; 02625 u32 ctrl_ext, txdctl, snoop; 02626 s32 ret_val; 02627 u16 i; 02628 02629 e1000e_initialize_hw_bits_ich8lan(hw); 02630 02631 /* Initialize identification LED */ 02632 ret_val = mac->ops.id_led_init(hw); 02633 if (ret_val) 02634 /* This is not fatal and we should not stop init due to this */ 02635 e_dbg("Error initializing identification LED\n"); 02636 02637 /* Setup the receive address. */ 02638 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 02639 02640 /* Zero out the Multicast HASH table */ 02641 e_dbg("Zeroing the MTA\n"); 02642 for (i = 0; i < mac->mta_reg_count; i++) 02643 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 02644 02645 /* 02646 * The 82578 Rx buffer will stall if wakeup is enabled in host and 02647 * the ME. Reading the BM_WUC register will clear the host wakeup bit. 02648 * Reset the phy after disabling host wakeup to reset the Rx buffer. 02649 */ 02650 if (hw->phy.type == e1000_phy_82578) { 02651 e1e_rphy(hw, BM_WUC, &i); 02652 ret_val = e1000e_phy_hw_reset_ich8lan(hw); 02653 if (ret_val) 02654 return ret_val; 02655 } 02656 02657 /* Setup link and flow control */ 02658 ret_val = mac->ops.setup_link(hw); 02659 02660 /* Set the transmit descriptor write-back policy for both queues */ 02661 txdctl = er32(TXDCTL(0)); 02662 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 02663 E1000_TXDCTL_FULL_TX_DESC_WB; 02664 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 02665 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 02666 ew32(TXDCTL(0), txdctl); 02667 txdctl = er32(TXDCTL(1)); 02668 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 02669 E1000_TXDCTL_FULL_TX_DESC_WB; 02670 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | 02671 E1000_TXDCTL_MAX_TX_DESC_PREFETCH; 02672 ew32(TXDCTL(1), txdctl); 02673 02674 /* 02675 * ICH8 has opposite polarity of no_snoop bits. 02676 * By default, we should use snoop behavior. 02677 */ 02678 if (mac->type == e1000_ich8lan) 02679 snoop = PCIE_ICH8_SNOOP_ALL; 02680 else 02681 snoop = (u32)~(PCIE_NO_SNOOP_ALL); 02682 e1000e_set_pcie_no_snoop(hw, snoop); 02683 02684 ctrl_ext = er32(CTRL_EXT); 02685 ctrl_ext |= E1000_CTRL_EXT_RO_DIS; 02686 ew32(CTRL_EXT, ctrl_ext); 02687 02688 /* 02689 * Clear all of the statistics registers (clear on read). It is 02690 * important that we do this after we have tried to establish link 02691 * because the symbol error count will increment wildly if there 02692 * is no link. 02693 */ 02694 e1000e_clear_hw_cntrs_ich8lan(hw); 02695 02696 return ret_val; 02697 }
e1000e_setup_link_ich8lan - Setup flow control and link settings : pointer to the HW structure
Determines which flow control settings to use, then configures flow control. Calls the appropriate media-specific link configuration function. Assuming the adapter has a valid link partner, a valid link should be established. Assumes the hardware has previously been reset and the transmitter and receiver are not enabled.
Definition at line 2763 of file e1000e_ich8lan.c.
References BM_PORT_CTRL_PAGE, e1000_fc_info::current_mode, e1000_fc_default, e1000_fc_full, e1000_phy_82577, e1000_phy_82578, E1000_SUCCESS, e1000e_check_reset_block(), e1000e_set_fc_watermarks(), e1e_wphy(), e_dbg, ew32, e1000_hw::fc, e1000_hw::mac, e1000_mac_info::ops, e1000_fc_info::pause_time, e1000_hw::phy, PHY_REG, e1000_fc_info::requested_mode, e1000_mac_operations::setup_physical_interface, and e1000_phy_info::type.
Referenced by e1000e_init_mac_params_ich8lan().
02764 { 02765 s32 ret_val = E1000_SUCCESS; 02766 02767 if (e1000e_check_reset_block(hw)) 02768 goto out; 02769 02770 /* 02771 * ICH parts do not have a word in the NVM to determine 02772 * the default flow control setting, so we explicitly 02773 * set it to full. 02774 */ 02775 if (hw->fc.requested_mode == e1000_fc_default) 02776 hw->fc.requested_mode = e1000_fc_full; 02777 02778 /* 02779 * Save off the requested flow control mode for use later. Depending 02780 * on the link partner's capabilities, we may or may not use this mode. 02781 */ 02782 hw->fc.current_mode = hw->fc.requested_mode; 02783 02784 e_dbg("After fix-ups FlowControl is now = %x\n", 02785 hw->fc.current_mode); 02786 02787 /* Continue to configure the copper link. */ 02788 ret_val = hw->mac.ops.setup_physical_interface(hw); 02789 if (ret_val) 02790 goto out; 02791 02792 ew32(FCTTV, hw->fc.pause_time); 02793 if ((hw->phy.type == e1000_phy_82578) || 02794 (hw->phy.type == e1000_phy_82577)) { 02795 ret_val = e1e_wphy(hw, 02796 PHY_REG(BM_PORT_CTRL_PAGE, 27), 02797 hw->fc.pause_time); 02798 if (ret_val) 02799 goto out; 02800 } 02801 02802 ret_val = e1000e_set_fc_watermarks(hw); 02803 02804 out: 02805 return ret_val; 02806 }
e1000e_setup_copper_link_ich8lan - Configure MAC/PHY interface : pointer to the HW structure
Configures the kumeran interface to the PHY to wait the appropriate time when polling the PHY, then call the generic setup_copper_link to finish configuring the copper link.
Definition at line 2816 of file e1000e_ich8lan.c.
References E1000_CTRL_FRCDPX, E1000_CTRL_FRCSPD, E1000_CTRL_SLU, E1000_KMRNCTRLSTA_INBAND_PARAM, E1000_KMRNCTRLSTA_TIMEOUTS, e1000_phy_82577, e1000_phy_82578, e1000_phy_bm, e1000_phy_ife, e1000_phy_igp_3, e1000e_copper_link_setup_82577(), e1000e_copper_link_setup_igp(), e1000e_copper_link_setup_m88(), e1000e_read_kmrn_reg(), e1000e_setup_copper_link(), e1000e_write_kmrn_reg(), e1e_rphy(), e1e_wphy(), er32, ew32, IFE_PHY_MDIX_CONTROL, IFE_PMC_AUTO_MDIX, IFE_PMC_FORCE_MDIX, e1000_phy_info::mdix, e1000_hw::phy, e1000_phy_info::type, u16, and u32.
Referenced by e1000e_init_mac_params_ich8lan().
02817 { 02818 u32 ctrl; 02819 s32 ret_val; 02820 u16 reg_data; 02821 02822 ctrl = er32(CTRL); 02823 ctrl |= E1000_CTRL_SLU; 02824 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 02825 ew32(CTRL, ctrl); 02826 02827 /* 02828 * Set the mac to wait the maximum time between each iteration 02829 * and increase the max iterations when polling the phy; 02830 * this fixes erroneous timeouts at 10Mbps. 02831 */ 02832 ret_val = e1000e_write_kmrn_reg(hw, 02833 E1000_KMRNCTRLSTA_TIMEOUTS, 02834 0xFFFF); 02835 if (ret_val) 02836 goto out; 02837 ret_val = e1000e_read_kmrn_reg(hw, 02838 E1000_KMRNCTRLSTA_INBAND_PARAM, 02839 ®_data); 02840 if (ret_val) 02841 goto out; 02842 reg_data |= 0x3F; 02843 ret_val = e1000e_write_kmrn_reg(hw, 02844 E1000_KMRNCTRLSTA_INBAND_PARAM, 02845 reg_data); 02846 if (ret_val) 02847 goto out; 02848 02849 switch (hw->phy.type) { 02850 case e1000_phy_igp_3: 02851 ret_val = e1000e_copper_link_setup_igp(hw); 02852 if (ret_val) 02853 goto out; 02854 break; 02855 case e1000_phy_bm: 02856 case e1000_phy_82578: 02857 ret_val = e1000e_copper_link_setup_m88(hw); 02858 if (ret_val) 02859 goto out; 02860 break; 02861 case e1000_phy_82577: 02862 ret_val = e1000e_copper_link_setup_82577(hw); 02863 if (ret_val) 02864 goto out; 02865 break; 02866 case e1000_phy_ife: 02867 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, 02868 ®_data); 02869 if (ret_val) 02870 goto out; 02871 02872 reg_data &= ~IFE_PMC_AUTO_MDIX; 02873 02874 switch (hw->phy.mdix) { 02875 case 1: 02876 reg_data &= ~IFE_PMC_FORCE_MDIX; 02877 break; 02878 case 2: 02879 reg_data |= IFE_PMC_FORCE_MDIX; 02880 break; 02881 case 0: 02882 default: 02883 reg_data |= IFE_PMC_AUTO_MDIX; 02884 break; 02885 } 02886 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, 02887 reg_data); 02888 if (ret_val) 02889 goto out; 02890 break; 02891 default: 02892 break; 02893 } 02894 ret_val = e1000e_setup_copper_link(hw); 02895 02896 out: 02897 return ret_val; 02898 }
| static s32 e1000e_get_link_up_info_ich8lan | ( | struct e1000_hw * | hw, | |
| u16 * | speed, | |||
| u16 * | duplex | |||
| ) | [static] |
e1000e_get_link_up_info_ich8lan - Get current link speed and duplex : pointer to the HW structure : pointer to store current link speed : pointer to store the current link duplex
Calls the generic get_speed_and_duplex to retrieve the current link information and then calls the Kumeran lock loss workaround for links at gigabit speeds.
Definition at line 2910 of file e1000e_ich8lan.c.
References e1000_ich8lan, e1000_phy_igp_3, e1000e_get_speed_and_duplex_copper(), e1000e_kmrn_lock_loss_workaround_ich8lan(), e1000_hw::mac, e1000_hw::phy, SPEED_1000, e1000_phy_info::type, and e1000_mac_info::type.
Referenced by e1000e_init_mac_params_ich8lan().
02912 { 02913 s32 ret_val; 02914 02915 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); 02916 if (ret_val) 02917 goto out; 02918 02919 if ((hw->mac.type == e1000_ich8lan) && 02920 (hw->phy.type == e1000_phy_igp_3) && 02921 (*speed == SPEED_1000)) { 02922 ret_val = e1000e_kmrn_lock_loss_workaround_ich8lan(hw); 02923 } 02924 02925 out: 02926 return ret_val; 02927 }
e1000e_cleanup_led_ich8lan - Restore the default LED operation : pointer to the HW structure
Return the LED back to the default configuration.
Definition at line 3161 of file e1000e_ich8lan.c.
References e1000_phy_ife, E1000_SUCCESS, e1e_wphy(), ew32, IFE_PHY_SPECIAL_CONTROL_LED, e1000_mac_info::ledctl_default, e1000_hw::mac, e1000_hw::phy, and e1000_phy_info::type.
Referenced by e1000e_init_mac_params_ich8lan().
03162 { 03163 s32 ret_val = E1000_SUCCESS; 03164 03165 if (hw->phy.type == e1000_phy_ife) 03166 ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 03167 0); 03168 else 03169 ew32(LEDCTL, hw->mac.ledctl_default); 03170 03171 return ret_val; 03172 }
e1000e_led_on_ich8lan - Turn LEDs on : pointer to the HW structure
Turn on the LEDs.
Definition at line 3180 of file e1000e_ich8lan.c.
References e1000_phy_ife, E1000_SUCCESS, e1e_wphy(), ew32, IFE_PHY_SPECIAL_CONTROL_LED, IFE_PSCL_PROBE_LEDS_ON, IFE_PSCL_PROBE_MODE, e1000_mac_info::ledctl_mode2, e1000_hw::mac, e1000_hw::phy, and e1000_phy_info::type.
Referenced by e1000e_init_mac_params_ich8lan().
03181 { 03182 s32 ret_val = E1000_SUCCESS; 03183 03184 if (hw->phy.type == e1000_phy_ife) 03185 ret_val = e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 03186 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); 03187 else 03188 ew32(LEDCTL, hw->mac.ledctl_mode2); 03189 03190 return ret_val; 03191 }
e1000e_led_off_ich8lan - Turn LEDs off : pointer to the HW structure
Turn off the LEDs.
Definition at line 3199 of file e1000e_ich8lan.c.
References e1000_phy_ife, E1000_SUCCESS, e1e_wphy(), ew32, IFE_PHY_SPECIAL_CONTROL_LED, IFE_PSCL_PROBE_LEDS_OFF, IFE_PSCL_PROBE_MODE, e1000_mac_info::ledctl_mode1, e1000_hw::mac, e1000_hw::phy, and e1000_phy_info::type.
Referenced by e1000e_init_mac_params_ich8lan().
03200 { 03201 s32 ret_val = E1000_SUCCESS; 03202 03203 if (hw->phy.type == e1000_phy_ife) 03204 ret_val = e1e_wphy(hw, 03205 IFE_PHY_SPECIAL_CONTROL_LED, 03206 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); 03207 else 03208 ew32(LEDCTL, hw->mac.ledctl_mode1); 03209 03210 return ret_val; 03211 }
e1000e_k1_gig_workaround_hv - K1 Si workaround : pointer to the HW structure link up bool flag
If K1 is enabled for 1Gbps, the MAC might stall when transitioning from a lower speed. This workaround disables K1 whenever link is at 1Gig If link is down, the function will restore the default K1 setting located in the NVM.
Definition at line 869 of file e1000e_ich8lan.c.
References e1000_phy_operations::acquire, BM_CS_STATUS, BM_CS_STATUS_LINK_UP, BM_CS_STATUS_RESOLVED, BM_CS_STATUS_SPEED_1000, BM_CS_STATUS_SPEED_MASK, e1000_hw::dev_spec, e1000_pchlan, e1000_phy_82577, e1000_phy_82578, E1000_SUCCESS, e1000e_configure_k1_ich8lan(), HV_M_STATUS, HV_M_STATUS_AUTONEG_COMPLETE, HV_M_STATUS_LINK_UP, HV_M_STATUS_SPEED_1000, HV_M_STATUS_SPEED_MASK, e1000_hw::ich8lan, e1000_hw::mac, e1000_dev_spec_ich8lan::nvm_k1_enabled, e1000_phy_info::ops, e1000_hw::phy, PHY_REG, e1000_phy_operations::read_reg_locked, e1000_phy_operations::release, e1000_phy_info::type, e1000_mac_info::type, u16, and e1000_phy_operations::write_reg_locked.
Referenced by e1000e_check_for_copper_link_ich8lan(), and e1000e_hv_phy_workarounds_ich8lan().
00870 { 00871 s32 ret_val = E1000_SUCCESS; 00872 u16 status_reg = 0; 00873 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; 00874 00875 if (hw->mac.type != e1000_pchlan) 00876 goto out; 00877 00878 /* Wrap the whole flow with the sw flag */ 00879 ret_val = hw->phy.ops.acquire(hw); 00880 if (ret_val) 00881 goto out; 00882 00883 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ 00884 if (link) { 00885 if (hw->phy.type == e1000_phy_82578) { 00886 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS, 00887 &status_reg); 00888 if (ret_val) 00889 goto release; 00890 00891 status_reg &= BM_CS_STATUS_LINK_UP | 00892 BM_CS_STATUS_RESOLVED | 00893 BM_CS_STATUS_SPEED_MASK; 00894 00895 if (status_reg == (BM_CS_STATUS_LINK_UP | 00896 BM_CS_STATUS_RESOLVED | 00897 BM_CS_STATUS_SPEED_1000)) 00898 k1_enable = false; 00899 } 00900 00901 if (hw->phy.type == e1000_phy_82577) { 00902 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS, 00903 &status_reg); 00904 if (ret_val) 00905 goto release; 00906 00907 status_reg &= HV_M_STATUS_LINK_UP | 00908 HV_M_STATUS_AUTONEG_COMPLETE | 00909 HV_M_STATUS_SPEED_MASK; 00910 00911 if (status_reg == (HV_M_STATUS_LINK_UP | 00912 HV_M_STATUS_AUTONEG_COMPLETE | 00913 HV_M_STATUS_SPEED_1000)) 00914 k1_enable = false; 00915 } 00916 00917 /* Link stall fix for link up */ 00918 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 00919 0x0100); 00920 if (ret_val) 00921 goto release; 00922 00923 } else { 00924 /* Link stall fix for link down */ 00925 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19), 00926 0x4100); 00927 if (ret_val) 00928 goto release; 00929 } 00930 00931 ret_val = e1000e_configure_k1_ich8lan(hw, k1_enable); 00932 00933 release: 00934 hw->phy.ops.release(hw); 00935 out: 00936 return ret_val; 00937 }
e1000e_setup_led_pchlan - Configures SW controllable LED : pointer to the HW structure
This prepares the SW controllable LED for use.
Definition at line 3219 of file e1000e_ich8lan.c.
References e1e_wphy(), HV_LED_CONFIG, e1000_mac_info::ledctl_mode1, e1000_hw::mac, and u16.
Referenced by e1000e_init_mac_params_ich8lan().
03220 { 03221 return e1e_wphy(hw, HV_LED_CONFIG, 03222 (u16)hw->mac.ledctl_mode1); 03223 }
e1000e_cleanup_led_pchlan - Restore the default LED operation : pointer to the HW structure
Return the LED back to the default configuration.
Definition at line 3231 of file e1000e_ich8lan.c.
References e1e_wphy(), HV_LED_CONFIG, e1000_mac_info::ledctl_default, e1000_hw::mac, and u16.
Referenced by e1000e_init_mac_params_ich8lan().
03232 { 03233 return e1e_wphy(hw, HV_LED_CONFIG, 03234 (u16)hw->mac.ledctl_default); 03235 }
e1000e_led_on_pchlan - Turn LEDs on : pointer to the HW structure
Turn on the LEDs.
Definition at line 3243 of file e1000e_ich8lan.c.
References E1000_LEDCTL_MODE_LINK_UP, E1000_PHY_LED0_IVRT, E1000_PHY_LED0_MASK, E1000_PHY_LED0_MODE_MASK, E1000_STATUS_LU, e1e_wphy(), er32, HV_LED_CONFIG, e1000_mac_info::ledctl_mode2, e1000_hw::mac, u16, and u32.
Referenced by e1000e_init_mac_params_ich8lan().
03244 { 03245 u16 data = (u16)hw->mac.ledctl_mode2; 03246 u32 i, led; 03247 03248 /* 03249 * If no link, then turn LED on by setting the invert bit 03250 * for each LED that's mode is "link_up" in ledctl_mode2. 03251 */ 03252 if (!(er32(STATUS) & E1000_STATUS_LU)) { 03253 for (i = 0; i < 3; i++) { 03254 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 03255 if ((led & E1000_PHY_LED0_MODE_MASK) != 03256 E1000_LEDCTL_MODE_LINK_UP) 03257 continue; 03258 if (led & E1000_PHY_LED0_IVRT) 03259 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 03260 else 03261 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 03262 } 03263 } 03264 03265 return e1e_wphy(hw, HV_LED_CONFIG, data); 03266 }
e1000e_led_off_pchlan - Turn LEDs off : pointer to the HW structure
Turn off the LEDs.
Definition at line 3274 of file e1000e_ich8lan.c.
References E1000_LEDCTL_MODE_LINK_UP, E1000_PHY_LED0_IVRT, E1000_PHY_LED0_MASK, E1000_PHY_LED0_MODE_MASK, E1000_STATUS_LU, e1e_wphy(), er32, HV_LED_CONFIG, e1000_mac_info::ledctl_mode1, e1000_hw::mac, u16, and u32.
Referenced by e1000e_init_mac_params_ich8lan().
03275 { 03276 u16 data = (u16)hw->mac.ledctl_mode1; 03277 u32 i, led; 03278 03279 /* 03280 * If no link, then turn LED off by clearing the invert bit 03281 * for each LED that's mode is "link_up" in ledctl_mode1. 03282 */ 03283 if (!(er32(STATUS) & E1000_STATUS_LU)) { 03284 for (i = 0; i < 3; i++) { 03285 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; 03286 if ((led & E1000_PHY_LED0_MODE_MASK) != 03287 E1000_LEDCTL_MODE_LINK_UP) 03288 continue; 03289 if (led & E1000_PHY_LED0_IVRT) 03290 data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); 03291 else 03292 data |= (E1000_PHY_LED0_IVRT << (i * 5)); 03293 } 03294 } 03295 03296 return e1e_wphy(hw, HV_LED_CONFIG, data); 03297 }
| static void e1000e_clear_hw_cntrs_ich8lan | ( | struct e1000_hw * | hw | ) | [static] |
Referenced by e1000e_init_hw_ich8lan(), and e1000e_init_mac_params_ich8lan().
e1000e_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM : pointer to the HW structure : 0 for first bank, 1 for second bank, etc.
Erases the bank specified. Each bank is a 4k block. Banks are 0 based. bank N is 4096 * N + flash_reg_addr.
Definition at line 2248 of file e1000e_ich8lan.c.
References ich8_hws_flash_status::ich8_hsfsts::berasesz, E1000_ERR_NVM, E1000_SUCCESS, e1000e_flash_cycle_ich8lan(), e1000e_flash_cycle_init_ich8lan(), er16flash, ew16flash, ew32flash, e1000_nvm_info::flash_bank_size, e1000_nvm_info::flash_base_addr, ich8_hws_flash_status::ich8_hsfsts::flcdone, ich8_hws_flash_status::ich8_hsfsts::flcerr, ich8_hws_flash_ctrl::ich8_hsflctl::flcycle, ich8_hws_flash_ctrl::hsf_ctrl, ich8_hws_flash_status::hsf_status, ICH_CYCLE_ERASE, ICH_FLASH_CYCLE_REPEAT_COUNT, ICH_FLASH_ERASE_COMMAND_TIMEOUT, ICH_FLASH_FADDR, ICH_FLASH_HSFCTL, ICH_FLASH_HSFSTS, ICH_FLASH_SEG_SIZE_256, ICH_FLASH_SEG_SIZE_4K, ICH_FLASH_SEG_SIZE_64K, ICH_FLASH_SEG_SIZE_8K, e1000_hw::nvm, ich8_hws_flash_ctrl::regval, ich8_hws_flash_status::regval, and u32.
Referenced by e1000e_update_nvm_checksum_ich8lan().
02249 { 02250 struct e1000_nvm_info *nvm = &hw->nvm; 02251 union ich8_hws_flash_status hsfsts; 02252 union ich8_hws_flash_ctrl hsflctl; 02253 u32 flash_linear_addr; 02254 /* bank size is in 16bit words - adjust to bytes */ 02255 u32 flash_bank_size = nvm->flash_bank_size * 2; 02256 s32 ret_val = E1000_SUCCESS; 02257 s32 count = 0; 02258 s32 j, iteration, sector_size; 02259 02260 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 02261 02262 /* 02263 * Determine HW Sector size: Read BERASE bits of hw flash status 02264 * register 02265 * 00: The Hw sector is 256 bytes, hence we need to erase 16 02266 * consecutive sectors. The start index for the nth Hw sector 02267 * can be calculated as = bank * 4096 + n * 256 02268 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. 02269 * The start index for the nth Hw sector can be calculated 02270 * as = bank * 4096 02271 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 02272 * (ich9 only, otherwise error condition) 02273 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 02274 */ 02275 switch (hsfsts.hsf_status.berasesz) { 02276 case 0: 02277 /* Hw sector size 256 */ 02278 sector_size = ICH_FLASH_SEG_SIZE_256; 02279 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; 02280 break; 02281 case 1: 02282 sector_size = ICH_FLASH_SEG_SIZE_4K; 02283 iteration = 1; 02284 break; 02285 case 2: 02286 sector_size = ICH_FLASH_SEG_SIZE_8K; 02287 iteration = 1; 02288 break; 02289 case 3: 02290 sector_size = ICH_FLASH_SEG_SIZE_64K; 02291 iteration = 1; 02292 break; 02293 default: 02294 ret_val = -E1000_ERR_NVM; 02295 goto out; 02296 } 02297 02298 /* Start with the base address, then add the sector offset. */ 02299 flash_linear_addr = hw->nvm.flash_base_addr; 02300 flash_linear_addr += (bank) ? flash_bank_size : 0; 02301 02302 for (j = 0; j < iteration ; j++) { 02303 do { 02304 /* Steps */ 02305 ret_val = e1000e_flash_cycle_init_ich8lan(hw); 02306 if (ret_val) 02307 goto out; 02308 02309 /* 02310 * Write a value 11 (block Erase) in Flash 02311 * Cycle field in hw flash control 02312 */ 02313 hsflctl.regval = er16flash( 02314 ICH_FLASH_HSFCTL); 02315 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; 02316 ew16flash(ICH_FLASH_HSFCTL, 02317 hsflctl.regval); 02318 02319 /* 02320 * Write the last 24 bits of an index within the 02321 * block into Flash Linear address field in Flash 02322 * Address. 02323 */ 02324 flash_linear_addr += (j * sector_size); 02325 ew32flash(ICH_FLASH_FADDR, 02326 flash_linear_addr); 02327 02328 ret_val = e1000e_flash_cycle_ich8lan(hw, 02329 ICH_FLASH_ERASE_COMMAND_TIMEOUT); 02330 if (ret_val == E1000_SUCCESS) 02331 break; 02332 02333 /* 02334 * Check if FCERR is set to 1. If 1, 02335 * clear it and try the whole sequence 02336 * a few more times else Done 02337 */ 02338 hsfsts.regval = er16flash( 02339 ICH_FLASH_HSFSTS); 02340 if (hsfsts.hsf_status.flcerr == 1) 02341 /* repeat for some time before giving up */ 02342 continue; 02343 else if (hsfsts.hsf_status.flcdone == 0) 02344 goto out; 02345 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); 02346 } 02347 02348 out: 02349 return ret_val; 02350 }
e1000e_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) : pointer to the HW structure : maximum time to wait for completion
This function starts a flash cycle and waits for its completion.
Definition at line 1708 of file e1000e_ich8lan.c.
References E1000_ERR_NVM, E1000_SUCCESS, er16flash, ew16flash, ich8_hws_flash_status::ich8_hsfsts::flcdone, ich8_hws_flash_status::ich8_hsfsts::flcerr, ich8_hws_flash_ctrl::ich8_hsflctl::flcgo, ich8_hws_flash_ctrl::hsf_ctrl, ich8_hws_flash_status::hsf_status, ICH_FLASH_HSFCTL, ICH_FLASH_HSFSTS, ich8_hws_flash_status::regval, ich8_hws_flash_ctrl::regval, u32, and udelay().
Referenced by e1000e_erase_flash_bank_ich8lan(), e1000e_read_flash_data_ich8lan(), and e1000e_write_flash_data_ich8lan().
01709 { 01710 union ich8_hws_flash_ctrl hsflctl; 01711 union ich8_hws_flash_status hsfsts; 01712 s32 ret_val = -E1000_ERR_NVM; 01713 u32 i = 0; 01714 01715 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ 01716 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 01717 hsflctl.hsf_ctrl.flcgo = 1; 01718 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 01719 01720 /* wait till FDONE bit is set to 1 */ 01721 do { 01722 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 01723 if (hsfsts.hsf_status.flcdone == 1) 01724 break; 01725 udelay(1); 01726 } while (i++ < timeout); 01727 01728 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) 01729 ret_val = E1000_SUCCESS; 01730 01731 return ret_val; 01732 }
e1000e_flash_cycle_init_ich8lan - Initialize flash : pointer to the HW structure
This function does initial flash setup so that a new read/write/erase cycle can be started.
Definition at line 1631 of file e1000e_ich8lan.c.
References ich8_hws_flash_status::ich8_hsfsts::dael, E1000_ERR_NVM, E1000_SUCCESS, e_dbg, er16flash, ew16flash, ich8_hws_flash_status::ich8_hsfsts::flcdone, ich8_hws_flash_status::ich8_hsfsts::flcerr, ich8_hws_flash_status::ich8_hsfsts::flcinprog, ich8_hws_flash_status::ich8_hsfsts::fldesvalid, ich8_hws_flash_status::hsf_status, ICH_FLASH_HSFSTS, ICH_FLASH_READ_COMMAND_TIMEOUT, ich8_hws_flash_status::regval, and udelay().
Referenced by e1000e_erase_flash_bank_ich8lan(), e1000e_read_flash_data_ich8lan(), and e1000e_write_flash_data_ich8lan().
01632 { 01633 union ich8_hws_flash_status hsfsts; 01634 s32 ret_val = -E1000_ERR_NVM; 01635 s32 i = 0; 01636 01637 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 01638 01639 /* Check if the flash descriptor is valid */ 01640 if (hsfsts.hsf_status.fldesvalid == 0) { 01641 e_dbg("Flash descriptor invalid. " 01642 "SW Sequencing must be used."); 01643 goto out; 01644 } 01645 01646 /* Clear FCERR and DAEL in hw status by writing 1 */ 01647 hsfsts.hsf_status.flcerr = 1; 01648 hsfsts.hsf_status.dael = 1; 01649 01650 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 01651 01652 /* 01653 * Either we should have a hardware SPI cycle in progress 01654 * bit to check against, in order to start a new cycle or 01655 * FDONE bit should be changed in the hardware so that it 01656 * is 1 after hardware reset, which can then be used as an 01657 * indication whether a cycle is in progress or has been 01658 * completed. 01659 */ 01660 01661 if (hsfsts.hsf_status.flcinprog == 0) { 01662 /* 01663 * There is no cycle running at present, 01664 * so we can start a cycle. 01665 * Begin by setting Flash Cycle Done. 01666 */ 01667 hsfsts.hsf_status.flcdone = 1; 01668 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); 01669 ret_val = E1000_SUCCESS; 01670 } else { 01671 /* 01672 * Otherwise poll for sometime so the current 01673 * cycle has a chance to end before giving up. 01674 */ 01675 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { 01676 hsfsts.regval = er16flash( 01677 ICH_FLASH_HSFSTS); 01678 if (hsfsts.hsf_status.flcinprog == 0) { 01679 ret_val = E1000_SUCCESS; 01680 break; 01681 } 01682 udelay(1); 01683 } 01684 if (ret_val == E1000_SUCCESS) { 01685 /* 01686 * Successful in waiting for previous cycle to timeout, 01687 * now set the Flash Cycle Done. 01688 */ 01689 hsfsts.hsf_status.flcdone = 1; 01690 ew16flash(ICH_FLASH_HSFSTS, 01691 hsfsts.regval); 01692 } else { 01693 e_dbg("Flash controller busy, cannot get access"); 01694 } 01695 } 01696 01697 out: 01698 return ret_val; 01699 }
e1000e_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states : pointer to the HW structure
Populates "phy" structure with various feature states. This function is only called by other family-specific routines.
Definition at line 1224 of file e1000e_ich8lan.c.
References e1000_phy_info::cable_length, e1000_phy_info::cable_polarity, e1000_1000t_rx_status_undefined, E1000_CABLE_LENGTH_UNDEFINED, E1000_ERR_CONFIG, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, e1000e_check_polarity_ife(), e1000e_phy_has_link_generic(), e1e_rphy(), e_dbg, IFE_PHY_MDIX_CONTROL, IFE_PHY_SPECIAL_CONTROL, IFE_PMC_MDIX_STATUS, IFE_PSC_AUTO_POLARITY_DISABLE, IFE_PSC_FORCE_POLARITY, e1000_phy_info::is_mdix, e1000_phy_info::local_rx, e1000_hw::phy, e1000_phy_info::polarity_correction, e1000_phy_info::remote_rx, and u16.
Referenced by e1000e_get_phy_info_ich8lan().
01225 { 01226 struct e1000_phy_info *phy = &hw->phy; 01227 s32 ret_val; 01228 u16 data; 01229 bool link; 01230 01231 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 01232 if (ret_val) 01233 goto out; 01234 01235 if (!link) { 01236 e_dbg("Phy info is only valid if link is up\n"); 01237 ret_val = -E1000_ERR_CONFIG; 01238 goto out; 01239 } 01240 01241 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); 01242 if (ret_val) 01243 goto out; 01244 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) 01245 ? false : true; 01246 01247 if (phy->polarity_correction) { 01248 ret_val = e1000e_check_polarity_ife(hw); 01249 if (ret_val) 01250 goto out; 01251 } else { 01252 /* Polarity is forced */ 01253 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) 01254 ? e1000_rev_polarity_reversed 01255 : e1000_rev_polarity_normal; 01256 } 01257 01258 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); 01259 if (ret_val) 01260 goto out; 01261 01262 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false; 01263 01264 /* The following parameters are undefined for 10/100 operation. */ 01265 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 01266 phy->local_rx = e1000_1000t_rx_status_undefined; 01267 phy->remote_rx = e1000_1000t_rx_status_undefined; 01268 01269 out: 01270 return ret_val; 01271 }
| static void e1000e_initialize_hw_bits_ich8lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_initialize_hw_bits_ich8lan - Initialize required hardware bits : pointer to the HW structure
Sets/Clears required hardware bits necessary for correctly setting up the hardware for transmit and receive.
Definition at line 2705 of file e1000e_ich8lan.c.
References E1000_CTRL_EXT_PHYPDEN, e1000_ich8lan, e1000_pchlan, E1000_TCTL_MULR, er32, ew32, e1000_hw::mac, e1000_mac_info::type, and u32.
Referenced by e1000e_init_hw_ich8lan().
02706 { 02707 u32 reg; 02708 02709 /* Extended Device Control */ 02710 reg = er32(CTRL_EXT); 02711 reg |= (1 << 22); 02712 /* Enable PHY low-power state when MAC is at D3 w/o WoL */ 02713 if (hw->mac.type >= e1000_pchlan) 02714 reg |= E1000_CTRL_EXT_PHYPDEN; 02715 ew32(CTRL_EXT, reg); 02716 02717 /* Transmit Descriptor Control 0 */ 02718 reg = er32(TXDCTL(0)); 02719 reg |= (1 << 22); 02720 ew32(TXDCTL(0), reg); 02721 02722 /* Transmit Descriptor Control 1 */ 02723 reg = er32(TXDCTL(1)); 02724 reg |= (1 << 22); 02725 ew32(TXDCTL(1), reg); 02726 02727 /* Transmit Arbitration Control 0 */ 02728 reg = er32(TARC(0)); 02729 if (hw->mac.type == e1000_ich8lan) 02730 reg |= (1 << 28) | (1 << 29); 02731 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); 02732 ew32(TARC(0), reg); 02733 02734 /* Transmit Arbitration Control 1 */ 02735 reg = er32(TARC(1)); 02736 if (er32(TCTL) & E1000_TCTL_MULR) 02737 reg &= ~(1 << 28); 02738 else 02739 reg |= (1 << 28); 02740 reg |= (1 << 24) | (1 << 26) | (1 << 30); 02741 ew32(TARC(1), reg); 02742 02743 /* Device Status */ 02744 if (hw->mac.type == e1000_ich8lan) { 02745 reg = er32(STATUS); 02746 reg &= ~(1 << 31); 02747 ew32(STATUS, reg); 02748 } 02749 02750 return; 02751 }
e1000e_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround : pointer to the HW structure
Work-around for 82566 Kumeran PCS lock loss: On link status change (i.e. PCI reset, speed change) and link is up and speed is gigabit- 0) if workaround is optionally disabled do nothing 1) wait 1ms for Kumeran link to come up 2) check Kumeran Diagnostic register PCS lock loss bit 3) if not set the link is locked (all is good), otherwise... 4) reset the PHY 5) repeat up to 10 times Note: this is only called for IGP3 copper when speed is 1gb.
Definition at line 2944 of file e1000e_ich8lan.c.
References e1000_hw::dev_spec, E1000_ERR_PHY, E1000_PHY_CTRL_GBE_DISABLE, E1000_PHY_CTRL_NOND0A_GBE_DISABLE, E1000_SUCCESS, e1000e_gig_downshift_workaround_ich8lan(), e1000e_phy_has_link_generic(), e1000e_phy_hw_reset(), e1e_rphy(), er32, ew32, e1000_hw::ich8lan, IGP3_KMRN_DIAG, IGP3_KMRN_DIAG_PCS_LOCK_LOSS, e1000_dev_spec_ich8lan::kmrn_lock_loss_workaround_enabled, mdelay(), u16, and u32.
Referenced by e1000e_get_link_up_info_ich8lan().
02945 { 02946 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 02947 u32 phy_ctrl; 02948 s32 ret_val = E1000_SUCCESS; 02949 u16 i, data; 02950 bool link; 02951 02952 if (!(dev_spec->kmrn_lock_loss_workaround_enabled)) 02953 goto out; 02954 02955 /* 02956 * Make sure link is up before proceeding. If not just return. 02957 * Attempting this while link is negotiating fouled up link 02958 * stability 02959 */ 02960 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 02961 if (!link) { 02962 ret_val = E1000_SUCCESS; 02963 goto out; 02964 } 02965 02966 for (i = 0; i < 10; i++) { 02967 /* read once to clear */ 02968 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 02969 if (ret_val) 02970 goto out; 02971 /* and again to get new status */ 02972 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); 02973 if (ret_val) 02974 goto out; 02975 02976 /* check for PCS lock */ 02977 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) { 02978 ret_val = E1000_SUCCESS; 02979 goto out; 02980 } 02981 02982 /* Issue PHY reset */ 02983 e1000e_phy_hw_reset(hw); 02984 mdelay(5); 02985 } 02986 /* Disable GigE link negotiation */ 02987 phy_ctrl = er32(PHY_CTRL); 02988 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | 02989 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 02990 ew32(PHY_CTRL, phy_ctrl); 02991 02992 /* 02993 * Call gig speed drop workaround on Gig disable before accessing 02994 * any PHY registers 02995 */ 02996 e1000e_gig_downshift_workaround_ich8lan(hw); 02997 02998 /* unable to acquire PCS lock */ 02999 ret_val = -E1000_ERR_PHY; 03000 03001 out: 03002 return ret_val; 03003 }
e1000e_read_flash_byte_ich8lan - Read byte from flash : pointer to the HW structure : The offset of the byte to read.
: Pointer to a byte to store the value read.
Reads a single byte from the NVM using the flash access registers.
Definition at line 1770 of file e1000e_ich8lan.c.
References E1000_SUCCESS, e1000e_read_flash_data_ich8lan(), u16, and u8.
Referenced by e1000e_valid_nvm_bank_detect_ich8lan().
01772 { 01773 s32 ret_val = E1000_SUCCESS; 01774 u16 word = 0; 01775 01776 ret_val = e1000e_read_flash_data_ich8lan(hw, offset, 1, &word); 01777 if (ret_val) 01778 goto out; 01779 01780 *data = (u8)word; 01781 01782 out: 01783 return ret_val; 01784 }
| static s32 e1000e_read_flash_data_ich8lan | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u8 | size, | |||
| u16 * | data | |||
| ) | [static] |
e1000e_read_flash_data_ich8lan - Read byte or word from NVM : pointer to the HW structure : The offset (in bytes) of the byte or word to read.
: Size of data to read, 1=byte 2=word : Pointer to the word to store the value read.
Reads a byte or word from the NVM using the flash access registers.
Definition at line 1795 of file e1000e_ich8lan.c.
References E1000_ERR_NVM, E1000_SUCCESS, e1000e_flash_cycle_ich8lan(), e1000e_flash_cycle_init_ich8lan(), e_dbg, er16flash, er32flash, ew16flash, ew32flash, e1000_nvm_info::flash_base_addr, ich8_hws_flash_status::ich8_hsfsts::flcdone, ich8_hws_flash_status::ich8_hsfsts::flcerr, ich8_hws_flash_ctrl::ich8_hsflctl::flcycle, ich8_hws_flash_ctrl::ich8_hsflctl::fldbcount, ich8_hws_flash_ctrl::hsf_ctrl, ich8_hws_flash_status::hsf_status, ICH_CYCLE_READ, ICH_FLASH_FADDR, ICH_FLASH_FDATA0, ICH_FLASH_HSFCTL, ICH_FLASH_HSFSTS, ICH_FLASH_LINEAR_ADDR_MASK, ICH_FLASH_READ_COMMAND_TIMEOUT, e1000_hw::nvm, ich8_hws_flash_status::regval, ich8_hws_flash_ctrl::regval, u16, u32, u8, and udelay().
Referenced by e1000e_read_flash_byte_ich8lan(), and e1000e_read_flash_word_ich8lan().
01797 { 01798 union ich8_hws_flash_status hsfsts; 01799 union ich8_hws_flash_ctrl hsflctl; 01800 u32 flash_linear_addr; 01801 u32 flash_data = 0; 01802 s32 ret_val = -E1000_ERR_NVM; 01803 u8 count = 0; 01804 01805 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) 01806 goto out; 01807 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 01808 hw->nvm.flash_base_addr; 01809 01810 do { 01811 udelay(1); 01812 /* Steps */ 01813 ret_val = e1000e_flash_cycle_init_ich8lan(hw); 01814 if (ret_val != E1000_SUCCESS) 01815 break; 01816 01817 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 01818 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 01819 hsflctl.hsf_ctrl.fldbcount = size - 1; 01820 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; 01821 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 01822 01823 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 01824 01825 ret_val = e1000e_flash_cycle_ich8lan(hw, 01826 ICH_FLASH_READ_COMMAND_TIMEOUT); 01827 01828 /* 01829 * Check if FCERR is set to 1, if set to 1, clear it 01830 * and try the whole sequence a few more times, else 01831 * read in (shift in) the Flash Data0, the order is 01832 * least significant byte first msb to lsb 01833 */ 01834 if (ret_val == E1000_SUCCESS) { 01835 flash_data = er32flash(ICH_FLASH_FDATA0); 01836 if (size == 1) 01837 *data = (u8)(flash_data & 0x000000FF); 01838 else if (size == 2) 01839 *data = (u16)(flash_data & 0x0000FFFF); 01840 break; 01841 } else { 01842 /* 01843 * If we've gotten here, then things are probably 01844 * completely hosed, but if the error condition is 01845 * detected, it won't hurt to give it another try... 01846 * ICH_FLASH_CYCLE_REPEAT_COUNT times. 01847 */ 01848 hsfsts.regval = er16flash( 01849 ICH_FLASH_HSFSTS); 01850 if (hsfsts.hsf_status.flcerr == 1) { 01851 /* Repeat for some time before giving up. */ 01852 continue; 01853 } else if (hsfsts.hsf_status.flcdone == 0) { 01854 e_dbg("Timeout error - flash cycle " 01855 "did not complete."); 01856 break; 01857 } 01858 } 01859 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 01860 01861 out: 01862 return ret_val; 01863 }
e1000e_read_flash_word_ich8lan - Read word from flash : pointer to the HW structure : offset to data location : pointer to the location for storing the data
Reads the flash word at offset into data. Offset is converted to bytes before read.
Definition at line 1743 of file e1000e_ich8lan.c.
References E1000_ERR_NVM, and e1000e_read_flash_data_ich8lan().
Referenced by e1000e_read_nvm_ich8lan(), and e1000e_update_nvm_checksum_ich8lan().
01745 { 01746 s32 ret_val; 01747 01748 if (!data) { 01749 ret_val = -E1000_ERR_NVM; 01750 goto out; 01751 } 01752 01753 /* Must convert offset into bytes. */ 01754 offset <<= 1; 01755 01756 ret_val = e1000e_read_flash_data_ich8lan(hw, offset, 2, data); 01757 01758 out: 01759 return ret_val; 01760 }
| static s32 e1000e_retry_write_flash_byte_ich8lan | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u8 | byte | |||
| ) | [static] |
e1000e_retry_write_flash_byte_ich8lan - Writes a single byte to NVM : pointer to the HW structure : The offset of the byte to write.
: The byte to write to the NVM.
Writes a single byte to the NVM using the flash access registers. Goes through a retry algorithm before giving up.
Definition at line 2214 of file e1000e_ich8lan.c.
References E1000_ERR_NVM, E1000_SUCCESS, e1000e_write_flash_byte_ich8lan(), e_dbg, u16, and udelay().
Referenced by e1000e_update_nvm_checksum_ich8lan().
02216 { 02217 s32 ret_val; 02218 u16 program_retries; 02219 02220 ret_val = e1000e_write_flash_byte_ich8lan(hw, offset, byte); 02221 if (ret_val == E1000_SUCCESS) 02222 goto out; 02223 02224 for (program_retries = 0; program_retries < 100; program_retries++) { 02225 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); 02226 udelay(100); 02227 ret_val = e1000e_write_flash_byte_ich8lan(hw, offset, byte); 02228 if (ret_val == E1000_SUCCESS) 02229 break; 02230 } 02231 if (program_retries == 100) { 02232 ret_val = -E1000_ERR_NVM; 02233 goto out; 02234 } 02235 02236 out: 02237 return ret_val; 02238 }
e1000e_write_flash_byte_ich8lan - Write a single byte to NVM : pointer to the HW structure : The index of the byte to read.
: The byte to write to the NVM.
Writes a single byte to the NVM using the flash access registers.
Definition at line 2197 of file e1000e_ich8lan.c.
References e1000e_write_flash_data_ich8lan(), and u16.
Referenced by e1000e_retry_write_flash_byte_ich8lan().
02199 { 02200 u16 word = (u16)data; 02201 02202 return e1000e_write_flash_data_ich8lan(hw, offset, 1, word); 02203 }
| static s32 e1000e_write_flash_data_ich8lan | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u8 | size, | |||
| u16 | data | |||
| ) | [static] |
e1000e_write_flash_data_ich8lan - Writes bytes to the NVM : pointer to the HW structure : The offset (in bytes) of the byte/word to read.
: Size of data to read, 1=byte 2=word : The byte(s) to write to the NVM.
Writes one/two bytes to the NVM using the flash access registers.
Definition at line 2120 of file e1000e_ich8lan.c.
References E1000_ERR_NVM, E1000_SUCCESS, e1000e_flash_cycle_ich8lan(), e1000e_flash_cycle_init_ich8lan(), e_dbg, er16flash, ew16flash, ew32flash, e1000_nvm_info::flash_base_addr, ich8_hws_flash_status::ich8_hsfsts::flcdone, ich8_hws_flash_status::ich8_hsfsts::flcerr, ich8_hws_flash_ctrl::ich8_hsflctl::flcycle, ich8_hws_flash_ctrl::ich8_hsflctl::fldbcount, ich8_hws_flash_ctrl::hsf_ctrl, ich8_hws_flash_status::hsf_status, ICH_CYCLE_WRITE, ICH_FLASH_FADDR, ICH_FLASH_FDATA0, ICH_FLASH_HSFCTL, ICH_FLASH_HSFSTS, ICH_FLASH_LINEAR_ADDR_MASK, ICH_FLASH_WRITE_COMMAND_TIMEOUT, e1000_hw::nvm, ich8_hws_flash_status::regval, ich8_hws_flash_ctrl::regval, u32, u8, and udelay().
Referenced by e1000e_write_flash_byte_ich8lan().
02122 { 02123 union ich8_hws_flash_status hsfsts; 02124 union ich8_hws_flash_ctrl hsflctl; 02125 u32 flash_linear_addr; 02126 u32 flash_data = 0; 02127 s32 ret_val = -E1000_ERR_NVM; 02128 u8 count = 0; 02129 02130 if (size < 1 || size > 2 || data > size * 0xff || 02131 offset > ICH_FLASH_LINEAR_ADDR_MASK) 02132 goto out; 02133 02134 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + 02135 hw->nvm.flash_base_addr; 02136 02137 do { 02138 udelay(1); 02139 /* Steps */ 02140 ret_val = e1000e_flash_cycle_init_ich8lan(hw); 02141 if (ret_val != E1000_SUCCESS) 02142 break; 02143 02144 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); 02145 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ 02146 hsflctl.hsf_ctrl.fldbcount = size - 1; 02147 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; 02148 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); 02149 02150 ew32flash(ICH_FLASH_FADDR, flash_linear_addr); 02151 02152 if (size == 1) 02153 flash_data = (u32)data & 0x00FF; 02154 else 02155 flash_data = (u32)data; 02156 02157 ew32flash(ICH_FLASH_FDATA0, flash_data); 02158 02159 /* 02160 * check if FCERR is set to 1 , if set to 1, clear it 02161 * and try the whole sequence a few more times else done 02162 */ 02163 ret_val = e1000e_flash_cycle_ich8lan(hw, 02164 ICH_FLASH_WRITE_COMMAND_TIMEOUT); 02165 if (ret_val == E1000_SUCCESS) 02166 break; 02167 02168 /* 02169 * If we're here, then things are most likely 02170 * completely hosed, but if the error condition 02171 * is detected, it won't hurt to give it another 02172 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. 02173 */ 02174 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); 02175 if (hsfsts.hsf_status.flcerr == 1) { 02176 /* Repeat for some time before giving up. */ 02177 continue; 02178 } else if (hsfsts.hsf_status.flcdone == 0) { 02179 e_dbg("Timeout error - flash cycle " 02180 "did not complete."); 02181 break; 02182 } 02183 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); 02184 02185 out: 02186 return ret_val; 02187 }
e1000e_get_cfg_done_ich8lan - Read config done bit : pointer to the HW structure
Read the management control register for the config done bit for completion status. NOTE: silicon which is EEPROM-less will fail trying to read the config done bit, so an error is *ONLY* logged and returns E1000_SUCCESS. If we were to return with error, EEPROM-less silicon would not be able to be reset or change link.
Definition at line 3309 of file e1000e_ich8lan.c.
References E1000_EECD_PRES, E1000_ERR_CONFIG, e1000_ich10lan, e1000_pchlan, e1000_phy_igp_3, E1000_STATUS_PHYRA, E1000_SUCCESS, e1000e_get_cfg_done(), e1000e_phy_init_script_igp3(), e1000e_valid_nvm_bank_detect_ich8lan(), e_dbg, er32, ew32, e1000_hw::mac, e1000_hw::phy, e1000_phy_info::type, e1000_mac_info::type, and u32.
Referenced by e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
03310 { 03311 s32 ret_val = E1000_SUCCESS; 03312 u32 bank = 0; 03313 03314 if (hw->mac.type >= e1000_pchlan) { 03315 u32 status = er32(STATUS); 03316 03317 if (status & E1000_STATUS_PHYRA) { 03318 ew32(STATUS, status & 03319 ~E1000_STATUS_PHYRA); 03320 } else 03321 e_dbg("PHY Reset Asserted not set - needs delay\n"); 03322 } 03323 03324 e1000e_get_cfg_done(hw); 03325 03326 /* If EEPROM is not marked present, init the IGP 3 PHY manually */ 03327 if ((hw->mac.type != e1000_ich10lan) && 03328 (hw->mac.type != e1000_pchlan)) { 03329 if (((er32(EECD) & E1000_EECD_PRES) == 0) && 03330 (hw->phy.type == e1000_phy_igp_3)) { 03331 e1000e_phy_init_script_igp3(hw); 03332 } 03333 } else { 03334 if (e1000e_valid_nvm_bank_detect_ich8lan(hw, &bank)) { 03335 /* Maybe we should do a basic PHY config */ 03336 e_dbg("EEPROM not present\n"); 03337 ret_val = -E1000_ERR_CONFIG; 03338 } 03339 } 03340 03341 return ret_val; 03342 }
| static void e1000e_power_down_phy_copper_ich8lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_power_down_phy_copper_ich8lan - Remove link during PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, remove the link.
Definition at line 3351 of file e1000e_ich8lan.c.
References e1000_mac_operations::check_mng_mode, e1000e_check_reset_block(), e1000e_power_down_phy_copper(), e1000_hw::mac, and e1000_mac_info::ops.
Referenced by e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
03352 { 03353 /* If the management interface is not enabled, then power down */ 03354 if (!(hw->mac.ops.check_mng_mode(hw) || 03355 e1000e_check_reset_block(hw))) 03356 e1000e_power_down_phy_copper(hw); 03357 03358 return; 03359 }
e1000e_check_for_copper_link_ich8lan - Check for link (Copper) : pointer to the HW structure
Checks to see of the link status of the hardware has changed. If a change in link status has been detected, then we read the PHY registers to get the current speed/duplex if link exists.
Definition at line 482 of file e1000e_ich8lan.c.
References e1000_mac_info::autoneg, E1000_ERR_CONFIG, e1000_pchlan, e1000_phy_82578, E1000_SUCCESS, e1000e_check_downshift(), e1000e_config_collision_dist(), e1000e_config_fc_after_link_up(), e1000e_k1_gig_workaround_hv(), e1000e_link_stall_workaround_hv(), e1000e_phy_has_link_generic(), e_dbg, e1000_mac_info::get_link_status, e1000_hw::mac, e1000_hw::phy, e1000_phy_info::type, and e1000_mac_info::type.
Referenced by e1000e_init_mac_params_ich8lan().
00483 { 00484 struct e1000_mac_info *mac = &hw->mac; 00485 s32 ret_val; 00486 bool link; 00487 00488 /* 00489 * We only want to go out to the PHY registers to see if Auto-Neg 00490 * has completed and/or if our link status has changed. The 00491 * get_link_status flag is set upon receiving a Link Status 00492 * Change or Rx Sequence Error interrupt. 00493 */ 00494 if (!mac->get_link_status) { 00495 ret_val = E1000_SUCCESS; 00496 goto out; 00497 } 00498 00499 /* 00500 * First we want to see if the MII Status Register reports 00501 * link. If so, then we want to get the current speed/duplex 00502 * of the PHY. 00503 */ 00504 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 00505 if (ret_val) 00506 goto out; 00507 00508 if (hw->mac.type == e1000_pchlan) { 00509 ret_val = e1000e_k1_gig_workaround_hv(hw, link); 00510 if (ret_val) 00511 goto out; 00512 } 00513 00514 if (!link) 00515 goto out; /* No link detected */ 00516 00517 mac->get_link_status = false; 00518 00519 if (hw->phy.type == e1000_phy_82578) { 00520 ret_val = e1000e_link_stall_workaround_hv(hw); 00521 if (ret_val) 00522 goto out; 00523 } 00524 00525 /* 00526 * Check if there was DownShift, must be checked 00527 * immediately after link-up 00528 */ 00529 e1000e_check_downshift(hw); 00530 00531 /* 00532 * If we are forcing speed/duplex, then we simply return since 00533 * we have already determined whether we have link or not. 00534 */ 00535 if (!mac->autoneg) { 00536 ret_val = -E1000_ERR_CONFIG; 00537 goto out; 00538 } 00539 00540 /* 00541 * Auto-Neg is enabled. Auto Speed Detection takes care 00542 * of MAC speed/duplex configuration. So we only need to 00543 * configure Collision Distance in the MAC. 00544 */ 00545 e1000e_config_collision_dist(hw); 00546 00547 /* 00548 * Configure Flow Control now that Auto-Neg has completed. 00549 * First, we need to restore the desired flow control 00550 * settings because we may have had to re-autoneg with a 00551 * different link partner. 00552 */ 00553 ret_val = e1000e_config_fc_after_link_up(hw); 00554 if (ret_val) 00555 e_dbg("Error configuring flow control\n"); 00556 00557 out: 00558 return ret_val; 00559 }
| static void e1000e_lan_init_done_ich8lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_lan_init_done_ich8lan - Check for PHY config completion : pointer to the HW structure
Check the appropriate indication the MAC has finished configuring the PHY after a software reset.
Definition at line 1121 of file e1000e_ich8lan.c.
References E1000_ICH8_LAN_INIT_TIMEOUT, E1000_STATUS_LAN_INIT_DONE, e_dbg, er32, ew32, u32, and udelay().
Referenced by e1000e_reset_hw_ich8lan(), and e1000e_sw_lcd_config_ich8lan().
01122 { 01123 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; 01124 01125 /* Wait for basic configuration completes before proceeding */ 01126 do { 01127 data = er32(STATUS); 01128 data &= E1000_STATUS_LAN_INIT_DONE; 01129 udelay(100); 01130 } while ((!data) && --loop); 01131 01132 /* 01133 * If basic configuration is incomplete before the above loop 01134 * count reaches 0, loading the configuration from NVM will 01135 * leave the PHY in a bad state possibly resulting in no link. 01136 */ 01137 if (loop == 0) 01138 e_dbg("LAN_INIT_DONE not set, increase timeout\n"); 01139 01140 /* Clear the Init Done bit for the next init event */ 01141 data = er32(STATUS); 01142 data &= ~E1000_STATUS_LAN_INIT_DONE; 01143 ew32(STATUS, data); 01144 }
e1000e_sw_lcd_config_ich8lan - SW-based LCD Configuration : pointer to the HW structure
SW should configure the LCD from the NVM extended configuration region as a workaround for certain parts.
Definition at line 745 of file e1000e_ich8lan.c.
References e1000_phy_operations::acquire, e1000_hw::device_id, E1000_DEV_ID_ICH8_IGP_M, E1000_DEV_ID_ICH8_IGP_M_AMT, E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK, E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT, E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE, E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE, E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK, E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT, E1000_FEXTNVM_SW_CONFIG, E1000_FEXTNVM_SW_CONFIG_ICH8M, e1000_ich8lan, e1000_pchlan, e1000_phy_igp_3, E1000_STRAP_SMBUS_ADDRESS_MASK, E1000_STRAP_SMBUS_ADDRESS_SHIFT, e1000e_lan_init_done_ich8lan(), e1000e_read_nvm(), e1000e_write_phy_reg_hv_locked(), er32, HV_LED_CONFIG, HV_SMB_ADDR, HV_SMB_ADDR_PEC_EN, HV_SMB_ADDR_VALID, IGP01E1000_PHY_PAGE_SELECT, e1000_hw::mac, e1000_phy_info::ops, e1000_hw::phy, PHY_REG_MASK, e1000_phy_operations::release, e1000_phy_info::type, e1000_mac_info::type, u16, u32, and e1000_phy_operations::write_reg_locked.
Referenced by e1000e_phy_hw_reset_ich8lan(), and e1000e_reset_hw_ich8lan().
00746 { 00747 struct e1000_phy_info *phy = &hw->phy; 00748 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; 00749 s32 ret_val; 00750 u16 word_addr, reg_data, reg_addr, phy_page = 0; 00751 00752 ret_val = hw->phy.ops.acquire(hw); 00753 if (ret_val) 00754 return ret_val; 00755 00756 /* 00757 * Initialize the PHY from the NVM on ICH platforms. This 00758 * is needed due to an issue where the NVM configuration is 00759 * not properly autoloaded after power transitions. 00760 * Therefore, after each PHY reset, we will load the 00761 * configuration data out of the NVM manually. 00762 */ 00763 if ((hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) || 00764 (hw->mac.type == e1000_pchlan)) { 00765 /* Check if SW needs to configure the PHY */ 00766 if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) || 00767 (hw->device_id == E1000_DEV_ID_ICH8_IGP_M) || 00768 (hw->mac.type == e1000_pchlan)) 00769 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; 00770 else 00771 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; 00772 00773 data = er32(FEXTNVM); 00774 if (!(data & sw_cfg_mask)) 00775 goto out; 00776 00777 /* Wait for basic configuration completes before proceeding */ 00778 e1000e_lan_init_done_ich8lan(hw); 00779 00780 /* 00781 * Make sure HW does not configure LCD from PHY 00782 * extended configuration before SW configuration 00783 */ 00784 data = er32(EXTCNF_CTRL); 00785 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) 00786 goto out; 00787 00788 cnf_size = er32(EXTCNF_SIZE); 00789 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; 00790 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; 00791 if (!cnf_size) 00792 goto out; 00793 00794 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; 00795 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; 00796 00797 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) && 00798 (hw->mac.type == e1000_pchlan)) { 00799 /* 00800 * HW configures the SMBus address and LEDs when the 00801 * OEM and LCD Write Enable bits are set in the NVM. 00802 * When both NVM bits are cleared, SW will configure 00803 * them instead. 00804 */ 00805 data = er32(STRAP); 00806 data &= E1000_STRAP_SMBUS_ADDRESS_MASK; 00807 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT; 00808 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; 00809 ret_val = e1000e_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, 00810 reg_data); 00811 if (ret_val) 00812 goto out; 00813 00814 data = er32(LEDCTL); 00815 ret_val = e1000e_write_phy_reg_hv_locked(hw, 00816 HV_LED_CONFIG, 00817 (u16)data); 00818 if (ret_val) 00819 goto out; 00820 } 00821 00822 /* Configure LCD from extended configuration region. */ 00823 00824 /* cnf_base_addr is in DWORD */ 00825 word_addr = (u16)(cnf_base_addr << 1); 00826 00827 for (i = 0; i < cnf_size; i++) { 00828 ret_val = e1000e_read_nvm(hw, (word_addr + i * 2), 1, 00829 ®_data); 00830 if (ret_val) 00831 goto out; 00832 00833 ret_val = e1000e_read_nvm(hw, (word_addr + i * 2 + 1), 00834 1, ®_addr); 00835 if (ret_val) 00836 goto out; 00837 00838 /* Save off the PHY page for future writes. */ 00839 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { 00840 phy_page = reg_data; 00841 continue; 00842 } 00843 00844 reg_addr &= PHY_REG_MASK; 00845 reg_addr |= phy_page; 00846 00847 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr, 00848 reg_data); 00849 if (ret_val) 00850 goto out; 00851 } 00852 } 00853 00854 out: 00855 hw->phy.ops.release(hw); 00856 return ret_val; 00857 }
| void e1000e_init_function_pointers_ich8lan | ( | struct e1000_hw * | hw | ) |
e1000e_init_function_pointers_ich8lan - Initialize ICH8 function pointers : pointer to the HW structure
Initialize family-specific function pointers for PHY, MAC, and NVM.
Definition at line 567 of file e1000e_ich8lan.c.
References e1000_ich10lan, e1000_ich8lan, e1000_ich9lan, e1000_pchlan, e1000e_init_mac_ops_generic(), e1000e_init_mac_params_ich8lan(), e1000e_init_nvm_ops_generic(), e1000e_init_nvm_params_ich8lan(), e1000e_init_phy_params_ich8lan(), e1000e_init_phy_params_pchlan(), e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::nvm, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, e1000_hw::phy, and e1000_mac_info::type.
00568 { 00569 e1000e_init_mac_ops_generic(hw); 00570 e1000e_init_nvm_ops_generic(hw); 00571 hw->mac.ops.init_params = e1000e_init_mac_params_ich8lan; 00572 hw->nvm.ops.init_params = e1000e_init_nvm_params_ich8lan; 00573 switch (hw->mac.type) { 00574 case e1000_ich8lan: 00575 case e1000_ich9lan: 00576 case e1000_ich10lan: 00577 hw->phy.ops.init_params = e1000e_init_phy_params_ich8lan; 00578 break; 00579 case e1000_pchlan: 00580 hw->phy.ops.init_params = e1000e_init_phy_params_pchlan; 00581 break; 00582 default: 00583 break; 00584 } 00585 }
e1000e_acquire_nvm_ich8lan - Acquire NVM mutex : pointer to the HW structure
Acquires the mutex for performing NVM operations.
Definition at line 597 of file e1000e_ich8lan.c.
References E1000_SUCCESS.
00598 { 00599 #if 0 00600 mutex_lock(&nvm_mutex); 00601 #endif 00602 return E1000_SUCCESS; 00603 }
e1000e_release_nvm_ich8lan - Release NVM mutex : pointer to the HW structure
Releases the mutex used while performing NVM operations.
Definition at line 611 of file e1000e_ich8lan.c.
e1000e_configure_k1_ich8lan - Configure K1 power state : pointer to the HW structure : K1 state to configure
Configure the K1 power state based on the provided parameter. Assumes semaphore already acquired.
Success returns 0, Failure returns -E1000_ERR_PHY (-2)
Definition at line 949 of file e1000e_ich8lan.c.
References E1000_CTRL_EXT, E1000_CTRL_EXT_SPD_BYPS, E1000_CTRL_FRCSPD, E1000_CTRL_SPD_100, E1000_CTRL_SPD_1000, E1000_KMRNCTRLSTA_K1_CONFIG, E1000_KMRNCTRLSTA_K1_ENABLE, E1000_SUCCESS, E1000_WRITE_REG, e1000e_read_kmrn_reg_locked(), e1000e_write_kmrn_reg_locked(), er32, ew32, u16, u32, and udelay().
Referenced by e1000e_k1_gig_workaround_hv().
00950 { 00951 s32 ret_val = E1000_SUCCESS; 00952 u32 ctrl_reg = 0; 00953 u32 ctrl_ext = 0; 00954 u32 reg = 0; 00955 u16 kmrn_reg = 0; 00956 00957 ret_val = e1000e_read_kmrn_reg_locked(hw, 00958 E1000_KMRNCTRLSTA_K1_CONFIG, 00959 &kmrn_reg); 00960 if (ret_val) 00961 goto out; 00962 00963 if (k1_enable) 00964 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; 00965 else 00966 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; 00967 00968 ret_val = e1000e_write_kmrn_reg_locked(hw, 00969 E1000_KMRNCTRLSTA_K1_CONFIG, 00970 kmrn_reg); 00971 if (ret_val) 00972 goto out; 00973 00974 udelay(20); 00975 ctrl_ext = er32(CTRL_EXT); 00976 ctrl_reg = er32(CTRL); 00977 00978 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 00979 reg |= E1000_CTRL_FRCSPD; 00980 ew32(CTRL, reg); 00981 00982 E1000_WRITE_REG(hw, 00983 E1000_CTRL_EXT, 00984 ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); 00985 udelay(20); 00986 ew32(CTRL, ctrl_reg); 00987 ew32(CTRL_EXT, ctrl_ext); 00988 udelay(20); 00989 00990 out: 00991 return ret_val; 00992 }
e1000e_oem_bits_config_ich8lan - SW-based LCD Configuration : pointer to the HW structure : boolean if entering d0 or d3 device state
SW will configure Gbe Disable and LPLU based on the NVM. The four bits are collectively called OEM bits. The OEM Write Enable bit and SW Config bit in NVM determines whether HW should configure LPLU and Gbe Disable.
Definition at line 1003 of file e1000e_ich8lan.c.
References e1000_phy_operations::acquire, E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE, E1000_FEXTNVM_SW_CONFIG_ICH8M, e1000_pchlan, E1000_PHY_CTRL_D0A_LPLU, E1000_PHY_CTRL_GBE_DISABLE, E1000_PHY_CTRL_NOND0A_GBE_DISABLE, E1000_PHY_CTRL_NOND0A_LPLU, e1000e_check_reset_block(), er32, HV_OEM_BITS, HV_OEM_BITS_GBE_DIS, HV_OEM_BITS_LPLU, HV_OEM_BITS_RESTART_AN, e1000_hw::mac, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg_locked, e1000_phy_operations::release, e1000_mac_info::type, u16, u32, and e1000_phy_operations::write_reg_locked.
Referenced by e1000e_phy_hw_reset_ich8lan(), and e1000e_reset_hw_ich8lan().
01004 { 01005 s32 ret_val = 0; 01006 u32 mac_reg; 01007 u16 oem_reg; 01008 01009 if (hw->mac.type != e1000_pchlan) 01010 return ret_val; 01011 01012 ret_val = hw->phy.ops.acquire(hw); 01013 if (ret_val) 01014 return ret_val; 01015 01016 mac_reg = er32(EXTCNF_CTRL); 01017 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) 01018 goto out; 01019 01020 mac_reg = er32(FEXTNVM); 01021 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) 01022 goto out; 01023 01024 mac_reg = er32(PHY_CTRL); 01025 01026 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg); 01027 if (ret_val) 01028 goto out; 01029 01030 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); 01031 01032 if (d0_state) { 01033 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) 01034 oem_reg |= HV_OEM_BITS_GBE_DIS; 01035 01036 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) 01037 oem_reg |= HV_OEM_BITS_LPLU; 01038 } else { 01039 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE) 01040 oem_reg |= HV_OEM_BITS_GBE_DIS; 01041 01042 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU) 01043 oem_reg |= HV_OEM_BITS_LPLU; 01044 } 01045 /* Restart auto-neg to activate the bits */ 01046 if (!e1000e_check_reset_block(hw)) 01047 oem_reg |= HV_OEM_BITS_RESTART_AN; 01048 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg); 01049 01050 out: 01051 hw->phy.ops.release(hw); 01052 01053 return ret_val; 01054 }
e1000e_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be done after every PHY reset.
Definition at line 1060 of file e1000e_ich8lan.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, e1000_pchlan, e1000_phy_82577, e1000_phy_82578, E1000_SUCCESS, e1000e_k1_gig_workaround_hv(), e1000e_phy_sw_reset(), e1000e_write_phy_reg_mdic(), e1e_wphy(), IGP01E1000_PHY_PAGE_SELECT, e1000_hw::mac, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, PHY_REG, e1000_phy_operations::release, e1000_phy_info::revision, e1000_phy_info::type, and e1000_mac_info::type.
Referenced by e1000e_phy_hw_reset_ich8lan(), and e1000e_reset_hw_ich8lan().
01061 { 01062 s32 ret_val = E1000_SUCCESS; 01063 01064 if (hw->mac.type != e1000_pchlan) 01065 goto out; 01066 01067 if (((hw->phy.type == e1000_phy_82577) && 01068 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || 01069 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { 01070 /* Disable generation of early preamble */ 01071 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); 01072 if (ret_val) 01073 goto out; 01074 01075 /* Preamble tuning for SSC */ 01076 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204); 01077 if (ret_val) 01078 goto out; 01079 } 01080 01081 if (hw->phy.type == e1000_phy_82578) { 01082 /* 01083 * Return registers to default by doing a soft reset then 01084 * writing 0x3140 to the control register. 01085 */ 01086 if (hw->phy.revision < 2) { 01087 e1000e_phy_sw_reset(hw); 01088 ret_val = e1e_wphy(hw, PHY_CONTROL, 01089 0x3140); 01090 } 01091 } 01092 01093 /* Select page 0 */ 01094 ret_val = hw->phy.ops.acquire(hw); 01095 if (ret_val) 01096 goto out; 01097 01098 hw->phy.addr = 1; 01099 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); 01100 if (ret_val) 01101 goto out; 01102 hw->phy.ops.release(hw); 01103 01104 /* 01105 * Configure the K1 Si workaround during phy reset assuming there is 01106 * link so that it disables K1 if link is in 1Gbps. 01107 */ 01108 ret_val = e1000e_k1_gig_workaround_hv(hw, true); 01109 01110 out: 01111 return ret_val; 01112 }
e1000e_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 : pointer to the HW structure : pointer to the variable that returns the active bank
Reads signature byte from the NVM using the flash access registers. Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
Definition at line 1503 of file e1000e_ich8lan.c.
References E1000_EECD_SEC1VAL, E1000_EECD_SEC1VAL_VALID_MASK, E1000_ERR_NVM, e1000_ich8lan, e1000_ich9lan, E1000_ICH_NVM_SIG_VALUE, E1000_ICH_NVM_SIG_WORD, E1000_ICH_NVM_VALID_SIG_MASK, E1000_SUCCESS, e1000e_read_flash_byte_ich8lan(), e_dbg, er32, e1000_nvm_info::flash_bank_size, e1000_hw::mac, e1000_hw::nvm, e1000_mac_info::type, u16, u32, and u8.
Referenced by e1000e_get_cfg_done_ich8lan(), e1000e_read_nvm_ich8lan(), and e1000e_update_nvm_checksum_ich8lan().
01504 { 01505 u32 eecd; 01506 struct e1000_nvm_info *nvm = &hw->nvm; 01507 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); 01508 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; 01509 u8 sig_byte = 0; 01510 s32 ret_val = E1000_SUCCESS; 01511 01512 switch (hw->mac.type) { 01513 case e1000_ich8lan: 01514 case e1000_ich9lan: 01515 eecd = er32(EECD); 01516 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == 01517 E1000_EECD_SEC1VAL_VALID_MASK) { 01518 if (eecd & E1000_EECD_SEC1VAL) 01519 *bank = 1; 01520 else 01521 *bank = 0; 01522 01523 goto out; 01524 } 01525 e_dbg("Unable to determine valid NVM bank via EEC - " 01526 "reading flash signature\n"); 01527 /* fall-thru */ 01528 default: 01529 /* set bank to 0 in case flash read fails */ 01530 *bank = 0; 01531 01532 /* Check bank 0 */ 01533 ret_val = e1000e_read_flash_byte_ich8lan(hw, act_offset, 01534 &sig_byte); 01535 if (ret_val) 01536 goto out; 01537 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 01538 E1000_ICH_NVM_SIG_VALUE) { 01539 *bank = 0; 01540 goto out; 01541 } 01542 01543 /* Check bank 1 */ 01544 ret_val = e1000e_read_flash_byte_ich8lan(hw, act_offset + 01545 bank1_offset, 01546 &sig_byte); 01547 if (ret_val) 01548 goto out; 01549 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == 01550 E1000_ICH_NVM_SIG_VALUE) { 01551 *bank = 1; 01552 goto out; 01553 } 01554 01555 e_dbg("ERROR: No valid NVM bank present\n"); 01556 ret_val = -E1000_ERR_NVM; 01557 break; 01558 } 01559 out: 01560 return ret_val; 01561 }
e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state : pointer to the HW structure : boolean value used to set the current Kumeran workaround state
If ICH8, set the current Kumeran workaround state (enabled - true /disabled - false).
Definition at line 3013 of file e1000e_ich8lan.c.
References e1000_hw::dev_spec, e1000_ich8lan, e_dbg, e1000_hw::ich8lan, e1000_dev_spec_ich8lan::kmrn_lock_loss_workaround_enabled, e1000_hw::mac, and e1000_mac_info::type.
Referenced by e1000e_init_mac_params_ich8lan().
03015 { 03016 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 03017 03018 if (hw->mac.type != e1000_ich8lan) { 03019 e_dbg("Workaround applies to ICH8 only.\n"); 03020 return; 03021 } 03022 03023 dev_spec->kmrn_lock_loss_workaround_enabled = state; 03024 03025 return; 03026 }
| void e1000e_igp3_phy_powerdown_workaround_ich8lan | ( | struct e1000_hw * | hw | ) |
e1000e_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 : pointer to the HW structure
Workaround for 82566 power-down on D3 entry: 1) disable gigabit link 2) write VR power-down enable 3) read it back Continue if successful, else issue LCD reset and repeat
Definition at line 3038 of file e1000e_ich8lan.c.
References E1000_CTRL_PHY_RST, e1000_ich8lan, E1000_PHY_CTRL_GBE_DISABLE, E1000_PHY_CTRL_NOND0A_GBE_DISABLE, e1000_phy_igp_3, e1000e_gig_downshift_workaround_ich8lan(), e1e_rphy(), e1e_wphy(), er32, ew32, IGP3_VR_CTRL, IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK, IGP3_VR_CTRL_MODE_SHUTDOWN, e1000_hw::mac, e1000_hw::phy, e1000_mac_info::type, e1000_phy_info::type, u16, u32, and u8.
03039 { 03040 u32 reg; 03041 u16 data; 03042 u8 retry = 0; 03043 03044 if (hw->phy.type != e1000_phy_igp_3) 03045 goto out; 03046 03047 /* Try the workaround twice (if needed) */ 03048 do { 03049 /* Disable link */ 03050 reg = er32(PHY_CTRL); 03051 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 03052 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 03053 ew32(PHY_CTRL, reg); 03054 03055 /* 03056 * Call gig speed drop workaround on Gig disable before 03057 * accessing any PHY registers 03058 */ 03059 if (hw->mac.type == e1000_ich8lan) 03060 e1000e_gig_downshift_workaround_ich8lan(hw); 03061 03062 /* Write VR power-down enable */ 03063 e1e_rphy(hw, IGP3_VR_CTRL, &data); 03064 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 03065 e1e_wphy(hw, IGP3_VR_CTRL, 03066 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 03067 03068 /* Read it back and test */ 03069 e1e_rphy(hw, IGP3_VR_CTRL, &data); 03070 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 03071 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 03072 break; 03073 03074 /* Issue PHY reset and repeat at most one more time */ 03075 reg = er32(CTRL); 03076 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 03077 retry++; 03078 } while (retry); 03079 03080 out: 03081 return; 03082 }
| void e1000e_gig_downshift_workaround_ich8lan | ( | struct e1000_hw * | hw | ) |
e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working : pointer to the HW structure
Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), LPLU, Gig disable, MDIC PHY reset): 1) Set Kumeran Near-end loopback 2) Clear Kumeran Near-end loopback Should only be called for ICH8[m] devices with IGP_3 Phy.
Definition at line 3094 of file e1000e_ich8lan.c.
References e1000_ich8lan, E1000_KMRNCTRLSTA_DIAG_NELPBK, E1000_KMRNCTRLSTA_DIAG_OFFSET, e1000_phy_igp_3, E1000_SUCCESS, e1000e_read_kmrn_reg(), e1000e_write_kmrn_reg(), e1000_hw::mac, e1000_hw::phy, e1000_phy_info::type, e1000_mac_info::type, and u16.
Referenced by e1000e_igp3_phy_powerdown_workaround_ich8lan(), e1000e_kmrn_lock_loss_workaround_ich8lan(), e1000e_set_d0_lplu_state_ich8lan(), and e1000e_set_d3_lplu_state_ich8lan().
03095 { 03096 s32 ret_val = E1000_SUCCESS; 03097 u16 reg_data; 03098 03099 if ((hw->mac.type != e1000_ich8lan) || 03100 (hw->phy.type != e1000_phy_igp_3)) 03101 goto out; 03102 03103 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 03104 ®_data); 03105 if (ret_val) 03106 goto out; 03107 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 03108 ret_val = e1000e_write_kmrn_reg(hw, 03109 E1000_KMRNCTRLSTA_DIAG_OFFSET, 03110 reg_data); 03111 if (ret_val) 03112 goto out; 03113 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 03114 ret_val = e1000e_write_kmrn_reg(hw, 03115 E1000_KMRNCTRLSTA_DIAG_OFFSET, 03116 reg_data); 03117 out: 03118 return; 03119 }
| void e1000e_disable_gig_wol_ich8lan | ( | struct e1000_hw * | hw | ) |
e1000e_disable_gig_wol_ich8lan - disable gig during WoL : pointer to the HW structure
During S0 to Sx transition, it is possible the link remains at gig instead of negotiating to a lower speed. Before going to Sx, set 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation to a lower speed.
Should only be called for applicable parts.
Definition at line 3132 of file e1000e_ich8lan.c.
References e1000_ich10lan, e1000_ich8lan, e1000_ich9lan, e1000_pchlan, E1000_PHY_CTRL_D0A_LPLU, E1000_PHY_CTRL_GBE_DISABLE, e1000e_phy_hw_reset_ich8lan(), er32, ew32, e1000_hw::mac, e1000_mac_info::type, and u32.
03133 { 03134 u32 phy_ctrl; 03135 03136 switch (hw->mac.type) { 03137 case e1000_ich8lan: 03138 case e1000_ich9lan: 03139 case e1000_ich10lan: 03140 case e1000_pchlan: 03141 phy_ctrl = er32(PHY_CTRL); 03142 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 03143 E1000_PHY_CTRL_GBE_DISABLE; 03144 ew32(PHY_CTRL, phy_ctrl); 03145 03146 if (hw->mac.type == e1000_pchlan) 03147 e1000e_phy_hw_reset_ich8lan(hw); 03148 default: 03149 break; 03150 } 03151 03152 return; 03153 }
e1000e_clear_hw_cntrs_ich8lan - Clear statistical counters : pointer to the HW structure
Clears hardware counters specific to the silicon family and calls clear_hw_cntrs_generic to clear all general purpose counters.
Definition at line 3368 of file e1000e_ich8lan.c.
References e1000_phy_82577, e1000_phy_82578, e1000e_clear_hw_cntrs_base(), e1e_rphy(), er32, HV_COLC_LOWER, HV_COLC_UPPER, HV_DC_LOWER, HV_DC_UPPER, HV_ECOL_LOWER, HV_ECOL_UPPER, HV_LATECOL_LOWER, HV_LATECOL_UPPER, HV_MCC_LOWER, HV_MCC_UPPER, HV_SCC_LOWER, HV_SCC_UPPER, HV_TNCRS_LOWER, HV_TNCRS_UPPER, and u16.
03369 { 03370 #if 0 03371 u16 phy_data; 03372 03373 e1000e_clear_hw_cntrs_base(hw); 03374 03375 er32(ALGNERRC); 03376 er32(RXERRC); 03377 er32(TNCRS); 03378 er32(CEXTERR); 03379 er32(TSCTC); 03380 er32(TSCTFC); 03381 03382 er32(MGTPRC); 03383 er32(MGTPDC); 03384 er32(MGTPTC); 03385 03386 er32(IAC); 03387 er32(ICRXOC); 03388 03389 /* Clear PHY statistics registers */ 03390 if ((hw->phy.type == e1000_phy_82578) || 03391 (hw->phy.type == e1000_phy_82577)) { 03392 e1e_rphy(hw, HV_SCC_UPPER, &phy_data); 03393 e1e_rphy(hw, HV_SCC_LOWER, &phy_data); 03394 e1e_rphy(hw, HV_ECOL_UPPER, &phy_data); 03395 e1e_rphy(hw, HV_ECOL_LOWER, &phy_data); 03396 e1e_rphy(hw, HV_MCC_UPPER, &phy_data); 03397 e1e_rphy(hw, HV_MCC_LOWER, &phy_data); 03398 e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data); 03399 e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data); 03400 e1e_rphy(hw, HV_COLC_UPPER, &phy_data); 03401 e1e_rphy(hw, HV_COLC_LOWER, &phy_data); 03402 e1e_rphy(hw, HV_DC_UPPER, &phy_data); 03403 e1e_rphy(hw, HV_DC_LOWER, &phy_data); 03404 e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data); 03405 e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data); 03406 } 03407 #endif 03408 }
struct pci_device_id e1000e_ich8lan_nics[] [static] |
Initial value:
{
PCI_ROM(0x8086, 0x104C, "E1000_DEV_ID_ICH8_IFE", "E1000_DEV_ID_ICH8_IFE", board_ich8lan),
PCI_ROM(0x8086, 0x10C5, "E1000_DEV_ID_ICH8_IFE_G", "E1000_DEV_ID_ICH8_IFE_G", board_ich8lan),
PCI_ROM(0x8086, 0x10C4, "E1000_DEV_ID_ICH8_IFE_GT", "E1000_DEV_ID_ICH8_IFE_GT", board_ich8lan),
PCI_ROM(0x8086, 0x104A, "E1000_DEV_ID_ICH8_IGP_AMT", "E1000_DEV_ID_ICH8_IGP_AMT", board_ich8lan),
PCI_ROM(0x8086, 0x104B, "E1000_DEV_ID_ICH8_IGP_C", "E1000_DEV_ID_ICH8_IGP_C", board_ich8lan),
PCI_ROM(0x8086, 0x104D, "E1000_DEV_ID_ICH8_IGP_M", "E1000_DEV_ID_ICH8_IGP_M", board_ich8lan),
PCI_ROM(0x8086, 0x1049, "E1000_DEV_ID_ICH8_IGP_M_AMT", "E1000_DEV_ID_ICH8_IGP_M_AMT", board_ich8lan),
PCI_ROM(0x8086, 0x1501, "E1000_DEV_ID_ICH8_82567V_3", "E1000_DEV_ID_ICH8_82567V_3", board_ich8lan),
PCI_ROM(0x8086, 0x10C0, "E1000_DEV_ID_ICH9_IFE", "E1000_DEV_ID_ICH9_IFE", board_ich9lan),
PCI_ROM(0x8086, 0x10C2, "E1000_DEV_ID_ICH9_IFE_G", "E1000_DEV_ID_ICH9_IFE_G", board_ich9lan),
PCI_ROM(0x8086, 0x10C3, "E1000_DEV_ID_ICH9_IFE_GT", "E1000_DEV_ID_ICH9_IFE_GT", board_ich9lan),
PCI_ROM(0x8086, 0x10BD, "E1000_DEV_ID_ICH9_IGP_AMT", "E1000_DEV_ID_ICH9_IGP_AMT", board_ich9lan),
PCI_ROM(0x8086, 0x294C, "E1000_DEV_ID_ICH9_IGP_C", "E1000_DEV_ID_ICH9_IGP_C", board_ich9lan),
PCI_ROM(0x8086, 0x10E5, "E1000_DEV_ID_ICH9_BM", "E1000_DEV_ID_ICH9_BM", board_ich9lan),
PCI_ROM(0x8086, 0x10BF, "E1000_DEV_ID_ICH9_IGP_M", "E1000_DEV_ID_ICH9_IGP_M", board_ich9lan),
PCI_ROM(0x8086, 0x10F5, "E1000_DEV_ID_ICH9_IGP_M_AMT", "E1000_DEV_ID_ICH9_IGP_M_AMT", board_ich9lan),
PCI_ROM(0x8086, 0x10CB, "E1000_DEV_ID_ICH9_IGP_M_V", "E1000_DEV_ID_ICH9_IGP_M_V", board_ich9lan),
PCI_ROM(0x8086, 0x10CC, "E1000_DEV_ID_ICH10_R_BM_LM", "E1000_DEV_ID_ICH10_R_BM_LM", board_ich9lan),
PCI_ROM(0x8086, 0x10CD, "E1000_DEV_ID_ICH10_R_BM_LF", "E1000_DEV_ID_ICH10_R_BM_LF", board_ich9lan),
PCI_ROM(0x8086, 0x10CE, "E1000_DEV_ID_ICH10_R_BM_V", "E1000_DEV_ID_ICH10_R_BM_V", board_ich9lan),
PCI_ROM(0x8086, 0x10DE, "E1000_DEV_ID_ICH10_D_BM_LM", "E1000_DEV_ID_ICH10_D_BM_LM", board_ich10lan),
PCI_ROM(0x8086, 0x10DF, "E1000_DEV_ID_ICH10_D_BM_LF", "E1000_DEV_ID_ICH10_D_BM_LF", board_ich10lan),
PCI_ROM(0x8086, 0x10EA, "E1000_DEV_ID_PCH_M_HV_LM", "E1000_DEV_ID_PCH_M_HV_LM", board_pchlan),
PCI_ROM(0x8086, 0x10EB, "E1000_DEV_ID_PCH_M_HV_LC", "E1000_DEV_ID_PCH_M_HV_LC", board_pchlan),
PCI_ROM(0x8086, 0x10EF, "E1000_DEV_ID_PCH_D_HV_DM", "E1000_DEV_ID_PCH_D_HV_DM", board_pchlan),
PCI_ROM(0x8086, 0x10F0, "E1000_DEV_ID_PCH_D_HV_DC", "E1000_DEV_ID_PCH_D_HV_DC", board_pchlan),
}
Definition at line 3410 of file e1000e_ich8lan.c.
| struct pci_driver e1000e_ich8lan_driver __pci_driver |
Initial value:
{
.ids = e1000e_ich8lan_nics,
.id_count = (sizeof (e1000e_ich8lan_nics) / sizeof (e1000e_ich8lan_nics[0])),
.probe = e1000e_probe,
.remove = e1000e_remove,
}
Definition at line 3439 of file e1000e_ich8lan.c.
1.5.7.1