#include "e1000e.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| static s32 | e1000e_init_phy_params_82571 (struct e1000_hw *hw) |
| e1000e_init_phy_params_82571 - Init PHY func ptrs. | |
| static s32 | e1000e_init_nvm_params_82571 (struct e1000_hw *hw) |
| e1000e_init_nvm_params_82571 - Init NVM func ptrs. | |
| static s32 | e1000e_init_mac_params_82571 (struct e1000_hw *hw) |
| e1000e_init_mac_params_82571 - Init MAC func ptrs. | |
| static s32 | e1000e_acquire_nvm_82571 (struct e1000_hw *hw) |
| e1000e_acquire_nvm_82571 - Request for access to the EEPROM : pointer to the HW structure | |
| static void | e1000e_release_nvm_82571 (struct e1000_hw *hw) |
| e1000e_release_nvm_82571 - Release exclusive access to EEPROM : pointer to the HW structure | |
| static s32 | e1000e_write_nvm_82571 (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| e1000e_write_nvm_82571 - Write to EEPROM using appropriate interface : pointer to the HW structure : offset within the EEPROM to be written to : number of words to write : 16 bit word(s) to be written to the EEPROM | |
| static s32 | e1000e_update_nvm_checksum_82571 (struct e1000_hw *hw) |
| e1000e_update_nvm_checksum_82571 - Update EEPROM checksum : pointer to the HW structure | |
| static s32 | e1000e_validate_nvm_checksum_82571 (struct e1000_hw *hw) |
| e1000e_validate_nvm_checksum_82571 - Validate EEPROM checksum : pointer to the HW structure | |
| static s32 | e1000e_get_cfg_done_82571 (struct e1000_hw *hw) |
| e1000e_get_cfg_done_82571 - Poll for configuration done : pointer to the HW structure | |
| static s32 | e1000e_set_d0_lplu_state_82571 (struct e1000_hw *hw, bool active) |
| e1000e_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state : pointer to the HW structure : true to enable LPLU, false to disable | |
| static s32 | e1000e_reset_hw_82571 (struct e1000_hw *hw) |
| e1000e_reset_hw_82571 - Reset hardware : pointer to the HW structure | |
| static s32 | e1000e_init_hw_82571 (struct e1000_hw *hw) |
| e1000e_init_hw_82571 - Initialize hardware : pointer to the HW structure | |
| static void | e1000e_clear_vfta_82571 (struct e1000_hw *hw) |
| e1000e_clear_vfta_82571 - Clear VLAN filter table : pointer to the HW structure | |
| static s32 | e1000e_led_on_82574 (struct e1000_hw *hw) |
| static s32 | e1000e_setup_link_82571 (struct e1000_hw *hw) |
| e1000e_setup_link_82571 - Setup flow control and link settings : pointer to the HW structure | |
| static s32 | e1000e_setup_copper_link_82571 (struct e1000_hw *hw) |
| e1000e_setup_copper_link_82571 - Configure copper link settings : pointer to the HW structure | |
| static s32 | e1000e_check_for_serdes_link_82571 (struct e1000_hw *hw) |
| e1000e_check_for_serdes_link_82571 - Check for link (Serdes) : pointer to the HW structure | |
| static s32 | e1000e_setup_fiber_serdes_link_82571 (struct e1000_hw *hw) |
| e1000e_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes : pointer to the HW structure | |
| static s32 | e1000e_valid_led_default_82571 (struct e1000_hw *hw, u16 *data) |
| e1000e_valid_led_default_82571 - Verify a valid default LED config : pointer to the HW structure : pointer to the NVM (EEPROM) | |
| static void | e1000e_clear_hw_cntrs_82571 (struct e1000_hw *hw) |
| static s32 | e1000e_get_hw_semaphore_82571 (struct e1000_hw *hw) |
| e1000e_get_hw_semaphore_82571 - Acquire hardware semaphore : pointer to the HW structure | |
| static s32 | e1000e_fix_nvm_checksum_82571 (struct e1000_hw *hw) |
| e1000e_fix_nvm_checksum_82571 - Fix EEPROM checksum : pointer to the HW structure | |
| static s32 | e1000e_get_phy_id_82571 (struct e1000_hw *hw) |
| e1000e_get_phy_id_82571 - Retrieve the PHY ID and revision : pointer to the HW structure | |
| static void | e1000e_put_hw_semaphore_82571 (struct e1000_hw *hw) |
| e1000e_put_hw_semaphore_82571 - Release hardware semaphore : pointer to the HW structure | |
| static void | e1000e_initialize_hw_bits_82571 (struct e1000_hw *hw) |
| e1000e_initialize_hw_bits_82571 - Initialize hardware-dependent bits : pointer to the HW structure | |
| static s32 | e1000e_write_nvm_eewr_82571 (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| e1000e_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon : pointer to the HW structure : offset within the EEPROM to be written to : number of words to write : 16 bit word(s) to be written to the EEPROM | |
| static s32 | e1000e_read_mac_addr_82571 (struct e1000_hw *hw) |
| e1000e_read_mac_addr_82571 - Read device MAC address : pointer to the HW structure | |
| static void | e1000e_power_down_phy_copper_82571 (struct e1000_hw *hw) |
| e1000e_power_down_phy_copper_82571 - Remove link during PHY power down : pointer to the HW structure | |
| void | e1000e_init_function_pointers_82571 (struct e1000_hw *hw) |
| e1000e_init_function_pointers_82571 - Init func ptrs. | |
| static s32 | e1000e_led_on_82574 (struct e1000_hw *hw __unused) |
| e1000e_led_on_82574 - Turn LED on : pointer to the HW structure | |
| bool | e1000e_get_laa_state_82571 (struct e1000_hw *hw) |
| e1000e_get_laa_state_82571 - Get locally administered address state : pointer to the HW structure | |
| void | e1000e_set_laa_state_82571 (struct e1000_hw *hw, bool state) |
| e1000e_set_laa_state_82571 - Set locally administered address state : pointer to the HW structure : enable/disable locally administered address | |
| static void | e1000e_clear_hw_cntrs_82571 (struct e1000_hw *hw __unused) |
| e1000e_clear_hw_cntrs_82571 - Clear device specific hardware counters : pointer to the HW structure | |
Variables | |
| static struct pci_device_id | e1000e_82571_nics [] |
| struct pci_driver e1000e_82571_driver | __pci_driver |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
e1000e_init_phy_params_82571 - Init PHY func ptrs.
: pointer to the HW structure
Definition at line 90 of file e1000e_82571.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, AUTONEG_ADVERTISE_SPEED_DEFAULT, e1000_phy_info::autoneg_mask, BME1000_E_PHY_ID_R2, e1000_phy_operations::check_polarity, e1000_phy_operations::check_reset_block, e1000_phy_operations::commit, e1000_82571, e1000_82572, e1000_82573, e1000_82574, e1000_82583, E1000_ERR_PHY, e1000_media_type_copper, e1000_phy_bm, e1000_phy_igp_2, e1000_phy_m88, e1000_phy_none, E1000_SUCCESS, e1000e_check_polarity_igp(), e1000e_check_reset_block_generic(), e1000e_get_cfg_done(), e1000e_get_cfg_done_82571(), e1000e_get_hw_semaphore_82571(), e1000e_get_phy_id_82571(), e1000e_get_phy_info_igp(), e1000e_get_phy_info_m88(), e1000e_phy_hw_reset_generic(), e1000e_phy_sw_reset(), e1000e_power_down_phy_copper_82571(), e1000e_power_up_phy_copper(), e1000e_put_hw_semaphore_82571(), e1000e_read_phy_reg_bm2(), e1000e_read_phy_reg_igp(), e1000e_read_phy_reg_m88(), e1000e_set_d0_lplu_state_82571(), e1000e_set_d3_lplu_state(), e1000e_write_phy_reg_bm2(), e1000e_write_phy_reg_igp(), e1000e_write_phy_reg_m88(), e_dbg, e1000_phy_operations::get_cfg_done, e1000_phy_operations::get_info, e1000_phy_info::id, IGP01E1000_I_PHY_ID, M88E1111_I_PHY_ID, e1000_hw::mac, e1000_phy_info::media_type, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_down, e1000_phy_operations::power_up, e1000_phy_operations::read_reg, e1000_phy_operations::release, e1000_phy_operations::reset, e1000_phy_info::reset_delay_us, e1000_phy_operations::set_d0_lplu_state, e1000_phy_operations::set_d3_lplu_state, e1000_mac_info::type, e1000_phy_info::type, and e1000_phy_operations::write_reg.
Referenced by e1000e_init_function_pointers_82571().
00091 { 00092 struct e1000_phy_info *phy = &hw->phy; 00093 s32 ret_val = E1000_SUCCESS; 00094 00095 if (hw->phy.media_type != e1000_media_type_copper) { 00096 phy->type = e1000_phy_none; 00097 goto out; 00098 } 00099 00100 phy->addr = 1; 00101 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 00102 phy->reset_delay_us = 100; 00103 00104 phy->ops.acquire = e1000e_get_hw_semaphore_82571; 00105 phy->ops.check_polarity = e1000e_check_polarity_igp; 00106 phy->ops.check_reset_block = e1000e_check_reset_block_generic; 00107 phy->ops.release = e1000e_put_hw_semaphore_82571; 00108 phy->ops.reset = e1000e_phy_hw_reset_generic; 00109 phy->ops.set_d0_lplu_state = e1000e_set_d0_lplu_state_82571; 00110 phy->ops.set_d3_lplu_state = e1000e_set_d3_lplu_state; 00111 phy->ops.power_up = e1000e_power_up_phy_copper; 00112 phy->ops.power_down = e1000e_power_down_phy_copper_82571; 00113 00114 switch (hw->mac.type) { 00115 case e1000_82571: 00116 case e1000_82572: 00117 phy->type = e1000_phy_igp_2; 00118 phy->ops.get_cfg_done = e1000e_get_cfg_done_82571; 00119 phy->ops.get_info = e1000e_get_phy_info_igp; 00120 #if 0 00121 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; 00122 #endif 00123 #if 0 00124 phy->ops.get_cable_length = e1000e_get_cable_length_igp_2; 00125 #endif 00126 phy->ops.read_reg = e1000e_read_phy_reg_igp; 00127 phy->ops.write_reg = e1000e_write_phy_reg_igp; 00128 00129 /* This uses above function pointers */ 00130 ret_val = e1000e_get_phy_id_82571(hw); 00131 00132 /* Verify PHY ID */ 00133 if (phy->id != IGP01E1000_I_PHY_ID) { 00134 ret_val = -E1000_ERR_PHY; 00135 goto out; 00136 } 00137 break; 00138 case e1000_82573: 00139 phy->type = e1000_phy_m88; 00140 phy->ops.get_cfg_done = e1000e_get_cfg_done; 00141 phy->ops.get_info = e1000e_get_phy_info_m88; 00142 phy->ops.commit = e1000e_phy_sw_reset; 00143 #if 0 00144 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 00145 #endif 00146 #if 0 00147 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 00148 #endif 00149 phy->ops.read_reg = e1000e_read_phy_reg_m88; 00150 phy->ops.write_reg = e1000e_write_phy_reg_m88; 00151 00152 /* This uses above function pointers */ 00153 ret_val = e1000e_get_phy_id_82571(hw); 00154 00155 /* Verify PHY ID */ 00156 if (phy->id != M88E1111_I_PHY_ID) { 00157 ret_val = -E1000_ERR_PHY; 00158 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); 00159 goto out; 00160 } 00161 break; 00162 case e1000_82583: 00163 case e1000_82574: 00164 phy->type = e1000_phy_bm; 00165 phy->ops.get_cfg_done = e1000e_get_cfg_done; 00166 phy->ops.get_info = e1000e_get_phy_info_m88; 00167 phy->ops.commit = e1000e_phy_sw_reset; 00168 #if 0 00169 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; 00170 #endif 00171 #if 0 00172 phy->ops.get_cable_length = e1000e_get_cable_length_m88; 00173 #endif 00174 phy->ops.read_reg = e1000e_read_phy_reg_bm2; 00175 phy->ops.write_reg = e1000e_write_phy_reg_bm2; 00176 00177 /* This uses above function pointers */ 00178 ret_val = e1000e_get_phy_id_82571(hw); 00179 /* Verify PHY ID */ 00180 if (phy->id != BME1000_E_PHY_ID_R2) { 00181 ret_val = -E1000_ERR_PHY; 00182 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); 00183 goto out; 00184 } 00185 break; 00186 default: 00187 ret_val = -E1000_ERR_PHY; 00188 goto out; 00189 break; 00190 } 00191 00192 out: 00193 return ret_val; 00194 }
e1000e_init_nvm_params_82571 - Init NVM func ptrs.
: pointer to the HW structure
Definition at line 200 of file e1000e_82571.c.
References e1000_nvm_operations::acquire, e1000_nvm_info::address_bits, e1000_nvm_info::delay_usec, e1000_82573, e1000_82574, e1000_82583, E1000_EECD_ADDR_BITS, E1000_EECD_AUPDEN, E1000_EECD_SIZE_EX_MASK, E1000_EECD_SIZE_EX_SHIFT, e1000_nvm_eeprom_spi, e1000_nvm_flash_hw, e1000_nvm_override_spi_large, e1000_nvm_override_spi_small, E1000_SUCCESS, e1000e_acquire_nvm_82571(), e1000e_read_nvm_eerd(), e1000e_release_nvm_82571(), e1000e_update_nvm_checksum_82571(), e1000e_valid_led_default_82571(), e1000e_validate_nvm_checksum_82571(), e1000e_write_nvm_82571(), er32, ew32, e1000_hw::mac, e1000_hw::nvm, NVM_WORD_SIZE_BASE_SHIFT, e1000_nvm_info::opcode_bits, e1000_nvm_info::ops, e1000_nvm_info::override, e1000_nvm_info::page_size, e1000_nvm_operations::read, e1000_nvm_operations::release, size, e1000_nvm_info::type, e1000_mac_info::type, u16, u32, e1000_nvm_operations::update, e1000_nvm_operations::valid_led_default, e1000_nvm_operations::validate, e1000_nvm_info::word_size, and e1000_nvm_operations::write.
Referenced by e1000e_init_function_pointers_82571().
00201 { 00202 struct e1000_nvm_info *nvm = &hw->nvm; 00203 u32 eecd = er32(EECD); 00204 u16 size; 00205 00206 nvm->opcode_bits = 8; 00207 nvm->delay_usec = 1; 00208 switch (nvm->override) { 00209 case e1000_nvm_override_spi_large: 00210 nvm->page_size = 32; 00211 nvm->address_bits = 16; 00212 break; 00213 case e1000_nvm_override_spi_small: 00214 nvm->page_size = 8; 00215 nvm->address_bits = 8; 00216 break; 00217 default: 00218 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 00219 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 00220 break; 00221 } 00222 00223 switch (hw->mac.type) { 00224 case e1000_82573: 00225 case e1000_82574: 00226 case e1000_82583: 00227 if (((eecd >> 15) & 0x3) == 0x3) { 00228 nvm->type = e1000_nvm_flash_hw; 00229 nvm->word_size = 2048; 00230 /* 00231 * Autonomous Flash update bit must be cleared due 00232 * to Flash update issue. 00233 */ 00234 eecd &= ~E1000_EECD_AUPDEN; 00235 ew32(EECD, eecd); 00236 break; 00237 } 00238 /* Fall Through */ 00239 default: 00240 nvm->type = e1000_nvm_eeprom_spi; 00241 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 00242 E1000_EECD_SIZE_EX_SHIFT); 00243 /* 00244 * Added to a constant, "size" becomes the left-shift value 00245 * for setting word_size. 00246 */ 00247 size += NVM_WORD_SIZE_BASE_SHIFT; 00248 00249 /* EEPROM access above 16k is unsupported */ 00250 if (size > 14) 00251 size = 14; 00252 nvm->word_size = 1 << size; 00253 break; 00254 } 00255 00256 /* Function Pointers */ 00257 nvm->ops.acquire = e1000e_acquire_nvm_82571; 00258 nvm->ops.read = e1000e_read_nvm_eerd; 00259 nvm->ops.release = e1000e_release_nvm_82571; 00260 nvm->ops.update = e1000e_update_nvm_checksum_82571; 00261 nvm->ops.validate = e1000e_validate_nvm_checksum_82571; 00262 nvm->ops.valid_led_default = e1000e_valid_led_default_82571; 00263 nvm->ops.write = e1000e_write_nvm_82571; 00264 00265 return E1000_SUCCESS; 00266 }
e1000e_init_mac_params_82571 - Init MAC func ptrs.
: pointer to the HW structure
Definition at line 272 of file e1000e_82571.c.
References e1000_hw::_82571, e1000_mac_info::arc_subsystem_valid, e1000_mac_info::asf_firmware_present, e1000_mac_operations::blink_led, e1000_mac_operations::check_for_link, e1000_mac_operations::check_mng_mode, e1000_mac_operations::cleanup_led, e1000_mac_operations::clear_hw_cntrs, e1000_mac_operations::clear_vfta, e1000_hw::dev_spec, e1000_hw::device_id, e1000_82571, e1000_82572, e1000_82573, e1000_82574, e1000_82583, E1000_DEV_ID_82571EB_FIBER, E1000_DEV_ID_82571EB_QUAD_FIBER, E1000_DEV_ID_82571EB_SERDES, E1000_DEV_ID_82571EB_SERDES_DUAL, E1000_DEV_ID_82571EB_SERDES_QUAD, E1000_DEV_ID_82572EI_FIBER, E1000_DEV_ID_82572EI_SERDES, E1000_ERR_CONFIG, E1000_FWSM_MODE_MASK, e1000_media_type_copper, e1000_media_type_fiber, e1000_media_type_internal_serdes, E1000_RAR_ENTRIES, E1000_SUCCESS, E1000_SWSM2_LOCK, E1000_SWSM_SMBI, e1000e_blink_led(), e1000e_check_for_copper_link(), e1000e_check_for_fiber_link(), e1000e_check_for_serdes_link_82571(), e1000e_check_mng_mode_generic(), e1000e_cleanup_led_generic(), e1000e_clear_hw_cntrs_82571(), e1000e_clear_vfta_82571(), e1000e_get_bus_info_pcie(), e1000e_get_speed_and_duplex_copper(), e1000e_get_speed_and_duplex_fiber_serdes(), e1000e_id_led_init(), e1000e_init_hw_82571(), e1000e_led_off_generic(), e1000e_led_on_82574(), e1000e_led_on_generic(), e1000e_mta_set_generic(), e1000e_read_mac_addr_82571(), e1000e_reset_hw_82571(), e1000e_set_lan_id_single_port(), e1000e_setup_copper_link_82571(), e1000e_setup_fiber_serdes_link_82571(), e1000e_setup_led_generic(), e1000e_setup_link_82571(), e1000e_update_mc_addr_list_generic(), e1000e_write_vfta_generic(), e_dbg, er32, ew32, e1000_mac_operations::get_bus_info, e1000_mac_operations::get_link_up_info, e1000_mac_operations::id_led_init, e1000_mac_operations::init_hw, e1000_mac_operations::led_off, e1000_mac_operations::led_on, e1000_hw::mac, e1000_phy_info::media_type, e1000_mac_info::mta_reg_count, e1000_mac_operations::mta_set, e1000_mac_info::ops, e1000_hw::phy, e1000_mac_info::rar_entry_count, e1000_mac_operations::read_mac_addr, e1000_mac_operations::reset_hw, e1000_mac_operations::set_lan_id, e1000_mac_operations::setup_led, e1000_mac_operations::setup_link, e1000_mac_operations::setup_physical_interface, e1000_dev_spec_82571::smb_counter, e1000_mac_info::type, u32, e1000_mac_operations::update_mc_addr_list, and e1000_mac_operations::write_vfta.
Referenced by e1000e_init_function_pointers_82571().
00273 { 00274 struct e1000_mac_info *mac = &hw->mac; 00275 s32 ret_val = E1000_SUCCESS; 00276 u32 swsm = 0; 00277 u32 swsm2 = 0; 00278 bool force_clear_smbi = false; 00279 00280 /* Set media type */ 00281 switch (hw->device_id) { 00282 case E1000_DEV_ID_82571EB_FIBER: 00283 case E1000_DEV_ID_82572EI_FIBER: 00284 case E1000_DEV_ID_82571EB_QUAD_FIBER: 00285 hw->phy.media_type = e1000_media_type_fiber; 00286 break; 00287 case E1000_DEV_ID_82571EB_SERDES: 00288 case E1000_DEV_ID_82571EB_SERDES_DUAL: 00289 case E1000_DEV_ID_82571EB_SERDES_QUAD: 00290 case E1000_DEV_ID_82572EI_SERDES: 00291 hw->phy.media_type = e1000_media_type_internal_serdes; 00292 break; 00293 default: 00294 hw->phy.media_type = e1000_media_type_copper; 00295 break; 00296 } 00297 00298 /* Set mta register count */ 00299 mac->mta_reg_count = 128; 00300 /* Set rar entry count */ 00301 mac->rar_entry_count = E1000_RAR_ENTRIES; 00302 /* Set if part includes ASF firmware */ 00303 mac->asf_firmware_present = true; 00304 /* Set if manageability features are enabled. */ 00305 mac->arc_subsystem_valid = 00306 (er32(FWSM) & E1000_FWSM_MODE_MASK) 00307 ? true : false; 00308 00309 /* Function pointers */ 00310 00311 /* bus type/speed/width */ 00312 mac->ops.get_bus_info = e1000e_get_bus_info_pcie; 00313 /* function id */ 00314 switch (hw->mac.type) { 00315 case e1000_82573: 00316 case e1000_82574: 00317 case e1000_82583: 00318 mac->ops.set_lan_id = e1000e_set_lan_id_single_port; 00319 break; 00320 default: 00321 break; 00322 } 00323 /* reset */ 00324 mac->ops.reset_hw = e1000e_reset_hw_82571; 00325 /* hw initialization */ 00326 mac->ops.init_hw = e1000e_init_hw_82571; 00327 /* link setup */ 00328 mac->ops.setup_link = e1000e_setup_link_82571; 00329 /* physical interface link setup */ 00330 mac->ops.setup_physical_interface = 00331 (hw->phy.media_type == e1000_media_type_copper) 00332 ? e1000e_setup_copper_link_82571 00333 : e1000e_setup_fiber_serdes_link_82571; 00334 /* check for link */ 00335 switch (hw->phy.media_type) { 00336 case e1000_media_type_copper: 00337 mac->ops.check_for_link = e1000e_check_for_copper_link; 00338 break; 00339 case e1000_media_type_fiber: 00340 mac->ops.check_for_link = e1000e_check_for_fiber_link; 00341 break; 00342 case e1000_media_type_internal_serdes: 00343 mac->ops.check_for_link = e1000e_check_for_serdes_link_82571; 00344 break; 00345 default: 00346 ret_val = -E1000_ERR_CONFIG; 00347 goto out; 00348 break; 00349 } 00350 /* check management mode */ 00351 #if 0 00352 switch (hw->mac.type) { 00353 case e1000_82574: 00354 case e1000_82583: 00355 mac->ops.check_mng_mode = e1000e_check_mng_mode_82574; 00356 break; 00357 default: 00358 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; 00359 break; 00360 } 00361 #endif 00362 /* multicast address update */ 00363 mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic; 00364 /* writing VFTA */ 00365 mac->ops.write_vfta = e1000e_write_vfta_generic; 00366 /* clearing VFTA */ 00367 mac->ops.clear_vfta = e1000e_clear_vfta_82571; 00368 /* setting MTA */ 00369 mac->ops.mta_set = e1000e_mta_set_generic; 00370 /* read mac address */ 00371 mac->ops.read_mac_addr = e1000e_read_mac_addr_82571; 00372 /* ID LED init */ 00373 mac->ops.id_led_init = e1000e_id_led_init; 00374 /* blink LED */ 00375 mac->ops.blink_led = e1000e_blink_led; 00376 /* setup LED */ 00377 mac->ops.setup_led = e1000e_setup_led_generic; 00378 /* cleanup LED */ 00379 mac->ops.cleanup_led = e1000e_cleanup_led_generic; 00380 /* turn on/off LED */ 00381 switch (hw->mac.type) { 00382 case e1000_82574: 00383 case e1000_82583: 00384 mac->ops.led_on = e1000e_led_on_82574; 00385 break; 00386 default: 00387 mac->ops.led_on = e1000e_led_on_generic; 00388 break; 00389 } 00390 mac->ops.led_off = e1000e_led_off_generic; 00391 /* clear hardware counters */ 00392 mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_82571; 00393 /* link info */ 00394 mac->ops.get_link_up_info = 00395 (hw->phy.media_type == e1000_media_type_copper) 00396 ? e1000e_get_speed_and_duplex_copper 00397 : e1000e_get_speed_and_duplex_fiber_serdes; 00398 00399 /* 00400 * Ensure that the inter-port SWSM.SMBI lock bit is clear before 00401 * first NVM or PHY acess. This should be done for single-port 00402 * devices, and for one port only on dual-port devices so that 00403 * for those devices we can still use the SMBI lock to synchronize 00404 * inter-port accesses to the PHY & NVM. 00405 */ 00406 switch (hw->mac.type) { 00407 case e1000_82571: 00408 case e1000_82572: 00409 swsm2 = er32(SWSM2); 00410 00411 if (!(swsm2 & E1000_SWSM2_LOCK)) { 00412 /* Only do this for the first interface on this card */ 00413 ew32(SWSM2, 00414 swsm2 | E1000_SWSM2_LOCK); 00415 force_clear_smbi = true; 00416 } else 00417 force_clear_smbi = false; 00418 break; 00419 default: 00420 force_clear_smbi = true; 00421 break; 00422 } 00423 00424 if (force_clear_smbi) { 00425 /* Make sure SWSM.SMBI is clear */ 00426 swsm = er32(SWSM); 00427 if (swsm & E1000_SWSM_SMBI) { 00428 /* This bit should not be set on a first interface, and 00429 * indicates that the bootagent or EFI code has 00430 * improperly left this bit enabled 00431 */ 00432 e_dbg("Please update your 82571 Bootagent\n"); 00433 } 00434 ew32(SWSM, swsm & ~E1000_SWSM_SMBI); 00435 } 00436 00437 /* 00438 * Initialze device specific counter of SMBI acquisition 00439 * timeouts. 00440 */ 00441 hw->dev_spec._82571.smb_counter = 0; 00442 00443 out: 00444 return ret_val; 00445 }
e1000e_acquire_nvm_82571 - Request for access to the EEPROM : pointer to the HW structure
To gain access to the EEPROM, first we must obtain a hardware semaphore. Then for non-82573 hardware, set the EEPROM access request bit and wait for EEPROM access grant bit. If the access grant bit is not set, release hardware semaphore.
Definition at line 599 of file e1000e_82571.c.
References e1000_82573, e1000_82574, e1000_82583, e1000e_acquire_nvm(), e1000e_get_hw_semaphore_82571(), e1000e_put_hw_semaphore_82571(), e1000_hw::mac, and e1000_mac_info::type.
Referenced by e1000e_init_nvm_params_82571().
00600 { 00601 s32 ret_val; 00602 00603 ret_val = e1000e_get_hw_semaphore_82571(hw); 00604 if (ret_val) 00605 goto out; 00606 00607 switch (hw->mac.type) { 00608 case e1000_82574: 00609 case e1000_82583: 00610 case e1000_82573: 00611 break; 00612 default: 00613 ret_val = e1000e_acquire_nvm(hw); 00614 break; 00615 } 00616 00617 if (ret_val) 00618 e1000e_put_hw_semaphore_82571(hw); 00619 00620 out: 00621 return ret_val; 00622 }
| static void e1000e_release_nvm_82571 | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_release_nvm_82571 - Release exclusive access to EEPROM : pointer to the HW structure
Stop any current commands to the EEPROM and clear the EEPROM request bit.
Definition at line 630 of file e1000e_82571.c.
References e1000e_put_hw_semaphore_82571(), and e1000e_release_nvm().
Referenced by e1000e_init_nvm_params_82571().
00631 { 00632 e1000e_release_nvm(hw); 00633 e1000e_put_hw_semaphore_82571(hw); 00634 }
| static s32 e1000e_write_nvm_82571 | ( | struct e1000_hw * | hw, | |
| u16 | offset, | |||
| u16 | words, | |||
| u16 * | data | |||
| ) | [static] |
e1000e_write_nvm_82571 - Write to EEPROM using appropriate interface : pointer to the HW structure : offset within the EEPROM to be written to : number of words to write : 16 bit word(s) to be written to the EEPROM
For non-82573 silicon, write data to EEPROM at offset using SPI interface.
If e1000e_update_nvm_checksum is not called after this function, the EEPROM will most likely contain an invalid checksum.
Definition at line 648 of file e1000e_82571.c.
References e1000_82571, e1000_82572, e1000_82573, e1000_82574, e1000_82583, E1000_ERR_NVM, E1000_SUCCESS, e1000e_write_nvm_eewr_82571(), e1000e_write_nvm_spi(), e1000_hw::mac, and e1000_mac_info::type.
Referenced by e1000e_init_nvm_params_82571().
00650 { 00651 s32 ret_val = E1000_SUCCESS; 00652 00653 switch (hw->mac.type) { 00654 case e1000_82573: 00655 case e1000_82574: 00656 case e1000_82583: 00657 ret_val = e1000e_write_nvm_eewr_82571(hw, offset, words, data); 00658 break; 00659 case e1000_82571: 00660 case e1000_82572: 00661 ret_val = e1000e_write_nvm_spi(hw, offset, words, data); 00662 break; 00663 default: 00664 ret_val = -E1000_ERR_NVM; 00665 break; 00666 } 00667 00668 return ret_val; 00669 }
e1000e_update_nvm_checksum_82571 - Update EEPROM checksum : pointer to the HW structure
Updates the EEPROM checksum by reading/adding each word of the EEPROM up to the checksum. Then calculates the EEPROM checksum and writes the value to the EEPROM.
Definition at line 679 of file e1000e_82571.c.
References E1000_EECD_FLUPD, E1000_ERR_NVM, E1000_FLASH_UPDATES, E1000_HICR_FW_RESET, E1000_HICR_FW_RESET_ENABLE, e1000_nvm_flash_hw, E1000_STM_OPCODE, e1000e_update_nvm_checksum_generic(), e1e_flush, er32, ew32, msleep, e1000_hw::nvm, e1000_nvm_info::type, u16, and u32.
Referenced by e1000e_init_nvm_params_82571().
00680 { 00681 u32 eecd; 00682 s32 ret_val; 00683 u16 i; 00684 00685 ret_val = e1000e_update_nvm_checksum_generic(hw); 00686 if (ret_val) 00687 goto out; 00688 00689 /* 00690 * If our nvm is an EEPROM, then we're done 00691 * otherwise, commit the checksum to the flash NVM. 00692 */ 00693 if (hw->nvm.type != e1000_nvm_flash_hw) 00694 goto out; 00695 00696 /* Check for pending operations. */ 00697 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 00698 msleep(1); 00699 if ((er32(EECD) & E1000_EECD_FLUPD) == 0) 00700 break; 00701 } 00702 00703 if (i == E1000_FLASH_UPDATES) { 00704 ret_val = -E1000_ERR_NVM; 00705 goto out; 00706 } 00707 00708 /* Reset the firmware if using STM opcode. */ 00709 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { 00710 /* 00711 * The enabling of and the actual reset must be done 00712 * in two write cycles. 00713 */ 00714 ew32(HICR, E1000_HICR_FW_RESET_ENABLE); 00715 e1e_flush(); 00716 ew32(HICR, E1000_HICR_FW_RESET); 00717 } 00718 00719 /* Commit the write to flash */ 00720 eecd = er32(EECD) | E1000_EECD_FLUPD; 00721 ew32(EECD, eecd); 00722 00723 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 00724 msleep(1); 00725 if ((er32(EECD) & E1000_EECD_FLUPD) == 0) 00726 break; 00727 } 00728 00729 if (i == E1000_FLASH_UPDATES) { 00730 ret_val = -E1000_ERR_NVM; 00731 goto out; 00732 } 00733 00734 out: 00735 return ret_val; 00736 }
e1000e_validate_nvm_checksum_82571 - Validate EEPROM checksum : pointer to the HW structure
Calculates the EEPROM checksum by reading/adding each word of the EEPROM and then verifies that the sum of the EEPROM is equal to 0xBABA.
Definition at line 745 of file e1000e_82571.c.
References e1000_nvm_flash_hw, e1000e_fix_nvm_checksum_82571(), e1000e_validate_nvm_checksum_generic(), e1000_hw::nvm, and e1000_nvm_info::type.
Referenced by e1000e_init_nvm_params_82571().
00746 { 00747 if (hw->nvm.type == e1000_nvm_flash_hw) 00748 e1000e_fix_nvm_checksum_82571(hw); 00749 00750 return e1000e_validate_nvm_checksum_generic(hw); 00751 }
e1000e_get_cfg_done_82571 - Poll for configuration done : pointer to the HW structure
Reads the management control register for the config done bit to be set.
Definition at line 811 of file e1000e_82571.c.
References E1000_ERR_RESET, E1000_NVM_CFG_DONE_PORT_0, E1000_SUCCESS, e_dbg, er32, msleep, PHY_CFG_TIMEOUT, and timeout().
Referenced by e1000e_init_phy_params_82571().
00812 { 00813 s32 timeout = PHY_CFG_TIMEOUT; 00814 s32 ret_val = E1000_SUCCESS; 00815 00816 while (timeout) { 00817 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 00818 break; 00819 msleep(1); 00820 timeout--; 00821 } 00822 if (!timeout) { 00823 e_dbg("MNG configuration cycle has not completed.\n"); 00824 ret_val = -E1000_ERR_RESET; 00825 goto out; 00826 } 00827 00828 out: 00829 return ret_val; 00830 }
e1000e_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state : pointer to the HW structure : true to enable LPLU, false to disable
Sets the LPLU D0 state according to the active flag. When activating LPLU this function also disables smart speed and vice versa. LPLU will not be activated unless the device autonegotiation advertisement meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function pointer entry point only called by PHY setup routines.
Definition at line 843 of file e1000e_82571.c.
References e1000_smart_speed_off, e1000_smart_speed_on, E1000_SUCCESS, e1e_rphy(), e1e_wphy(), IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PSCFR_SMART_SPEED, IGP02E1000_PHY_POWER_MGMT, IGP02E1000_PM_D0_LPLU, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::smart_speed, and u16.
Referenced by e1000e_init_phy_params_82571().
00844 { 00845 struct e1000_phy_info *phy = &hw->phy; 00846 s32 ret_val = E1000_SUCCESS; 00847 u16 data; 00848 00849 if (!(phy->ops.read_reg)) 00850 goto out; 00851 00852 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 00853 if (ret_val) 00854 goto out; 00855 00856 if (active) { 00857 data |= IGP02E1000_PM_D0_LPLU; 00858 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, 00859 data); 00860 if (ret_val) 00861 goto out; 00862 00863 /* When LPLU is enabled, we should disable SmartSpeed */ 00864 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 00865 &data); 00866 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 00867 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 00868 data); 00869 if (ret_val) 00870 goto out; 00871 } else { 00872 data &= ~IGP02E1000_PM_D0_LPLU; 00873 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, 00874 data); 00875 /* 00876 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 00877 * during Dx states where the power conservation is most 00878 * important. During driver activity we should enable 00879 * SmartSpeed, so performance is maintained. 00880 */ 00881 if (phy->smart_speed == e1000_smart_speed_on) { 00882 ret_val = e1e_rphy(hw, 00883 IGP01E1000_PHY_PORT_CONFIG, 00884 &data); 00885 if (ret_val) 00886 goto out; 00887 00888 data |= IGP01E1000_PSCFR_SMART_SPEED; 00889 ret_val = e1e_wphy(hw, 00890 IGP01E1000_PHY_PORT_CONFIG, 00891 data); 00892 if (ret_val) 00893 goto out; 00894 } else if (phy->smart_speed == e1000_smart_speed_off) { 00895 ret_val = e1e_rphy(hw, 00896 IGP01E1000_PHY_PORT_CONFIG, 00897 &data); 00898 if (ret_val) 00899 goto out; 00900 00901 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 00902 ret_val = e1e_wphy(hw, 00903 IGP01E1000_PHY_PORT_CONFIG, 00904 data); 00905 if (ret_val) 00906 goto out; 00907 } 00908 } 00909 00910 out: 00911 return ret_val; 00912 }
e1000e_reset_hw_82571 - Reset hardware : pointer to the HW structure
This resets the hardware into a known state.
Definition at line 920 of file e1000e_82571.c.
References e1000_82573, e1000_82574, e1000_82583, E1000_CTRL_EXT_EE_RST, E1000_CTRL_RST, E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP, e1000_media_type_internal_serdes, e1000_nvm_flash_hw, e1000_serdes_link_down, E1000_TCTL_PSP, e1000e_check_alt_mac_addr_generic(), e1000e_disable_pcie_master(), e1000e_get_auto_rd_done(), e1000e_set_laa_state_82571(), e1e_flush, e_dbg, er32, ew32, e1000_hw::mac, MDIO_OWNERSHIP_TIMEOUT, e1000_phy_info::media_type, msleep, e1000_hw::nvm, e1000_hw::phy, e1000_mac_info::serdes_link_state, e1000_nvm_info::type, e1000_mac_info::type, u16, u32, and udelay().
Referenced by e1000e_init_mac_params_82571().
00921 { 00922 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 00923 s32 ret_val; 00924 u16 i = 0; 00925 00926 /* 00927 * Prevent the PCI-E bus from sticking if there is no TLP connection 00928 * on the last TLP read/write transaction when MAC is reset. 00929 */ 00930 ret_val = e1000e_disable_pcie_master(hw); 00931 if (ret_val) 00932 e_dbg("PCI-E Master disable polling has failed.\n"); 00933 00934 e_dbg("Masking off all interrupts\n"); 00935 ew32(IMC, 0xffffffff); 00936 00937 ew32(RCTL, 0); 00938 ew32(TCTL, E1000_TCTL_PSP); 00939 e1e_flush(); 00940 00941 msleep(10); 00942 00943 /* 00944 * Must acquire the MDIO ownership before MAC reset. 00945 * Ownership defaults to firmware after a reset. 00946 */ 00947 switch (hw->mac.type) { 00948 case e1000_82574: 00949 case e1000_82583: 00950 case e1000_82573: 00951 extcnf_ctrl = er32(EXTCNF_CTRL); 00952 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 00953 00954 do { 00955 ew32(EXTCNF_CTRL, extcnf_ctrl); 00956 extcnf_ctrl = er32(EXTCNF_CTRL); 00957 00958 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 00959 break; 00960 00961 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 00962 00963 msleep(2); 00964 i++; 00965 } while (i < MDIO_OWNERSHIP_TIMEOUT); 00966 break; 00967 default: 00968 break; 00969 } 00970 00971 ctrl = er32(CTRL); 00972 00973 e_dbg("Issuing a global reset to MAC\n"); 00974 ew32(CTRL, ctrl | E1000_CTRL_RST); 00975 00976 if (hw->nvm.type == e1000_nvm_flash_hw) { 00977 udelay(10); 00978 ctrl_ext = er32(CTRL_EXT); 00979 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 00980 ew32(CTRL_EXT, ctrl_ext); 00981 e1e_flush(); 00982 } 00983 00984 ret_val = e1000e_get_auto_rd_done(hw); 00985 if (ret_val) 00986 /* We don't want to continue accessing MAC registers. */ 00987 goto out; 00988 00989 /* 00990 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 00991 * Need to wait for Phy configuration completion before accessing 00992 * NVM and Phy. 00993 */ 00994 00995 switch (hw->mac.type) { 00996 case e1000_82574: 00997 case e1000_82583: 00998 case e1000_82573: 00999 msleep(25); 01000 break; 01001 default: 01002 break; 01003 } 01004 01005 /* Clear any pending interrupt events. */ 01006 ew32(IMC, 0xffffffff); 01007 icr = er32(ICR); 01008 01009 /* Install any alternate MAC address into RAR0 */ 01010 ret_val = e1000e_check_alt_mac_addr_generic(hw); 01011 if (ret_val) 01012 goto out; 01013 01014 e1000e_set_laa_state_82571(hw, true); 01015 01016 /* Reinitialize the 82571 serdes link state machine */ 01017 if (hw->phy.media_type == e1000_media_type_internal_serdes) 01018 hw->mac.serdes_link_state = e1000_serdes_link_down; 01019 01020 out: 01021 return ret_val; 01022 }
e1000e_init_hw_82571 - Initialize hardware : pointer to the HW structure
This inits the hardware readying it for operation.
Definition at line 1030 of file e1000e_82571.c.
References e1000_82573, e1000_82574, e1000_82583, E1000_GCR_L1_ACT_WITHOUT_L0S_RX, E1000_MTA, E1000_TXDCTL_COUNT_DESC, E1000_TXDCTL_FULL_TX_DESC_WB, E1000_TXDCTL_WTHRESH, E1000_WRITE_REG_ARRAY, e1000e_clear_hw_cntrs_82571(), e1000e_clear_vfta(), e1000e_enable_tx_pkt_filtering(), e1000e_get_laa_state_82571(), e1000e_init_rx_addrs(), e1000e_initialize_hw_bits_82571(), e_dbg, er32, ew32, e1000_mac_operations::id_led_init, e1000_hw::mac, e1000_mac_info::mta_reg_count, e1000_mac_info::ops, e1000_mac_info::rar_entry_count, e1000_mac_operations::setup_link, e1000_mac_info::type, u16, and u32.
Referenced by e1000e_init_mac_params_82571().
01031 { 01032 struct e1000_mac_info *mac = &hw->mac; 01033 u32 reg_data; 01034 s32 ret_val; 01035 u16 i, rar_count = mac->rar_entry_count; 01036 01037 e1000e_initialize_hw_bits_82571(hw); 01038 01039 /* Initialize identification LED */ 01040 ret_val = mac->ops.id_led_init(hw); 01041 if (ret_val) { 01042 e_dbg("Error initializing identification LED\n"); 01043 /* This is not fatal and we should not stop init due to this */ 01044 } 01045 01046 /* Disabling VLAN filtering */ 01047 e_dbg("Initializing the IEEE VLAN\n"); 01048 e1000e_clear_vfta(hw); 01049 01050 /* Setup the receive address. */ 01051 /* 01052 * If, however, a locally administered address was assigned to the 01053 * 82571, we must reserve a RAR for it to work around an issue where 01054 * resetting one port will reload the MAC on the other port. 01055 */ 01056 if (e1000e_get_laa_state_82571(hw)) 01057 rar_count--; 01058 e1000e_init_rx_addrs(hw, rar_count); 01059 01060 /* Zero out the Multicast HASH table */ 01061 e_dbg("Zeroing the MTA\n"); 01062 for (i = 0; i < mac->mta_reg_count; i++) 01063 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 01064 01065 /* Setup link and flow control */ 01066 ret_val = mac->ops.setup_link(hw); 01067 01068 /* Set the transmit descriptor write-back policy */ 01069 reg_data = er32(TXDCTL(0)); 01070 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 01071 E1000_TXDCTL_FULL_TX_DESC_WB | 01072 E1000_TXDCTL_COUNT_DESC; 01073 ew32(TXDCTL(0), reg_data); 01074 01075 /* ...for both queues. */ 01076 switch (mac->type) { 01077 case e1000_82574: 01078 case e1000_82583: 01079 case e1000_82573: 01080 #if 0 01081 e1000e_enable_tx_pkt_filtering(hw); 01082 #endif 01083 reg_data = er32(GCR); 01084 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 01085 ew32(GCR, reg_data); 01086 break; 01087 default: 01088 reg_data = er32(TXDCTL(1)); 01089 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 01090 E1000_TXDCTL_FULL_TX_DESC_WB | 01091 E1000_TXDCTL_COUNT_DESC; 01092 ew32(TXDCTL(1), reg_data); 01093 break; 01094 } 01095 01096 /* 01097 * Clear all of the statistics registers (clear on read). It is 01098 * important that we do this after we have tried to establish link 01099 * because the symbol error count will increment wildly if there 01100 * is no link. 01101 */ 01102 e1000e_clear_hw_cntrs_82571(hw); 01103 01104 return ret_val; 01105 }
| static void e1000e_clear_vfta_82571 | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_clear_vfta_82571 - Clear VLAN filter table : pointer to the HW structure
Clears the register array which contains the VLAN filter table by setting all the values to 0.
Definition at line 1236 of file e1000e_82571.c.
References e1000_82573, e1000_82574, e1000_82583, E1000_VFTA, E1000_VFTA_ENTRY_BIT_SHIFT_MASK, E1000_VFTA_ENTRY_MASK, E1000_VFTA_ENTRY_SHIFT, E1000_VLAN_FILTER_TBL_SIZE, E1000_WRITE_REG_ARRAY, e1e_flush, e1000_hw::mac, e1000_hw::mng_cookie, offset, e1000_mac_info::type, u32, and e1000_host_mng_dhcp_cookie::vlan_id.
Referenced by e1000e_init_mac_params_82571().
01237 { 01238 u32 offset; 01239 u32 vfta_value = 0; 01240 u32 vfta_offset = 0; 01241 u32 vfta_bit_in_reg = 0; 01242 01243 switch (hw->mac.type) { 01244 case e1000_82574: 01245 case e1000_82583: 01246 case e1000_82573: 01247 if (hw->mng_cookie.vlan_id != 0) { 01248 /* 01249 *The VFTA is a 4096b bit-field, each identifying 01250 *a single VLAN ID. The following operations 01251 *determine which 32b entry (i.e. offset) into the 01252 *array we want to set the VLAN ID (i.e. bit) of 01253 *the manageability unit. 01254 */ 01255 vfta_offset = (hw->mng_cookie.vlan_id >> 01256 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK; 01257 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 01258 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 01259 } 01260 01261 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 01262 /* 01263 *If the offset we want to clear is the same offset of 01264 *the manageability VLAN ID, then clear all bits except 01265 *that of the manageability unit 01266 */ 01267 vfta_value = (offset == vfta_offset) ? 01268 vfta_bit_in_reg : 0; 01269 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 01270 vfta_value); 01271 e1e_flush(); 01272 } 01273 break; 01274 default: 01275 break; 01276 } 01277 }
Referenced by e1000e_init_mac_params_82571().
e1000e_setup_link_82571 - Setup flow control and link settings : pointer to the HW structure
Determines which flow control settings to use, then configures flow control. Calls the appropriate media-specific link configuration function. Assuming the adapter has a valid link partner, a valid link should be established. Assumes the hardware has previously been reset and the transmitter and receiver are not enabled.
Definition at line 1334 of file e1000e_82571.c.
References e1000_82573, e1000_82574, e1000_82583, e1000_fc_default, e1000_fc_full, e1000e_setup_link(), e1000_hw::fc, e1000_hw::mac, e1000_fc_info::requested_mode, and e1000_mac_info::type.
Referenced by e1000e_init_mac_params_82571().
01335 { 01336 /* 01337 * 82573 does not have a word in the NVM to determine 01338 * the default flow control setting, so we explicitly 01339 * set it to full. 01340 */ 01341 switch (hw->mac.type) { 01342 case e1000_82574: 01343 case e1000_82583: 01344 case e1000_82573: 01345 if (hw->fc.requested_mode == e1000_fc_default) 01346 hw->fc.requested_mode = e1000_fc_full; 01347 break; 01348 default: 01349 break; 01350 } 01351 return e1000e_setup_link(hw); 01352 }
e1000e_setup_copper_link_82571 - Configure copper link settings : pointer to the HW structure
Configures the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called.
Definition at line 1362 of file e1000e_82571.c.
References E1000_CTRL_FRCDPX, E1000_CTRL_FRCSPD, E1000_CTRL_SLU, E1000_ERR_PHY, e1000_phy_bm, e1000_phy_igp_2, e1000_phy_m88, e1000e_copper_link_setup_igp(), e1000e_copper_link_setup_m88(), e1000e_setup_copper_link(), er32, ew32, e1000_hw::phy, e1000_phy_info::type, and u32.
Referenced by e1000e_init_mac_params_82571().
01363 { 01364 u32 ctrl; 01365 s32 ret_val; 01366 01367 ctrl = er32(CTRL); 01368 ctrl |= E1000_CTRL_SLU; 01369 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 01370 ew32(CTRL, ctrl); 01371 01372 switch (hw->phy.type) { 01373 case e1000_phy_m88: 01374 case e1000_phy_bm: 01375 ret_val = e1000e_copper_link_setup_m88(hw); 01376 break; 01377 case e1000_phy_igp_2: 01378 ret_val = e1000e_copper_link_setup_igp(hw); 01379 break; 01380 default: 01381 ret_val = -E1000_ERR_PHY; 01382 break; 01383 } 01384 01385 if (ret_val) 01386 goto out; 01387 01388 ret_val = e1000e_setup_copper_link(hw); 01389 01390 out: 01391 return ret_val; 01392 }
e1000e_check_for_serdes_link_82571 - Check for link (Serdes) : pointer to the HW structure
Reports the link state as up or down.
If autonegotiation is supported by the link partner, the link state is determined by the result of autongotiation. This is the most likely case. If autonegotiation is not supported by the link partner, and the link has a valid signal, force the link up.
The link state is represented internally here by 4 states:
1) down 2) autoneg_progress 3) autoneg_complete (the link sucessfully autonegotiated) 4) forced_up (the link has been forced up, it did not autonegotiate)
Definition at line 1441 of file e1000e_82571.c.
References E1000_CTRL_FD, E1000_CTRL_SLU, E1000_RXCW_C, E1000_RXCW_IV, E1000_RXCW_SYNCH, e1000_serdes_link_autoneg_complete, e1000_serdes_link_autoneg_progress, e1000_serdes_link_down, e1000_serdes_link_forced_up, E1000_STATUS_LU, E1000_SUCCESS, E1000_TXCW_ANE, e1000e_config_fc_after_link_up(), e_dbg, er32, ew32, e1000_hw::mac, e1000_mac_info::serdes_has_link, e1000_mac_info::serdes_link_state, e1000_mac_info::txcw, u32, and udelay().
Referenced by e1000e_init_mac_params_82571().
01442 { 01443 struct e1000_mac_info *mac = &hw->mac; 01444 u32 rxcw; 01445 u32 ctrl; 01446 u32 status; 01447 s32 ret_val = E1000_SUCCESS; 01448 01449 ctrl = er32(CTRL); 01450 status = er32(STATUS); 01451 rxcw = er32(RXCW); 01452 01453 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { 01454 01455 /* Receiver is synchronized with no invalid bits. */ 01456 switch (mac->serdes_link_state) { 01457 case e1000_serdes_link_autoneg_complete: 01458 if (!(status & E1000_STATUS_LU)) { 01459 /* 01460 * We have lost link, retry autoneg before 01461 * reporting link failure 01462 */ 01463 mac->serdes_link_state = 01464 e1000_serdes_link_autoneg_progress; 01465 mac->serdes_has_link = false; 01466 e_dbg("AN_UP -> AN_PROG\n"); 01467 } 01468 break; 01469 01470 case e1000_serdes_link_forced_up: 01471 /* 01472 * If we are receiving /C/ ordered sets, re-enable 01473 * auto-negotiation in the TXCW register and disable 01474 * forced link in the Device Control register in an 01475 * attempt to auto-negotiate with our link partner. 01476 */ 01477 if (rxcw & E1000_RXCW_C) { 01478 /* Enable autoneg, and unforce link up */ 01479 ew32(TXCW, mac->txcw); 01480 ew32(CTRL, 01481 (ctrl & ~E1000_CTRL_SLU)); 01482 mac->serdes_link_state = 01483 e1000_serdes_link_autoneg_progress; 01484 mac->serdes_has_link = false; 01485 e_dbg("FORCED_UP -> AN_PROG\n"); 01486 } 01487 break; 01488 01489 case e1000_serdes_link_autoneg_progress: 01490 if (rxcw & E1000_RXCW_C) { 01491 /* We received /C/ ordered sets, meaning the 01492 * link partner has autonegotiated, and we can 01493 * trust the Link Up (LU) status bit 01494 */ 01495 if (status & E1000_STATUS_LU) { 01496 mac->serdes_link_state = 01497 e1000_serdes_link_autoneg_complete; 01498 e_dbg("AN_PROG -> AN_UP\n"); 01499 mac->serdes_has_link = true; 01500 } else { 01501 /* Autoneg completed, but failed */ 01502 mac->serdes_link_state = 01503 e1000_serdes_link_down; 01504 e_dbg("AN_PROG -> DOWN\n"); 01505 } 01506 } else { 01507 /* The link partner did not autoneg. 01508 * Force link up and full duplex, and change 01509 * state to forced. 01510 */ 01511 ew32(TXCW, 01512 (mac->txcw & ~E1000_TXCW_ANE)); 01513 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 01514 ew32(CTRL, ctrl); 01515 01516 /* Configure Flow Control after link up. */ 01517 ret_val = 01518 e1000e_config_fc_after_link_up(hw); 01519 if (ret_val) { 01520 e_dbg("Error config flow control\n"); 01521 break; 01522 } 01523 mac->serdes_link_state = 01524 e1000_serdes_link_forced_up; 01525 mac->serdes_has_link = true; 01526 e_dbg("AN_PROG -> FORCED_UP\n"); 01527 } 01528 break; 01529 01530 case e1000_serdes_link_down: 01531 default: 01532 /* The link was down but the receiver has now gained 01533 * valid sync, so lets see if we can bring the link 01534 * up. */ 01535 ew32(TXCW, mac->txcw); 01536 ew32(CTRL, 01537 (ctrl & ~E1000_CTRL_SLU)); 01538 mac->serdes_link_state = 01539 e1000_serdes_link_autoneg_progress; 01540 e_dbg("DOWN -> AN_PROG\n"); 01541 break; 01542 } 01543 } else { 01544 if (!(rxcw & E1000_RXCW_SYNCH)) { 01545 mac->serdes_has_link = false; 01546 mac->serdes_link_state = e1000_serdes_link_down; 01547 e_dbg("ANYSTATE -> DOWN\n"); 01548 } else { 01549 /* 01550 * We have sync, and can tolerate one 01551 * invalid (IV) codeword before declaring 01552 * link down, so reread to look again 01553 */ 01554 udelay(10); 01555 rxcw = er32(RXCW); 01556 if (rxcw & E1000_RXCW_IV) { 01557 mac->serdes_link_state = e1000_serdes_link_down; 01558 mac->serdes_has_link = false; 01559 e_dbg("ANYSTATE -> DOWN\n"); 01560 } 01561 } 01562 } 01563 01564 return ret_val; 01565 }
e1000e_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes : pointer to the HW structure
Configures collision distance and flow control for fiber and serdes links. Upon successful setup, poll for link.
Definition at line 1401 of file e1000e_82571.c.
References e1000_82571, e1000_82572, E1000_SCTL_DISABLE_SERDES_LOOPBACK, e1000e_setup_fiber_serdes_link(), ew32, e1000_hw::mac, and e1000_mac_info::type.
Referenced by e1000e_init_mac_params_82571().
01402 { 01403 switch (hw->mac.type) { 01404 case e1000_82571: 01405 case e1000_82572: 01406 /* 01407 * If SerDes loopback mode is entered, there is no form 01408 * of reset to take the adapter out of that mode. So we 01409 * have to explicitly take the adapter out of loopback 01410 * mode. This prevents drivers from twiddling their thumbs 01411 * if another tool failed to take it out of loopback mode. 01412 */ 01413 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 01414 break; 01415 default: 01416 break; 01417 } 01418 01419 return e1000e_setup_fiber_serdes_link(hw); 01420 }
e1000e_valid_led_default_82571 - Verify a valid default LED config : pointer to the HW structure : pointer to the NVM (EEPROM)
Read the EEPROM for the current default LED configuration. If the LED configuration is not valid, set to a valid LED configuration.
Definition at line 1575 of file e1000e_82571.c.
References e1000_82573, e1000_82574, e1000_82583, e1000e_read_nvm(), e_dbg, ID_LED_DEFAULT, ID_LED_DEFAULT_82573, ID_LED_RESERVED_0000, ID_LED_RESERVED_F746, ID_LED_RESERVED_FFFF, e1000_hw::mac, NVM_ID_LED_SETTINGS, and e1000_mac_info::type.
Referenced by e1000e_init_nvm_params_82571().
01576 { 01577 s32 ret_val; 01578 01579 ret_val = e1000e_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 01580 if (ret_val) { 01581 e_dbg("NVM Read Error\n"); 01582 goto out; 01583 } 01584 01585 switch (hw->mac.type) { 01586 case e1000_82574: 01587 case e1000_82583: 01588 case e1000_82573: 01589 if(*data == ID_LED_RESERVED_F746) 01590 *data = ID_LED_DEFAULT_82573; 01591 break; 01592 default: 01593 if (*data == ID_LED_RESERVED_0000 || 01594 *data == ID_LED_RESERVED_FFFF) 01595 *data = ID_LED_DEFAULT; 01596 break; 01597 } 01598 01599 out: 01600 return ret_val; 01601 }
| static void e1000e_clear_hw_cntrs_82571 | ( | struct e1000_hw * | hw | ) | [static] |
Referenced by e1000e_init_hw_82571(), and e1000e_init_mac_params_82571().
e1000e_get_hw_semaphore_82571 - Acquire hardware semaphore : pointer to the HW structure
Acquire the HW semaphore to access the PHY or NVM
Definition at line 518 of file e1000e_82571.c.
References e1000_hw::_82571, e1000_hw::dev_spec, E1000_ERR_NVM, E1000_SUCCESS, E1000_SWSM_SMBI, E1000_SWSM_SWESMBI, e1000e_put_hw_semaphore_82571(), e_dbg, er32, ew32, e1000_hw::nvm, e1000_dev_spec_82571::smb_counter, u32, udelay(), and e1000_nvm_info::word_size.
Referenced by e1000e_acquire_nvm_82571(), and e1000e_init_phy_params_82571().
00519 { 00520 u32 swsm; 00521 s32 ret_val = E1000_SUCCESS; 00522 s32 sw_timeout = hw->nvm.word_size + 1; 00523 s32 fw_timeout = hw->nvm.word_size + 1; 00524 s32 i = 0; 00525 00526 /* 00527 * If we have timedout 3 times on trying to acquire 00528 * the inter-port SMBI semaphore, there is old code 00529 * operating on the other port, and it is not 00530 * releasing SMBI. Modify the number of times that 00531 * we try for the semaphore to interwork with this 00532 * older code. 00533 */ 00534 if (hw->dev_spec._82571.smb_counter > 2) 00535 sw_timeout = 1; 00536 00537 /* Get the SW semaphore */ 00538 while (i < sw_timeout) { 00539 swsm = er32(SWSM); 00540 if (!(swsm & E1000_SWSM_SMBI)) 00541 break; 00542 00543 udelay(50); 00544 i++; 00545 } 00546 00547 if (i == sw_timeout) { 00548 e_dbg("Driver can't access device - SMBI bit is set.\n"); 00549 hw->dev_spec._82571.smb_counter++; 00550 } 00551 /* Get the FW semaphore. */ 00552 for (i = 0; i < fw_timeout; i++) { 00553 swsm = er32(SWSM); 00554 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 00555 00556 /* Semaphore acquired if bit latched */ 00557 if (er32(SWSM) & E1000_SWSM_SWESMBI) 00558 break; 00559 00560 udelay(50); 00561 } 00562 00563 if (i == fw_timeout) { 00564 /* Release semaphores */ 00565 e1000e_put_hw_semaphore_82571(hw); 00566 e_dbg("Driver can't access the NVM\n"); 00567 ret_val = -E1000_ERR_NVM; 00568 goto out; 00569 } 00570 00571 out: 00572 return ret_val; 00573 }
e1000e_fix_nvm_checksum_82571 - Fix EEPROM checksum : pointer to the HW structure
Verifies that the EEPROM has completed the update. After updating the EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If the checksum fix is not implemented, we need to set the bit and update the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, we need to return bad checksum.
Definition at line 1655 of file e1000e_82571.c.
References e1000_nvm_flash_hw, E1000_SUCCESS, e1000e_read_nvm(), e1000e_update_nvm_checksum(), e1000e_write_nvm(), e1000_hw::nvm, e1000_nvm_info::type, and u16.
Referenced by e1000e_validate_nvm_checksum_82571().
01656 { 01657 struct e1000_nvm_info *nvm = &hw->nvm; 01658 s32 ret_val = E1000_SUCCESS; 01659 u16 data; 01660 01661 if (nvm->type != e1000_nvm_flash_hw) 01662 goto out; 01663 01664 /* 01665 * Check bit 4 of word 10h. If it is 0, firmware is done updating 01666 * 10h-12h. Checksum may need to be fixed. 01667 */ 01668 ret_val = e1000e_read_nvm(hw, 0x10, 1, &data); 01669 if (ret_val) 01670 goto out; 01671 01672 if (!(data & 0x10)) { 01673 /* 01674 * Read 0x23 and check bit 15. This bit is a 1 01675 * when the checksum has already been fixed. If 01676 * the checksum is still wrong and this bit is a 01677 * 1, we need to return bad checksum. Otherwise, 01678 * we need to set this bit to a 1 and update the 01679 * checksum. 01680 */ 01681 ret_val = e1000e_read_nvm(hw, 0x23, 1, &data); 01682 if (ret_val) 01683 goto out; 01684 01685 if (!(data & 0x8000)) { 01686 data |= 0x8000; 01687 ret_val = e1000e_write_nvm(hw, 0x23, 1, &data); 01688 if (ret_val) 01689 goto out; 01690 ret_val = e1000e_update_nvm_checksum(hw); 01691 } 01692 } 01693 01694 out: 01695 return ret_val; 01696 }
e1000e_get_phy_id_82571 - Retrieve the PHY ID and revision : pointer to the HW structure
Reads the PHY registers and stores the PHY ID and possibly the PHY revision in the hardware structure.
Definition at line 469 of file e1000e_82571.c.
References e1000_82571, e1000_82572, e1000_82573, e1000_82574, e1000_82583, E1000_ERR_PHY, E1000_SUCCESS, e1000e_get_phy_id(), e1e_rphy(), e1000_phy_info::id, IGP01E1000_I_PHY_ID, e1000_hw::mac, e1000_hw::phy, PHY_ID1, PHY_ID2, PHY_REVISION_MASK, e1000_phy_info::revision, e1000_mac_info::type, u16, u32, and udelay().
Referenced by e1000e_init_phy_params_82571().
00470 { 00471 struct e1000_phy_info *phy = &hw->phy; 00472 s32 ret_val = E1000_SUCCESS; 00473 u16 phy_id = 0; 00474 00475 switch (hw->mac.type) { 00476 case e1000_82571: 00477 case e1000_82572: 00478 /* 00479 * The 82571 firmware may still be configuring the PHY. 00480 * In this case, we cannot access the PHY until the 00481 * configuration is done. So we explicitly set the 00482 * PHY ID. 00483 */ 00484 phy->id = IGP01E1000_I_PHY_ID; 00485 break; 00486 case e1000_82573: 00487 ret_val = e1000e_get_phy_id(hw); 00488 break; 00489 case e1000_82574: 00490 case e1000_82583: 00491 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); 00492 if (ret_val) 00493 goto out; 00494 00495 phy->id = (u32)(phy_id << 16); 00496 udelay(20); 00497 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); 00498 if (ret_val) 00499 goto out; 00500 00501 phy->id |= (u32)(phy_id); 00502 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 00503 break; 00504 default: 00505 ret_val = -E1000_ERR_PHY; 00506 break; 00507 } 00508 out: 00509 return ret_val; 00510 }
| void e1000e_put_hw_semaphore_82571 | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_put_hw_semaphore_82571 - Release hardware semaphore : pointer to the HW structure
Release hardware semaphore used to access the PHY or NVM
Definition at line 581 of file e1000e_82571.c.
References E1000_SWSM_SMBI, E1000_SWSM_SWESMBI, er32, ew32, and u32.
Referenced by e1000e_acquire_nvm_82571(), e1000e_get_hw_semaphore_82571(), e1000e_init_phy_params_82571(), and e1000e_release_nvm_82571().
00582 { 00583 u32 swsm; 00584 00585 swsm = er32(SWSM); 00586 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 00587 ew32(SWSM, swsm); 00588 }
| static void e1000e_initialize_hw_bits_82571 | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_initialize_hw_bits_82571 - Initialize hardware-dependent bits : pointer to the HW structure
Initializes required hardware-dependent bits needed for normal operation.
Definition at line 1113 of file e1000e_82571.c.
References e1000_82571, e1000_82572, e1000_82573, e1000_82574, e1000_82583, E1000_CTRL_EXT_DMA_DYN_CLK_EN, E1000_PBA_ECC_CORR_EN, E1000_TCTL_MULR, er32, ew32, e1000_hw::mac, e1000_mac_info::type, and u32.
Referenced by e1000e_init_hw_82571().
01114 { 01115 u32 reg; 01116 01117 /* Transmit Descriptor Control 0 */ 01118 reg = er32(TXDCTL(0)); 01119 reg |= (1 << 22); 01120 ew32(TXDCTL(0), reg); 01121 01122 /* Transmit Descriptor Control 1 */ 01123 reg = er32(TXDCTL(1)); 01124 reg |= (1 << 22); 01125 ew32(TXDCTL(1), reg); 01126 01127 /* Transmit Arbitration Control 0 */ 01128 reg = er32(TARC(0)); 01129 reg &= ~(0xF << 27); /* 30:27 */ 01130 switch (hw->mac.type) { 01131 case e1000_82571: 01132 case e1000_82572: 01133 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 01134 break; 01135 default: 01136 break; 01137 } 01138 ew32(TARC(0), reg); 01139 01140 /* Transmit Arbitration Control 1 */ 01141 reg = er32(TARC(1)); 01142 switch (hw->mac.type) { 01143 case e1000_82571: 01144 case e1000_82572: 01145 reg &= ~((1 << 29) | (1 << 30)); 01146 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 01147 if (er32(TCTL) & E1000_TCTL_MULR) 01148 reg &= ~(1 << 28); 01149 else 01150 reg |= (1 << 28); 01151 ew32(TARC(1), reg); 01152 break; 01153 default: 01154 break; 01155 } 01156 01157 /* Device Control */ 01158 01159 switch (hw->mac.type) { 01160 case e1000_82574: 01161 case e1000_82583: 01162 case e1000_82573: 01163 reg = er32(CTRL); 01164 reg &= ~(1 << 29); 01165 ew32(CTRL, reg); 01166 break; 01167 default: 01168 break; 01169 } 01170 01171 /* Extended Device Control */ 01172 switch (hw->mac.type) { 01173 case e1000_82574: 01174 case e1000_82583: 01175 case e1000_82573: 01176 reg = er32(CTRL_EXT); 01177 reg &= ~(1 << 23); 01178 reg |= (1 << 22); 01179 ew32(CTRL_EXT, reg); 01180 break; 01181 default: 01182 break; 01183 } 01184 01185 01186 if (hw->mac.type == e1000_82571) { 01187 reg = er32(PBA_ECC); 01188 reg |= E1000_PBA_ECC_CORR_EN; 01189 ew32(PBA_ECC, reg); 01190 } 01191 01192 /* 01193 * Workaround for hardware errata. 01194 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 01195 */ 01196 01197 if ((hw->mac.type == e1000_82571) || 01198 (hw->mac.type == e1000_82572)) { 01199 reg = er32(CTRL_EXT); 01200 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; 01201 ew32(CTRL_EXT, reg); 01202 } 01203 01204 /* PCI-Ex Control Registers */ 01205 01206 switch (hw->mac.type) { 01207 case e1000_82574: 01208 case e1000_82583: 01209 reg = er32(GCR); 01210 reg |= (1 << 22); 01211 ew32(GCR, reg); 01212 /* 01213 * Workaround for hardware errata. 01214 * apply workaround for hardware errata documented in errata 01215 * docs Fixes issue where some error prone or unreliable PCIe 01216 * completions are occurring, particularly with ASPM enabled. 01217 * Without fix, issue can cause tx timeouts. 01218 */ 01219 reg = er32(GCR2); 01220 reg |= 1; 01221 ew32(GCR2, reg); 01222 break; 01223 default: 01224 break; 01225 } 01226 return; 01227 }
| static s32 e1000e_write_nvm_eewr_82571 | ( | struct e1000_hw * | hw, | |
| u16 | offset, | |||
| u16 | words, | |||
| u16 * | data | |||
| ) | [static] |
e1000e_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon : pointer to the HW structure : offset within the EEPROM to be written to : number of words to write : 16 bit word(s) to be written to the EEPROM
After checking for invalid values, poll the EEPROM to ensure the previous command has completed before trying to write the next word. After write poll for completion.
If e1000e_update_nvm_checksum is not called after this function, the EEPROM will most likely contain an invalid checksum.
Definition at line 767 of file e1000e_82571.c.
References E1000_ERR_NVM, E1000_NVM_POLL_WRITE, E1000_NVM_RW_ADDR_SHIFT, E1000_NVM_RW_REG_DATA, E1000_NVM_RW_REG_START, e1000e_poll_eerd_eewr_done(), e_dbg, ew32, e1000_hw::nvm, u32, and e1000_nvm_info::word_size.
Referenced by e1000e_write_nvm_82571().
00769 { 00770 struct e1000_nvm_info *nvm = &hw->nvm; 00771 u32 i, eewr = 0; 00772 s32 ret_val = 0; 00773 00774 /* 00775 * A check for invalid values: offset too large, too many words, 00776 * and not enough words. 00777 */ 00778 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 00779 (words == 0)) { 00780 e_dbg("nvm parameter(s) out of bounds\n"); 00781 ret_val = -E1000_ERR_NVM; 00782 goto out; 00783 } 00784 00785 for (i = 0; i < words; i++) { 00786 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 00787 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 00788 E1000_NVM_RW_REG_START; 00789 00790 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 00791 if (ret_val) 00792 break; 00793 00794 ew32(EEWR, eewr); 00795 00796 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 00797 if (ret_val) 00798 break; 00799 } 00800 00801 out: 00802 return ret_val; 00803 }
e1000e_read_mac_addr_82571 - Read device MAC address : pointer to the HW structure
Definition at line 1702 of file e1000e_82571.c.
References E1000_SUCCESS, e1000e_check_alt_mac_addr_generic(), and e1000e_read_mac_addr_generic().
Referenced by e1000e_init_mac_params_82571().
01703 { 01704 s32 ret_val = E1000_SUCCESS; 01705 01706 /* 01707 * If there's an alternate MAC address place it in RAR0 01708 * so that it will override the Si installed default perm 01709 * address. 01710 */ 01711 ret_val = e1000e_check_alt_mac_addr_generic(hw); 01712 if (ret_val) 01713 goto out; 01714 01715 ret_val = e1000e_read_mac_addr_generic(hw); 01716 01717 out: 01718 return ret_val; 01719 }
| static void e1000e_power_down_phy_copper_82571 | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_power_down_phy_copper_82571 - Remove link during PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, remove the link.
Definition at line 1728 of file e1000e_82571.c.
References e1000_mac_operations::check_mng_mode, e1000_phy_operations::check_reset_block, e1000e_check_reset_block(), e1000e_power_down_phy_copper(), e1000_hw::mac, e1000_mac_info::ops, e1000_phy_info::ops, and e1000_hw::phy.
Referenced by e1000e_init_phy_params_82571().
01729 { 01730 struct e1000_phy_info *phy = &hw->phy; 01731 struct e1000_mac_info *mac = &hw->mac; 01732 01733 if (!(phy->ops.check_reset_block)) 01734 return; 01735 01736 /* If the management interface is not enabled, then power down */ 01737 if (!(mac->ops.check_mng_mode(hw) || e1000e_check_reset_block(hw))) 01738 e1000e_power_down_phy_copper(hw); 01739 01740 return; 01741 }
| void e1000e_init_function_pointers_82571 | ( | struct e1000_hw * | hw | ) |
e1000e_init_function_pointers_82571 - Init func ptrs.
: pointer to the HW structure
Called to initialize all function pointers and parameters.
Definition at line 453 of file e1000e_82571.c.
References e1000e_init_mac_ops_generic(), e1000e_init_mac_params_82571(), e1000e_init_nvm_ops_generic(), e1000e_init_nvm_params_82571(), e1000e_init_phy_params_82571(), e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::nvm, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, and e1000_hw::phy.
00454 { 00455 e1000e_init_mac_ops_generic(hw); 00456 e1000e_init_nvm_ops_generic(hw); 00457 hw->mac.ops.init_params = e1000e_init_mac_params_82571; 00458 hw->nvm.ops.init_params = e1000e_init_nvm_params_82571; 00459 hw->phy.ops.init_params = e1000e_init_phy_params_82571; 00460 }
e1000e_led_on_82574 - Turn LED on : pointer to the HW structure
Turn LED on.
Definition at line 1302 of file e1000e_82571.c.
References E1000_LEDCTL_LED0_IVRT, E1000_LEDCTL_MODE_LED_ON, E1000_STATUS_LU, E1000_SUCCESS, er32, ew32, e1000_mac_info::ledctl_mode2, e1000_hw::mac, and u32.
01303 { 01304 #if 0 01305 u32 ctrl; 01306 u32 i; 01307 01308 ctrl = hw->mac.ledctl_mode2; 01309 if (!(E1000_STATUS_LU & er32(STATUS))) { 01310 /* 01311 * If no link, then turn LED on by setting the invert bit 01312 * for each LED that's "on" (0x0E) in ledctl_mode2. 01313 */ 01314 for (i = 0; i < 4; i++) 01315 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 01316 E1000_LEDCTL_MODE_LED_ON) 01317 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); 01318 } 01319 ew32(LEDCTL, ctrl); 01320 #endif 01321 return E1000_SUCCESS; 01322 }
e1000e_get_laa_state_82571 - Get locally administered address state : pointer to the HW structure
Retrieve and return the current locally administered address state.
Definition at line 1609 of file e1000e_82571.c.
References e1000_hw::_82571, e1000_hw::dev_spec, e1000_82571, e1000_dev_spec_82571::laa_is_present, e1000_hw::mac, and e1000_mac_info::type.
Referenced by e1000e_init_hw_82571().
01610 { 01611 if (hw->mac.type != e1000_82571) 01612 return false; 01613 01614 return hw->dev_spec._82571.laa_is_present; 01615 }
e1000e_set_laa_state_82571 - Set locally administered address state : pointer to the HW structure : enable/disable locally administered address
Enable/Disable the current locally administered address state.
Definition at line 1624 of file e1000e_82571.c.
References e1000_hw::_82571, e1000_mac_info::addr, e1000_hw::dev_spec, e1000_82571, e1000e_rar_set(), e1000_dev_spec_82571::laa_is_present, e1000_hw::mac, e1000_mac_info::rar_entry_count, and e1000_mac_info::type.
Referenced by e1000e_reset_hw_82571().
01625 { 01626 if (hw->mac.type != e1000_82571) 01627 return; 01628 01629 hw->dev_spec._82571.laa_is_present = state; 01630 01631 /* If workaround is activated... */ 01632 if (state) 01633 /* 01634 * Hold a copy of the LAA in RAR[14] This is done so that 01635 * between the time RAR[0] gets clobbered and the time it 01636 * gets fixed, the actual LAA is in one of the RARs and no 01637 * incoming packets directed to this port are dropped. 01638 * Eventually the LAA will be in RAR[0] and RAR[14]. 01639 */ 01640 e1000e_rar_set(hw, hw->mac.addr, 01641 hw->mac.rar_entry_count - 1); 01642 return; 01643 }
e1000e_clear_hw_cntrs_82571 - Clear device specific hardware counters : pointer to the HW structure
Clears the hardware counters by reading the counter registers.
Definition at line 1749 of file e1000e_82571.c.
References e1000e_clear_hw_cntrs_base(), and er32.
01750 { 01751 #if 0 01752 e1000e_clear_hw_cntrs_base(hw); 01753 01754 er32(PRC64); 01755 er32(PRC127); 01756 er32(PRC255); 01757 er32(PRC511); 01758 er32(PRC1023); 01759 er32(PRC1522); 01760 er32(PTC64); 01761 er32(PTC127); 01762 er32(PTC255); 01763 er32(PTC511); 01764 er32(PTC1023); 01765 er32(PTC1522); 01766 01767 er32(ALGNERRC); 01768 er32(RXERRC); 01769 er32(TNCRS); 01770 er32(CEXTERR); 01771 er32(TSCTC); 01772 er32(TSCTFC); 01773 01774 er32(MGTPRC); 01775 er32(MGTPDC); 01776 er32(MGTPTC); 01777 01778 er32(IAC); 01779 er32(ICRXOC); 01780 01781 er32(ICRXPTC); 01782 er32(ICRXATC); 01783 er32(ICTXPTC); 01784 er32(ICTXATC); 01785 er32(ICTXQEC); 01786 er32(ICTXQMTC); 01787 er32(ICRXDMTC); 01788 #endif 01789 }
struct pci_device_id e1000e_82571_nics[] [static] |
Initial value:
{
PCI_ROM(0x8086, 0x105E, "E1000_DEV_ID_82571EB_COPPER", "E1000_DEV_ID_82571EB_COPPER", board_82571),
PCI_ROM(0x8086, 0x105F, "E1000_DEV_ID_82571EB_FIBER", "E1000_DEV_ID_82571EB_FIBER", board_82571),
PCI_ROM(0x8086, 0x10A4, "E1000_DEV_ID_82571EB_QUAD_COPPER", "E1000_DEV_ID_82571EB_QUAD_COPPER", board_82571),
PCI_ROM(0x8086, 0x10BC, "E1000_DEV_ID_82571EB_QUAD_COPPER_LP", "E1000_DEV_ID_82571EB_QUAD_COPPER_LP", board_82571),
PCI_ROM(0x8086, 0x10A5, "E1000_DEV_ID_82571EB_QUAD_FIBER", "E1000_DEV_ID_82571EB_QUAD_FIBER", board_82571),
PCI_ROM(0x8086, 0x1060, "E1000_DEV_ID_82571EB_SERDES", "E1000_DEV_ID_82571EB_SERDES", board_82571),
PCI_ROM(0x8086, 0x10D9, "E1000_DEV_ID_82571EB_SERDES_DUAL", "E1000_DEV_ID_82571EB_SERDES_DUAL", board_82571),
PCI_ROM(0x8086, 0x10DA, "E1000_DEV_ID_82571EB_SERDES_QUAD", "E1000_DEV_ID_82571EB_SERDES_QUAD", board_82571),
PCI_ROM(0x8086, 0x10D5, "E1000_DEV_ID_82571PT_QUAD_COPPER", "E1000_DEV_ID_82571PT_QUAD_COPPER", board_82571),
PCI_ROM(0x8086, 0x10B9, "E1000_DEV_ID_82572EI", "E1000_DEV_ID_82572EI", board_82572),
PCI_ROM(0x8086, 0x107D, "E1000_DEV_ID_82572EI_COPPER", "E1000_DEV_ID_82572EI_COPPER", board_82572),
PCI_ROM(0x8086, 0x107E, "E1000_DEV_ID_82572EI_FIBER", "E1000_DEV_ID_82572EI_FIBER", board_82572),
PCI_ROM(0x8086, 0x107F, "E1000_DEV_ID_82572EI_SERDES", "E1000_DEV_ID_82572EI_SERDES", board_82572),
PCI_ROM(0x8086, 0x108B, "E1000_DEV_ID_82573E", "E1000_DEV_ID_82573E", board_82573),
PCI_ROM(0x8086, 0x108C, "E1000_DEV_ID_82573E_IAMT", "E1000_DEV_ID_82573E_IAMT", board_82573),
PCI_ROM(0x8086, 0x109A, "E1000_DEV_ID_82573L", "E1000_DEV_ID_82573L", board_82573),
PCI_ROM(0x8086, 0x10D3, "E1000_DEV_ID_82574L", "E1000_DEV_ID_82574L", board_82574),
PCI_ROM(0x8086, 0x10F6, "E1000_DEV_ID_82574LA", "E1000_DEV_ID_82574LA", board_82574),
PCI_ROM(0x8086, 0x150C, "E1000_DEV_ID_82583V", "E1000_DEV_ID_82583V", board_82583),
}
Definition at line 1791 of file e1000e_82571.c.
| struct pci_driver e1000e_82571_driver __pci_driver |
Initial value:
{
.ids = e1000e_82571_nics,
.id_count = (sizeof (e1000e_82571_nics) / sizeof (e1000e_82571_nics[0])),
.probe = e1000e_probe,
.remove = e1000e_remove,
}
Definition at line 1813 of file e1000e_82571.c.
1.5.7.1