e1000e_80003es2lan.h

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00001 /*******************************************************************************
00002 
00003   Intel PRO/1000 Linux driver
00004   Copyright(c) 1999 - 2009 Intel Corporation.
00005 
00006   This program is free software; you can redistribute it and/or modify it
00007   under the terms and conditions of the GNU General Public License,
00008   version 2, as published by the Free Software Foundation.
00009 
00010   This program is distributed in the hope it will be useful, but WITHOUT
00011   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
00012   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
00013   more details.
00014 
00015   You should have received a copy of the GNU General Public License along with
00016   this program; if not, write to the Free Software Foundation, Inc.,
00017   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
00018 
00019   The full GNU General Public License is included in this distribution in
00020   the file called "COPYING".
00021 
00022   Contact Information:
00023   Linux NICS <linux.nics@intel.com>
00024   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
00025   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
00026 
00027 *******************************************************************************/
00028 
00029 FILE_LICENCE ( GPL2_OR_LATER );
00030 
00031 #ifndef _E1000E_80003ES2LAN_H_
00032 #define _E1000E_80003ES2LAN_H_
00033 
00034 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
00035 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
00036 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
00037 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
00038 
00039 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
00040 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
00041 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
00042 
00043 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
00044 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
00045 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
00046 
00047 #define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
00048 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
00049 
00050 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
00051 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
00052 
00053 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
00054 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
00055 
00056 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
00057 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disabled */
00058 #define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
00059 #define GG82563_PSCR_CROSSOVER_MODE_MDI         0x0000 /* 00=Manual MDI */
00060 #define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
00061 #define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
00062 
00063 /* PHY Specific Control Register 2 (Page 0, Register 26) */
00064 #define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000
00065                                                /* 1=Reverse Auto-Negotiation */
00066 
00067 /* MAC Specific Control Register (Page 2, Register 21) */
00068 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
00069 #define GG82563_MSCR_TX_CLK_MASK                0x0007
00070 #define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
00071 #define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
00072 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5        0x0006
00073 #define GG82563_MSCR_TX_CLK_1000MBPS_25         0x0007
00074 
00075 #define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
00076 
00077 /* DSP Distance Register (Page 5, Register 26) */
00078 /*
00079  * 0 = <50M
00080  * 1 = 50-80M
00081  * 2 = 80-100M
00082  * 3 = 110-140M
00083  * 4 = >140M
00084  */
00085 #define GG82563_DSPD_CABLE_LENGTH               0x0007
00086 
00087 /* Kumeran Mode Control Register (Page 193, Register 16) */
00088 #define GG82563_KMCR_PASS_FALSE_CARRIER         0x0800
00089 
00090 /* Max number of times Kumeran read/write should be validated */
00091 #define GG82563_MAX_KMRN_RETRY                  0x5
00092 
00093 /* Power Management Control Register (Page 193, Register 20) */
00094 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
00095                                           /* 1=Enable SERDES Electrical Idle */
00096 
00097 /* In-Band Control Register (Page 194, Register 18) */
00098 #define GG82563_ICR_DIS_PADDING                 0x0010 /* Disable Padding */
00099 
00100 #endif

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