#include "e1000e.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| static s32 | e1000e_init_phy_params_80003es2lan (struct e1000_hw *hw) |
| e1000e_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. | |
| static s32 | e1000e_init_nvm_params_80003es2lan (struct e1000_hw *hw) |
| e1000e_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. | |
| static s32 | e1000e_init_mac_params_80003es2lan (struct e1000_hw *hw) |
| e1000e_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. | |
| static s32 | e1000e_acquire_phy_80003es2lan (struct e1000_hw *hw) |
| e1000e_acquire_phy_80003es2lan - Acquire rights to access PHY : pointer to the HW structure | |
| static void | e1000e_release_phy_80003es2lan (struct e1000_hw *hw) |
| e1000e_release_phy_80003es2lan - Release rights to access PHY : pointer to the HW structure | |
| static s32 | e1000e_acquire_nvm_80003es2lan (struct e1000_hw *hw) |
| e1000e_acquire_nvm_80003es2lan - Acquire rights to access NVM : pointer to the HW structure | |
| static void | e1000e_release_nvm_80003es2lan (struct e1000_hw *hw) |
| e1000e_release_nvm_80003es2lan - Relinquish rights to access NVM : pointer to the HW structure | |
| static s32 | e1000e_read_phy_reg_gg82563_80003es2lan (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register : pointer to the HW structure : offset of the register to read : pointer to the data returned from the operation | |
| static s32 | e1000e_write_phy_reg_gg82563_80003es2lan (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register : pointer to the HW structure : offset of the register to read : value to write to the register | |
| static s32 | e1000e_write_nvm_80003es2lan (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| e1000e_write_nvm_80003es2lan - Write to ESB2 NVM : pointer to the HW structure : offset of the register to read : number of words to write : buffer of data to write to the NVM | |
| static s32 | e1000e_get_cfg_done_80003es2lan (struct e1000_hw *hw) |
| e1000e_get_cfg_done_80003es2lan - Wait for configuration to complete : pointer to the HW structure | |
| static s32 | e1000e_get_link_up_info_80003es2lan (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| e1000e_get_link_up_info_80003es2lan - Report speed and duplex : pointer to the HW structure : pointer to speed buffer : pointer to duplex buffer | |
| static s32 | e1000e_reset_hw_80003es2lan (struct e1000_hw *hw) |
| e1000e_reset_hw_80003es2lan - Reset the ESB2 controller : pointer to the HW structure | |
| static s32 | e1000e_init_hw_80003es2lan (struct e1000_hw *hw) |
| e1000e_init_hw_80003es2lan - Initialize the ESB2 controller : pointer to the HW structure | |
| static s32 | e1000e_setup_copper_link_80003es2lan (struct e1000_hw *hw) |
| e1000e_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 : pointer to the HW structure | |
| static void | e1000e_clear_hw_cntrs_80003es2lan (struct e1000_hw *hw) |
| static s32 | e1000e_acquire_swfw_sync_80003es2lan (struct e1000_hw *hw, u16 mask) |
| e1000e_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore : pointer to the HW structure : specifies which semaphore to acquire | |
| static s32 | e1000e_cfg_kmrn_10_100_80003es2lan (struct e1000_hw *hw, u16 duplex) |
| e1000e_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation : pointer to the HW structure : current duplex setting | |
| static s32 | e1000e_cfg_kmrn_1000_80003es2lan (struct e1000_hw *hw) |
| e1000e_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation : pointer to the HW structure | |
| static s32 | e1000e_cfg_on_link_up_80003es2lan (struct e1000_hw *hw) |
| e1000e_cfg_on_link_up_80003es2lan - es2 link configuration after link-up : pointer to the HW structure : current duplex setting | |
| static s32 | e1000e_read_kmrn_reg_80003es2lan (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_kmrn_reg_80003es2lan - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| static s32 | e1000e_write_kmrn_reg_80003es2lan (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_kmrn_reg_80003es2lan - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| static s32 | e1000e_copper_link_setup_gg82563_80003es2lan (struct e1000_hw *hw) |
| e1000e_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link : pointer to the HW structure | |
| static void | e1000e_initialize_hw_bits_80003es2lan (struct e1000_hw *hw) |
| e1000e_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 : pointer to the HW structure | |
| static void | e1000e_release_swfw_sync_80003es2lan (struct e1000_hw *hw, u16 mask) |
| e1000e_release_swfw_sync_80003es2lan - Release SW/FW semaphore : pointer to the HW structure : specifies which semaphore to acquire | |
| static s32 | e1000e_read_mac_addr_80003es2lan (struct e1000_hw *hw) |
| e1000e_read_mac_addr_80003es2lan - Read device MAC address : pointer to the HW structure | |
| static void | e1000e_power_down_phy_copper_80003es2lan (struct e1000_hw *hw) |
| e1000e_power_down_phy_copper_80003es2lan - Remove link during PHY power down : pointer to the HW structure | |
| void | e1000e_init_function_pointers_80003es2lan (struct e1000_hw *hw) |
| e1000e_init_function_pointers_80003es2lan - Init ESB2 func ptrs. | |
| static s32 | e1000e_acquire_mac_csr_80003es2lan (struct e1000_hw *hw) |
| e1000e_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register : pointer to the HW structure | |
| static void | e1000e_release_mac_csr_80003es2lan (struct e1000_hw *hw) |
| e1000e_release_mac_csr_80003es2lan - Release rights to access Kumeran Register : pointer to the HW structure | |
| static void | e1000e_clear_hw_cntrs_80003es2lan (struct e1000_hw *hw __unused) |
| e1000e_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters : pointer to the HW structure | |
Variables | |
| static struct pci_device_id | e1000e_80003es2lan_nics [] |
| struct pci_driver e1000e_80003es2lan_driver | __pci_driver |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
e1000e_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
: pointer to the HW structure
Definition at line 97 of file e1000e_80003es2lan.c.
References e1000_phy_operations::acquire, e1000_phy_info::addr, AUTONEG_ADVERTISE_SPEED_DEFAULT, e1000_phy_info::autoneg_mask, e1000_phy_operations::cfg_on_link_up, e1000_phy_operations::check_polarity, e1000_phy_operations::check_reset_block, e1000_phy_operations::commit, E1000_ERR_PHY, e1000_media_type_copper, e1000_phy_gg82563, e1000_phy_none, E1000_SUCCESS, e1000e_acquire_phy_80003es2lan(), e1000e_cfg_on_link_up_80003es2lan(), e1000e_check_polarity_m88(), e1000e_check_reset_block_generic(), e1000e_get_cfg_done_80003es2lan(), e1000e_get_phy_id(), e1000e_get_phy_info_m88(), e1000e_phy_hw_reset_generic(), e1000e_phy_sw_reset(), e1000e_power_down_phy_copper_80003es2lan(), e1000e_power_up_phy_copper(), e1000e_read_phy_reg_gg82563_80003es2lan(), e1000e_release_phy_80003es2lan(), e1000e_set_d3_lplu_state(), e1000e_write_phy_reg_gg82563_80003es2lan(), e1000_phy_operations::get_cfg_done, e1000_phy_operations::get_info, GG82563_E_PHY_ID, e1000_phy_info::id, e1000_phy_info::media_type, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_down, e1000_phy_operations::power_up, e1000_phy_operations::read_reg, e1000_phy_operations::release, e1000_phy_operations::reset, e1000_phy_info::reset_delay_us, e1000_phy_operations::set_d3_lplu_state, e1000_phy_info::type, and e1000_phy_operations::write_reg.
Referenced by e1000e_init_function_pointers_80003es2lan().
00098 { 00099 struct e1000_phy_info *phy = &hw->phy; 00100 s32 ret_val = E1000_SUCCESS; 00101 00102 if (hw->phy.media_type != e1000_media_type_copper) { 00103 phy->type = e1000_phy_none; 00104 goto out; 00105 } else { 00106 phy->ops.power_up = e1000e_power_up_phy_copper; 00107 phy->ops.power_down = e1000e_power_down_phy_copper_80003es2lan; 00108 } 00109 00110 phy->addr = 1; 00111 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 00112 phy->reset_delay_us = 100; 00113 phy->type = e1000_phy_gg82563; 00114 00115 phy->ops.acquire = e1000e_acquire_phy_80003es2lan; 00116 phy->ops.check_polarity = e1000e_check_polarity_m88; 00117 phy->ops.check_reset_block = e1000e_check_reset_block_generic; 00118 phy->ops.commit = e1000e_phy_sw_reset; 00119 phy->ops.get_cfg_done = e1000e_get_cfg_done_80003es2lan; 00120 phy->ops.get_info = e1000e_get_phy_info_m88; 00121 phy->ops.release = e1000e_release_phy_80003es2lan; 00122 phy->ops.reset = e1000e_phy_hw_reset_generic; 00123 phy->ops.set_d3_lplu_state = e1000e_set_d3_lplu_state; 00124 #if 0 00125 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_80003es2lan; 00126 #endif 00127 #if 0 00128 phy->ops.get_cable_length = e1000e_get_cable_length_80003es2lan; 00129 #endif 00130 phy->ops.read_reg = e1000e_read_phy_reg_gg82563_80003es2lan; 00131 phy->ops.write_reg = e1000e_write_phy_reg_gg82563_80003es2lan; 00132 00133 phy->ops.cfg_on_link_up = e1000e_cfg_on_link_up_80003es2lan; 00134 00135 /* This can only be done after all function pointers are setup. */ 00136 ret_val = e1000e_get_phy_id(hw); 00137 00138 /* Verify phy id */ 00139 if (phy->id != GG82563_E_PHY_ID) { 00140 ret_val = -E1000_ERR_PHY; 00141 goto out; 00142 } 00143 00144 out: 00145 return ret_val; 00146 }
e1000e_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
: pointer to the HW structure
Definition at line 152 of file e1000e_80003es2lan.c.
References e1000_nvm_operations::acquire, e1000_nvm_info::address_bits, e1000_nvm_info::delay_usec, E1000_EECD_ADDR_BITS, E1000_EECD_SIZE_EX_MASK, E1000_EECD_SIZE_EX_SHIFT, e1000_nvm_eeprom_spi, e1000_nvm_override_spi_large, e1000_nvm_override_spi_small, E1000_SUCCESS, e1000e_acquire_nvm_80003es2lan(), e1000e_read_nvm_eerd(), e1000e_release_nvm_80003es2lan(), e1000e_update_nvm_checksum_generic(), e1000e_valid_led_default(), e1000e_validate_nvm_checksum_generic(), e1000e_write_nvm_80003es2lan(), er32, e1000_hw::nvm, NVM_WORD_SIZE_BASE_SHIFT, e1000_nvm_info::opcode_bits, e1000_nvm_info::ops, e1000_nvm_info::override, e1000_nvm_info::page_size, e1000_nvm_operations::read, e1000_nvm_operations::release, size, e1000_nvm_info::type, u16, u32, e1000_nvm_operations::update, e1000_nvm_operations::valid_led_default, e1000_nvm_operations::validate, e1000_nvm_info::word_size, and e1000_nvm_operations::write.
Referenced by e1000e_init_function_pointers_80003es2lan().
00153 { 00154 struct e1000_nvm_info *nvm = &hw->nvm; 00155 u32 eecd = er32(EECD); 00156 u16 size; 00157 00158 nvm->opcode_bits = 8; 00159 nvm->delay_usec = 1; 00160 switch (nvm->override) { 00161 case e1000_nvm_override_spi_large: 00162 nvm->page_size = 32; 00163 nvm->address_bits = 16; 00164 break; 00165 case e1000_nvm_override_spi_small: 00166 nvm->page_size = 8; 00167 nvm->address_bits = 8; 00168 break; 00169 default: 00170 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 00171 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 00172 break; 00173 } 00174 00175 nvm->type = e1000_nvm_eeprom_spi; 00176 00177 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 00178 E1000_EECD_SIZE_EX_SHIFT); 00179 00180 /* 00181 * Added to a constant, "size" becomes the left-shift value 00182 * for setting word_size. 00183 */ 00184 size += NVM_WORD_SIZE_BASE_SHIFT; 00185 00186 /* EEPROM access above 16k is unsupported */ 00187 if (size > 14) 00188 size = 14; 00189 nvm->word_size = 1 << size; 00190 00191 /* Function Pointers */ 00192 nvm->ops.acquire = e1000e_acquire_nvm_80003es2lan; 00193 nvm->ops.read = e1000e_read_nvm_eerd; 00194 nvm->ops.release = e1000e_release_nvm_80003es2lan; 00195 nvm->ops.update = e1000e_update_nvm_checksum_generic; 00196 nvm->ops.valid_led_default = e1000e_valid_led_default; 00197 nvm->ops.validate = e1000e_validate_nvm_checksum_generic; 00198 nvm->ops.write = e1000e_write_nvm_80003es2lan; 00199 00200 return E1000_SUCCESS; 00201 }
e1000e_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
: pointer to the HW structure
Definition at line 207 of file e1000e_80003es2lan.c.
References e1000_mac_info::arc_subsystem_valid, e1000_mac_info::asf_firmware_present, e1000_mac_operations::blink_led, e1000_mac_operations::check_for_link, e1000_mac_operations::check_mng_mode, e1000_mac_operations::cleanup_led, e1000_mac_operations::clear_hw_cntrs, e1000_mac_operations::clear_vfta, e1000_hw::device_id, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, E1000_ERR_CONFIG, E1000_FWSM_MODE_MASK, e1000_media_type_copper, e1000_media_type_fiber, e1000_media_type_internal_serdes, E1000_RAR_ENTRIES, E1000_SUCCESS, e1000e_blink_led(), e1000e_check_for_copper_link(), e1000e_check_for_fiber_link(), e1000e_check_for_serdes_link(), e1000e_check_mng_mode_generic(), e1000e_cleanup_led_generic(), e1000e_clear_hw_cntrs_80003es2lan(), e1000e_clear_vfta_generic(), e1000e_get_bus_info_pcie(), e1000e_get_link_up_info_80003es2lan(), e1000e_id_led_init(), e1000e_init_hw_80003es2lan(), e1000e_led_off_generic(), e1000e_led_on_generic(), e1000e_mta_set_generic(), e1000e_read_mac_addr_80003es2lan(), e1000e_reset_hw_80003es2lan(), e1000e_setup_copper_link_80003es2lan(), e1000e_setup_fiber_serdes_link(), e1000e_setup_led_generic(), e1000e_setup_link(), e1000e_update_mc_addr_list_generic(), e1000e_write_vfta_generic(), er32, e1000_mac_operations::get_bus_info, e1000_mac_operations::get_link_up_info, e1000_mac_operations::id_led_init, e1000_mac_operations::init_hw, e1000_mac_operations::led_off, e1000_mac_operations::led_on, e1000_hw::mac, e1000_phy_info::media_type, e1000_mac_info::mta_reg_count, e1000_mac_operations::mta_set, e1000_mac_info::ops, e1000_hw::phy, e1000_mac_info::rar_entry_count, e1000_mac_operations::read_mac_addr, e1000_mac_operations::reset_hw, e1000_mac_operations::set_lan_id, e1000_mac_operations::setup_led, e1000_mac_operations::setup_link, e1000_mac_operations::setup_physical_interface, e1000_mac_operations::update_mc_addr_list, and e1000_mac_operations::write_vfta.
Referenced by e1000e_init_function_pointers_80003es2lan().
00208 { 00209 struct e1000_mac_info *mac = &hw->mac; 00210 s32 ret_val = E1000_SUCCESS; 00211 00212 /* Set media type */ 00213 switch (hw->device_id) { 00214 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 00215 hw->phy.media_type = e1000_media_type_internal_serdes; 00216 break; 00217 default: 00218 hw->phy.media_type = e1000_media_type_copper; 00219 break; 00220 } 00221 00222 /* Set mta register count */ 00223 mac->mta_reg_count = 128; 00224 /* Set rar entry count */ 00225 mac->rar_entry_count = E1000_RAR_ENTRIES; 00226 /* Set if part includes ASF firmware */ 00227 mac->asf_firmware_present = true; 00228 /* Set if manageability features are enabled. */ 00229 mac->arc_subsystem_valid = 00230 (er32(FWSM) & E1000_FWSM_MODE_MASK) 00231 ? true : false; 00232 00233 /* Function pointers */ 00234 00235 /* bus type/speed/width */ 00236 mac->ops.get_bus_info = e1000e_get_bus_info_pcie; 00237 /* reset */ 00238 mac->ops.reset_hw = e1000e_reset_hw_80003es2lan; 00239 /* hw initialization */ 00240 mac->ops.init_hw = e1000e_init_hw_80003es2lan; 00241 /* link setup */ 00242 mac->ops.setup_link = e1000e_setup_link; 00243 /* physical interface link setup */ 00244 mac->ops.setup_physical_interface = 00245 (hw->phy.media_type == e1000_media_type_copper) 00246 ? e1000e_setup_copper_link_80003es2lan 00247 : e1000e_setup_fiber_serdes_link; 00248 /* check for link */ 00249 switch (hw->phy.media_type) { 00250 case e1000_media_type_copper: 00251 mac->ops.check_for_link = e1000e_check_for_copper_link; 00252 break; 00253 case e1000_media_type_fiber: 00254 mac->ops.check_for_link = e1000e_check_for_fiber_link; 00255 break; 00256 case e1000_media_type_internal_serdes: 00257 mac->ops.check_for_link = e1000e_check_for_serdes_link; 00258 break; 00259 default: 00260 ret_val = -E1000_ERR_CONFIG; 00261 goto out; 00262 break; 00263 } 00264 /* check management mode */ 00265 #if 0 00266 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic; 00267 #endif 00268 /* multicast address update */ 00269 mac->ops.update_mc_addr_list = e1000e_update_mc_addr_list_generic; 00270 /* writing VFTA */ 00271 mac->ops.write_vfta = e1000e_write_vfta_generic; 00272 /* clearing VFTA */ 00273 mac->ops.clear_vfta = e1000e_clear_vfta_generic; 00274 /* setting MTA */ 00275 mac->ops.mta_set = e1000e_mta_set_generic; 00276 /* read mac address */ 00277 mac->ops.read_mac_addr = e1000e_read_mac_addr_80003es2lan; 00278 /* ID LED init */ 00279 mac->ops.id_led_init = e1000e_id_led_init; 00280 /* blink LED */ 00281 mac->ops.blink_led = e1000e_blink_led; 00282 /* setup LED */ 00283 mac->ops.setup_led = e1000e_setup_led_generic; 00284 /* cleanup LED */ 00285 mac->ops.cleanup_led = e1000e_cleanup_led_generic; 00286 /* turn on/off LED */ 00287 mac->ops.led_on = e1000e_led_on_generic; 00288 mac->ops.led_off = e1000e_led_off_generic; 00289 /* clear hardware counters */ 00290 mac->ops.clear_hw_cntrs = e1000e_clear_hw_cntrs_80003es2lan; 00291 /* link info */ 00292 mac->ops.get_link_up_info = e1000e_get_link_up_info_80003es2lan; 00293 00294 /* set lan id for port to determine which phy lock to use */ 00295 hw->mac.ops.set_lan_id(hw); 00296 00297 out: 00298 return ret_val; 00299 }
e1000e_acquire_phy_80003es2lan - Acquire rights to access PHY : pointer to the HW structure
A wrapper to acquire access rights to the correct PHY.
Definition at line 322 of file e1000e_80003es2lan.c.
References e1000_hw::bus, E1000_SWFW_PHY0_SM, E1000_SWFW_PHY1_SM, e1000e_acquire_swfw_sync_80003es2lan(), e1000_bus_info::func, and u16.
Referenced by e1000e_init_phy_params_80003es2lan(), e1000e_read_phy_reg_gg82563_80003es2lan(), e1000e_reset_hw_80003es2lan(), and e1000e_write_phy_reg_gg82563_80003es2lan().
00323 { 00324 u16 mask; 00325 00326 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 00327 return e1000e_acquire_swfw_sync_80003es2lan(hw, mask); 00328 }
| static void e1000e_release_phy_80003es2lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_release_phy_80003es2lan - Release rights to access PHY : pointer to the HW structure
A wrapper to release access rights to the correct PHY.
Definition at line 336 of file e1000e_80003es2lan.c.
References e1000_hw::bus, E1000_SWFW_PHY0_SM, E1000_SWFW_PHY1_SM, e1000e_release_swfw_sync_80003es2lan(), e1000_bus_info::func, and u16.
Referenced by e1000e_init_phy_params_80003es2lan(), e1000e_read_phy_reg_gg82563_80003es2lan(), e1000e_reset_hw_80003es2lan(), and e1000e_write_phy_reg_gg82563_80003es2lan().
00337 { 00338 u16 mask; 00339 00340 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 00341 e1000e_release_swfw_sync_80003es2lan(hw, mask); 00342 }
e1000e_acquire_nvm_80003es2lan - Acquire rights to access NVM : pointer to the HW structure
Acquire the semaphore to access the EEPROM.
Definition at line 381 of file e1000e_80003es2lan.c.
References E1000_SWFW_EEP_SM, e1000e_acquire_nvm(), e1000e_acquire_swfw_sync_80003es2lan(), and e1000e_release_swfw_sync_80003es2lan().
Referenced by e1000e_init_nvm_params_80003es2lan().
00382 { 00383 s32 ret_val; 00384 00385 ret_val = e1000e_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 00386 if (ret_val) 00387 goto out; 00388 00389 ret_val = e1000e_acquire_nvm(hw); 00390 00391 if (ret_val) 00392 e1000e_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 00393 00394 out: 00395 return ret_val; 00396 }
| static void e1000e_release_nvm_80003es2lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_release_nvm_80003es2lan - Relinquish rights to access NVM : pointer to the HW structure
Release the semaphore used to access the EEPROM.
Definition at line 404 of file e1000e_80003es2lan.c.
References E1000_SWFW_EEP_SM, e1000e_release_nvm(), and e1000e_release_swfw_sync_80003es2lan().
Referenced by e1000e_init_nvm_params_80003es2lan().
00405 { 00406 e1000e_release_nvm(hw); 00407 e1000e_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 00408 }
| static s32 e1000e_read_phy_reg_gg82563_80003es2lan | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u16 * | data | |||
| ) | [static] |
e1000e_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register : pointer to the HW structure : offset of the register to read : pointer to the data returned from the operation
Read the GG82563 PHY register.
Definition at line 490 of file e1000e_80003es2lan.c.
References e1000_hw::_80003es2lan, e1000_hw::dev_spec, E1000_ERR_PHY, e1000e_acquire_phy_80003es2lan(), e1000e_read_phy_reg_mdic(), e1000e_release_phy_80003es2lan(), e1000e_write_phy_reg_mdic(), GG82563_MIN_ALT_REG, GG82563_PAGE_SHIFT, GG82563_PHY_PAGE_SELECT, GG82563_PHY_PAGE_SELECT_ALT, MAX_PHY_REG_ADDRESS, e1000_dev_spec_80003es2lan::mdic_wa_enable, u16, u32, and udelay().
Referenced by e1000e_init_phy_params_80003es2lan().
00492 { 00493 s32 ret_val; 00494 u32 page_select; 00495 u16 temp; 00496 00497 ret_val = e1000e_acquire_phy_80003es2lan(hw); 00498 if (ret_val) 00499 goto out; 00500 00501 /* Select Configuration Page */ 00502 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 00503 page_select = GG82563_PHY_PAGE_SELECT; 00504 } else { 00505 /* 00506 * Use Alternative Page Select register to access 00507 * registers 30 and 31 00508 */ 00509 page_select = GG82563_PHY_PAGE_SELECT_ALT; 00510 } 00511 00512 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 00513 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); 00514 if (ret_val) { 00515 e1000e_release_phy_80003es2lan(hw); 00516 goto out; 00517 } 00518 00519 if (hw->dev_spec._80003es2lan.mdic_wa_enable == true) { 00520 /* 00521 * The "ready" bit in the MDIC register may be incorrectly set 00522 * before the device has completed the "Page Select" MDI 00523 * transaction. So we wait 200us after each MDI command... 00524 */ 00525 udelay(200); 00526 00527 /* ...and verify the command was successful. */ 00528 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); 00529 00530 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 00531 ret_val = -E1000_ERR_PHY; 00532 e1000e_release_phy_80003es2lan(hw); 00533 goto out; 00534 } 00535 00536 udelay(200); 00537 00538 ret_val = e1000e_read_phy_reg_mdic(hw, 00539 MAX_PHY_REG_ADDRESS & offset, 00540 data); 00541 00542 udelay(200); 00543 } else 00544 ret_val = e1000e_read_phy_reg_mdic(hw, 00545 MAX_PHY_REG_ADDRESS & offset, 00546 data); 00547 00548 e1000e_release_phy_80003es2lan(hw); 00549 00550 out: 00551 return ret_val; 00552 }
| static s32 e1000e_write_phy_reg_gg82563_80003es2lan | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u16 | data | |||
| ) | [static] |
e1000e_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register : pointer to the HW structure : offset of the register to read : value to write to the register
Write to the GG82563 PHY register.
Definition at line 562 of file e1000e_80003es2lan.c.
References e1000_hw::_80003es2lan, e1000_hw::dev_spec, E1000_ERR_PHY, e1000e_acquire_phy_80003es2lan(), e1000e_read_phy_reg_mdic(), e1000e_release_phy_80003es2lan(), e1000e_write_phy_reg_mdic(), GG82563_MIN_ALT_REG, GG82563_PAGE_SHIFT, GG82563_PHY_PAGE_SELECT, GG82563_PHY_PAGE_SELECT_ALT, MAX_PHY_REG_ADDRESS, e1000_dev_spec_80003es2lan::mdic_wa_enable, u16, u32, and udelay().
Referenced by e1000e_init_phy_params_80003es2lan().
00564 { 00565 s32 ret_val; 00566 u32 page_select; 00567 u16 temp; 00568 00569 ret_val = e1000e_acquire_phy_80003es2lan(hw); 00570 if (ret_val) 00571 goto out; 00572 00573 /* Select Configuration Page */ 00574 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 00575 page_select = GG82563_PHY_PAGE_SELECT; 00576 } else { 00577 /* 00578 * Use Alternative Page Select register to access 00579 * registers 30 and 31 00580 */ 00581 page_select = GG82563_PHY_PAGE_SELECT_ALT; 00582 } 00583 00584 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 00585 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); 00586 if (ret_val) { 00587 e1000e_release_phy_80003es2lan(hw); 00588 goto out; 00589 } 00590 00591 if (hw->dev_spec._80003es2lan.mdic_wa_enable == true) { 00592 /* 00593 * The "ready" bit in the MDIC register may be incorrectly set 00594 * before the device has completed the "Page Select" MDI 00595 * transaction. So we wait 200us after each MDI command... 00596 */ 00597 udelay(200); 00598 00599 /* ...and verify the command was successful. */ 00600 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); 00601 00602 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 00603 ret_val = -E1000_ERR_PHY; 00604 e1000e_release_phy_80003es2lan(hw); 00605 goto out; 00606 } 00607 00608 udelay(200); 00609 00610 ret_val = e1000e_write_phy_reg_mdic(hw, 00611 MAX_PHY_REG_ADDRESS & offset, 00612 data); 00613 00614 udelay(200); 00615 } else 00616 ret_val = e1000e_write_phy_reg_mdic(hw, 00617 MAX_PHY_REG_ADDRESS & offset, 00618 data); 00619 00620 e1000e_release_phy_80003es2lan(hw); 00621 00622 out: 00623 return ret_val; 00624 }
| static s32 e1000e_write_nvm_80003es2lan | ( | struct e1000_hw * | hw, | |
| u16 | offset, | |||
| u16 | words, | |||
| u16 * | data | |||
| ) | [static] |
e1000e_write_nvm_80003es2lan - Write to ESB2 NVM : pointer to the HW structure : offset of the register to read : number of words to write : buffer of data to write to the NVM
Write "words" of data to the ESB2 NVM.
Definition at line 635 of file e1000e_80003es2lan.c.
References e1000e_write_nvm_spi().
Referenced by e1000e_init_nvm_params_80003es2lan().
00637 { 00638 return e1000e_write_nvm_spi(hw, offset, words, data); 00639 }
e1000e_get_cfg_done_80003es2lan - Wait for configuration to complete : pointer to the HW structure
Wait a specific amount of time for manageability processes to complete. This is a function pointer entry point called by the phy module.
Definition at line 648 of file e1000e_80003es2lan.c.
References e1000_hw::bus, E1000_ERR_RESET, E1000_NVM_CFG_DONE_PORT_0, E1000_NVM_CFG_DONE_PORT_1, E1000_SUCCESS, e_dbg, er32, e1000_bus_info::func, msleep, PHY_CFG_TIMEOUT, timeout(), and u32.
Referenced by e1000e_init_phy_params_80003es2lan().
00649 { 00650 s32 timeout = PHY_CFG_TIMEOUT; 00651 s32 ret_val = E1000_SUCCESS; 00652 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 00653 00654 if (hw->bus.func == 1) 00655 mask = E1000_NVM_CFG_DONE_PORT_1; 00656 00657 while (timeout) { 00658 if (er32(EEMNGCTL) & mask) 00659 break; 00660 msleep(1); 00661 timeout--; 00662 } 00663 if (!timeout) { 00664 e_dbg("MNG configuration cycle has not completed.\n"); 00665 ret_val = -E1000_ERR_RESET; 00666 goto out; 00667 } 00668 00669 out: 00670 return ret_val; 00671 }
| static s32 e1000e_get_link_up_info_80003es2lan | ( | struct e1000_hw * | hw, | |
| u16 * | speed, | |||
| u16 * | duplex | |||
| ) | [static] |
e1000e_get_link_up_info_80003es2lan - Report speed and duplex : pointer to the HW structure : pointer to speed buffer : pointer to duplex buffer
Retrieve the current speed and duplex configuration.
Definition at line 817 of file e1000e_80003es2lan.c.
References e1000_phy_operations::cfg_on_link_up, e1000_media_type_copper, e1000e_get_speed_and_duplex_copper(), e1000e_get_speed_and_duplex_fiber_serdes(), e1000_phy_info::media_type, e1000_phy_info::ops, and e1000_hw::phy.
Referenced by e1000e_init_mac_params_80003es2lan().
00819 { 00820 s32 ret_val; 00821 00822 if (hw->phy.media_type == e1000_media_type_copper) { 00823 ret_val = e1000e_get_speed_and_duplex_copper(hw, 00824 speed, 00825 duplex); 00826 hw->phy.ops.cfg_on_link_up(hw); 00827 } else { 00828 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, 00829 speed, 00830 duplex); 00831 } 00832 00833 return ret_val; 00834 }
e1000e_reset_hw_80003es2lan - Reset the ESB2 controller : pointer to the HW structure
Perform a global reset to the ESB2 controller.
Definition at line 842 of file e1000e_80003es2lan.c.
References E1000_CTRL_RST, E1000_TCTL_PSP, e1000e_acquire_phy_80003es2lan(), e1000e_check_alt_mac_addr_generic(), e1000e_disable_pcie_master(), e1000e_get_auto_rd_done(), e1000e_release_phy_80003es2lan(), e1e_flush, e_dbg, er32, ew32, msleep, and u32.
Referenced by e1000e_init_mac_params_80003es2lan().
00843 { 00844 u32 ctrl, icr; 00845 s32 ret_val; 00846 00847 /* 00848 * Prevent the PCI-E bus from sticking if there is no TLP connection 00849 * on the last TLP read/write transaction when MAC is reset. 00850 */ 00851 ret_val = e1000e_disable_pcie_master(hw); 00852 if (ret_val) 00853 e_dbg("PCI-E Master disable polling has failed.\n"); 00854 00855 e_dbg("Masking off all interrupts\n"); 00856 ew32(IMC, 0xffffffff); 00857 00858 ew32(RCTL, 0); 00859 ew32(TCTL, E1000_TCTL_PSP); 00860 e1e_flush(); 00861 00862 msleep(10); 00863 00864 ctrl = er32(CTRL); 00865 00866 ret_val = e1000e_acquire_phy_80003es2lan(hw); 00867 e_dbg("Issuing a global reset to MAC\n"); 00868 ew32(CTRL, ctrl | E1000_CTRL_RST); 00869 e1000e_release_phy_80003es2lan(hw); 00870 00871 ret_val = e1000e_get_auto_rd_done(hw); 00872 if (ret_val) 00873 /* We don't want to continue accessing MAC registers. */ 00874 goto out; 00875 00876 /* Clear any pending interrupt events. */ 00877 ew32(IMC, 0xffffffff); 00878 icr = er32(ICR); 00879 00880 ret_val = e1000e_check_alt_mac_addr_generic(hw); 00881 00882 out: 00883 return ret_val; 00884 }
e1000e_init_hw_80003es2lan - Initialize the ESB2 controller : pointer to the HW structure
Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
Definition at line 892 of file e1000e_80003es2lan.c.
References e1000_hw::_80003es2lan, DEFAULT_TCTL_EXT_GCEX_80003ES2LAN, DEFAULT_TIPG_IPGT_1000_80003ES2LAN, e1000_hw::dev_spec, E1000_FFLT, E1000_KMRNCTRLSTA_OFFSET, E1000_KMRNCTRLSTA_OFFSET_SHIFT, E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO, E1000_KMRNCTRLSTA_OPMODE_MASK, E1000_MTA, E1000_READ_REG_ARRAY, E1000_TCTL_EXT_GCEX_MASK, E1000_TCTL_RTLC, E1000_TIPG_IPGT_MASK, E1000_TXDCTL_COUNT_DESC, E1000_TXDCTL_FULL_TX_DESC_WB, E1000_TXDCTL_WTHRESH, E1000_WRITE_REG_ARRAY, e1000e_clear_hw_cntrs_80003es2lan(), e1000e_clear_vfta(), e1000e_init_rx_addrs(), e1000e_initialize_hw_bits_80003es2lan(), e1000e_read_kmrn_reg_80003es2lan(), e_dbg, er32, ew32, e1000_mac_operations::id_led_init, e1000_hw::mac, e1000_dev_spec_80003es2lan::mdic_wa_enable, e1000_mac_info::mta_reg_count, e1000_mac_info::ops, e1000_mac_info::rar_entry_count, e1000_mac_operations::setup_link, u16, and u32.
Referenced by e1000e_init_mac_params_80003es2lan().
00893 { 00894 struct e1000_mac_info *mac = &hw->mac; 00895 u32 reg_data; 00896 s32 ret_val; 00897 u16 i; 00898 00899 e1000e_initialize_hw_bits_80003es2lan(hw); 00900 00901 /* Initialize identification LED */ 00902 ret_val = mac->ops.id_led_init(hw); 00903 if (ret_val) { 00904 e_dbg("Error initializing identification LED\n"); 00905 /* This is not fatal and we should not stop init due to this */ 00906 } 00907 00908 /* Disabling VLAN filtering */ 00909 e_dbg("Initializing the IEEE VLAN\n"); 00910 e1000e_clear_vfta(hw); 00911 00912 /* Setup the receive address. */ 00913 e1000e_init_rx_addrs(hw, mac->rar_entry_count); 00914 00915 /* Zero out the Multicast HASH table */ 00916 e_dbg("Zeroing the MTA\n"); 00917 for (i = 0; i < mac->mta_reg_count; i++) 00918 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 00919 00920 /* Setup link and flow control */ 00921 ret_val = mac->ops.setup_link(hw); 00922 00923 /* Set the transmit descriptor write-back policy */ 00924 reg_data = er32(TXDCTL(0)); 00925 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 00926 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 00927 ew32(TXDCTL(0), reg_data); 00928 00929 /* ...for both queues. */ 00930 reg_data = er32(TXDCTL(1)); 00931 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 00932 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 00933 ew32(TXDCTL(1), reg_data); 00934 00935 /* Enable retransmit on late collisions */ 00936 reg_data = er32(TCTL); 00937 reg_data |= E1000_TCTL_RTLC; 00938 ew32(TCTL, reg_data); 00939 00940 /* Configure Gigabit Carry Extend Padding */ 00941 reg_data = er32(TCTL_EXT); 00942 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 00943 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 00944 ew32(TCTL_EXT, reg_data); 00945 00946 /* Configure Transmit Inter-Packet Gap */ 00947 reg_data = er32(TIPG); 00948 reg_data &= ~E1000_TIPG_IPGT_MASK; 00949 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 00950 ew32(TIPG, reg_data); 00951 00952 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 00953 reg_data &= ~0x00100000; 00954 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 00955 00956 /* default to true to enable the MDIC W/A */ 00957 hw->dev_spec._80003es2lan.mdic_wa_enable = true; 00958 00959 ret_val = e1000e_read_kmrn_reg_80003es2lan(hw, 00960 E1000_KMRNCTRLSTA_OFFSET >> 00961 E1000_KMRNCTRLSTA_OFFSET_SHIFT, 00962 &i); 00963 if (!ret_val) { 00964 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 00965 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 00966 hw->dev_spec._80003es2lan.mdic_wa_enable = false; 00967 } 00968 00969 /* 00970 * Clear all of the statistics registers (clear on read). It is 00971 * important that we do this after we have tried to establish link 00972 * because the symbol error count will increment wildly if there 00973 * is no link. 00974 */ 00975 e1000e_clear_hw_cntrs_80003es2lan(hw); 00976 00977 return ret_val; 00978 }
e1000e_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 : pointer to the HW structure
Essentially a wrapper for setting up all things "copper" related. This is a function pointer entry point called by the mac module.
Definition at line 1183 of file e1000e_80003es2lan.c.
References E1000_CTRL_FRCDPX, E1000_CTRL_FRCSPD, E1000_CTRL_SLU, E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, e1000e_copper_link_setup_gg82563_80003es2lan(), e1000e_read_kmrn_reg_80003es2lan(), e1000e_setup_copper_link(), e1000e_write_kmrn_reg_80003es2lan(), er32, ew32, GG82563_REG, u16, and u32.
Referenced by e1000e_init_mac_params_80003es2lan().
01184 { 01185 u32 ctrl; 01186 s32 ret_val; 01187 u16 reg_data; 01188 01189 ctrl = er32(CTRL); 01190 ctrl |= E1000_CTRL_SLU; 01191 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 01192 ew32(CTRL, ctrl); 01193 01194 /* 01195 * Set the mac to wait the maximum time between each 01196 * iteration and increase the max iterations when 01197 * polling the phy; this fixes erroneous timeouts at 10Mbps. 01198 */ 01199 ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 01200 0xFFFF); 01201 if (ret_val) 01202 goto out; 01203 ret_val = e1000e_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 01204 ®_data); 01205 if (ret_val) 01206 goto out; 01207 reg_data |= 0x3F; 01208 ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 01209 reg_data); 01210 if (ret_val) 01211 goto out; 01212 ret_val = e1000e_read_kmrn_reg_80003es2lan(hw, 01213 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 01214 ®_data); 01215 if (ret_val) 01216 goto out; 01217 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 01218 ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, 01219 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 01220 reg_data); 01221 if (ret_val) 01222 goto out; 01223 01224 ret_val = e1000e_copper_link_setup_gg82563_80003es2lan(hw); 01225 if (ret_val) 01226 goto out; 01227 01228 ret_val = e1000e_setup_copper_link(hw); 01229 01230 out: 01231 return ret_val; 01232 }
| static void e1000e_clear_hw_cntrs_80003es2lan | ( | struct e1000_hw * | hw | ) | [static] |
Referenced by e1000e_init_hw_80003es2lan(), and e1000e_init_mac_params_80003es2lan().
e1000e_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore : pointer to the HW structure : specifies which semaphore to acquire
Acquire the SW/FW semaphore to access the PHY or NVM. The mask will also specify which port we're acquiring the lock for.
Definition at line 418 of file e1000e_80003es2lan.c.
References E1000_ERR_SWFW_SYNC, E1000_SUCCESS, e1000e_get_hw_semaphore(), e1000e_put_hw_semaphore(), e_dbg, er32, ew32, mdelay(), timeout(), and u32.
Referenced by e1000e_acquire_mac_csr_80003es2lan(), e1000e_acquire_nvm_80003es2lan(), and e1000e_acquire_phy_80003es2lan().
00419 { 00420 u32 swfw_sync; 00421 u32 swmask = mask; 00422 u32 fwmask = mask << 16; 00423 s32 ret_val = E1000_SUCCESS; 00424 s32 i = 0, timeout = 50; 00425 00426 while (i < timeout) { 00427 if (e1000e_get_hw_semaphore(hw)) { 00428 ret_val = -E1000_ERR_SWFW_SYNC; 00429 goto out; 00430 } 00431 00432 swfw_sync = er32(SW_FW_SYNC); 00433 if (!(swfw_sync & (fwmask | swmask))) 00434 break; 00435 00436 /* 00437 * Firmware currently using resource (fwmask) 00438 * or other software thread using resource (swmask) 00439 */ 00440 e1000e_put_hw_semaphore(hw); 00441 mdelay(5); 00442 i++; 00443 } 00444 00445 if (i == timeout) { 00446 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 00447 ret_val = -E1000_ERR_SWFW_SYNC; 00448 goto out; 00449 } 00450 00451 swfw_sync |= swmask; 00452 ew32(SW_FW_SYNC, swfw_sync); 00453 00454 e1000e_put_hw_semaphore(hw); 00455 00456 out: 00457 return ret_val; 00458 }
e1000e_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation : pointer to the HW structure : current duplex setting
Configure the KMRN interface by applying last minute quirks for 10/100 operation.
Definition at line 1273 of file e1000e_80003es2lan.c.
References DEFAULT_TIPG_IPGT_10_100_80003ES2LAN, E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, E1000_SUCCESS, E1000_TIPG_IPGT_MASK, e1000e_write_kmrn_reg_80003es2lan(), e1e_rphy(), e1e_wphy(), er32, ew32, GG82563_KMCR_PASS_FALSE_CARRIER, GG82563_MAX_KMRN_RETRY, GG82563_PHY_KMRN_MODE_CTRL, HALF_DUPLEX, u16, and u32.
Referenced by e1000e_cfg_on_link_up_80003es2lan().
01274 { 01275 s32 ret_val = E1000_SUCCESS; 01276 u32 tipg; 01277 u32 i = 0; 01278 u16 reg_data, reg_data2; 01279 01280 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 01281 ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, 01282 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 01283 reg_data); 01284 if (ret_val) 01285 goto out; 01286 01287 /* Configure Transmit Inter-Packet Gap */ 01288 tipg = er32(TIPG); 01289 tipg &= ~E1000_TIPG_IPGT_MASK; 01290 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 01291 ew32(TIPG, tipg); 01292 01293 01294 do { 01295 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 01296 ®_data); 01297 if (ret_val) 01298 goto out; 01299 01300 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 01301 ®_data2); 01302 if (ret_val) 01303 goto out; 01304 i++; 01305 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 01306 01307 if (duplex == HALF_DUPLEX) 01308 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 01309 else 01310 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 01311 01312 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 01313 01314 out: 01315 return ret_val; 01316 }
e1000e_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation : pointer to the HW structure
Configure the KMRN interface by applying last minute quirks for gigabit operation.
Definition at line 1325 of file e1000e_80003es2lan.c.
References DEFAULT_TIPG_IPGT_1000_80003ES2LAN, E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, E1000_SUCCESS, E1000_TIPG_IPGT_MASK, e1000e_write_kmrn_reg_80003es2lan(), e1e_rphy(), e1e_wphy(), er32, ew32, GG82563_KMCR_PASS_FALSE_CARRIER, GG82563_MAX_KMRN_RETRY, GG82563_PHY_KMRN_MODE_CTRL, u16, and u32.
Referenced by e1000e_cfg_on_link_up_80003es2lan().
01326 { 01327 s32 ret_val = E1000_SUCCESS; 01328 u16 reg_data, reg_data2; 01329 u32 tipg; 01330 u32 i = 0; 01331 01332 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 01333 ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, 01334 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 01335 reg_data); 01336 if (ret_val) 01337 goto out; 01338 01339 /* Configure Transmit Inter-Packet Gap */ 01340 tipg = er32(TIPG); 01341 tipg &= ~E1000_TIPG_IPGT_MASK; 01342 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 01343 ew32(TIPG, tipg); 01344 01345 01346 do { 01347 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 01348 ®_data); 01349 if (ret_val) 01350 goto out; 01351 01352 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 01353 ®_data2); 01354 if (ret_val) 01355 goto out; 01356 i++; 01357 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 01358 01359 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 01360 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 01361 01362 out: 01363 return ret_val; 01364 }
e1000e_cfg_on_link_up_80003es2lan - es2 link configuration after link-up : pointer to the HW structure : current duplex setting
Configure the KMRN interface by applying last minute quirks for 10/100 operation.
Definition at line 1242 of file e1000e_80003es2lan.c.
References e1000_media_type_copper, E1000_SUCCESS, e1000e_cfg_kmrn_1000_80003es2lan(), e1000e_cfg_kmrn_10_100_80003es2lan(), e1000e_get_speed_and_duplex_copper(), e1000_phy_info::media_type, e1000_hw::phy, SPEED_1000, and u16.
Referenced by e1000e_init_phy_params_80003es2lan().
01243 { 01244 s32 ret_val = E1000_SUCCESS; 01245 u16 speed; 01246 u16 duplex; 01247 01248 if (hw->phy.media_type == e1000_media_type_copper) { 01249 ret_val = e1000e_get_speed_and_duplex_copper(hw, 01250 &speed, 01251 &duplex); 01252 if (ret_val) 01253 goto out; 01254 01255 if (speed == SPEED_1000) 01256 ret_val = e1000e_cfg_kmrn_1000_80003es2lan(hw); 01257 else 01258 ret_val = e1000e_cfg_kmrn_10_100_80003es2lan(hw, duplex); 01259 } 01260 01261 out: 01262 return ret_val; 01263 }
| static s32 e1000e_read_kmrn_reg_80003es2lan | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u16 * | data | |||
| ) | [static] |
e1000e_read_kmrn_reg_80003es2lan - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquire semaphore, then read the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Release the semaphore before exiting.
Definition at line 1376 of file e1000e_80003es2lan.c.
References E1000_KMRNCTRLSTA_OFFSET, E1000_KMRNCTRLSTA_OFFSET_SHIFT, E1000_KMRNCTRLSTA_REN, E1000_SUCCESS, e1000e_acquire_mac_csr_80003es2lan(), e1000e_release_mac_csr_80003es2lan(), er32, ew32, u16, u32, and udelay().
Referenced by e1000e_copper_link_setup_gg82563_80003es2lan(), e1000e_init_hw_80003es2lan(), and e1000e_setup_copper_link_80003es2lan().
01378 { 01379 u32 kmrnctrlsta; 01380 s32 ret_val = E1000_SUCCESS; 01381 01382 ret_val = e1000e_acquire_mac_csr_80003es2lan(hw); 01383 if (ret_val) 01384 goto out; 01385 01386 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 01387 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 01388 ew32(KMRNCTRLSTA, kmrnctrlsta); 01389 01390 udelay(2); 01391 01392 kmrnctrlsta = er32(KMRNCTRLSTA); 01393 *data = (u16)kmrnctrlsta; 01394 01395 e1000e_release_mac_csr_80003es2lan(hw); 01396 01397 out: 01398 return ret_val; 01399 }
| static s32 e1000e_write_kmrn_reg_80003es2lan | ( | struct e1000_hw * | hw, | |
| u32 | offset, | |||
| u16 | data | |||
| ) | [static] |
e1000e_write_kmrn_reg_80003es2lan - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquire semaphore, then write the data to PHY register at the offset using the kumeran interface. Release semaphore before exiting.
Definition at line 1411 of file e1000e_80003es2lan.c.
References E1000_KMRNCTRLSTA_OFFSET, E1000_KMRNCTRLSTA_OFFSET_SHIFT, E1000_SUCCESS, e1000e_acquire_mac_csr_80003es2lan(), e1000e_release_mac_csr_80003es2lan(), ew32, u32, and udelay().
Referenced by e1000e_cfg_kmrn_1000_80003es2lan(), e1000e_cfg_kmrn_10_100_80003es2lan(), e1000e_copper_link_setup_gg82563_80003es2lan(), and e1000e_setup_copper_link_80003es2lan().
01413 { 01414 u32 kmrnctrlsta; 01415 s32 ret_val = E1000_SUCCESS; 01416 01417 ret_val = e1000e_acquire_mac_csr_80003es2lan(hw); 01418 if (ret_val) 01419 goto out; 01420 01421 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 01422 E1000_KMRNCTRLSTA_OFFSET) | data; 01423 ew32(KMRNCTRLSTA, kmrnctrlsta); 01424 01425 udelay(2); 01426 01427 e1000e_release_mac_csr_80003es2lan(hw); 01428 01429 out: 01430 return ret_val; 01431 }
e1000e_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link : pointer to the HW structure
Setup some GG82563 PHY registers for obtaining link
Definition at line 1024 of file e1000e_80003es2lan.c.
References e1000_mac_operations::check_mng_mode, e1000_phy_info::disable_polarity_correction, E1000_CTRL_EXT_LINK_MODE_MASK, E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS, E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, E1000_KMRNCTRLSTA_OPMODE_E_IDLE, e1000e_commit_phy(), e1000e_read_kmrn_reg_80003es2lan(), e1000e_write_kmrn_reg_80003es2lan(), e1e_rphy(), e1e_wphy(), e_dbg, er32, ew32, GG82563_ICR_DIS_PADDING, GG82563_KMCR_PASS_FALSE_CARRIER, GG82563_MSCR_ASSERT_CRS_ON_TX, GG82563_MSCR_TX_CLK_1000MBPS_25, GG82563_PHY_INBAND_CTRL, GG82563_PHY_KMRN_MODE_CTRL, GG82563_PHY_MAC_SPEC_CTRL, GG82563_PHY_PWR_MGMT_CTRL, GG82563_PHY_SPEC_CTRL, GG82563_PHY_SPEC_CTRL_2, GG82563_PMCR_ENABLE_ELECTRICAL_IDLE, GG82563_PSCR2_REVERSE_AUTO_NEG, GG82563_PSCR_CROSSOVER_MODE_AUTO, GG82563_PSCR_CROSSOVER_MODE_MASK, GG82563_PSCR_CROSSOVER_MODE_MDI, GG82563_PSCR_CROSSOVER_MODE_MDIX, GG82563_PSCR_POLARITY_REVERSAL_DISABLE, e1000_hw::mac, e1000_phy_info::mdix, e1000_mac_info::ops, e1000_hw::phy, e1000_phy_info::reset_disable, u16, and u32.
Referenced by e1000e_setup_copper_link_80003es2lan().
01025 { 01026 struct e1000_phy_info *phy = &hw->phy; 01027 s32 ret_val; 01028 u32 ctrl_ext; 01029 u16 data; 01030 01031 if (!phy->reset_disable) { 01032 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, 01033 &data); 01034 if (ret_val) 01035 goto out; 01036 01037 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 01038 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 01039 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 01040 01041 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, 01042 data); 01043 if (ret_val) 01044 goto out; 01045 01046 /* 01047 * Options: 01048 * MDI/MDI-X = 0 (default) 01049 * 0 - Auto for all speeds 01050 * 1 - MDI mode 01051 * 2 - MDI-X mode 01052 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 01053 */ 01054 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); 01055 if (ret_val) 01056 goto out; 01057 01058 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 01059 01060 switch (phy->mdix) { 01061 case 1: 01062 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 01063 break; 01064 case 2: 01065 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 01066 break; 01067 case 0: 01068 default: 01069 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 01070 break; 01071 } 01072 01073 /* 01074 * Options: 01075 * disable_polarity_correction = 0 (default) 01076 * Automatic Correction for Reversed Cable Polarity 01077 * 0 - Disabled 01078 * 1 - Enabled 01079 */ 01080 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 01081 if (phy->disable_polarity_correction) 01082 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 01083 01084 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); 01085 if (ret_val) 01086 goto out; 01087 01088 /* SW Reset the PHY so all changes take effect */ 01089 ret_val = e1000e_commit_phy(hw); 01090 if (ret_val) { 01091 e_dbg("Error Resetting the PHY\n"); 01092 goto out; 01093 } 01094 01095 } 01096 01097 /* Bypass Rx and Tx FIFO's */ 01098 ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, 01099 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 01100 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 01101 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 01102 if (ret_val) 01103 goto out; 01104 01105 ret_val = e1000e_read_kmrn_reg_80003es2lan(hw, 01106 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 01107 &data); 01108 if (ret_val) 01109 goto out; 01110 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 01111 ret_val = e1000e_write_kmrn_reg_80003es2lan(hw, 01112 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 01113 data); 01114 if (ret_val) 01115 goto out; 01116 01117 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); 01118 if (ret_val) 01119 goto out; 01120 01121 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 01122 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); 01123 if (ret_val) 01124 goto out; 01125 01126 ctrl_ext = er32(CTRL_EXT); 01127 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 01128 ew32(CTRL_EXT, ctrl_ext); 01129 01130 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 01131 if (ret_val) 01132 goto out; 01133 01134 /* 01135 * Do not init these registers when the HW is in IAMT mode, since the 01136 * firmware will have already initialized them. We only initialize 01137 * them if the HW is not in IAMT mode. 01138 */ 01139 if (!(hw->mac.ops.check_mng_mode(hw))) { 01140 /* Enable Electrical Idle on the PHY */ 01141 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 01142 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, 01143 data); 01144 if (ret_val) 01145 goto out; 01146 01147 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 01148 &data); 01149 if (ret_val) 01150 goto out; 01151 01152 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 01153 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, 01154 data); 01155 if (ret_val) 01156 goto out; 01157 } 01158 01159 /* 01160 * Workaround: Disable padding in Kumeran interface in the MAC 01161 * and in the PHY to avoid CRC errors. 01162 */ 01163 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); 01164 if (ret_val) 01165 goto out; 01166 01167 data |= GG82563_ICR_DIS_PADDING; 01168 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); 01169 if (ret_val) 01170 goto out; 01171 01172 out: 01173 return ret_val; 01174 }
| static void e1000e_initialize_hw_bits_80003es2lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 : pointer to the HW structure
Initializes required hardware-dependent bits needed for normal operation.
Definition at line 986 of file e1000e_80003es2lan.c.
References e1000_media_type_copper, E1000_TCTL_MULR, er32, ew32, e1000_phy_info::media_type, e1000_hw::phy, and u32.
Referenced by e1000e_init_hw_80003es2lan().
00987 { 00988 u32 reg; 00989 00990 /* Transmit Descriptor Control 0 */ 00991 reg = er32(TXDCTL(0)); 00992 reg |= (1 << 22); 00993 ew32(TXDCTL(0), reg); 00994 00995 /* Transmit Descriptor Control 1 */ 00996 reg = er32(TXDCTL(1)); 00997 reg |= (1 << 22); 00998 ew32(TXDCTL(1), reg); 00999 01000 /* Transmit Arbitration Control 0 */ 01001 reg = er32(TARC(0)); 01002 reg &= ~(0xF << 27); /* 30:27 */ 01003 if (hw->phy.media_type != e1000_media_type_copper) 01004 reg &= ~(1 << 20); 01005 ew32(TARC(0), reg); 01006 01007 /* Transmit Arbitration Control 1 */ 01008 reg = er32(TARC(1)); 01009 if (er32(TCTL) & E1000_TCTL_MULR) 01010 reg &= ~(1 << 28); 01011 else 01012 reg |= (1 << 28); 01013 ew32(TARC(1), reg); 01014 01015 return; 01016 }
e1000e_release_swfw_sync_80003es2lan - Release SW/FW semaphore : pointer to the HW structure : specifies which semaphore to acquire
Release the SW/FW semaphore used to access the PHY or NVM. The mask will also specify which port we're releasing the lock for.
Definition at line 468 of file e1000e_80003es2lan.c.
References E1000_SUCCESS, e1000e_get_hw_semaphore(), e1000e_put_hw_semaphore(), er32, ew32, and u32.
Referenced by e1000e_acquire_nvm_80003es2lan(), e1000e_release_mac_csr_80003es2lan(), e1000e_release_nvm_80003es2lan(), and e1000e_release_phy_80003es2lan().
00469 { 00470 u32 swfw_sync; 00471 00472 while (e1000e_get_hw_semaphore(hw) != E1000_SUCCESS) 00473 ; /* Empty */ 00474 00475 swfw_sync = er32(SW_FW_SYNC); 00476 swfw_sync &= ~mask; 00477 ew32(SW_FW_SYNC, swfw_sync); 00478 00479 e1000e_put_hw_semaphore(hw); 00480 }
e1000e_read_mac_addr_80003es2lan - Read device MAC address : pointer to the HW structure
Definition at line 1437 of file e1000e_80003es2lan.c.
References E1000_SUCCESS, e1000e_check_alt_mac_addr_generic(), and e1000e_read_mac_addr_generic().
Referenced by e1000e_init_mac_params_80003es2lan().
01438 { 01439 s32 ret_val = E1000_SUCCESS; 01440 01441 /* 01442 * If there's an alternate MAC address place it in RAR0 01443 * so that it will override the Si installed default perm 01444 * address. 01445 */ 01446 ret_val = e1000e_check_alt_mac_addr_generic(hw); 01447 if (ret_val) 01448 goto out; 01449 01450 ret_val = e1000e_read_mac_addr_generic(hw); 01451 01452 out: 01453 return ret_val; 01454 }
| static void e1000e_power_down_phy_copper_80003es2lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_power_down_phy_copper_80003es2lan - Remove link during PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, remove the link.
Definition at line 1463 of file e1000e_80003es2lan.c.
References e1000_mac_operations::check_mng_mode, e1000e_check_reset_block(), e1000e_power_down_phy_copper(), e1000_hw::mac, and e1000_mac_info::ops.
Referenced by e1000e_init_phy_params_80003es2lan().
01464 { 01465 /* If the management interface is not enabled, then power down */ 01466 if (!(hw->mac.ops.check_mng_mode(hw) || 01467 e1000e_check_reset_block(hw))) 01468 e1000e_power_down_phy_copper(hw); 01469 01470 return; 01471 }
| void e1000e_init_function_pointers_80003es2lan | ( | struct e1000_hw * | hw | ) |
e1000e_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
: pointer to the HW structure
Called to initialize all function pointers and parameters.
Definition at line 307 of file e1000e_80003es2lan.c.
References e1000e_init_mac_ops_generic(), e1000e_init_mac_params_80003es2lan(), e1000e_init_nvm_ops_generic(), e1000e_init_nvm_params_80003es2lan(), e1000e_init_phy_params_80003es2lan(), e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::nvm, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, and e1000_hw::phy.
00308 { 00309 e1000e_init_mac_ops_generic(hw); 00310 e1000e_init_nvm_ops_generic(hw); 00311 hw->mac.ops.init_params = e1000e_init_mac_params_80003es2lan; 00312 hw->nvm.ops.init_params = e1000e_init_nvm_params_80003es2lan; 00313 hw->phy.ops.init_params = e1000e_init_phy_params_80003es2lan; 00314 }
e1000e_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register : pointer to the HW structure
Acquire the semaphore to access the Kumeran interface.
Definition at line 351 of file e1000e_80003es2lan.c.
References E1000_SWFW_CSR_SM, e1000e_acquire_swfw_sync_80003es2lan(), and u16.
Referenced by e1000e_read_kmrn_reg_80003es2lan(), and e1000e_write_kmrn_reg_80003es2lan().
00352 { 00353 u16 mask; 00354 00355 mask = E1000_SWFW_CSR_SM; 00356 00357 return e1000e_acquire_swfw_sync_80003es2lan(hw, mask); 00358 }
| static void e1000e_release_mac_csr_80003es2lan | ( | struct e1000_hw * | hw | ) | [static] |
e1000e_release_mac_csr_80003es2lan - Release rights to access Kumeran Register : pointer to the HW structure
Release the semaphore used to access the Kumeran interface
Definition at line 366 of file e1000e_80003es2lan.c.
References E1000_SWFW_CSR_SM, e1000e_release_swfw_sync_80003es2lan(), and u16.
Referenced by e1000e_read_kmrn_reg_80003es2lan(), and e1000e_write_kmrn_reg_80003es2lan().
00367 { 00368 u16 mask; 00369 00370 mask = E1000_SWFW_CSR_SM; 00371 00372 e1000e_release_swfw_sync_80003es2lan(hw, mask); 00373 }
e1000e_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters : pointer to the HW structure
Clears the hardware counters by reading the counter registers.
Definition at line 1479 of file e1000e_80003es2lan.c.
References e1000e_clear_hw_cntrs_base(), and er32.
01480 { 01481 #if 0 01482 e1000e_clear_hw_cntrs_base(hw); 01483 01484 er32(PRC64); 01485 er32(PRC127); 01486 er32(PRC255); 01487 er32(PRC511); 01488 er32(PRC1023); 01489 er32(PRC1522); 01490 er32(PTC64); 01491 er32(PTC127); 01492 er32(PTC255); 01493 er32(PTC511); 01494 er32(PTC1023); 01495 er32(PTC1522); 01496 01497 er32(ALGNERRC); 01498 er32(RXERRC); 01499 er32(TNCRS); 01500 er32(CEXTERR); 01501 er32(TSCTC); 01502 er32(TSCTFC); 01503 01504 er32(MGTPRC); 01505 er32(MGTPDC); 01506 er32(MGTPTC); 01507 01508 er32(IAC); 01509 er32(ICRXOC); 01510 01511 er32(ICRXPTC); 01512 er32(ICRXATC); 01513 er32(ICTXPTC); 01514 er32(ICTXATC); 01515 er32(ICTXQEC); 01516 er32(ICTXQMTC); 01517 er32(ICRXDMTC); 01518 #endif 01519 }
struct pci_device_id e1000e_80003es2lan_nics[] [static] |
Initial value:
{
PCI_ROM(0x8086, 0x1096, "E1000_DEV_ID_80003ES2LAN_COPPER_DPT", "E1000_DEV_ID_80003ES2LAN_COPPER_DPT", board_80003es2lan),
PCI_ROM(0x8086, 0x10BA, "E1000_DEV_ID_80003ES2LAN_COPPER_SPT", "E1000_DEV_ID_80003ES2LAN_COPPER_SPT", board_80003es2lan),
PCI_ROM(0x8086, 0x1098, "E1000_DEV_ID_80003ES2LAN_SERDES_DPT", "E1000_DEV_ID_80003ES2LAN_SERDES_DPT", board_80003es2lan),
PCI_ROM(0x8086, 0x10BB, "E1000_DEV_ID_80003ES2LAN_SERDES_SPT", "E1000_DEV_ID_80003ES2LAN_SERDES_SPT", board_80003es2lan),
}
Definition at line 1521 of file e1000e_80003es2lan.c.
| struct pci_driver e1000e_80003es2lan_driver __pci_driver |
Initial value:
{
.ids = e1000e_80003es2lan_nics,
.id_count = (sizeof (e1000e_80003es2lan_nics) / sizeof (e1000e_80003es2lan_nics[0])),
.probe = e1000e_probe,
.remove = e1000e_remove,
}
Definition at line 1528 of file e1000e_80003es2lan.c.
1.5.7.1