#include <stdint.h>#include <stdlib.h>#include <stdio.h>#include <string.h>#include <unistd.h>#include <gpxe/io.h>#include <errno.h>#include <byteswap.h>#include <gpxe/pci.h>#include <gpxe/malloc.h>#include <gpxe/if_ether.h>#include <gpxe/ethernet.h>#include <gpxe/iobuf.h>#include <gpxe/netdevice.h>#include "e1000e_hw.h"Go to the source code of this file.
Data Structures | |
| struct | e1000_adapter |
| struct | e1000_info |
Defines | |
| #define | u8 unsigned char |
| #define | bool boolean_t |
| #define | dma_addr_t unsigned long |
| #define | __le16 uint16_t |
| #define | __le32 uint32_t |
| #define | __le64 uint64_t |
| #define | __iomem |
| #define | msleep(x) mdelay(x) |
| #define | ETH_FCS_LEN 4 |
| #define | E1000_TX_FLAGS_CSUM 0x00000001 |
| #define | E1000_TX_FLAGS_VLAN 0x00000002 |
| #define | E1000_TX_FLAGS_TSO 0x00000004 |
| #define | E1000_TX_FLAGS_IPV4 0x00000008 |
| #define | E1000_TX_FLAGS_VLAN_MASK 0xffff0000 |
| #define | E1000_TX_FLAGS_VLAN_SHIFT 16 |
| #define | E1000_MAX_PER_TXD 8192 |
| #define | E1000_MAX_TXD_PWR 12 |
| #define | MINIMUM_DHCP_PACKET_SIZE 282 |
| #define | e_dbg(arg...) if (0) { printf (arg); }; |
| #define | E1000_MAX_INTR 10 |
| #define | E1000_DEFAULT_TXD 256 |
| #define | E1000_MAX_TXD 4096 |
| #define | E1000_MIN_TXD 64 |
| #define | E1000_DEFAULT_RXD 256 |
| #define | E1000_MAX_RXD 4096 |
| #define | E1000_MIN_RXD 64 |
| #define | E1000_MIN_ITR_USECS 10 |
| #define | E1000_MAX_ITR_USECS 10000 |
| #define | E1000_ERT_2048 0x100 |
| #define | E1000_FC_PAUSE_TIME 0x0680 |
| #define | E1000_RX_BUFFER_WRITE 16 |
| #define | AUTO_ALL_MODES 0 |
| #define | E1000_EEPROM_APME 0x0400 |
| #define | E1000_MNG_VLAN_NONE (-1) |
| #define | PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) |
| #define | MAXIMUM_ETHERNET_VLAN_SIZE 1522 |
| #define | DEFAULT_JUMBO 9234 |
| #define | NUM_TX_DESC 8 |
| #define | NUM_RX_DESC 8 |
| #define | FLAG_HAS_AMT (1 << 0) |
| #define | FLAG_HAS_FLASH (1 << 1) |
| #define | FLAG_HAS_HW_VLAN_FILTER (1 << 2) |
| #define | FLAG_HAS_WOL (1 << 3) |
| #define | FLAG_HAS_ERT (1 << 4) |
| #define | FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) |
| #define | FLAG_HAS_SWSM_ON_LOAD (1 << 6) |
| #define | FLAG_HAS_JUMBO_FRAMES (1 << 7) |
| #define | FLAG_IS_ICH (1 << 9) |
| #define | FLAG_HAS_SMART_POWER_DOWN (1 << 11) |
| #define | FLAG_IS_QUAD_PORT_A (1 << 12) |
| #define | FLAG_IS_QUAD_PORT (1 << 13) |
| #define | FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14) |
| #define | FLAG_APME_IN_WUC (1 << 15) |
| #define | FLAG_APME_IN_CTRL3 (1 << 16) |
| #define | FLAG_APME_CHECK_PORT_B (1 << 17) |
| #define | FLAG_DISABLE_FC_PAUSE_TIME (1 << 18) |
| #define | FLAG_NO_WAKE_UCAST (1 << 19) |
| #define | FLAG_MNG_PT_ENABLED (1 << 20) |
| #define | FLAG_RESET_OVERWRITES_LAA (1 << 21) |
| #define | FLAG_TARC_SPEED_MODE_BIT (1 << 22) |
| #define | FLAG_TARC_SET_BIT_ZERO (1 << 23) |
| #define | FLAG_RX_NEEDS_RESTART (1 << 24) |
| #define | FLAG_LSC_GIG_SPEED_DROP (1 << 25) |
| #define | FLAG_SMART_POWER_DOWN (1 << 26) |
| #define | FLAG_MSI_ENABLED (1 << 27) |
| #define | FLAG_RX_CSUM_ENABLED (1 << 28) |
| #define | FLAG_TSO_FORCE (1 << 29) |
| #define | FLAG_RX_RESTART_NOW (1 << 30) |
| #define | FLAG_MSI_TEST_FAILED (1 << 31) |
| #define | FLAG2_CRC_STRIPPING (1 << 0) |
| #define | FLAG2_HAS_PHY_WAKEUP (1 << 1) |
| #define | E1000_RX_DESC_PS(R, i) (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) |
| #define | E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) |
| #define | E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc) |
| #define | E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc) |
| #define | E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc) |
| #define | er32(reg) __er32(hw, E1000_##reg) |
| #define | ew32(reg, val) __ew32(hw, E1000_##reg, (val)) |
| #define | e1e_flush() er32(STATUS) |
| #define | E1000_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + reg)) |
| #define | E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg)) |
| #define | E1000_WRITE_REG_ARRAY(a, reg, offset, value) writel((value), ((a)->hw_addr + reg + ((offset) << 2))) |
| #define | E1000_READ_REG_ARRAY(a, reg, offset) |
| #define | E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY |
| #define | E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY |
| #define | er16flash(reg) __er16flash(hw, (reg)) |
| #define | er32flash(reg) __er32flash(hw, (reg)) |
| #define | ew16flash(reg, val) __ew16flash(hw, (reg), (val)) |
| #define | ew32flash(reg, val) __ew32flash(hw, (reg), (val)) |
Typedefs | |
| typedef int | spinlock_t |
Enumerations | |
| enum | boolean_t { false = 0, true = 1, false = 0, true = 1, false = 0, true = 1 } |
| enum | e1000_boards { board_82571, board_82572, board_82573, board_82574, board_80003es2lan, board_ich8lan, board_ich9lan, board_ich10lan, board_pchlan, board_82583 } |
| enum | e1000_state_t { __E1000E_TESTING, __E1000E_RESETTING, __E1000E_DOWN } |
| enum | latency_range { lowest_latency = 0, low_latency = 1, bulk_latency = 2, latency_invalid = 255 } |
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| void | e1000e_check_options (struct e1000_adapter *adapter) |
| void | e1000e_reset (struct e1000_adapter *adapter) |
| e1000e_reset - bring the hardware into a known good state | |
| void | e1000e_power_up_phy (struct e1000_adapter *adapter) |
| e1000e_power_up_phy - restore link in case the phy was powered down : address of board private structure | |
| void | e1000e_init_function_pointers_82571 (struct e1000_hw *hw) |
| e1000e_init_function_pointers_82571 - Init func ptrs. | |
| void | e1000e_init_function_pointers_80003es2lan (struct e1000_hw *hw) |
| e1000e_init_function_pointers_80003es2lan - Init ESB2 func ptrs. | |
| void | e1000e_init_function_pointers_ich8lan (struct e1000_hw *hw) |
| e1000e_init_function_pointers_ich8lan - Initialize ICH8 function pointers : pointer to the HW structure | |
| int | e1000e_probe (struct pci_device *pdev, const struct pci_device_id *id __unused) |
| void | e1000e_remove (struct pci_device *pdev) |
| e1000e_remove - Device Removal Routine | |
| s32 | e1000e_read_pba_num (struct e1000_hw *hw, u32 *pba_num) |
| e1000e_read_pba_num - Read device part number : pointer to the HW structure : pointer to device part number | |
| static s32 | e1000e_commit_phy (struct e1000_hw *hw) |
| bool | e1000e_enable_mng_pass_thru (struct e1000_hw *hw) |
| bool | e1000e_get_laa_state_82571 (struct e1000_hw *hw) |
| e1000e_get_laa_state_82571 - Get locally administered address state : pointer to the HW structure | |
| void | e1000e_set_laa_state_82571 (struct e1000_hw *hw, bool state) |
| e1000e_set_laa_state_82571 - Set locally administered address state : pointer to the HW structure : enable/disable locally administered address | |
| void | e1000e_set_kmrn_lock_loss_workaround_ich8lan (struct e1000_hw *hw, bool state) |
| e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state : pointer to the HW structure : boolean value used to set the current Kumeran workaround state | |
| void | e1000e_igp3_phy_powerdown_workaround_ich8lan (struct e1000_hw *hw) |
| e1000e_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 : pointer to the HW structure | |
| void | e1000e_gig_downshift_workaround_ich8lan (struct e1000_hw *hw) |
| e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working : pointer to the HW structure | |
| void | e1000e_disable_gig_wol_ich8lan (struct e1000_hw *hw) |
| e1000e_disable_gig_wol_ich8lan - disable gig during WoL : pointer to the HW structure | |
| s32 | e1000e_check_for_copper_link (struct e1000_hw *hw) |
| e1000e_check_for_copper_link - Check for link (Copper) : pointer to the HW structure | |
| s32 | e1000e_check_for_fiber_link (struct e1000_hw *hw) |
| e1000e_check_for_fiber_link - Check for link (Fiber) : pointer to the HW structure | |
| s32 | e1000e_check_for_serdes_link (struct e1000_hw *hw) |
| e1000e_check_for_serdes_link - Check for link (Serdes) : pointer to the HW structure | |
| s32 | e1000e_cleanup_led_generic (struct e1000_hw *hw) |
| s32 | e1000e_led_on_generic (struct e1000_hw *hw) |
| s32 | e1000e_led_off_generic (struct e1000_hw *hw) |
| s32 | e1000e_get_bus_info_pcie (struct e1000_hw *hw) |
| e1000e_get_bus_info_pcie - Get PCIe bus information : pointer to the HW structure | |
| s32 | e1000e_get_speed_and_duplex_copper (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex | |
| s32 | e1000e_get_speed_and_duplex_fiber_serdes (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| s32 | e1000e_disable_pcie_master (struct e1000_hw *hw) |
| e1000e_disable_pcie_master - Disables PCI-express master access : pointer to the HW structure | |
| s32 | e1000e_get_auto_rd_done (struct e1000_hw *hw) |
| e1000e_get_auto_rd_done - Check for auto read completion : pointer to the HW structure | |
| s32 | e1000e_id_led_init (struct e1000_hw *hw) |
| void | e1000e_clear_hw_cntrs_base (struct e1000_hw *hw) |
| s32 | e1000e_setup_fiber_serdes_link (struct e1000_hw *hw) |
| e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes : pointer to the HW structure | |
| s32 | e1000e_copper_link_setup_m88 (struct e1000_hw *hw) |
| e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link : pointer to the HW structure | |
| s32 | e1000e_copper_link_setup_igp (struct e1000_hw *hw) |
| e1000e_copper_link_setup_igp - Setup igp PHY's for copper link : pointer to the HW structure | |
| s32 | e1000e_setup_link (struct e1000_hw *hw) |
| e1000e_setup_link - Setup flow control and link settings : pointer to the HW structure | |
| static void | e1000e_clear_vfta (struct e1000_hw *hw) |
| void | e1000e_init_rx_addrs (struct e1000_hw *hw, u16 rar_count) |
| e1000e_init_rx_addrs - Initialize receive address's : pointer to the HW structure : receive address registers | |
| void | e1000e_update_mc_addr_list_generic (struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count) |
| e1000e_update_mc_addr_list_generic - Update Multicast addresses : pointer to the HW structure : array of multicast addresses to program : number of multicast addresses to program | |
| void | e1000e_rar_set (struct e1000_hw *hw, u8 *addr, u32 index) |
| e1000e_rar_set - Set receive address register : pointer to the HW structure : pointer to the receive address : receive address array register | |
| s32 | e1000e_set_fc_watermarks (struct e1000_hw *hw) |
| e1000e_set_fc_watermarks - Set flow control high/low watermarks : pointer to the HW structure | |
| void | e1000e_set_pcie_no_snoop (struct e1000_hw *hw, u32 no_snoop) |
| e1000e_set_pcie_no_snoop - Set PCI-express capabilities : pointer to the HW structure : bitmap of snoop events | |
| s32 | e1000e_get_hw_semaphore (struct e1000_hw *hw) |
| e1000e_get_hw_semaphore - Acquire hardware semaphore : pointer to the HW structure | |
| s32 | e1000e_valid_led_default (struct e1000_hw *hw, u16 *data) |
| e1000e_valid_led_default - Verify a valid default LED config : pointer to the HW structure : pointer to the NVM (EEPROM) | |
| void | e1000e_config_collision_dist (struct e1000_hw *hw) |
| e1000e_config_collision_dist - Configure collision distance : pointer to the HW structure | |
| s32 | e1000e_config_fc_after_link_up (struct e1000_hw *hw) |
| e1000e_config_fc_after_link_up - Configures flow control after link : pointer to the HW structure | |
| s32 | e1000e_force_mac_fc (struct e1000_hw *hw) |
| e1000e_force_mac_fc - Force the MAC's flow control settings : pointer to the HW structure | |
| s32 | e1000e_blink_led (struct e1000_hw *hw) |
| void | e1000e_write_vfta_generic (struct e1000_hw *hw, u32 offset, u32 value) |
| e1000e_write_vfta_generic - Write value to VLAN filter table : pointer to the HW structure : register offset in VLAN filter table : register value written to VLAN filter table | |
| static void | e1000e_write_vfta (struct e1000_hw *hw, u32 offset, u32 value) |
| void | e1000e_reset_adaptive (struct e1000_hw *hw) |
| e1000e_reset_adaptive - Reset Adaptive Interframe Spacing : pointer to the HW structure | |
| void | e1000e_update_adaptive (struct e1000_hw *hw) |
| e1000e_update_adaptive - Update Adaptive Interframe Spacing : pointer to the HW structure | |
| s32 | e1000e_setup_copper_link (struct e1000_hw *hw) |
| e1000e_setup_copper_link - Configure copper link settings : pointer to the HW structure | |
| void | e1000e_put_hw_semaphore (struct e1000_hw *hw) |
| e1000e_put_hw_semaphore - Release hardware semaphore : pointer to the HW structure | |
| s32 | e1000e_check_reset_block_generic (struct e1000_hw *hw) |
| e1000e_check_reset_block_generic - Check if PHY reset is blocked : pointer to the HW structure | |
| s32 | e1000e_get_phy_info_igp (struct e1000_hw *hw) |
| e1000e_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure | |
| s32 | e1000e_read_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_phy_hw_reset_generic (struct e1000_hw *hw) |
| e1000e_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure | |
| s32 | e1000e_set_d3_lplu_state (struct e1000_hw *hw, bool active) |
| e1000e_set_d3_lplu_state - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu | |
| s32 | e1000e_write_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_phy_sw_reset (struct e1000_hw *hw) |
| e1000e_phy_sw_reset - PHY software reset : pointer to the HW structure | |
| s32 | e1000e_get_cfg_done (struct e1000_hw *hw) |
| s32 | e1000e_get_phy_info_m88 (struct e1000_hw *hw) |
| e1000e_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure | |
| s32 | e1000e_read_phy_reg_m88 (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_write_phy_reg_m88 (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_m88 - Write m88 PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| enum e1000_phy_type | e1000e_get_phy_type_from_id (u32 phy_id) |
| e1000e_get_phy_type_from_id - Get PHY type from id : phy_id read from the phy | |
| s32 | e1000e_determine_phy_address (struct e1000_hw *hw) |
| e1000e_determine_phy_address - Determines PHY address. | |
| s32 | e1000e_write_phy_reg_bm (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_bm - Write BM PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_read_phy_reg_bm (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_bm - Read BM PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_write_kmrn_reg (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_kmrn_reg - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000e_read_kmrn_reg (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_kmrn_reg - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_phy_has_link_generic (struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success) |
| e1000e_phy_has_link_generic - Polls PHY for link : pointer to the HW structure : number of times to poll for link : delay between polling attempts : pointer to whether polling was successful or not | |
| s32 | e1000e_phy_reset_dsp (struct e1000_hw *hw) |
| e1000e_phy_reset_dsp - Reset PHY DSP : pointer to the HW structure | |
| s32 | e1000e_read_phy_reg_mdic (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000e_read_phy_reg_mdic - Read MDI control register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000e_write_phy_reg_mdic (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000e_write_phy_reg_mdic - Write MDI control register : pointer to the HW structure : register offset to write to : data to write to register at offset | |
| s32 | e1000e_check_downshift (struct e1000_hw *hw) |
| e1000e_check_downshift - Checks whether a downshift in speed occurred : pointer to the HW structure | |
| static s32 | e1000e_phy_hw_reset (struct e1000_hw *hw) |
| static s32 | e1000e_check_reset_block (struct e1000_hw *hw) |
| static s32 | e1e_rphy (struct e1000_hw *hw, u32 offset, u16 *data) |
| static s32 | e1e_wphy (struct e1000_hw *hw, u32 offset, u16 data) |
| s32 | e1000e_acquire_nvm (struct e1000_hw *hw) |
| e1000e_acquire_nvm - Generic request for access to EEPROM : pointer to the HW structure | |
| s32 | e1000e_write_nvm_spi (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| e1000e_write_nvm_spi - Write to EEPROM using SPI : pointer to the HW structure : offset within the EEPROM to be written to : number of words to write : 16 bit word(s) to be written to the EEPROM | |
| s32 | e1000e_update_nvm_checksum_generic (struct e1000_hw *hw) |
| e1000e_update_nvm_checksum_generic - Update EEPROM checksum : pointer to the HW structure | |
| s32 | e1000e_poll_eerd_eewr_done (struct e1000_hw *hw, int ee_reg) |
| e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion : pointer to the HW structure : EEPROM flag for polling | |
| s32 | e1000e_read_nvm_eerd (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| e1000e_read_nvm_eerd - Reads EEPROM using EERD register : pointer to the HW structure : offset of word in the EEPROM to read : number of words to read : word read from the EEPROM | |
| s32 | e1000e_validate_nvm_checksum_generic (struct e1000_hw *hw) |
| e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum : pointer to the HW structure | |
| void | e1000e_release_nvm (struct e1000_hw *hw) |
| e1000e_release_nvm - Release exclusive access to EEPROM : pointer to the HW structure | |
| static s32 | e1000e_read_mac_addr (struct e1000_hw *hw) |
| static s32 | e1000e_validate_nvm_checksum (struct e1000_hw *hw) |
| static s32 | e1000e_update_nvm_checksum (struct e1000_hw *hw) |
| static s32 | e1000e_read_nvm (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| static s32 | e1000e_write_nvm (struct e1000_hw *hw, u16 offset, u16 words, u16 *data) |
| static s32 | e1000e_get_phy_info (struct e1000_hw *hw) |
| bool | e1000e_enable_tx_pkt_filtering (struct e1000_hw *hw) |
| static u32 | __er32 (struct e1000_hw *hw, unsigned long reg) |
| static void | __ew32 (struct e1000_hw *hw, unsigned long reg, u32 val) |
| static u16 | __er16flash (struct e1000_hw *hw, unsigned long reg) |
| static u32 | __er32flash (struct e1000_hw *hw, unsigned long reg) |
| static void | __ew16flash (struct e1000_hw *hw, unsigned long reg, u16 val) |
| static void | __ew32flash (struct e1000_hw *hw, unsigned long reg, u32 val) |
| #define dma_addr_t unsigned long |
| #define msleep | ( | x | ) | mdelay(x) |
Definition at line 62 of file e1000e.h.
Referenced by e1000e_copper_link_setup_igp(), e1000e_determine_phy_address(), e1000e_get_auto_rd_done(), e1000e_get_cfg_done_80003es2lan(), e1000e_get_cfg_done_82571(), e1000e_init_phy_params_ich8lan(), e1000e_link_stall_workaround_hv(), e1000e_phy_hw_reset_ich8lan(), e1000e_poll_fiber_serdes_link_generic(), e1000e_power_down_phy_copper(), e1000e_reset_hw_80003es2lan(), e1000e_reset_hw_82571(), e1000e_reset_hw_ich8lan(), e1000e_setup_fiber_serdes_link(), e1000e_update_nvm_checksum_82571(), e1000e_update_nvm_checksum_ich8lan(), e1000e_wait_autoneg(), and e1000e_write_nvm_spi().
| #define e_dbg | ( | arg... | ) | if (0) { printf (arg); }; |
Definition at line 90 of file e1000e.h.
Referenced by e1000e_access_phy_debug_regs_hv(), e1000e_access_phy_wakeup_reg_bm(), e1000e_acquire_nvm(), e1000e_acquire_swflag_ich8lan(), e1000e_acquire_swfw_sync_80003es2lan(), e1000e_check_alt_mac_addr_generic(), e1000e_check_for_copper_link(), e1000e_check_for_copper_link_ich8lan(), e1000e_check_for_fiber_link(), e1000e_check_for_serdes_link(), e1000e_check_for_serdes_link_82571(), e1000e_commit_fc_settings_generic(), e1000e_config_fc_after_link_up(), e1000e_copper_link_autoneg(), e1000e_copper_link_setup_gg82563_80003es2lan(), e1000e_copper_link_setup_igp(), e1000e_copper_link_setup_m88(), e1000e_disable_pcie_master(), e1000e_flash_cycle_init_ich8lan(), e1000e_force_mac_fc(), e1000e_get_auto_rd_done(), e1000e_get_cfg_done_80003es2lan(), e1000e_get_cfg_done_82571(), e1000e_get_cfg_done_ich8lan(), e1000e_get_hw_semaphore(), e1000e_get_hw_semaphore_82571(), e1000e_get_phy_info_82577(), e1000e_get_phy_info_ife_ich8lan(), e1000e_get_phy_info_igp(), e1000e_get_phy_info_m88(), e1000e_get_speed_and_duplex_copper(), e1000e_init_hw_80003es2lan(), e1000e_init_hw_82571(), e1000e_init_hw_ich8lan(), e1000e_init_mac_params_82571(), e1000e_init_nvm_params_ich8lan(), e1000e_init_phy_params_82571(), e1000e_init_rx_addrs(), e1000e_lan_init_done_ich8lan(), e1000e_phy_init_script_igp3(), e1000e_phy_setup_autoneg(), e1000e_poll_fiber_serdes_link_generic(), e1000e_read_flash_data_ich8lan(), e1000e_read_nvm_eerd(), e1000e_read_nvm_ich8lan(), e1000e_read_pba_num(), e1000e_read_phy_reg_mdic(), e1000e_ready_nvm_eeprom(), e1000e_reset_adaptive(), e1000e_reset_hw_80003es2lan(), e1000e_reset_hw_82571(), e1000e_reset_hw_ich8lan(), e1000e_retry_write_flash_byte_ich8lan(), e1000e_set_default_fc_generic(), e1000e_set_kmrn_lock_loss_workaround_ich8lan(), e1000e_setup_copper_link(), e1000e_setup_fiber_serdes_link(), e1000e_setup_link(), e1000e_setup_link_ich8lan(), e1000e_update_adaptive(), e1000e_update_nvm_checksum_generic(), e1000e_update_nvm_checksum_ich8lan(), e1000e_valid_led_default(), e1000e_valid_led_default_82571(), e1000e_valid_led_default_ich8lan(), e1000e_valid_nvm_bank_detect_ich8lan(), e1000e_validate_mdi_setting_generic(), e1000e_validate_nvm_checksum_generic(), e1000e_write_flash_data_ich8lan(), e1000e_write_nvm_eewr_82571(), e1000e_write_nvm_ich8lan(), e1000e_write_nvm_spi(), and e1000e_write_phy_reg_mdic().
| #define DEFAULT_JUMBO 9234 |
| #define FLAG_HAS_AMT (1 << 0) |
| #define FLAG_HAS_FLASH (1 << 1) |
| #define FLAG_HAS_WOL (1 << 3) |
| #define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) |
| #define FLAG_HAS_SWSM_ON_LOAD (1 << 6) |
| #define FLAG_HAS_JUMBO_FRAMES (1 << 7) |
Definition at line 216 of file e1000e.h.
Referenced by e1000e_get_variants_82571(), and e1000e_get_variants_ich8lan().
| #define FLAG_HAS_SMART_POWER_DOWN (1 << 11) |
| #define FLAG_IS_QUAD_PORT_A (1 << 12) |
| #define FLAG_IS_QUAD_PORT (1 << 13) |
| #define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14) |
| #define FLAG_TARC_SPEED_MODE_BIT (1 << 22) |
| #define FLAG_TARC_SET_BIT_ZERO (1 << 23) |
| #define FLAG_LSC_GIG_SPEED_DROP (1 << 25) |
| #define FLAG_SMART_POWER_DOWN (1 << 26) |
| #define FLAG2_HAS_PHY_WAKEUP (1 << 1) |
| #define E1000_RX_DESC_PS | ( | R, | |||
| i | ) | (&(((union e1000_rx_desc_packet_split *)((R).desc))[i])) |
| #define E1000_GET_DESC | ( | R, | |||
| i, | |||||
| type | ) | (&(((struct type *)((R).desc))[i])) |
| #define E1000_RX_DESC | ( | R, | |||
| i | ) | E1000_GET_DESC(R, i, e1000_rx_desc) |
| #define E1000_TX_DESC | ( | R, | |||
| i | ) | E1000_GET_DESC(R, i, e1000_tx_desc) |
| #define E1000_CONTEXT_DESC | ( | R, | |||
| i | ) | E1000_GET_DESC(R, i, e1000_context_desc) |
| #define er32 | ( | reg | ) | __er32(hw, E1000_##reg) |
Definition at line 490 of file e1000e.h.
Referenced by __e1000e_read_kmrn_reg(), __e1000e_read_phy_reg_hv(), __e1000e_write_phy_reg_hv(), e1000e_access_phy_wakeup_reg_bm(), e1000e_acquire_nvm(), e1000e_acquire_swflag_ich8lan(), e1000e_acquire_swfw_sync_80003es2lan(), e1000e_cfg_kmrn_1000_80003es2lan(), e1000e_cfg_kmrn_10_100_80003es2lan(), e1000e_check_for_fiber_link(), e1000e_check_for_serdes_link(), e1000e_check_for_serdes_link_82571(), e1000e_check_mng_mode_ich8lan(), e1000e_check_reset_block_generic(), e1000e_check_reset_block_ich8lan(), e1000e_clear_hw_cntrs_80003es2lan(), e1000e_clear_hw_cntrs_82571(), e1000e_clear_hw_cntrs_base(), e1000e_clear_hw_cntrs_ich8lan(), e1000e_config_collision_dist(), e1000e_configure_k1_ich8lan(), e1000e_configure_tx(), e1000e_copper_link_setup_gg82563_80003es2lan(), e1000e_disable_gig_wol_ich8lan(), e1000e_disable_pcie_master(), e1000e_force_mac_fc(), e1000e_get_auto_rd_done(), e1000e_get_cfg_done_80003es2lan(), e1000e_get_cfg_done_82571(), e1000e_get_cfg_done_ich8lan(), e1000e_get_hw_control(), e1000e_get_hw_semaphore(), e1000e_get_hw_semaphore_82571(), e1000e_get_speed_and_duplex_copper(), e1000e_get_variants_82571(), e1000e_id_led_init(), e1000e_id_led_init_pchlan(), e1000e_igp3_phy_powerdown_workaround_ich8lan(), e1000e_init_hw_80003es2lan(), e1000e_init_hw_82571(), e1000e_init_hw_ich8lan(), e1000e_init_mac_params_80003es2lan(), e1000e_init_mac_params_82571(), e1000e_init_nvm_params_80003es2lan(), e1000e_init_nvm_params_82571(), e1000e_initialize_hw_bits_80003es2lan(), e1000e_initialize_hw_bits_82571(), e1000e_initialize_hw_bits_ich8lan(), e1000e_kmrn_lock_loss_workaround_ich8lan(), e1000e_lan_init_done_ich8lan(), e1000e_led_off_generic(), e1000e_led_off_pchlan(), e1000e_led_on_82574(), e1000e_led_on_generic(), e1000e_led_on_pchlan(), e1000e_oem_bits_config_ich8lan(), e1000e_phy_hw_reset_generic(), e1000e_poll_eerd_eewr_done(), e1000e_poll_fiber_serdes_link_generic(), e1000e_put_hw_semaphore(), e1000e_put_hw_semaphore_82571(), e1000e_read_kmrn_reg_80003es2lan(), e1000e_read_mac_addr_generic(), e1000e_read_nvm_eerd(), e1000e_read_phy_reg_mdic(), e1000e_ready_nvm_eeprom(), e1000e_release_nvm(), e1000e_release_swflag_ich8lan(), e1000e_release_swfw_sync_80003es2lan(), e1000e_reload_nvm(), e1000e_reset_hw_80003es2lan(), e1000e_reset_hw_82571(), e1000e_reset_hw_ich8lan(), e1000e_set_d0_lplu_state_ich8lan(), e1000e_set_d3_lplu_state_ich8lan(), e1000e_set_lan_id_multi_port_pcie(), e1000e_set_pcie_no_snoop(), e1000e_setup_copper_link_80003es2lan(), e1000e_setup_copper_link_82571(), e1000e_setup_copper_link_ich8lan(), e1000e_setup_fiber_serdes_link(), e1000e_setup_led_generic(), e1000e_shift_in_eec_bits(), e1000e_shift_out_eec_bits(), e1000e_standby_nvm(), e1000e_stop_nvm(), e1000e_sw_lcd_config_ich8lan(), e1000e_update_nvm_checksum_82571(), e1000e_valid_nvm_bank_detect_ich8lan(), and e1000e_write_phy_reg_mdic().
| #define ew32 | ( | reg, | |||
| val | ) | __ew32(hw, E1000_##reg, (val)) |
Definition at line 491 of file e1000e.h.
Referenced by __e1000e_read_kmrn_reg(), __e1000e_write_kmrn_reg(), e1000e_acquire_nvm(), e1000e_acquire_swflag_ich8lan(), e1000e_acquire_swfw_sync_80003es2lan(), e1000e_blink_led(), e1000e_cfg_kmrn_1000_80003es2lan(), e1000e_cfg_kmrn_10_100_80003es2lan(), e1000e_check_for_fiber_link(), e1000e_check_for_serdes_link(), e1000e_check_for_serdes_link_82571(), e1000e_cleanup_led_generic(), e1000e_cleanup_led_ich8lan(), e1000e_commit_fc_settings_generic(), e1000e_config_collision_dist(), e1000e_configure_k1_ich8lan(), e1000e_configure_tx(), e1000e_copper_link_setup_gg82563_80003es2lan(), e1000e_disable_gig_wol_ich8lan(), e1000e_disable_pcie_master(), e1000e_force_mac_fc(), e1000e_get_cfg_done_ich8lan(), e1000e_get_hw_control(), e1000e_get_hw_semaphore(), e1000e_get_hw_semaphore_82571(), e1000e_igp3_phy_powerdown_workaround_ich8lan(), e1000e_init_hw_80003es2lan(), e1000e_init_hw_82571(), e1000e_init_hw_ich8lan(), e1000e_init_mac_params_82571(), e1000e_init_nvm_params_82571(), e1000e_initialize_hw_bits_80003es2lan(), e1000e_initialize_hw_bits_82571(), e1000e_initialize_hw_bits_ich8lan(), e1000e_irq_disable(), e1000e_irq_enable(), e1000e_kmrn_lock_loss_workaround_ich8lan(), e1000e_lan_init_done_ich8lan(), e1000e_led_off_generic(), e1000e_led_off_ich8lan(), e1000e_led_on_82574(), e1000e_led_on_generic(), e1000e_led_on_ich8lan(), e1000e_lower_eec_clk(), e1000e_phy_hw_reset_generic(), e1000e_put_hw_semaphore(), e1000e_put_hw_semaphore_82571(), e1000e_raise_eec_clk(), e1000e_rar_set(), e1000e_read_kmrn_reg_80003es2lan(), e1000e_read_nvm_eerd(), e1000e_read_phy_reg_mdic(), e1000e_ready_nvm_eeprom(), e1000e_release_nvm(), e1000e_release_swflag_ich8lan(), e1000e_release_swfw_sync_80003es2lan(), e1000e_reload_nvm(), e1000e_reset(), e1000e_reset_adaptive(), e1000e_reset_hw_80003es2lan(), e1000e_reset_hw_82571(), e1000e_reset_hw_ich8lan(), e1000e_set_d0_lplu_state_ich8lan(), e1000e_set_d3_lplu_state_ich8lan(), e1000e_set_fc_watermarks(), e1000e_set_pcie_no_snoop(), e1000e_setup_copper_link_80003es2lan(), e1000e_setup_copper_link_82571(), e1000e_setup_copper_link_ich8lan(), e1000e_setup_fiber_serdes_link(), e1000e_setup_fiber_serdes_link_82571(), e1000e_setup_led_generic(), e1000e_setup_link(), e1000e_setup_link_ich8lan(), e1000e_shift_out_eec_bits(), e1000e_standby_nvm(), e1000e_update_adaptive(), e1000e_update_nvm_checksum_82571(), e1000e_write_kmrn_reg_80003es2lan(), e1000e_write_nvm_eewr_82571(), and e1000e_write_phy_reg_mdic().
| #define e1e_flush | ( | ) | er32(STATUS) |
Definition at line 492 of file e1000e.h.
Referenced by e1000e_clear_vfta_82571(), e1000e_clear_vfta_generic(), e1000e_close(), e1000e_config_collision_dist(), e1000e_configure_rx(), e1000e_configure_tx(), e1000e_irq_disable(), e1000e_irq_enable(), e1000e_lower_eec_clk(), e1000e_mta_set_generic(), e1000e_phy_hw_reset_generic(), e1000e_raise_eec_clk(), e1000e_rar_set(), e1000e_reload_nvm(), e1000e_reset_hw_80003es2lan(), e1000e_reset_hw_82571(), e1000e_reset_hw_ich8lan(), e1000e_setup_fiber_serdes_link(), e1000e_shift_out_eec_bits(), e1000e_standby_nvm(), e1000e_transmit(), e1000e_update_mc_addr_list_generic(), e1000e_update_nvm_checksum_82571(), and e1000e_write_vfta_generic().
| #define E1000_WRITE_REG | ( | a, | |||
| reg, | |||||
| value | ) | writel((value), ((a)->hw_addr + reg)) |
| #define E1000_READ_REG | ( | a, | |||
| reg | ) | (readl((a)->hw_addr + reg)) |
| #define E1000_READ_REG_ARRAY | ( | a, | |||
| reg, | |||||
| offset | ) |
| #define er16flash | ( | reg | ) | __er16flash(hw, (reg)) |
Definition at line 528 of file e1000e.h.
Referenced by e1000e_erase_flash_bank_ich8lan(), e1000e_flash_cycle_ich8lan(), e1000e_flash_cycle_init_ich8lan(), e1000e_read_flash_data_ich8lan(), and e1000e_write_flash_data_ich8lan().
| #define er32flash | ( | reg | ) | __er32flash(hw, (reg)) |
Definition at line 529 of file e1000e.h.
Referenced by e1000e_init_nvm_params_ich8lan(), and e1000e_read_flash_data_ich8lan().
| #define ew16flash | ( | reg, | |||
| val | ) | __ew16flash(hw, (reg), (val)) |
Definition at line 530 of file e1000e.h.
Referenced by e1000e_erase_flash_bank_ich8lan(), e1000e_flash_cycle_ich8lan(), e1000e_flash_cycle_init_ich8lan(), e1000e_read_flash_data_ich8lan(), and e1000e_write_flash_data_ich8lan().
| #define ew32flash | ( | reg, | |||
| val | ) | __ew32flash(hw, (reg), (val)) |
Definition at line 531 of file e1000e.h.
Referenced by e1000e_erase_flash_bank_ich8lan(), e1000e_read_flash_data_ich8lan(), and e1000e_write_flash_data_ich8lan().
| typedef int spinlock_t |
| enum boolean_t |
| enum e1000_boards |
| board_82571 | |
| board_82572 | |
| board_82573 | |
| board_82574 | |
| board_80003es2lan | |
| board_ich8lan | |
| board_ich9lan | |
| board_ich10lan | |
| board_pchlan | |
| board_82583 |
Definition at line 136 of file e1000e.h.
00136 { 00137 board_82571, 00138 board_82572, 00139 board_82573, 00140 board_82574, 00141 board_80003es2lan, 00142 board_ich8lan, 00143 board_ich9lan, 00144 board_ich10lan, 00145 board_pchlan, 00146 board_82583, 00147 };
| enum e1000_state_t |
Definition at line 254 of file e1000e.h.
00254 { 00255 __E1000E_TESTING, 00256 __E1000E_RESETTING, 00257 __E1000E_DOWN 00258 };
| enum latency_range |
Definition at line 260 of file e1000e.h.
00260 { 00261 lowest_latency = 0, 00262 low_latency = 1, 00263 bulk_latency = 2, 00264 latency_invalid = 255 00265 };
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
| void e1000e_check_options | ( | struct e1000_adapter * | adapter | ) |
| void e1000e_reset | ( | struct e1000_adapter * | adapter | ) |
e1000e_reset - bring the hardware into a known good state
This function boots the hardware and enables some settings that require a configuration cycle of the hardware - those cannot be set/changed during runtime. After reset the device needs to be properly configured for Rx, Tx etc.
Definition at line 397 of file e1000e_main.c.
References BM_WUC, e1000_fc_info::current_mode, DBG, e1000_fc_none, e1000_pchlan, e1000e_get_hw_control(), e1000e_get_phy_info(), e1000e_reset_adaptive(), e1e_rphy(), e1e_wphy(), ew32, e1000_hw::fc, FLAG2_HAS_PHY_WAKEUP, FLAG_HAS_AMT, FLAG_HAS_SMART_POWER_DOWN, FLAG_SMART_POWER_DOWN, e1000_adapter::flags, e1000_adapter::flags2, e1000_adapter::hw, IGP02E1000_PHY_POWER_MGMT, IGP02E1000_PM_SPD, e1000_mac_operations::init_hw, e1000_hw::mac, e1000_mac_info::ops, e1000_adapter::pba, e1000_fc_info::requested_mode, e1000_mac_operations::reset_hw, e1000_mac_info::type, u16, and u32.
Referenced by e1000e_close(), e1000e_open(), e1000e_probe(), and e1000e_remove().
00398 { 00399 struct e1000_mac_info *mac = &adapter->hw.mac; 00400 struct e1000_fc_info *fc = &adapter->hw.fc; 00401 u32 pba = adapter->pba; 00402 struct e1000_hw *hw = &adapter->hw; 00403 00404 /* Reset Packet Buffer Allocation to default */ 00405 ew32(PBA, pba); 00406 00407 hw->fc.requested_mode = e1000_fc_none; 00408 fc->current_mode = fc->requested_mode; 00409 00410 /* Allow time for pending master requests to run */ 00411 mac->ops.reset_hw(hw); 00412 00413 /* 00414 * For parts with AMT enabled, let the firmware know 00415 * that the network interface is in control 00416 */ 00417 if (adapter->flags & FLAG_HAS_AMT) 00418 e1000e_get_hw_control(adapter); 00419 00420 ew32(WUC, 0); 00421 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) 00422 e1e_wphy(&adapter->hw, BM_WUC, 0); 00423 00424 if (mac->ops.init_hw(hw)) 00425 DBG("Hardware Error\n"); 00426 00427 /* additional part of the flow-control workaround above */ 00428 if (hw->mac.type == e1000_pchlan) 00429 ew32(FCRTV_PCH, 0x1000); 00430 00431 e1000e_reset_adaptive(hw); 00432 00433 e1000e_get_phy_info(hw); 00434 00435 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && 00436 !(adapter->flags & FLAG_SMART_POWER_DOWN)) { 00437 u16 phy_data = 0; 00438 /* 00439 * speed up time to link by disabling smart power down, ignore 00440 * the return value of this function because there is nothing 00441 * different we would do if it failed 00442 */ 00443 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); 00444 phy_data &= ~IGP02E1000_PM_SPD; 00445 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); 00446 } 00447 }
| void e1000e_power_up_phy | ( | struct e1000_adapter * | adapter | ) |
e1000e_power_up_phy - restore link in case the phy was powered down : address of board private structure
The phy may be powered down to save power and turn off link when the driver is unloaded and wake on lan is not enabled (among others) *** this routine MUST be followed by a call to e1000e_reset ***
Definition at line 365 of file e1000e_main.c.
References e1000_adapter::hw, e1000_hw::mac, e1000_mac_info::ops, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_up, and e1000_mac_operations::setup_link.
00366 { 00367 if (adapter->hw.phy.ops.power_up) 00368 adapter->hw.phy.ops.power_up(&adapter->hw); 00369 00370 adapter->hw.mac.ops.setup_link(&adapter->hw); 00371 }
| void e1000e_init_function_pointers_82571 | ( | struct e1000_hw * | hw | ) |
e1000e_init_function_pointers_82571 - Init func ptrs.
: pointer to the HW structure
Called to initialize all function pointers and parameters.
Definition at line 453 of file e1000e_82571.c.
References e1000e_init_mac_ops_generic(), e1000e_init_mac_params_82571(), e1000e_init_nvm_ops_generic(), e1000e_init_nvm_params_82571(), e1000e_init_phy_params_82571(), e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::nvm, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, and e1000_hw::phy.
00454 { 00455 e1000e_init_mac_ops_generic(hw); 00456 e1000e_init_nvm_ops_generic(hw); 00457 hw->mac.ops.init_params = e1000e_init_mac_params_82571; 00458 hw->nvm.ops.init_params = e1000e_init_nvm_params_82571; 00459 hw->phy.ops.init_params = e1000e_init_phy_params_82571; 00460 }
| void e1000e_init_function_pointers_80003es2lan | ( | struct e1000_hw * | hw | ) |
e1000e_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
: pointer to the HW structure
Called to initialize all function pointers and parameters.
Definition at line 307 of file e1000e_80003es2lan.c.
References e1000e_init_mac_ops_generic(), e1000e_init_mac_params_80003es2lan(), e1000e_init_nvm_ops_generic(), e1000e_init_nvm_params_80003es2lan(), e1000e_init_phy_params_80003es2lan(), e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::nvm, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, and e1000_hw::phy.
00308 { 00309 e1000e_init_mac_ops_generic(hw); 00310 e1000e_init_nvm_ops_generic(hw); 00311 hw->mac.ops.init_params = e1000e_init_mac_params_80003es2lan; 00312 hw->nvm.ops.init_params = e1000e_init_nvm_params_80003es2lan; 00313 hw->phy.ops.init_params = e1000e_init_phy_params_80003es2lan; 00314 }
| void e1000e_init_function_pointers_ich8lan | ( | struct e1000_hw * | hw | ) |
e1000e_init_function_pointers_ich8lan - Initialize ICH8 function pointers : pointer to the HW structure
Initialize family-specific function pointers for PHY, MAC, and NVM.
Definition at line 567 of file e1000e_ich8lan.c.
References e1000_ich10lan, e1000_ich8lan, e1000_ich9lan, e1000_pchlan, e1000e_init_mac_ops_generic(), e1000e_init_mac_params_ich8lan(), e1000e_init_nvm_ops_generic(), e1000e_init_nvm_params_ich8lan(), e1000e_init_phy_params_ich8lan(), e1000e_init_phy_params_pchlan(), e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::nvm, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, e1000_hw::phy, and e1000_mac_info::type.
00568 { 00569 e1000e_init_mac_ops_generic(hw); 00570 e1000e_init_nvm_ops_generic(hw); 00571 hw->mac.ops.init_params = e1000e_init_mac_params_ich8lan; 00572 hw->nvm.ops.init_params = e1000e_init_nvm_params_ich8lan; 00573 switch (hw->mac.type) { 00574 case e1000_ich8lan: 00575 case e1000_ich9lan: 00576 case e1000_ich10lan: 00577 hw->phy.ops.init_params = e1000e_init_phy_params_ich8lan; 00578 break; 00579 case e1000_pchlan: 00580 hw->phy.ops.init_params = e1000e_init_phy_params_pchlan; 00581 break; 00582 default: 00583 break; 00584 } 00585 }
| int e1000e_probe | ( | struct pci_device * | pdev, | |
| const struct pci_device_id *id | __unused | |||
| ) |
| void e1000e_remove | ( | struct pci_device * | pdev | ) |
e1000e_remove - Device Removal Routine
| pdev | PCI device information struct |
Definition at line 1197 of file e1000e_main.c.
References DBGP, e1000e_reset(), e1000_hw::flash_address, e1000_adapter::hw, e1000_hw::hw_addr, iounmap(), netdev, netdev_nullify(), netdev_priv(), netdev_put(), pci_get_drvdata(), and unregister_netdev().
01198 { 01199 struct net_device *netdev = pci_get_drvdata ( pdev ); 01200 struct e1000_adapter *adapter = netdev_priv ( netdev ); 01201 01202 DBGP ( "e1000e_remove\n" ); 01203 01204 if ( adapter->hw.flash_address ) 01205 iounmap ( adapter->hw.flash_address ); 01206 if ( adapter->hw.hw_addr ) 01207 iounmap ( adapter->hw.hw_addr ); 01208 01209 unregister_netdev ( netdev ); 01210 e1000e_reset ( adapter ); 01211 netdev_nullify ( netdev ); 01212 netdev_put ( netdev ); 01213 }
e1000e_read_pba_num - Read device part number : pointer to the HW structure : pointer to device part number
Reads the product board assembly (PBA) number from the EEPROM and stores the value in pba_num.
Definition at line 464 of file e1000e_nvm.c.
00465 { 00466 s32 ret_val; 00467 u16 nvm_data; 00468 00469 ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 00470 if (ret_val) { 00471 e_dbg("NVM Read Error\n"); 00472 goto out; 00473 } 00474 *pba_num = (u32)(nvm_data << 16); 00475 00476 ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 00477 if (ret_val) { 00478 e_dbg("NVM Read Error\n"); 00479 goto out; 00480 } 00481 *pba_num |= nvm_data; 00482 00483 out: 00484 return ret_val; 00485 }
Definition at line 286 of file e1000e.h.
References e1000_phy_operations::commit, e1000_phy_info::ops, and e1000_hw::phy.
Referenced by e1000e_copper_link_setup_gg82563_80003es2lan(), and e1000e_copper_link_setup_m88().
00287 { 00288 if (hw->phy.ops.commit) 00289 return hw->phy.ops.commit(hw); 00290 00291 return 0; 00292 }
e1000e_get_laa_state_82571 - Get locally administered address state : pointer to the HW structure
Retrieve and return the current locally administered address state.
Definition at line 1609 of file e1000e_82571.c.
Referenced by e1000e_init_hw_82571().
01610 { 01611 if (hw->mac.type != e1000_82571) 01612 return false; 01613 01614 return hw->dev_spec._82571.laa_is_present; 01615 }
e1000e_set_laa_state_82571 - Set locally administered address state : pointer to the HW structure : enable/disable locally administered address
Enable/Disable the current locally administered address state.
Definition at line 1624 of file e1000e_82571.c.
Referenced by e1000e_reset_hw_82571().
01625 { 01626 if (hw->mac.type != e1000_82571) 01627 return; 01628 01629 hw->dev_spec._82571.laa_is_present = state; 01630 01631 /* If workaround is activated... */ 01632 if (state) 01633 /* 01634 * Hold a copy of the LAA in RAR[14] This is done so that 01635 * between the time RAR[0] gets clobbered and the time it 01636 * gets fixed, the actual LAA is in one of the RARs and no 01637 * incoming packets directed to this port are dropped. 01638 * Eventually the LAA will be in RAR[0] and RAR[14]. 01639 */ 01640 e1000e_rar_set(hw, hw->mac.addr, 01641 hw->mac.rar_entry_count - 1); 01642 return; 01643 }
e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state : pointer to the HW structure : boolean value used to set the current Kumeran workaround state
If ICH8, set the current Kumeran workaround state (enabled - true /disabled - false).
Definition at line 3013 of file e1000e_ich8lan.c.
Referenced by e1000e_init_mac_params_ich8lan().
03015 { 03016 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 03017 03018 if (hw->mac.type != e1000_ich8lan) { 03019 e_dbg("Workaround applies to ICH8 only.\n"); 03020 return; 03021 } 03022 03023 dev_spec->kmrn_lock_loss_workaround_enabled = state; 03024 03025 return; 03026 }
| void e1000e_igp3_phy_powerdown_workaround_ich8lan | ( | struct e1000_hw * | hw | ) |
e1000e_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 : pointer to the HW structure
Workaround for 82566 power-down on D3 entry: 1) disable gigabit link 2) write VR power-down enable 3) read it back Continue if successful, else issue LCD reset and repeat
Definition at line 3038 of file e1000e_ich8lan.c.
03039 { 03040 u32 reg; 03041 u16 data; 03042 u8 retry = 0; 03043 03044 if (hw->phy.type != e1000_phy_igp_3) 03045 goto out; 03046 03047 /* Try the workaround twice (if needed) */ 03048 do { 03049 /* Disable link */ 03050 reg = er32(PHY_CTRL); 03051 reg |= (E1000_PHY_CTRL_GBE_DISABLE | 03052 E1000_PHY_CTRL_NOND0A_GBE_DISABLE); 03053 ew32(PHY_CTRL, reg); 03054 03055 /* 03056 * Call gig speed drop workaround on Gig disable before 03057 * accessing any PHY registers 03058 */ 03059 if (hw->mac.type == e1000_ich8lan) 03060 e1000e_gig_downshift_workaround_ich8lan(hw); 03061 03062 /* Write VR power-down enable */ 03063 e1e_rphy(hw, IGP3_VR_CTRL, &data); 03064 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 03065 e1e_wphy(hw, IGP3_VR_CTRL, 03066 data | IGP3_VR_CTRL_MODE_SHUTDOWN); 03067 03068 /* Read it back and test */ 03069 e1e_rphy(hw, IGP3_VR_CTRL, &data); 03070 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; 03071 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) 03072 break; 03073 03074 /* Issue PHY reset and repeat at most one more time */ 03075 reg = er32(CTRL); 03076 ew32(CTRL, reg | E1000_CTRL_PHY_RST); 03077 retry++; 03078 } while (retry); 03079 03080 out: 03081 return; 03082 }
| void e1000e_gig_downshift_workaround_ich8lan | ( | struct e1000_hw * | hw | ) |
e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working : pointer to the HW structure
Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), LPLU, Gig disable, MDIC PHY reset): 1) Set Kumeran Near-end loopback 2) Clear Kumeran Near-end loopback Should only be called for ICH8[m] devices with IGP_3 Phy.
Definition at line 3094 of file e1000e_ich8lan.c.
Referenced by e1000e_igp3_phy_powerdown_workaround_ich8lan(), e1000e_kmrn_lock_loss_workaround_ich8lan(), e1000e_set_d0_lplu_state_ich8lan(), and e1000e_set_d3_lplu_state_ich8lan().
03095 { 03096 s32 ret_val = E1000_SUCCESS; 03097 u16 reg_data; 03098 03099 if ((hw->mac.type != e1000_ich8lan) || 03100 (hw->phy.type != e1000_phy_igp_3)) 03101 goto out; 03102 03103 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, 03104 ®_data); 03105 if (ret_val) 03106 goto out; 03107 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; 03108 ret_val = e1000e_write_kmrn_reg(hw, 03109 E1000_KMRNCTRLSTA_DIAG_OFFSET, 03110 reg_data); 03111 if (ret_val) 03112 goto out; 03113 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; 03114 ret_val = e1000e_write_kmrn_reg(hw, 03115 E1000_KMRNCTRLSTA_DIAG_OFFSET, 03116 reg_data); 03117 out: 03118 return; 03119 }
| void e1000e_disable_gig_wol_ich8lan | ( | struct e1000_hw * | hw | ) |
e1000e_disable_gig_wol_ich8lan - disable gig during WoL : pointer to the HW structure
During S0 to Sx transition, it is possible the link remains at gig instead of negotiating to a lower speed. Before going to Sx, set 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation to a lower speed.
Should only be called for applicable parts.
Definition at line 3132 of file e1000e_ich8lan.c.
03133 { 03134 u32 phy_ctrl; 03135 03136 switch (hw->mac.type) { 03137 case e1000_ich8lan: 03138 case e1000_ich9lan: 03139 case e1000_ich10lan: 03140 case e1000_pchlan: 03141 phy_ctrl = er32(PHY_CTRL); 03142 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | 03143 E1000_PHY_CTRL_GBE_DISABLE; 03144 ew32(PHY_CTRL, phy_ctrl); 03145 03146 if (hw->mac.type == e1000_pchlan) 03147 e1000e_phy_hw_reset_ich8lan(hw); 03148 default: 03149 break; 03150 } 03151 03152 return; 03153 }
e1000e_check_for_copper_link - Check for link (Copper) : pointer to the HW structure
Checks to see of the link status of the hardware has changed. If a change in link status has been detected, then we read the PHY registers to get the current speed/duplex if link exists.
Definition at line 489 of file e1000e_mac.c.
Referenced by e1000e_init_mac_params_80003es2lan(), and e1000e_init_mac_params_82571().
00490 { 00491 struct e1000_mac_info *mac = &hw->mac; 00492 s32 ret_val; 00493 bool link; 00494 00495 /* 00496 * We only want to go out to the PHY registers to see if Auto-Neg 00497 * has completed and/or if our link status has changed. The 00498 * get_link_status flag is set upon receiving a Link Status 00499 * Change or Rx Sequence Error interrupt. 00500 */ 00501 if (!mac->get_link_status) { 00502 ret_val = E1000_SUCCESS; 00503 goto out; 00504 } 00505 00506 /* 00507 * First we want to see if the MII Status Register reports 00508 * link. If so, then we want to get the current speed/duplex 00509 * of the PHY. 00510 */ 00511 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 00512 if (ret_val) 00513 goto out; 00514 00515 if (!link) 00516 goto out; /* No link detected */ 00517 00518 mac->get_link_status = false; 00519 00520 /* 00521 * Check if there was DownShift, must be checked 00522 * immediately after link-up 00523 */ 00524 e1000e_check_downshift(hw); 00525 00526 /* 00527 * If we are forcing speed/duplex, then we simply return since 00528 * we have already determined whether we have link or not. 00529 */ 00530 if (!mac->autoneg) { 00531 ret_val = -E1000_ERR_CONFIG; 00532 goto out; 00533 } 00534 00535 /* 00536 * Auto-Neg is enabled. Auto Speed Detection takes care 00537 * of MAC speed/duplex configuration. So we only need to 00538 * configure Collision Distance in the MAC. 00539 */ 00540 e1000e_config_collision_dist(hw); 00541 00542 /* 00543 * Configure Flow Control now that Auto-Neg has completed. 00544 * First, we need to restore the desired flow control 00545 * settings because we may have had to re-autoneg with a 00546 * different link partner. 00547 */ 00548 ret_val = e1000e_config_fc_after_link_up(hw); 00549 if (ret_val) 00550 e_dbg("Error configuring flow control\n"); 00551 00552 out: 00553 return ret_val; 00554 }
e1000e_check_for_fiber_link - Check for link (Fiber) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 563 of file e1000e_mac.c.
Referenced by e1000e_init_mac_params_80003es2lan(), and e1000e_init_mac_params_82571().
00564 { 00565 struct e1000_mac_info *mac = &hw->mac; 00566 u32 rxcw; 00567 u32 ctrl; 00568 u32 status; 00569 s32 ret_val = E1000_SUCCESS; 00570 00571 ctrl = er32(CTRL); 00572 status = er32(STATUS); 00573 rxcw = er32(RXCW); 00574 00575 /* 00576 * If we don't have link (auto-negotiation failed or link partner 00577 * cannot auto-negotiate), the cable is plugged in (we have signal), 00578 * and our link partner is not trying to auto-negotiate with us (we 00579 * are receiving idles or data), we need to force link up. We also 00580 * need to give auto-negotiation time to complete, in case the cable 00581 * was just plugged in. The autoneg_failed flag does this. 00582 */ 00583 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 00584 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 00585 (!(rxcw & E1000_RXCW_C))) { 00586 if (mac->autoneg_failed == 0) { 00587 mac->autoneg_failed = 1; 00588 goto out; 00589 } 00590 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 00591 00592 /* Disable auto-negotiation in the TXCW register */ 00593 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 00594 00595 /* Force link-up and also force full-duplex. */ 00596 ctrl = er32(CTRL); 00597 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 00598 ew32(CTRL, ctrl); 00599 00600 /* Configure Flow Control after forcing link up. */ 00601 ret_val = e1000e_config_fc_after_link_up(hw); 00602 if (ret_val) { 00603 e_dbg("Error configuring flow control\n"); 00604 goto out; 00605 } 00606 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 00607 /* 00608 * If we are forcing link and we are receiving /C/ ordered 00609 * sets, re-enable auto-negotiation in the TXCW register 00610 * and disable forced link in the Device Control register 00611 * in an attempt to auto-negotiate with our link partner. 00612 */ 00613 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 00614 ew32(TXCW, mac->txcw); 00615 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 00616 00617 mac->serdes_has_link = true; 00618 } 00619 00620 out: 00621 return ret_val; 00622 }
e1000e_check_for_serdes_link - Check for link (Serdes) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 631 of file e1000e_mac.c.
Referenced by e1000e_init_mac_params_80003es2lan().
00632 { 00633 struct e1000_mac_info *mac = &hw->mac; 00634 u32 rxcw; 00635 u32 ctrl; 00636 u32 status; 00637 s32 ret_val = E1000_SUCCESS; 00638 00639 ctrl = er32(CTRL); 00640 status = er32(STATUS); 00641 rxcw = er32(RXCW); 00642 00643 /* 00644 * If we don't have link (auto-negotiation failed or link partner 00645 * cannot auto-negotiate), and our link partner is not trying to 00646 * auto-negotiate with us (we are receiving idles or data), 00647 * we need to force link up. We also need to give auto-negotiation 00648 * time to complete. 00649 */ 00650 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 00651 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 00652 if (mac->autoneg_failed == 0) { 00653 mac->autoneg_failed = 1; 00654 goto out; 00655 } 00656 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n"); 00657 00658 /* Disable auto-negotiation in the TXCW register */ 00659 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 00660 00661 /* Force link-up and also force full-duplex. */ 00662 ctrl = er32(CTRL); 00663 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 00664 ew32(CTRL, ctrl); 00665 00666 /* Configure Flow Control after forcing link up. */ 00667 ret_val = e1000e_config_fc_after_link_up(hw); 00668 if (ret_val) { 00669 e_dbg("Error configuring flow control\n"); 00670 goto out; 00671 } 00672 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 00673 /* 00674 * If we are forcing link and we are receiving /C/ ordered 00675 * sets, re-enable auto-negotiation in the TXCW register 00676 * and disable forced link in the Device Control register 00677 * in an attempt to auto-negotiate with our link partner. 00678 */ 00679 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n"); 00680 ew32(TXCW, mac->txcw); 00681 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 00682 00683 mac->serdes_has_link = true; 00684 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 00685 /* 00686 * If we force link for non-auto-negotiation switch, check 00687 * link status based on MAC synchronization for internal 00688 * serdes media type. 00689 */ 00690 /* SYNCH bit and IV bit are sticky. */ 00691 udelay(10); 00692 rxcw = er32(RXCW); 00693 if (rxcw & E1000_RXCW_SYNCH) { 00694 if (!(rxcw & E1000_RXCW_IV)) { 00695 mac->serdes_has_link = true; 00696 e_dbg("SERDES: Link up - forced.\n"); 00697 } 00698 } else { 00699 mac->serdes_has_link = false; 00700 e_dbg("SERDES: Link down - force failed.\n"); 00701 } 00702 } 00703 00704 if (E1000_TXCW_ANE & er32(TXCW)) { 00705 status = er32(STATUS); 00706 if (status & E1000_STATUS_LU) { 00707 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 00708 udelay(10); 00709 rxcw = er32(RXCW); 00710 if (rxcw & E1000_RXCW_SYNCH) { 00711 if (!(rxcw & E1000_RXCW_IV)) { 00712 mac->serdes_has_link = true; 00713 e_dbg("SERDES: Link up - autoneg " 00714 "completed sucessfully.\n"); 00715 } else { 00716 mac->serdes_has_link = false; 00717 e_dbg("SERDES: Link down - invalid" 00718 "codewords detected in autoneg.\n"); 00719 } 00720 } else { 00721 mac->serdes_has_link = false; 00722 e_dbg("SERDES: Link down - no sync.\n"); 00723 } 00724 } else { 00725 mac->serdes_has_link = false; 00726 e_dbg("SERDES: Link down - autoneg failed\n"); 00727 } 00728 } 00729 00730 out: 00731 return ret_val; 00732 }
Referenced by e1000e_init_mac_params_80003es2lan(), and e1000e_init_mac_params_82571().
Referenced by e1000e_init_mac_params_80003es2lan(), and e1000e_init_mac_params_82571().
e1000e_get_bus_info_pcie - Get PCIe bus information : pointer to the HW structure
Determines and stores the system bus information for a particular network interface. The following bus information is determined and stored: bus speed, bus width, type (PCIe), and PCIe function.
Definition at line 74 of file e1000e_mac.c.
Referenced by e1000e_get_bus_info_ich8lan(), e1000e_init_mac_params_80003es2lan(), and e1000e_init_mac_params_82571().
00075 { 00076 struct e1000_mac_info *mac = &hw->mac; 00077 struct e1000_bus_info *bus = &hw->bus; 00078 00079 s32 ret_val; 00080 u16 pcie_link_status; 00081 00082 bus->type = e1000_bus_type_pci_express; 00083 bus->speed = e1000_bus_speed_2500; 00084 00085 ret_val = e1000e_read_pcie_cap_reg(hw, 00086 PCIE_LINK_STATUS, 00087 &pcie_link_status); 00088 if (ret_val) 00089 bus->width = e1000_bus_width_unknown; 00090 else 00091 bus->width = (enum e1000_bus_width)((pcie_link_status & 00092 PCIE_LINK_WIDTH_MASK) >> 00093 PCIE_LINK_WIDTH_SHIFT); 00094 00095 mac->ops.set_lan_id(hw); 00096 00097 return E1000_SUCCESS; 00098 }
e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex
Read the status register for the current speed/duplex and store the current speed and duplex for copper connections.
Definition at line 1343 of file e1000e_mac.c.
Referenced by e1000e_cfg_on_link_up_80003es2lan(), e1000e_get_link_up_info_80003es2lan(), e1000e_get_link_up_info_ich8lan(), and e1000e_init_mac_params_82571().
01345 { 01346 u32 status; 01347 01348 status = er32(STATUS); 01349 if (status & E1000_STATUS_SPEED_1000) { 01350 *speed = SPEED_1000; 01351 e_dbg("1000 Mbs, "); 01352 } else if (status & E1000_STATUS_SPEED_100) { 01353 *speed = SPEED_100; 01354 e_dbg("100 Mbs, "); 01355 } else { 01356 *speed = SPEED_10; 01357 e_dbg("10 Mbs, "); 01358 } 01359 01360 if (status & E1000_STATUS_FD) { 01361 *duplex = FULL_DUPLEX; 01362 e_dbg("Full Duplex\n"); 01363 } else { 01364 *duplex = HALF_DUPLEX; 01365 e_dbg("Half Duplex\n"); 01366 } 01367 01368 return E1000_SUCCESS; 01369 }
Referenced by e1000e_get_link_up_info_80003es2lan(), and e1000e_init_mac_params_82571().
e1000e_disable_pcie_master - Disables PCI-express master access : pointer to the HW structure
Returns 0 (E1000_SUCCESS) if successful, else returns -10 (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused the master requests to be disabled.
Disables PCI-Express master access and verifies there are no pending requests.
Definition at line 1765 of file e1000e_mac.c.
Referenced by e1000e_reset_hw_80003es2lan(), e1000e_reset_hw_82571(), and e1000e_reset_hw_ich8lan().
01766 { 01767 u32 ctrl; 01768 s32 timeout = MASTER_DISABLE_TIMEOUT; 01769 s32 ret_val = E1000_SUCCESS; 01770 01771 if (hw->bus.type != e1000_bus_type_pci_express) 01772 goto out; 01773 01774 ctrl = er32(CTRL); 01775 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 01776 ew32(CTRL, ctrl); 01777 01778 while (timeout) { 01779 if (!(er32(STATUS) & 01780 E1000_STATUS_GIO_MASTER_ENABLE)) 01781 break; 01782 udelay(100); 01783 timeout--; 01784 } 01785 01786 if (!timeout) { 01787 e_dbg("Master requests are pending.\n"); 01788 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 01789 goto out; 01790 } 01791 01792 out: 01793 return ret_val; 01794 }
e1000e_get_auto_rd_done - Check for auto read completion : pointer to the HW structure
Check EEPROM for Auto Read done bit.
Definition at line 1462 of file e1000e_mac.c.
Referenced by e1000e_reset_hw_80003es2lan(), e1000e_reset_hw_82571(), and e1000e_reset_hw_ich8lan().
01463 { 01464 s32 i = 0; 01465 s32 ret_val = E1000_SUCCESS; 01466 01467 while (i < AUTO_READ_DONE_TIMEOUT) { 01468 if (er32(EECD) & E1000_EECD_AUTO_RD) 01469 break; 01470 msleep(1); 01471 i++; 01472 } 01473 01474 if (i == AUTO_READ_DONE_TIMEOUT) { 01475 e_dbg("Auto read by HW from NVM has not completed.\n"); 01476 ret_val = -E1000_ERR_RESET; 01477 goto out; 01478 } 01479 01480 out: 01481 return ret_val; 01482 }
| void e1000e_clear_hw_cntrs_base | ( | struct e1000_hw * | hw | ) |
e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes : pointer to the HW structure
Configures collision distance and flow control for fiber and serdes links. Upon successful setup, poll for link.
Definition at line 806 of file e1000e_mac.c.
Referenced by e1000e_init_mac_params_80003es2lan(), and e1000e_setup_fiber_serdes_link_82571().
00807 { 00808 u32 ctrl; 00809 s32 ret_val = E1000_SUCCESS; 00810 00811 ctrl = er32(CTRL); 00812 00813 /* Take the link out of reset */ 00814 ctrl &= ~E1000_CTRL_LRST; 00815 00816 e1000e_config_collision_dist(hw); 00817 00818 ret_val = e1000e_commit_fc_settings_generic(hw); 00819 if (ret_val) 00820 goto out; 00821 00822 /* 00823 * Since auto-negotiation is enabled, take the link out of reset (the 00824 * link will be in reset, because we previously reset the chip). This 00825 * will restart auto-negotiation. If auto-negotiation is successful 00826 * then the link-up status bit will be set and the flow control enable 00827 * bits (RFCE and TFCE) will be set according to their negotiated value. 00828 */ 00829 e_dbg("Auto-negotiation enabled\n"); 00830 00831 ew32(CTRL, ctrl); 00832 e1e_flush(); 00833 msleep(1); 00834 00835 /* 00836 * For these adapters, the SW definable pin 1 is set when the optics 00837 * detect a signal. If we have a signal, then poll for a "Link-Up" 00838 * indication. 00839 */ 00840 if (hw->phy.media_type == e1000_media_type_internal_serdes || 00841 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { 00842 ret_val = e1000e_poll_fiber_serdes_link_generic(hw); 00843 } else { 00844 e_dbg("No signal detected\n"); 00845 } 00846 00847 out: 00848 return ret_val; 00849 }
e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link : pointer to the HW structure
Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock and downshift values are set also.
Definition at line 653 of file e1000e_phy.c.
Referenced by e1000e_setup_copper_link_82571(), and e1000e_setup_copper_link_ich8lan().
00654 { 00655 struct e1000_phy_info *phy = &hw->phy; 00656 s32 ret_val; 00657 u16 phy_data; 00658 00659 if (phy->reset_disable) { 00660 ret_val = E1000_SUCCESS; 00661 goto out; 00662 } 00663 00664 /* Enable CRS on TX. This must be set for half-duplex operation. */ 00665 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 00666 if (ret_val) 00667 goto out; 00668 00669 /* For BM PHY this bit is downshift enable */ 00670 if (phy->type != e1000_phy_bm) 00671 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 00672 00673 /* 00674 * Options: 00675 * MDI/MDI-X = 0 (default) 00676 * 0 - Auto for all speeds 00677 * 1 - MDI mode 00678 * 2 - MDI-X mode 00679 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 00680 */ 00681 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 00682 00683 switch (phy->mdix) { 00684 case 1: 00685 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 00686 break; 00687 case 2: 00688 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 00689 break; 00690 case 3: 00691 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 00692 break; 00693 case 0: 00694 default: 00695 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 00696 break; 00697 } 00698 00699 /* 00700 * Options: 00701 * disable_polarity_correction = 0 (default) 00702 * Automatic Correction for Reversed Cable Polarity 00703 * 0 - Disabled 00704 * 1 - Enabled 00705 */ 00706 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 00707 if (phy->disable_polarity_correction == 1) 00708 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 00709 00710 /* Enable downshift on BM (disabled by default) */ 00711 if (phy->type == e1000_phy_bm) 00712 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 00713 00714 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 00715 if (ret_val) 00716 goto out; 00717 00718 if ((phy->type == e1000_phy_m88) && 00719 (phy->revision < E1000_REVISION_4) && 00720 (phy->id != BME1000_E_PHY_ID_R2)) { 00721 /* 00722 * Force TX_CLK in the Extended PHY Specific Control Register 00723 * to 25MHz clock. 00724 */ 00725 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00726 &phy_data); 00727 if (ret_val) 00728 goto out; 00729 00730 phy_data |= M88E1000_EPSCR_TX_CLK_25; 00731 00732 if ((phy->revision == E1000_REVISION_2) && 00733 (phy->id == M88E1111_I_PHY_ID)) { 00734 /* 82573L PHY - set the downshift counter to 5x. */ 00735 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 00736 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 00737 } else { 00738 /* Configure Master and Slave downshift values */ 00739 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 00740 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 00741 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 00742 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 00743 } 00744 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00745 phy_data); 00746 if (ret_val) 00747 goto out; 00748 } 00749 00750 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 00751 /* Set PHY page 0, register 29 to 0x0003 */ 00752 ret_val = e1e_wphy(hw, 29, 0x0003); 00753 if (ret_val) 00754 goto out; 00755 00756 /* Set PHY page 0, register 30 to 0x0000 */ 00757 ret_val = e1e_wphy(hw, 30, 0x0000); 00758 if (ret_val) 00759 goto out; 00760 } 00761 00762 /* Commit the changes. */ 00763 ret_val = e1000e_commit_phy(hw); 00764 if (ret_val) { 00765 e_dbg("Error committing the PHY changes\n"); 00766 goto out; 00767 } 00768 00769 if (phy->type == e1000_phy_82578) { 00770 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00771 &phy_data); 00772 if (ret_val) 00773 goto out; 00774 00775 /* 82578 PHY - set the downshift count to 1x. */ 00776 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 00777 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 00778 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00779 phy_data); 00780 if (ret_val) 00781 goto out; 00782 } 00783 00784 out: 00785 return ret_val; 00786 }
e1000e_copper_link_setup_igp - Setup igp PHY's for copper link : pointer to the HW structure
Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for igp PHY's.
Definition at line 795 of file e1000e_phy.c.
Referenced by e1000e_setup_copper_link_82571(), and e1000e_setup_copper_link_ich8lan().
00796 { 00797 struct e1000_phy_info *phy = &hw->phy; 00798 s32 ret_val; 00799 u16 data; 00800 00801 if (phy->reset_disable) { 00802 ret_val = E1000_SUCCESS; 00803 goto out; 00804 } 00805 00806 ret_val = e1000e_phy_hw_reset(hw); 00807 if (ret_val) { 00808 e_dbg("Error resetting the PHY.\n"); 00809 goto out; 00810 } 00811 00812 /* 00813 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 00814 * timeout issues when LFS is enabled. 00815 */ 00816 msleep(100); 00817 00818 /* 00819 * The NVM settings will configure LPLU in D3 for 00820 * non-IGP1 PHYs. 00821 */ 00822 if (phy->type == e1000_phy_igp) { 00823 /* disable lplu d3 during driver init */ 00824 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 00825 if (ret_val) { 00826 e_dbg("Error Disabling LPLU D3\n"); 00827 goto out; 00828 } 00829 } 00830 00831 /* disable lplu d0 during driver init */ 00832 if (hw->phy.ops.set_d0_lplu_state) { 00833 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 00834 if (ret_val) { 00835 e_dbg("Error Disabling LPLU D0\n"); 00836 goto out; 00837 } 00838 } 00839 /* Configure mdi-mdix settings */ 00840 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); 00841 if (ret_val) 00842 goto out; 00843 00844 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 00845 00846 switch (phy->mdix) { 00847 case 1: 00848 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 00849 break; 00850 case 2: 00851 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 00852 break; 00853 case 0: 00854 default: 00855 data |= IGP01E1000_PSCR_AUTO_MDIX; 00856 break; 00857 } 00858 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); 00859 if (ret_val) 00860 goto out; 00861 00862 /* set auto-master slave resolution settings */ 00863 if (hw->mac.autoneg) { 00864 /* 00865 * when autonegotiation advertisement is only 1000Mbps then we 00866 * should disable SmartSpeed and enable Auto MasterSlave 00867 * resolution as hardware default. 00868 */ 00869 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 00870 /* Disable SmartSpeed */ 00871 ret_val = e1e_rphy(hw, 00872 IGP01E1000_PHY_PORT_CONFIG, 00873 &data); 00874 if (ret_val) 00875 goto out; 00876 00877 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 00878 ret_val = e1e_wphy(hw, 00879 IGP01E1000_PHY_PORT_CONFIG, 00880 data); 00881 if (ret_val) 00882 goto out; 00883 00884 /* Set auto Master/Slave resolution process */ 00885 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 00886 if (ret_val) 00887 goto out; 00888 00889 data &= ~CR_1000T_MS_ENABLE; 00890 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 00891 if (ret_val) 00892 goto out; 00893 } 00894 00895 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); 00896 if (ret_val) 00897 goto out; 00898 00899 /* load defaults for future use */ 00900 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 00901 ((data & CR_1000T_MS_VALUE) ? 00902 e1000_ms_force_master : 00903 e1000_ms_force_slave) : 00904 e1000_ms_auto; 00905 00906 switch (phy->ms_type) { 00907 case e1000_ms_force_master: 00908 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 00909 break; 00910 case e1000_ms_force_slave: 00911 data |= CR_1000T_MS_ENABLE; 00912 data &= ~(CR_1000T_MS_VALUE); 00913 break; 00914 case e1000_ms_auto: 00915 data &= ~CR_1000T_MS_ENABLE; 00916 default: 00917 break; 00918 } 00919 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); 00920 if (ret_val) 00921 goto out; 00922 } 00923 00924 out: 00925 return ret_val; 00926 }
e1000e_setup_link - Setup flow control and link settings : pointer to the HW structure
Determines which flow control settings to use, then configures flow control. Calls the appropriate media-specific link configuration function. Assuming the adapter has a valid link partner, a valid link should be established. Assumes the hardware has previously been reset and the transmitter and receiver are not enabled.
Definition at line 744 of file e1000e_mac.c.
Referenced by e1000e_init_mac_params_80003es2lan(), and e1000e_setup_link_82571().
00745 { 00746 s32 ret_val = E1000_SUCCESS; 00747 00748 /* 00749 * In the case of the phy reset being blocked, we already have a link. 00750 * We do not need to set it up again. 00751 */ 00752 if (hw->phy.ops.check_reset_block) 00753 if (e1000e_check_reset_block(hw)) 00754 goto out; 00755 00756 /* 00757 * If requested flow control is set to default, set flow control 00758 * based on the EEPROM flow control settings. 00759 */ 00760 if (hw->fc.requested_mode == e1000_fc_default) { 00761 ret_val = e1000e_set_default_fc_generic(hw); 00762 if (ret_val) 00763 goto out; 00764 } 00765 00766 /* 00767 * Save off the requested flow control mode for use later. Depending 00768 * on the link partner's capabilities, we may or may not use this mode. 00769 */ 00770 hw->fc.current_mode = hw->fc.requested_mode; 00771 00772 e_dbg("After fix-ups FlowControl is now = %x\n", 00773 hw->fc.current_mode); 00774 00775 /* Call the necessary media_type subroutine to configure the link. */ 00776 ret_val = hw->mac.ops.setup_physical_interface(hw); 00777 if (ret_val) 00778 goto out; 00779 00780 /* 00781 * Initialize the flow control address, type, and PAUSE timer 00782 * registers to their default values. This is done even if flow 00783 * control is disabled, because it does not hurt anything to 00784 * initialize these registers. 00785 */ 00786 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 00787 ew32(FCT, FLOW_CONTROL_TYPE); 00788 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 00789 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 00790 00791 ew32(FCTTV, hw->fc.pause_time); 00792 00793 ret_val = e1000e_set_fc_watermarks(hw); 00794 00795 out: 00796 return ret_val; 00797 }
| static void e1000e_clear_vfta | ( | struct e1000_hw * | hw | ) | [inline, static] |
Definition at line 322 of file e1000e.h.
References e1000_mac_operations::clear_vfta, e1000_hw::mac, and e1000_mac_info::ops.
Referenced by e1000e_init_hw_80003es2lan(), and e1000e_init_hw_82571().
00323 { 00324 hw->mac.ops.clear_vfta(hw); 00325 }
e1000e_init_rx_addrs - Initialize receive address's : pointer to the HW structure : receive address registers
Setups the receive address registers by setting the base receive address register to the devices MAC address and clearing all the other receive address registers to 0.
Definition at line 175 of file e1000e_mac.c.
Referenced by e1000e_init_hw_80003es2lan(), e1000e_init_hw_82571(), and e1000e_init_hw_ich8lan().
00176 { 00177 u32 i; 00178 u8 mac_addr[ETH_ADDR_LEN] = {0}; 00179 00180 /* Setup the receive address */ 00181 e_dbg("Programming MAC Address into RAR[0]\n"); 00182 00183 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 00184 00185 /* Zero out the other (rar_entry_count - 1) receive addresses */ 00186 e_dbg("Clearing RAR[1-%u]\n", rar_count-1); 00187 for (i = 1; i < rar_count; i++) 00188 hw->mac.ops.rar_set(hw, mac_addr, i); 00189 }
| void e1000e_update_mc_addr_list_generic | ( | struct e1000_hw * | hw, | |
| u8 * | mc_addr_list, | |||
| u32 | mc_addr_count | |||
| ) |
e1000e_update_mc_addr_list_generic - Update Multicast addresses : pointer to the HW structure : array of multicast addresses to program : number of multicast addresses to program
Updates entire Multicast Table Array. The caller must have a packed mc_addr_list of multicast addresses.
Definition at line 335 of file e1000e_mac.c.
Referenced by e1000e_init_mac_params_80003es2lan(), e1000e_init_mac_params_82571(), and e1000e_init_mac_params_ich8lan().
00337 { 00338 u32 hash_value, hash_bit, hash_reg; 00339 int i; 00340 00341 /* clear mta_shadow */ 00342 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 00343 00344 /* update mta_shadow from mc_addr_list */ 00345 for (i = 0; (u32) i < mc_addr_count; i++) { 00346 hash_value = e1000e_hash_mc_addr_generic(hw, mc_addr_list); 00347 00348 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 00349 hash_bit = hash_value & 0x1F; 00350 00351 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 00352 mc_addr_list += (ETH_ADDR_LEN); 00353 } 00354 00355 /* replace the entire MTA table */ 00356 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 00357 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 00358 e1e_flush(); 00359 }
e1000e_rar_set - Set receive address register : pointer to the HW structure : pointer to the receive address : receive address array register
Sets the receive address array register at index to the address passed in by addr.
Definition at line 262 of file e1000e_mac.c.
Referenced by e1000e_init_mac_ops_generic(), and e1000e_set_laa_state_82571().
00263 { 00264 u32 rar_low, rar_high; 00265 00266 /* 00267 * HW expects these in little endian so we reverse the byte order 00268 * from network order (big endian) to little endian 00269 */ 00270 rar_low = ((u32) addr[0] | 00271 ((u32) addr[1] << 8) | 00272 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 00273 00274 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 00275 00276 /* If MAC address zero, no need to set the AV bit */ 00277 if (rar_low || rar_high) 00278 rar_high |= E1000_RAH_AV; 00279 00280 /* 00281 * Some bridges will combine consecutive 32-bit writes into 00282 * a single burst write, which will malfunction on some parts. 00283 * The flushes avoid this. 00284 */ 00285 ew32(RAL(index), rar_low); 00286 e1e_flush(); 00287 ew32(RAH(index), rar_high); 00288 e1e_flush(); 00289 }
e1000e_set_fc_watermarks - Set flow control high/low watermarks : pointer to the HW structure
Sets the flow control high/low threshold (watermark) registers. If flow control XON frame transmission is enabled, then set XON frame transmission as well.
Definition at line 1004 of file e1000e_mac.c.
Referenced by e1000e_setup_link(), and e1000e_setup_link_ich8lan().
01005 { 01006 s32 ret_val = E1000_SUCCESS; 01007 u32 fcrtl = 0, fcrth = 0; 01008 01009 /* 01010 * Set the flow control receive threshold registers. Normally, 01011 * these registers will be set to a default threshold that may be 01012 * adjusted later by the driver's runtime code. However, if the 01013 * ability to transmit pause frames is not enabled, then these 01014 * registers will be set to 0. 01015 */ 01016 if (hw->fc.current_mode & e1000_fc_tx_pause) { 01017 /* 01018 * We need to set up the Receive Threshold high and low water 01019 * marks as well as (optionally) enabling the transmission of 01020 * XON frames. 01021 */ 01022 fcrtl = hw->fc.low_water; 01023 if (hw->fc.send_xon) 01024 fcrtl |= E1000_FCRTL_XONE; 01025 01026 fcrth = hw->fc.high_water; 01027 } 01028 ew32(FCRTL, fcrtl); 01029 ew32(FCRTH, fcrth); 01030 01031 return ret_val; 01032 }
e1000e_set_pcie_no_snoop - Set PCI-express capabilities : pointer to the HW structure : bitmap of snoop events
Set the PCI-express register to snoop for events enabled in 'no_snoop'.
Definition at line 1737 of file e1000e_mac.c.
Referenced by e1000e_init_hw_ich8lan().
01738 { 01739 u32 gcr; 01740 01741 if (hw->bus.type != e1000_bus_type_pci_express) 01742 goto out; 01743 01744 if (no_snoop) { 01745 gcr = er32(GCR); 01746 gcr &= ~(PCIE_NO_SNOOP_ALL); 01747 gcr |= no_snoop; 01748 ew32(GCR, gcr); 01749 } 01750 out: 01751 return; 01752 }
e1000e_get_hw_semaphore - Acquire hardware semaphore : pointer to the HW structure
Acquire the HW semaphore to access the PHY or NVM
Definition at line 1395 of file e1000e_mac.c.
Referenced by e1000e_acquire_swfw_sync_80003es2lan(), and e1000e_release_swfw_sync_80003es2lan().
01396 { 01397 u32 swsm; 01398 s32 ret_val = E1000_SUCCESS; 01399 s32 timeout = hw->nvm.word_size + 1; 01400 s32 i = 0; 01401 01402 /* Get the SW semaphore */ 01403 while (i < timeout) { 01404 swsm = er32(SWSM); 01405 if (!(swsm & E1000_SWSM_SMBI)) 01406 break; 01407 01408 udelay(50); 01409 i++; 01410 } 01411 01412 if (i == timeout) { 01413 e_dbg("Driver can't access device - SMBI bit is set.\n"); 01414 ret_val = -E1000_ERR_NVM; 01415 goto out; 01416 } 01417 01418 /* Get the FW semaphore. */ 01419 for (i = 0; i < timeout; i++) { 01420 swsm = er32(SWSM); 01421 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 01422 01423 /* Semaphore acquired if bit latched */ 01424 if (er32(SWSM) & E1000_SWSM_SWESMBI) 01425 break; 01426 01427 udelay(50); 01428 } 01429 01430 if (i == timeout) { 01431 /* Release semaphores */ 01432 e1000e_put_hw_semaphore(hw); 01433 e_dbg("Driver can't access the NVM\n"); 01434 ret_val = -E1000_ERR_NVM; 01435 goto out; 01436 } 01437 01438 out: 01439 return ret_val; 01440 }
e1000e_valid_led_default - Verify a valid default LED config : pointer to the HW structure : pointer to the NVM (EEPROM)
Read the EEPROM for the current default LED configuration. If the LED configuration is not valid, set to a valid LED configuration.
Definition at line 1492 of file e1000e_mac.c.
Referenced by e1000e_init_nvm_params_80003es2lan().
01493 { 01494 s32 ret_val; 01495 01496 ret_val = e1000e_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 01497 if (ret_val) { 01498 e_dbg("NVM Read Error\n"); 01499 goto out; 01500 } 01501 01502 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 01503 *data = ID_LED_DEFAULT; 01504 01505 out: 01506 return ret_val; 01507 }
| void e1000e_config_collision_dist | ( | struct e1000_hw * | hw | ) |
e1000e_config_collision_dist - Configure collision distance : pointer to the HW structure
Configures the collision distance to the default value and is used during link setup. Currently no func pointer exists and all implementations are handled in the generic version of this function.
Definition at line 859 of file e1000e_mac.c.
Referenced by e1000e_check_for_copper_link(), e1000e_check_for_copper_link_ich8lan(), e1000e_configure_tx(), e1000e_init_mac_ops_generic(), e1000e_setup_copper_link(), and e1000e_setup_fiber_serdes_link().
00860 { 00861 u32 tctl; 00862 00863 tctl = er32(TCTL); 00864 00865 tctl &= ~E1000_TCTL_COLD; 00866 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 00867 00868 ew32(TCTL, tctl); 00869 e1e_flush(); 00870 }
e1000e_config_fc_after_link_up - Configures flow control after link : pointer to the HW structure
Checks the status of auto-negotiation after link up to ensure that the speed and duplex were not forced. If the link needed to be forced, then flow control needs to be forced also. If auto-negotiation is enabled and did not fail, then we configure flow control based on our link partner.
Definition at line 1148 of file e1000e_mac.c.
Referenced by e1000e_check_for_copper_link(), e1000e_check_for_copper_link_ich8lan(), e1000e_check_for_fiber_link(), e1000e_check_for_serdes_link(), e1000e_check_for_serdes_link_82571(), and e1000e_setup_copper_link().
01149 { 01150 struct e1000_mac_info *mac = &hw->mac; 01151 s32 ret_val = E1000_SUCCESS; 01152 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 01153 u16 speed, duplex; 01154 01155 /* 01156 * Check for the case where we have fiber media and auto-neg failed 01157 * so we had to force link. In this case, we need to force the 01158 * configuration of the MAC to match the "fc" parameter. 01159 */ 01160 if (mac->autoneg_failed) { 01161 if (hw->phy.media_type == e1000_media_type_fiber || 01162 hw->phy.media_type == e1000_media_type_internal_serdes) 01163 ret_val = e1000e_force_mac_fc(hw); 01164 } else { 01165 if (hw->phy.media_type == e1000_media_type_copper) 01166 ret_val = e1000e_force_mac_fc(hw); 01167 } 01168 01169 if (ret_val) { 01170 e_dbg("Error forcing flow control settings\n"); 01171 goto out; 01172 } 01173 01174 /* 01175 * Check for the case where we have copper media and auto-neg is 01176 * enabled. In this case, we need to check and see if Auto-Neg 01177 * has completed, and if so, how the PHY and link partner has 01178 * flow control configured. 01179 */ 01180 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 01181 /* 01182 * Read the MII Status Register and check to see if AutoNeg 01183 * has completed. We read this twice because this reg has 01184 * some "sticky" (latched) bits. 01185 */ 01186 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 01187 if (ret_val) 01188 goto out; 01189 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 01190 if (ret_val) 01191 goto out; 01192 01193 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 01194 e_dbg("Copper PHY and Auto Neg " 01195 "has not completed.\n"); 01196 goto out; 01197 } 01198 01199 /* 01200 * The AutoNeg process has completed, so we now need to 01201 * read both the Auto Negotiation Advertisement 01202 * Register (Address 4) and the Auto_Negotiation Base 01203 * Page Ability Register (Address 5) to determine how 01204 * flow control was negotiated. 01205 */ 01206 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, 01207 &mii_nway_adv_reg); 01208 if (ret_val) 01209 goto out; 01210 ret_val = e1e_rphy(hw, PHY_LP_ABILITY, 01211 &mii_nway_lp_ability_reg); 01212 if (ret_val) 01213 goto out; 01214 01215 /* 01216 * Two bits in the Auto Negotiation Advertisement Register 01217 * (Address 4) and two bits in the Auto Negotiation Base 01218 * Page Ability Register (Address 5) determine flow control 01219 * for both the PHY and the link partner. The following 01220 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 01221 * 1999, describes these PAUSE resolution bits and how flow 01222 * control is determined based upon these settings. 01223 * NOTE: DC = Don't Care 01224 * 01225 * LOCAL DEVICE | LINK PARTNER 01226 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 01227 *-------|---------|-------|---------|-------------------- 01228 * 0 | 0 | DC | DC | e1000_fc_none 01229 * 0 | 1 | 0 | DC | e1000_fc_none 01230 * 0 | 1 | 1 | 0 | e1000_fc_none 01231 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 01232 * 1 | 0 | 0 | DC | e1000_fc_none 01233 * 1 | DC | 1 | DC | e1000_fc_full 01234 * 1 | 1 | 0 | 0 | e1000_fc_none 01235 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 01236 * 01237 * Are both PAUSE bits set to 1? If so, this implies 01238 * Symmetric Flow Control is enabled at both ends. The 01239 * ASM_DIR bits are irrelevant per the spec. 01240 * 01241 * For Symmetric Flow Control: 01242 * 01243 * LOCAL DEVICE | LINK PARTNER 01244 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01245 *-------|---------|-------|---------|-------------------- 01246 * 1 | DC | 1 | DC | E1000_fc_full 01247 * 01248 */ 01249 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 01250 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 01251 /* 01252 * Now we need to check if the user selected Rx ONLY 01253 * of pause frames. In this case, we had to advertise 01254 * FULL flow control because we could not advertise RX 01255 * ONLY. Hence, we must now check to see if we need to 01256 * turn OFF the TRANSMISSION of PAUSE frames. 01257 */ 01258 if (hw->fc.requested_mode == e1000_fc_full) { 01259 hw->fc.current_mode = e1000_fc_full; 01260 e_dbg("Flow Control = FULL.\r\n"); 01261 } else { 01262 hw->fc.current_mode = e1000_fc_rx_pause; 01263 e_dbg("Flow Control = " 01264 "RX PAUSE frames only.\r\n"); 01265 } 01266 } 01267 /* 01268 * For receiving PAUSE frames ONLY. 01269 * 01270 * LOCAL DEVICE | LINK PARTNER 01271 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01272 *-------|---------|-------|---------|-------------------- 01273 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 01274 */ 01275 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 01276 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 01277 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 01278 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 01279 hw->fc.current_mode = e1000_fc_tx_pause; 01280 e_dbg("Flow Control = TX PAUSE frames only.\r\n"); 01281 } 01282 /* 01283 * For transmitting PAUSE frames ONLY. 01284 * 01285 * LOCAL DEVICE | LINK PARTNER 01286 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01287 *-------|---------|-------|---------|-------------------- 01288 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 01289 */ 01290 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 01291 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 01292 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 01293 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 01294 hw->fc.current_mode = e1000_fc_rx_pause; 01295 e_dbg("Flow Control = RX PAUSE frames only.\r\n"); 01296 } else { 01297 /* 01298 * Per the IEEE spec, at this point flow control 01299 * should be disabled. 01300 */ 01301 hw->fc.current_mode = e1000_fc_none; 01302 e_dbg("Flow Control = NONE.\r\n"); 01303 } 01304 01305 /* 01306 * Now we need to do one last check... If we auto- 01307 * negotiated to HALF DUPLEX, flow control should not be 01308 * enabled per IEEE 802.3 spec. 01309 */ 01310 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 01311 if (ret_val) { 01312 e_dbg("Error getting link speed and duplex\n"); 01313 goto out; 01314 } 01315 01316 if (duplex == HALF_DUPLEX) 01317 hw->fc.current_mode = e1000_fc_none; 01318 01319 /* 01320 * Now we call a subroutine to actually force the MAC 01321 * controller to use the correct flow control settings. 01322 */ 01323 ret_val = e1000e_force_mac_fc(hw); 01324 if (ret_val) { 01325 e_dbg("Error forcing flow control settings\n"); 01326 goto out; 01327 } 01328 } 01329 01330 out: 01331 return ret_val; 01332 }
e1000e_force_mac_fc - Force the MAC's flow control settings : pointer to the HW structure
Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the device control register to reflect the adapter settings. TFCE and RFCE need to be explicitly set by software when a copper PHY is used because autonegotiation is managed by the PHY rather than the MAC. Software must also configure these bits when link is forced on a fiber connection.
Definition at line 1084 of file e1000e_mac.c.
Referenced by e1000e_config_fc_after_link_up().
01085 { 01086 u32 ctrl; 01087 s32 ret_val = E1000_SUCCESS; 01088 01089 ctrl = er32(CTRL); 01090 01091 /* 01092 * Because we didn't get link via the internal auto-negotiation 01093 * mechanism (we either forced link or we got link via PHY 01094 * auto-neg), we have to manually enable/disable transmit an 01095 * receive flow control. 01096 * 01097 * The "Case" statement below enables/disable flow control 01098 * according to the "hw->fc.current_mode" parameter. 01099 * 01100 * The possible values of the "fc" parameter are: 01101 * 0: Flow control is completely disabled 01102 * 1: Rx flow control is enabled (we can receive pause 01103 * frames but not send pause frames). 01104 * 2: Tx flow control is enabled (we can send pause frames 01105 * frames but we do not receive pause frames). 01106 * 3: Both Rx and Tx flow control (symmetric) is enabled. 01107 * other: No other values should be possible at this point. 01108 */ 01109 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 01110 01111 switch (hw->fc.current_mode) { 01112 case e1000_fc_none: 01113 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 01114 break; 01115 case e1000_fc_rx_pause: 01116 ctrl &= (~E1000_CTRL_TFCE); 01117 ctrl |= E1000_CTRL_RFCE; 01118 break; 01119 case e1000_fc_tx_pause: 01120 ctrl &= (~E1000_CTRL_RFCE); 01121 ctrl |= E1000_CTRL_TFCE; 01122 break; 01123 case e1000_fc_full: 01124 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 01125 break; 01126 default: 01127 e_dbg("Flow control param set incorrectly\n"); 01128 ret_val = -E1000_ERR_CONFIG; 01129 goto out; 01130 } 01131 01132 ew32(CTRL, ctrl); 01133 01134 out: 01135 return ret_val; 01136 }
e1000e_write_vfta_generic - Write value to VLAN filter table : pointer to the HW structure : register offset in VLAN filter table : register value written to VLAN filter table
Writes value at the given offset in the register array which stores the VLAN filter table.
Definition at line 160 of file e1000e_mac.c.
Referenced by e1000e_init_mac_params_80003es2lan(), and e1000e_init_mac_params_82571().
00161 { 00162 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 00163 e1e_flush(); 00164 }
Definition at line 340 of file e1000e.h.
References e1000_hw::mac, e1000_mac_info::ops, and e1000_mac_operations::write_vfta.
00341 { 00342 if (hw->mac.ops.write_vfta) 00343 hw->mac.ops.write_vfta(hw, offset, value); 00344 }
| void e1000e_reset_adaptive | ( | struct e1000_hw * | hw | ) |
e1000e_reset_adaptive - Reset Adaptive Interframe Spacing : pointer to the HW structure
Reset the Adaptive Interframe Spacing throttle to default values.
Definition at line 1802 of file e1000e_mac.c.
Referenced by e1000e_reset().
01803 { 01804 struct e1000_mac_info *mac = &hw->mac; 01805 01806 if (!mac->adaptive_ifs) { 01807 e_dbg("Not in Adaptive IFS mode!\n"); 01808 goto out; 01809 } 01810 01811 mac->current_ifs_val = 0; 01812 mac->ifs_min_val = IFS_MIN; 01813 mac->ifs_max_val = IFS_MAX; 01814 mac->ifs_step_size = IFS_STEP; 01815 mac->ifs_ratio = IFS_RATIO; 01816 01817 mac->in_ifs_mode = false; 01818 ew32(AIT, 0); 01819 out: 01820 return; 01821 }
| void e1000e_update_adaptive | ( | struct e1000_hw * | hw | ) |
e1000e_update_adaptive - Update Adaptive Interframe Spacing : pointer to the HW structure
Update the Adaptive Interframe Spacing Throttle value based on the time between transmitted packets and time between collisions.
Definition at line 1830 of file e1000e_mac.c.
01831 { 01832 struct e1000_mac_info *mac = &hw->mac; 01833 01834 if (!mac->adaptive_ifs) { 01835 e_dbg("Not in Adaptive IFS mode!\n"); 01836 goto out; 01837 } 01838 01839 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 01840 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 01841 mac->in_ifs_mode = true; 01842 if (mac->current_ifs_val < mac->ifs_max_val) { 01843 if (!mac->current_ifs_val) 01844 mac->current_ifs_val = mac->ifs_min_val; 01845 else 01846 mac->current_ifs_val += 01847 mac->ifs_step_size; 01848 ew32(AIT, mac->current_ifs_val); 01849 } 01850 } 01851 } else { 01852 if (mac->in_ifs_mode && 01853 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 01854 mac->current_ifs_val = 0; 01855 mac->in_ifs_mode = false; 01856 ew32(AIT, 0); 01857 } 01858 } 01859 out: 01860 return; 01861 }
e1000e_setup_copper_link - Configure copper link settings : pointer to the HW structure
Calls the appropriate function to configure the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called. If link is not established, we return -E1000_ERR_PHY (-2).
Definition at line 1169 of file e1000e_phy.c.
Referenced by e1000e_setup_copper_link_80003es2lan(), e1000e_setup_copper_link_82571(), and e1000e_setup_copper_link_ich8lan().
01170 { 01171 s32 ret_val; 01172 bool link; 01173 01174 if (hw->mac.autoneg) { 01175 /* 01176 * Setup autoneg and flow control advertisement and perform 01177 * autonegotiation. 01178 */ 01179 ret_val = e1000e_copper_link_autoneg(hw); 01180 if (ret_val) 01181 goto out; 01182 } else { 01183 #if 0 01184 /* 01185 * PHY will be set to 10H, 10F, 100H or 100F 01186 * depending on user settings. 01187 */ 01188 e_dbg("Forcing Speed and Duplex\n"); 01189 ret_val = hw->phy.ops.force_speed_duplex(hw); 01190 if (ret_val) { 01191 e_dbg("Error Forcing Speed and Duplex\n"); 01192 goto out; 01193 } 01194 #endif 01195 } 01196 01197 /* 01198 * Check link status. Wait up to 100 microseconds for link to become 01199 * valid. 01200 */ 01201 ret_val = e1000e_phy_has_link_generic(hw, 01202 COPPER_LINK_UP_LIMIT, 01203 10, 01204 &link); 01205 if (ret_val) 01206 goto out; 01207 01208 if (link) { 01209 e_dbg("Valid link established!!!\n"); 01210 e1000e_config_collision_dist(hw); 01211 ret_val = e1000e_config_fc_after_link_up(hw); 01212 } else { 01213 e_dbg("Unable to establish link!!!\n"); 01214 } 01215 01216 out: 01217 return ret_val; 01218 }
| void e1000e_put_hw_semaphore | ( | struct e1000_hw * | hw | ) |
e1000e_put_hw_semaphore - Release hardware semaphore : pointer to the HW structure
Release hardware semaphore used to access the PHY or NVM
Definition at line 1448 of file e1000e_mac.c.
Referenced by e1000e_acquire_swfw_sync_80003es2lan(), e1000e_get_hw_semaphore(), and e1000e_release_swfw_sync_80003es2lan().
01449 { 01450 u32 swsm; 01451 01452 swsm = er32(SWSM); 01453 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 01454 ew32(SWSM, swsm); 01455 }
e1000e_check_reset_block_generic - Check if PHY reset is blocked : pointer to the HW structure
Read the PHY management control register and check whether a PHY reset is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise return E1000_BLK_PHY_RESET (12).
Definition at line 71 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_80003es2lan(), and e1000e_init_phy_params_82571().
00072 { 00073 u32 manc; 00074 00075 manc = er32(MANC); 00076 00077 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 00078 E1000_BLK_PHY_RESET : E1000_SUCCESS; 00079 }
e1000e_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure
Read PHY status to determine if link is up. If link is up, then set/determine 10base-T extended distance and polarity correction. Read PHY port status to determine MDI/MDIx and speed. Based on the speed, determine on the cable length, local and remote receiver.
Definition at line 2062 of file e1000e_phy.c.
Referenced by e1000e_get_phy_info_ich8lan(), and e1000e_init_phy_params_82571().
02063 { 02064 struct e1000_phy_info *phy = &hw->phy; 02065 s32 ret_val; 02066 u16 data; 02067 bool link; 02068 02069 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 02070 if (ret_val) 02071 goto out; 02072 02073 if (!link) { 02074 e_dbg("Phy info is only valid if link is up\n"); 02075 ret_val = -E1000_ERR_CONFIG; 02076 goto out; 02077 } 02078 02079 phy->polarity_correction = true; 02080 02081 ret_val = e1000e_check_polarity_igp(hw); 02082 if (ret_val) 02083 goto out; 02084 02085 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); 02086 if (ret_val) 02087 goto out; 02088 02089 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 02090 02091 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 02092 IGP01E1000_PSSR_SPEED_1000MBPS) { 02093 #if 0 02094 ret_val = phy->ops.get_cable_length(hw); 02095 #endif 02096 ret_val = -E1000_ERR_CONFIG; 02097 if (ret_val) 02098 goto out; 02099 #if 0 02100 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); 02101 if (ret_val) 02102 goto out; 02103 02104 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 02105 ? e1000_1000t_rx_status_ok 02106 : e1000_1000t_rx_status_not_ok; 02107 02108 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 02109 ? e1000_1000t_rx_status_ok 02110 : e1000_1000t_rx_status_not_ok; 02111 #endif 02112 } else { 02113 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 02114 phy->local_rx = e1000_1000t_rx_status_undefined; 02115 phy->remote_rx = e1000_1000t_rx_status_undefined; 02116 } 02117 out: 02118 return ret_val; 02119 }
e1000e_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore then reads the PHY register at offset and stores the retrieved information in data. Release the acquired semaphore before exiting.
Definition at line 384 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_82571(), and e1000e_init_phy_params_ich8lan().
00385 { 00386 return __e1000e_read_phy_reg_igp(hw, offset, data, false); 00387 }
e1000e_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure
Verify the reset block is not blocking us from resetting. Acquire semaphore (if necessary) and read/set/write the device control reset bit in the PHY. Wait the appropriate delay time for the device to reset and release the semaphore (if necessary).
Definition at line 2160 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_80003es2lan(), e1000e_init_phy_params_82571(), and e1000e_phy_hw_reset_ich8lan().
02161 { 02162 struct e1000_phy_info *phy = &hw->phy; 02163 s32 ret_val = E1000_SUCCESS; 02164 u32 ctrl; 02165 02166 ret_val = e1000e_check_reset_block(hw); 02167 if (ret_val) { 02168 ret_val = E1000_SUCCESS; 02169 goto out; 02170 } 02171 02172 ret_val = phy->ops.acquire(hw); 02173 if (ret_val) 02174 goto out; 02175 02176 ctrl = er32(CTRL); 02177 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); 02178 e1e_flush(); 02179 02180 udelay(phy->reset_delay_us); 02181 02182 ew32(CTRL, ctrl); 02183 e1e_flush(); 02184 02185 udelay(150); 02186 02187 phy->ops.release(hw); 02188 02189 ret_val = phy->ops.get_cfg_done(hw); 02190 02191 out: 02192 return ret_val; 02193 }
e1000e_set_d3_lplu_state - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu
Success returns 0, Failure returns 1
The low power link up (lplu) state is set to the power management level D3 and SmartSpeed is disabled when active is true, else clear lplu for D3 and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU is used during Dx states where the power conservation is most important. During driver activity, SmartSpeed should be enabled so performance is maintained.
Definition at line 1550 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_80003es2lan(), and e1000e_init_phy_params_82571().
01551 { 01552 struct e1000_phy_info *phy = &hw->phy; 01553 s32 ret_val = E1000_SUCCESS; 01554 u16 data; 01555 01556 if (!(hw->phy.ops.read_reg)) 01557 goto out; 01558 01559 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); 01560 if (ret_val) 01561 goto out; 01562 01563 if (!active) { 01564 data &= ~IGP02E1000_PM_D3_LPLU; 01565 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, 01566 data); 01567 if (ret_val) 01568 goto out; 01569 /* 01570 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 01571 * during Dx states where the power conservation is most 01572 * important. During driver activity we should enable 01573 * SmartSpeed, so performance is maintained. 01574 */ 01575 if (phy->smart_speed == e1000_smart_speed_on) { 01576 ret_val = e1e_rphy(hw, 01577 IGP01E1000_PHY_PORT_CONFIG, 01578 &data); 01579 if (ret_val) 01580 goto out; 01581 01582 data |= IGP01E1000_PSCFR_SMART_SPEED; 01583 ret_val = e1e_wphy(hw, 01584 IGP01E1000_PHY_PORT_CONFIG, 01585 data); 01586 if (ret_val) 01587 goto out; 01588 } else if (phy->smart_speed == e1000_smart_speed_off) { 01589 ret_val = e1e_rphy(hw, 01590 IGP01E1000_PHY_PORT_CONFIG, 01591 &data); 01592 if (ret_val) 01593 goto out; 01594 01595 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01596 ret_val = e1e_wphy(hw, 01597 IGP01E1000_PHY_PORT_CONFIG, 01598 data); 01599 if (ret_val) 01600 goto out; 01601 } 01602 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 01603 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 01604 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 01605 data |= IGP02E1000_PM_D3_LPLU; 01606 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, 01607 data); 01608 if (ret_val) 01609 goto out; 01610 01611 /* When LPLU is enabled, we should disable SmartSpeed */ 01612 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, 01613 &data); 01614 if (ret_val) 01615 goto out; 01616 01617 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01618 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, 01619 data); 01620 } 01621 01622 out: 01623 return ret_val; 01624 }
e1000e_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 455 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_82571(), and e1000e_init_phy_params_ich8lan().
00456 { 00457 return __e1000e_write_phy_reg_igp(hw, offset, data, false); 00458 }
e1000e_phy_sw_reset - PHY software reset : pointer to the HW structure
Does a software reset of the PHY by reading the PHY control register and setting/write the control register reset bit to the PHY.
Definition at line 2128 of file e1000e_phy.c.
Referenced by e1000e_hv_phy_workarounds_ich8lan(), e1000e_init_phy_params_80003es2lan(), e1000e_init_phy_params_82571(), e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
02129 { 02130 s32 ret_val = E1000_SUCCESS; 02131 u16 phy_ctrl; 02132 02133 if (!(hw->phy.ops.read_reg)) 02134 goto out; 02135 02136 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); 02137 if (ret_val) 02138 goto out; 02139 02140 phy_ctrl |= MII_CR_RESET; 02141 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); 02142 if (ret_val) 02143 goto out; 02144 02145 udelay(1); 02146 02147 out: 02148 return ret_val; 02149 }
Referenced by e1000e_get_cfg_done_ich8lan(), and e1000e_init_phy_params_82571().
e1000e_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure
Valid for only copper links. Read the PHY status register (sticky read) to verify that link is up. Read the PHY special control register to determine the polarity and 10base-T extended distance. Read the PHY special status register to determine MDI/MDIx and current speed. If speed is 1000, then determine cable length, local and remote receiver.
Definition at line 1983 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_80003es2lan(), and e1000e_init_phy_params_82571().
01984 { 01985 struct e1000_phy_info *phy = &hw->phy; 01986 s32 ret_val; 01987 u16 phy_data; 01988 bool link; 01989 01990 if (phy->media_type != e1000_media_type_copper) { 01991 e_dbg("Phy info is only valid for copper media\n"); 01992 ret_val = -E1000_ERR_CONFIG; 01993 goto out; 01994 } 01995 01996 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 01997 if (ret_val) 01998 goto out; 01999 02000 if (!link) { 02001 e_dbg("Phy info is only valid if link is up\n"); 02002 ret_val = -E1000_ERR_CONFIG; 02003 goto out; 02004 } 02005 02006 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 02007 if (ret_val) 02008 goto out; 02009 02010 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 02011 ? true : false; 02012 02013 ret_val = e1000e_check_polarity_m88(hw); 02014 if (ret_val) 02015 goto out; 02016 02017 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 02018 if (ret_val) 02019 goto out; 02020 02021 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 02022 02023 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 02024 #if 0 02025 ret_val = e1000e_get_cable_length(hw); 02026 #endif 02027 ret_val = -E1000_ERR_CONFIG; 02028 if (ret_val) 02029 goto out; 02030 #if 0 02031 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); 02032 if (ret_val) 02033 goto out; 02034 02035 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 02036 ? e1000_1000t_rx_status_ok 02037 : e1000_1000t_rx_status_not_ok; 02038 02039 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 02040 ? e1000_1000t_rx_status_ok 02041 : e1000_1000t_rx_status_not_ok; 02042 #endif 02043 } else { 02044 /* Set values to "undefined" */ 02045 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 02046 phy->local_rx = e1000_1000t_rx_status_undefined; 02047 phy->remote_rx = e1000_1000t_rx_status_undefined; 02048 } 02049 out: 02050 return ret_val; 02051 }
e1000e_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 282 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_82571().
00283 { 00284 s32 ret_val = E1000_SUCCESS; 00285 00286 if (!(hw->phy.ops.acquire)) 00287 goto out; 00288 00289 ret_val = hw->phy.ops.acquire(hw); 00290 if (ret_val) 00291 goto out; 00292 00293 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00294 data); 00295 00296 hw->phy.ops.release(hw); 00297 00298 out: 00299 return ret_val; 00300 }
e1000e_write_phy_reg_m88 - Write m88 PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 311 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_82571().
00312 { 00313 s32 ret_val = E1000_SUCCESS; 00314 00315 if (!(hw->phy.ops.acquire)) 00316 goto out; 00317 00318 ret_val = hw->phy.ops.acquire(hw); 00319 if (ret_val) 00320 goto out; 00321 00322 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00323 data); 00324 00325 hw->phy.ops.release(hw); 00326 00327 out: 00328 return ret_val; 00329 }
| enum e1000_phy_type e1000e_get_phy_type_from_id | ( | u32 | phy_id | ) |
e1000e_get_phy_type_from_id - Get PHY type from id : phy_id read from the phy
Returns the phy type from the id.
Definition at line 2300 of file e1000e_phy.c.
Referenced by e1000e_determine_phy_address(), e1000e_init_phy_params_ich8lan(), and e1000e_init_phy_params_pchlan().
02301 { 02302 enum e1000_phy_type phy_type = e1000_phy_unknown; 02303 02304 switch (phy_id) { 02305 case M88E1000_I_PHY_ID: 02306 case M88E1000_E_PHY_ID: 02307 case M88E1111_I_PHY_ID: 02308 case M88E1011_I_PHY_ID: 02309 phy_type = e1000_phy_m88; 02310 break; 02311 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 02312 phy_type = e1000_phy_igp_2; 02313 break; 02314 case GG82563_E_PHY_ID: 02315 phy_type = e1000_phy_gg82563; 02316 break; 02317 case IGP03E1000_E_PHY_ID: 02318 phy_type = e1000_phy_igp_3; 02319 break; 02320 case IFE_E_PHY_ID: 02321 case IFE_PLUS_E_PHY_ID: 02322 case IFE_C_E_PHY_ID: 02323 phy_type = e1000_phy_ife; 02324 break; 02325 case BME1000_E_PHY_ID: 02326 case BME1000_E_PHY_ID_R2: 02327 phy_type = e1000_phy_bm; 02328 break; 02329 case I82578_E_PHY_ID: 02330 phy_type = e1000_phy_82578; 02331 break; 02332 case I82577_E_PHY_ID: 02333 phy_type = e1000_phy_82577; 02334 break; 02335 default: 02336 phy_type = e1000_phy_unknown; 02337 break; 02338 } 02339 return phy_type; 02340 }
e1000e_determine_phy_address - Determines PHY address.
: pointer to the HW structure
This uses a trial and error method to loop through possible PHY addresses. It tests each by reading the PHY ID registers and checking for a match.
Definition at line 2350 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_ich8lan().
02351 { 02352 s32 ret_val = -E1000_ERR_PHY_TYPE; 02353 u32 phy_addr = 0; 02354 u32 i; 02355 enum e1000_phy_type phy_type = e1000_phy_unknown; 02356 02357 hw->phy.id = phy_type; 02358 02359 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 02360 hw->phy.addr = phy_addr; 02361 i = 0; 02362 02363 do { 02364 e1000e_get_phy_id(hw); 02365 phy_type = e1000e_get_phy_type_from_id(hw->phy.id); 02366 02367 /* 02368 * If phy_type is valid, break - we found our 02369 * PHY address 02370 */ 02371 if (phy_type != e1000_phy_unknown) { 02372 ret_val = E1000_SUCCESS; 02373 goto out; 02374 } 02375 msleep(1); 02376 i++; 02377 } while (i < 10); 02378 } 02379 02380 out: 02381 return ret_val; 02382 }
e1000e_write_phy_reg_bm - Write BM PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 2409 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_ich8lan().
02410 { 02411 s32 ret_val; 02412 u32 page_select = 0; 02413 u32 page = offset >> IGP_PAGE_SHIFT; 02414 u32 page_shift = 0; 02415 02416 ret_val = hw->phy.ops.acquire(hw); 02417 if (ret_val) 02418 return ret_val; 02419 02420 /* Page 800 works differently than the rest so it has its own func */ 02421 if (page == BM_WUC_PAGE) { 02422 ret_val = e1000e_access_phy_wakeup_reg_bm(hw, offset, &data, 02423 false); 02424 goto out; 02425 } 02426 02427 hw->phy.addr = e1000e_get_phy_addr_for_bm_page(page, offset); 02428 02429 if (offset > MAX_PHY_MULTI_PAGE_REG) { 02430 /* 02431 * Page select is register 31 for phy address 1 and 22 for 02432 * phy address 2 and 3. Page select is shifted only for 02433 * phy address 1. 02434 */ 02435 if (hw->phy.addr == 1) { 02436 page_shift = IGP_PAGE_SHIFT; 02437 page_select = IGP01E1000_PHY_PAGE_SELECT; 02438 } else { 02439 page_shift = 0; 02440 page_select = BM_PHY_PAGE_SELECT; 02441 } 02442 02443 /* Page is shifted left, PHY expects (page x 32) */ 02444 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 02445 (page << page_shift)); 02446 if (ret_val) 02447 goto out; 02448 } 02449 02450 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 02451 data); 02452 02453 out: 02454 hw->phy.ops.release(hw); 02455 return ret_val; 02456 }
e1000e_read_phy_reg_bm - Read BM PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 2468 of file e1000e_phy.c.
Referenced by e1000e_init_phy_params_ich8lan().
02469 { 02470 s32 ret_val; 02471 u32 page_select = 0; 02472 u32 page = offset >> IGP_PAGE_SHIFT; 02473 u32 page_shift = 0; 02474 02475 ret_val = hw->phy.ops.acquire(hw); 02476 if (ret_val) 02477 return ret_val; 02478 02479 /* Page 800 works differently than the rest so it has its own func */ 02480 if (page == BM_WUC_PAGE) { 02481 ret_val = e1000e_access_phy_wakeup_reg_bm(hw, offset, data, 02482 true); 02483 goto out; 02484 } 02485 02486 hw->phy.addr = e1000e_get_phy_addr_for_bm_page(page, offset); 02487 02488 if (offset > MAX_PHY_MULTI_PAGE_REG) { 02489 /* 02490 * Page select is register 31 for phy address 1 and 22 for 02491 * phy address 2 and 3. Page select is shifted only for 02492 * phy address 1. 02493 */ 02494 if (hw->phy.addr == 1) { 02495 page_shift = IGP_PAGE_SHIFT; 02496 page_select = IGP01E1000_PHY_PAGE_SELECT; 02497 } else { 02498 page_shift = 0; 02499 page_select = BM_PHY_PAGE_SELECT; 02500 } 02501 02502 /* Page is shifted left, PHY expects (page x 32) */ 02503 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, 02504 (page << page_shift)); 02505 if (ret_val) 02506 goto out; 02507 } 02508 02509 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 02510 data); 02511 out: 02512 hw->phy.ops.release(hw); 02513 return ret_val; 02514 }
e1000e_write_kmrn_reg - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore then writes the data to the PHY register at the offset using the kumeran interface. Release the acquired semaphore before exiting.
Definition at line 594 of file e1000e_phy.c.
Referenced by e1000e_gig_downshift_workaround_ich8lan(), and e1000e_setup_copper_link_ich8lan().
00595 { 00596 return __e1000e_write_kmrn_reg(hw, offset, data, false); 00597 }
e1000e_read_kmrn_reg - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore then reads the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Release the acquired semaphore before exiting.
Definition at line 526 of file e1000e_phy.c.
Referenced by e1000e_gig_downshift_workaround_ich8lan(), and e1000e_setup_copper_link_ich8lan().
00527 { 00528 return __e1000e_read_kmrn_reg(hw, offset, data, false); 00529 }
| s32 e1000e_phy_has_link_generic | ( | struct e1000_hw * | hw, | |
| u32 | iterations, | |||
| u32 | usec_interval, | |||
| bool * | success | |||
| ) |
e1000e_phy_has_link_generic - Polls PHY for link : pointer to the HW structure : number of times to poll for link : delay between polling attempts : pointer to whether polling was successful or not
Polls the PHY status register for link, 'iterations' number of times.
Definition at line 1818 of file e1000e_phy.c.
Referenced by e1000e_check_for_copper_link(), e1000e_check_for_copper_link_ich8lan(), e1000e_get_phy_info_82577(), e1000e_get_phy_info_ife_ich8lan(), e1000e_get_phy_info_igp(), e1000e_get_phy_info_m88(), e1000e_kmrn_lock_loss_workaround_ich8lan(), and e1000e_setup_copper_link().
01820 { 01821 s32 ret_val = E1000_SUCCESS; 01822 u16 i, phy_status; 01823 01824 if (!(hw->phy.ops.read_reg)) 01825 return E1000_SUCCESS; 01826 01827 for (i = 0; i < iterations; i++) { 01828 /* 01829 * Some PHYs require the PHY_STATUS register to be read 01830 * twice due to the link bit being sticky. No harm doing 01831 * it across the board. 01832 */ 01833 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 01834 if (ret_val) { 01835 /* 01836 * If the first read fails, another entity may have 01837 * ownership of the resources, wait and try again to 01838 * see if they have relinquished the resources yet. 01839 */ 01840 udelay(usec_interval); 01841 } 01842 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); 01843 if (ret_val) 01844 break; 01845 if (phy_status & MII_SR_LINK_STATUS) 01846 break; 01847 if (usec_interval >= 1000) 01848 mdelay(usec_interval/1000); 01849 else 01850 udelay(usec_interval); 01851 } 01852 01853 *success = (i < iterations) ? true : false; 01854 01855 return ret_val; 01856 }
e1000e_phy_reset_dsp - Reset PHY DSP : pointer to the HW structure
Reset the digital signal processor.
Definition at line 150 of file e1000e_phy.c.
00151 { 00152 s32 ret_val = E1000_SUCCESS; 00153 00154 if (!(hw->phy.ops.write_reg)) 00155 goto out; 00156 00157 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 00158 if (ret_val) 00159 goto out; 00160 00161 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); 00162 00163 out: 00164 return ret_val; 00165 }
e1000e_read_phy_reg_mdic - Read MDI control register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the MDI control register in the PHY at offset and stores the information read to data.
Definition at line 176 of file e1000e_phy.c.
Referenced by __e1000e_read_phy_reg_hv(), __e1000e_read_phy_reg_igp(), e1000e_access_phy_debug_regs_hv(), e1000e_access_phy_wakeup_reg_bm(), e1000e_read_phy_reg_bm(), e1000e_read_phy_reg_bm2(), e1000e_read_phy_reg_gg82563_80003es2lan(), e1000e_read_phy_reg_m88(), e1000e_set_mdio_slow_mode_hv(), and e1000e_write_phy_reg_gg82563_80003es2lan().
00177 { 00178 struct e1000_phy_info *phy = &hw->phy; 00179 u32 i, mdic = 0; 00180 s32 ret_val = E1000_SUCCESS; 00181 00182 /* 00183 * Set up Op-code, Phy Address, and register offset in the MDI 00184 * Control register. The MAC will take care of interfacing with the 00185 * PHY to retrieve the desired data. 00186 */ 00187 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 00188 (phy->addr << E1000_MDIC_PHY_SHIFT) | 00189 (E1000_MDIC_OP_READ)); 00190 00191 ew32(MDIC, mdic); 00192 00193 /* 00194 * Poll the ready bit to see if the MDI read completed 00195 * Increasing the time out as testing showed failures with 00196 * the lower time out 00197 */ 00198 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 00199 udelay(50); 00200 mdic = er32(MDIC); 00201 if (mdic & E1000_MDIC_READY) 00202 break; 00203 } 00204 if (!(mdic & E1000_MDIC_READY)) { 00205 e_dbg("MDI Read did not complete\n"); 00206 ret_val = -E1000_ERR_PHY; 00207 goto out; 00208 } 00209 if (mdic & E1000_MDIC_ERROR) { 00210 e_dbg("MDI Error\n"); 00211 ret_val = -E1000_ERR_PHY; 00212 goto out; 00213 } 00214 *data = (u16) mdic; 00215 00216 out: 00217 return ret_val; 00218 }
e1000e_write_phy_reg_mdic - Write MDI control register : pointer to the HW structure : register offset to write to : data to write to register at offset
Writes data to MDI control register in the PHY at offset.
Definition at line 228 of file e1000e_phy.c.
Referenced by __e1000e_read_phy_reg_hv(), __e1000e_read_phy_reg_igp(), __e1000e_write_phy_reg_hv(), __e1000e_write_phy_reg_igp(), e1000e_access_phy_debug_regs_hv(), e1000e_access_phy_wakeup_reg_bm(), e1000e_hv_phy_workarounds_ich8lan(), e1000e_read_phy_reg_bm(), e1000e_read_phy_reg_bm2(), e1000e_read_phy_reg_gg82563_80003es2lan(), e1000e_set_mdio_slow_mode_hv(), e1000e_write_phy_reg_bm(), e1000e_write_phy_reg_bm2(), e1000e_write_phy_reg_gg82563_80003es2lan(), and e1000e_write_phy_reg_m88().
00229 { 00230 struct e1000_phy_info *phy = &hw->phy; 00231 u32 i, mdic = 0; 00232 s32 ret_val = E1000_SUCCESS; 00233 00234 /* 00235 * Set up Op-code, Phy Address, and register offset in the MDI 00236 * Control register. The MAC will take care of interfacing with the 00237 * PHY to retrieve the desired data. 00238 */ 00239 mdic = (((u32)data) | 00240 (offset << E1000_MDIC_REG_SHIFT) | 00241 (phy->addr << E1000_MDIC_PHY_SHIFT) | 00242 (E1000_MDIC_OP_WRITE)); 00243 00244 ew32(MDIC, mdic); 00245 00246 /* 00247 * Poll the ready bit to see if the MDI read completed 00248 * Increasing the time out as testing showed failures with 00249 * the lower time out 00250 */ 00251 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 00252 udelay(50); 00253 mdic = er32(MDIC); 00254 if (mdic & E1000_MDIC_READY) 00255 break; 00256 } 00257 if (!(mdic & E1000_MDIC_READY)) { 00258 e_dbg("MDI Write did not complete\n"); 00259 ret_val = -E1000_ERR_PHY; 00260 goto out; 00261 } 00262 if (mdic & E1000_MDIC_ERROR) { 00263 e_dbg("MDI Error\n"); 00264 ret_val = -E1000_ERR_PHY; 00265 goto out; 00266 } 00267 00268 out: 00269 return ret_val; 00270 }
e1000e_check_downshift - Checks whether a downshift in speed occurred : pointer to the HW structure
Success returns 0, Failure returns 1
A downshift is detected by querying the PHY link health.
Definition at line 1634 of file e1000e_phy.c.
Referenced by e1000e_check_for_copper_link(), and e1000e_check_for_copper_link_ich8lan().
01635 { 01636 struct e1000_phy_info *phy = &hw->phy; 01637 s32 ret_val; 01638 u16 phy_data, offset, mask; 01639 01640 switch (phy->type) { 01641 case e1000_phy_m88: 01642 case e1000_phy_gg82563: 01643 case e1000_phy_bm: 01644 case e1000_phy_82578: 01645 offset = M88E1000_PHY_SPEC_STATUS; 01646 mask = M88E1000_PSSR_DOWNSHIFT; 01647 break; 01648 case e1000_phy_igp_2: 01649 case e1000_phy_igp: 01650 case e1000_phy_igp_3: 01651 offset = IGP01E1000_PHY_LINK_HEALTH; 01652 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 01653 break; 01654 default: 01655 /* speed downshift not supported */ 01656 phy->speed_downgraded = false; 01657 ret_val = E1000_SUCCESS; 01658 goto out; 01659 } 01660 01661 ret_val = e1e_rphy(hw, offset, &phy_data); 01662 01663 if (!ret_val) 01664 phy->speed_downgraded = (phy_data & mask) ? true : false; 01665 01666 out: 01667 return ret_val; 01668 }
Definition at line 389 of file e1000e.h.
References e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::reset.
Referenced by e1000e_copper_link_setup_igp(), e1000e_kmrn_lock_loss_workaround_ich8lan(), and e1000e_probe().
00390 { 00391 if (hw->phy.ops.reset) 00392 return hw->phy.ops.reset(hw); 00393 00394 return 0; 00395 }
Definition at line 397 of file e1000e.h.
References e1000_phy_operations::check_reset_block, e1000_phy_info::ops, and e1000_hw::phy.
Referenced by e1000e_oem_bits_config_ich8lan(), e1000e_phy_hw_reset_generic(), e1000e_power_down_phy_copper_80003es2lan(), e1000e_power_down_phy_copper_82571(), e1000e_power_down_phy_copper_ich8lan(), e1000e_probe(), e1000e_reset_hw_ich8lan(), e1000e_setup_link(), and e1000e_setup_link_ich8lan().
00398 { 00399 if (hw->phy.ops.check_reset_block) 00400 return hw->phy.ops.check_reset_block(hw); 00401 00402 return 0; 00403 }
Definition at line 405 of file e1000e.h.
References e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::read_reg.
Referenced by e1000e_cfg_kmrn_1000_80003es2lan(), e1000e_cfg_kmrn_10_100_80003es2lan(), e1000e_check_downshift(), e1000e_check_polarity_82577(), e1000e_check_polarity_ife(), e1000e_check_polarity_igp(), e1000e_check_polarity_m88(), e1000e_clear_hw_cntrs_ich8lan(), e1000e_config_fc_after_link_up(), e1000e_copper_link_autoneg(), e1000e_copper_link_setup_82577(), e1000e_copper_link_setup_gg82563_80003es2lan(), e1000e_copper_link_setup_igp(), e1000e_copper_link_setup_m88(), e1000e_get_phy_id(), e1000e_get_phy_id_82571(), e1000e_get_phy_info_82577(), e1000e_get_phy_info_ife_ich8lan(), e1000e_get_phy_info_igp(), e1000e_get_phy_info_m88(), e1000e_igp3_phy_powerdown_workaround_ich8lan(), e1000e_init_hw_ich8lan(), e1000e_kmrn_lock_loss_workaround_ich8lan(), e1000e_link_stall_workaround_hv(), e1000e_phy_has_link_generic(), e1000e_phy_hw_reset_ich8lan(), e1000e_phy_setup_autoneg(), e1000e_phy_sw_reset(), e1000e_power_down_phy_copper(), e1000e_power_up_phy_copper(), e1000e_reset(), e1000e_reset_hw_ich8lan(), e1000e_set_d0_lplu_state_82571(), e1000e_set_d0_lplu_state_ich8lan(), e1000e_set_d3_lplu_state(), e1000e_set_d3_lplu_state_ich8lan(), e1000e_set_lplu_state_pchlan(), e1000e_setup_copper_link_ich8lan(), and e1000e_wait_autoneg().
00406 { 00407 if (hw->phy.ops.read_reg) 00408 return hw->phy.ops.read_reg(hw, offset, data); 00409 00410 return 0; 00411 }
Definition at line 413 of file e1000e.h.
References e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::write_reg.
Referenced by e1000e_cfg_kmrn_1000_80003es2lan(), e1000e_cfg_kmrn_10_100_80003es2lan(), e1000e_cleanup_led_ich8lan(), e1000e_cleanup_led_pchlan(), e1000e_copper_link_autoneg(), e1000e_copper_link_setup_82577(), e1000e_copper_link_setup_gg82563_80003es2lan(), e1000e_copper_link_setup_igp(), e1000e_copper_link_setup_m88(), e1000e_hv_phy_workarounds_ich8lan(), e1000e_igp3_phy_powerdown_workaround_ich8lan(), e1000e_led_off_ich8lan(), e1000e_led_off_pchlan(), e1000e_led_on_ich8lan(), e1000e_led_on_pchlan(), e1000e_link_stall_workaround_hv(), e1000e_phy_init_script_igp3(), e1000e_phy_reset_dsp(), e1000e_phy_setup_autoneg(), e1000e_phy_sw_reset(), e1000e_power_down_phy_copper(), e1000e_power_up_phy_copper(), e1000e_reset(), e1000e_set_d0_lplu_state_82571(), e1000e_set_d0_lplu_state_ich8lan(), e1000e_set_d3_lplu_state(), e1000e_set_d3_lplu_state_ich8lan(), e1000e_set_lplu_state_pchlan(), e1000e_setup_copper_link_ich8lan(), e1000e_setup_led_pchlan(), and e1000e_setup_link_ich8lan().
00414 { 00415 if (hw->phy.ops.write_reg) 00416 return hw->phy.ops.write_reg(hw, offset, data); 00417 00418 return 0; 00419 }
e1000e_acquire_nvm - Generic request for access to EEPROM : pointer to the HW structure
Set the EEPROM access request bit and wait for EEPROM access grant bit. Return successful if access grant bit set, else clear the request for EEPROM access and return -E1000_ERR_NVM (-1).
Definition at line 196 of file e1000e_nvm.c.
Referenced by e1000e_acquire_nvm_80003es2lan(), and e1000e_acquire_nvm_82571().
00197 { 00198 u32 eecd = er32(EECD); 00199 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 00200 s32 ret_val = E1000_SUCCESS; 00201 00202 ew32(EECD, eecd | E1000_EECD_REQ); 00203 eecd = er32(EECD); 00204 while (timeout) { 00205 if (eecd & E1000_EECD_GNT) 00206 break; 00207 udelay(5); 00208 eecd = er32(EECD); 00209 timeout--; 00210 } 00211 00212 if (!timeout) { 00213 eecd &= ~E1000_EECD_REQ; 00214 ew32(EECD, eecd); 00215 e_dbg("Could not acquire NVM grant\n"); 00216 ret_val = -E1000_ERR_NVM; 00217 } 00218 00219 return ret_val; 00220 }
e1000e_write_nvm_spi - Write to EEPROM using SPI : pointer to the HW structure : offset within the EEPROM to be written to : number of words to write : 16 bit word(s) to be written to the EEPROM
Writes data to EEPROM at offset using SPI interface.
If e1000e_update_nvm_checksum is not called after this function , the EEPROM will most likely contain an invalid checksum.
Definition at line 386 of file e1000e_nvm.c.
Referenced by e1000e_write_nvm_80003es2lan(), and e1000e_write_nvm_82571().
00387 { 00388 struct e1000_nvm_info *nvm = &hw->nvm; 00389 s32 ret_val; 00390 u16 widx = 0; 00391 00392 /* 00393 * A check for invalid values: offset too large, too many words, 00394 * and not enough words. 00395 */ 00396 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 00397 (words == 0)) { 00398 e_dbg("nvm parameter(s) out of bounds\n"); 00399 ret_val = -E1000_ERR_NVM; 00400 goto out; 00401 } 00402 00403 ret_val = nvm->ops.acquire(hw); 00404 if (ret_val) 00405 goto out; 00406 00407 while (widx < words) { 00408 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 00409 00410 ret_val = e1000e_ready_nvm_eeprom(hw); 00411 if (ret_val) 00412 goto release; 00413 00414 e1000e_standby_nvm(hw); 00415 00416 /* Send the WRITE ENABLE command (8 bit opcode) */ 00417 e1000e_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 00418 nvm->opcode_bits); 00419 00420 e1000e_standby_nvm(hw); 00421 00422 /* 00423 * Some SPI eeproms use the 8th address bit embedded in the 00424 * opcode 00425 */ 00426 if ((nvm->address_bits == 8) && (offset >= 128)) 00427 write_opcode |= NVM_A8_OPCODE_SPI; 00428 00429 /* Send the Write command (8-bit opcode + addr) */ 00430 e1000e_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 00431 e1000e_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 00432 nvm->address_bits); 00433 00434 /* Loop to allow for up to whole page write of eeprom */ 00435 while (widx < words) { 00436 u16 word_out = data[widx]; 00437 word_out = (word_out >> 8) | (word_out << 8); 00438 e1000e_shift_out_eec_bits(hw, word_out, 16); 00439 widx++; 00440 00441 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 00442 e1000e_standby_nvm(hw); 00443 break; 00444 } 00445 } 00446 } 00447 00448 msleep(10); 00449 release: 00450 nvm->ops.release(hw); 00451 00452 out: 00453 return ret_val; 00454 }
e1000e_update_nvm_checksum_generic - Update EEPROM checksum : pointer to the HW structure
Updates the EEPROM checksum by reading/adding each word of the EEPROM up to the checksum. Then calculates the EEPROM checksum and writes the value to the EEPROM.
Definition at line 556 of file e1000e_nvm.c.
Referenced by e1000e_init_nvm_params_80003es2lan(), e1000e_update_nvm_checksum_82571(), and e1000e_update_nvm_checksum_ich8lan().
00557 { 00558 s32 ret_val; 00559 u16 checksum = 0; 00560 u16 i, nvm_data; 00561 00562 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 00563 ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data); 00564 if (ret_val) { 00565 e_dbg("NVM Read Error while updating checksum.\n"); 00566 goto out; 00567 } 00568 checksum += nvm_data; 00569 } 00570 checksum = (u16) NVM_SUM - checksum; 00571 ret_val = e1000e_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum); 00572 if (ret_val) 00573 e_dbg("NVM Write Error while updating checksum.\n"); 00574 00575 out: 00576 return ret_val; 00577 }
e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion : pointer to the HW structure : EEPROM flag for polling
Polls the EEPROM status bit for either read or write completion based upon the value of 'ee_reg'.
Definition at line 165 of file e1000e_nvm.c.
Referenced by e1000e_read_nvm_eerd(), and e1000e_write_nvm_eewr_82571().
00166 { 00167 u32 attempts = 100000; 00168 u32 i, reg = 0; 00169 s32 ret_val = -E1000_ERR_NVM; 00170 00171 for (i = 0; i < attempts; i++) { 00172 if (ee_reg == E1000_NVM_POLL_READ) 00173 reg = er32(EERD); 00174 else 00175 reg = er32(EEWR); 00176 00177 if (reg & E1000_NVM_RW_REG_DONE) { 00178 ret_val = E1000_SUCCESS; 00179 break; 00180 } 00181 00182 udelay(5); 00183 } 00184 00185 return ret_val; 00186 }
e1000e_read_nvm_eerd - Reads EEPROM using EERD register : pointer to the HW structure : offset of word in the EEPROM to read : number of words to read : word read from the EEPROM
Reads a 16 bit word from the EEPROM using the EERD register.
Definition at line 340 of file e1000e_nvm.c.
Referenced by e1000e_init_nvm_params_80003es2lan(), and e1000e_init_nvm_params_82571().
00341 { 00342 struct e1000_nvm_info *nvm = &hw->nvm; 00343 u32 i, eerd = 0; 00344 s32 ret_val = E1000_SUCCESS; 00345 00346 /* 00347 * A check for invalid values: offset too large, too many words, 00348 * too many words for the offset, and not enough words. 00349 */ 00350 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 00351 (words == 0)) { 00352 e_dbg("nvm parameter(s) out of bounds\n"); 00353 ret_val = -E1000_ERR_NVM; 00354 goto out; 00355 } 00356 00357 for (i = 0; i < words; i++) { 00358 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 00359 E1000_NVM_RW_REG_START; 00360 00361 ew32(EERD, eerd); 00362 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 00363 if (ret_val) 00364 break; 00365 00366 data[i] = (er32(EERD) >> 00367 E1000_NVM_RW_REG_DATA); 00368 } 00369 00370 out: 00371 return ret_val; 00372 }
e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum : pointer to the HW structure
Calculates the EEPROM checksum by reading/adding each word of the EEPROM and then verifies that the sum of the EEPROM is equal to 0xBABA.
Definition at line 523 of file e1000e_nvm.c.
Referenced by e1000e_init_nvm_params_80003es2lan(), e1000e_validate_nvm_checksum_82571(), and e1000e_validate_nvm_checksum_ich8lan().
00524 { 00525 s32 ret_val = E1000_SUCCESS; 00526 u16 checksum = 0; 00527 u16 i, nvm_data; 00528 00529 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 00530 ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data); 00531 if (ret_val) { 00532 e_dbg("NVM Read Error\n"); 00533 goto out; 00534 } 00535 checksum += nvm_data; 00536 } 00537 00538 if (checksum != (u16) NVM_SUM) { 00539 e_dbg("NVM Checksum Invalid\n"); 00540 ret_val = -E1000_ERR_NVM; 00541 goto out; 00542 } 00543 00544 out: 00545 return ret_val; 00546 }
| void e1000e_release_nvm | ( | struct e1000_hw * | hw | ) |
e1000e_release_nvm - Release exclusive access to EEPROM : pointer to the HW structure
Stop any current commands to the EEPROM and clear the EEPROM request bit.
Definition at line 270 of file e1000e_nvm.c.
Referenced by e1000e_release_nvm_80003es2lan(), and e1000e_release_nvm_82571().
00271 { 00272 u32 eecd; 00273 00274 e1000e_stop_nvm(hw); 00275 00276 eecd = er32(EECD); 00277 eecd &= ~E1000_EECD_REQ; 00278 ew32(EECD, eecd); 00279 }
Definition at line 439 of file e1000e.h.
References e1000e_read_mac_addr_generic(), e1000_hw::mac, e1000_mac_info::ops, and e1000_mac_operations::read_mac_addr.
Referenced by e1000e_probe().
00440 { 00441 if (hw->mac.ops.read_mac_addr) 00442 return hw->mac.ops.read_mac_addr(hw); 00443 00444 return e1000e_read_mac_addr_generic(hw); 00445 }
Definition at line 447 of file e1000e.h.
References e1000_hw::nvm, e1000_nvm_info::ops, and e1000_nvm_operations::validate.
Referenced by e1000e_probe().
Definition at line 452 of file e1000e.h.
References e1000_hw::nvm, e1000_nvm_info::ops, and e1000_nvm_operations::update.
Referenced by e1000e_fix_nvm_checksum_82571(), and e1000e_validate_nvm_checksum_ich8lan().
| static s32 e1000e_read_nvm | ( | struct e1000_hw * | hw, | |
| u16 | offset, | |||
| u16 | words, | |||
| u16 * | data | |||
| ) | [inline, static] |
Definition at line 457 of file e1000e.h.
References e1000_hw::nvm, e1000_nvm_info::ops, and e1000_nvm_operations::read.
Referenced by e1000e_check_alt_mac_addr_generic(), e1000e_fix_nvm_checksum_82571(), e1000e_get_variants_82571(), e1000e_read_pba_num(), e1000e_reset_hw_ich8lan(), e1000e_set_default_fc_generic(), e1000e_sw_lcd_config_ich8lan(), e1000e_update_nvm_checksum_generic(), e1000e_valid_led_default(), e1000e_valid_led_default_82571(), e1000e_valid_led_default_ich8lan(), e1000e_validate_nvm_checksum_generic(), and e1000e_validate_nvm_checksum_ich8lan().
| static s32 e1000e_write_nvm | ( | struct e1000_hw * | hw, | |
| u16 | offset, | |||
| u16 | words, | |||
| u16 * | data | |||
| ) | [inline, static] |
Definition at line 462 of file e1000e.h.
References e1000_hw::nvm, e1000_nvm_info::ops, and e1000_nvm_operations::write.
Referenced by e1000e_fix_nvm_checksum_82571(), e1000e_update_nvm_checksum_generic(), and e1000e_validate_nvm_checksum_ich8lan().
Definition at line 467 of file e1000e.h.
References e1000_phy_operations::get_info, e1000_phy_info::ops, and e1000_hw::phy.
Referenced by e1000e_reset().
00468 { 00469 if (hw->phy.ops.get_info) 00470 return hw->phy.ops.get_info(hw); 00471 00472 return 0; 00473 }
Referenced by e1000e_init_hw_82571().
Definition at line 508 of file e1000e.h.
References e1000_hw::flash_address, and readw.
00509 { 00510 return readw(hw->flash_address + reg); 00511 }
Definition at line 513 of file e1000e.h.
References e1000_hw::flash_address, and readl.
00514 { 00515 return readl(hw->flash_address + reg); 00516 }
Definition at line 518 of file e1000e.h.
References e1000_hw::flash_address, and writew.
00519 { 00520 writew(val, hw->flash_address + reg); 00521 }
Definition at line 523 of file e1000e.h.
References e1000_hw::flash_address, and writel.
00524 { 00525 writel(val, hw->flash_address + reg); 00526 }
1.5.7.1