#include "e1000_api.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| void | e1000_init_phy_ops_generic (struct e1000_hw *hw) |
| e1000_init_phy_ops_generic - Initialize PHY function pointers : pointer to the HW structure | |
| s32 | e1000_null_read_reg (struct e1000_hw *hw __unused, u32 offset __unused, u16 *data __unused) |
| e1000_null_read_reg - No-op function, return 0 : pointer to the HW structure | |
| void | e1000_null_phy_generic (struct e1000_hw *hw __unused) |
| e1000_null_phy_generic - No-op function, return void : pointer to the HW structure | |
| s32 | e1000_null_lplu_state (struct e1000_hw *hw __unused, bool active __unused) |
| e1000_null_lplu_state - No-op function, return 0 : pointer to the HW structure | |
| s32 | e1000_null_write_reg (struct e1000_hw *hw __unused, u32 offset __unused, u16 data __unused) |
| e1000_null_write_reg - No-op function, return 0 : pointer to the HW structure | |
| s32 | e1000_check_reset_block_generic (struct e1000_hw *hw) |
| e1000_check_reset_block_generic - Check if PHY reset is blocked : pointer to the HW structure | |
| s32 | e1000_get_phy_id (struct e1000_hw *hw) |
| e1000_get_phy_id - Retrieve the PHY ID and revision : pointer to the HW structure | |
| s32 | e1000_phy_reset_dsp_generic (struct e1000_hw *hw) |
| e1000_phy_reset_dsp_generic - Reset PHY DSP : pointer to the HW structure | |
| s32 | e1000_read_phy_reg_mdic (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000_read_phy_reg_mdic - Read MDI control register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000_write_phy_reg_mdic (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000_write_phy_reg_mdic - Write MDI control register : pointer to the HW structure : register offset to write to : data to write to register at offset | |
| s32 | e1000_read_phy_reg_m88 (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000_write_phy_reg_m88 (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000_write_phy_reg_m88 - Write m88 PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000_read_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000_write_phy_reg_igp (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000_read_kmrn_reg_generic (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000_read_kmrn_reg_generic - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| s32 | e1000_write_kmrn_reg_generic (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000_write_kmrn_reg_generic - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset | |
| s32 | e1000_copper_link_setup_m88 (struct e1000_hw *hw) |
| e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link : pointer to the HW structure | |
| s32 | e1000_copper_link_setup_igp (struct e1000_hw *hw) |
| e1000_copper_link_setup_igp - Setup igp PHY's for copper link : pointer to the HW structure | |
| s32 | e1000_copper_link_autoneg (struct e1000_hw *hw) |
| e1000_copper_link_autoneg - Setup/Enable autoneg for copper link : pointer to the HW structure | |
| s32 | e1000_phy_setup_autoneg (struct e1000_hw *hw) |
| e1000_phy_setup_autoneg - Configure PHY for auto-negotiation : pointer to the HW structure | |
| s32 | e1000_setup_copper_link_generic (struct e1000_hw *hw) |
| e1000_setup_copper_link_generic - Configure copper link settings : pointer to the HW structure | |
| s32 | e1000_set_d3_lplu_state_generic (struct e1000_hw *hw, bool active) |
| e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu | |
| s32 | e1000_check_downshift_generic (struct e1000_hw *hw) |
| e1000_check_downshift_generic - Checks whether a downshift in speed occurred : pointer to the HW structure | |
| s32 | e1000_check_polarity_m88 (struct e1000_hw *hw) |
| e1000_check_polarity_m88 - Checks the polarity. | |
| s32 | e1000_check_polarity_igp (struct e1000_hw *hw) |
| e1000_check_polarity_igp - Checks the polarity. | |
| s32 | e1000_check_polarity_ife (struct e1000_hw *hw) |
| e1000_check_polarity_ife - Check cable polarity for IFE PHY : pointer to the HW structure | |
| s32 | e1000_wait_autoneg_generic (struct e1000_hw *hw) |
| e1000_wait_autoneg_generic - Wait for auto-neg completion : pointer to the HW structure | |
| s32 | e1000_phy_has_link_generic (struct e1000_hw *hw, u32 iterations, u32 usec_interval, bool *success) |
| e1000_phy_has_link_generic - Polls PHY for link : pointer to the HW structure : number of times to poll for link : delay between polling attempts : pointer to whether polling was successful or not | |
| s32 | e1000_get_phy_info_m88 (struct e1000_hw *hw) |
| e1000_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure | |
| s32 | e1000_get_phy_info_igp (struct e1000_hw *hw) |
| e1000_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure | |
| s32 | e1000_phy_sw_reset_generic (struct e1000_hw *hw) |
| e1000_phy_sw_reset_generic - PHY software reset : pointer to the HW structure | |
| s32 | e1000_phy_hw_reset_generic (struct e1000_hw *hw) |
| e1000_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure | |
| s32 | e1000_get_cfg_done_generic (struct e1000_hw *hw __unused) |
| e1000_get_cfg_done_generic - Generic configuration done : pointer to the HW structure | |
| s32 | e1000_phy_init_script_igp3 (struct e1000_hw *hw) |
| e1000_phy_init_script_igp3 - Inits the IGP3 PHY : pointer to the HW structure | |
| enum e1000_phy_type | e1000_get_phy_type_from_id (u32 phy_id) |
| e1000_get_phy_type_from_id - Get PHY type from id : phy_id read from the phy | |
| s32 | e1000_determine_phy_address (struct e1000_hw *hw) |
| e1000_determine_phy_address - Determines PHY address. | |
| void | e1000_power_up_phy_copper (struct e1000_hw *hw) |
| e1000_power_up_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure | |
| void | e1000_power_down_phy_copper (struct e1000_hw *hw) |
| e1000_power_down_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure | |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
| void e1000_init_phy_ops_generic | ( | struct e1000_hw * | hw | ) |
e1000_init_phy_ops_generic - Initialize PHY function pointers : pointer to the HW structure
Setups up the function pointers to no-op functions
Definition at line 61 of file e1000_phy.c.
References e1000_phy_operations::acquire, e1000_phy_operations::check_polarity, e1000_phy_operations::check_reset_block, e1000_phy_operations::commit, DEBUGFUNC, e1000_null_lplu_state(), e1000_null_ops_generic(), e1000_null_phy_generic(), e1000_null_read_reg(), e1000_null_write_reg(), e1000_phy_operations::get_cfg_done, e1000_phy_operations::get_info, e1000_phy_operations::init_params, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_down, e1000_phy_operations::power_up, e1000_phy_operations::read_reg, e1000_phy_operations::release, e1000_phy_operations::reset, e1000_phy_operations::set_d0_lplu_state, e1000_phy_operations::set_d3_lplu_state, and e1000_phy_operations::write_reg.
Referenced by e1000_setup_init_funcs().
00062 { 00063 struct e1000_phy_info *phy = &hw->phy; 00064 DEBUGFUNC("e1000_init_phy_ops_generic"); 00065 00066 /* Initialize function pointers */ 00067 phy->ops.init_params = e1000_null_ops_generic; 00068 phy->ops.acquire = e1000_null_ops_generic; 00069 phy->ops.check_polarity = e1000_null_ops_generic; 00070 phy->ops.check_reset_block = e1000_null_ops_generic; 00071 phy->ops.commit = e1000_null_ops_generic; 00072 #if 0 00073 phy->ops.force_speed_duplex = e1000_null_ops_generic; 00074 #endif 00075 phy->ops.get_cfg_done = e1000_null_ops_generic; 00076 #if 0 00077 phy->ops.get_cable_length = e1000_null_ops_generic; 00078 #endif 00079 phy->ops.get_info = e1000_null_ops_generic; 00080 phy->ops.read_reg = e1000_null_read_reg; 00081 phy->ops.release = e1000_null_phy_generic; 00082 phy->ops.reset = e1000_null_ops_generic; 00083 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 00084 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 00085 phy->ops.write_reg = e1000_null_write_reg; 00086 phy->ops.power_up = e1000_null_phy_generic; 00087 phy->ops.power_down = e1000_null_phy_generic; 00088 }
e1000_null_read_reg - No-op function, return 0 : pointer to the HW structure
Definition at line 94 of file e1000_phy.c.
References DEBUGFUNC, and E1000_SUCCESS.
Referenced by e1000_init_phy_ops_generic().
00096 { 00097 DEBUGFUNC("e1000_null_read_reg"); 00098 return E1000_SUCCESS; 00099 }
e1000_null_phy_generic - No-op function, return void : pointer to the HW structure
Definition at line 105 of file e1000_phy.c.
References DEBUGFUNC.
Referenced by e1000_init_phy_ops_generic().
00106 { 00107 DEBUGFUNC("e1000_null_phy_generic"); 00108 return; 00109 }
e1000_null_lplu_state - No-op function, return 0 : pointer to the HW structure
Definition at line 115 of file e1000_phy.c.
References DEBUGFUNC, and E1000_SUCCESS.
Referenced by e1000_init_phy_ops_generic().
00116 { 00117 DEBUGFUNC("e1000_null_lplu_state"); 00118 return E1000_SUCCESS; 00119 }
e1000_null_write_reg - No-op function, return 0 : pointer to the HW structure
Definition at line 125 of file e1000_phy.c.
References DEBUGFUNC, and E1000_SUCCESS.
Referenced by e1000_init_phy_ops_generic().
00127 { 00128 DEBUGFUNC("e1000_null_write_reg"); 00129 return E1000_SUCCESS; 00130 }
e1000_check_reset_block_generic - Check if PHY reset is blocked : pointer to the HW structure
Read the PHY management control register and check whether a PHY reset is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise return E1000_BLK_PHY_RESET (12).
Definition at line 140 of file e1000_phy.c.
References DEBUGFUNC, E1000_BLK_PHY_RESET, E1000_MANC, E1000_MANC_BLK_PHY_RST_ON_IDE, E1000_READ_REG, E1000_SUCCESS, and u32.
00141 { 00142 u32 manc; 00143 00144 DEBUGFUNC("e1000_check_reset_block"); 00145 00146 manc = E1000_READ_REG(hw, E1000_MANC); 00147 00148 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 00149 E1000_BLK_PHY_RESET : E1000_SUCCESS; 00150 }
e1000_get_phy_id - Retrieve the PHY ID and revision : pointer to the HW structure
Reads the PHY registers and stores the PHY ID and possibly the PHY revision in the hardware structure.
Definition at line 159 of file e1000_phy.c.
References DEBUGFUNC, E1000_SUCCESS, e1000_phy_info::id, e1000_phy_info::ops, e1000_hw::phy, PHY_ID1, PHY_ID2, PHY_REVISION_MASK, e1000_phy_operations::read_reg, e1000_phy_info::revision, u16, u32, and usec_delay.
Referenced by e1000_determine_phy_address(), e1000_init_phy_params_82540(), e1000_init_phy_params_82541(), and e1000_init_phy_params_82543().
00160 { 00161 struct e1000_phy_info *phy = &hw->phy; 00162 s32 ret_val = E1000_SUCCESS; 00163 u16 phy_id; 00164 00165 DEBUGFUNC("e1000_get_phy_id"); 00166 00167 if (!(phy->ops.read_reg)) 00168 goto out; 00169 00170 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 00171 if (ret_val) 00172 goto out; 00173 00174 phy->id = (u32)(phy_id << 16); 00175 usec_delay(20); 00176 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 00177 if (ret_val) 00178 goto out; 00179 00180 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 00181 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 00182 00183 out: 00184 return ret_val; 00185 }
e1000_phy_reset_dsp_generic - Reset PHY DSP : pointer to the HW structure
Reset the digital signal processor.
Definition at line 193 of file e1000_phy.c.
References DEBUGFUNC, E1000_SUCCESS, M88E1000_PHY_GEN_CONTROL, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::write_reg.
00194 { 00195 s32 ret_val = E1000_SUCCESS; 00196 00197 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 00198 00199 if (!(hw->phy.ops.write_reg)) 00200 goto out; 00201 00202 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 00203 if (ret_val) 00204 goto out; 00205 00206 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 00207 00208 out: 00209 return ret_val; 00210 }
e1000_read_phy_reg_mdic - Read MDI control register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the MDI control register in the PHY at offset and stores the information read to data.
Definition at line 221 of file e1000_phy.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT, E1000_ERR_PHY, E1000_GEN_POLL_TIMEOUT, E1000_MDIC, E1000_MDIC_ERROR, E1000_MDIC_OP_READ, E1000_MDIC_PHY_SHIFT, E1000_MDIC_READY, E1000_MDIC_REG_SHIFT, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::phy, u16, u32, and usec_delay.
Referenced by e1000_read_phy_reg_igp(), and e1000_read_phy_reg_m88().
00222 { 00223 struct e1000_phy_info *phy = &hw->phy; 00224 u32 i, mdic = 0; 00225 s32 ret_val = E1000_SUCCESS; 00226 00227 DEBUGFUNC("e1000_read_phy_reg_mdic"); 00228 00229 /* 00230 * Set up Op-code, Phy Address, and register offset in the MDI 00231 * Control register. The MAC will take care of interfacing with the 00232 * PHY to retrieve the desired data. 00233 */ 00234 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 00235 (phy->addr << E1000_MDIC_PHY_SHIFT) | 00236 (E1000_MDIC_OP_READ)); 00237 00238 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 00239 00240 /* 00241 * Poll the ready bit to see if the MDI read completed 00242 * Increasing the time out as testing showed failures with 00243 * the lower time out 00244 */ 00245 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 00246 usec_delay(50); 00247 mdic = E1000_READ_REG(hw, E1000_MDIC); 00248 if (mdic & E1000_MDIC_READY) 00249 break; 00250 } 00251 if (!(mdic & E1000_MDIC_READY)) { 00252 DEBUGOUT("MDI Read did not complete\n"); 00253 ret_val = -E1000_ERR_PHY; 00254 goto out; 00255 } 00256 if (mdic & E1000_MDIC_ERROR) { 00257 DEBUGOUT("MDI Error\n"); 00258 ret_val = -E1000_ERR_PHY; 00259 goto out; 00260 } 00261 *data = (u16) mdic; 00262 00263 out: 00264 return ret_val; 00265 }
e1000_write_phy_reg_mdic - Write MDI control register : pointer to the HW structure : register offset to write to : data to write to register at offset
Writes data to MDI control register in the PHY at offset.
Definition at line 275 of file e1000_phy.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT, E1000_ERR_PHY, E1000_GEN_POLL_TIMEOUT, E1000_MDIC, E1000_MDIC_ERROR, E1000_MDIC_OP_WRITE, E1000_MDIC_PHY_SHIFT, E1000_MDIC_READY, E1000_MDIC_REG_SHIFT, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::phy, u32, and usec_delay.
Referenced by e1000_read_phy_reg_igp(), e1000_write_phy_reg_igp(), and e1000_write_phy_reg_m88().
00276 { 00277 struct e1000_phy_info *phy = &hw->phy; 00278 u32 i, mdic = 0; 00279 s32 ret_val = E1000_SUCCESS; 00280 00281 DEBUGFUNC("e1000_write_phy_reg_mdic"); 00282 00283 /* 00284 * Set up Op-code, Phy Address, and register offset in the MDI 00285 * Control register. The MAC will take care of interfacing with the 00286 * PHY to retrieve the desired data. 00287 */ 00288 mdic = (((u32)data) | 00289 (offset << E1000_MDIC_REG_SHIFT) | 00290 (phy->addr << E1000_MDIC_PHY_SHIFT) | 00291 (E1000_MDIC_OP_WRITE)); 00292 00293 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 00294 00295 /* 00296 * Poll the ready bit to see if the MDI read completed 00297 * Increasing the time out as testing showed failures with 00298 * the lower time out 00299 */ 00300 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 00301 usec_delay(50); 00302 mdic = E1000_READ_REG(hw, E1000_MDIC); 00303 if (mdic & E1000_MDIC_READY) 00304 break; 00305 } 00306 if (!(mdic & E1000_MDIC_READY)) { 00307 DEBUGOUT("MDI Write did not complete\n"); 00308 ret_val = -E1000_ERR_PHY; 00309 goto out; 00310 } 00311 if (mdic & E1000_MDIC_ERROR) { 00312 DEBUGOUT("MDI Error\n"); 00313 ret_val = -E1000_ERR_PHY; 00314 goto out; 00315 } 00316 00317 out: 00318 return ret_val; 00319 }
e1000_read_phy_reg_m88 - Read m88 PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 331 of file e1000_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, e1000_read_phy_reg_mdic(), E1000_SUCCESS, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::release.
Referenced by e1000_init_phy_params_82540(), and e1000_init_phy_params_82543().
00332 { 00333 s32 ret_val = E1000_SUCCESS; 00334 00335 DEBUGFUNC("e1000_read_phy_reg_m88"); 00336 00337 if (!(hw->phy.ops.acquire)) 00338 goto out; 00339 00340 ret_val = hw->phy.ops.acquire(hw); 00341 if (ret_val) 00342 goto out; 00343 00344 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00345 data); 00346 00347 hw->phy.ops.release(hw); 00348 00349 out: 00350 return ret_val; 00351 }
e1000_write_phy_reg_m88 - Write m88 PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 362 of file e1000_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_SUCCESS, e1000_write_phy_reg_mdic(), MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::release.
Referenced by e1000_init_phy_params_82540(), and e1000_init_phy_params_82543().
00363 { 00364 s32 ret_val = E1000_SUCCESS; 00365 00366 DEBUGFUNC("e1000_write_phy_reg_m88"); 00367 00368 if (!(hw->phy.ops.acquire)) 00369 goto out; 00370 00371 ret_val = hw->phy.ops.acquire(hw); 00372 if (ret_val) 00373 goto out; 00374 00375 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00376 data); 00377 00378 hw->phy.ops.release(hw); 00379 00380 out: 00381 return ret_val; 00382 }
e1000_read_phy_reg_igp - Read igp PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary, then reads the PHY register at offset and storing the retrieved information in data. Release any acquired semaphores before exiting.
Definition at line 394 of file e1000_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, e1000_read_phy_reg_mdic(), E1000_SUCCESS, e1000_write_phy_reg_mdic(), IGP01E1000_PHY_PAGE_SELECT, MAX_PHY_MULTI_PAGE_REG, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, and u16.
Referenced by e1000_init_phy_params_82541().
00395 { 00396 s32 ret_val = E1000_SUCCESS; 00397 00398 DEBUGFUNC("e1000_read_phy_reg_igp"); 00399 00400 if (!(hw->phy.ops.acquire)) 00401 goto out; 00402 00403 ret_val = hw->phy.ops.acquire(hw); 00404 if (ret_val) 00405 goto out; 00406 00407 if (offset > MAX_PHY_MULTI_PAGE_REG) { 00408 ret_val = e1000_write_phy_reg_mdic(hw, 00409 IGP01E1000_PHY_PAGE_SELECT, 00410 (u16)offset); 00411 if (ret_val) { 00412 hw->phy.ops.release(hw); 00413 goto out; 00414 } 00415 } 00416 00417 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00418 data); 00419 00420 hw->phy.ops.release(hw); 00421 00422 out: 00423 return ret_val; 00424 }
e1000_write_phy_reg_igp - Write igp PHY register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary, then writes the data to PHY register at the offset. Release any acquired semaphores before exiting.
Definition at line 435 of file e1000_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_SUCCESS, e1000_write_phy_reg_mdic(), IGP01E1000_PHY_PAGE_SELECT, MAX_PHY_MULTI_PAGE_REG, MAX_PHY_REG_ADDRESS, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, and u16.
Referenced by e1000_init_phy_params_82541().
00436 { 00437 s32 ret_val = E1000_SUCCESS; 00438 00439 DEBUGFUNC("e1000_write_phy_reg_igp"); 00440 00441 if (!(hw->phy.ops.acquire)) 00442 goto out; 00443 00444 ret_val = hw->phy.ops.acquire(hw); 00445 if (ret_val) 00446 goto out; 00447 00448 if (offset > MAX_PHY_MULTI_PAGE_REG) { 00449 ret_val = e1000_write_phy_reg_mdic(hw, 00450 IGP01E1000_PHY_PAGE_SELECT, 00451 (u16)offset); 00452 if (ret_val) { 00453 hw->phy.ops.release(hw); 00454 goto out; 00455 } 00456 } 00457 00458 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 00459 data); 00460 00461 hw->phy.ops.release(hw); 00462 00463 out: 00464 return ret_val; 00465 }
e1000_read_kmrn_reg_generic - Read kumeran register : pointer to the HW structure : register offset to be read : pointer to the read data
Acquires semaphore, if necessary. Then reads the PHY register at offset using the kumeran interface. The information retrieved is stored in data. Release any acquired semaphores before exiting.
Definition at line 477 of file e1000_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_KMRNCTRLSTA, E1000_KMRNCTRLSTA_OFFSET, E1000_KMRNCTRLSTA_OFFSET_SHIFT, E1000_KMRNCTRLSTA_REN, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, u16, u32, and usec_delay.
Referenced by e1000_read_kmrn_reg().
00478 { 00479 u32 kmrnctrlsta; 00480 s32 ret_val = E1000_SUCCESS; 00481 00482 DEBUGFUNC("e1000_read_kmrn_reg_generic"); 00483 00484 if (!(hw->phy.ops.acquire)) 00485 goto out; 00486 00487 ret_val = hw->phy.ops.acquire(hw); 00488 if (ret_val) 00489 goto out; 00490 00491 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 00492 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 00493 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 00494 00495 usec_delay(2); 00496 00497 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 00498 *data = (u16)kmrnctrlsta; 00499 00500 hw->phy.ops.release(hw); 00501 00502 out: 00503 return ret_val; 00504 }
e1000_write_kmrn_reg_generic - Write kumeran register : pointer to the HW structure : register offset to write to : data to write at register offset
Acquires semaphore, if necessary. Then write the data to PHY register at the offset using the kumeran interface. Release any acquired semaphores before exiting.
Definition at line 516 of file e1000_phy.c.
References e1000_phy_operations::acquire, DEBUGFUNC, E1000_KMRNCTRLSTA, E1000_KMRNCTRLSTA_OFFSET, E1000_KMRNCTRLSTA_OFFSET_SHIFT, E1000_SUCCESS, E1000_WRITE_REG, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, u32, and usec_delay.
Referenced by e1000_write_kmrn_reg().
00517 { 00518 u32 kmrnctrlsta; 00519 s32 ret_val = E1000_SUCCESS; 00520 00521 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 00522 00523 if (!(hw->phy.ops.acquire)) 00524 goto out; 00525 00526 ret_val = hw->phy.ops.acquire(hw); 00527 if (ret_val) 00528 goto out; 00529 00530 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 00531 E1000_KMRNCTRLSTA_OFFSET) | data; 00532 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 00533 00534 usec_delay(2); 00535 hw->phy.ops.release(hw); 00536 00537 out: 00538 return ret_val; 00539 }
e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link : pointer to the HW structure
Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock and downshift values are set also.
Definition at line 548 of file e1000_phy.c.
References e1000_phy_operations::commit, DEBUGFUNC, DEBUGOUT, e1000_phy_info::disable_polarity_correction, E1000_REVISION_2, E1000_REVISION_4, E1000_SUCCESS, e1000_phy_info::id, M88E1000_EPSCR_MASTER_DOWNSHIFT_1X, M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK, M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X, M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK, M88E1000_EPSCR_TX_CLK_25, M88E1000_EXT_PHY_SPEC_CTRL, M88E1000_PHY_SPEC_CTRL, M88E1000_PSCR_ASSERT_CRS_ON_TX, M88E1000_PSCR_AUTO_X_1000T, M88E1000_PSCR_AUTO_X_MODE, M88E1000_PSCR_MDI_MANUAL_MODE, M88E1000_PSCR_MDIX_MANUAL_MODE, M88E1000_PSCR_POLARITY_REVERSAL, M88E1111_I_PHY_ID, M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X, M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK, e1000_phy_info::mdix, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::reset_disable, e1000_phy_info::revision, u16, and e1000_phy_operations::write_reg.
Referenced by e1000_setup_copper_link_82540(), and e1000_setup_copper_link_82543().
00549 { 00550 struct e1000_phy_info *phy = &hw->phy; 00551 s32 ret_val; 00552 u16 phy_data; 00553 00554 DEBUGFUNC("e1000_copper_link_setup_m88"); 00555 00556 if (phy->reset_disable) { 00557 ret_val = E1000_SUCCESS; 00558 goto out; 00559 } 00560 00561 /* Enable CRS on TX. This must be set for half-duplex operation. */ 00562 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 00563 if (ret_val) 00564 goto out; 00565 00566 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 00567 00568 /* 00569 * Options: 00570 * MDI/MDI-X = 0 (default) 00571 * 0 - Auto for all speeds 00572 * 1 - MDI mode 00573 * 2 - MDI-X mode 00574 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 00575 */ 00576 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 00577 00578 switch (phy->mdix) { 00579 case 1: 00580 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 00581 break; 00582 case 2: 00583 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 00584 break; 00585 case 3: 00586 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 00587 break; 00588 case 0: 00589 default: 00590 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 00591 break; 00592 } 00593 00594 /* 00595 * Options: 00596 * disable_polarity_correction = 0 (default) 00597 * Automatic Correction for Reversed Cable Polarity 00598 * 0 - Disabled 00599 * 1 - Enabled 00600 */ 00601 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 00602 if (phy->disable_polarity_correction == 1) 00603 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 00604 00605 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 00606 if (ret_val) 00607 goto out; 00608 00609 if (phy->revision < E1000_REVISION_4) { 00610 /* 00611 * Force TX_CLK in the Extended PHY Specific Control Register 00612 * to 25MHz clock. 00613 */ 00614 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00615 &phy_data); 00616 if (ret_val) 00617 goto out; 00618 00619 phy_data |= M88E1000_EPSCR_TX_CLK_25; 00620 00621 if ((phy->revision == E1000_REVISION_2) && 00622 (phy->id == M88E1111_I_PHY_ID)) { 00623 /* 82573L PHY - set the downshift counter to 5x. */ 00624 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 00625 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 00626 } else { 00627 /* Configure Master and Slave downshift values */ 00628 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 00629 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 00630 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 00631 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 00632 } 00633 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 00634 phy_data); 00635 if (ret_val) 00636 goto out; 00637 } 00638 00639 /* Commit the changes. */ 00640 ret_val = phy->ops.commit(hw); 00641 if (ret_val) { 00642 DEBUGOUT("Error committing the PHY changes\n"); 00643 goto out; 00644 } 00645 00646 out: 00647 return ret_val; 00648 }
e1000_copper_link_setup_igp - Setup igp PHY's for copper link : pointer to the HW structure
Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for igp PHY's.
Definition at line 657 of file e1000_phy.c.
References ADVERTISE_1000_FULL, e1000_mac_info::autoneg, e1000_phy_info::autoneg_advertised, CR_1000T_MS_ENABLE, CR_1000T_MS_VALUE, DEBUGFUNC, DEBUGOUT, e1000_ms_auto, e1000_ms_force_master, e1000_ms_force_slave, e1000_phy_igp, E1000_SUCCESS, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PHY_PORT_CTRL, IGP01E1000_PSCFR_SMART_SPEED, IGP01E1000_PSCR_AUTO_MDIX, IGP01E1000_PSCR_FORCE_MDI_MDIX, e1000_hw::mac, e1000_phy_info::mdix, e1000_phy_info::ms_type, msec_delay, e1000_phy_info::ops, e1000_phy_info::original_ms_type, e1000_hw::phy, PHY_1000T_CTRL, e1000_phy_operations::read_reg, e1000_phy_operations::reset, e1000_phy_info::reset_disable, e1000_phy_operations::set_d0_lplu_state, e1000_phy_operations::set_d3_lplu_state, e1000_phy_info::type, u16, and e1000_phy_operations::write_reg.
Referenced by e1000_setup_copper_link_82541().
00658 { 00659 struct e1000_phy_info *phy = &hw->phy; 00660 s32 ret_val; 00661 u16 data; 00662 00663 DEBUGFUNC("e1000_copper_link_setup_igp"); 00664 00665 if (phy->reset_disable) { 00666 ret_val = E1000_SUCCESS; 00667 goto out; 00668 } 00669 00670 ret_val = hw->phy.ops.reset(hw); 00671 if (ret_val) { 00672 DEBUGOUT("Error resetting the PHY.\n"); 00673 goto out; 00674 } 00675 00676 /* 00677 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 00678 * timeout issues when LFS is enabled. 00679 */ 00680 msec_delay(100); 00681 00682 /* 00683 * The NVM settings will configure LPLU in D3 for 00684 * non-IGP1 PHYs. 00685 */ 00686 if (phy->type == e1000_phy_igp) { 00687 /* disable lplu d3 during driver init */ 00688 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false); 00689 if (ret_val) { 00690 DEBUGOUT("Error Disabling LPLU D3\n"); 00691 goto out; 00692 } 00693 } 00694 00695 /* disable lplu d0 during driver init */ 00696 if (hw->phy.ops.set_d0_lplu_state) { 00697 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); 00698 if (ret_val) { 00699 DEBUGOUT("Error Disabling LPLU D0\n"); 00700 goto out; 00701 } 00702 } 00703 /* Configure mdi-mdix settings */ 00704 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 00705 if (ret_val) 00706 goto out; 00707 00708 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 00709 00710 switch (phy->mdix) { 00711 case 1: 00712 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 00713 break; 00714 case 2: 00715 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 00716 break; 00717 case 0: 00718 default: 00719 data |= IGP01E1000_PSCR_AUTO_MDIX; 00720 break; 00721 } 00722 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 00723 if (ret_val) 00724 goto out; 00725 00726 /* set auto-master slave resolution settings */ 00727 if (hw->mac.autoneg) { 00728 /* 00729 * when autonegotiation advertisement is only 1000Mbps then we 00730 * should disable SmartSpeed and enable Auto MasterSlave 00731 * resolution as hardware default. 00732 */ 00733 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 00734 /* Disable SmartSpeed */ 00735 ret_val = phy->ops.read_reg(hw, 00736 IGP01E1000_PHY_PORT_CONFIG, 00737 &data); 00738 if (ret_val) 00739 goto out; 00740 00741 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 00742 ret_val = phy->ops.write_reg(hw, 00743 IGP01E1000_PHY_PORT_CONFIG, 00744 data); 00745 if (ret_val) 00746 goto out; 00747 00748 /* Set auto Master/Slave resolution process */ 00749 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 00750 if (ret_val) 00751 goto out; 00752 00753 data &= ~CR_1000T_MS_ENABLE; 00754 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 00755 if (ret_val) 00756 goto out; 00757 } 00758 00759 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 00760 if (ret_val) 00761 goto out; 00762 00763 /* load defaults for future use */ 00764 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 00765 ((data & CR_1000T_MS_VALUE) ? 00766 e1000_ms_force_master : 00767 e1000_ms_force_slave) : 00768 e1000_ms_auto; 00769 00770 switch (phy->ms_type) { 00771 case e1000_ms_force_master: 00772 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 00773 break; 00774 case e1000_ms_force_slave: 00775 data |= CR_1000T_MS_ENABLE; 00776 data &= ~(CR_1000T_MS_VALUE); 00777 break; 00778 case e1000_ms_auto: 00779 data &= ~CR_1000T_MS_ENABLE; 00780 default: 00781 break; 00782 } 00783 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 00784 if (ret_val) 00785 goto out; 00786 } 00787 00788 out: 00789 return ret_val; 00790 }
e1000_copper_link_autoneg - Setup/Enable autoneg for copper link : pointer to the HW structure
Performs initial bounds checking on autoneg advertisement parameter, then configure to advertise the full capability. Setup the PHY to autoneg and restart the negotiation process between the link partner. If autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
Definition at line 801 of file e1000_phy.c.
References e1000_phy_info::autoneg_advertised, e1000_phy_info::autoneg_mask, e1000_phy_info::autoneg_wait_to_complete, DEBUGFUNC, DEBUGOUT, e1000_phy_setup_autoneg(), e1000_mac_info::get_link_status, e1000_hw::mac, MII_CR_AUTO_NEG_EN, MII_CR_RESTART_AUTO_NEG, e1000_mac_info::ops, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, e1000_mac_operations::wait_autoneg, and e1000_phy_operations::write_reg.
Referenced by e1000_setup_copper_link_82543(), and e1000_setup_copper_link_generic().
00802 { 00803 struct e1000_phy_info *phy = &hw->phy; 00804 s32 ret_val; 00805 u16 phy_ctrl; 00806 00807 DEBUGFUNC("e1000_copper_link_autoneg"); 00808 00809 /* 00810 * Perform some bounds checking on the autoneg advertisement 00811 * parameter. 00812 */ 00813 phy->autoneg_advertised &= phy->autoneg_mask; 00814 00815 /* 00816 * If autoneg_advertised is zero, we assume it was not defaulted 00817 * by the calling code so we set to advertise full capability. 00818 */ 00819 if (phy->autoneg_advertised == 0) 00820 phy->autoneg_advertised = phy->autoneg_mask; 00821 00822 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 00823 ret_val = e1000_phy_setup_autoneg(hw); 00824 if (ret_val) { 00825 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 00826 goto out; 00827 } 00828 DEBUGOUT("Restarting Auto-Neg\n"); 00829 00830 /* 00831 * Restart auto-negotiation by setting the Auto Neg Enable bit and 00832 * the Auto Neg Restart bit in the PHY control register. 00833 */ 00834 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 00835 if (ret_val) 00836 goto out; 00837 00838 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 00839 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 00840 if (ret_val) 00841 goto out; 00842 00843 /* 00844 * Does the user want to wait for Auto-Neg to complete here, or 00845 * check at a later time (for example, callback routine). 00846 */ 00847 if (phy->autoneg_wait_to_complete) { 00848 ret_val = hw->mac.ops.wait_autoneg(hw); 00849 if (ret_val) { 00850 DEBUGOUT("Error while waiting for " 00851 "autoneg to complete\n"); 00852 goto out; 00853 } 00854 } 00855 00856 hw->mac.get_link_status = true; 00857 00858 out: 00859 return ret_val; 00860 }
e1000_phy_setup_autoneg - Configure PHY for auto-negotiation : pointer to the HW structure
Reads the MII auto-neg advertisement register and/or the 1000T control register and if the PHY is already setup for auto-negotiation, then return successful. Otherwise, setup advertisement and flow control to the appropriate values for the wanted auto-negotiation.
Definition at line 871 of file e1000_phy.c.
References ADVERTISE_1000_FULL, ADVERTISE_1000_HALF, ADVERTISE_100_FULL, ADVERTISE_100_HALF, ADVERTISE_10_FULL, ADVERTISE_10_HALF, e1000_phy_info::autoneg_advertised, e1000_phy_info::autoneg_mask, CR_1000T_FD_CAPS, CR_1000T_HD_CAPS, e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, DEBUGOUT1, E1000_ERR_CONFIG, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, e1000_hw::fc, NWAY_AR_100TX_FD_CAPS, NWAY_AR_100TX_HD_CAPS, NWAY_AR_10T_FD_CAPS, NWAY_AR_10T_HD_CAPS, NWAY_AR_ASM_DIR, NWAY_AR_PAUSE, e1000_phy_info::ops, e1000_hw::phy, PHY_1000T_CTRL, PHY_AUTONEG_ADV, e1000_phy_operations::read_reg, u16, and e1000_phy_operations::write_reg.
Referenced by e1000_copper_link_autoneg().
00872 { 00873 struct e1000_phy_info *phy = &hw->phy; 00874 s32 ret_val; 00875 u16 mii_autoneg_adv_reg; 00876 u16 mii_1000t_ctrl_reg = 0; 00877 00878 DEBUGFUNC("e1000_phy_setup_autoneg"); 00879 00880 phy->autoneg_advertised &= phy->autoneg_mask; 00881 00882 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 00883 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 00884 if (ret_val) 00885 goto out; 00886 00887 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 00888 /* Read the MII 1000Base-T Control Register (Address 9). */ 00889 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 00890 &mii_1000t_ctrl_reg); 00891 if (ret_val) 00892 goto out; 00893 } 00894 00895 /* 00896 * Need to parse both autoneg_advertised and fc and set up 00897 * the appropriate PHY registers. First we will parse for 00898 * autoneg_advertised software override. Since we can advertise 00899 * a plethora of combinations, we need to check each bit 00900 * individually. 00901 */ 00902 00903 /* 00904 * First we clear all the 10/100 mb speed bits in the Auto-Neg 00905 * Advertisement Register (Address 4) and the 1000 mb speed bits in 00906 * the 1000Base-T Control Register (Address 9). 00907 */ 00908 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 00909 NWAY_AR_100TX_HD_CAPS | 00910 NWAY_AR_10T_FD_CAPS | 00911 NWAY_AR_10T_HD_CAPS); 00912 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 00913 00914 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 00915 00916 /* Do we want to advertise 10 Mb Half Duplex? */ 00917 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 00918 DEBUGOUT("Advertise 10mb Half duplex\n"); 00919 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 00920 } 00921 00922 /* Do we want to advertise 10 Mb Full Duplex? */ 00923 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 00924 DEBUGOUT("Advertise 10mb Full duplex\n"); 00925 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 00926 } 00927 00928 /* Do we want to advertise 100 Mb Half Duplex? */ 00929 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 00930 DEBUGOUT("Advertise 100mb Half duplex\n"); 00931 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 00932 } 00933 00934 /* Do we want to advertise 100 Mb Full Duplex? */ 00935 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 00936 DEBUGOUT("Advertise 100mb Full duplex\n"); 00937 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 00938 } 00939 00940 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 00941 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 00942 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 00943 00944 /* Do we want to advertise 1000 Mb Full Duplex? */ 00945 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 00946 DEBUGOUT("Advertise 1000mb Full duplex\n"); 00947 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 00948 } 00949 00950 /* 00951 * Check for a software override of the flow control settings, and 00952 * setup the PHY advertisement registers accordingly. If 00953 * auto-negotiation is enabled, then software will have to set the 00954 * "PAUSE" bits to the correct value in the Auto-Negotiation 00955 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 00956 * negotiation. 00957 * 00958 * The possible values of the "fc" parameter are: 00959 * 0: Flow control is completely disabled 00960 * 1: Rx flow control is enabled (we can receive pause frames 00961 * but not send pause frames). 00962 * 2: Tx flow control is enabled (we can send pause frames 00963 * but we do not support receiving pause frames). 00964 * 3: Both Rx and Tx flow control (symmetric) are enabled. 00965 * other: No software override. The flow control configuration 00966 * in the EEPROM is used. 00967 */ 00968 switch (hw->fc.current_mode) { 00969 case e1000_fc_none: 00970 /* 00971 * Flow control (Rx & Tx) is completely disabled by a 00972 * software over-ride. 00973 */ 00974 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 00975 break; 00976 case e1000_fc_rx_pause: 00977 /* 00978 * Rx Flow control is enabled, and Tx Flow control is 00979 * disabled, by a software over-ride. 00980 * 00981 * Since there really isn't a way to advertise that we are 00982 * capable of Rx Pause ONLY, we will advertise that we 00983 * support both symmetric and asymmetric Rx PAUSE. Later 00984 * (in e1000_config_fc_after_link_up) we will disable the 00985 * hw's ability to send PAUSE frames. 00986 */ 00987 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 00988 break; 00989 case e1000_fc_tx_pause: 00990 /* 00991 * Tx Flow control is enabled, and Rx Flow control is 00992 * disabled, by a software over-ride. 00993 */ 00994 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 00995 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 00996 break; 00997 case e1000_fc_full: 00998 /* 00999 * Flow control (both Rx and Tx) is enabled by a software 01000 * over-ride. 01001 */ 01002 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 01003 break; 01004 default: 01005 DEBUGOUT("Flow control param set incorrectly\n"); 01006 ret_val = -E1000_ERR_CONFIG; 01007 goto out; 01008 } 01009 01010 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 01011 if (ret_val) 01012 goto out; 01013 01014 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 01015 01016 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 01017 ret_val = phy->ops.write_reg(hw, 01018 PHY_1000T_CTRL, 01019 mii_1000t_ctrl_reg); 01020 if (ret_val) 01021 goto out; 01022 } 01023 01024 out: 01025 return ret_val; 01026 }
e1000_setup_copper_link_generic - Configure copper link settings : pointer to the HW structure
Calls the appropriate function to configure the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called. If link is not established, we return -E1000_ERR_PHY (-2).
Definition at line 1037 of file e1000_phy.c.
References e1000_mac_info::autoneg, COPPER_LINK_UP_LIMIT, DEBUGFUNC, DEBUGOUT, e1000_config_collision_dist_generic(), e1000_config_fc_after_link_up_generic(), e1000_copper_link_autoneg(), e1000_phy_has_link_generic(), e1000_hw::mac, e1000_phy_info::ops, and e1000_hw::phy.
Referenced by e1000_setup_copper_link_82540(), and e1000_setup_copper_link_82541().
01038 { 01039 s32 ret_val; 01040 bool link; 01041 01042 DEBUGFUNC("e1000_setup_copper_link_generic"); 01043 01044 if (hw->mac.autoneg) { 01045 /* 01046 * Setup autoneg and flow control advertisement and perform 01047 * autonegotiation. 01048 */ 01049 ret_val = e1000_copper_link_autoneg(hw); 01050 if (ret_val) 01051 goto out; 01052 } else { 01053 #if 0 01054 /* 01055 * PHY will be set to 10H, 10F, 100H or 100F 01056 * depending on user settings. 01057 */ 01058 DEBUGOUT("Forcing Speed and Duplex\n"); 01059 ret_val = hw->phy.ops.force_speed_duplex(hw); 01060 if (ret_val) { 01061 DEBUGOUT("Error Forcing Speed and Duplex\n"); 01062 goto out; 01063 } 01064 #endif 01065 } 01066 01067 /* 01068 * Check link status. Wait up to 100 microseconds for link to become 01069 * valid. 01070 */ 01071 ret_val = e1000_phy_has_link_generic(hw, 01072 COPPER_LINK_UP_LIMIT, 01073 10, 01074 &link); 01075 if (ret_val) 01076 goto out; 01077 01078 if (link) { 01079 DEBUGOUT("Valid link established!!!\n"); 01080 e1000_config_collision_dist_generic(hw); 01081 ret_val = e1000_config_fc_after_link_up_generic(hw); 01082 } else { 01083 DEBUGOUT("Unable to establish link!!!\n"); 01084 } 01085 01086 out: 01087 return ret_val; 01088 }
e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu
Success returns 0, Failure returns 1
The low power link up (lplu) state is set to the power management level D3 and SmartSpeed is disabled when active is true, else clear lplu for D3 and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU is used during Dx states where the power conservation is most important. During driver activity, SmartSpeed should be enabled so performance is maintained.
Definition at line 1422 of file e1000_phy.c.
References e1000_phy_info::autoneg_advertised, DEBUGFUNC, E1000_ALL_10_SPEED, E1000_ALL_NOT_GIG, E1000_ALL_SPEED_DUPLEX, e1000_smart_speed_off, e1000_smart_speed_on, E1000_SUCCESS, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PSCFR_SMART_SPEED, IGP02E1000_PHY_POWER_MGMT, IGP02E1000_PM_D3_LPLU, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::smart_speed, u16, and e1000_phy_operations::write_reg.
Referenced by e1000_set_d3_lplu_state_82541().
01423 { 01424 struct e1000_phy_info *phy = &hw->phy; 01425 s32 ret_val = E1000_SUCCESS; 01426 u16 data; 01427 01428 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 01429 01430 if (!(hw->phy.ops.read_reg)) 01431 goto out; 01432 01433 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 01434 if (ret_val) 01435 goto out; 01436 01437 if (!active) { 01438 data &= ~IGP02E1000_PM_D3_LPLU; 01439 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 01440 data); 01441 if (ret_val) 01442 goto out; 01443 /* 01444 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 01445 * during Dx states where the power conservation is most 01446 * important. During driver activity we should enable 01447 * SmartSpeed, so performance is maintained. 01448 */ 01449 if (phy->smart_speed == e1000_smart_speed_on) { 01450 ret_val = phy->ops.read_reg(hw, 01451 IGP01E1000_PHY_PORT_CONFIG, 01452 &data); 01453 if (ret_val) 01454 goto out; 01455 01456 data |= IGP01E1000_PSCFR_SMART_SPEED; 01457 ret_val = phy->ops.write_reg(hw, 01458 IGP01E1000_PHY_PORT_CONFIG, 01459 data); 01460 if (ret_val) 01461 goto out; 01462 } else if (phy->smart_speed == e1000_smart_speed_off) { 01463 ret_val = phy->ops.read_reg(hw, 01464 IGP01E1000_PHY_PORT_CONFIG, 01465 &data); 01466 if (ret_val) 01467 goto out; 01468 01469 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01470 ret_val = phy->ops.write_reg(hw, 01471 IGP01E1000_PHY_PORT_CONFIG, 01472 data); 01473 if (ret_val) 01474 goto out; 01475 } 01476 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 01477 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 01478 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 01479 data |= IGP02E1000_PM_D3_LPLU; 01480 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 01481 data); 01482 if (ret_val) 01483 goto out; 01484 01485 /* When LPLU is enabled, we should disable SmartSpeed */ 01486 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 01487 &data); 01488 if (ret_val) 01489 goto out; 01490 01491 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01492 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 01493 data); 01494 } 01495 01496 out: 01497 return ret_val; 01498 }
e1000_check_downshift_generic - Checks whether a downshift in speed occurred : pointer to the HW structure
Success returns 0, Failure returns 1
A downshift is detected by querying the PHY link health.
Definition at line 1508 of file e1000_phy.c.
References DEBUGFUNC, e1000_phy_gg82563, e1000_phy_igp, e1000_phy_igp_2, e1000_phy_igp_3, e1000_phy_m88, E1000_SUCCESS, IGP01E1000_PHY_LINK_HEALTH, IGP01E1000_PLHR_SS_DOWNGRADE, M88E1000_PHY_SPEC_STATUS, M88E1000_PSSR_DOWNSHIFT, offset, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::speed_downgraded, e1000_phy_info::type, and u16.
Referenced by e1000_check_for_copper_link_82543(), e1000_check_for_copper_link_generic(), and e1000_check_for_link_82541().
01509 { 01510 struct e1000_phy_info *phy = &hw->phy; 01511 s32 ret_val; 01512 u16 phy_data, offset, mask; 01513 01514 DEBUGFUNC("e1000_check_downshift_generic"); 01515 01516 switch (phy->type) { 01517 case e1000_phy_m88: 01518 case e1000_phy_gg82563: 01519 offset = M88E1000_PHY_SPEC_STATUS; 01520 mask = M88E1000_PSSR_DOWNSHIFT; 01521 break; 01522 case e1000_phy_igp_2: 01523 case e1000_phy_igp: 01524 case e1000_phy_igp_3: 01525 offset = IGP01E1000_PHY_LINK_HEALTH; 01526 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 01527 break; 01528 default: 01529 /* speed downshift not supported */ 01530 phy->speed_downgraded = false; 01531 ret_val = E1000_SUCCESS; 01532 goto out; 01533 } 01534 01535 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 01536 01537 if (!ret_val) 01538 phy->speed_downgraded = (phy_data & mask) ? true : false; 01539 01540 out: 01541 return ret_val; 01542 }
e1000_check_polarity_m88 - Checks the polarity.
: pointer to the HW structure
Success returns 0, Failure returns -E1000_ERR_PHY (-2)
Polarity is determined based on the PHY specific status register.
Definition at line 1552 of file e1000_phy.c.
References e1000_phy_info::cable_polarity, DEBUGFUNC, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, M88E1000_PHY_SPEC_STATUS, M88E1000_PSSR_REV_POLARITY, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, and u16.
Referenced by e1000_get_phy_info_m88(), e1000_init_phy_params_82540(), and e1000_init_phy_params_82543().
01553 { 01554 struct e1000_phy_info *phy = &hw->phy; 01555 s32 ret_val; 01556 u16 data; 01557 01558 DEBUGFUNC("e1000_check_polarity_m88"); 01559 01560 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 01561 01562 if (!ret_val) 01563 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 01564 ? e1000_rev_polarity_reversed 01565 : e1000_rev_polarity_normal; 01566 01567 return ret_val; 01568 }
e1000_check_polarity_igp - Checks the polarity.
: pointer to the HW structure
Success returns 0, Failure returns -E1000_ERR_PHY (-2)
Polarity is determined based on the PHY port status register, and the current speed (since there is no polarity at 100Mbps).
Definition at line 1579 of file e1000_phy.c.
References e1000_phy_info::cable_polarity, DEBUGFUNC, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, IGP01E1000_PHY_PCS_INIT_REG, IGP01E1000_PHY_POLARITY_MASK, IGP01E1000_PHY_PORT_STATUS, IGP01E1000_PSSR_POLARITY_REVERSED, IGP01E1000_PSSR_SPEED_1000MBPS, IGP01E1000_PSSR_SPEED_MASK, offset, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, and u16.
Referenced by e1000_get_phy_info_igp(), and e1000_init_phy_params_82541().
01580 { 01581 struct e1000_phy_info *phy = &hw->phy; 01582 s32 ret_val; 01583 u16 data, offset, mask; 01584 01585 DEBUGFUNC("e1000_check_polarity_igp"); 01586 01587 /* 01588 * Polarity is determined based on the speed of 01589 * our connection. 01590 */ 01591 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 01592 if (ret_val) 01593 goto out; 01594 01595 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 01596 IGP01E1000_PSSR_SPEED_1000MBPS) { 01597 offset = IGP01E1000_PHY_PCS_INIT_REG; 01598 mask = IGP01E1000_PHY_POLARITY_MASK; 01599 } else { 01600 /* 01601 * This really only applies to 10Mbps since 01602 * there is no polarity for 100Mbps (always 0). 01603 */ 01604 offset = IGP01E1000_PHY_PORT_STATUS; 01605 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 01606 } 01607 01608 ret_val = phy->ops.read_reg(hw, offset, &data); 01609 01610 if (!ret_val) 01611 phy->cable_polarity = (data & mask) 01612 ? e1000_rev_polarity_reversed 01613 : e1000_rev_polarity_normal; 01614 01615 out: 01616 return ret_val; 01617 }
e1000_check_polarity_ife - Check cable polarity for IFE PHY : pointer to the HW structure
Polarity is determined on the polarity reversal feature being enabled.
Definition at line 1625 of file e1000_phy.c.
References e1000_phy_info::cable_polarity, DEBUGFUNC, e1000_rev_polarity_normal, e1000_rev_polarity_reversed, IFE_PESC_POLARITY_REVERSED, IFE_PHY_EXTENDED_STATUS_CONTROL, IFE_PHY_SPECIAL_CONTROL, IFE_PSC_FORCE_POLARITY, offset, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_info::polarity_correction, e1000_phy_operations::read_reg, and u16.
01626 { 01627 struct e1000_phy_info *phy = &hw->phy; 01628 s32 ret_val; 01629 u16 phy_data, offset, mask; 01630 01631 DEBUGFUNC("e1000_check_polarity_ife"); 01632 01633 /* 01634 * Polarity is determined based on the reversal feature being enabled. 01635 */ 01636 if (phy->polarity_correction) { 01637 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 01638 mask = IFE_PESC_POLARITY_REVERSED; 01639 } else { 01640 offset = IFE_PHY_SPECIAL_CONTROL; 01641 mask = IFE_PSC_FORCE_POLARITY; 01642 } 01643 01644 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 01645 01646 if (!ret_val) 01647 phy->cable_polarity = (phy_data & mask) 01648 ? e1000_rev_polarity_reversed 01649 : e1000_rev_polarity_normal; 01650 01651 return ret_val; 01652 }
e1000_wait_autoneg_generic - Wait for auto-neg completion : pointer to the HW structure
Waits for auto-negotiation to complete or for the auto-negotiation time limit to expire, which ever happens first.
Definition at line 1661 of file e1000_phy.c.
References DEBUGFUNC, E1000_SUCCESS, MII_SR_AUTONEG_COMPLETE, msec_delay, e1000_phy_info::ops, e1000_hw::phy, PHY_AUTO_NEG_LIMIT, PHY_STATUS, e1000_phy_operations::read_reg, and u16.
Referenced by e1000_init_mac_ops_generic().
01662 { 01663 s32 ret_val = E1000_SUCCESS; 01664 u16 i, phy_status; 01665 01666 DEBUGFUNC("e1000_wait_autoneg_generic"); 01667 01668 if (!(hw->phy.ops.read_reg)) 01669 return E1000_SUCCESS; 01670 01671 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 01672 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 01673 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 01674 if (ret_val) 01675 break; 01676 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 01677 if (ret_val) 01678 break; 01679 if (phy_status & MII_SR_AUTONEG_COMPLETE) 01680 break; 01681 msec_delay(100); 01682 } 01683 01684 /* 01685 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 01686 * has completed. 01687 */ 01688 return ret_val; 01689 }
| s32 e1000_phy_has_link_generic | ( | struct e1000_hw * | hw, | |
| u32 | iterations, | |||
| u32 | usec_interval, | |||
| bool * | success | |||
| ) |
e1000_phy_has_link_generic - Polls PHY for link : pointer to the HW structure : number of times to poll for link : delay between polling attempts : pointer to whether polling was successful or not
Polls the PHY status register for link, 'iterations' number of times.
Definition at line 1700 of file e1000_phy.c.
References DEBUGFUNC, E1000_SUCCESS, MII_SR_LINK_STATUS, msec_delay_irq, e1000_phy_info::ops, e1000_hw::phy, PHY_STATUS, e1000_phy_operations::read_reg, u16, and usec_delay.
Referenced by e1000_check_for_copper_link_82543(), e1000_check_for_copper_link_generic(), e1000_check_for_link_82541(), e1000_get_phy_info_igp(), e1000_get_phy_info_m88(), e1000_polarity_reversal_workaround_82543(), e1000_setup_copper_link_82543(), and e1000_setup_copper_link_generic().
01702 { 01703 s32 ret_val = E1000_SUCCESS; 01704 u16 i, phy_status; 01705 01706 DEBUGFUNC("e1000_phy_has_link_generic"); 01707 01708 if (!(hw->phy.ops.read_reg)) 01709 return E1000_SUCCESS; 01710 01711 for (i = 0; i < iterations; i++) { 01712 /* 01713 * Some PHYs require the PHY_STATUS register to be read 01714 * twice due to the link bit being sticky. No harm doing 01715 * it across the board. 01716 */ 01717 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 01718 if (ret_val) { 01719 /* 01720 * If the first read fails, another entity may have 01721 * ownership of the resources, wait and try again to 01722 * see if they have relinquished the resources yet. 01723 */ 01724 usec_delay(usec_interval); 01725 } 01726 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 01727 if (ret_val) 01728 break; 01729 if (phy_status & MII_SR_LINK_STATUS) 01730 break; 01731 if (usec_interval >= 1000) 01732 msec_delay_irq(usec_interval/1000); 01733 else 01734 usec_delay(usec_interval); 01735 } 01736 01737 *success = (i < iterations) ? true : false; 01738 01739 return ret_val; 01740 }
e1000_get_phy_info_m88 - Retrieve PHY information : pointer to the HW structure
Valid for only copper links. Read the PHY status register (sticky read) to verify that link is up. Read the PHY special control register to determine the polarity and 10base-T extended distance. Read the PHY special status register to determine MDI/MDIx and current speed. If speed is 1000, then determine cable length, local and remote receiver.
Definition at line 1871 of file e1000_phy.c.
References e1000_phy_info::cable_length, DEBUGFUNC, DEBUGOUT, e1000_1000t_rx_status_not_ok, e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined, E1000_CABLE_LENGTH_UNDEFINED, e1000_check_polarity_m88(), E1000_ERR_CONFIG, e1000_media_type_copper, e1000_phy_has_link_generic(), e1000_phy_info::is_mdix, e1000_phy_info::local_rx, M88E1000_PHY_SPEC_CTRL, M88E1000_PHY_SPEC_STATUS, M88E1000_PSCR_POLARITY_REVERSAL, M88E1000_PSSR_1000MBS, M88E1000_PSSR_MDIX, M88E1000_PSSR_SPEED, e1000_phy_info::media_type, e1000_phy_info::ops, e1000_hw::phy, PHY_1000T_STATUS, e1000_phy_info::polarity_correction, e1000_phy_operations::read_reg, e1000_phy_info::remote_rx, SR_1000T_LOCAL_RX_STATUS, SR_1000T_REMOTE_RX_STATUS, and u16.
Referenced by e1000_init_phy_params_82540(), and e1000_init_phy_params_82543().
01872 { 01873 struct e1000_phy_info *phy = &hw->phy; 01874 s32 ret_val; 01875 u16 phy_data; 01876 bool link; 01877 01878 DEBUGFUNC("e1000_get_phy_info_m88"); 01879 01880 if (hw->phy.media_type != e1000_media_type_copper) { 01881 DEBUGOUT("Phy info is only valid for copper media\n"); 01882 ret_val = -E1000_ERR_CONFIG; 01883 goto out; 01884 } 01885 01886 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 01887 if (ret_val) 01888 goto out; 01889 01890 if (!link) { 01891 DEBUGOUT("Phy info is only valid if link is up\n"); 01892 ret_val = -E1000_ERR_CONFIG; 01893 goto out; 01894 } 01895 01896 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 01897 if (ret_val) 01898 goto out; 01899 01900 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 01901 ? true : false; 01902 01903 ret_val = e1000_check_polarity_m88(hw); 01904 if (ret_val) 01905 goto out; 01906 01907 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 01908 if (ret_val) 01909 goto out; 01910 01911 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 01912 01913 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 01914 #if 0 01915 ret_val = hw->phy.ops.get_cable_length(hw); 01916 #endif 01917 ret_val = -E1000_ERR_CONFIG; 01918 if (ret_val) 01919 goto out; 01920 01921 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 01922 if (ret_val) 01923 goto out; 01924 01925 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 01926 ? e1000_1000t_rx_status_ok 01927 : e1000_1000t_rx_status_not_ok; 01928 01929 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 01930 ? e1000_1000t_rx_status_ok 01931 : e1000_1000t_rx_status_not_ok; 01932 } else { 01933 /* Set values to "undefined" */ 01934 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 01935 phy->local_rx = e1000_1000t_rx_status_undefined; 01936 phy->remote_rx = e1000_1000t_rx_status_undefined; 01937 } 01938 01939 out: 01940 return ret_val; 01941 }
e1000_get_phy_info_igp - Retrieve igp PHY information : pointer to the HW structure
Read PHY status to determine if link is up. If link is up, then set/determine 10base-T extended distance and polarity correction. Read PHY port status to determine MDI/MDIx and speed. Based on the speed, determine on the cable length, local and remote receiver.
Definition at line 1952 of file e1000_phy.c.
References e1000_phy_info::cable_length, DEBUGFUNC, DEBUGOUT, e1000_1000t_rx_status_not_ok, e1000_1000t_rx_status_ok, e1000_1000t_rx_status_undefined, E1000_CABLE_LENGTH_UNDEFINED, e1000_check_polarity_igp(), E1000_ERR_CONFIG, e1000_phy_has_link_generic(), IGP01E1000_PHY_PORT_STATUS, IGP01E1000_PSSR_MDIX, IGP01E1000_PSSR_SPEED_1000MBPS, IGP01E1000_PSSR_SPEED_MASK, e1000_phy_info::is_mdix, e1000_phy_info::local_rx, e1000_phy_info::ops, e1000_hw::phy, PHY_1000T_STATUS, e1000_phy_info::polarity_correction, e1000_phy_operations::read_reg, e1000_phy_info::remote_rx, SR_1000T_LOCAL_RX_STATUS, SR_1000T_REMOTE_RX_STATUS, and u16.
Referenced by e1000_init_phy_params_82541().
01953 { 01954 struct e1000_phy_info *phy = &hw->phy; 01955 s32 ret_val; 01956 u16 data; 01957 bool link; 01958 01959 DEBUGFUNC("e1000_get_phy_info_igp"); 01960 01961 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 01962 if (ret_val) 01963 goto out; 01964 01965 if (!link) { 01966 DEBUGOUT("Phy info is only valid if link is up\n"); 01967 ret_val = -E1000_ERR_CONFIG; 01968 goto out; 01969 } 01970 01971 phy->polarity_correction = true; 01972 01973 ret_val = e1000_check_polarity_igp(hw); 01974 if (ret_val) 01975 goto out; 01976 01977 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 01978 if (ret_val) 01979 goto out; 01980 01981 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 01982 01983 #if 0 01984 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 01985 IGP01E1000_PSSR_SPEED_1000MBPS) { 01986 ret_val = hw->phy.ops.get_cable_length(hw); 01987 if (ret_val) 01988 goto out; 01989 01990 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 01991 if (ret_val) 01992 goto out; 01993 01994 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 01995 ? e1000_1000t_rx_status_ok 01996 : e1000_1000t_rx_status_not_ok; 01997 01998 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 01999 ? e1000_1000t_rx_status_ok 02000 : e1000_1000t_rx_status_not_ok; 02001 } else { 02002 #endif 02003 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 02004 phy->local_rx = e1000_1000t_rx_status_undefined; 02005 phy->remote_rx = e1000_1000t_rx_status_undefined; 02006 #if 0 02007 } 02008 #endif 02009 02010 out: 02011 return ret_val; 02012 }
e1000_phy_sw_reset_generic - PHY software reset : pointer to the HW structure
Does a software reset of the PHY by reading the PHY control register and setting/write the control register reset bit to the PHY.
Definition at line 2021 of file e1000_phy.c.
References DEBUGFUNC, E1000_SUCCESS, MII_CR_RESET, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, usec_delay, and e1000_phy_operations::write_reg.
Referenced by e1000_init_phy_params_82540(), and e1000_init_phy_params_82543().
02022 { 02023 s32 ret_val = E1000_SUCCESS; 02024 u16 phy_ctrl; 02025 02026 DEBUGFUNC("e1000_phy_sw_reset_generic"); 02027 02028 if (!(hw->phy.ops.read_reg)) 02029 goto out; 02030 02031 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 02032 if (ret_val) 02033 goto out; 02034 02035 phy_ctrl |= MII_CR_RESET; 02036 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 02037 if (ret_val) 02038 goto out; 02039 02040 usec_delay(1); 02041 02042 out: 02043 return ret_val; 02044 }
e1000_phy_hw_reset_generic - PHY hardware reset : pointer to the HW structure
Verify the reset block is not blocking us from resetting. Acquire semaphore (if necessary) and read/set/write the device control reset bit in the PHY. Wait the appropriate delay time for the device to reset and release the semaphore (if necessary).
Definition at line 2055 of file e1000_phy.c.
References e1000_phy_operations::acquire, e1000_phy_operations::check_reset_block, DEBUGFUNC, E1000_CTRL, E1000_CTRL_PHY_RST, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_FLUSH, E1000_WRITE_REG, e1000_phy_operations::get_cfg_done, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::release, e1000_phy_info::reset_delay_us, u32, and usec_delay.
Referenced by e1000_init_phy_params_82540(), e1000_init_phy_params_82543(), and e1000_phy_hw_reset_82541().
02056 { 02057 struct e1000_phy_info *phy = &hw->phy; 02058 s32 ret_val = E1000_SUCCESS; 02059 u32 ctrl; 02060 02061 DEBUGFUNC("e1000_phy_hw_reset_generic"); 02062 02063 ret_val = phy->ops.check_reset_block(hw); 02064 if (ret_val) { 02065 ret_val = E1000_SUCCESS; 02066 goto out; 02067 } 02068 02069 ret_val = phy->ops.acquire(hw); 02070 if (ret_val) 02071 goto out; 02072 02073 ctrl = E1000_READ_REG(hw, E1000_CTRL); 02074 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 02075 E1000_WRITE_FLUSH(hw); 02076 02077 usec_delay(phy->reset_delay_us); 02078 02079 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 02080 E1000_WRITE_FLUSH(hw); 02081 02082 usec_delay(150); 02083 02084 phy->ops.release(hw); 02085 02086 ret_val = phy->ops.get_cfg_done(hw); 02087 02088 out: 02089 return ret_val; 02090 }
e1000_get_cfg_done_generic - Generic configuration done : pointer to the HW structure
Generic function to wait 10 milli-seconds for configuration to complete and return success.
Definition at line 2099 of file e1000_phy.c.
References DEBUGFUNC, E1000_SUCCESS, and msec_delay_irq.
Referenced by e1000_init_phy_params_82540(), e1000_init_phy_params_82541(), and e1000_init_phy_params_82543().
02100 { 02101 DEBUGFUNC("e1000_get_cfg_done_generic"); 02102 02103 msec_delay_irq(10); 02104 02105 return E1000_SUCCESS; 02106 }
e1000_phy_init_script_igp3 - Inits the IGP3 PHY : pointer to the HW structure
Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
Definition at line 2114 of file e1000_phy.c.
References DEBUGOUT, E1000_SUCCESS, e1000_phy_info::ops, e1000_hw::phy, and e1000_phy_operations::write_reg.
02115 { 02116 DEBUGOUT("Running IGP 3 PHY init script\n"); 02117 02118 /* PHY init IGP 3 */ 02119 /* Enable rise/fall, 10-mode work in class-A */ 02120 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 02121 /* Remove all caps from Replica path filter */ 02122 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 02123 /* Bias trimming for ADC, AFE and Driver (Default) */ 02124 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 02125 /* Increase Hybrid poly bias */ 02126 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 02127 /* Add 4% to Tx amplitude in Gig mode */ 02128 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 02129 /* Disable trimming (TTT) */ 02130 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 02131 /* Poly DC correction to 94.6% + 2% for all channels */ 02132 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 02133 /* ABS DC correction to 95.9% */ 02134 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 02135 /* BG temp curve trim */ 02136 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 02137 /* Increasing ADC OPAMP stage 1 currents to max */ 02138 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 02139 /* Force 1000 ( required for enabling PHY regs configuration) */ 02140 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 02141 /* Set upd_freq to 6 */ 02142 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 02143 /* Disable NPDFE */ 02144 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 02145 /* Disable adaptive fixed FFE (Default) */ 02146 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 02147 /* Enable FFE hysteresis */ 02148 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 02149 /* Fixed FFE for short cable lengths */ 02150 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 02151 /* Fixed FFE for medium cable lengths */ 02152 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 02153 /* Fixed FFE for long cable lengths */ 02154 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 02155 /* Enable Adaptive Clip Threshold */ 02156 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 02157 /* AHT reset limit to 1 */ 02158 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 02159 /* Set AHT master delay to 127 msec */ 02160 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 02161 /* Set scan bits for AHT */ 02162 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 02163 /* Set AHT Preset bits */ 02164 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 02165 /* Change integ_factor of channel A to 3 */ 02166 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 02167 /* Change prop_factor of channels BCD to 8 */ 02168 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 02169 /* Change cg_icount + enable integbp for channels BCD */ 02170 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 02171 /* 02172 * Change cg_icount + enable integbp + change prop_factor_master 02173 * to 8 for channel A 02174 */ 02175 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 02176 /* Disable AHT in Slave mode on channel A */ 02177 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 02178 /* 02179 * Enable LPLU and disable AN to 1000 in non-D0a states, 02180 * Enable SPD+B2B 02181 */ 02182 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 02183 /* Enable restart AN on an1000_dis change */ 02184 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 02185 /* Enable wh_fifo read clock in 10/100 modes */ 02186 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 02187 /* Restart AN, Speed selection is 1000 */ 02188 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 02189 02190 return E1000_SUCCESS; 02191 }
| enum e1000_phy_type e1000_get_phy_type_from_id | ( | u32 | phy_id | ) |
e1000_get_phy_type_from_id - Get PHY type from id : phy_id read from the phy
Returns the phy type from the id.
Definition at line 2199 of file e1000_phy.c.
References e1000_phy_gg82563, e1000_phy_ife, e1000_phy_igp_2, e1000_phy_igp_3, e1000_phy_m88, e1000_phy_unknown, GG82563_E_PHY_ID, IFE_C_E_PHY_ID, IFE_E_PHY_ID, IFE_PLUS_E_PHY_ID, IGP01E1000_I_PHY_ID, IGP03E1000_E_PHY_ID, M88E1000_E_PHY_ID, M88E1000_I_PHY_ID, M88E1011_I_PHY_ID, and M88E1111_I_PHY_ID.
Referenced by e1000_determine_phy_address().
02200 { 02201 enum e1000_phy_type phy_type = e1000_phy_unknown; 02202 02203 switch (phy_id) { 02204 case M88E1000_I_PHY_ID: 02205 case M88E1000_E_PHY_ID: 02206 case M88E1111_I_PHY_ID: 02207 case M88E1011_I_PHY_ID: 02208 phy_type = e1000_phy_m88; 02209 break; 02210 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 02211 phy_type = e1000_phy_igp_2; 02212 break; 02213 case GG82563_E_PHY_ID: 02214 phy_type = e1000_phy_gg82563; 02215 break; 02216 case IGP03E1000_E_PHY_ID: 02217 phy_type = e1000_phy_igp_3; 02218 break; 02219 case IFE_E_PHY_ID: 02220 case IFE_PLUS_E_PHY_ID: 02221 case IFE_C_E_PHY_ID: 02222 phy_type = e1000_phy_ife; 02223 break; 02224 default: 02225 phy_type = e1000_phy_unknown; 02226 break; 02227 } 02228 return phy_type; 02229 }
e1000_determine_phy_address - Determines PHY address.
: pointer to the HW structure
This uses a trial and error method to loop through possible PHY addresses. It tests each by reading the PHY ID registers and checking for a match.
Definition at line 2239 of file e1000_phy.c.
References e1000_phy_info::addr, E1000_ERR_PHY_TYPE, e1000_get_phy_id(), e1000_get_phy_type_from_id(), E1000_MAX_PHY_ADDR, e1000_phy_unknown, E1000_SUCCESS, e1000_phy_info::id, msec_delay, e1000_hw::phy, and u32.
02240 { 02241 s32 ret_val = -E1000_ERR_PHY_TYPE; 02242 u32 phy_addr = 0; 02243 u32 i; 02244 enum e1000_phy_type phy_type = e1000_phy_unknown; 02245 02246 hw->phy.id = phy_type; 02247 02248 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 02249 hw->phy.addr = phy_addr; 02250 i = 0; 02251 02252 do { 02253 e1000_get_phy_id(hw); 02254 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 02255 02256 /* 02257 * If phy_type is valid, break - we found our 02258 * PHY address 02259 */ 02260 if (phy_type != e1000_phy_unknown) { 02261 ret_val = E1000_SUCCESS; 02262 goto out; 02263 } 02264 msec_delay(1); 02265 i++; 02266 } while (i < 10); 02267 } 02268 02269 out: 02270 return ret_val; 02271 }
| void e1000_power_up_phy_copper | ( | struct e1000_hw * | hw | ) |
e1000_power_up_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, restore the link to previous settings.
Definition at line 2281 of file e1000_phy.c.
References MII_CR_POWER_DOWN, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, and e1000_phy_operations::write_reg.
Referenced by e1000_init_phy_params_82540(), e1000_init_phy_params_82541(), and e1000_init_phy_params_82543().
02282 { 02283 u16 mii_reg = 0; 02284 02285 /* The PHY will retain its settings across a power down/up cycle */ 02286 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 02287 mii_reg &= ~MII_CR_POWER_DOWN; 02288 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 02289 }
| void e1000_power_down_phy_copper | ( | struct e1000_hw * | hw | ) |
e1000_power_down_phy_copper - Restore copper link in case of PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, restore the link to previous settings.
Definition at line 2299 of file e1000_phy.c.
References MII_CR_POWER_DOWN, msec_delay, e1000_phy_info::ops, e1000_hw::phy, PHY_CONTROL, e1000_phy_operations::read_reg, u16, and e1000_phy_operations::write_reg.
Referenced by e1000_init_phy_params_82543(), e1000_power_down_phy_copper_82540(), and e1000_power_down_phy_copper_82541().
02300 { 02301 u16 mii_reg = 0; 02302 02303 /* The PHY will retain its settings across a power down/up cycle */ 02304 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 02305 mii_reg |= MII_CR_POWER_DOWN; 02306 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 02307 msec_delay(1); 02308 }
1.5.7.1