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00032 FILE_LICENCE ( GPL2_ONLY );
00033
00034 #include "e1000.h"
00035
00036
00037
00038
00039
00040
00041 static void e1000_irq_disable ( struct e1000_adapter *adapter )
00042 {
00043 E1000_WRITE_REG ( &adapter->hw, E1000_IMC, ~0 );
00044 E1000_WRITE_FLUSH ( &adapter->hw );
00045 }
00046
00047
00048
00049
00050
00051
00052 static void e1000_irq_enable ( struct e1000_adapter *adapter )
00053 {
00054 E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
00055 E1000_WRITE_FLUSH(&adapter->hw);
00056 }
00057
00058
00059
00060
00061
00062
00063
00064
00065
00066 static int e1000_sw_init(struct e1000_adapter *adapter)
00067 {
00068 struct e1000_hw *hw = &adapter->hw;
00069 struct pci_device *pdev = adapter->pdev;
00070
00071
00072
00073 hw->vendor_id = pdev->vendor;
00074 hw->device_id = pdev->device;
00075
00076 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &hw->subsystem_vendor_id);
00077 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_device_id);
00078
00079 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
00080
00081 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
00082
00083 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
00084 adapter->max_frame_size = MAXIMUM_ETHERNET_VLAN_SIZE +
00085 ETH_HLEN + ETH_FCS_LEN;
00086 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
00087
00088 hw->fc.requested_mode = e1000_fc_none;
00089
00090
00091 if (e1000_setup_init_funcs(hw, false)) {
00092 DBG ("Hardware Initialization Failure\n");
00093 return -EIO;
00094 }
00095
00096
00097 e1000_irq_disable ( adapter );
00098
00099 return 0;
00100 }
00101
00102 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
00103 {
00104 struct e1000_adapter *adapter = hw->back;
00105 uint16_t cap_offset;
00106
00107 #define PCI_CAP_ID_EXP 0x10
00108 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
00109 if (!cap_offset)
00110 return -E1000_ERR_CONFIG;
00111
00112 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
00113
00114 return 0;
00115 }
00116
00117 void e1000_pci_clear_mwi ( struct e1000_hw *hw )
00118 {
00119 struct e1000_adapter *adapter = hw->back;
00120
00121 pci_write_config_word ( adapter->pdev, PCI_COMMAND,
00122 hw->bus.pci_cmd_word & ~PCI_COMMAND_INVALIDATE );
00123 }
00124
00125 void e1000_pci_set_mwi ( struct e1000_hw *hw )
00126 {
00127 struct e1000_adapter *adapter = hw->back;
00128
00129 pci_write_config_word ( adapter->pdev, PCI_COMMAND,
00130 hw->bus.pci_cmd_word );
00131 }
00132
00133 void e1000_read_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
00134 {
00135 struct e1000_adapter *adapter = hw->back;
00136
00137 pci_read_config_word ( adapter->pdev, reg, value );
00138 }
00139
00140 void e1000_write_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
00141 {
00142 struct e1000_adapter *adapter = hw->back;
00143
00144 pci_write_config_word ( adapter->pdev, reg, *value );
00145 }
00146
00147
00148
00149
00150
00151
00152 static void e1000_init_manageability ( struct e1000_adapter *adapter )
00153 {
00154 if (adapter->en_mng_pt) {
00155 u32 manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
00156
00157
00158 manc &= ~(E1000_MANC_ARP_EN);
00159
00160 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
00161 }
00162 }
00163
00164
00165
00166
00167
00168
00169
00170
00171 static int e1000_setup_tx_resources ( struct e1000_adapter *adapter )
00172 {
00173 DBG ( "e1000_setup_tx_resources\n" );
00174
00175
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185 adapter->tx_base =
00186 malloc_dma ( adapter->tx_ring_size, adapter->tx_ring_size );
00187
00188 if ( ! adapter->tx_base ) {
00189 return -ENOMEM;
00190 }
00191
00192 memset ( adapter->tx_base, 0, adapter->tx_ring_size );
00193
00194 DBG ( "adapter->tx_base = %#08lx\n", virt_to_bus ( adapter->tx_base ) );
00195
00196 return 0;
00197 }
00198
00199
00200
00201
00202
00203
00204 static void e1000_process_tx_packets ( struct net_device *netdev )
00205 {
00206 struct e1000_adapter *adapter = netdev_priv ( netdev );
00207 uint32_t i;
00208 uint32_t tx_status;
00209 struct e1000_tx_desc *tx_curr_desc;
00210
00211
00212
00213 while ( ( i = adapter->tx_head ) != adapter->tx_tail ) {
00214
00215 tx_curr_desc = ( void * ) ( adapter->tx_base ) +
00216 ( i * sizeof ( *adapter->tx_base ) );
00217
00218 tx_status = tx_curr_desc->upper.data;
00219
00220
00221 if ( ! ( tx_status & E1000_TXD_STAT_DD ) )
00222 break;
00223
00224 DBG ( "Sent packet. tx_head: %d tx_tail: %d tx_status: %#08x\n",
00225 adapter->tx_head, adapter->tx_tail, tx_status );
00226
00227 if ( tx_status & ( E1000_TXD_STAT_EC | E1000_TXD_STAT_LC |
00228 E1000_TXD_STAT_TU ) ) {
00229 netdev_tx_complete_err ( netdev, adapter->tx_iobuf[i], -EINVAL );
00230 DBG ( "Error transmitting packet, tx_status: %#08x\n",
00231 tx_status );
00232 } else {
00233 netdev_tx_complete ( netdev, adapter->tx_iobuf[i] );
00234 DBG ( "Success transmitting packet, tx_status: %#08x\n",
00235 tx_status );
00236 }
00237
00238
00239
00240 adapter->tx_fill_ctr--;
00241 memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) );
00242
00243 adapter->tx_head = ( adapter->tx_head + 1 ) % NUM_TX_DESC;
00244 }
00245 }
00246
00247 static void e1000_free_tx_resources ( struct e1000_adapter *adapter )
00248 {
00249 DBG ( "e1000_free_tx_resources\n" );
00250
00251 free_dma ( adapter->tx_base, adapter->tx_ring_size );
00252 }
00253
00254
00255
00256
00257
00258
00259
00260 static void e1000_configure_tx ( struct e1000_adapter *adapter )
00261 {
00262 struct e1000_hw *hw = &adapter->hw;
00263 uint32_t tctl;
00264
00265 DBG ( "e1000_configure_tx\n" );
00266
00267 E1000_WRITE_REG ( hw, E1000_TDBAH(0), 0 );
00268 E1000_WRITE_REG ( hw, E1000_TDBAL(0), virt_to_bus ( adapter->tx_base ) );
00269 E1000_WRITE_REG ( hw, E1000_TDLEN(0), adapter->tx_ring_size );
00270
00271 DBG ( "E1000_TDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_TDBAL(0) ) );
00272 DBG ( "E1000_TDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_TDLEN(0) ) );
00273
00274
00275 E1000_WRITE_REG ( hw, E1000_TDH(0), 0 );
00276 E1000_WRITE_REG ( hw, E1000_TDT(0), 0 );
00277
00278 adapter->tx_head = 0;
00279 adapter->tx_tail = 0;
00280 adapter->tx_fill_ctr = 0;
00281
00282
00283 tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
00284 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
00285 (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
00286
00287 e1000_config_collision_dist ( hw );
00288
00289 E1000_WRITE_REG ( hw, E1000_TCTL, tctl );
00290 E1000_WRITE_FLUSH ( hw );
00291 }
00292
00293 static void e1000_free_rx_resources ( struct e1000_adapter *adapter )
00294 {
00295 int i;
00296
00297 DBG ( "e1000_free_rx_resources\n" );
00298
00299 free_dma ( adapter->rx_base, adapter->rx_ring_size );
00300
00301 for ( i = 0; i < NUM_RX_DESC; i++ ) {
00302 free_iob ( adapter->rx_iobuf[i] );
00303 }
00304 }
00305
00306
00307
00308
00309
00310
00311
00312
00313 static int e1000_refill_rx_ring ( struct e1000_adapter *adapter )
00314 {
00315 int i, rx_curr;
00316 int rc = 0;
00317 struct e1000_rx_desc *rx_curr_desc;
00318 struct e1000_hw *hw = &adapter->hw;
00319 struct io_buffer *iob;
00320
00321 DBG ("e1000_refill_rx_ring\n");
00322
00323 for ( i = 0; i < NUM_RX_DESC; i++ ) {
00324 rx_curr = ( ( adapter->rx_curr + i ) % NUM_RX_DESC );
00325 rx_curr_desc = adapter->rx_base + rx_curr;
00326
00327 if ( rx_curr_desc->status & E1000_RXD_STAT_DD )
00328 continue;
00329
00330 if ( adapter->rx_iobuf[rx_curr] != NULL )
00331 continue;
00332
00333 DBG2 ( "Refilling rx desc %d\n", rx_curr );
00334
00335 iob = alloc_iob ( MAXIMUM_ETHERNET_VLAN_SIZE );
00336 adapter->rx_iobuf[rx_curr] = iob;
00337
00338 if ( ! iob ) {
00339 DBG ( "alloc_iob failed\n" );
00340 rc = -ENOMEM;
00341 break;
00342 } else {
00343 rx_curr_desc->buffer_addr = virt_to_bus ( iob->data );
00344
00345 E1000_WRITE_REG ( hw, E1000_RDT(0), rx_curr );
00346 }
00347 }
00348 return rc;
00349 }
00350
00351
00352
00353
00354
00355
00356
00357
00358 static int e1000_setup_rx_resources ( struct e1000_adapter *adapter )
00359 {
00360 int i, rc = 0;
00361
00362 DBG ( "e1000_setup_rx_resources\n" );
00363
00364
00365
00366
00367
00368 adapter->rx_base =
00369 malloc_dma ( adapter->rx_ring_size, adapter->rx_ring_size );
00370
00371 if ( ! adapter->rx_base ) {
00372 return -ENOMEM;
00373 }
00374 memset ( adapter->rx_base, 0, adapter->rx_ring_size );
00375
00376 for ( i = 0; i < NUM_RX_DESC; i++ ) {
00377
00378 adapter->rx_iobuf[i] = NULL;
00379 }
00380
00381
00382 rc = e1000_refill_rx_ring ( adapter );
00383 if ( rc < 0 )
00384 e1000_free_rx_resources ( adapter );
00385
00386 return rc;
00387 }
00388
00389
00390
00391
00392
00393
00394
00395 static void e1000_configure_rx ( struct e1000_adapter *adapter )
00396 {
00397 struct e1000_hw *hw = &adapter->hw;
00398 uint32_t rctl;
00399
00400 DBG ( "e1000_configure_rx\n" );
00401
00402
00403 rctl = E1000_READ_REG ( hw, E1000_RCTL );
00404 E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );
00405 E1000_WRITE_FLUSH ( hw );
00406 mdelay(10);
00407
00408 adapter->rx_curr = 0;
00409
00410
00411
00412
00413 E1000_WRITE_REG ( hw, E1000_RDBAL(0), virt_to_bus ( adapter->rx_base ) );
00414 E1000_WRITE_REG ( hw, E1000_RDBAH(0), 0 );
00415 E1000_WRITE_REG ( hw, E1000_RDLEN(0), adapter->rx_ring_size );
00416
00417 E1000_WRITE_REG ( hw, E1000_RDH(0), 0 );
00418 E1000_WRITE_REG ( hw, E1000_RDT(0), NUM_RX_DESC - 1 );
00419
00420
00421 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
00422 E1000_RCTL_MPE;
00423 E1000_WRITE_REG ( hw, E1000_RCTL, rctl );
00424 E1000_WRITE_FLUSH ( hw );
00425
00426 DBG ( "E1000_RDBAL(0): %#08x\n", E1000_READ_REG ( hw, E1000_RDBAL(0) ) );
00427 DBG ( "E1000_RDLEN(0): %d\n", E1000_READ_REG ( hw, E1000_RDLEN(0) ) );
00428 DBG ( "E1000_RCTL: %#08x\n", E1000_READ_REG ( hw, E1000_RCTL ) );
00429 }
00430
00431
00432
00433
00434
00435
00436 static void e1000_process_rx_packets ( struct net_device *netdev )
00437 {
00438 struct e1000_adapter *adapter = netdev_priv ( netdev );
00439 uint32_t i;
00440 uint32_t rx_status;
00441 uint32_t rx_len;
00442 uint32_t rx_err;
00443 struct e1000_rx_desc *rx_curr_desc;
00444
00445
00446
00447 while ( 1 ) {
00448
00449 i = adapter->rx_curr;
00450
00451 rx_curr_desc = ( void * ) ( adapter->rx_base ) +
00452 ( i * sizeof ( *adapter->rx_base ) );
00453 rx_status = rx_curr_desc->status;
00454
00455 DBG2 ( "Before DD Check RX_status: %#08x\n", rx_status );
00456
00457 if ( ! ( rx_status & E1000_RXD_STAT_DD ) )
00458 break;
00459
00460 if ( adapter->rx_iobuf[i] == NULL )
00461 break;
00462
00463 DBG ( "E1000_RCTL = %#08x\n", E1000_READ_REG ( &adapter->hw, E1000_RCTL ) );
00464
00465 rx_len = rx_curr_desc->length;
00466
00467 DBG ( "Received packet, rx_curr: %d rx_status: %#08x rx_len: %d\n",
00468 i, rx_status, rx_len );
00469
00470 rx_err = rx_curr_desc->errors;
00471
00472 iob_put ( adapter->rx_iobuf[i], rx_len );
00473
00474 if ( rx_err & E1000_RXD_ERR_FRAME_ERR_MASK ) {
00475
00476 netdev_rx_err ( netdev, adapter->rx_iobuf[i], -EINVAL );
00477 DBG ( "e1000_poll: Corrupted packet received!"
00478 " rx_err: %#08x\n", rx_err );
00479 } else {
00480
00481 netdev_rx ( netdev, adapter->rx_iobuf[i] );
00482 }
00483 adapter->rx_iobuf[i] = NULL;
00484
00485 memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) );
00486
00487 adapter->rx_curr = ( adapter->rx_curr + 1 ) % NUM_RX_DESC;
00488 }
00489 }
00490
00491
00492
00493
00494
00495
00496 void e1000_reset ( struct e1000_adapter *adapter )
00497 {
00498 struct e1000_mac_info *mac = &adapter->hw.mac;
00499 u32 pba = 0;
00500
00501 DBG ( "e1000_reset\n" );
00502
00503 switch (mac->type) {
00504 case e1000_82542:
00505 case e1000_82543:
00506 case e1000_82544:
00507 case e1000_82540:
00508 case e1000_82541:
00509 case e1000_82541_rev_2:
00510 pba = E1000_PBA_48K;
00511 break;
00512 case e1000_82545:
00513 case e1000_82545_rev_3:
00514 case e1000_82546:
00515 case e1000_82546_rev_3:
00516 pba = E1000_PBA_48K;
00517 break;
00518 case e1000_82547:
00519 case e1000_82547_rev_2:
00520 pba = E1000_PBA_30K;
00521 break;
00522 case e1000_undefined:
00523 case e1000_num_macs:
00524 break;
00525 }
00526
00527 E1000_WRITE_REG ( &adapter->hw, E1000_PBA, pba );
00528
00529
00530 e1000_reset_hw ( &adapter->hw );
00531
00532 if ( mac->type >= e1000_82544 )
00533 E1000_WRITE_REG ( &adapter->hw, E1000_WUC, 0 );
00534
00535 if ( e1000_init_hw ( &adapter->hw ) )
00536 DBG ( "Hardware Error\n" );
00537
00538 e1000_reset_adaptive ( &adapter->hw );
00539 e1000_get_phy_info ( &adapter->hw );
00540
00541 e1000_init_manageability ( adapter );
00542 }
00543
00544
00545
00546
00547
00548
00549
00550
00551
00552 static void e1000_close ( struct net_device *netdev )
00553 {
00554 struct e1000_adapter *adapter = netdev_priv ( netdev );
00555 struct e1000_hw *hw = &adapter->hw;
00556 uint32_t rctl;
00557 uint32_t icr;
00558
00559 DBG ( "e1000_close\n" );
00560
00561
00562 icr = E1000_READ_REG ( hw, E1000_ICR );
00563
00564 e1000_irq_disable ( adapter );
00565
00566
00567 rctl = E1000_READ_REG ( hw, E1000_RCTL );
00568 E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );
00569 E1000_WRITE_FLUSH ( hw );
00570
00571 e1000_reset_hw ( hw );
00572
00573 e1000_free_tx_resources ( adapter );
00574 e1000_free_rx_resources ( adapter );
00575 }
00576
00577
00578
00579
00580
00581
00582
00583
00584
00585 static int e1000_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
00586 {
00587 struct e1000_adapter *adapter = netdev_priv( netdev );
00588 struct e1000_hw *hw = &adapter->hw;
00589 uint32_t tx_curr = adapter->tx_tail;
00590 struct e1000_tx_desc *tx_curr_desc;
00591
00592 DBG ("e1000_transmit\n");
00593
00594 if ( adapter->tx_fill_ctr == NUM_TX_DESC ) {
00595 DBG ("TX overflow\n");
00596 return -ENOBUFS;
00597 }
00598
00599
00600
00601
00602 adapter->tx_iobuf[tx_curr] = iobuf;
00603
00604 tx_curr_desc = ( void * ) ( adapter->tx_base ) +
00605 ( tx_curr * sizeof ( *adapter->tx_base ) );
00606
00607 DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) );
00608 DBG ( "tx_curr_desc + 16 = %#08lx\n", virt_to_bus ( tx_curr_desc ) + 16 );
00609 DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) );
00610
00611
00612
00613 tx_curr_desc->buffer_addr =
00614 virt_to_bus ( iobuf->data );
00615 tx_curr_desc->lower.data =
00616 E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP |
00617 E1000_TXD_CMD_IFCS | iob_len ( iobuf );
00618 tx_curr_desc->upper.data = 0;
00619
00620 DBG ( "TX fill: %d tx_curr: %d addr: %#08lx len: %zd\n", adapter->tx_fill_ctr,
00621 tx_curr, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) );
00622
00623
00624 adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC;
00625 adapter->tx_fill_ctr++;
00626
00627
00628
00629 wmb();
00630 E1000_WRITE_REG ( hw, E1000_TDT(0), adapter->tx_tail );
00631
00632 return 0;
00633 }
00634
00635
00636
00637
00638
00639
00640 static void e1000_poll ( struct net_device *netdev )
00641 {
00642 struct e1000_adapter *adapter = netdev_priv( netdev );
00643 struct e1000_hw *hw = &adapter->hw;
00644
00645 uint32_t icr;
00646
00647 DBGP ( "e1000_poll\n" );
00648
00649
00650 icr = E1000_READ_REG ( hw, E1000_ICR );
00651 if ( ! icr )
00652 return;
00653
00654 DBG ( "e1000_poll: intr_status = %#08x\n", icr );
00655
00656 e1000_process_tx_packets ( netdev );
00657
00658 e1000_process_rx_packets ( netdev );
00659
00660 e1000_refill_rx_ring(adapter);
00661 }
00662
00663
00664
00665
00666
00667
00668
00669 static void e1000_irq ( struct net_device *netdev, int enable )
00670 {
00671 struct e1000_adapter *adapter = netdev_priv ( netdev );
00672
00673 DBG ( "e1000_irq\n" );
00674
00675 if ( enable ) {
00676 e1000_irq_enable ( adapter );
00677 } else {
00678 e1000_irq_disable ( adapter );
00679 }
00680 }
00681
00682 static struct net_device_operations e1000_operations;
00683
00684
00685
00686
00687
00688
00689
00690
00691
00692 int e1000_probe ( struct pci_device *pdev,
00693 const struct pci_device_id *id __unused )
00694 {
00695 int i, err;
00696 struct net_device *netdev;
00697 struct e1000_adapter *adapter;
00698 unsigned long mmio_start, mmio_len;
00699
00700 DBG ( "e1000_probe\n" );
00701
00702 err = -ENOMEM;
00703
00704
00705
00706 netdev = alloc_etherdev ( sizeof ( struct e1000_adapter ) );
00707 if ( ! netdev )
00708 goto err_alloc_etherdev;
00709
00710
00711
00712 netdev_init ( netdev, &e1000_operations );
00713
00714
00715 pci_set_drvdata ( pdev, netdev );
00716 netdev->dev = &pdev->dev;
00717
00718
00719 adapter = netdev_priv ( netdev );
00720 memset ( adapter, 0, ( sizeof ( *adapter ) ) );
00721
00722 adapter->pdev = pdev;
00723
00724 adapter->ioaddr = pdev->ioaddr;
00725 adapter->hw.io_base = pdev->ioaddr;
00726
00727 adapter->irqno = pdev->irq;
00728 adapter->netdev = netdev;
00729 adapter->hw.back = adapter;
00730
00731 adapter->tx_ring_size = sizeof ( *adapter->tx_base ) * NUM_TX_DESC;
00732 adapter->rx_ring_size = sizeof ( *adapter->rx_base ) * NUM_RX_DESC;
00733
00734 mmio_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_0 );
00735 mmio_len = pci_bar_size ( pdev, PCI_BASE_ADDRESS_0 );
00736
00737 DBG ( "mmio_start: %#08lx\n", mmio_start );
00738 DBG ( "mmio_len: %#08lx\n", mmio_len );
00739
00740
00741 adjust_pci_device ( pdev );
00742
00743 err = -EIO;
00744
00745 adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len );
00746 DBG ( "adapter->hw.hw_addr: %p\n", adapter->hw.hw_addr );
00747
00748 if ( ! adapter->hw.hw_addr )
00749 goto err_ioremap;
00750
00751
00752 if (adapter->hw.mac.type >= e1000_82540) {
00753 adapter->flags |= E1000_FLAG_HAS_SMBUS;
00754 adapter->flags |= E1000_FLAG_HAS_INTR_MODERATION;
00755 }
00756
00757 if (adapter->hw.mac.type == e1000_82543)
00758 adapter->flags |= E1000_FLAG_BAD_TX_CARRIER_STATS_FD;
00759
00760 adapter->hw.phy.autoneg_wait_to_complete = true;
00761 adapter->hw.mac.adaptive_ifs = true;
00762
00763
00764 if ( ( err = e1000_sw_init ( adapter ) ) )
00765 goto err_sw_init;
00766
00767 if ((err = e1000_init_mac_params(&adapter->hw)))
00768 goto err_hw_init;
00769
00770 if ((err = e1000_init_nvm_params(&adapter->hw)))
00771 goto err_hw_init;
00772
00773
00774 adapter->hw.mac.autoneg = 1;
00775
00776 if ((err = e1000_init_phy_params(&adapter->hw)))
00777 goto err_hw_init;
00778
00779 DBG ( "adapter->hw.mac.type: %#08x\n", adapter->hw.mac.type );
00780
00781
00782
00783
00784 err = e1000_reset_hw ( &adapter->hw );
00785 if ( err < 0 ) {
00786 DBG ( "Hardware Initialization Failed\n" );
00787 goto err_reset;
00788 }
00789
00790
00791 if ( e1000_validate_nvm_checksum(&adapter->hw) < 0 ) {
00792 DBG ( "The NVM Checksum Is Not Valid\n" );
00793 err = -EIO;
00794 goto err_eeprom;
00795 }
00796
00797
00798 if ( e1000_read_mac_addr ( &adapter->hw ) )
00799 DBG ( "EEPROM Read Error\n" );
00800
00801 memcpy ( netdev->hw_addr, adapter->hw.mac.perm_addr, ETH_ALEN );
00802
00803
00804 e1000_reset ( adapter );
00805
00806
00807 netdev_link_up ( netdev );
00808
00809 if ( ( err = register_netdev ( netdev ) ) != 0)
00810 goto err_register;
00811
00812 for (i = 0; i < 6; i++)
00813 DBG ("%02x%s", netdev->ll_addr[i], i == 5 ? "\n" : ":");
00814
00815 DBG ( "e1000_probe succeeded!\n" );
00816
00817
00818 return 0;
00819
00820
00821 err_reset:
00822 err_register:
00823 err_hw_init:
00824 err_eeprom:
00825 if (!e1000_check_reset_block(&adapter->hw))
00826 e1000_phy_hw_reset(&adapter->hw);
00827 if (adapter->hw.flash_address)
00828 iounmap(adapter->hw.flash_address);
00829 err_sw_init:
00830 iounmap ( adapter->hw.hw_addr );
00831 err_ioremap:
00832 netdev_put ( netdev );
00833 err_alloc_etherdev:
00834 return err;
00835 }
00836
00837
00838
00839
00840
00841
00842
00843 void e1000_remove ( struct pci_device *pdev )
00844 {
00845 struct net_device *netdev = pci_get_drvdata ( pdev );
00846 struct e1000_adapter *adapter = netdev_priv ( netdev );
00847
00848 DBG ( "e1000_remove\n" );
00849
00850 if ( adapter->hw.flash_address )
00851 iounmap ( adapter->hw.flash_address );
00852 if ( adapter->hw.hw_addr )
00853 iounmap ( adapter->hw.hw_addr );
00854
00855 unregister_netdev ( netdev );
00856 e1000_reset_hw ( &adapter->hw );
00857 netdev_nullify ( netdev );
00858 netdev_put ( netdev );
00859 }
00860
00861
00862
00863
00864
00865
00866
00867
00868 static int e1000_open ( struct net_device *netdev )
00869 {
00870 struct e1000_adapter *adapter = netdev_priv(netdev);
00871 int err;
00872
00873 DBG ( "e1000_open\n" );
00874
00875
00876 err = e1000_setup_tx_resources ( adapter );
00877 if ( err ) {
00878 DBG ( "Error setting up TX resources!\n" );
00879 goto err_setup_tx;
00880 }
00881
00882
00883 err = e1000_setup_rx_resources ( adapter );
00884 if ( err ) {
00885 DBG ( "Error setting up RX resources!\n" );
00886 goto err_setup_rx;
00887 }
00888
00889 e1000_configure_tx ( adapter );
00890
00891 e1000_configure_rx ( adapter );
00892
00893 DBG ( "E1000_RXDCTL(0): %#08x\n", E1000_READ_REG ( &adapter->hw, E1000_RXDCTL(0) ) );
00894
00895 return 0;
00896
00897 err_setup_rx:
00898 e1000_free_tx_resources ( adapter );
00899 err_setup_tx:
00900 e1000_reset ( adapter );
00901
00902 return err;
00903 }
00904
00905
00906 static struct net_device_operations e1000_operations = {
00907 .open = e1000_open,
00908 .close = e1000_close,
00909 .transmit = e1000_transmit,
00910 .poll = e1000_poll,
00911 .irq = e1000_irq,
00912 };