Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| void | e1000_init_mac_ops_generic (struct e1000_hw *hw) |
| e1000_init_mac_ops_generic - Initialize MAC function pointers : pointer to the HW structure | |
| void | e1000_null_mac_generic (struct e1000_hw *hw) |
| s32 | e1000_null_ops_generic (struct e1000_hw *hw) |
| s32 | e1000_null_link_info (struct e1000_hw *hw, u16 *s, u16 *d) |
| bool | e1000_null_mng_mode (struct e1000_hw *hw) |
| void | e1000_null_update_mc (struct e1000_hw *hw, u8 *h, u32 a) |
| void | e1000_null_write_vfta (struct e1000_hw *hw, u32 a, u32 b) |
| void | e1000_null_mta_set (struct e1000_hw *hw, u32 a) |
| void | e1000_null_rar_set (struct e1000_hw *hw, u8 *h, u32 a) |
| s32 | e1000_blink_led_generic (struct e1000_hw *hw) |
| s32 | e1000_check_for_copper_link_generic (struct e1000_hw *hw) |
| e1000_check_for_copper_link_generic - Check for link (Copper) : pointer to the HW structure | |
| s32 | e1000_check_for_fiber_link_generic (struct e1000_hw *hw) |
| e1000_check_for_fiber_link_generic - Check for link (Fiber) : pointer to the HW structure | |
| s32 | e1000_check_for_serdes_link_generic (struct e1000_hw *hw) |
| e1000_check_for_serdes_link_generic - Check for link (Serdes) : pointer to the HW structure | |
| s32 | e1000_cleanup_led_generic (struct e1000_hw *hw) |
| s32 | e1000_commit_fc_settings_generic (struct e1000_hw *hw) |
| e1000_commit_fc_settings_generic - Configure flow control : pointer to the HW structure | |
| s32 | e1000_poll_fiber_serdes_link_generic (struct e1000_hw *hw) |
| e1000_poll_fiber_serdes_link_generic - Poll for link up : pointer to the HW structure | |
| s32 | e1000_config_fc_after_link_up_generic (struct e1000_hw *hw) |
| e1000_config_fc_after_link_up_generic - Configures flow control after link : pointer to the HW structure | |
| s32 | e1000_disable_pcie_master_generic (struct e1000_hw *hw) |
| e1000_disable_pcie_master_generic - Disables PCI-express master access : pointer to the HW structure | |
| s32 | e1000_force_mac_fc_generic (struct e1000_hw *hw) |
| e1000_force_mac_fc_generic - Force the MAC's flow control settings : pointer to the HW structure | |
| s32 | e1000_get_auto_rd_done_generic (struct e1000_hw *hw) |
| e1000_get_auto_rd_done_generic - Check for auto read completion : pointer to the HW structure | |
| s32 | e1000_get_bus_info_pci_generic (struct e1000_hw *hw) |
| s32 | e1000_get_bus_info_pcie_generic (struct e1000_hw *hw) |
| void | e1000_set_lan_id_single_port (struct e1000_hw *hw) |
| e1000_set_lan_id_single_port - Set LAN id for a single port device : pointer to the HW structure | |
| void | e1000_set_lan_id_multi_port_pci (struct e1000_hw *hw) |
| e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices : pointer to the HW structure | |
| s32 | e1000_get_hw_semaphore_generic (struct e1000_hw *hw) |
| s32 | e1000_get_speed_and_duplex_copper_generic (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex | |
| s32 | e1000_get_speed_and_duplex_fiber_serdes_generic (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| s32 | e1000_id_led_init_generic (struct e1000_hw *hw) |
| s32 | e1000_led_on_generic (struct e1000_hw *hw) |
| s32 | e1000_led_off_generic (struct e1000_hw *hw) |
| void | e1000_update_mc_addr_list_generic (struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count) |
| e1000_update_mc_addr_list_generic - Update Multicast addresses : pointer to the HW structure : array of multicast addresses to program : number of multicast addresses to program | |
| s32 | e1000_set_default_fc_generic (struct e1000_hw *hw) |
| e1000_set_default_fc_generic - Set flow control default values : pointer to the HW structure | |
| s32 | e1000_set_fc_watermarks_generic (struct e1000_hw *hw) |
| e1000_set_fc_watermarks_generic - Set flow control high/low watermarks : pointer to the HW structure | |
| s32 | e1000_setup_fiber_serdes_link_generic (struct e1000_hw *hw) |
| e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes : pointer to the HW structure | |
| s32 | e1000_setup_led_generic (struct e1000_hw *hw) |
| s32 | e1000_setup_link_generic (struct e1000_hw *hw) |
| e1000_setup_link_generic - Setup flow control and link settings : pointer to the HW structure | |
| u32 | e1000_hash_mc_addr_generic (struct e1000_hw *hw, u8 *mc_addr) |
| e1000_hash_mc_addr_generic - Generate a multicast hash value : pointer to the HW structure : pointer to a multicast address | |
| void | e1000_clear_hw_cntrs_base_generic (struct e1000_hw *hw) |
| void | e1000_clear_vfta_generic (struct e1000_hw *hw) |
| e1000_clear_vfta_generic - Clear VLAN filter table : pointer to the HW structure | |
| void | e1000_config_collision_dist_generic (struct e1000_hw *hw) |
| e1000_config_collision_dist_generic - Configure collision distance : pointer to the HW structure | |
| void | e1000_init_rx_addrs_generic (struct e1000_hw *hw, u16 rar_count) |
| e1000_init_rx_addrs_generic - Initialize receive address's : pointer to the HW structure : receive address registers | |
| void | e1000_mta_set_generic (struct e1000_hw *hw, u32 hash_value) |
| e1000_mta_set_generic - Set multicast filter table address : pointer to the HW structure : determines the MTA register and bit to set | |
| void | e1000_pcix_mmrbc_workaround_generic (struct e1000_hw *hw) |
| e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value : pointer to the HW structure | |
| void | e1000_put_hw_semaphore_generic (struct e1000_hw *hw) |
| void | e1000_rar_set_generic (struct e1000_hw *hw, u8 *addr, u32 index) |
| e1000_rar_set_generic - Set receive address register : pointer to the HW structure : pointer to the receive address : receive address array register | |
| s32 | e1000_check_alt_mac_addr_generic (struct e1000_hw *hw) |
| e1000_check_alt_mac_addr_generic - Check for alternate MAC addr : pointer to the HW structure | |
| void | e1000_reset_adaptive_generic (struct e1000_hw *hw) |
| e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing : pointer to the HW structure | |
| void | e1000_set_pcie_no_snoop_generic (struct e1000_hw *hw, u32 no_snoop) |
| e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities : pointer to the HW structure : bitmap of snoop events | |
| void | e1000_update_adaptive_generic (struct e1000_hw *hw) |
| e1000_update_adaptive_generic - Update Adaptive Interframe Spacing : pointer to the HW structure | |
| void | e1000_write_vfta_generic (struct e1000_hw *hw, u32 offset, u32 value) |
| e1000_write_vfta_generic - Write value to VLAN filter table : pointer to the HW structure : register offset in VLAN filter table : register value written to VLAN filter table | |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
| void e1000_init_mac_ops_generic | ( | struct e1000_hw * | hw | ) |
e1000_init_mac_ops_generic - Initialize MAC function pointers : pointer to the HW structure
Setups up the function pointers to no-op functions
Definition at line 42 of file e1000_mac.c.
References e1000_mac_operations::blink_led, e1000_mac_operations::check_for_link, e1000_mac_operations::check_mng_mode, e1000_mac_operations::cleanup_led, e1000_mac_operations::clear_hw_cntrs, e1000_mac_operations::clear_vfta, e1000_mac_operations::config_collision_dist, DEBUGFUNC, e1000_config_collision_dist_generic(), e1000_mng_enable_host_if_generic(), e1000_mng_host_if_write_generic(), e1000_mng_write_cmd_header_generic(), e1000_null_link_info(), e1000_null_mac_generic(), e1000_null_mng_mode(), e1000_null_mta_set(), e1000_null_ops_generic(), e1000_null_update_mc(), e1000_null_write_vfta(), e1000_rar_set_generic(), e1000_read_mac_addr_generic(), e1000_set_lan_id_multi_port_pcie(), e1000_validate_mdi_setting_generic(), e1000_wait_autoneg_generic(), e1000_mac_operations::get_bus_info, e1000_mac_operations::get_link_up_info, e1000_mac_operations::init_hw, e1000_mac_operations::init_params, e1000_mac_operations::led_off, e1000_mac_operations::led_on, e1000_hw::mac, e1000_mac_operations::mng_enable_host_if, e1000_mac_operations::mng_host_if_write, e1000_mac_operations::mng_write_cmd_header, e1000_mac_operations::mta_set, e1000_mac_info::ops, e1000_mac_operations::rar_set, e1000_mac_operations::read_mac_addr, e1000_mac_operations::reset_hw, e1000_mac_operations::set_lan_id, e1000_mac_operations::setup_led, e1000_mac_operations::setup_link, e1000_mac_operations::setup_physical_interface, e1000_mac_operations::update_mc_addr_list, e1000_mac_operations::validate_mdi_setting, e1000_mac_operations::wait_autoneg, and e1000_mac_operations::write_vfta.
Referenced by e1000_setup_init_funcs().
00043 { 00044 struct e1000_mac_info *mac = &hw->mac; 00045 DEBUGFUNC("e1000_init_mac_ops_generic"); 00046 00047 /* General Setup */ 00048 mac->ops.init_params = e1000_null_ops_generic; 00049 mac->ops.init_hw = e1000_null_ops_generic; 00050 mac->ops.reset_hw = e1000_null_ops_generic; 00051 mac->ops.setup_physical_interface = e1000_null_ops_generic; 00052 mac->ops.get_bus_info = e1000_null_ops_generic; 00053 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 00054 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 00055 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 00056 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 00057 /* LED */ 00058 mac->ops.cleanup_led = e1000_null_ops_generic; 00059 mac->ops.setup_led = e1000_null_ops_generic; 00060 mac->ops.blink_led = e1000_null_ops_generic; 00061 mac->ops.led_on = e1000_null_ops_generic; 00062 mac->ops.led_off = e1000_null_ops_generic; 00063 /* LINK */ 00064 mac->ops.setup_link = e1000_null_ops_generic; 00065 mac->ops.get_link_up_info = e1000_null_link_info; 00066 mac->ops.check_for_link = e1000_null_ops_generic; 00067 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 00068 #if 0 00069 /* Management */ 00070 mac->ops.check_mng_mode = e1000_null_mng_mode; 00071 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 00072 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 00073 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 00074 #endif 00075 /* VLAN, MC, etc. */ 00076 mac->ops.update_mc_addr_list = e1000_null_update_mc; 00077 mac->ops.clear_vfta = e1000_null_mac_generic; 00078 mac->ops.write_vfta = e1000_null_write_vfta; 00079 mac->ops.mta_set = e1000_null_mta_set; 00080 mac->ops.rar_set = e1000_rar_set_generic; 00081 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 00082 }
| void e1000_null_mac_generic | ( | struct e1000_hw * | hw | ) |
e1000_check_for_copper_link_generic - Check for link (Copper) : pointer to the HW structure
Checks to see of the link status of the hardware has changed. If a change in link status has been detected, then we read the PHY registers to get the current speed/duplex if link exists.
Definition at line 730 of file e1000_mac.c.
References e1000_mac_info::autoneg, DEBUGFUNC, DEBUGOUT, e1000_check_downshift_generic(), e1000_config_collision_dist_generic(), e1000_config_fc_after_link_up_generic(), E1000_ERR_CONFIG, e1000_phy_has_link_generic(), E1000_SUCCESS, e1000_mac_info::get_link_status, and e1000_hw::mac.
Referenced by e1000_init_mac_params_82540().
00731 { 00732 struct e1000_mac_info *mac = &hw->mac; 00733 s32 ret_val; 00734 bool link; 00735 00736 DEBUGFUNC("e1000_check_for_copper_link"); 00737 00738 /* 00739 * We only want to go out to the PHY registers to see if Auto-Neg 00740 * has completed and/or if our link status has changed. The 00741 * get_link_status flag is set upon receiving a Link Status 00742 * Change or Rx Sequence Error interrupt. 00743 */ 00744 if (!mac->get_link_status) { 00745 ret_val = E1000_SUCCESS; 00746 goto out; 00747 } 00748 00749 /* 00750 * First we want to see if the MII Status Register reports 00751 * link. If so, then we want to get the current speed/duplex 00752 * of the PHY. 00753 */ 00754 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 00755 if (ret_val) 00756 goto out; 00757 00758 if (!link) 00759 goto out; /* No link detected */ 00760 00761 mac->get_link_status = false; 00762 00763 /* 00764 * Check if there was DownShift, must be checked 00765 * immediately after link-up 00766 */ 00767 e1000_check_downshift_generic(hw); 00768 00769 /* 00770 * If we are forcing speed/duplex, then we simply return since 00771 * we have already determined whether we have link or not. 00772 */ 00773 if (!mac->autoneg) { 00774 ret_val = -E1000_ERR_CONFIG; 00775 goto out; 00776 } 00777 00778 /* 00779 * Auto-Neg is enabled. Auto Speed Detection takes care 00780 * of MAC speed/duplex configuration. So we only need to 00781 * configure Collision Distance in the MAC. 00782 */ 00783 e1000_config_collision_dist_generic(hw); 00784 00785 /* 00786 * Configure Flow Control now that Auto-Neg has completed. 00787 * First, we need to restore the desired flow control 00788 * settings because we may have had to re-autoneg with a 00789 * different link partner. 00790 */ 00791 ret_val = e1000_config_fc_after_link_up_generic(hw); 00792 if (ret_val) 00793 DEBUGOUT("Error configuring flow control\n"); 00794 00795 out: 00796 return ret_val; 00797 }
e1000_check_for_fiber_link_generic - Check for link (Fiber) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 806 of file e1000_mac.c.
References e1000_mac_info::autoneg_failed, DEBUGFUNC, DEBUGOUT, e1000_config_fc_after_link_up_generic(), E1000_CTRL, E1000_CTRL_FD, E1000_CTRL_SLU, E1000_CTRL_SWDPIN1, E1000_READ_REG, E1000_RXCW, E1000_RXCW_C, E1000_STATUS, E1000_STATUS_LU, E1000_SUCCESS, E1000_TXCW, E1000_TXCW_ANE, E1000_WRITE_REG, e1000_hw::mac, e1000_mac_info::serdes_has_link, e1000_mac_info::txcw, and u32.
Referenced by e1000_init_mac_params_82540(), and e1000_init_mac_params_82542().
00807 { 00808 struct e1000_mac_info *mac = &hw->mac; 00809 u32 rxcw; 00810 u32 ctrl; 00811 u32 status; 00812 s32 ret_val = E1000_SUCCESS; 00813 00814 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 00815 00816 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00817 status = E1000_READ_REG(hw, E1000_STATUS); 00818 rxcw = E1000_READ_REG(hw, E1000_RXCW); 00819 00820 /* 00821 * If we don't have link (auto-negotiation failed or link partner 00822 * cannot auto-negotiate), the cable is plugged in (we have signal), 00823 * and our link partner is not trying to auto-negotiate with us (we 00824 * are receiving idles or data), we need to force link up. We also 00825 * need to give auto-negotiation time to complete, in case the cable 00826 * was just plugged in. The autoneg_failed flag does this. 00827 */ 00828 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 00829 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 00830 (!(rxcw & E1000_RXCW_C))) { 00831 if (mac->autoneg_failed == 0) { 00832 mac->autoneg_failed = 1; 00833 goto out; 00834 } 00835 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 00836 00837 /* Disable auto-negotiation in the TXCW register */ 00838 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 00839 00840 /* Force link-up and also force full-duplex. */ 00841 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00842 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 00843 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 00844 00845 /* Configure Flow Control after forcing link up. */ 00846 ret_val = e1000_config_fc_after_link_up_generic(hw); 00847 if (ret_val) { 00848 DEBUGOUT("Error configuring flow control\n"); 00849 goto out; 00850 } 00851 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 00852 /* 00853 * If we are forcing link and we are receiving /C/ ordered 00854 * sets, re-enable auto-negotiation in the TXCW register 00855 * and disable forced link in the Device Control register 00856 * in an attempt to auto-negotiate with our link partner. 00857 */ 00858 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 00859 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 00860 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 00861 00862 mac->serdes_has_link = true; 00863 } 00864 00865 out: 00866 return ret_val; 00867 }
e1000_check_for_serdes_link_generic - Check for link (Serdes) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 876 of file e1000_mac.c.
References e1000_mac_info::autoneg_failed, DEBUGFUNC, DEBUGOUT, e1000_config_fc_after_link_up_generic(), E1000_CTRL, E1000_CTRL_FD, E1000_CTRL_SLU, E1000_READ_REG, E1000_RXCW, E1000_RXCW_C, E1000_RXCW_IV, E1000_RXCW_SYNCH, E1000_STATUS, E1000_STATUS_LU, E1000_SUCCESS, E1000_TXCW, E1000_TXCW_ANE, E1000_WRITE_REG, e1000_hw::mac, e1000_mac_info::serdes_has_link, e1000_mac_info::txcw, u32, and usec_delay.
Referenced by e1000_init_mac_params_82540().
00877 { 00878 struct e1000_mac_info *mac = &hw->mac; 00879 u32 rxcw; 00880 u32 ctrl; 00881 u32 status; 00882 s32 ret_val = E1000_SUCCESS; 00883 00884 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 00885 00886 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00887 status = E1000_READ_REG(hw, E1000_STATUS); 00888 rxcw = E1000_READ_REG(hw, E1000_RXCW); 00889 00890 /* 00891 * If we don't have link (auto-negotiation failed or link partner 00892 * cannot auto-negotiate), and our link partner is not trying to 00893 * auto-negotiate with us (we are receiving idles or data), 00894 * we need to force link up. We also need to give auto-negotiation 00895 * time to complete. 00896 */ 00897 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 00898 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 00899 if (mac->autoneg_failed == 0) { 00900 mac->autoneg_failed = 1; 00901 goto out; 00902 } 00903 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 00904 00905 /* Disable auto-negotiation in the TXCW register */ 00906 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 00907 00908 /* Force link-up and also force full-duplex. */ 00909 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00910 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 00911 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 00912 00913 /* Configure Flow Control after forcing link up. */ 00914 ret_val = e1000_config_fc_after_link_up_generic(hw); 00915 if (ret_val) { 00916 DEBUGOUT("Error configuring flow control\n"); 00917 goto out; 00918 } 00919 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 00920 /* 00921 * If we are forcing link and we are receiving /C/ ordered 00922 * sets, re-enable auto-negotiation in the TXCW register 00923 * and disable forced link in the Device Control register 00924 * in an attempt to auto-negotiate with our link partner. 00925 */ 00926 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 00927 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 00928 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 00929 00930 mac->serdes_has_link = true; 00931 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 00932 /* 00933 * If we force link for non-auto-negotiation switch, check 00934 * link status based on MAC synchronization for internal 00935 * serdes media type. 00936 */ 00937 /* SYNCH bit and IV bit are sticky. */ 00938 usec_delay(10); 00939 rxcw = E1000_READ_REG(hw, E1000_RXCW); 00940 if (rxcw & E1000_RXCW_SYNCH) { 00941 if (!(rxcw & E1000_RXCW_IV)) { 00942 mac->serdes_has_link = true; 00943 DEBUGOUT("SERDES: Link up - forced.\n"); 00944 } 00945 } else { 00946 mac->serdes_has_link = false; 00947 DEBUGOUT("SERDES: Link down - force failed.\n"); 00948 } 00949 } 00950 00951 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 00952 status = E1000_READ_REG(hw, E1000_STATUS); 00953 if (status & E1000_STATUS_LU) { 00954 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 00955 usec_delay(10); 00956 rxcw = E1000_READ_REG(hw, E1000_RXCW); 00957 if (rxcw & E1000_RXCW_SYNCH) { 00958 if (!(rxcw & E1000_RXCW_IV)) { 00959 mac->serdes_has_link = true; 00960 DEBUGOUT("SERDES: Link up - autoneg " 00961 "completed sucessfully.\n"); 00962 } else { 00963 mac->serdes_has_link = false; 00964 DEBUGOUT("SERDES: Link down - invalid" 00965 "codewords detected in autoneg.\n"); 00966 } 00967 } else { 00968 mac->serdes_has_link = false; 00969 DEBUGOUT("SERDES: Link down - no sync.\n"); 00970 } 00971 } else { 00972 mac->serdes_has_link = false; 00973 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 00974 } 00975 } 00976 00977 out: 00978 return ret_val; 00979 }
e1000_commit_fc_settings_generic - Configure flow control : pointer to the HW structure
Write the flow control settings to the Transmit Config Word Register (TXCW) base on the flow control settings in e1000_mac_info.
Definition at line 1184 of file e1000_mac.c.
References e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, E1000_ERR_CONFIG, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, E1000_SUCCESS, E1000_TXCW, E1000_TXCW_ANE, E1000_TXCW_ASM_DIR, E1000_TXCW_FD, E1000_TXCW_PAUSE_MASK, E1000_WRITE_REG, e1000_hw::fc, e1000_hw::mac, e1000_mac_info::txcw, and u32.
Referenced by e1000_setup_fiber_link_82543(), and e1000_setup_fiber_serdes_link_generic().
01185 { 01186 struct e1000_mac_info *mac = &hw->mac; 01187 u32 txcw; 01188 s32 ret_val = E1000_SUCCESS; 01189 01190 DEBUGFUNC("e1000_commit_fc_settings_generic"); 01191 01192 /* 01193 * Check for a software override of the flow control settings, and 01194 * setup the device accordingly. If auto-negotiation is enabled, then 01195 * software will have to set the "PAUSE" bits to the correct value in 01196 * the Transmit Config Word Register (TXCW) and re-start auto- 01197 * negotiation. However, if auto-negotiation is disabled, then 01198 * software will have to manually configure the two flow control enable 01199 * bits in the CTRL register. 01200 * 01201 * The possible values of the "fc" parameter are: 01202 * 0: Flow control is completely disabled 01203 * 1: Rx flow control is enabled (we can receive pause frames, 01204 * but not send pause frames). 01205 * 2: Tx flow control is enabled (we can send pause frames but we 01206 * do not support receiving pause frames). 01207 * 3: Both Rx and Tx flow control (symmetric) are enabled. 01208 */ 01209 switch (hw->fc.current_mode) { 01210 case e1000_fc_none: 01211 /* Flow control completely disabled by a software over-ride. */ 01212 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 01213 break; 01214 case e1000_fc_rx_pause: 01215 /* 01216 * Rx Flow control is enabled and Tx Flow control is disabled 01217 * by a software over-ride. Since there really isn't a way to 01218 * advertise that we are capable of Rx Pause ONLY, we will 01219 * advertise that we support both symmetric and asymmetric RX 01220 * PAUSE. Later, we will disable the adapter's ability to send 01221 * PAUSE frames. 01222 */ 01223 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 01224 break; 01225 case e1000_fc_tx_pause: 01226 /* 01227 * Tx Flow control is enabled, and Rx Flow control is disabled, 01228 * by a software over-ride. 01229 */ 01230 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 01231 break; 01232 case e1000_fc_full: 01233 /* 01234 * Flow control (both Rx and Tx) is enabled by a software 01235 * over-ride. 01236 */ 01237 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 01238 break; 01239 default: 01240 DEBUGOUT("Flow control param set incorrectly\n"); 01241 ret_val = -E1000_ERR_CONFIG; 01242 goto out; 01243 break; 01244 } 01245 01246 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 01247 mac->txcw = txcw; 01248 01249 out: 01250 return ret_val; 01251 }
e1000_poll_fiber_serdes_link_generic - Poll for link up : pointer to the HW structure
Polls for link up by reading the status register, if link fails to come up with auto-negotiation, then the link is forced if a signal is detected.
Definition at line 1132 of file e1000_mac.c.
References e1000_mac_info::autoneg_failed, e1000_mac_operations::check_for_link, DEBUGFUNC, DEBUGOUT, E1000_READ_REG, E1000_STATUS, E1000_STATUS_LU, E1000_SUCCESS, FIBER_LINK_UP_LIMIT, e1000_hw::mac, msec_delay, e1000_mac_info::ops, and u32.
Referenced by e1000_setup_fiber_link_82543(), and e1000_setup_fiber_serdes_link_generic().
01133 { 01134 struct e1000_mac_info *mac = &hw->mac; 01135 u32 i, status; 01136 s32 ret_val = E1000_SUCCESS; 01137 01138 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 01139 01140 /* 01141 * If we have a signal (the cable is plugged in, or assumed true for 01142 * serdes media) then poll for a "Link-Up" indication in the Device 01143 * Status Register. Time-out if a link isn't seen in 500 milliseconds 01144 * seconds (Auto-negotiation should complete in less than 500 01145 * milliseconds even if the other end is doing it in SW). 01146 */ 01147 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 01148 msec_delay(10); 01149 status = E1000_READ_REG(hw, E1000_STATUS); 01150 if (status & E1000_STATUS_LU) 01151 break; 01152 } 01153 if (i == FIBER_LINK_UP_LIMIT) { 01154 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 01155 mac->autoneg_failed = 1; 01156 /* 01157 * AutoNeg failed to achieve a link, so we'll call 01158 * mac->check_for_link. This routine will force the 01159 * link up if we detect a signal. This will allow us to 01160 * communicate with non-autonegotiating link partners. 01161 */ 01162 ret_val = hw->mac.ops.check_for_link(hw); 01163 if (ret_val) { 01164 DEBUGOUT("Error while checking for link\n"); 01165 goto out; 01166 } 01167 mac->autoneg_failed = 0; 01168 } else { 01169 mac->autoneg_failed = 0; 01170 DEBUGOUT("Valid Link Found\n"); 01171 } 01172 01173 out: 01174 return ret_val; 01175 }
e1000_config_fc_after_link_up_generic - Configures flow control after link : pointer to the HW structure
Checks the status of auto-negotiation after link up to ensure that the speed and duplex were not forced. If the link needed to be forced, then flow control needs to be forced also. If auto-negotiation is enabled and did not fail, then we configure flow control based on our link partner.
Definition at line 1411 of file e1000_mac.c.
References e1000_mac_info::autoneg, e1000_mac_info::autoneg_failed, e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, e1000_force_mac_fc_generic(), e1000_media_type_copper, e1000_media_type_fiber, e1000_media_type_internal_serdes, E1000_SUCCESS, e1000_hw::fc, e1000_mac_operations::get_link_up_info, HALF_DUPLEX, e1000_hw::mac, e1000_phy_info::media_type, MII_SR_AUTONEG_COMPLETE, NWAY_AR_ASM_DIR, NWAY_AR_PAUSE, NWAY_LPAR_ASM_DIR, NWAY_LPAR_PAUSE, e1000_mac_info::ops, e1000_phy_info::ops, e1000_hw::phy, PHY_AUTONEG_ADV, PHY_LP_ABILITY, PHY_STATUS, e1000_phy_operations::read_reg, e1000_fc_info::requested_mode, and u16.
Referenced by e1000_check_for_copper_link_82543(), e1000_check_for_copper_link_generic(), e1000_check_for_fiber_link_82543(), e1000_check_for_fiber_link_generic(), e1000_check_for_link_82541(), e1000_check_for_serdes_link_generic(), e1000_setup_copper_link_82543(), and e1000_setup_copper_link_generic().
01412 { 01413 struct e1000_mac_info *mac = &hw->mac; 01414 s32 ret_val = E1000_SUCCESS; 01415 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 01416 u16 speed, duplex; 01417 01418 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 01419 01420 /* 01421 * Check for the case where we have fiber media and auto-neg failed 01422 * so we had to force link. In this case, we need to force the 01423 * configuration of the MAC to match the "fc" parameter. 01424 */ 01425 if (mac->autoneg_failed) { 01426 if (hw->phy.media_type == e1000_media_type_fiber || 01427 hw->phy.media_type == e1000_media_type_internal_serdes) 01428 ret_val = e1000_force_mac_fc_generic(hw); 01429 } else { 01430 if (hw->phy.media_type == e1000_media_type_copper) 01431 ret_val = e1000_force_mac_fc_generic(hw); 01432 } 01433 01434 if (ret_val) { 01435 DEBUGOUT("Error forcing flow control settings\n"); 01436 goto out; 01437 } 01438 01439 /* 01440 * Check for the case where we have copper media and auto-neg is 01441 * enabled. In this case, we need to check and see if Auto-Neg 01442 * has completed, and if so, how the PHY and link partner has 01443 * flow control configured. 01444 */ 01445 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 01446 /* 01447 * Read the MII Status Register and check to see if AutoNeg 01448 * has completed. We read this twice because this reg has 01449 * some "sticky" (latched) bits. 01450 */ 01451 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 01452 if (ret_val) 01453 goto out; 01454 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 01455 if (ret_val) 01456 goto out; 01457 01458 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 01459 DEBUGOUT("Copper PHY and Auto Neg " 01460 "has not completed.\n"); 01461 goto out; 01462 } 01463 01464 /* 01465 * The AutoNeg process has completed, so we now need to 01466 * read both the Auto Negotiation Advertisement 01467 * Register (Address 4) and the Auto_Negotiation Base 01468 * Page Ability Register (Address 5) to determine how 01469 * flow control was negotiated. 01470 */ 01471 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 01472 &mii_nway_adv_reg); 01473 if (ret_val) 01474 goto out; 01475 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 01476 &mii_nway_lp_ability_reg); 01477 if (ret_val) 01478 goto out; 01479 01480 /* 01481 * Two bits in the Auto Negotiation Advertisement Register 01482 * (Address 4) and two bits in the Auto Negotiation Base 01483 * Page Ability Register (Address 5) determine flow control 01484 * for both the PHY and the link partner. The following 01485 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 01486 * 1999, describes these PAUSE resolution bits and how flow 01487 * control is determined based upon these settings. 01488 * NOTE: DC = Don't Care 01489 * 01490 * LOCAL DEVICE | LINK PARTNER 01491 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 01492 *-------|---------|-------|---------|-------------------- 01493 * 0 | 0 | DC | DC | e1000_fc_none 01494 * 0 | 1 | 0 | DC | e1000_fc_none 01495 * 0 | 1 | 1 | 0 | e1000_fc_none 01496 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 01497 * 1 | 0 | 0 | DC | e1000_fc_none 01498 * 1 | DC | 1 | DC | e1000_fc_full 01499 * 1 | 1 | 0 | 0 | e1000_fc_none 01500 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 01501 * 01502 * Are both PAUSE bits set to 1? If so, this implies 01503 * Symmetric Flow Control is enabled at both ends. The 01504 * ASM_DIR bits are irrelevant per the spec. 01505 * 01506 * For Symmetric Flow Control: 01507 * 01508 * LOCAL DEVICE | LINK PARTNER 01509 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01510 *-------|---------|-------|---------|-------------------- 01511 * 1 | DC | 1 | DC | E1000_fc_full 01512 * 01513 */ 01514 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 01515 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 01516 /* 01517 * Now we need to check if the user selected Rx ONLY 01518 * of pause frames. In this case, we had to advertise 01519 * FULL flow control because we could not advertise RX 01520 * ONLY. Hence, we must now check to see if we need to 01521 * turn OFF the TRANSMISSION of PAUSE frames. 01522 */ 01523 if (hw->fc.requested_mode == e1000_fc_full) { 01524 hw->fc.current_mode = e1000_fc_full; 01525 DEBUGOUT("Flow Control = FULL.\r\n"); 01526 } else { 01527 hw->fc.current_mode = e1000_fc_rx_pause; 01528 DEBUGOUT("Flow Control = " 01529 "RX PAUSE frames only.\r\n"); 01530 } 01531 } 01532 /* 01533 * For receiving PAUSE frames ONLY. 01534 * 01535 * LOCAL DEVICE | LINK PARTNER 01536 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01537 *-------|---------|-------|---------|-------------------- 01538 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 01539 */ 01540 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 01541 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 01542 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 01543 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 01544 hw->fc.current_mode = e1000_fc_tx_pause; 01545 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 01546 } 01547 /* 01548 * For transmitting PAUSE frames ONLY. 01549 * 01550 * LOCAL DEVICE | LINK PARTNER 01551 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 01552 *-------|---------|-------|---------|-------------------- 01553 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 01554 */ 01555 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 01556 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 01557 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 01558 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 01559 hw->fc.current_mode = e1000_fc_rx_pause; 01560 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 01561 } else { 01562 /* 01563 * Per the IEEE spec, at this point flow control 01564 * should be disabled. 01565 */ 01566 hw->fc.current_mode = e1000_fc_none; 01567 DEBUGOUT("Flow Control = NONE.\r\n"); 01568 } 01569 01570 /* 01571 * Now we need to do one last check... If we auto- 01572 * negotiated to HALF DUPLEX, flow control should not be 01573 * enabled per IEEE 802.3 spec. 01574 */ 01575 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 01576 if (ret_val) { 01577 DEBUGOUT("Error getting link speed and duplex\n"); 01578 goto out; 01579 } 01580 01581 if (duplex == HALF_DUPLEX) 01582 hw->fc.current_mode = e1000_fc_none; 01583 01584 /* 01585 * Now we call a subroutine to actually force the MAC 01586 * controller to use the correct flow control settings. 01587 */ 01588 ret_val = e1000_force_mac_fc_generic(hw); 01589 if (ret_val) { 01590 DEBUGOUT("Error forcing flow control settings\n"); 01591 goto out; 01592 } 01593 } 01594 01595 out: 01596 return ret_val; 01597 }
e1000_disable_pcie_master_generic - Disables PCI-express master access : pointer to the HW structure
Returns 0 (E1000_SUCCESS) if successful, else returns -10 (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused the master requests to be disabled.
Disables PCI-Express master access and verifies there are no pending requests.
Definition at line 2070 of file e1000_mac.c.
References e1000_hw::bus, DEBUGFUNC, DEBUGOUT, e1000_bus_type_pci_express, E1000_CTRL, E1000_CTRL_GIO_MASTER_DISABLE, E1000_ERR_MASTER_REQUESTS_PENDING, E1000_READ_REG, E1000_STATUS, E1000_STATUS_GIO_MASTER_ENABLE, E1000_SUCCESS, E1000_WRITE_REG, MASTER_DISABLE_TIMEOUT, timeout(), e1000_bus_info::type, u32, and usec_delay.
Referenced by e1000_disable_pcie_master().
02071 { 02072 u32 ctrl; 02073 s32 timeout = MASTER_DISABLE_TIMEOUT; 02074 s32 ret_val = E1000_SUCCESS; 02075 02076 DEBUGFUNC("e1000_disable_pcie_master_generic"); 02077 02078 if (hw->bus.type != e1000_bus_type_pci_express) 02079 goto out; 02080 02081 ctrl = E1000_READ_REG(hw, E1000_CTRL); 02082 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 02083 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 02084 02085 while (timeout) { 02086 if (!(E1000_READ_REG(hw, E1000_STATUS) & 02087 E1000_STATUS_GIO_MASTER_ENABLE)) 02088 break; 02089 usec_delay(100); 02090 timeout--; 02091 } 02092 02093 if (!timeout) { 02094 DEBUGOUT("Master requests are pending.\n"); 02095 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 02096 goto out; 02097 } 02098 02099 out: 02100 return ret_val; 02101 }
e1000_force_mac_fc_generic - Force the MAC's flow control settings : pointer to the HW structure
Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the device control register to reflect the adapter settings. TFCE and RFCE need to be explicitly set by software when a copper PHY is used because autonegotiation is managed by the PHY rather than the MAC. Software must also configure these bits when link is forced on a fiber connection.
Definition at line 1345 of file e1000_mac.c.
References e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, DEBUGOUT1, E1000_CTRL, E1000_CTRL_RFCE, E1000_CTRL_TFCE, E1000_ERR_CONFIG, e1000_fc_full, e1000_fc_none, e1000_fc_rx_pause, e1000_fc_tx_pause, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::fc, and u32.
Referenced by e1000_config_fc_after_link_up_generic(), and e1000_force_mac_fc().
01346 { 01347 u32 ctrl; 01348 s32 ret_val = E1000_SUCCESS; 01349 01350 DEBUGFUNC("e1000_force_mac_fc_generic"); 01351 01352 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01353 01354 /* 01355 * Because we didn't get link via the internal auto-negotiation 01356 * mechanism (we either forced link or we got link via PHY 01357 * auto-neg), we have to manually enable/disable transmit an 01358 * receive flow control. 01359 * 01360 * The "Case" statement below enables/disable flow control 01361 * according to the "hw->fc.current_mode" parameter. 01362 * 01363 * The possible values of the "fc" parameter are: 01364 * 0: Flow control is completely disabled 01365 * 1: Rx flow control is enabled (we can receive pause 01366 * frames but not send pause frames). 01367 * 2: Tx flow control is enabled (we can send pause frames 01368 * frames but we do not receive pause frames). 01369 * 3: Both Rx and Tx flow control (symmetric) is enabled. 01370 * other: No other values should be possible at this point. 01371 */ 01372 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 01373 01374 switch (hw->fc.current_mode) { 01375 case e1000_fc_none: 01376 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 01377 break; 01378 case e1000_fc_rx_pause: 01379 ctrl &= (~E1000_CTRL_TFCE); 01380 ctrl |= E1000_CTRL_RFCE; 01381 break; 01382 case e1000_fc_tx_pause: 01383 ctrl &= (~E1000_CTRL_RFCE); 01384 ctrl |= E1000_CTRL_TFCE; 01385 break; 01386 case e1000_fc_full: 01387 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 01388 break; 01389 default: 01390 DEBUGOUT("Flow control param set incorrectly\n"); 01391 ret_val = -E1000_ERR_CONFIG; 01392 goto out; 01393 } 01394 01395 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01396 01397 out: 01398 return ret_val; 01399 }
e1000_get_auto_rd_done_generic - Check for auto read completion : pointer to the HW structure
Check EEPROM for Auto Read done bit.
Definition at line 1743 of file e1000_mac.c.
References AUTO_READ_DONE_TIMEOUT, DEBUGFUNC, DEBUGOUT, E1000_EECD, E1000_EECD_AUTO_RD, E1000_ERR_RESET, E1000_READ_REG, E1000_SUCCESS, and msec_delay.
01744 { 01745 s32 i = 0; 01746 s32 ret_val = E1000_SUCCESS; 01747 01748 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 01749 01750 while (i < AUTO_READ_DONE_TIMEOUT) { 01751 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 01752 break; 01753 msec_delay(1); 01754 i++; 01755 } 01756 01757 if (i == AUTO_READ_DONE_TIMEOUT) { 01758 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 01759 ret_val = -E1000_ERR_RESET; 01760 goto out; 01761 } 01762 01763 out: 01764 return ret_val; 01765 }
| void e1000_set_lan_id_single_port | ( | struct e1000_hw * | hw | ) |
e1000_set_lan_id_single_port - Set LAN id for a single port device : pointer to the HW structure
Sets the LAN function id to zero for a single port device.
Definition at line 314 of file e1000_mac.c.
References e1000_hw::bus, and e1000_bus_info::func.
Referenced by e1000_init_mac_params_82541().
00315 { 00316 struct e1000_bus_info *bus = &hw->bus; 00317 00318 bus->func = 0; 00319 }
| void e1000_set_lan_id_multi_port_pci | ( | struct e1000_hw * | hw | ) |
e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices : pointer to the HW structure
Determines the LAN function id by reading PCI config space.
Definition at line 292 of file e1000_mac.c.
References e1000_hw::bus, e1000_read_pci_cfg(), E1000_READ_REG, E1000_STATUS, E1000_STATUS_FUNC_MASK, E1000_STATUS_FUNC_SHIFT, e1000_bus_info::func, PCI_HEADER_TYPE_MULTIFUNC, PCI_HEADER_TYPE_REGISTER, u16, and u32.
Referenced by e1000_init_mac_params_82540(), e1000_init_mac_params_82542(), and e1000_init_mac_params_82543().
00293 { 00294 struct e1000_bus_info *bus = &hw->bus; 00295 u16 pci_header_type; 00296 u32 status; 00297 00298 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type); 00299 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) { 00300 status = E1000_READ_REG(hw, E1000_STATUS); 00301 bus->func = (status & E1000_STATUS_FUNC_MASK) 00302 >> E1000_STATUS_FUNC_SHIFT; 00303 } else { 00304 bus->func = 0; 00305 } 00306 }
e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex : pointer to the HW structure : stores the current speed : stores the current duplex
Read the status register for the current speed/duplex and store the current speed and duplex for copper connections.
Definition at line 1608 of file e1000_mac.c.
References DEBUGFUNC, DEBUGOUT, E1000_READ_REG, E1000_STATUS, E1000_STATUS_FD, E1000_STATUS_SPEED_100, E1000_STATUS_SPEED_1000, E1000_SUCCESS, FULL_DUPLEX, HALF_DUPLEX, SPEED_10, SPEED_100, SPEED_1000, and u32.
Referenced by e1000_get_link_up_info_82541(), e1000_init_mac_params_82540(), and e1000_init_mac_params_82543().
01610 { 01611 u32 status; 01612 01613 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 01614 01615 status = E1000_READ_REG(hw, E1000_STATUS); 01616 if (status & E1000_STATUS_SPEED_1000) { 01617 *speed = SPEED_1000; 01618 DEBUGOUT("1000 Mbs, "); 01619 } else if (status & E1000_STATUS_SPEED_100) { 01620 *speed = SPEED_100; 01621 DEBUGOUT("100 Mbs, "); 01622 } else { 01623 *speed = SPEED_10; 01624 DEBUGOUT("10 Mbs, "); 01625 } 01626 01627 if (status & E1000_STATUS_FD) { 01628 *duplex = FULL_DUPLEX; 01629 DEBUGOUT("Full Duplex\n"); 01630 } else { 01631 *duplex = HALF_DUPLEX; 01632 DEBUGOUT("Half Duplex\n"); 01633 } 01634 01635 return E1000_SUCCESS; 01636 }
| s32 e1000_get_speed_and_duplex_fiber_serdes_generic | ( | struct e1000_hw * | hw, | |
| u16 * | speed, | |||
| u16 * | duplex | |||
| ) |
| void e1000_update_mc_addr_list_generic | ( | struct e1000_hw * | hw, | |
| u8 * | mc_addr_list, | |||
| u32 | mc_addr_count | |||
| ) |
e1000_update_mc_addr_list_generic - Update Multicast addresses : pointer to the HW structure : array of multicast addresses to program : number of multicast addresses to program
Updates entire Multicast Table Array. The caller must have a packed mc_addr_list of multicast addresses.
Definition at line 533 of file e1000_mac.c.
References DEBUGFUNC, e1000_hash_mc_addr_generic(), E1000_MTA, E1000_WRITE_FLUSH, E1000_WRITE_REG_ARRAY, ETH_ADDR_LEN, e1000_hw::mac, memset(), e1000_mac_info::mta_reg_count, e1000_mac_info::mta_shadow, and u32.
Referenced by e1000_init_mac_params_82540(), e1000_init_mac_params_82541(), e1000_init_mac_params_82542(), and e1000_init_mac_params_82543().
00535 { 00536 u32 hash_value, hash_bit, hash_reg; 00537 int i; 00538 00539 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 00540 00541 /* clear mta_shadow */ 00542 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 00543 00544 /* update mta_shadow from mc_addr_list */ 00545 for (i = 0; (u32) i < mc_addr_count; i++) { 00546 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 00547 00548 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 00549 hash_bit = hash_value & 0x1F; 00550 00551 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 00552 mc_addr_list += (ETH_ADDR_LEN); 00553 } 00554 00555 /* replace the entire MTA table */ 00556 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 00557 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 00558 E1000_WRITE_FLUSH(hw); 00559 }
e1000_set_default_fc_generic - Set flow control default values : pointer to the HW structure
Read the EEPROM for the default values for flow control and store the values.
Definition at line 1300 of file e1000_mac.c.
References DEBUGFUNC, DEBUGOUT, e1000_fc_full, e1000_fc_none, e1000_fc_tx_pause, E1000_SUCCESS, e1000_hw::fc, e1000_hw::nvm, NVM_INIT_CONTROL2_REG, NVM_WORD0F_ASM_DIR, NVM_WORD0F_PAUSE_MASK, e1000_nvm_info::ops, e1000_nvm_operations::read, e1000_fc_info::requested_mode, and u16.
Referenced by e1000_setup_link_82542(), and e1000_setup_link_generic().
01301 { 01302 s32 ret_val = E1000_SUCCESS; 01303 u16 nvm_data; 01304 01305 DEBUGFUNC("e1000_set_default_fc_generic"); 01306 01307 /* 01308 * Read and store word 0x0F of the EEPROM. This word contains bits 01309 * that determine the hardware's default PAUSE (flow control) mode, 01310 * a bit that determines whether the HW defaults to enabling or 01311 * disabling auto-negotiation, and the direction of the 01312 * SW defined pins. If there is no SW over-ride of the flow 01313 * control setting, then the variable hw->fc will 01314 * be initialized based on a value in the EEPROM. 01315 */ 01316 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 01317 01318 if (ret_val) { 01319 DEBUGOUT("NVM Read Error\n"); 01320 goto out; 01321 } 01322 01323 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 01324 hw->fc.requested_mode = e1000_fc_none; 01325 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 01326 NVM_WORD0F_ASM_DIR) 01327 hw->fc.requested_mode = e1000_fc_tx_pause; 01328 else 01329 hw->fc.requested_mode = e1000_fc_full; 01330 01331 out: 01332 return ret_val; 01333 }
e1000_set_fc_watermarks_generic - Set flow control high/low watermarks : pointer to the HW structure
Sets the flow control high/low threshold (watermark) registers. If flow control XON frame transmission is enabled, then set XON frame transmission as well.
Definition at line 1261 of file e1000_mac.c.
References e1000_fc_info::current_mode, DEBUGFUNC, e1000_fc_tx_pause, E1000_FCRTH, E1000_FCRTL, E1000_FCRTL_XONE, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::fc, e1000_fc_info::high_water, e1000_fc_info::low_water, e1000_fc_info::send_xon, and u32.
Referenced by e1000_setup_link_82542(), and e1000_setup_link_generic().
01262 { 01263 s32 ret_val = E1000_SUCCESS; 01264 u32 fcrtl = 0, fcrth = 0; 01265 01266 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 01267 01268 /* 01269 * Set the flow control receive threshold registers. Normally, 01270 * these registers will be set to a default threshold that may be 01271 * adjusted later by the driver's runtime code. However, if the 01272 * ability to transmit pause frames is not enabled, then these 01273 * registers will be set to 0. 01274 */ 01275 if (hw->fc.current_mode & e1000_fc_tx_pause) { 01276 /* 01277 * We need to set up the Receive Threshold high and low water 01278 * marks as well as (optionally) enabling the transmission of 01279 * XON frames. 01280 */ 01281 fcrtl = hw->fc.low_water; 01282 if (hw->fc.send_xon) 01283 fcrtl |= E1000_FCRTL_XONE; 01284 01285 fcrth = hw->fc.high_water; 01286 } 01287 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 01288 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 01289 01290 return ret_val; 01291 }
e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes : pointer to the HW structure
Configures collision distance and flow control for fiber and serdes links. Upon successful setup, poll for link.
Definition at line 1055 of file e1000_mac.c.
References DEBUGFUNC, DEBUGOUT, e1000_commit_fc_settings_generic(), e1000_config_collision_dist_generic(), E1000_CTRL, E1000_CTRL_LRST, E1000_CTRL_SWDPIN1, e1000_media_type_internal_serdes, e1000_poll_fiber_serdes_link_generic(), E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_FLUSH, E1000_WRITE_REG, e1000_phy_info::media_type, msec_delay, e1000_hw::phy, and u32.
Referenced by e1000_init_mac_params_82542(), and e1000_setup_fiber_serdes_link_82540().
01056 { 01057 u32 ctrl; 01058 s32 ret_val = E1000_SUCCESS; 01059 01060 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 01061 01062 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01063 01064 /* Take the link out of reset */ 01065 ctrl &= ~E1000_CTRL_LRST; 01066 01067 e1000_config_collision_dist_generic(hw); 01068 01069 ret_val = e1000_commit_fc_settings_generic(hw); 01070 if (ret_val) 01071 goto out; 01072 01073 /* 01074 * Since auto-negotiation is enabled, take the link out of reset (the 01075 * link will be in reset, because we previously reset the chip). This 01076 * will restart auto-negotiation. If auto-negotiation is successful 01077 * then the link-up status bit will be set and the flow control enable 01078 * bits (RFCE and TFCE) will be set according to their negotiated value. 01079 */ 01080 DEBUGOUT("Auto-negotiation enabled\n"); 01081 01082 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01083 E1000_WRITE_FLUSH(hw); 01084 msec_delay(1); 01085 01086 /* 01087 * For these adapters, the SW definable pin 1 is set when the optics 01088 * detect a signal. If we have a signal, then poll for a "Link-Up" 01089 * indication. 01090 */ 01091 if (hw->phy.media_type == e1000_media_type_internal_serdes || 01092 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 01093 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 01094 } else { 01095 DEBUGOUT("No signal detected\n"); 01096 } 01097 01098 out: 01099 return ret_val; 01100 }
e1000_setup_link_generic - Setup flow control and link settings : pointer to the HW structure
Determines which flow control settings to use, then configures flow control. Calls the appropriate media-specific link configuration function. Assuming the adapter has a valid link partner, a valid link should be established. Assumes the hardware has previously been reset and the transmitter and receiver are not enabled.
Definition at line 991 of file e1000_mac.c.
References e1000_phy_operations::check_reset_block, e1000_fc_info::current_mode, DEBUGFUNC, DEBUGOUT, DEBUGOUT1, e1000_fc_default, E1000_FCAH, E1000_FCAL, E1000_FCT, E1000_FCTTV, e1000_set_default_fc_generic(), e1000_set_fc_watermarks_generic(), E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::fc, FLOW_CONTROL_ADDRESS_HIGH, FLOW_CONTROL_ADDRESS_LOW, FLOW_CONTROL_TYPE, e1000_hw::mac, e1000_mac_info::ops, e1000_phy_info::ops, e1000_fc_info::pause_time, e1000_hw::phy, e1000_fc_info::requested_mode, and e1000_mac_operations::setup_physical_interface.
Referenced by e1000_init_mac_params_82540(), e1000_init_mac_params_82541(), and e1000_setup_link_82543().
00992 { 00993 s32 ret_val = E1000_SUCCESS; 00994 00995 DEBUGFUNC("e1000_setup_link_generic"); 00996 00997 /* 00998 * In the case of the phy reset being blocked, we already have a link. 00999 * We do not need to set it up again. 01000 */ 01001 if (hw->phy.ops.check_reset_block) 01002 if (hw->phy.ops.check_reset_block(hw)) 01003 goto out; 01004 01005 /* 01006 * If requested flow control is set to default, set flow control 01007 * based on the EEPROM flow control settings. 01008 */ 01009 if (hw->fc.requested_mode == e1000_fc_default) { 01010 ret_val = e1000_set_default_fc_generic(hw); 01011 if (ret_val) 01012 goto out; 01013 } 01014 01015 /* 01016 * Save off the requested flow control mode for use later. Depending 01017 * on the link partner's capabilities, we may or may not use this mode. 01018 */ 01019 hw->fc.current_mode = hw->fc.requested_mode; 01020 01021 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 01022 hw->fc.current_mode); 01023 01024 /* Call the necessary media_type subroutine to configure the link. */ 01025 ret_val = hw->mac.ops.setup_physical_interface(hw); 01026 if (ret_val) 01027 goto out; 01028 01029 /* 01030 * Initialize the flow control address, type, and PAUSE timer 01031 * registers to their default values. This is done even if flow 01032 * control is disabled, because it does not hurt anything to 01033 * initialize these registers. 01034 */ 01035 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); 01036 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 01037 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 01038 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 01039 01040 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 01041 01042 ret_val = e1000_set_fc_watermarks_generic(hw); 01043 01044 out: 01045 return ret_val; 01046 }
e1000_hash_mc_addr_generic - Generate a multicast hash value : pointer to the HW structure : pointer to a multicast address
Generates a multicast address hash value which is used to determine the multicast filter table array address and new table value. See e1000_mta_set_generic()
Definition at line 570 of file e1000_mac.c.
References DEBUGFUNC, e1000_hw::mac, e1000_mac_info::mc_filter_type, e1000_mac_info::mta_reg_count, u16, u32, and u8.
Referenced by e1000_hash_mc_addr(), and e1000_update_mc_addr_list_generic().
00571 { 00572 u32 hash_value, hash_mask; 00573 u8 bit_shift = 0; 00574 00575 DEBUGFUNC("e1000_hash_mc_addr_generic"); 00576 00577 /* Register count multiplied by bits per register */ 00578 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 00579 00580 /* 00581 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 00582 * where 0xFF would still fall within the hash mask. 00583 */ 00584 while (hash_mask >> bit_shift != 0xFF) 00585 bit_shift++; 00586 00587 /* 00588 * The portion of the address that is used for the hash table 00589 * is determined by the mc_filter_type setting. 00590 * The algorithm is such that there is a total of 8 bits of shifting. 00591 * The bit_shift for a mc_filter_type of 0 represents the number of 00592 * left-shifts where the MSB of mc_addr[5] would still fall within 00593 * the hash_mask. Case 0 does this exactly. Since there are a total 00594 * of 8 bits of shifting, then mc_addr[4] will shift right the 00595 * remaining number of bits. Thus 8 - bit_shift. The rest of the 00596 * cases are a variation of this algorithm...essentially raising the 00597 * number of bits to shift mc_addr[5] left, while still keeping the 00598 * 8-bit shifting total. 00599 * 00600 * For example, given the following Destination MAC Address and an 00601 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 00602 * we can see that the bit_shift for case 0 is 4. These are the hash 00603 * values resulting from each mc_filter_type... 00604 * [0] [1] [2] [3] [4] [5] 00605 * 01 AA 00 12 34 56 00606 * LSB MSB 00607 * 00608 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 00609 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 00610 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 00611 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 00612 */ 00613 switch (hw->mac.mc_filter_type) { 00614 default: 00615 case 0: 00616 break; 00617 case 1: 00618 bit_shift += 1; 00619 break; 00620 case 2: 00621 bit_shift += 2; 00622 break; 00623 case 3: 00624 bit_shift += 4; 00625 break; 00626 } 00627 00628 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 00629 (((u16) mc_addr[5]) << bit_shift))); 00630 00631 return hash_value; 00632 }
| void e1000_clear_hw_cntrs_base_generic | ( | struct e1000_hw * | hw | ) |
| void e1000_clear_vfta_generic | ( | struct e1000_hw * | hw | ) |
e1000_clear_vfta_generic - Clear VLAN filter table : pointer to the HW structure
Clears the register array which contains the VLAN filter table by setting all the values to 0.
Definition at line 328 of file e1000_mac.c.
References DEBUGFUNC, E1000_VFTA, E1000_VLAN_FILTER_TBL_SIZE, E1000_WRITE_FLUSH, E1000_WRITE_REG_ARRAY, offset, and u32.
Referenced by e1000_init_mac_params_82540(), e1000_init_mac_params_82541(), e1000_init_mac_params_82542(), and e1000_init_mac_params_82543().
00329 { 00330 u32 offset; 00331 00332 DEBUGFUNC("e1000_clear_vfta_generic"); 00333 00334 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 00335 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 00336 E1000_WRITE_FLUSH(hw); 00337 } 00338 }
| void e1000_config_collision_dist_generic | ( | struct e1000_hw * | hw | ) |
e1000_config_collision_dist_generic - Configure collision distance : pointer to the HW structure
Configures the collision distance to the default value and is used during link setup. Currently no func pointer exists and all implementations are handled in the generic version of this function.
Definition at line 1110 of file e1000_mac.c.
References DEBUGFUNC, E1000_COLD_SHIFT, E1000_COLLISION_DISTANCE, E1000_READ_REG, E1000_TCTL, E1000_TCTL_COLD, E1000_WRITE_FLUSH, E1000_WRITE_REG, and u32.
Referenced by e1000_check_for_copper_link_82543(), e1000_check_for_copper_link_generic(), e1000_check_for_link_82541(), e1000_config_mac_to_phy_82543(), e1000_init_mac_ops_generic(), e1000_setup_copper_link_82543(), e1000_setup_copper_link_generic(), e1000_setup_fiber_link_82543(), and e1000_setup_fiber_serdes_link_generic().
01111 { 01112 u32 tctl; 01113 01114 DEBUGFUNC("e1000_config_collision_dist_generic"); 01115 01116 tctl = E1000_READ_REG(hw, E1000_TCTL); 01117 01118 tctl &= ~E1000_TCTL_COLD; 01119 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 01120 01121 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 01122 E1000_WRITE_FLUSH(hw); 01123 }
e1000_init_rx_addrs_generic - Initialize receive address's : pointer to the HW structure : receive address registers
Setups the receive address registers by setting the base receive address register to the devices MAC address and clearing all the other receive address registers to 0.
Definition at line 366 of file e1000_mac.c.
References e1000_mac_info::addr, DEBUGFUNC, DEBUGOUT, DEBUGOUT1, ETH_ADDR_LEN, e1000_hw::mac, e1000_mac_info::ops, e1000_mac_operations::rar_set, u32, and u8.
Referenced by e1000_init_hw_82540(), e1000_init_hw_82541(), e1000_init_hw_82542(), and e1000_init_hw_82543().
00367 { 00368 u32 i; 00369 u8 mac_addr[ETH_ADDR_LEN] = {0}; 00370 00371 DEBUGFUNC("e1000_init_rx_addrs_generic"); 00372 00373 /* Setup the receive address */ 00374 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 00375 00376 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 00377 00378 /* Zero out the other (rar_entry_count - 1) receive addresses */ 00379 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 00380 for (i = 1; i < rar_count; i++) 00381 hw->mac.ops.rar_set(hw, mac_addr, i); 00382 }
e1000_mta_set_generic - Set multicast filter table address : pointer to the HW structure : determines the MTA register and bit to set
The multicast table address is a register array of 32-bit registers. The hash_value is used to determine what register the bit is in, the current value is read, the new bit is OR'd in and the new value is written back into the register.
Definition at line 498 of file e1000_mac.c.
References DEBUGFUNC, E1000_MTA, E1000_READ_REG_ARRAY, E1000_WRITE_FLUSH, E1000_WRITE_REG_ARRAY, e1000_hw::mac, e1000_mac_info::mta_reg_count, and u32.
Referenced by e1000_init_mac_params_82540(), e1000_init_mac_params_82541(), e1000_init_mac_params_82542(), and e1000_mta_set_82543().
00499 { 00500 u32 hash_bit, hash_reg, mta; 00501 00502 DEBUGFUNC("e1000_mta_set_generic"); 00503 /* 00504 * The MTA is a register array of 32-bit registers. It is 00505 * treated like an array of (32*mta_reg_count) bits. We want to 00506 * set bit BitArray[hash_value]. So we figure out what register 00507 * the bit is in, read it, OR in the new bit, then write 00508 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 00509 * mask to bits 31:5 of the hash value which gives us the 00510 * register we're modifying. The hash bit within that register 00511 * is determined by the lower 5 bits of the hash value. 00512 */ 00513 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 00514 hash_bit = hash_value & 0x1F; 00515 00516 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 00517 00518 mta |= (1 << hash_bit); 00519 00520 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 00521 E1000_WRITE_FLUSH(hw); 00522 }
| void e1000_pcix_mmrbc_workaround_generic | ( | struct e1000_hw * | hw | ) |
e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value : pointer to the HW structure
In certain situations, a system BIOS may report that the PCIx maximum memory read byte count (MMRBC) value is higher than than the actual value. We check the PCIx command register with the current PCIx status register.
Definition at line 643 of file e1000_mac.c.
References e1000_hw::bus, DEBUGFUNC, e1000_bus_type_pcix, e1000_read_pci_cfg(), e1000_write_pci_cfg(), PCIX_COMMAND_MMRBC_MASK, PCIX_COMMAND_MMRBC_SHIFT, PCIX_COMMAND_REGISTER, PCIX_STATUS_HI_MMRBC_2K, PCIX_STATUS_HI_MMRBC_4K, PCIX_STATUS_HI_MMRBC_MASK, PCIX_STATUS_HI_MMRBC_SHIFT, PCIX_STATUS_REGISTER_HI, e1000_bus_info::type, and u16.
Referenced by e1000_init_hw_82540(), and e1000_init_hw_82543().
00644 { 00645 u16 cmd_mmrbc; 00646 u16 pcix_cmd; 00647 u16 pcix_stat_hi_word; 00648 u16 stat_mmrbc; 00649 00650 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic"); 00651 00652 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */ 00653 if (hw->bus.type != e1000_bus_type_pcix) 00654 return; 00655 00656 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 00657 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word); 00658 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >> 00659 PCIX_COMMAND_MMRBC_SHIFT; 00660 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> 00661 PCIX_STATUS_HI_MMRBC_SHIFT; 00662 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) 00663 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; 00664 if (cmd_mmrbc > stat_mmrbc) { 00665 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK; 00666 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; 00667 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd); 00668 } 00669 }
| void e1000_put_hw_semaphore_generic | ( | struct e1000_hw * | hw | ) |
e1000_rar_set_generic - Set receive address register : pointer to the HW structure : pointer to the receive address : receive address array register
Sets the receive address array register at index to the address passed in by addr.
Definition at line 457 of file e1000_mac.c.
References DEBUGFUNC, E1000_RAH, E1000_RAH_AV, E1000_RAL, E1000_WRITE_FLUSH, E1000_WRITE_REG, and u32.
Referenced by e1000_init_mac_ops_generic().
00458 { 00459 u32 rar_low, rar_high; 00460 00461 DEBUGFUNC("e1000_rar_set_generic"); 00462 00463 /* 00464 * HW expects these in little endian so we reverse the byte order 00465 * from network order (big endian) to little endian 00466 */ 00467 rar_low = ((u32) addr[0] | 00468 ((u32) addr[1] << 8) | 00469 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 00470 00471 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 00472 00473 /* If MAC address zero, no need to set the AV bit */ 00474 if (rar_low || rar_high) 00475 rar_high |= E1000_RAH_AV; 00476 00477 /* 00478 * Some bridges will combine consecutive 32-bit writes into 00479 * a single burst write, which will malfunction on some parts. 00480 * The flushes avoid this. 00481 */ 00482 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 00483 E1000_WRITE_FLUSH(hw); 00484 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 00485 E1000_WRITE_FLUSH(hw); 00486 }
e1000_check_alt_mac_addr_generic - Check for alternate MAC addr : pointer to the HW structure
Checks the nvm for an alternate MAC address. An alternate MAC address can be setup by pre-boot software and must be treated like a permanent address and must override the actual permanent MAC address. If an alternate MAC address is found it is programmed into RAR0, replacing the permanent address that was installed into RAR0 by the Si on reset. This function will return SUCCESS unless it encounters an error while reading the EEPROM.
Definition at line 396 of file e1000_mac.c.
References e1000_hw::bus, DEBUGFUNC, DEBUGOUT, E1000_ALT_MAC_ADDRESS_OFFSET_LAN1, E1000_FUNC_1, E1000_SUCCESS, ETH_ADDR_LEN, e1000_bus_info::func, e1000_hw::mac, e1000_hw::nvm, NVM_ALT_MAC_ADDR_PTR, offset, e1000_mac_info::ops, e1000_nvm_info::ops, e1000_mac_operations::rar_set, e1000_nvm_operations::read, u16, u32, and u8.
00397 { 00398 u32 i; 00399 s32 ret_val = E1000_SUCCESS; 00400 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 00401 u8 alt_mac_addr[ETH_ADDR_LEN]; 00402 00403 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 00404 00405 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 00406 &nvm_alt_mac_addr_offset); 00407 if (ret_val) { 00408 DEBUGOUT("NVM Read Error\n"); 00409 goto out; 00410 } 00411 00412 if (nvm_alt_mac_addr_offset == 0xFFFF) { 00413 /* There is no Alternate MAC Address */ 00414 goto out; 00415 } 00416 00417 if (hw->bus.func == E1000_FUNC_1) 00418 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 00419 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 00420 offset = nvm_alt_mac_addr_offset + (i >> 1); 00421 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 00422 if (ret_val) { 00423 DEBUGOUT("NVM Read Error\n"); 00424 goto out; 00425 } 00426 00427 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 00428 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 00429 } 00430 00431 /* if multicast bit is set, the alternate address will not be used */ 00432 if (alt_mac_addr[0] & 0x01) { 00433 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 00434 goto out; 00435 } 00436 00437 /* 00438 * We have a valid alternate MAC address, and we want to treat it the 00439 * same as the normal permanent MAC address stored by the HW into the 00440 * RAR. Do this by mapping this address into RAR0. 00441 */ 00442 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 00443 00444 out: 00445 return ret_val; 00446 }
| void e1000_reset_adaptive_generic | ( | struct e1000_hw * | hw | ) |
e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing : pointer to the HW structure
Reset the Adaptive Interframe Spacing throttle to default values.
Definition at line 2109 of file e1000_mac.c.
References e1000_mac_info::adaptive_ifs, e1000_mac_info::current_ifs_val, DEBUGFUNC, DEBUGOUT, E1000_AIT, E1000_WRITE_REG, IFS_MAX, e1000_mac_info::ifs_max_val, IFS_MIN, e1000_mac_info::ifs_min_val, IFS_RATIO, e1000_mac_info::ifs_ratio, IFS_STEP, e1000_mac_info::ifs_step_size, e1000_mac_info::in_ifs_mode, and e1000_hw::mac.
Referenced by e1000_reset_adaptive().
02110 { 02111 struct e1000_mac_info *mac = &hw->mac; 02112 02113 DEBUGFUNC("e1000_reset_adaptive_generic"); 02114 02115 if (!mac->adaptive_ifs) { 02116 DEBUGOUT("Not in Adaptive IFS mode!\n"); 02117 goto out; 02118 } 02119 02120 mac->current_ifs_val = 0; 02121 mac->ifs_min_val = IFS_MIN; 02122 mac->ifs_max_val = IFS_MAX; 02123 mac->ifs_step_size = IFS_STEP; 02124 mac->ifs_ratio = IFS_RATIO; 02125 02126 mac->in_ifs_mode = false; 02127 E1000_WRITE_REG(hw, E1000_AIT, 0); 02128 out: 02129 return; 02130 }
e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities : pointer to the HW structure : bitmap of snoop events
Set the PCI-express register to snoop for events enabled in 'no_snoop'.
Definition at line 2040 of file e1000_mac.c.
References e1000_hw::bus, DEBUGFUNC, e1000_bus_type_pci_express, E1000_GCR, E1000_READ_REG, E1000_WRITE_REG, PCIE_NO_SNOOP_ALL, e1000_bus_info::type, and u32.
02041 { 02042 u32 gcr; 02043 02044 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 02045 02046 if (hw->bus.type != e1000_bus_type_pci_express) 02047 goto out; 02048 02049 if (no_snoop) { 02050 gcr = E1000_READ_REG(hw, E1000_GCR); 02051 gcr &= ~(PCIE_NO_SNOOP_ALL); 02052 gcr |= no_snoop; 02053 E1000_WRITE_REG(hw, E1000_GCR, gcr); 02054 } 02055 out: 02056 return; 02057 }
| void e1000_update_adaptive_generic | ( | struct e1000_hw * | hw | ) |
e1000_update_adaptive_generic - Update Adaptive Interframe Spacing : pointer to the HW structure
Update the Adaptive Interframe Spacing Throttle value based on the time between transmitted packets and time between collisions.
Definition at line 2139 of file e1000_mac.c.
References e1000_mac_info::adaptive_ifs, e1000_mac_info::collision_delta, e1000_mac_info::current_ifs_val, DEBUGFUNC, DEBUGOUT, E1000_AIT, E1000_WRITE_REG, e1000_mac_info::ifs_max_val, e1000_mac_info::ifs_min_val, e1000_mac_info::ifs_ratio, e1000_mac_info::ifs_step_size, e1000_mac_info::in_ifs_mode, e1000_hw::mac, MIN_NUM_XMITS, and e1000_mac_info::tx_packet_delta.
Referenced by e1000_update_adaptive().
02140 { 02141 struct e1000_mac_info *mac = &hw->mac; 02142 02143 DEBUGFUNC("e1000_update_adaptive_generic"); 02144 02145 if (!mac->adaptive_ifs) { 02146 DEBUGOUT("Not in Adaptive IFS mode!\n"); 02147 goto out; 02148 } 02149 02150 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 02151 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 02152 mac->in_ifs_mode = true; 02153 if (mac->current_ifs_val < mac->ifs_max_val) { 02154 if (!mac->current_ifs_val) 02155 mac->current_ifs_val = mac->ifs_min_val; 02156 else 02157 mac->current_ifs_val += 02158 mac->ifs_step_size; 02159 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val); 02160 } 02161 } 02162 } else { 02163 if (mac->in_ifs_mode && 02164 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 02165 mac->current_ifs_val = 0; 02166 mac->in_ifs_mode = false; 02167 E1000_WRITE_REG(hw, E1000_AIT, 0); 02168 } 02169 } 02170 out: 02171 return; 02172 }
e1000_write_vfta_generic - Write value to VLAN filter table : pointer to the HW structure : register offset in VLAN filter table : register value written to VLAN filter table
Writes value at the given offset in the register array which stores the VLAN filter table.
Definition at line 349 of file e1000_mac.c.
References DEBUGFUNC, E1000_VFTA, E1000_WRITE_FLUSH, and E1000_WRITE_REG_ARRAY.
Referenced by e1000_init_mac_params_82540(), e1000_init_mac_params_82541(), e1000_init_mac_params_82542(), and e1000_write_vfta_82543().
00350 { 00351 DEBUGFUNC("e1000_write_vfta_generic"); 00352 00353 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 00354 E1000_WRITE_FLUSH(hw); 00355 }
1.5.7.1