#include "e1000_api.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| static s32 | e1000_init_phy_params_82543 (struct e1000_hw *hw) |
| e1000_init_phy_params_82543 - Init PHY func ptrs. | |
| static s32 | e1000_init_nvm_params_82543 (struct e1000_hw *hw) |
| e1000_init_nvm_params_82543 - Init NVM func ptrs. | |
| static s32 | e1000_init_mac_params_82543 (struct e1000_hw *hw) |
| e1000_init_mac_params_82543 - Init MAC func ptrs. | |
| static s32 | e1000_read_phy_reg_82543 (struct e1000_hw *hw, u32 offset, u16 *data) |
| e1000_read_phy_reg_82543 - Read PHY register : pointer to the HW structure : register offset to be read : pointer to the read data | |
| static s32 | e1000_write_phy_reg_82543 (struct e1000_hw *hw, u32 offset, u16 data) |
| e1000_write_phy_reg_82543 - Write PHY register : pointer to the HW structure : register offset to be written : pointer to the data to be written at offset | |
| static s32 | e1000_phy_hw_reset_82543 (struct e1000_hw *hw) |
| e1000_phy_hw_reset_82543 - PHY hardware reset : pointer to the HW structure | |
| static s32 | e1000_reset_hw_82543 (struct e1000_hw *hw) |
| e1000_reset_hw_82543 - Reset hardware : pointer to the HW structure | |
| static s32 | e1000_init_hw_82543 (struct e1000_hw *hw) |
| e1000_init_hw_82543 - Initialize hardware : pointer to the HW structure | |
| static s32 | e1000_setup_link_82543 (struct e1000_hw *hw) |
| e1000_setup_link_82543 - Setup flow control and link settings : pointer to the HW structure | |
| static s32 | e1000_setup_copper_link_82543 (struct e1000_hw *hw) |
| e1000_setup_copper_link_82543 - Configure copper link settings : pointer to the HW structure | |
| static s32 | e1000_setup_fiber_link_82543 (struct e1000_hw *hw) |
| e1000_setup_fiber_link_82543 - Setup link for fiber : pointer to the HW structure | |
| static s32 | e1000_check_for_copper_link_82543 (struct e1000_hw *hw) |
| e1000_check_for_copper_link_82543 - Check for link (Copper) : pointer to the HW structure | |
| static s32 | e1000_check_for_fiber_link_82543 (struct e1000_hw *hw) |
| e1000_check_for_fiber_link_82543 - Check for link (Fiber) : pointer to the HW structure | |
| static s32 | e1000_led_on_82543 (struct e1000_hw *hw) |
| static s32 | e1000_led_off_82543 (struct e1000_hw *hw) |
| static void | e1000_write_vfta_82543 (struct e1000_hw *hw, u32 offset, u32 value) |
| e1000_write_vfta_82543 - Write value to VLAN filter table : pointer to the HW structure : the 32-bit offset in which to write the value to. | |
| static void | e1000_mta_set_82543 (struct e1000_hw *hw, u32 hash_value) |
| e1000_mta_set_82543 - Set multicast filter table address : pointer to the HW structure : determines the MTA register and bit to set | |
| static void | e1000_clear_hw_cntrs_82543 (struct e1000_hw *hw) |
| e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters : pointer to the HW structure | |
| static s32 | e1000_config_mac_to_phy_82543 (struct e1000_hw *hw) |
| e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings : pointer to the HW structure | |
| static bool | e1000_init_phy_disabled_82543 (struct e1000_hw *hw) |
| e1000_init_phy_disabled_82543 - Returns init PHY status : pointer to the HW structure | |
| static void | e1000_lower_mdi_clk_82543 (struct e1000_hw *hw, u32 *ctrl) |
| e1000_lower_mdi_clk_82543 - Lower Management Data Input clock : pointer to the HW structure : pointer to the control register | |
| static s32 | e1000_polarity_reversal_workaround_82543 (struct e1000_hw *hw) |
| e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal : pointer to the HW structure | |
| static void | e1000_raise_mdi_clk_82543 (struct e1000_hw *hw, u32 *ctrl) |
| e1000_raise_mdi_clk_82543 - Raise Management Data Input clock : pointer to the HW structure : pointer to the control register | |
| static u16 | e1000_shift_in_mdi_bits_82543 (struct e1000_hw *hw) |
| e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY : pointer to the HW structure | |
| static void | e1000_shift_out_mdi_bits_82543 (struct e1000_hw *hw, u32 data, u16 count) |
| e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY : pointer to the HW structure : data to send to the PHY : number of bits to shift out | |
| static bool | e1000_tbi_compatibility_enabled_82543 (struct e1000_hw *hw) |
| e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status : pointer to the HW structure | |
| static void | e1000_set_tbi_compatibility_82543 (struct e1000_hw *hw, bool state) |
| e1000_set_tbi_compatibility_82543 - Set TBI compatibility : pointer to the HW structure : enable/disable TBI compatibility | |
| static void | e1000_set_tbi_sbp_82543 (struct e1000_hw *hw, bool state) |
| e1000_set_tbi_sbp_82543 - Set TBI SBP : pointer to the HW structure : enable/disable TBI store bad packet | |
| void | e1000_init_function_pointers_82543 (struct e1000_hw *hw) |
| e1000_init_function_pointers_82543 - Init func ptrs. | |
| bool | e1000_tbi_sbp_enabled_82543 (struct e1000_hw *hw) |
| e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status : pointer to the HW structure | |
| static s32 | e1000_led_on_82543 (struct e1000_hw *hw __unused) |
| e1000_led_on_82543 - Turn on SW controllable LED : pointer to the HW structure | |
| static s32 | e1000_led_off_82543 (struct e1000_hw *hw __unused) |
| e1000_led_off_82543 - Turn off SW controllable LED : pointer to the HW structure | |
Variables | |
| static struct pci_device_id | e1000_82543_nics [] |
| struct pci_driver e1000_82543_driver | __pci_driver |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
e1000_init_phy_params_82543 - Init PHY func ptrs.
: pointer to the HW structure
Definition at line 82 of file e1000_82543.c.
References e1000_phy_info::addr, AUTONEG_ADVERTISE_SPEED_DEFAULT, e1000_phy_info::autoneg_mask, e1000_phy_operations::check_polarity, e1000_phy_operations::commit, DEBUGFUNC, DEBUGOUT, e1000_82543, e1000_82544, e1000_check_polarity_m88(), E1000_ERR_PHY, e1000_get_cfg_done_generic(), e1000_get_phy_id(), e1000_get_phy_info_m88(), e1000_init_phy_disabled_82543(), e1000_media_type_copper, e1000_phy_hw_reset_82543(), e1000_phy_hw_reset_generic(), e1000_phy_m88, e1000_phy_none, e1000_phy_sw_reset_generic(), e1000_power_down_phy_copper(), e1000_power_up_phy_copper(), e1000_read_phy_reg_82543(), e1000_read_phy_reg_m88(), E1000_SUCCESS, e1000_write_phy_reg_82543(), e1000_write_phy_reg_m88(), e1000_phy_operations::get_cfg_done, e1000_phy_operations::get_info, e1000_phy_info::id, M88E1000_E_PHY_ID, M88E1000_I_PHY_ID, e1000_hw::mac, e1000_phy_info::media_type, msec_delay, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_down, e1000_phy_operations::power_up, e1000_phy_operations::read_reg, e1000_phy_operations::reset, e1000_phy_info::reset_delay_us, e1000_mac_info::type, e1000_phy_info::type, and e1000_phy_operations::write_reg.
Referenced by e1000_init_function_pointers_82543().
00083 { 00084 struct e1000_phy_info *phy = &hw->phy; 00085 s32 ret_val = E1000_SUCCESS; 00086 00087 DEBUGFUNC("e1000_init_phy_params_82543"); 00088 00089 if (hw->phy.media_type != e1000_media_type_copper) { 00090 phy->type = e1000_phy_none; 00091 goto out; 00092 } else { 00093 phy->ops.power_up = e1000_power_up_phy_copper; 00094 phy->ops.power_down = e1000_power_down_phy_copper; 00095 } 00096 00097 phy->addr = 1; 00098 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 00099 phy->reset_delay_us = 10000; 00100 phy->type = e1000_phy_m88; 00101 00102 /* Function Pointers */ 00103 phy->ops.check_polarity = e1000_check_polarity_m88; 00104 phy->ops.commit = e1000_phy_sw_reset_generic; 00105 #if 0 00106 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543; 00107 #endif 00108 #if 0 00109 phy->ops.get_cable_length = e1000_get_cable_length_m88; 00110 #endif 00111 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 00112 phy->ops.read_reg = (hw->mac.type == e1000_82543) 00113 ? e1000_read_phy_reg_82543 00114 : e1000_read_phy_reg_m88; 00115 phy->ops.reset = (hw->mac.type == e1000_82543) 00116 ? e1000_phy_hw_reset_82543 00117 : e1000_phy_hw_reset_generic; 00118 phy->ops.write_reg = (hw->mac.type == e1000_82543) 00119 ? e1000_write_phy_reg_82543 00120 : e1000_write_phy_reg_m88; 00121 phy->ops.get_info = e1000_get_phy_info_m88; 00122 00123 /* 00124 * The external PHY of the 82543 can be in a funky state. 00125 * Resetting helps us read the PHY registers for acquiring 00126 * the PHY ID. 00127 */ 00128 if (!e1000_init_phy_disabled_82543(hw)) { 00129 ret_val = phy->ops.reset(hw); 00130 if (ret_val) { 00131 DEBUGOUT("Resetting PHY during init failed.\n"); 00132 goto out; 00133 } 00134 msec_delay(20); 00135 } 00136 00137 ret_val = e1000_get_phy_id(hw); 00138 if (ret_val) 00139 goto out; 00140 00141 /* Verify phy id */ 00142 switch (hw->mac.type) { 00143 case e1000_82543: 00144 if (phy->id != M88E1000_E_PHY_ID) { 00145 ret_val = -E1000_ERR_PHY; 00146 goto out; 00147 } 00148 break; 00149 case e1000_82544: 00150 if (phy->id != M88E1000_I_PHY_ID) { 00151 ret_val = -E1000_ERR_PHY; 00152 goto out; 00153 } 00154 break; 00155 default: 00156 ret_val = -E1000_ERR_PHY; 00157 goto out; 00158 break; 00159 } 00160 00161 out: 00162 return ret_val; 00163 }
e1000_init_nvm_params_82543 - Init NVM func ptrs.
: pointer to the HW structure
Definition at line 169 of file e1000_82543.c.
References e1000_nvm_info::address_bits, DEBUGFUNC, e1000_nvm_info::delay_usec, e1000_nvm_eeprom_microwire, e1000_read_nvm_microwire(), E1000_SUCCESS, e1000_update_nvm_checksum_generic(), e1000_valid_led_default_generic(), e1000_validate_nvm_checksum_generic(), e1000_write_nvm_microwire(), e1000_hw::nvm, e1000_nvm_info::opcode_bits, e1000_nvm_info::ops, e1000_nvm_operations::read, e1000_nvm_info::type, e1000_nvm_operations::update, e1000_nvm_operations::valid_led_default, e1000_nvm_operations::validate, e1000_nvm_info::word_size, and e1000_nvm_operations::write.
Referenced by e1000_init_function_pointers_82543().
00170 { 00171 struct e1000_nvm_info *nvm = &hw->nvm; 00172 00173 DEBUGFUNC("e1000_init_nvm_params_82543"); 00174 00175 nvm->type = e1000_nvm_eeprom_microwire; 00176 nvm->word_size = 64; 00177 nvm->delay_usec = 50; 00178 nvm->address_bits = 6; 00179 nvm->opcode_bits = 3; 00180 00181 /* Function Pointers */ 00182 nvm->ops.read = e1000_read_nvm_microwire; 00183 nvm->ops.update = e1000_update_nvm_checksum_generic; 00184 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 00185 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 00186 nvm->ops.write = e1000_write_nvm_microwire; 00187 00188 return E1000_SUCCESS; 00189 }
e1000_init_mac_params_82543 - Init MAC func ptrs.
: pointer to the HW structure
Definition at line 195 of file e1000_82543.c.
References e1000_mac_operations::check_for_link, e1000_mac_operations::clear_hw_cntrs, e1000_mac_operations::clear_vfta, DEBUGFUNC, e1000_hw::device_id, e1000_82543, e1000_check_for_copper_link_82543(), e1000_check_for_fiber_link_82543(), e1000_clear_hw_cntrs_82543(), e1000_clear_vfta_generic(), E1000_DEV_ID_82543GC_FIBER, E1000_DEV_ID_82544EI_FIBER, e1000_get_bus_info_pci_generic(), e1000_get_speed_and_duplex_copper_generic(), e1000_get_speed_and_duplex_fiber_serdes_generic(), e1000_init_hw_82543(), e1000_led_off_82543(), e1000_led_on_82543(), e1000_media_type_copper, e1000_media_type_fiber, e1000_mta_set_82543(), E1000_RAR_ENTRIES, e1000_reset_hw_82543(), e1000_set_lan_id_multi_port_pci(), e1000_set_tbi_compatibility_82543(), e1000_setup_copper_link_82543(), e1000_setup_fiber_link_82543(), e1000_setup_link_82543(), E1000_SUCCESS, e1000_update_mc_addr_list_generic(), e1000_write_vfta_82543(), e1000_mac_operations::get_bus_info, e1000_mac_operations::get_link_up_info, e1000_mac_operations::init_hw, e1000_mac_operations::led_off, e1000_mac_operations::led_on, e1000_hw::mac, e1000_phy_info::media_type, e1000_mac_info::mta_reg_count, e1000_mac_operations::mta_set, e1000_mac_info::ops, e1000_hw::phy, e1000_mac_info::rar_entry_count, e1000_mac_operations::reset_hw, e1000_mac_operations::set_lan_id, e1000_mac_operations::setup_link, e1000_mac_operations::setup_physical_interface, e1000_mac_info::type, e1000_mac_operations::update_mc_addr_list, and e1000_mac_operations::write_vfta.
Referenced by e1000_init_function_pointers_82543().
00196 { 00197 struct e1000_mac_info *mac = &hw->mac; 00198 00199 DEBUGFUNC("e1000_init_mac_params_82543"); 00200 00201 /* Set media type */ 00202 switch (hw->device_id) { 00203 case E1000_DEV_ID_82543GC_FIBER: 00204 case E1000_DEV_ID_82544EI_FIBER: 00205 hw->phy.media_type = e1000_media_type_fiber; 00206 break; 00207 default: 00208 hw->phy.media_type = e1000_media_type_copper; 00209 break; 00210 } 00211 00212 /* Set mta register count */ 00213 mac->mta_reg_count = 128; 00214 /* Set rar entry count */ 00215 mac->rar_entry_count = E1000_RAR_ENTRIES; 00216 00217 /* Function pointers */ 00218 00219 /* bus type/speed/width */ 00220 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 00221 /* function id */ 00222 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 00223 /* reset */ 00224 mac->ops.reset_hw = e1000_reset_hw_82543; 00225 /* hw initialization */ 00226 mac->ops.init_hw = e1000_init_hw_82543; 00227 /* link setup */ 00228 mac->ops.setup_link = e1000_setup_link_82543; 00229 /* physical interface setup */ 00230 mac->ops.setup_physical_interface = 00231 (hw->phy.media_type == e1000_media_type_copper) 00232 ? e1000_setup_copper_link_82543 00233 : e1000_setup_fiber_link_82543; 00234 /* check for link */ 00235 mac->ops.check_for_link = 00236 (hw->phy.media_type == e1000_media_type_copper) 00237 ? e1000_check_for_copper_link_82543 00238 : e1000_check_for_fiber_link_82543; 00239 /* link info */ 00240 mac->ops.get_link_up_info = 00241 (hw->phy.media_type == e1000_media_type_copper) 00242 ? e1000_get_speed_and_duplex_copper_generic 00243 : e1000_get_speed_and_duplex_fiber_serdes_generic; 00244 /* multicast address update */ 00245 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 00246 /* writing VFTA */ 00247 mac->ops.write_vfta = e1000_write_vfta_82543; 00248 /* clearing VFTA */ 00249 mac->ops.clear_vfta = e1000_clear_vfta_generic; 00250 /* setting MTA */ 00251 mac->ops.mta_set = e1000_mta_set_82543; 00252 /* turn on/off LED */ 00253 mac->ops.led_on = e1000_led_on_82543; 00254 mac->ops.led_off = e1000_led_off_82543; 00255 /* clear hardware counters */ 00256 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543; 00257 00258 /* Set tbi compatibility */ 00259 if ((hw->mac.type != e1000_82543) || 00260 (hw->phy.media_type == e1000_media_type_fiber)) 00261 e1000_set_tbi_compatibility_82543(hw, false); 00262 00263 return E1000_SUCCESS; 00264 }
e1000_read_phy_reg_82543 - Read PHY register : pointer to the HW structure : register offset to be read : pointer to the read data
Reads the PHY at offset and stores the information read to data.
Definition at line 494 of file e1000_82543.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT1, E1000_ERR_PARAM, e1000_shift_in_mdi_bits_82543(), e1000_shift_out_mdi_bits_82543(), E1000_SUCCESS, MAX_PHY_REG_ADDRESS, e1000_hw::phy, PHY_OP_READ, PHY_PREAMBLE, PHY_PREAMBLE_SIZE, PHY_SOF, and u32.
Referenced by e1000_init_phy_params_82543().
00495 { 00496 u32 mdic; 00497 s32 ret_val = E1000_SUCCESS; 00498 00499 DEBUGFUNC("e1000_read_phy_reg_82543"); 00500 00501 if (offset > MAX_PHY_REG_ADDRESS) { 00502 DEBUGOUT1("PHY Address %d is out of range\n", offset); 00503 ret_val = -E1000_ERR_PARAM; 00504 goto out; 00505 } 00506 00507 /* 00508 * We must first send a preamble through the MDIO pin to signal the 00509 * beginning of an MII instruction. This is done by sending 32 00510 * consecutive "1" bits. 00511 */ 00512 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 00513 00514 /* 00515 * Now combine the next few fields that are required for a read 00516 * operation. We use this method instead of calling the 00517 * e1000_shift_out_mdi_bits routine five different times. The format 00518 * of an MII read instruction consists of a shift out of 14 bits and 00519 * is defined as follows: 00520 * <Preamble><SOF><Op Code><Phy Addr><Offset> 00521 * followed by a shift in of 18 bits. This first two bits shifted in 00522 * are TurnAround bits used to avoid contention on the MDIO pin when a 00523 * READ operation is performed. These two bits are thrown away 00524 * followed by a shift in of 16 bits which contains the desired data. 00525 */ 00526 mdic = (offset | (hw->phy.addr << 5) | 00527 (PHY_OP_READ << 10) | (PHY_SOF << 12)); 00528 00529 e1000_shift_out_mdi_bits_82543(hw, mdic, 14); 00530 00531 /* 00532 * Now that we've shifted out the read command to the MII, we need to 00533 * "shift in" the 16-bit value (18 total bits) of the requested PHY 00534 * register address. 00535 */ 00536 *data = e1000_shift_in_mdi_bits_82543(hw); 00537 00538 out: 00539 return ret_val; 00540 }
e1000_write_phy_reg_82543 - Write PHY register : pointer to the HW structure : register offset to be written : pointer to the data to be written at offset
Writes data to the PHY at offset.
Definition at line 550 of file e1000_82543.c.
References e1000_phy_info::addr, DEBUGFUNC, DEBUGOUT1, E1000_ERR_PARAM, e1000_shift_out_mdi_bits_82543(), E1000_SUCCESS, MAX_PHY_REG_ADDRESS, e1000_hw::phy, PHY_OP_WRITE, PHY_PREAMBLE, PHY_PREAMBLE_SIZE, PHY_SOF, PHY_TURNAROUND, and u32.
Referenced by e1000_init_phy_params_82543().
00551 { 00552 u32 mdic; 00553 s32 ret_val = E1000_SUCCESS; 00554 00555 DEBUGFUNC("e1000_write_phy_reg_82543"); 00556 00557 if (offset > MAX_PHY_REG_ADDRESS) { 00558 DEBUGOUT1("PHY Address %d is out of range\n", offset); 00559 ret_val = -E1000_ERR_PARAM; 00560 goto out; 00561 } 00562 00563 /* 00564 * We'll need to use the SW defined pins to shift the write command 00565 * out to the PHY. We first send a preamble to the PHY to signal the 00566 * beginning of the MII instruction. This is done by sending 32 00567 * consecutive "1" bits. 00568 */ 00569 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); 00570 00571 /* 00572 * Now combine the remaining required fields that will indicate a 00573 * write operation. We use this method instead of calling the 00574 * e1000_shift_out_mdi_bits routine for each field in the command. The 00575 * format of a MII write instruction is as follows: 00576 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. 00577 */ 00578 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) | 00579 (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); 00580 mdic <<= 16; 00581 mdic |= (u32) data; 00582 00583 e1000_shift_out_mdi_bits_82543(hw, mdic, 32); 00584 00585 out: 00586 return ret_val; 00587 }
e1000_phy_hw_reset_82543 - PHY hardware reset : pointer to the HW structure
Sets the PHY_RESET_DIR bit in the extended device control register to put the PHY into a reset and waits for completion. Once the reset has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out of reset.
Definition at line 868 of file e1000_82543.c.
References DEBUGFUNC, E1000_CTRL_EXT, E1000_CTRL_EXT_SDP4_DATA, E1000_CTRL_EXT_SDP4_DIR, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_FLUSH, E1000_WRITE_REG, e1000_phy_operations::get_cfg_done, msec_delay, e1000_phy_info::ops, e1000_hw::phy, u32, and usec_delay.
Referenced by e1000_init_phy_params_82543().
00869 { 00870 u32 ctrl_ext; 00871 s32 ret_val; 00872 00873 DEBUGFUNC("e1000_phy_hw_reset_82543"); 00874 00875 /* 00876 * Read the Extended Device Control Register, assert the PHY_RESET_DIR 00877 * bit to put the PHY into reset... 00878 */ 00879 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 00880 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; 00881 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; 00882 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 00883 E1000_WRITE_FLUSH(hw); 00884 00885 msec_delay(10); 00886 00887 /* ...then take it out of reset. */ 00888 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; 00889 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 00890 E1000_WRITE_FLUSH(hw); 00891 00892 usec_delay(150); 00893 00894 if (!(hw->phy.ops.get_cfg_done)) 00895 return E1000_SUCCESS; 00896 00897 ret_val = hw->phy.ops.get_cfg_done(hw); 00898 00899 return ret_val; 00900 }
e1000_reset_hw_82543 - Reset hardware : pointer to the HW structure
This resets the hardware into a known state.
Definition at line 908 of file e1000_82543.c.
References DEBUGFUNC, DEBUGOUT, e1000_82543, E1000_CTRL, E1000_CTRL_RST, E1000_ICR, E1000_IMC, E1000_RCTL, E1000_READ_REG, e1000_set_tbi_sbp_82543(), E1000_SUCCESS, E1000_TCTL, E1000_TCTL_PSP, E1000_WRITE_FLUSH, E1000_WRITE_REG, E1000_WRITE_REG_IO, e1000_hw::mac, msec_delay, e1000_hw::nvm, e1000_nvm_info::ops, e1000_nvm_operations::reload, e1000_mac_info::type, and u32.
Referenced by e1000_init_mac_params_82543().
00909 { 00910 u32 ctrl, icr; 00911 s32 ret_val = E1000_SUCCESS; 00912 00913 DEBUGFUNC("e1000_reset_hw_82543"); 00914 00915 DEBUGOUT("Masking off all interrupts\n"); 00916 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 00917 00918 E1000_WRITE_REG(hw, E1000_RCTL, 0); 00919 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 00920 E1000_WRITE_FLUSH(hw); 00921 00922 e1000_set_tbi_sbp_82543(hw, false); 00923 00924 /* 00925 * Delay to allow any outstanding PCI transactions to complete before 00926 * resetting the device 00927 */ 00928 msec_delay(10); 00929 00930 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00931 00932 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n"); 00933 if (hw->mac.type == e1000_82543) { 00934 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 00935 } else { 00936 /* 00937 * The 82544 can't ACK the 64-bit write when issuing the 00938 * reset, so use IO-mapping as a workaround. 00939 */ 00940 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 00941 } 00942 00943 /* 00944 * After MAC reset, force reload of NVM to restore power-on 00945 * settings to device. 00946 */ 00947 hw->nvm.ops.reload(hw); 00948 msec_delay(2); 00949 00950 /* Masking off and clearing any pending interrupts */ 00951 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 00952 icr = E1000_READ_REG(hw, E1000_ICR); 00953 00954 return ret_val; 00955 }
e1000_init_hw_82543 - Initialize hardware : pointer to the HW structure
This inits the hardware readying it for operation.
Definition at line 963 of file e1000_82543.c.
References e1000_hw::_82543, e1000_mac_operations::clear_vfta, DEBUGFUNC, DEBUGOUT, e1000_hw::dev_spec, e1000_dev_spec_82543::dma_fairness, e1000_82543, e1000_clear_hw_cntrs_82543(), E1000_CTRL, E1000_CTRL_PRIOR, e1000_init_rx_addrs_generic(), E1000_MTA, e1000_pcix_mmrbc_workaround_generic(), E1000_READ_REG, E1000_VET, E1000_WRITE_FLUSH, E1000_WRITE_REG, E1000_WRITE_REG_ARRAY, e1000_hw::mac, e1000_mac_info::mta_reg_count, e1000_mac_info::ops, e1000_mac_info::rar_entry_count, e1000_mac_operations::setup_link, e1000_mac_info::type, u16, and u32.
Referenced by e1000_init_mac_params_82543().
00964 { 00965 struct e1000_mac_info *mac = &hw->mac; 00966 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 00967 u32 ctrl; 00968 s32 ret_val; 00969 u16 i; 00970 00971 DEBUGFUNC("e1000_init_hw_82543"); 00972 00973 /* Disabling VLAN filtering */ 00974 E1000_WRITE_REG(hw, E1000_VET, 0); 00975 mac->ops.clear_vfta(hw); 00976 00977 /* Setup the receive address. */ 00978 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 00979 00980 /* Zero out the Multicast HASH table */ 00981 DEBUGOUT("Zeroing the MTA\n"); 00982 for (i = 0; i < mac->mta_reg_count; i++) { 00983 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 00984 E1000_WRITE_FLUSH(hw); 00985 } 00986 00987 /* 00988 * Set the PCI priority bit correctly in the CTRL register. This 00989 * determines if the adapter gives priority to receives, or if it 00990 * gives equal priority to transmits and receives. 00991 */ 00992 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) { 00993 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00994 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 00995 } 00996 00997 e1000_pcix_mmrbc_workaround_generic(hw); 00998 00999 /* Setup link and flow control */ 01000 ret_val = mac->ops.setup_link(hw); 01001 01002 /* 01003 * Clear all of the statistics registers (clear on read). It is 01004 * important that we do this after we have tried to establish link 01005 * because the symbol error count will increment wildly if there 01006 * is no link. 01007 */ 01008 e1000_clear_hw_cntrs_82543(hw); 01009 01010 return ret_val; 01011 }
e1000_setup_link_82543 - Setup flow control and link settings : pointer to the HW structure
Read the EEPROM to determine the initial polarity value and write the extended device control register with the information before calling the generic setup link function, which does the following: Determines which flow control settings to use, then configures flow control. Calls the appropriate media-specific link configuration function. Assuming the adapter has a valid link partner, a valid link should be established. Assumes the hardware has previously been reset and the transmitter and receiver are not enabled.
Definition at line 1026 of file e1000_82543.c.
References DEBUGFUNC, DEBUGOUT, e1000_82543, E1000_CTRL_EXT, E1000_ERR_NVM, e1000_setup_link_generic(), E1000_WRITE_REG, e1000_hw::mac, e1000_hw::nvm, NVM_INIT_CONTROL2_REG, NVM_SWDPIO_EXT_SHIFT, NVM_WORD0F_SWPDIO_EXT_MASK, e1000_nvm_info::ops, e1000_nvm_operations::read, e1000_mac_info::type, u16, and u32.
Referenced by e1000_init_mac_params_82543().
01027 { 01028 u32 ctrl_ext; 01029 s32 ret_val; 01030 u16 data; 01031 01032 DEBUGFUNC("e1000_setup_link_82543"); 01033 01034 /* 01035 * Take the 4 bits from NVM word 0xF that determine the initial 01036 * polarity value for the SW controlled pins, and setup the 01037 * Extended Device Control reg with that info. 01038 * This is needed because one of the SW controlled pins is used for 01039 * signal detection. So this should be done before phy setup. 01040 */ 01041 if (hw->mac.type == e1000_82543) { 01042 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data); 01043 if (ret_val) { 01044 DEBUGOUT("NVM Read Error\n"); 01045 ret_val = -E1000_ERR_NVM; 01046 goto out; 01047 } 01048 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) << 01049 NVM_SWDPIO_EXT_SHIFT); 01050 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 01051 } 01052 01053 ret_val = e1000_setup_link_generic(hw); 01054 01055 out: 01056 return ret_val; 01057 }
e1000_setup_copper_link_82543 - Configure copper link settings : pointer to the HW structure
Configures the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called.
Definition at line 1067 of file e1000_82543.c.
References e1000_mac_info::autoneg, COPPER_LINK_UP_LIMIT, DEBUGFUNC, DEBUGOUT, e1000_82543, e1000_82544, e1000_config_collision_dist_generic(), e1000_config_fc_after_link_up_generic(), e1000_config_mac_to_phy_82543(), e1000_copper_link_autoneg(), e1000_copper_link_setup_m88(), E1000_CTRL, E1000_CTRL_FRCDPX, E1000_CTRL_FRCSPD, E1000_CTRL_SLU, e1000_phy_has_link_generic(), E1000_READ_REG, E1000_WRITE_REG, e1000_hw::mac, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::reset, e1000_phy_info::reset_disable, e1000_mac_info::type, and u32.
Referenced by e1000_init_mac_params_82543().
01068 { 01069 u32 ctrl; 01070 s32 ret_val; 01071 bool link; 01072 01073 DEBUGFUNC("e1000_setup_copper_link_82543"); 01074 01075 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU; 01076 /* 01077 * With 82543, we need to force speed and duplex on the MAC 01078 * equal to what the PHY speed and duplex configuration is. 01079 * In addition, we need to perform a hardware reset on the 01080 * PHY to take it out of reset. 01081 */ 01082 if (hw->mac.type == e1000_82543) { 01083 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 01084 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01085 ret_val = hw->phy.ops.reset(hw); 01086 if (ret_val) 01087 goto out; 01088 hw->phy.reset_disable = false; 01089 } else { 01090 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 01091 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01092 } 01093 01094 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */ 01095 ret_val = e1000_copper_link_setup_m88(hw); 01096 if (ret_val) 01097 goto out; 01098 01099 if (hw->mac.autoneg) { 01100 /* 01101 * Setup autoneg and flow control advertisement and perform 01102 * autonegotiation. 01103 */ 01104 ret_val = e1000_copper_link_autoneg(hw); 01105 if (ret_val) 01106 goto out; 01107 } else { 01108 /* 01109 * PHY will be set to 10H, 10F, 100H or 100F 01110 * depending on user settings. 01111 */ 01112 #if 0 01113 DEBUGOUT("Forcing Speed and Duplex\n"); 01114 ret_val = e1000_phy_force_speed_duplex_82543(hw); 01115 if (ret_val) { 01116 DEBUGOUT("Error Forcing Speed and Duplex\n"); 01117 goto out; 01118 } 01119 #endif 01120 } 01121 01122 /* 01123 * Check link status. Wait up to 100 microseconds for link to become 01124 * valid. 01125 */ 01126 ret_val = e1000_phy_has_link_generic(hw, 01127 COPPER_LINK_UP_LIMIT, 01128 10, 01129 &link); 01130 if (ret_val) 01131 goto out; 01132 01133 01134 if (link) { 01135 DEBUGOUT("Valid link established!!!\n"); 01136 /* Config the MAC and PHY after link is up */ 01137 if (hw->mac.type == e1000_82544) { 01138 e1000_config_collision_dist_generic(hw); 01139 } else { 01140 ret_val = e1000_config_mac_to_phy_82543(hw); 01141 if (ret_val) 01142 goto out; 01143 } 01144 ret_val = e1000_config_fc_after_link_up_generic(hw); 01145 } else { 01146 DEBUGOUT("Unable to establish link!!!\n"); 01147 } 01148 01149 out: 01150 return ret_val; 01151 }
e1000_setup_fiber_link_82543 - Setup link for fiber : pointer to the HW structure
Configures collision distance and flow control for fiber links. Upon successful setup, poll for link.
Definition at line 1160 of file e1000_82543.c.
References DEBUGFUNC, DEBUGOUT, e1000_commit_fc_settings_generic(), e1000_config_collision_dist_generic(), E1000_CTRL, E1000_CTRL_LRST, E1000_CTRL_SWDPIN1, e1000_poll_fiber_serdes_link_generic(), E1000_READ_REG, E1000_WRITE_FLUSH, E1000_WRITE_REG, msec_delay, and u32.
Referenced by e1000_init_mac_params_82543().
01161 { 01162 u32 ctrl; 01163 s32 ret_val; 01164 01165 DEBUGFUNC("e1000_setup_fiber_link_82543"); 01166 01167 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01168 01169 /* Take the link out of reset */ 01170 ctrl &= ~E1000_CTRL_LRST; 01171 01172 e1000_config_collision_dist_generic(hw); 01173 01174 ret_val = e1000_commit_fc_settings_generic(hw); 01175 if (ret_val) 01176 goto out; 01177 01178 DEBUGOUT("Auto-negotiation enabled\n"); 01179 01180 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01181 E1000_WRITE_FLUSH(hw); 01182 msec_delay(1); 01183 01184 /* 01185 * For these adapters, the SW definable pin 1 is cleared when the 01186 * optics detect a signal. If we have a signal, then poll for a 01187 * "Link-Up" indication. 01188 */ 01189 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 01190 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 01191 } else { 01192 DEBUGOUT("No signal detected\n"); 01193 } 01194 01195 out: 01196 return ret_val; 01197 }
e1000_check_for_copper_link_82543 - Check for link (Copper) : pointer to the HW structure
Checks the phy for link, if link exists, do the following:
Definition at line 1210 of file e1000_82543.c.
References e1000_mac_info::autoneg, DEBUGFUNC, DEBUGOUT, e1000_82544, E1000_ALL_10_SPEED, e1000_check_downshift_generic(), e1000_config_collision_dist_generic(), e1000_config_fc_after_link_up_generic(), e1000_config_mac_to_phy_82543(), E1000_ERR_CONFIG, E1000_ICR, E1000_ICS, E1000_ICS_LSC, E1000_IMC, E1000_IMS, e1000_phy_has_link_generic(), e1000_polarity_reversal_workaround_82543(), E1000_RCTL, E1000_RCTL_SBP, E1000_READ_REG, e1000_set_tbi_sbp_82543(), E1000_SUCCESS, e1000_tbi_compatibility_enabled_82543(), e1000_tbi_sbp_enabled_82543(), E1000_WRITE_REG, e1000_mac_info::forced_speed_duplex, e1000_mac_info::get_link_status, e1000_mac_operations::get_link_up_info, IMS_ENABLE_MASK, e1000_hw::mac, e1000_mac_info::ops, SPEED_1000, e1000_mac_info::type, u16, and u32.
Referenced by e1000_init_mac_params_82543().
01211 { 01212 struct e1000_mac_info *mac = &hw->mac; 01213 u32 icr, rctl; 01214 s32 ret_val; 01215 u16 speed, duplex; 01216 bool link; 01217 01218 DEBUGFUNC("e1000_check_for_copper_link_82543"); 01219 01220 if (!mac->get_link_status) { 01221 ret_val = E1000_SUCCESS; 01222 goto out; 01223 } 01224 01225 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 01226 if (ret_val) 01227 goto out; 01228 01229 if (!link) 01230 goto out; /* No link detected */ 01231 01232 mac->get_link_status = false; 01233 01234 e1000_check_downshift_generic(hw); 01235 01236 /* 01237 * If we are forcing speed/duplex, then we can return since 01238 * we have already determined whether we have link or not. 01239 */ 01240 if (!mac->autoneg) { 01241 /* 01242 * If speed and duplex are forced to 10H or 10F, then we will 01243 * implement the polarity reversal workaround. We disable 01244 * interrupts first, and upon returning, place the devices 01245 * interrupt state to its previous value except for the link 01246 * status change interrupt which will happened due to the 01247 * execution of this workaround. 01248 */ 01249 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) { 01250 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 01251 ret_val = e1000_polarity_reversal_workaround_82543(hw); 01252 icr = E1000_READ_REG(hw, E1000_ICR); 01253 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC)); 01254 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 01255 } 01256 01257 ret_val = -E1000_ERR_CONFIG; 01258 goto out; 01259 } 01260 01261 /* 01262 * We have a M88E1000 PHY and Auto-Neg is enabled. If we 01263 * have Si on board that is 82544 or newer, Auto 01264 * Speed Detection takes care of MAC speed/duplex 01265 * configuration. So we only need to configure Collision 01266 * Distance in the MAC. Otherwise, we need to force 01267 * speed/duplex on the MAC to the current PHY speed/duplex 01268 * settings. 01269 */ 01270 if (mac->type == e1000_82544) 01271 e1000_config_collision_dist_generic(hw); 01272 else { 01273 ret_val = e1000_config_mac_to_phy_82543(hw); 01274 if (ret_val) { 01275 DEBUGOUT("Error configuring MAC to PHY settings\n"); 01276 goto out; 01277 } 01278 } 01279 01280 /* 01281 * Configure Flow Control now that Auto-Neg has completed. 01282 * First, we need to restore the desired flow control 01283 * settings because we may have had to re-autoneg with a 01284 * different link partner. 01285 */ 01286 ret_val = e1000_config_fc_after_link_up_generic(hw); 01287 if (ret_val) { 01288 DEBUGOUT("Error configuring flow control\n"); 01289 } 01290 01291 /* 01292 * At this point we know that we are on copper and we have 01293 * auto-negotiated link. These are conditions for checking the link 01294 * partner capability register. We use the link speed to determine if 01295 * TBI compatibility needs to be turned on or off. If the link is not 01296 * at gigabit speed, then TBI compatibility is not needed. If we are 01297 * at gigabit speed, we turn on TBI compatibility. 01298 */ 01299 if (e1000_tbi_compatibility_enabled_82543(hw)) { 01300 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 01301 if (ret_val) { 01302 DEBUGOUT("Error getting link speed and duplex\n"); 01303 return ret_val; 01304 } 01305 if (speed != SPEED_1000) { 01306 /* 01307 * If link speed is not set to gigabit speed, 01308 * we do not need to enable TBI compatibility. 01309 */ 01310 if (e1000_tbi_sbp_enabled_82543(hw)) { 01311 /* 01312 * If we previously were in the mode, 01313 * turn it off. 01314 */ 01315 e1000_set_tbi_sbp_82543(hw, false); 01316 rctl = E1000_READ_REG(hw, E1000_RCTL); 01317 rctl &= ~E1000_RCTL_SBP; 01318 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 01319 } 01320 } else { 01321 /* 01322 * If TBI compatibility is was previously off, 01323 * turn it on. For compatibility with a TBI link 01324 * partner, we will store bad packets. Some 01325 * frames have an additional byte on the end and 01326 * will look like CRC errors to to the hardware. 01327 */ 01328 if (!e1000_tbi_sbp_enabled_82543(hw)) { 01329 e1000_set_tbi_sbp_82543(hw, true); 01330 rctl = E1000_READ_REG(hw, E1000_RCTL); 01331 rctl |= E1000_RCTL_SBP; 01332 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 01333 } 01334 } 01335 } 01336 out: 01337 return ret_val; 01338 }
e1000_check_for_fiber_link_82543 - Check for link (Fiber) : pointer to the HW structure
Checks for link up on the hardware. If link is not up and we have a signal, then we need to force link up.
Definition at line 1347 of file e1000_82543.c.
References e1000_mac_info::autoneg_failed, DEBUGFUNC, DEBUGOUT, e1000_config_fc_after_link_up_generic(), E1000_CTRL, E1000_CTRL_FD, E1000_CTRL_SLU, E1000_CTRL_SWDPIN1, E1000_READ_REG, E1000_RXCW, E1000_RXCW_C, E1000_STATUS, E1000_STATUS_LU, E1000_SUCCESS, E1000_TXCW, E1000_TXCW_ANE, E1000_WRITE_REG, e1000_hw::mac, e1000_mac_info::serdes_has_link, e1000_mac_info::txcw, and u32.
Referenced by e1000_init_mac_params_82543().
01348 { 01349 struct e1000_mac_info *mac = &hw->mac; 01350 u32 rxcw, ctrl, status; 01351 s32 ret_val = E1000_SUCCESS; 01352 01353 DEBUGFUNC("e1000_check_for_fiber_link_82543"); 01354 01355 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01356 status = E1000_READ_REG(hw, E1000_STATUS); 01357 rxcw = E1000_READ_REG(hw, E1000_RXCW); 01358 01359 /* 01360 * If we don't have link (auto-negotiation failed or link partner 01361 * cannot auto-negotiate), the cable is plugged in (we have signal), 01362 * and our link partner is not trying to auto-negotiate with us (we 01363 * are receiving idles or data), we need to force link up. We also 01364 * need to give auto-negotiation time to complete, in case the cable 01365 * was just plugged in. The autoneg_failed flag does this. 01366 */ 01367 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */ 01368 if ((!(ctrl & E1000_CTRL_SWDPIN1)) && 01369 (!(status & E1000_STATUS_LU)) && 01370 (!(rxcw & E1000_RXCW_C))) { 01371 if (mac->autoneg_failed == 0) { 01372 mac->autoneg_failed = 1; 01373 ret_val = 0; 01374 goto out; 01375 } 01376 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 01377 01378 /* Disable auto-negotiation in the TXCW register */ 01379 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 01380 01381 /* Force link-up and also force full-duplex. */ 01382 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01383 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 01384 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01385 01386 /* Configure Flow Control after forcing link up. */ 01387 ret_val = e1000_config_fc_after_link_up_generic(hw); 01388 if (ret_val) { 01389 DEBUGOUT("Error configuring flow control\n"); 01390 goto out; 01391 } 01392 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 01393 /* 01394 * If we are forcing link and we are receiving /C/ ordered 01395 * sets, re-enable auto-negotiation in the TXCW register 01396 * and disable forced link in the Device Control register 01397 * in an attempt to auto-negotiate with our link partner. 01398 */ 01399 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 01400 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 01401 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 01402 01403 mac->serdes_has_link = true; 01404 } 01405 01406 out: 01407 return ret_val; 01408 }
Referenced by e1000_init_mac_params_82543().
Referenced by e1000_init_mac_params_82543().
e1000_write_vfta_82543 - Write value to VLAN filter table : pointer to the HW structure : the 32-bit offset in which to write the value to.
: the 32-bit value to write at location offset.
This writes a 32-bit value to a 32-bit offset in the VLAN filter table.
Definition at line 1471 of file e1000_82543.c.
References DEBUGFUNC, e1000_82544, E1000_READ_REG_ARRAY, E1000_VFTA, E1000_WRITE_FLUSH, E1000_WRITE_REG_ARRAY, e1000_write_vfta_generic(), e1000_hw::mac, e1000_mac_info::type, and u32.
Referenced by e1000_init_mac_params_82543().
01472 { 01473 u32 temp; 01474 01475 DEBUGFUNC("e1000_write_vfta_82543"); 01476 01477 if ((hw->mac.type == e1000_82544) && (offset & 1)) { 01478 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1); 01479 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 01480 E1000_WRITE_FLUSH(hw); 01481 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp); 01482 E1000_WRITE_FLUSH(hw); 01483 } else { 01484 e1000_write_vfta_generic(hw, offset, value); 01485 } 01486 }
e1000_mta_set_82543 - Set multicast filter table address : pointer to the HW structure : determines the MTA register and bit to set
The multicast table address is a register array of 32-bit registers. The hash_value is used to determine what register the bit is in, the current value is read, the new bit is OR'd in and the new value is written back into the register.
Definition at line 1498 of file e1000_82543.c.
References DEBUGFUNC, e1000_82544, E1000_MTA, e1000_mta_set_generic(), E1000_READ_REG_ARRAY, E1000_WRITE_FLUSH, E1000_WRITE_REG_ARRAY, e1000_hw::mac, e1000_mac_info::mta_reg_count, e1000_mac_info::type, and u32.
Referenced by e1000_init_mac_params_82543().
01499 { 01500 u32 hash_bit, hash_reg, mta, temp; 01501 01502 DEBUGFUNC("e1000_mta_set_82543"); 01503 01504 hash_reg = (hash_value >> 5); 01505 01506 /* 01507 * If we are on an 82544 and we are trying to write an odd offset 01508 * in the MTA, save off the previous entry before writing and 01509 * restore the old value after writing. 01510 */ 01511 if ((hw->mac.type == e1000_82544) && (hash_reg & 1)) { 01512 hash_reg &= (hw->mac.mta_reg_count - 1); 01513 hash_bit = hash_value & 0x1F; 01514 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 01515 mta |= (1 << hash_bit); 01516 temp = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg - 1); 01517 01518 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 01519 E1000_WRITE_FLUSH(hw); 01520 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg - 1, temp); 01521 E1000_WRITE_FLUSH(hw); 01522 } else { 01523 e1000_mta_set_generic(hw, hash_value); 01524 } 01525 }
| static void e1000_clear_hw_cntrs_82543 | ( | struct e1000_hw * | hw | ) | [static] |
e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters : pointer to the HW structure
Clears the hardware counters by reading the counter registers.
Definition at line 1592 of file e1000_82543.c.
References DEBUGFUNC, E1000_ALGNERRC, E1000_CEXTERR, e1000_clear_hw_cntrs_base_generic(), E1000_PRC1023, E1000_PRC127, E1000_PRC1522, E1000_PRC255, E1000_PRC511, E1000_PRC64, E1000_PTC1023, E1000_PTC127, E1000_PTC1522, E1000_PTC255, E1000_PTC511, E1000_PTC64, E1000_READ_REG, E1000_RXERRC, E1000_TNCRS, E1000_TSCTC, and E1000_TSCTFC.
Referenced by e1000_init_hw_82543(), and e1000_init_mac_params_82543().
01593 { 01594 DEBUGFUNC("e1000_clear_hw_cntrs_82543"); 01595 01596 e1000_clear_hw_cntrs_base_generic(hw); 01597 01598 #if 0 01599 E1000_READ_REG(hw, E1000_PRC64); 01600 E1000_READ_REG(hw, E1000_PRC127); 01601 E1000_READ_REG(hw, E1000_PRC255); 01602 E1000_READ_REG(hw, E1000_PRC511); 01603 E1000_READ_REG(hw, E1000_PRC1023); 01604 E1000_READ_REG(hw, E1000_PRC1522); 01605 E1000_READ_REG(hw, E1000_PTC64); 01606 E1000_READ_REG(hw, E1000_PTC127); 01607 E1000_READ_REG(hw, E1000_PTC255); 01608 E1000_READ_REG(hw, E1000_PTC511); 01609 E1000_READ_REG(hw, E1000_PTC1023); 01610 E1000_READ_REG(hw, E1000_PTC1522); 01611 01612 E1000_READ_REG(hw, E1000_ALGNERRC); 01613 E1000_READ_REG(hw, E1000_RXERRC); 01614 E1000_READ_REG(hw, E1000_TNCRS); 01615 E1000_READ_REG(hw, E1000_CEXTERR); 01616 E1000_READ_REG(hw, E1000_TSCTC); 01617 E1000_READ_REG(hw, E1000_TSCTFC); 01618 #endif 01619 }
e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings : pointer to the HW structure
For the 82543 silicon, we need to set the MAC to match the settings of the PHY, even if the PHY is auto-negotiating.
Definition at line 1417 of file e1000_82543.c.
References DEBUGFUNC, e1000_config_collision_dist_generic(), E1000_CTRL, E1000_CTRL_FD, E1000_CTRL_FRCDPX, E1000_CTRL_FRCSPD, E1000_CTRL_ILOS, E1000_CTRL_SPD_100, E1000_CTRL_SPD_1000, E1000_CTRL_SPD_SEL, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, M88E1000_PHY_SPEC_STATUS, M88E1000_PSSR_1000MBS, M88E1000_PSSR_100MBS, M88E1000_PSSR_DPLX, M88E1000_PSSR_SPEED, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, u16, and u32.
Referenced by e1000_check_for_copper_link_82543(), and e1000_setup_copper_link_82543().
01418 { 01419 u32 ctrl; 01420 s32 ret_val = E1000_SUCCESS; 01421 u16 phy_data; 01422 01423 DEBUGFUNC("e1000_config_mac_to_phy_82543"); 01424 01425 if (!(hw->phy.ops.read_reg)) 01426 goto out; 01427 01428 /* Set the bits to force speed and duplex */ 01429 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01430 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 01431 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); 01432 01433 /* 01434 * Set up duplex in the Device Control and Transmit Control 01435 * registers depending on negotiated values. 01436 */ 01437 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 01438 if (ret_val) 01439 goto out; 01440 01441 ctrl &= ~E1000_CTRL_FD; 01442 if (phy_data & M88E1000_PSSR_DPLX) 01443 ctrl |= E1000_CTRL_FD; 01444 01445 e1000_config_collision_dist_generic(hw); 01446 01447 /* 01448 * Set up speed in the Device Control register depending on 01449 * negotiated values. 01450 */ 01451 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) 01452 ctrl |= E1000_CTRL_SPD_1000; 01453 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) 01454 ctrl |= E1000_CTRL_SPD_100; 01455 01456 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01457 01458 out: 01459 return ret_val; 01460 }
e1000_init_phy_disabled_82543 - Returns init PHY status : pointer to the HW structure
Returns the current status of whether PHY initialization is disabled. True if PHY initialization is disabled else false.
Definition at line 388 of file e1000_82543.c.
References e1000_hw::_82543, DEBUGFUNC, e1000_hw::dev_spec, e1000_82543, e1000_dev_spec_82543::init_phy_disabled, e1000_hw::mac, and e1000_mac_info::type.
Referenced by e1000_init_phy_params_82543().
00389 { 00390 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 00391 bool ret_val; 00392 00393 DEBUGFUNC("e1000_init_phy_disabled_82543"); 00394 00395 if (hw->mac.type != e1000_82543) { 00396 ret_val = false; 00397 goto out; 00398 } 00399 00400 ret_val = dev_spec->init_phy_disabled; 00401 00402 out: 00403 return ret_val; 00404 }
e1000_lower_mdi_clk_82543 - Lower Management Data Input clock : pointer to the HW structure : pointer to the control register
Lower the management data input clock by clearing the MDC bit in the control register.
Definition at line 616 of file e1000_82543.c.
References E1000_CTRL, E1000_CTRL_MDC, E1000_WRITE_FLUSH, E1000_WRITE_REG, and usec_delay.
Referenced by e1000_shift_in_mdi_bits_82543(), and e1000_shift_out_mdi_bits_82543().
00617 { 00618 /* 00619 * Lower the clock input to the Management Data Clock (by clearing the 00620 * MDC bit), and then delay a sufficient amount of time. 00621 */ 00622 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC)); 00623 E1000_WRITE_FLUSH(hw); 00624 usec_delay(10); 00625 }
e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal : pointer to the HW structure
When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity inadvertently. To workaround the issue, we disable the transmitter on the PHY until we have established the link partner's link parameters.
Definition at line 774 of file e1000_82543.c.
References e1000_phy_has_link_generic(), E1000_SUCCESS, M88E1000_PHY_GEN_CONTROL, M88E1000_PHY_PAGE_SELECT, MII_SR_LINK_STATUS, msec_delay_irq, e1000_phy_info::ops, e1000_hw::phy, PHY_FORCE_TIME, PHY_STATUS, e1000_phy_operations::read_reg, u16, and e1000_phy_operations::write_reg.
Referenced by e1000_check_for_copper_link_82543().
00775 { 00776 s32 ret_val = E1000_SUCCESS; 00777 u16 mii_status_reg; 00778 u16 i; 00779 bool link; 00780 00781 if (!(hw->phy.ops.write_reg)) 00782 goto out; 00783 00784 /* Polarity reversal workaround for forced 10F/10H links. */ 00785 00786 /* Disable the transmitter on the PHY */ 00787 00788 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 00789 if (ret_val) 00790 goto out; 00791 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); 00792 if (ret_val) 00793 goto out; 00794 00795 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 00796 if (ret_val) 00797 goto out; 00798 00799 /* 00800 * This loop will early-out if the NO link condition has been met. 00801 * In other words, DO NOT use e1000_phy_has_link_generic() here. 00802 */ 00803 for (i = PHY_FORCE_TIME; i > 0; i--) { 00804 /* 00805 * Read the MII Status Register and wait for Link Status bit 00806 * to be clear. 00807 */ 00808 00809 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 00810 if (ret_val) 00811 goto out; 00812 00813 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 00814 if (ret_val) 00815 goto out; 00816 00817 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) 00818 break; 00819 msec_delay_irq(100); 00820 } 00821 00822 /* Recommended delay time after link has been lost */ 00823 msec_delay_irq(1000); 00824 00825 /* Now we will re-enable the transmitter on the PHY */ 00826 00827 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); 00828 if (ret_val) 00829 goto out; 00830 msec_delay_irq(50); 00831 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); 00832 if (ret_val) 00833 goto out; 00834 msec_delay_irq(50); 00835 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); 00836 if (ret_val) 00837 goto out; 00838 msec_delay_irq(50); 00839 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); 00840 if (ret_val) 00841 goto out; 00842 00843 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); 00844 if (ret_val) 00845 goto out; 00846 00847 /* 00848 * Read the MII Status Register and wait for Link Status bit 00849 * to be set. 00850 */ 00851 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link); 00852 if (ret_val) 00853 goto out; 00854 00855 out: 00856 return ret_val; 00857 }
e1000_raise_mdi_clk_82543 - Raise Management Data Input clock : pointer to the HW structure : pointer to the control register
Raise the management data input clock by setting the MDC bit in the control register.
Definition at line 597 of file e1000_82543.c.
References E1000_CTRL, E1000_CTRL_MDC, E1000_WRITE_FLUSH, E1000_WRITE_REG, and usec_delay.
Referenced by e1000_shift_in_mdi_bits_82543(), and e1000_shift_out_mdi_bits_82543().
00598 { 00599 /* 00600 * Raise the clock input to the Management Data Clock (by setting the 00601 * MDC bit), and then delay a sufficient amount of time. 00602 */ 00603 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC)); 00604 E1000_WRITE_FLUSH(hw); 00605 usec_delay(10); 00606 }
e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY : pointer to the HW structure
In order to read a register from the PHY, we need to shift 18 bits in from the PHY. Bits are "shifted in" by raising the clock input to the PHY (setting the MDC bit), and then reading the value of the data out MDIO bit.
Definition at line 687 of file e1000_82543.c.
References E1000_CTRL, E1000_CTRL_MDIO, E1000_CTRL_MDIO_DIR, e1000_lower_mdi_clk_82543(), e1000_raise_mdi_clk_82543(), E1000_READ_REG, E1000_WRITE_FLUSH, E1000_WRITE_REG, u16, u32, and u8.
Referenced by e1000_read_phy_reg_82543().
00688 { 00689 u32 ctrl; 00690 u16 data = 0; 00691 u8 i; 00692 00693 /* 00694 * In order to read a register from the PHY, we need to shift in a 00695 * total of 18 bits from the PHY. The first two bit (turnaround) 00696 * times are used to avoid contention on the MDIO pin when a read 00697 * operation is performed. These two bits are ignored by us and 00698 * thrown away. Bits are "shifted in" by raising the input to the 00699 * Management Data Clock (setting the MDC bit) and then reading the 00700 * value of the MDIO bit. 00701 */ 00702 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00703 00704 /* 00705 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as 00706 * input. 00707 */ 00708 ctrl &= ~E1000_CTRL_MDIO_DIR; 00709 ctrl &= ~E1000_CTRL_MDIO; 00710 00711 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 00712 E1000_WRITE_FLUSH(hw); 00713 00714 /* 00715 * Raise and lower the clock before reading in the data. This accounts 00716 * for the turnaround bits. The first clock occurred when we clocked 00717 * out the last bit of the Register Address. 00718 */ 00719 e1000_raise_mdi_clk_82543(hw, &ctrl); 00720 e1000_lower_mdi_clk_82543(hw, &ctrl); 00721 00722 for (data = 0, i = 0; i < 16; i++) { 00723 data <<= 1; 00724 e1000_raise_mdi_clk_82543(hw, &ctrl); 00725 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00726 /* Check to see if we shifted in a "1". */ 00727 if (ctrl & E1000_CTRL_MDIO) 00728 data |= 1; 00729 e1000_lower_mdi_clk_82543(hw, &ctrl); 00730 } 00731 00732 e1000_raise_mdi_clk_82543(hw, &ctrl); 00733 e1000_lower_mdi_clk_82543(hw, &ctrl); 00734 00735 return data; 00736 }
e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY : pointer to the HW structure : data to send to the PHY : number of bits to shift out
We need to shift 'count' bits out to the PHY. So, the value in the "data" parameter will be shifted out to the PHY one bit at a time. In order to do this, "data" must be broken down into bits.
Definition at line 637 of file e1000_82543.c.
References E1000_CTRL, E1000_CTRL_MDC_DIR, E1000_CTRL_MDIO, E1000_CTRL_MDIO_DIR, e1000_lower_mdi_clk_82543(), e1000_raise_mdi_clk_82543(), E1000_READ_REG, E1000_WRITE_FLUSH, E1000_WRITE_REG, u32, and usec_delay.
Referenced by e1000_read_phy_reg_82543(), and e1000_write_phy_reg_82543().
00639 { 00640 u32 ctrl, mask; 00641 00642 /* 00643 * We need to shift "count" number of bits out to the PHY. So, the 00644 * value in the "data" parameter will be shifted out to the PHY one 00645 * bit at a time. In order to do this, "data" must be broken down 00646 * into bits. 00647 */ 00648 mask = 0x01; 00649 mask <<= (count -1); 00650 00651 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00652 00653 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ 00654 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); 00655 00656 while (mask) { 00657 /* 00658 * A "1" is shifted out to the PHY by setting the MDIO bit to 00659 * "1" and then raising and lowering the Management Data Clock. 00660 * A "0" is shifted out to the PHY by setting the MDIO bit to 00661 * "0" and then raising and lowering the clock. 00662 */ 00663 if (data & mask) ctrl |= E1000_CTRL_MDIO; 00664 else ctrl &= ~E1000_CTRL_MDIO; 00665 00666 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 00667 E1000_WRITE_FLUSH(hw); 00668 00669 usec_delay(10); 00670 00671 e1000_raise_mdi_clk_82543(hw, &ctrl); 00672 e1000_lower_mdi_clk_82543(hw, &ctrl); 00673 00674 mask >>= 1; 00675 } 00676 }
e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status : pointer to the HW structure
Returns the current status of 10-bit Interface (TBI) compatibility (enabled/disabled).
Definition at line 288 of file e1000_82543.c.
References e1000_hw::_82543, DEBUGFUNC, DEBUGOUT, e1000_hw::dev_spec, e1000_82543, e1000_hw::mac, TBI_COMPAT_ENABLED, e1000_dev_spec_82543::tbi_compatibility, and e1000_mac_info::type.
Referenced by e1000_check_for_copper_link_82543(), and e1000_set_tbi_sbp_82543().
00289 { 00290 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 00291 bool state = false; 00292 00293 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543"); 00294 00295 if (hw->mac.type != e1000_82543) { 00296 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 00297 goto out; 00298 } 00299 00300 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED) 00301 ? true : false; 00302 00303 out: 00304 return state; 00305 }
e1000_set_tbi_compatibility_82543 - Set TBI compatibility : pointer to the HW structure : enable/disable TBI compatibility
Enables or disabled 10-bit Interface (TBI) compatibility.
Definition at line 314 of file e1000_82543.c.
References e1000_hw::_82543, DEBUGFUNC, DEBUGOUT, e1000_hw::dev_spec, e1000_82543, e1000_hw::mac, TBI_COMPAT_ENABLED, e1000_dev_spec_82543::tbi_compatibility, and e1000_mac_info::type.
Referenced by e1000_init_mac_params_82543().
00315 { 00316 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 00317 00318 DEBUGFUNC("e1000_set_tbi_compatibility_82543"); 00319 00320 if (hw->mac.type != e1000_82543) { 00321 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 00322 goto out; 00323 } 00324 00325 if (state) 00326 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED; 00327 else 00328 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED; 00329 00330 out: 00331 return; 00332 }
e1000_set_tbi_sbp_82543 - Set TBI SBP : pointer to the HW structure : enable/disable TBI store bad packet
Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
Definition at line 367 of file e1000_82543.c.
References e1000_hw::_82543, DEBUGFUNC, e1000_hw::dev_spec, e1000_tbi_compatibility_enabled_82543(), e1000_dev_spec_82543::tbi_compatibility, and TBI_SBP_ENABLED.
Referenced by e1000_check_for_copper_link_82543(), and e1000_reset_hw_82543().
00368 { 00369 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 00370 00371 DEBUGFUNC("e1000_set_tbi_sbp_82543"); 00372 00373 if (state && e1000_tbi_compatibility_enabled_82543(hw)) 00374 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED; 00375 else 00376 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED; 00377 00378 return; 00379 }
| void e1000_init_function_pointers_82543 | ( | struct e1000_hw * | hw | ) |
e1000_init_function_pointers_82543 - Init func ptrs.
: pointer to the HW structure
Called to initialize all function pointers and parameters.
Definition at line 272 of file e1000_82543.c.
References DEBUGFUNC, e1000_init_mac_params_82543(), e1000_init_nvm_params_82543(), e1000_init_phy_params_82543(), e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::nvm, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, and e1000_hw::phy.
Referenced by e1000_setup_init_funcs().
00273 { 00274 DEBUGFUNC("e1000_init_function_pointers_82543"); 00275 00276 hw->mac.ops.init_params = e1000_init_mac_params_82543; 00277 hw->nvm.ops.init_params = e1000_init_nvm_params_82543; 00278 hw->phy.ops.init_params = e1000_init_phy_params_82543; 00279 }
e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status : pointer to the HW structure
Returns the current status of 10-bit Interface (TBI) store bad packet (SBP) (enabled/disabled).
Definition at line 341 of file e1000_82543.c.
References e1000_hw::_82543, DEBUGFUNC, DEBUGOUT, e1000_hw::dev_spec, e1000_82543, e1000_hw::mac, e1000_dev_spec_82543::tbi_compatibility, TBI_SBP_ENABLED, and e1000_mac_info::type.
Referenced by e1000_check_for_copper_link_82543().
00342 { 00343 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543; 00344 bool state = false; 00345 00346 DEBUGFUNC("e1000_tbi_sbp_enabled_82543"); 00347 00348 if (hw->mac.type != e1000_82543) { 00349 DEBUGOUT("TBI compatibility workaround for 82543 only.\n"); 00350 goto out; 00351 } 00352 00353 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED) 00354 ? true : false; 00355 00356 out: 00357 return state; 00358 }
e1000_led_on_82543 - Turn on SW controllable LED : pointer to the HW structure
Turns the SW defined LED on.
Definition at line 1533 of file e1000_82543.c.
References DEBUGFUNC, e1000_82544, E1000_CTRL, E1000_CTRL_SWDPIN0, E1000_CTRL_SWDPIO0, e1000_media_type_copper, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::mac, e1000_phy_info::media_type, e1000_hw::phy, e1000_mac_info::type, and u32.
01534 { 01535 #if 0 01536 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01537 01538 DEBUGFUNC("e1000_led_on_82543"); 01539 01540 if (hw->mac.type == e1000_82544 && 01541 hw->phy.media_type == e1000_media_type_copper) { 01542 /* Clear SW-definable Pin 0 to turn on the LED */ 01543 ctrl &= ~E1000_CTRL_SWDPIN0; 01544 ctrl |= E1000_CTRL_SWDPIO0; 01545 } else { 01546 /* Fiber 82544 and all 82543 use this method */ 01547 ctrl |= E1000_CTRL_SWDPIN0; 01548 ctrl |= E1000_CTRL_SWDPIO0; 01549 } 01550 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01551 01552 return E1000_SUCCESS; 01553 #endif 01554 return 0; 01555 }
e1000_led_off_82543 - Turn off SW controllable LED : pointer to the HW structure
Turns the SW defined LED off.
Definition at line 1563 of file e1000_82543.c.
References DEBUGFUNC, e1000_82544, E1000_CTRL, E1000_CTRL_SWDPIN0, E1000_CTRL_SWDPIO0, e1000_media_type_copper, E1000_READ_REG, E1000_SUCCESS, E1000_WRITE_REG, e1000_hw::mac, e1000_phy_info::media_type, e1000_hw::phy, e1000_mac_info::type, and u32.
01564 { 01565 #if 0 01566 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 01567 01568 DEBUGFUNC("e1000_led_off_82543"); 01569 01570 if (hw->mac.type == e1000_82544 && 01571 hw->phy.media_type == e1000_media_type_copper) { 01572 /* Set SW-definable Pin 0 to turn off the LED */ 01573 ctrl |= E1000_CTRL_SWDPIN0; 01574 ctrl |= E1000_CTRL_SWDPIO0; 01575 } else { 01576 ctrl &= ~E1000_CTRL_SWDPIN0; 01577 ctrl |= E1000_CTRL_SWDPIO0; 01578 } 01579 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 01580 01581 return E1000_SUCCESS; 01582 #endif 01583 return 0; 01584 }
struct pci_device_id e1000_82543_nics[] [static] |
Initial value:
{
PCI_ROM(0x8086, 0x1001, "E1000_DEV_ID_82543GC_FIBER", "E1000_DEV_ID_82543GC_FIBER", e1000_82543),
PCI_ROM(0x8086, 0x1004, "E1000_DEV_ID_82543GC_COPPER", "E1000_DEV_ID_82543GC_COPPER", e1000_82543),
PCI_ROM(0x8086, 0x1008, "E1000_DEV_ID_82544EI_COPPER", "E1000_DEV_ID_82544EI_COPPER", e1000_82544),
PCI_ROM(0x8086, 0x1009, "E1000_DEV_ID_82544EI_FIBER", "E1000_DEV_ID_82544EI_FIBER", e1000_82544),
PCI_ROM(0x8086, 0x100C, "E1000_DEV_ID_82544GC_COPPER", "E1000_DEV_ID_82544GC_COPPER", e1000_82544),
PCI_ROM(0x8086, 0x100D, "E1000_DEV_ID_82544GC_LOM", "E1000_DEV_ID_82544GC_LOM", e1000_82544),
}
Definition at line 1621 of file e1000_82543.c.
| struct pci_driver e1000_82543_driver __pci_driver |
Initial value:
{
.ids = e1000_82543_nics,
.id_count = (sizeof (e1000_82543_nics) / sizeof (e1000_82543_nics[0])),
.probe = e1000_probe,
.remove = e1000_remove,
}
Definition at line 1630 of file e1000_82543.c.
1.5.7.1