#include "e1000_api.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (GPL2_OR_LATER) | |
| static s32 | e1000_init_phy_params_82541 (struct e1000_hw *hw) |
| e1000_init_phy_params_82541 - Init PHY func ptrs. | |
| static s32 | e1000_init_nvm_params_82541 (struct e1000_hw *hw) |
| e1000_init_nvm_params_82541 - Init NVM func ptrs. | |
| static s32 | e1000_init_mac_params_82541 (struct e1000_hw *hw) |
| e1000_init_mac_params_82541 - Init MAC func ptrs. | |
| static s32 | e1000_reset_hw_82541 (struct e1000_hw *hw) |
| e1000_reset_hw_82541 - Reset hardware : pointer to the HW structure | |
| static s32 | e1000_init_hw_82541 (struct e1000_hw *hw) |
| e1000_init_hw_82541 - Initialize hardware : pointer to the HW structure | |
| static s32 | e1000_get_link_up_info_82541 (struct e1000_hw *hw, u16 *speed, u16 *duplex) |
| e1000_get_link_up_info_82541 - Report speed and duplex : pointer to the HW structure : pointer to speed buffer : pointer to duplex buffer | |
| static s32 | e1000_phy_hw_reset_82541 (struct e1000_hw *hw) |
| e1000_phy_hw_reset_82541 - PHY hardware reset : pointer to the HW structure | |
| static s32 | e1000_setup_copper_link_82541 (struct e1000_hw *hw) |
| e1000_setup_copper_link_82541 - Configure copper link settings : pointer to the HW structure | |
| static s32 | e1000_check_for_link_82541 (struct e1000_hw *hw) |
| e1000_check_for_link_82541 - Check/Store link connection : pointer to the HW structure | |
| static s32 | e1000_set_d3_lplu_state_82541 (struct e1000_hw *hw, bool active) |
| e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu | |
| static s32 | e1000_setup_led_82541 (struct e1000_hw *hw) |
| static s32 | e1000_cleanup_led_82541 (struct e1000_hw *hw) |
| static void | e1000_clear_hw_cntrs_82541 (struct e1000_hw *hw) |
| e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters : pointer to the HW structure | |
| static s32 | e1000_phy_init_script_82541 (struct e1000_hw *hw) |
| e1000_phy_init_script_82541 - Initialize GbE PHY : pointer to the HW structure | |
| static void | e1000_power_down_phy_copper_82541 (struct e1000_hw *hw) |
| e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down : pointer to the HW structure | |
| void | e1000_init_function_pointers_82541 (struct e1000_hw *hw) |
| e1000_init_function_pointers_82541 - Init func ptrs. | |
| static s32 | e1000_setup_led_82541 (struct e1000_hw *hw __unused) |
| e1000_setup_led_82541 - Configures SW controllable LED : pointer to the HW structure | |
| static s32 | e1000_cleanup_led_82541 (struct e1000_hw *hw __unused) |
| e1000_cleanup_led_82541 - Set LED config to default operation : pointer to the HW structure | |
Variables | |
| static struct pci_device_id | e1000_82541_nics [] |
| struct pci_driver e1000_82541_driver | __pci_driver |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
e1000_init_phy_params_82541 - Init PHY func ptrs.
: pointer to the HW structure
Definition at line 85 of file e1000_82541.c.
References e1000_phy_info::addr, AUTONEG_ADVERTISE_SPEED_DEFAULT, e1000_phy_info::autoneg_mask, e1000_phy_operations::check_polarity, DEBUGFUNC, e1000_check_polarity_igp(), E1000_ERR_PHY, e1000_get_cfg_done_generic(), e1000_get_phy_id(), e1000_get_phy_info_igp(), e1000_phy_hw_reset_82541(), e1000_phy_igp, e1000_power_down_phy_copper_82541(), e1000_power_up_phy_copper(), e1000_read_phy_reg_igp(), e1000_set_d3_lplu_state_82541(), E1000_SUCCESS, e1000_write_phy_reg_igp(), e1000_phy_operations::get_cfg_done, e1000_phy_operations::get_info, e1000_phy_info::id, IGP01E1000_I_PHY_ID, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::power_down, e1000_phy_operations::power_up, e1000_phy_operations::read_reg, e1000_phy_operations::reset, e1000_phy_info::reset_delay_us, e1000_phy_operations::set_d3_lplu_state, e1000_phy_info::type, and e1000_phy_operations::write_reg.
Referenced by e1000_init_function_pointers_82541().
00086 { 00087 struct e1000_phy_info *phy = &hw->phy; 00088 s32 ret_val = E1000_SUCCESS; 00089 00090 DEBUGFUNC("e1000_init_phy_params_82541"); 00091 00092 phy->addr = 1; 00093 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 00094 phy->reset_delay_us = 10000; 00095 phy->type = e1000_phy_igp; 00096 00097 /* Function Pointers */ 00098 phy->ops.check_polarity = e1000_check_polarity_igp; 00099 #if 0 00100 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 00101 #endif 00102 #if 0 00103 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 00104 #endif 00105 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 00106 phy->ops.get_info = e1000_get_phy_info_igp; 00107 phy->ops.read_reg = e1000_read_phy_reg_igp; 00108 phy->ops.reset = e1000_phy_hw_reset_82541; 00109 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 00110 phy->ops.write_reg = e1000_write_phy_reg_igp; 00111 phy->ops.power_up = e1000_power_up_phy_copper; 00112 phy->ops.power_down = e1000_power_down_phy_copper_82541; 00113 00114 ret_val = e1000_get_phy_id(hw); 00115 if (ret_val) 00116 goto out; 00117 00118 /* Verify phy id */ 00119 if (phy->id != IGP01E1000_I_PHY_ID) { 00120 ret_val = -E1000_ERR_PHY; 00121 goto out; 00122 } 00123 00124 out: 00125 return ret_val; 00126 }
e1000_init_nvm_params_82541 - Init NVM func ptrs.
: pointer to the HW structure
Definition at line 132 of file e1000_82541.c.
References e1000_nvm_operations::acquire, e1000_nvm_info::address_bits, DEBUGFUNC, e1000_nvm_info::delay_usec, e1000_acquire_nvm_generic(), E1000_EECD, E1000_EECD_ADDR_BITS, E1000_EECD_SIZE, E1000_EECD_TYPE, e1000_nvm_eeprom_microwire, e1000_nvm_eeprom_spi, e1000_nvm_override_microwire_large, e1000_nvm_override_microwire_small, e1000_nvm_override_spi_large, e1000_nvm_override_spi_small, e1000_read_nvm_microwire(), e1000_read_nvm_spi(), E1000_READ_REG, e1000_release_nvm_generic(), E1000_SUCCESS, e1000_update_nvm_checksum_generic(), e1000_valid_led_default_generic(), e1000_validate_nvm_checksum_generic(), e1000_write_nvm_microwire(), e1000_write_nvm_spi(), e1000_hw::nvm, NVM_CFG, NVM_SIZE_MASK, NVM_SIZE_SHIFT, NVM_WORD_SIZE_BASE_SHIFT_82541, e1000_nvm_info::opcode_bits, e1000_nvm_info::ops, e1000_nvm_info::override, e1000_nvm_info::page_size, e1000_nvm_operations::read, e1000_nvm_operations::release, size, e1000_nvm_info::type, u16, u32, e1000_nvm_operations::update, e1000_nvm_operations::valid_led_default, e1000_nvm_operations::validate, e1000_nvm_info::word_size, and e1000_nvm_operations::write.
Referenced by e1000_init_function_pointers_82541().
00133 { 00134 struct e1000_nvm_info *nvm = &hw->nvm; 00135 s32 ret_val = E1000_SUCCESS; 00136 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 00137 u16 size; 00138 00139 DEBUGFUNC("e1000_init_nvm_params_82541"); 00140 00141 switch (nvm->override) { 00142 case e1000_nvm_override_spi_large: 00143 nvm->type = e1000_nvm_eeprom_spi; 00144 eecd |= E1000_EECD_ADDR_BITS; 00145 break; 00146 case e1000_nvm_override_spi_small: 00147 nvm->type = e1000_nvm_eeprom_spi; 00148 eecd &= ~E1000_EECD_ADDR_BITS; 00149 break; 00150 case e1000_nvm_override_microwire_large: 00151 nvm->type = e1000_nvm_eeprom_microwire; 00152 eecd |= E1000_EECD_SIZE; 00153 break; 00154 case e1000_nvm_override_microwire_small: 00155 nvm->type = e1000_nvm_eeprom_microwire; 00156 eecd &= ~E1000_EECD_SIZE; 00157 break; 00158 default: 00159 nvm->type = eecd & E1000_EECD_TYPE 00160 ? e1000_nvm_eeprom_spi 00161 : e1000_nvm_eeprom_microwire; 00162 break; 00163 } 00164 00165 if (nvm->type == e1000_nvm_eeprom_spi) { 00166 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 00167 ? 16 : 8; 00168 nvm->delay_usec = 1; 00169 nvm->opcode_bits = 8; 00170 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 00171 ? 32 : 8; 00172 00173 /* Function Pointers */ 00174 nvm->ops.acquire = e1000_acquire_nvm_generic; 00175 nvm->ops.read = e1000_read_nvm_spi; 00176 nvm->ops.release = e1000_release_nvm_generic; 00177 nvm->ops.update = e1000_update_nvm_checksum_generic; 00178 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 00179 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 00180 nvm->ops.write = e1000_write_nvm_spi; 00181 00182 /* 00183 * nvm->word_size must be discovered after the pointers 00184 * are set so we can verify the size from the nvm image 00185 * itself. Temporarily set it to a dummy value so the 00186 * read will work. 00187 */ 00188 nvm->word_size = 64; 00189 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 00190 if (ret_val) 00191 goto out; 00192 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 00193 /* 00194 * if size != 0, it can be added to a constant and become 00195 * the left-shift value to set the word_size. Otherwise, 00196 * word_size stays at 64. 00197 */ 00198 if (size) { 00199 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 00200 nvm->word_size = 1 << size; 00201 } 00202 } else { 00203 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 00204 ? 8 : 6; 00205 nvm->delay_usec = 50; 00206 nvm->opcode_bits = 3; 00207 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 00208 ? 256 : 64; 00209 00210 /* Function Pointers */ 00211 nvm->ops.acquire = e1000_acquire_nvm_generic; 00212 nvm->ops.read = e1000_read_nvm_microwire; 00213 nvm->ops.release = e1000_release_nvm_generic; 00214 nvm->ops.update = e1000_update_nvm_checksum_generic; 00215 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 00216 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 00217 nvm->ops.write = e1000_write_nvm_microwire; 00218 } 00219 00220 out: 00221 return ret_val; 00222 }
e1000_init_mac_params_82541 - Init MAC func ptrs.
: pointer to the HW structure
Definition at line 228 of file e1000_82541.c.
References e1000_mac_info::asf_firmware_present, e1000_mac_operations::check_for_link, e1000_mac_operations::cleanup_led, e1000_mac_operations::clear_hw_cntrs, e1000_mac_operations::clear_vfta, DEBUGFUNC, e1000_check_for_link_82541(), e1000_cleanup_led_82541(), e1000_clear_hw_cntrs_82541(), e1000_clear_vfta_generic(), e1000_get_bus_info_pci_generic(), e1000_get_link_up_info_82541(), e1000_id_led_init_generic(), e1000_init_hw_82541(), e1000_led_off_generic(), e1000_led_on_generic(), e1000_media_type_copper, e1000_mta_set_generic(), E1000_RAR_ENTRIES, e1000_reset_hw_82541(), e1000_set_lan_id_single_port(), e1000_setup_copper_link_82541(), e1000_setup_led_82541(), e1000_setup_link_generic(), E1000_SUCCESS, e1000_update_mc_addr_list_generic(), e1000_write_vfta_generic(), e1000_mac_operations::get_bus_info, e1000_mac_operations::get_link_up_info, e1000_mac_operations::id_led_init, e1000_mac_operations::init_hw, e1000_mac_operations::led_off, e1000_mac_operations::led_on, e1000_hw::mac, e1000_phy_info::media_type, e1000_mac_info::mta_reg_count, e1000_mac_operations::mta_set, e1000_mac_info::ops, e1000_hw::phy, e1000_mac_info::rar_entry_count, e1000_mac_operations::reset_hw, e1000_mac_operations::set_lan_id, e1000_mac_operations::setup_led, e1000_mac_operations::setup_link, e1000_mac_operations::setup_physical_interface, e1000_mac_operations::update_mc_addr_list, and e1000_mac_operations::write_vfta.
Referenced by e1000_init_function_pointers_82541().
00229 { 00230 struct e1000_mac_info *mac = &hw->mac; 00231 00232 DEBUGFUNC("e1000_init_mac_params_82541"); 00233 00234 /* Set media type */ 00235 hw->phy.media_type = e1000_media_type_copper; 00236 /* Set mta register count */ 00237 mac->mta_reg_count = 128; 00238 /* Set rar entry count */ 00239 mac->rar_entry_count = E1000_RAR_ENTRIES; 00240 /* Set if part includes ASF firmware */ 00241 mac->asf_firmware_present = true; 00242 00243 /* Function Pointers */ 00244 00245 /* bus type/speed/width */ 00246 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 00247 /* function id */ 00248 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 00249 /* reset */ 00250 mac->ops.reset_hw = e1000_reset_hw_82541; 00251 /* hw initialization */ 00252 mac->ops.init_hw = e1000_init_hw_82541; 00253 /* link setup */ 00254 mac->ops.setup_link = e1000_setup_link_generic; 00255 /* physical interface link setup */ 00256 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 00257 /* check for link */ 00258 mac->ops.check_for_link = e1000_check_for_link_82541; 00259 /* link info */ 00260 mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 00261 /* multicast address update */ 00262 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 00263 /* writing VFTA */ 00264 mac->ops.write_vfta = e1000_write_vfta_generic; 00265 /* clearing VFTA */ 00266 mac->ops.clear_vfta = e1000_clear_vfta_generic; 00267 /* setting MTA */ 00268 mac->ops.mta_set = e1000_mta_set_generic; 00269 /* ID LED init */ 00270 mac->ops.id_led_init = e1000_id_led_init_generic; 00271 /* setup LED */ 00272 mac->ops.setup_led = e1000_setup_led_82541; 00273 /* cleanup LED */ 00274 mac->ops.cleanup_led = e1000_cleanup_led_82541; 00275 /* turn on/off LED */ 00276 mac->ops.led_on = e1000_led_on_generic; 00277 mac->ops.led_off = e1000_led_off_generic; 00278 /* clear hardware counters */ 00279 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 00280 00281 return E1000_SUCCESS; 00282 }
e1000_reset_hw_82541 - Reset hardware : pointer to the HW structure
This resets the hardware into a known state.
Definition at line 305 of file e1000_82541.c.
References DEBUGFUNC, DEBUGOUT, e1000_82541, e1000_82541_rev_2, e1000_82547, E1000_CTRL, E1000_CTRL_PHY_RST, E1000_CTRL_RST, E1000_ICR, E1000_IMC, E1000_LEDCTL, E1000_MANC, E1000_MANC_ARP_EN, e1000_phy_init_script_82541(), E1000_RCTL, E1000_READ_REG, E1000_SUCCESS, E1000_TCTL, E1000_TCTL_PSP, E1000_WRITE_FLUSH, E1000_WRITE_REG, E1000_WRITE_REG_IO, IGP_ACTIVITY_LED_ENABLE, IGP_ACTIVITY_LED_MASK, IGP_LED3_MODE, e1000_hw::mac, msec_delay, e1000_mac_info::type, and u32.
Referenced by e1000_init_mac_params_82541().
00306 { 00307 u32 ledctl, ctrl, icr, manc; 00308 00309 DEBUGFUNC("e1000_reset_hw_82541"); 00310 00311 DEBUGOUT("Masking off all interrupts\n"); 00312 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 00313 00314 E1000_WRITE_REG(hw, E1000_RCTL, 0); 00315 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 00316 E1000_WRITE_FLUSH(hw); 00317 00318 /* 00319 * Delay to allow any outstanding PCI transactions to complete 00320 * before resetting the device. 00321 */ 00322 msec_delay(10); 00323 00324 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00325 00326 /* Must reset the Phy before resetting the MAC */ 00327 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 00328 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 00329 msec_delay(5); 00330 } 00331 00332 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 00333 switch (hw->mac.type) { 00334 case e1000_82541: 00335 case e1000_82541_rev_2: 00336 /* 00337 * These controllers can't ack the 64-bit write when 00338 * issuing the reset, so we use IO-mapping as a 00339 * workaround to issue the reset. 00340 */ 00341 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 00342 break; 00343 default: 00344 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 00345 break; 00346 } 00347 00348 /* Wait for NVM reload */ 00349 msec_delay(20); 00350 00351 /* Disable HW ARPs on ASF enabled adapters */ 00352 manc = E1000_READ_REG(hw, E1000_MANC); 00353 manc &= ~E1000_MANC_ARP_EN; 00354 E1000_WRITE_REG(hw, E1000_MANC, manc); 00355 00356 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 00357 e1000_phy_init_script_82541(hw); 00358 00359 /* Configure activity LED after Phy reset */ 00360 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 00361 ledctl &= IGP_ACTIVITY_LED_MASK; 00362 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 00363 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 00364 } 00365 00366 /* Once again, mask the interrupts */ 00367 DEBUGOUT("Masking off all interrupts\n"); 00368 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 00369 00370 /* Clear any pending interrupt events. */ 00371 icr = E1000_READ_REG(hw, E1000_ICR); 00372 00373 return E1000_SUCCESS; 00374 }
e1000_init_hw_82541 - Initialize hardware : pointer to the HW structure
This inits the hardware readying it for operation.
Definition at line 382 of file e1000_82541.c.
References e1000_hw::_82541, e1000_mac_operations::clear_vfta, DEBUGFUNC, DEBUGOUT, e1000_hw::dev_spec, e1000_clear_hw_cntrs_82541(), e1000_init_rx_addrs_generic(), E1000_MTA, E1000_READ_REG, E1000_TXDCTL, E1000_TXDCTL_FULL_TX_DESC_WB, E1000_TXDCTL_WTHRESH, E1000_WRITE_FLUSH, E1000_WRITE_REG, E1000_WRITE_REG_ARRAY, e1000_mac_operations::id_led_init, IGP01E1000_GMII_FIFO, e1000_hw::mac, e1000_mac_info::mta_reg_count, e1000_phy_info::ops, e1000_mac_info::ops, e1000_hw::phy, e1000_mac_info::rar_entry_count, e1000_phy_operations::read_reg, e1000_mac_operations::setup_link, e1000_dev_spec_82541::spd_default, and u32.
Referenced by e1000_init_mac_params_82541().
00383 { 00384 struct e1000_mac_info *mac = &hw->mac; 00385 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 00386 u32 i, txdctl; 00387 s32 ret_val; 00388 00389 DEBUGFUNC("e1000_init_hw_82541"); 00390 00391 /* Initialize identification LED */ 00392 ret_val = mac->ops.id_led_init(hw); 00393 if (ret_val) { 00394 DEBUGOUT("Error initializing identification LED\n"); 00395 /* This is not fatal and we should not stop init due to this */ 00396 } 00397 00398 /* Storing the Speed Power Down value for later use */ 00399 ret_val = hw->phy.ops.read_reg(hw, 00400 IGP01E1000_GMII_FIFO, 00401 &dev_spec->spd_default); 00402 if (ret_val) 00403 goto out; 00404 00405 /* Disabling VLAN filtering */ 00406 DEBUGOUT("Initializing the IEEE VLAN\n"); 00407 mac->ops.clear_vfta(hw); 00408 00409 /* Setup the receive address. */ 00410 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 00411 00412 /* Zero out the Multicast HASH table */ 00413 DEBUGOUT("Zeroing the MTA\n"); 00414 for (i = 0; i < mac->mta_reg_count; i++) { 00415 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 00416 /* 00417 * Avoid back to back register writes by adding the register 00418 * read (flush). This is to protect against some strange 00419 * bridge configurations that may issue Memory Write Block 00420 * (MWB) to our register space. 00421 */ 00422 E1000_WRITE_FLUSH(hw); 00423 } 00424 00425 /* Setup link and flow control */ 00426 ret_val = mac->ops.setup_link(hw); 00427 00428 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 00429 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 00430 E1000_TXDCTL_FULL_TX_DESC_WB; 00431 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 00432 00433 /* 00434 * Clear all of the statistics registers (clear on read). It is 00435 * important that we do this after we have tried to establish link 00436 * because the symbol error count will increment wildly if there 00437 * is no link. 00438 */ 00439 e1000_clear_hw_cntrs_82541(hw); 00440 00441 out: 00442 return ret_val; 00443 }
| static s32 e1000_get_link_up_info_82541 | ( | struct e1000_hw * | hw, | |
| u16 * | speed, | |||
| u16 * | duplex | |||
| ) | [static] |
e1000_get_link_up_info_82541 - Report speed and duplex : pointer to the HW structure : pointer to speed buffer : pointer to duplex buffer
Retrieve the current speed and duplex configuration.
Definition at line 453 of file e1000_82541.c.
References DEBUGFUNC, e1000_get_speed_and_duplex_copper_generic(), HALF_DUPLEX, NWAY_ER_LP_NWAY_CAPS, NWAY_LPAR_100TX_FD_CAPS, NWAY_LPAR_10T_FD_CAPS, e1000_phy_info::ops, e1000_hw::phy, PHY_AUTONEG_EXP, PHY_LP_ABILITY, e1000_phy_operations::read_reg, SPEED_10, SPEED_100, e1000_phy_info::speed_downgraded, and u16.
Referenced by e1000_init_mac_params_82541().
00455 { 00456 struct e1000_phy_info *phy = &hw->phy; 00457 s32 ret_val; 00458 u16 data; 00459 00460 DEBUGFUNC("e1000_get_link_up_info_82541"); 00461 00462 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 00463 if (ret_val) 00464 goto out; 00465 00466 if (!phy->speed_downgraded) 00467 goto out; 00468 00469 /* 00470 * IGP01 PHY may advertise full duplex operation after speed 00471 * downgrade even if it is operating at half duplex. 00472 * Here we set the duplex settings to match the duplex in the 00473 * link partner's capabilities. 00474 */ 00475 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 00476 if (ret_val) 00477 goto out; 00478 00479 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 00480 *duplex = HALF_DUPLEX; 00481 } else { 00482 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 00483 if (ret_val) 00484 goto out; 00485 00486 if (*speed == SPEED_100) { 00487 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 00488 *duplex = HALF_DUPLEX; 00489 } else if (*speed == SPEED_10) { 00490 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 00491 *duplex = HALF_DUPLEX; 00492 } 00493 } 00494 00495 out: 00496 return ret_val; 00497 }
e1000_phy_hw_reset_82541 - PHY hardware reset : pointer to the HW structure
Verify the reset block is not blocking us from resetting. Acquire semaphore (if necessary) and read/set/write the device control reset bit in the PHY. Wait the appropriate delay time for the device to reset and release the semaphore (if necessary).
Definition at line 508 of file e1000_82541.c.
References DEBUGFUNC, e1000_82541, e1000_82547, E1000_LEDCTL, e1000_phy_hw_reset_generic(), e1000_phy_init_script_82541(), E1000_READ_REG, E1000_WRITE_REG, IGP_ACTIVITY_LED_ENABLE, IGP_ACTIVITY_LED_MASK, IGP_LED3_MODE, e1000_hw::mac, e1000_mac_info::type, and u32.
Referenced by e1000_init_phy_params_82541().
00509 { 00510 s32 ret_val; 00511 u32 ledctl; 00512 00513 DEBUGFUNC("e1000_phy_hw_reset_82541"); 00514 00515 ret_val = e1000_phy_hw_reset_generic(hw); 00516 if (ret_val) 00517 goto out; 00518 00519 e1000_phy_init_script_82541(hw); 00520 00521 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 00522 /* Configure activity LED after PHY reset */ 00523 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 00524 ledctl &= IGP_ACTIVITY_LED_MASK; 00525 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 00526 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 00527 } 00528 00529 out: 00530 return ret_val; 00531 }
e1000_setup_copper_link_82541 - Configure copper link settings : pointer to the HW structure
Calls the appropriate function to configure the link for auto-neg or forced speed and duplex. Then we check for link, once link is established calls to configure collision distance and flow control are called. If link is not established, we return -E1000_ERR_PHY (-2).
Definition at line 542 of file e1000_82541.c.
References e1000_hw::_82541, e1000_mac_info::autoneg, DEBUGFUNC, e1000_hw::dev_spec, e1000_dev_spec_82541::dsp_config, e1000_82541, e1000_82547, e1000_copper_link_setup_igp(), E1000_CTRL, E1000_CTRL_FRCDPX, E1000_CTRL_FRCSPD, E1000_CTRL_SLU, e1000_dsp_config_disabled, e1000_dsp_config_enabled, e1000_ffe_config_active, e1000_ffe_config_enabled, E1000_LEDCTL, E1000_READ_REG, e1000_setup_copper_link_generic(), E1000_WRITE_REG, e1000_dev_spec_82541::ffe_config, IGP_ACTIVITY_LED_ENABLE, IGP_ACTIVITY_LED_MASK, IGP_LED3_MODE, e1000_hw::mac, e1000_phy_info::mdix, e1000_hw::phy, e1000_phy_info::reset_disable, e1000_mac_info::type, and u32.
Referenced by e1000_init_mac_params_82541().
00543 { 00544 struct e1000_phy_info *phy = &hw->phy; 00545 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 00546 s32 ret_val; 00547 u32 ctrl, ledctl; 00548 00549 DEBUGFUNC("e1000_setup_copper_link_82541"); 00550 00551 ctrl = E1000_READ_REG(hw, E1000_CTRL); 00552 ctrl |= E1000_CTRL_SLU; 00553 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 00554 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 00555 00556 hw->phy.reset_disable = false; 00557 00558 /* Earlier revs of the IGP phy require us to force MDI. */ 00559 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 00560 dev_spec->dsp_config = e1000_dsp_config_disabled; 00561 phy->mdix = 1; 00562 } else { 00563 dev_spec->dsp_config = e1000_dsp_config_enabled; 00564 } 00565 00566 ret_val = e1000_copper_link_setup_igp(hw); 00567 if (ret_val) 00568 goto out; 00569 00570 if (hw->mac.autoneg) { 00571 if (dev_spec->ffe_config == e1000_ffe_config_active) 00572 dev_spec->ffe_config = e1000_ffe_config_enabled; 00573 } 00574 00575 /* Configure activity LED after Phy reset */ 00576 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 00577 ledctl &= IGP_ACTIVITY_LED_MASK; 00578 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 00579 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 00580 00581 ret_val = e1000_setup_copper_link_generic(hw); 00582 00583 out: 00584 return ret_val; 00585 }
e1000_check_for_link_82541 - Check/Store link connection : pointer to the HW structure
This checks the link condition of the adapter and stores the results in the hw->mac structure.
Definition at line 594 of file e1000_82541.c.
References e1000_mac_info::autoneg, DEBUGFUNC, DEBUGOUT, e1000_check_downshift_generic(), e1000_config_collision_dist_generic(), e1000_config_fc_after_link_up_generic(), E1000_ERR_CONFIG, e1000_phy_has_link_generic(), E1000_SUCCESS, e1000_mac_info::get_link_status, and e1000_hw::mac.
Referenced by e1000_init_mac_params_82541().
00595 { 00596 struct e1000_mac_info *mac = &hw->mac; 00597 s32 ret_val; 00598 bool link; 00599 00600 DEBUGFUNC("e1000_check_for_link_82541"); 00601 00602 /* 00603 * We only want to go out to the PHY registers to see if Auto-Neg 00604 * has completed and/or if our link status has changed. The 00605 * get_link_status flag is set upon receiving a Link Status 00606 * Change or Rx Sequence Error interrupt. 00607 */ 00608 if (!mac->get_link_status) { 00609 ret_val = E1000_SUCCESS; 00610 goto out; 00611 } 00612 00613 /* 00614 * First we want to see if the MII Status Register reports 00615 * link. If so, then we want to get the current speed/duplex 00616 * of the PHY. 00617 */ 00618 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 00619 if (ret_val) 00620 goto out; 00621 00622 if (!link) { 00623 ret_val = -E1000_ERR_CONFIG; 00624 #if 0 00625 ret_val = e1000_config_dsp_after_link_change_82541(hw, false); 00626 #endif 00627 goto out; /* No link detected */ 00628 } 00629 00630 mac->get_link_status = false; 00631 00632 /* 00633 * Check if there was DownShift, must be checked 00634 * immediately after link-up 00635 */ 00636 e1000_check_downshift_generic(hw); 00637 00638 /* 00639 * If we are forcing speed/duplex, then we simply return since 00640 * we have already determined whether we have link or not. 00641 */ 00642 if (!mac->autoneg) { 00643 ret_val = -E1000_ERR_CONFIG; 00644 goto out; 00645 } 00646 00647 #if 0 00648 ret_val = e1000_config_dsp_after_link_change_82541(hw, true); 00649 #endif 00650 00651 /* 00652 * Auto-Neg is enabled. Auto Speed Detection takes care 00653 * of MAC speed/duplex configuration. So we only need to 00654 * configure Collision Distance in the MAC. 00655 */ 00656 e1000_config_collision_dist_generic(hw); 00657 00658 /* 00659 * Configure Flow Control now that Auto-Neg has completed. 00660 * First, we need to restore the desired flow control 00661 * settings because we may have had to re-autoneg with a 00662 * different link partner. 00663 */ 00664 ret_val = e1000_config_fc_after_link_up_generic(hw); 00665 if (ret_val) { 00666 DEBUGOUT("Error configuring flow control\n"); 00667 } 00668 00669 out: 00670 return ret_val; 00671 }
e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 : pointer to the HW structure : boolean used to enable/disable lplu
Success returns 0, Failure returns 1
The low power link up (lplu) state is set to the power management level D3 and SmartSpeed is disabled when active is true, else clear lplu for D3 and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU is used during Dx states where the power conservation is most important. During driver activity, SmartSpeed should be enabled so performance is maintained.
Definition at line 977 of file e1000_82541.c.
References e1000_phy_info::autoneg_advertised, DEBUGFUNC, e1000_82541_rev_2, e1000_82547_rev_2, E1000_ALL_10_SPEED, E1000_ALL_NOT_GIG, E1000_ALL_SPEED_DUPLEX, e1000_set_d3_lplu_state_generic(), e1000_smart_speed_off, e1000_smart_speed_on, IGP01E1000_GMII_FIFO, IGP01E1000_GMII_FLEX_SPD, IGP01E1000_PHY_PORT_CONFIG, IGP01E1000_PSCFR_SMART_SPEED, e1000_hw::mac, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_phy_info::smart_speed, e1000_mac_info::type, u16, and e1000_phy_operations::write_reg.
Referenced by e1000_init_phy_params_82541().
00978 { 00979 struct e1000_phy_info *phy = &hw->phy; 00980 s32 ret_val; 00981 u16 data; 00982 00983 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 00984 00985 switch (hw->mac.type) { 00986 case e1000_82541_rev_2: 00987 case e1000_82547_rev_2: 00988 break; 00989 default: 00990 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 00991 goto out; 00992 break; 00993 } 00994 00995 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 00996 if (ret_val) 00997 goto out; 00998 00999 if (!active) { 01000 data &= ~IGP01E1000_GMII_FLEX_SPD; 01001 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 01002 if (ret_val) 01003 goto out; 01004 01005 /* 01006 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 01007 * during Dx states where the power conservation is most 01008 * important. During driver activity we should enable 01009 * SmartSpeed, so performance is maintained. 01010 */ 01011 if (phy->smart_speed == e1000_smart_speed_on) { 01012 ret_val = phy->ops.read_reg(hw, 01013 IGP01E1000_PHY_PORT_CONFIG, 01014 &data); 01015 if (ret_val) 01016 goto out; 01017 01018 data |= IGP01E1000_PSCFR_SMART_SPEED; 01019 ret_val = phy->ops.write_reg(hw, 01020 IGP01E1000_PHY_PORT_CONFIG, 01021 data); 01022 if (ret_val) 01023 goto out; 01024 } else if (phy->smart_speed == e1000_smart_speed_off) { 01025 ret_val = phy->ops.read_reg(hw, 01026 IGP01E1000_PHY_PORT_CONFIG, 01027 &data); 01028 if (ret_val) 01029 goto out; 01030 01031 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01032 ret_val = phy->ops.write_reg(hw, 01033 IGP01E1000_PHY_PORT_CONFIG, 01034 data); 01035 if (ret_val) 01036 goto out; 01037 } 01038 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 01039 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 01040 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 01041 data |= IGP01E1000_GMII_FLEX_SPD; 01042 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 01043 if (ret_val) 01044 goto out; 01045 01046 /* When LPLU is enabled, we should disable SmartSpeed */ 01047 ret_val = phy->ops.read_reg(hw, 01048 IGP01E1000_PHY_PORT_CONFIG, 01049 &data); 01050 if (ret_val) 01051 goto out; 01052 01053 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 01054 ret_val = phy->ops.write_reg(hw, 01055 IGP01E1000_PHY_PORT_CONFIG, 01056 data); 01057 } 01058 01059 out: 01060 return ret_val; 01061 }
Referenced by e1000_init_mac_params_82541().
Referenced by e1000_init_mac_params_82541().
| static void e1000_clear_hw_cntrs_82541 | ( | struct e1000_hw * | hw | ) | [static] |
e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters : pointer to the HW structure
Clears the hardware counters by reading the counter registers.
Definition at line 1263 of file e1000_82541.c.
References DEBUGFUNC, E1000_ALGNERRC, E1000_CEXTERR, e1000_clear_hw_cntrs_base_generic(), E1000_MGTPDC, E1000_MGTPRC, E1000_MGTPTC, E1000_PRC1023, E1000_PRC127, E1000_PRC1522, E1000_PRC255, E1000_PRC511, E1000_PRC64, E1000_PTC1023, E1000_PTC127, E1000_PTC1522, E1000_PTC255, E1000_PTC511, E1000_PTC64, E1000_READ_REG, E1000_RXERRC, E1000_TNCRS, E1000_TSCTC, and E1000_TSCTFC.
Referenced by e1000_init_hw_82541(), and e1000_init_mac_params_82541().
01264 { 01265 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 01266 01267 e1000_clear_hw_cntrs_base_generic(hw); 01268 01269 #if 0 01270 E1000_READ_REG(hw, E1000_PRC64); 01271 E1000_READ_REG(hw, E1000_PRC127); 01272 E1000_READ_REG(hw, E1000_PRC255); 01273 E1000_READ_REG(hw, E1000_PRC511); 01274 E1000_READ_REG(hw, E1000_PRC1023); 01275 E1000_READ_REG(hw, E1000_PRC1522); 01276 E1000_READ_REG(hw, E1000_PTC64); 01277 E1000_READ_REG(hw, E1000_PTC127); 01278 E1000_READ_REG(hw, E1000_PTC255); 01279 E1000_READ_REG(hw, E1000_PTC511); 01280 E1000_READ_REG(hw, E1000_PTC1023); 01281 E1000_READ_REG(hw, E1000_PTC1522); 01282 01283 E1000_READ_REG(hw, E1000_ALGNERRC); 01284 E1000_READ_REG(hw, E1000_RXERRC); 01285 E1000_READ_REG(hw, E1000_TNCRS); 01286 E1000_READ_REG(hw, E1000_CEXTERR); 01287 E1000_READ_REG(hw, E1000_TSCTC); 01288 E1000_READ_REG(hw, E1000_TSCTFC); 01289 01290 E1000_READ_REG(hw, E1000_MGTPRC); 01291 E1000_READ_REG(hw, E1000_MGTPDC); 01292 E1000_READ_REG(hw, E1000_MGTPTC); 01293 #endif 01294 }
e1000_phy_init_script_82541 - Initialize GbE PHY : pointer to the HW structure
Initializes the IGP PHY.
Definition at line 1134 of file e1000_82541.c.
References e1000_hw::_82541, DEBUGFUNC, e1000_hw::dev_spec, e1000_82541, e1000_82541_rev_2, e1000_82547, e1000_82547_rev_2, E1000_SUCCESS, IGP01E1000_ANALOG_FUSE_BYPASS, IGP01E1000_ANALOG_FUSE_COARSE_10, IGP01E1000_ANALOG_FUSE_COARSE_MASK, IGP01E1000_ANALOG_FUSE_COARSE_THRESH, IGP01E1000_ANALOG_FUSE_CONTROL, IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL, IGP01E1000_ANALOG_FUSE_FINE_1, IGP01E1000_ANALOG_FUSE_FINE_10, IGP01E1000_ANALOG_FUSE_FINE_MASK, IGP01E1000_ANALOG_FUSE_POLY_MASK, IGP01E1000_ANALOG_FUSE_STATUS, IGP01E1000_ANALOG_SPARE_FUSE_ENABLED, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, e1000_hw::mac, msec_delay, e1000_phy_info::ops, e1000_hw::phy, e1000_dev_spec_82541::phy_init_script, e1000_phy_operations::read_reg, e1000_mac_info::type, u16, u32, and e1000_phy_operations::write_reg.
Referenced by e1000_phy_hw_reset_82541(), and e1000_reset_hw_82541().
01135 { 01136 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 01137 u32 ret_val; 01138 u16 phy_saved_data; 01139 01140 DEBUGFUNC("e1000_phy_init_script_82541"); 01141 01142 if (!dev_spec->phy_init_script) { 01143 ret_val = E1000_SUCCESS; 01144 goto out; 01145 } 01146 01147 /* Delay after phy reset to enable NVM configuration to load */ 01148 msec_delay(20); 01149 01150 /* 01151 * Save off the current value of register 0x2F5B to be restored at 01152 * the end of this routine. 01153 */ 01154 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 01155 01156 /* Disabled the PHY transmitter */ 01157 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 01158 01159 msec_delay(20); 01160 01161 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 01162 01163 msec_delay(5); 01164 01165 switch (hw->mac.type) { 01166 case e1000_82541: 01167 case e1000_82547: 01168 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 01169 01170 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 01171 01172 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 01173 01174 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 01175 01176 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 01177 01178 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 01179 01180 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 01181 01182 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 01183 01184 hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 01185 break; 01186 case e1000_82541_rev_2: 01187 case e1000_82547_rev_2: 01188 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 01189 break; 01190 default: 01191 break; 01192 } 01193 01194 hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 01195 01196 msec_delay(20); 01197 01198 /* Now enable the transmitter */ 01199 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 01200 01201 if (hw->mac.type == e1000_82547) { 01202 u16 fused, fine, coarse; 01203 01204 /* Move to analog registers page */ 01205 hw->phy.ops.read_reg(hw, 01206 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 01207 &fused); 01208 01209 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 01210 hw->phy.ops.read_reg(hw, 01211 IGP01E1000_ANALOG_FUSE_STATUS, 01212 &fused); 01213 01214 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 01215 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 01216 01217 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 01218 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 01219 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 01220 } else if (coarse == 01221 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 01222 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 01223 01224 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 01225 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 01226 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 01227 01228 hw->phy.ops.write_reg(hw, 01229 IGP01E1000_ANALOG_FUSE_CONTROL, 01230 fused); 01231 hw->phy.ops.write_reg(hw, 01232 IGP01E1000_ANALOG_FUSE_BYPASS, 01233 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 01234 } 01235 } 01236 01237 out: 01238 return ret_val; 01239 }
| static void e1000_power_down_phy_copper_82541 | ( | struct e1000_hw * | hw | ) | [static] |
e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down : pointer to the HW structure
In the case of a PHY power down to save power, or to turn off link during a driver unload, or wake on lan is not enabled, remove the link.
Definition at line 1248 of file e1000_82541.c.
References E1000_MANC, E1000_MANC_SMBUS_EN, e1000_power_down_phy_copper(), and E1000_READ_REG.
Referenced by e1000_init_phy_params_82541().
01249 { 01250 /* If the management interface is not enabled, then power down */ 01251 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 01252 e1000_power_down_phy_copper(hw); 01253 01254 return; 01255 }
| void e1000_init_function_pointers_82541 | ( | struct e1000_hw * | hw | ) |
e1000_init_function_pointers_82541 - Init func ptrs.
: pointer to the HW structure
Called to initialize all function pointers and parameters.
Definition at line 290 of file e1000_82541.c.
References DEBUGFUNC, e1000_init_mac_params_82541(), e1000_init_nvm_params_82541(), e1000_init_phy_params_82541(), e1000_phy_operations::init_params, e1000_nvm_operations::init_params, e1000_mac_operations::init_params, e1000_hw::mac, e1000_hw::nvm, e1000_phy_info::ops, e1000_nvm_info::ops, e1000_mac_info::ops, and e1000_hw::phy.
Referenced by e1000_setup_init_funcs().
00291 { 00292 DEBUGFUNC("e1000_init_function_pointers_82541"); 00293 00294 hw->mac.ops.init_params = e1000_init_mac_params_82541; 00295 hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 00296 hw->phy.ops.init_params = e1000_init_phy_params_82541; 00297 }
e1000_setup_led_82541 - Configures SW controllable LED : pointer to the HW structure
This prepares the SW controllable LED for use and saves the current state of the LED so it can be later restored.
Definition at line 1070 of file e1000_82541.c.
References e1000_hw::_82541, DEBUGFUNC, e1000_hw::dev_spec, E1000_LEDCTL, E1000_WRITE_REG, IGP01E1000_GMII_FIFO, IGP01E1000_GMII_SPD, e1000_mac_info::ledctl_mode1, e1000_hw::mac, e1000_phy_info::ops, e1000_hw::phy, e1000_phy_operations::read_reg, e1000_dev_spec_82541::spd_default, u16, and e1000_phy_operations::write_reg.
01071 { 01072 #if 0 01073 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 01074 s32 ret_val; 01075 01076 DEBUGFUNC("e1000_setup_led_82541"); 01077 01078 ret_val = hw->phy.ops.read_reg(hw, 01079 IGP01E1000_GMII_FIFO, 01080 &dev_spec->spd_default); 01081 if (ret_val) 01082 goto out; 01083 01084 ret_val = hw->phy.ops.write_reg(hw, 01085 IGP01E1000_GMII_FIFO, 01086 (u16)(dev_spec->spd_default & 01087 ~IGP01E1000_GMII_SPD)); 01088 if (ret_val) 01089 goto out; 01090 01091 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 01092 01093 out: 01094 return ret_val; 01095 #endif 01096 return 0; 01097 }
e1000_cleanup_led_82541 - Set LED config to default operation : pointer to the HW structure
Remove the current LED configuration and set the LED configuration to the default value, saved from the EEPROM.
Definition at line 1106 of file e1000_82541.c.
References e1000_hw::_82541, DEBUGFUNC, e1000_hw::dev_spec, E1000_LEDCTL, E1000_WRITE_REG, IGP01E1000_GMII_FIFO, e1000_mac_info::ledctl_default, e1000_hw::mac, e1000_phy_info::ops, e1000_hw::phy, e1000_dev_spec_82541::spd_default, and e1000_phy_operations::write_reg.
01107 { 01108 #if 0 01109 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 01110 s32 ret_val; 01111 01112 DEBUGFUNC("e1000_cleanup_led_82541"); 01113 01114 ret_val = hw->phy.ops.write_reg(hw, 01115 IGP01E1000_GMII_FIFO, 01116 dev_spec->spd_default); 01117 if (ret_val) 01118 goto out; 01119 01120 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 01121 01122 out: 01123 return ret_val; 01124 #endif 01125 return 0; 01126 }
struct pci_device_id e1000_82541_nics[] [static] |
Initial value:
{
PCI_ROM(0x8086, 0x1013, "E1000_DEV_ID_82541EI", "E1000_DEV_ID_82541EI", e1000_82541),
PCI_ROM(0x8086, 0x1014, "E1000_DEV_ID_82541ER_LOM", "E1000_DEV_ID_82541ER_LOM", e1000_82541),
PCI_ROM(0x8086, 0x1018, "E1000_DEV_ID_82541EI_MOBILE", "E1000_DEV_ID_82541EI_MOBILE", e1000_82541),
PCI_ROM(0x8086, 0x1019, "E1000_DEV_ID_82547EI", "E1000_DEV_ID_82547EI", e1000_82547),
PCI_ROM(0x8086, 0x101A, "E1000_DEV_ID_82547EI_MOBILE", "E1000_DEV_ID_82547EI_MOBILE", e1000_82547),
PCI_ROM(0x8086, 0x1075, "E1000_DEV_ID_82547GI", "E1000_DEV_ID_82547GI", e1000_82547_rev_2),
PCI_ROM(0x8086, 0x1076, "E1000_DEV_ID_82541GI", "E1000_DEV_ID_82541GI", e1000_82541_rev_2),
PCI_ROM(0x8086, 0x1077, "E1000_DEV_ID_82541GI_MOBILE", "E1000_DEV_ID_82541GI_MOBILE", e1000_82541_rev_2),
PCI_ROM(0x8086, 0x1078, "E1000_DEV_ID_82541ER", "E1000_DEV_ID_82541ER", e1000_82541_rev_2),
PCI_ROM(0x8086, 0x107C, "E1000_DEV_ID_82541GI_LF", "E1000_DEV_ID_82541GI_LF", e1000_82541_rev_2),
}
Definition at line 1296 of file e1000_82541.c.
| struct pci_driver e1000_82541_driver __pci_driver |
Initial value:
{
.ids = e1000_82541_nics,
.id_count = (sizeof (e1000_82541_nics) / sizeof (e1000_82541_nics[0])),
.probe = e1000_probe,
.remove = e1000_remove,
}
Definition at line 1309 of file e1000_82541.c.
1.5.7.1