dmfe.c File Reference

#include "etherboot.h"
#include "nic.h"
#include <gpxe/pci.h>
#include <gpxe/ethernet.h>

Go to the source code of this file.

Data Structures

struct  tx_desc
struct  rx_desc
struct  dmfe_private

Defines

#define dprintf(x)
#define virt_to_le32desc(addr)   cpu_to_le32(virt_to_bus(addr))
#define le32desc_to_virt(addr)   bus_to_virt(le32_to_cpu(addr))
#define PCI_DM9132_ID   0x91321282
#define PCI_DM9102_ID   0x91021282
#define PCI_DM9100_ID   0x91001282
#define PCI_DM9009_ID   0x90091282
#define DM9102_IO_SIZE   0x80
#define DM9102A_IO_SIZE   0x100
#define TX_MAX_SEND_CNT   0x1
#define TX_DESC_CNT   0x10
#define RX_DESC_CNT   0x20
#define TX_FREE_DESC_CNT   (TX_DESC_CNT - 2)
#define TX_WAKE_DESC_CNT   (TX_DESC_CNT - 3)
#define DESC_ALL_CNT   (TX_DESC_CNT + RX_DESC_CNT)
#define TX_BUF_ALLOC   0x600
#define RX_ALLOC_SIZE   0x620
#define DM910X_RESET   1
#define CR0_DEFAULT   0x00E00000
#define CR6_DEFAULT   0x00080000
#define CR7_DEFAULT   0x180c1
#define CR15_DEFAULT   0x06
#define TDES0_ERR_MASK   0x4302
#define MAX_PACKET_SIZE   1514
#define DMFE_MAX_MULTICAST   14
#define RX_COPY_SIZE   100
#define MAX_CHECK_PACKET   0x8000
#define DM9801_NOISE_FLOOR   8
#define DM9802_NOISE_FLOOR   5
#define DMFE_10MHF   0
#define DMFE_100MHF   1
#define DMFE_10MFD   4
#define DMFE_100MFD   5
#define DMFE_AUTO   8
#define DMFE_1M_HPNA   0x10
#define DMFE_TXTH_72   0x400000
#define DMFE_TXTH_96   0x404000
#define DMFE_TXTH_128   0x0000
#define DMFE_TXTH_256   0x4000
#define DMFE_TXTH_512   0x8000
#define DMFE_TXTH_1K   0xC000
#define DMFE_TIMER_WUT   (jiffies + HZ * 1)
#define DMFE_TX_TIMEOUT   ((3*HZ)/2)
#define DMFE_TX_KICK   (HZ/2)
#define DMFE_DBUG(dbug_now, msg, value)   if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
#define SHOW_MEDIA_TYPE(mode)   printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
#define CR9_SROM_READ   0x4800
#define CR9_SRCS   0x1
#define CR9_SRCLK   0x2
#define CR9_CRDOUT   0x8
#define SROM_DATA_0   0x0
#define SROM_DATA_1   0x4
#define PHY_DATA_1   0x20000
#define PHY_DATA_0   0x00000
#define MDCLKH   0x10000
#define PHY_POWER_DOWN   0x800
#define SROM_V41_CODE   0x14
#define SROM_CLK_WRITE(data, ioaddr)   outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
#define __CHK_IO_SIZE(pci_id, dev_rev)   ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
#define CHK_IO_SIZE(pci_dev, dev_rev)   __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
#define DEVICE   net_device
#define txd   dmfe_bufs.txd
#define txb   dmfe_bufs.txb
#define rxd   dmfe_bufs.rxd
#define rxb   dmfe_bufs.rxb
#define board_found   1
#define valid_link   0

Enumerations

enum  dmfe_offsets {
  DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18,
  DCR4 = 0x20, DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38,
  DCR8 = 0x40, DCR9 = 0x48, DCR10 = 0x50, DCR11 = 0x58,
  DCR12 = 0x60, DCR13 = 0x68, DCR14, DCR15 = 0x78
}
enum  dmfe_CR6_bits {
  CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
  CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000, CR6_SFT = 0x200000,
  CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
}

Functions

 FILE_LICENCE (GPL2_OR_LATER)
static u16 read_srom_word (long ioaddr, int offset)
static void dmfe_init_dm910x (struct nic *nic)
static void dmfe_descriptor_init (struct nic *, unsigned long ioaddr)
static void update_cr6 (u32, unsigned long)
static void send_filter_frame (struct nic *nic)
static void dm9132_id_table (struct nic *nic)
static u16 phy_read (unsigned long, u8, u8, u32)
static void phy_write (unsigned long, u8, u8, u16, u32)
static void phy_write_1bit (unsigned long, u32)
static u16 phy_read_1bit (unsigned long)
static void dmfe_set_phyxcer (struct nic *nic)
static void dmfe_parse_srom (struct nic *nic)
static void dmfe_program_DM9801 (struct nic *nic, int)
static void dmfe_program_DM9802 (struct nic *nic)
static void dmfe_reset (struct nic *nic)
static int dmfe_poll (struct nic *nic, int retrieve)
static void dmfe_irq (struct nic *nic __unused, irq_action_t action __unused)
static void dmfe_transmit (struct nic *nic, const char *dest, unsigned int type, unsigned int size, const char *packet)
static void dmfe_disable (struct nic *nic __unused)
static int dmfe_probe (struct nic *nic, struct pci_device *pci)
static void dmfe_descriptor_init (struct nic *nic __unused, unsigned long ioaddr)
static void dm9132_id_table (struct nic *nic __unused)
static void dmfe_set_phyxcer (struct nic *nic __unused)
static void dmfe_program_DM9801 (struct nic *nic __unused, int HPNA_rev)
static void dmfe_program_DM9802 (struct nic *nic __unused)
 PCI_DRIVER (dmfe_driver, dmfe_nics, PCI_NO_CLASS)
 DRIVER ("DMFE/PCI", nic_driver, pci_driver, dmfe_driver, dmfe_probe, dmfe_disable)

Variables

static struct dmfe_private dfx
static struct dmfe_private * db
static struct nic_operations dmfe_operations
static unsigned char dmfe_media_mode = DMFE_AUTO
static u32 dmfe_cr6_user_set
static u8 chkmode = 1
static u8 HPNA_mode
static u8 HPNA_rx_cmd
static u8 HPNA_tx_cmd
static u8 HPNA_NoiseFloor
static u8 SF_mode
struct {
   struct tx_desc   txd [TX_DESC_CNT]
   unsigned char   txb [TX_BUF_ALLOC *TX_DESC_CNT]
   struct rx_desc   rxd [RX_DESC_CNT]
   unsigned char   rxb [RX_ALLOC_SIZE *RX_DESC_CNT]
} __shared
static long int BASE
static struct pci_device_id dmfe_nics []

Define Documentation

#define dprintf ( x   ) 

Definition at line 53 of file dmfe.c.

Referenced by dm9132_id_table(), dmfe_probe(), forcedeth_disable(), forcedeth_probe(), forcedeth_reset(), kick_tx(), mii_rw(), ns83820_do_reset(), ns83820_probe(), ns83820_reset(), ns83820_run_bist(), ns83820_setup_rx(), pcnet32_probe(), pcnet32_reset(), phy_intr(), send_filter_frame(), start_rx(), start_tx(), stop_rx(), stop_tx(), txrx_reset(), and update_linkspeed().

#define virt_to_le32desc ( addr   )     cpu_to_le32(virt_to_bus(addr))

Definition at line 57 of file dmfe.c.

Referenced by alloc_rx(), dmfe_descriptor_init(), dmfe_init_dm910x(), epic100_init_ring(), epic100_open(), forcedeth_reset(), forcedeth_transmit(), init_ring(), ns83820_setup_rx(), ns83820_transmit(), pcnet32_init_ring(), pcnet32_transmit(), sundance_reset(), sundance_transmit(), TLan_ResetLists(), tlan_transmit(), tulip_init_ring(), tulip_reset(), tulip_transmit(), velocity_init_registers(), velocity_rx_reset(), and w89c840_transmit().

#define le32desc_to_virt ( addr   )     bus_to_virt(le32_to_cpu(addr))

Definition at line 58 of file dmfe.c.

Referenced by w89c840_poll().

#define PCI_DM9132_ID   0x91321282

Definition at line 61 of file dmfe.c.

Referenced by dmfe_init_dm910x(), dmfe_reset(), phy_read(), and phy_write().

#define PCI_DM9102_ID   0x91021282

Definition at line 62 of file dmfe.c.

Referenced by dmfe_set_phyxcer().

#define PCI_DM9100_ID   0x91001282

Definition at line 63 of file dmfe.c.

#define PCI_DM9009_ID   0x90091282

Definition at line 64 of file dmfe.c.

Referenced by dmfe_init_dm910x(), and dmfe_set_phyxcer().

#define DM9102_IO_SIZE   0x80

Definition at line 66 of file dmfe.c.

#define DM9102A_IO_SIZE   0x100

Definition at line 67 of file dmfe.c.

#define TX_MAX_SEND_CNT   0x1

Definition at line 68 of file dmfe.c.

#define TX_DESC_CNT   0x10

Definition at line 69 of file dmfe.c.

#define RX_DESC_CNT   0x20

Definition at line 70 of file dmfe.c.

#define TX_FREE_DESC_CNT   (TX_DESC_CNT - 2)

Definition at line 71 of file dmfe.c.

#define TX_WAKE_DESC_CNT   (TX_DESC_CNT - 3)

Definition at line 72 of file dmfe.c.

#define DESC_ALL_CNT   (TX_DESC_CNT + RX_DESC_CNT)

Definition at line 73 of file dmfe.c.

#define TX_BUF_ALLOC   0x600

Definition at line 74 of file dmfe.c.

#define RX_ALLOC_SIZE   0x620

Definition at line 75 of file dmfe.c.

Referenced by dmfe_descriptor_init(), and dmfe_poll().

#define DM910X_RESET   1

Definition at line 76 of file dmfe.c.

Referenced by dmfe_disable(), and dmfe_init_dm910x().

#define CR0_DEFAULT   0x00E00000

Definition at line 77 of file dmfe.c.

Referenced by dmfe_reset().

#define CR6_DEFAULT   0x00080000

Definition at line 78 of file dmfe.c.

Referenced by dmfe_reset().

#define CR7_DEFAULT   0x180c1

Definition at line 79 of file dmfe.c.

Referenced by dmfe_init_dm910x().

#define CR15_DEFAULT   0x06

Definition at line 80 of file dmfe.c.

Referenced by dmfe_parse_srom().

#define TDES0_ERR_MASK   0x4302

Definition at line 81 of file dmfe.c.

#define MAX_PACKET_SIZE   1514

Definition at line 82 of file dmfe.c.

#define DMFE_MAX_MULTICAST   14

Definition at line 83 of file dmfe.c.

#define RX_COPY_SIZE   100

Definition at line 84 of file dmfe.c.

#define MAX_CHECK_PACKET   0x8000

Definition at line 85 of file dmfe.c.

#define DM9801_NOISE_FLOOR   8

Definition at line 86 of file dmfe.c.

Referenced by dmfe_program_DM9801().

#define DM9802_NOISE_FLOOR   5

Definition at line 87 of file dmfe.c.

Referenced by dmfe_program_DM9802().

#define DMFE_10MHF   0

Definition at line 89 of file dmfe.c.

Referenced by dmfe_set_phyxcer().

#define DMFE_100MHF   1

Definition at line 90 of file dmfe.c.

Referenced by dmfe_parse_srom(), and dmfe_set_phyxcer().

#define DMFE_10MFD   4

Definition at line 91 of file dmfe.c.

Referenced by dmfe_parse_srom(), and dmfe_set_phyxcer().

#define DMFE_100MFD   5

Definition at line 92 of file dmfe.c.

Referenced by dmfe_parse_srom(), and dmfe_set_phyxcer().

#define DMFE_AUTO   8

Definition at line 93 of file dmfe.c.

Referenced by dmfe_init_dm910x(), and dmfe_set_phyxcer().

#define DMFE_1M_HPNA   0x10

Definition at line 94 of file dmfe.c.

Referenced by dmfe_parse_srom().

#define DMFE_TXTH_72   0x400000

Definition at line 96 of file dmfe.c.

#define DMFE_TXTH_96   0x404000

Definition at line 97 of file dmfe.c.

#define DMFE_TXTH_128   0x0000

Definition at line 98 of file dmfe.c.

#define DMFE_TXTH_256   0x4000

Definition at line 99 of file dmfe.c.

Referenced by dmfe_reset().

#define DMFE_TXTH_512   0x8000

Definition at line 100 of file dmfe.c.

#define DMFE_TXTH_1K   0xC000

Definition at line 101 of file dmfe.c.

#define DMFE_TIMER_WUT   (jiffies + HZ * 1)

Definition at line 103 of file dmfe.c.

#define DMFE_TX_TIMEOUT   ((3*HZ)/2)

Definition at line 104 of file dmfe.c.

#define DMFE_TX_KICK   (HZ/2)

Definition at line 105 of file dmfe.c.

#define DMFE_DBUG ( dbug_now,
msg,
value   )     if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))

Definition at line 107 of file dmfe.c.

#define SHOW_MEDIA_TYPE ( mode   )     printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");

Definition at line 109 of file dmfe.c.

#define CR9_SROM_READ   0x4800

Definition at line 113 of file dmfe.c.

Referenced by read_srom_word().

#define CR9_SRCS   0x1

Definition at line 114 of file dmfe.c.

Referenced by read_srom_word().

#define CR9_SRCLK   0x2

Definition at line 115 of file dmfe.c.

Referenced by read_srom_word().

#define CR9_CRDOUT   0x8

Definition at line 116 of file dmfe.c.

Referenced by read_srom_word().

#define SROM_DATA_0   0x0

Definition at line 117 of file dmfe.c.

Referenced by read_srom_word().

#define SROM_DATA_1   0x4

Definition at line 118 of file dmfe.c.

Referenced by read_srom_word().

#define PHY_DATA_1   0x20000

Definition at line 119 of file dmfe.c.

#define PHY_DATA_0   0x00000

Definition at line 120 of file dmfe.c.

#define MDCLKH   0x10000

Definition at line 121 of file dmfe.c.

#define PHY_POWER_DOWN   0x800

Definition at line 123 of file dmfe.c.

#define SROM_V41_CODE   0x14

Definition at line 125 of file dmfe.c.

Referenced by dmfe_parse_srom().

#define SROM_CLK_WRITE ( data,
ioaddr   )     outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);

Definition at line 127 of file dmfe.c.

Referenced by read_srom_word().

#define __CHK_IO_SIZE ( pci_id,
dev_rev   )     ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE

Definition at line 129 of file dmfe.c.

#define CHK_IO_SIZE ( pci_dev,
dev_rev   )     __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)

Definition at line 130 of file dmfe.c.

#define DEVICE   net_device

Definition at line 133 of file dmfe.c.

#define txd   dmfe_bufs.txd

Definition at line 219 of file dmfe.c.

#define txb   dmfe_bufs.txb

Definition at line 220 of file dmfe.c.

#define rxd   dmfe_bufs.rxd

Definition at line 221 of file dmfe.c.

#define rxb   dmfe_bufs.rxb

Definition at line 222 of file dmfe.c.

#define board_found   1

Definition at line 449 of file dmfe.c.

#define valid_link   0

Definition at line 450 of file dmfe.c.

Enumeration Type Documentation

enum dmfe_offsets

Enumerator:
DCR0 
DCR1 
DCR2 
DCR3 
DCR4 
DCR5 
DCR6 
DCR7 
DCR8 
DCR9 
DCR10 
DCR11 
DCR12 
DCR13 
DCR14 
DCR15 

Definition at line 178 of file dmfe.c.

00178                   {
00179         DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
00180         DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
00181         DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 =
00182             0x70,
00183         DCR15 = 0x78
00184 };

enum dmfe_CR6_bits

Enumerator:
CR6_RXSC 
CR6_PBF 
CR6_PM 
CR6_PAM 
CR6_FDM 
CR6_TXSC 
CR6_STI 
CR6_SFT 
CR6_RXA 
CR6_NO_PURGE 

Definition at line 186 of file dmfe.c.

00186                    {
00187         CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
00188         CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
00189         CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
00190 };

Function Documentation

FILE_LICENCE ( GPL2_OR_LATER   ) 

static u16 read_srom_word ( long  ioaddr,
int  offset 
) [static]

Definition at line 661 of file dmfe.c.

References CR9_CRDOUT, CR9_SRCLK, CR9_SRCS, CR9_SROM_READ, DCR9, inl, outl, SROM_CLK_WRITE, SROM_DATA_0, SROM_DATA_1, u16, and udelay().

Referenced by dmfe_probe().

00662 {
00663         int i;
00664         u16 srom_data = 0;
00665         long cr9_ioaddr = ioaddr + DCR9;
00666 
00667         outl(CR9_SROM_READ, cr9_ioaddr);
00668         outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
00669 
00670         /* Send the Read Command 110b */
00671         SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
00672         SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
00673         SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
00674 
00675         /* Send the offset */
00676         for (i = 5; i >= 0; i--) {
00677                 srom_data =
00678                     (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
00679                 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
00680         }
00681 
00682         outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
00683 
00684         for (i = 16; i > 0; i--) {
00685                 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
00686                 udelay(5);
00687                 srom_data =
00688                     (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1
00689                                         : 0);
00690                 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
00691                 udelay(5);
00692         }
00693 
00694         outl(CR9_SROM_READ, cr9_ioaddr);
00695         return srom_data;
00696 }

static void dmfe_init_dm910x ( struct nic *  nic  )  [static]

Definition at line 276 of file dmfe.c.

References dmfe_private::chip_id, dmfe_private::cr0_data, dmfe_private::cr15_data, dmfe_private::cr6_data, CR6_RXSC, CR6_TXSC, dmfe_private::cr7_data, CR7_DEFAULT, DCR0, DCR12, DCR15, DCR3, DCR4, DCR7, DM910X_RESET, dm9132_id_table(), DMFE_AUTO, dmfe_descriptor_init(), dmfe_parse_srom(), dmfe_set_phyxcer(), ioaddr, mdelay(), dmfe_private::media_mode, dmfe_private::op_mode, outl, PCI_DM9009_ID, PCI_DM9132_ID, dmfe_private::phy_addr, rxd, send_filter_frame(), txd, udelay(), update_cr6(), and virt_to_le32desc.

Referenced by dmfe_reset().

00277 {
00278         unsigned long ioaddr = BASE;
00279 
00280         /* Reset DM910x MAC controller */
00281         outl(DM910X_RESET, ioaddr + DCR0);      /* RESET MAC */
00282         udelay(100);
00283         outl(db->cr0_data, ioaddr + DCR0);
00284         udelay(5);
00285 
00286         /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
00287         db->phy_addr = 1;
00288 
00289         /* Parser SROM and media mode */
00290         dmfe_parse_srom(nic);
00291         db->media_mode = dmfe_media_mode;
00292 
00293         /* RESET Phyxcer Chip by GPR port bit 7 */
00294         outl(0x180, ioaddr + DCR12);    /* Let bit 7 output port */
00295         if (db->chip_id == PCI_DM9009_ID) {
00296                 outl(0x80, ioaddr + DCR12);     /* Issue RESET signal */
00297                 mdelay(300);    /* Delay 300 ms */
00298         }
00299         outl(0x0, ioaddr + DCR12);      /* Clear RESET signal */
00300 
00301         /* Process Phyxcer Media Mode */
00302         if (!(db->media_mode & 0x10))   /* Force 1M mode */
00303                 dmfe_set_phyxcer(nic);
00304 
00305         /* Media Mode Process */
00306         if (!(db->media_mode & DMFE_AUTO))
00307                 db->op_mode = db->media_mode;   /* Force Mode */
00308 
00309         /* Initiliaze Transmit/Receive decriptor and CR3/4 */
00310         dmfe_descriptor_init(nic, ioaddr);
00311 
00312         /* tx descriptor start pointer */
00313         outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
00314 
00315         /* rx descriptor start pointer */
00316         outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
00317 
00318         /* Init CR6 to program DM910x operation */
00319         update_cr6(db->cr6_data, ioaddr);
00320 
00321         /* Send setup frame */
00322         if (db->chip_id == PCI_DM9132_ID) {
00323                 dm9132_id_table(nic);   /* DM9132 */
00324         } else {
00325                 send_filter_frame(nic); /* DM9102/DM9102A */
00326         }
00327 
00328         /* Init CR7, interrupt active bit */
00329         db->cr7_data = CR7_DEFAULT;
00330         outl(db->cr7_data, ioaddr + DCR7);
00331         /* Init CR15, Tx jabber and Rx watchdog timer */
00332         outl(db->cr15_data, ioaddr + DCR15);
00333         /* Enable DM910X Tx/Rx function */
00334         db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
00335         update_cr6(db->cr6_data, ioaddr);
00336 }

static void dmfe_descriptor_init ( struct nic *  ,
unsigned long  ioaddr 
) [static]

Referenced by dmfe_init_dm910x().

static void update_cr6 ( u32  cr6_data,
unsigned long  ioaddr 
) [static]

Definition at line 559 of file dmfe.c.

References DCR6, outl, u32, and udelay().

Referenced by dmfe_init_dm910x(), dmfe_parse_srom(), dmfe_set_phyxcer(), and send_filter_frame().

00560 {
00561         u32 cr6_tmp;
00562 
00563         cr6_tmp = cr6_data & ~0x2002;   /* stop Tx/Rx */
00564         outl(cr6_tmp, ioaddr + DCR6);
00565         udelay(5);
00566         outl(cr6_data, ioaddr + DCR6);
00567         udelay(5);
00568 }

static void send_filter_frame ( struct nic *  nic  )  [static]

Definition at line 627 of file dmfe.c.

References cpu_to_le32, dmfe_private::cr6_data, dmfe_private::cur_tx, DCR1, dprintf, nic::node_addr, outl, txb, txd, u8, and update_cr6().

Referenced by dmfe_init_dm910x().

00628 {
00629 
00630         u8 *ptxb;
00631         int i;
00632 
00633         dprintf(("send_filter_frame\n"));
00634         /* point to the current txb incase multiple tx_rings are used */
00635         ptxb = &txb[db->cur_tx];
00636 
00637         /* construct perfect filter frame with mac address as first match
00638            and broadcast address for all others */
00639         for (i = 0; i < 192; i++)
00640                 ptxb[i] = 0xFF;
00641         ptxb[0] = nic->node_addr[0];
00642         ptxb[1] = nic->node_addr[1];
00643         ptxb[4] = nic->node_addr[2];
00644         ptxb[5] = nic->node_addr[3];
00645         ptxb[8] = nic->node_addr[4];
00646         ptxb[9] = nic->node_addr[5];
00647 
00648         /* prepare the setup frame */
00649         txd[db->cur_tx].tdes1 = cpu_to_le32(0x890000c0);
00650         txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);
00651         update_cr6(db->cr6_data | 0x2000, BASE);
00652         outl(0x1, BASE + DCR1); /* Issue Tx polling */
00653         update_cr6(db->cr6_data, BASE);
00654         db->cur_tx++;
00655 }

static void dm9132_id_table ( struct nic *  nic  )  [static]

Referenced by dmfe_init_dm910x().

static u16 phy_read ( unsigned long  iobase,
u8  phy_addr,
u8  offset,
u32  chip_id 
) [static]

Definition at line 933 of file dmfe.c.

References DCR9, inw, ioaddr, PCI_DM9132_ID, PHY_DATA_0, PHY_DATA_1, phy_read_1bit(), phy_write_1bit(), and u16.

00935 {
00936         int i;
00937         u16 phy_data;
00938         unsigned long ioaddr;
00939 
00940         if (chip_id == PCI_DM9132_ID) {
00941                 /* DM9132 Chip */
00942                 ioaddr = iobase + 0x80 + offset * 4;
00943                 phy_data = inw(ioaddr);
00944         } else {
00945                 /* DM9102/DM9102A Chip */
00946                 ioaddr = iobase + DCR9;
00947 
00948                 /* Send 33 synchronization clock to Phy controller */
00949                 for (i = 0; i < 35; i++)
00950                         phy_write_1bit(ioaddr, PHY_DATA_1);
00951 
00952                 /* Send start command(01) to Phy */
00953                 phy_write_1bit(ioaddr, PHY_DATA_0);
00954                 phy_write_1bit(ioaddr, PHY_DATA_1);
00955 
00956                 /* Send read command(10) to Phy */
00957                 phy_write_1bit(ioaddr, PHY_DATA_1);
00958                 phy_write_1bit(ioaddr, PHY_DATA_0);
00959 
00960                 /* Send Phy addres */
00961                 for (i = 0x10; i > 0; i = i >> 1)
00962                         phy_write_1bit(ioaddr,
00963                                        phy_addr & i ? PHY_DATA_1 :
00964                                        PHY_DATA_0);
00965 
00966                 /* Send register addres */
00967                 for (i = 0x10; i > 0; i = i >> 1)
00968                         phy_write_1bit(ioaddr,
00969                                        offset & i ? PHY_DATA_1 :
00970                                        PHY_DATA_0);
00971 
00972                 /* Skip transition state */
00973                 phy_read_1bit(ioaddr);
00974 
00975                 /* read 16bit data */
00976                 for (phy_data = 0, i = 0; i < 16; i++) {
00977                         phy_data <<= 1;
00978                         phy_data |= phy_read_1bit(ioaddr);
00979                 }
00980         }
00981 
00982         return phy_data;
00983 }

static void phy_write ( unsigned long  iobase,
u8  phy_addr,
u8  offset,
u16  phy_data,
u32  chip_id 
) [static]

Definition at line 879 of file dmfe.c.

References DCR9, ioaddr, outw, PCI_DM9132_ID, PHY_DATA_0, PHY_DATA_1, phy_write_1bit(), and u16.

00881 {
00882         u16 i;
00883         unsigned long ioaddr;
00884 
00885         if (chip_id == PCI_DM9132_ID) {
00886                 ioaddr = iobase + 0x80 + offset * 4;
00887                 outw(phy_data, ioaddr);
00888         } else {
00889                 /* DM9102/DM9102A Chip */
00890                 ioaddr = iobase + DCR9;
00891 
00892                 /* Send 33 synchronization clock to Phy controller */
00893                 for (i = 0; i < 35; i++)
00894                         phy_write_1bit(ioaddr, PHY_DATA_1);
00895 
00896                 /* Send start command(01) to Phy */
00897                 phy_write_1bit(ioaddr, PHY_DATA_0);
00898                 phy_write_1bit(ioaddr, PHY_DATA_1);
00899 
00900                 /* Send write command(01) to Phy */
00901                 phy_write_1bit(ioaddr, PHY_DATA_0);
00902                 phy_write_1bit(ioaddr, PHY_DATA_1);
00903 
00904                 /* Send Phy addres */
00905                 for (i = 0x10; i > 0; i = i >> 1)
00906                         phy_write_1bit(ioaddr,
00907                                        phy_addr & i ? PHY_DATA_1 :
00908                                        PHY_DATA_0);
00909 
00910                 /* Send register addres */
00911                 for (i = 0x10; i > 0; i = i >> 1)
00912                         phy_write_1bit(ioaddr,
00913                                        offset & i ? PHY_DATA_1 :
00914                                        PHY_DATA_0);
00915 
00916                 /* written trasnition */
00917                 phy_write_1bit(ioaddr, PHY_DATA_1);
00918                 phy_write_1bit(ioaddr, PHY_DATA_0);
00919 
00920                 /* Write a word data to PHY controller */
00921                 for (i = 0x8000; i > 0; i >>= 1)
00922                         phy_write_1bit(ioaddr,
00923                                        phy_data & i ? PHY_DATA_1 :
00924                                        PHY_DATA_0);
00925         }
00926 }

static void phy_write_1bit ( unsigned long  ioaddr,
u32  phy_data 
) [static]

Definition at line 990 of file dmfe.c.

References MDCLKH, outl, and udelay().

00991 {
00992         outl(phy_data, ioaddr); /* MII Clock Low */
00993         udelay(1);
00994         outl(phy_data | MDCLKH, ioaddr);        /* MII Clock High */
00995         udelay(1);
00996         outl(phy_data, ioaddr); /* MII Clock Low */
00997         udelay(1);
00998 }

static u16 phy_read_1bit ( unsigned long  ioaddr  )  [static]

Definition at line 1005 of file dmfe.c.

References inl, outl, u16, and udelay().

01006 {
01007         u16 phy_data;
01008 
01009         outl(0x50000, ioaddr);
01010         udelay(1);
01011         phy_data = (inl(ioaddr) >> 19) & 0x1;
01012         outl(0x40000, ioaddr);
01013         udelay(1);
01014 
01015         return phy_data;
01016 }

static void dmfe_set_phyxcer ( struct nic *  nic  )  [static]

Referenced by dmfe_init_dm910x().

static void dmfe_parse_srom ( struct nic *  nic  )  [static]

Definition at line 1023 of file dmfe.c.

References dmfe_private::chip_id, dmfe_private::cr15_data, CR15_DEFAULT, dmfe_private::cr6_data, DMFE_100MFD, DMFE_100MHF, DMFE_10MFD, DMFE_1M_HPNA, dmfe_program_DM9801(), dmfe_program_DM9802(), dmfe_private::HPNA_command, dmfe_private::HPNA_present, dmfe_private::HPNA_timer, dmfe_private::NIC_capability, dmfe_private::phy_addr, phy_read(), dmfe_private::PHY_reg4, dmfe_private::srom, SROM_V41_CODE, u16, and update_cr6().

Referenced by dmfe_init_dm910x().

01024 {
01025         unsigned char *srom = db->srom;
01026         int dmfe_mode, tmp_reg;
01027 
01028         /* Init CR15 */
01029         db->cr15_data = CR15_DEFAULT;
01030 
01031         /* Check SROM Version */
01032         if (((int) srom[18] & 0xff) == SROM_V41_CODE) {
01033                 /* SROM V4.01 */
01034                 /* Get NIC support media mode */
01035                 db->NIC_capability = *(u16 *) (srom + 34);
01036                 db->PHY_reg4 = 0;
01037                 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
01038                         switch (db->NIC_capability & tmp_reg) {
01039                         case 0x1:
01040                                 db->PHY_reg4 |= 0x0020;
01041                                 break;
01042                         case 0x2:
01043                                 db->PHY_reg4 |= 0x0040;
01044                                 break;
01045                         case 0x4:
01046                                 db->PHY_reg4 |= 0x0080;
01047                                 break;
01048                         case 0x8:
01049                                 db->PHY_reg4 |= 0x0100;
01050                                 break;
01051                         }
01052                 }
01053 
01054                 /* Media Mode Force or not check */
01055                 dmfe_mode = *((int *) srom + 34) & *((int *) srom + 36);
01056                 switch (dmfe_mode) {
01057                 case 0x4:
01058                         dmfe_media_mode = DMFE_100MHF;
01059                         break;  /* 100MHF */
01060                 case 0x2:
01061                         dmfe_media_mode = DMFE_10MFD;
01062                         break;  /* 10MFD */
01063                 case 0x8:
01064                         dmfe_media_mode = DMFE_100MFD;
01065                         break;  /* 100MFD */
01066                 case 0x100:
01067                 case 0x200:
01068                         dmfe_media_mode = DMFE_1M_HPNA;
01069                         break;  /* HomePNA */
01070                 }
01071 
01072                 /* Special Function setting */
01073                 /* VLAN function */
01074                 if ((SF_mode & 0x1) || (srom[43] & 0x80))
01075                         db->cr15_data |= 0x40;
01076 
01077                 /* Flow Control */
01078                 if ((SF_mode & 0x2) || (srom[40] & 0x1))
01079                         db->cr15_data |= 0x400;
01080 
01081                 /* TX pause packet */
01082                 if ((SF_mode & 0x4) || (srom[40] & 0xe))
01083                         db->cr15_data |= 0x9800;
01084         }
01085 
01086         /* Parse HPNA parameter */
01087         db->HPNA_command = 1;
01088 
01089         /* Accept remote command or not */
01090         if (HPNA_rx_cmd == 0)
01091                 db->HPNA_command |= 0x8000;
01092 
01093         /* Issue remote command & operation mode */
01094         if (HPNA_tx_cmd == 1)
01095                 switch (HPNA_mode) {    /* Issue Remote Command */
01096                 case 0:
01097                         db->HPNA_command |= 0x0904;
01098                         break;
01099                 case 1:
01100                         db->HPNA_command |= 0x0a00;
01101                         break;
01102                 case 2:
01103                         db->HPNA_command |= 0x0506;
01104                         break;
01105                 case 3:
01106                         db->HPNA_command |= 0x0602;
01107                         break;
01108         } else
01109                 switch (HPNA_mode) {    /* Don't Issue */
01110                 case 0:
01111                         db->HPNA_command |= 0x0004;
01112                         break;
01113                 case 1:
01114                         db->HPNA_command |= 0x0000;
01115                         break;
01116                 case 2:
01117                         db->HPNA_command |= 0x0006;
01118                         break;
01119                 case 3:
01120                         db->HPNA_command |= 0x0002;
01121                         break;
01122                 }
01123 
01124         /* Check DM9801 or DM9802 present or not */
01125         db->HPNA_present = 0;
01126         update_cr6(db->cr6_data | 0x40000, BASE);
01127         tmp_reg = phy_read(BASE, db->phy_addr, 3, db->chip_id);
01128         if ((tmp_reg & 0xfff0) == 0xb900) {
01129                 /* DM9801 or DM9802 present */
01130                 db->HPNA_timer = 8;
01131                 if (phy_read(BASE, db->phy_addr, 31, db->chip_id) ==
01132                     0x4404) {
01133                         /* DM9801 HomeRun */
01134                         db->HPNA_present = 1;
01135                         dmfe_program_DM9801(nic, tmp_reg);
01136                 } else {
01137                         /* DM9802 LongRun */
01138                         db->HPNA_present = 2;
01139                         dmfe_program_DM9802(nic);
01140                 }
01141         }
01142 
01143 }

static void dmfe_program_DM9801 ( struct nic *  nic,
int   
) [static]

Referenced by dmfe_parse_srom().

static void dmfe_program_DM9802 ( struct nic *  nic  )  [static]

Referenced by dmfe_parse_srom().

static void dmfe_reset ( struct nic *  nic  )  [static]

Definition at line 244 of file dmfe.c.

References dmfe_private::chip_id, dmfe_private::chip_revision, dmfe_private::cr0_data, CR0_DEFAULT, dmfe_private::cr6_data, CR6_DEFAULT, CR6_SFT, dmfe_private::dm910x_chk_mode, dmfe_init_dm910x(), DMFE_TXTH_256, dmfe_private::NIC_capability, PCI_DM9132_ID, and dmfe_private::PHY_reg4.

Referenced by dmfe_probe().

00245 {
00246         /* system variable init */
00247         db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
00248 
00249         db->NIC_capability = 0xf;       /* All capability */
00250         db->PHY_reg4 = 0x1e0;
00251 
00252         /* CR6 operation mode decision */
00253         if (!chkmode || (db->chip_id == PCI_DM9132_ID) ||
00254             (db->chip_revision >= 0x02000030)) {
00255                 db->cr6_data |= DMFE_TXTH_256;
00256                 db->cr0_data = CR0_DEFAULT;
00257                 db->dm910x_chk_mode = 4;        /* Enter the normal mode */
00258         } else {
00259                 db->cr6_data |= CR6_SFT;        /* Store & Forward mode */
00260                 db->cr0_data = 0;
00261                 db->dm910x_chk_mode = 1;        /* Enter the check mode */
00262         }
00263         /* Initilize DM910X board */
00264         dmfe_init_dm910x(nic);
00265 
00266         return;
00267 }

static int dmfe_poll ( struct nic *  nic,
int  retrieve 
) [static]

Definition at line 343 of file dmfe.c.

References cpu_to_le32, dmfe_private::cr6_data, CR6_PM, dmfe_private::cur_rx, dmfe_private::dm910x_chk_mode, entry, le32_to_cpu, memcpy, nic::packet, nic::packetlen, printf(), rx_desc::rdes0, RX_ALLOC_SIZE, RX_DESC_CNT, rxb, rxd, rxlen, and u32.

00344 {
00345         u32 rdes0;
00346         int entry = db->cur_rx % RX_DESC_CNT;
00347         int rxlen;
00348         rdes0 = le32_to_cpu(rxd[entry].rdes0);
00349         if (rdes0 & 0x80000000)
00350                 return 0;
00351 
00352         if (!retrieve)
00353                 return 1;
00354 
00355         if ((rdes0 & 0x300) != 0x300) {
00356                 /* A packet without First/Last flag */
00357                 printf("strange Packet\n");
00358                 rxd[entry].rdes0 = cpu_to_le32(0x80000000);
00359                 return 0;
00360         } else {
00361                 /* A packet with First/Last flag */
00362                 rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
00363                 /* error summary bit check */
00364                 if (rdes0 & 0x8000) {
00365                         printf("Error\n");
00366                         return 0;
00367                 }
00368                 if (!(rdes0 & 0x8000) ||
00369                     ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
00370                         if (db->dm910x_chk_mode & 1)
00371                                 printf("Silly check mode\n");
00372 
00373                         nic->packetlen = rxlen;
00374                         memcpy(nic->packet, rxb + (entry * RX_ALLOC_SIZE),
00375                                nic->packetlen);
00376                 }
00377         }
00378         rxd[entry].rdes0 = cpu_to_le32(0x80000000);
00379         db->cur_rx++;
00380         return 1;
00381 }

static void dmfe_irq ( struct nic *nic  __unused,
irq_action_t action  __unused 
) [static]

Definition at line 383 of file dmfe.c.

References DISABLE, ENABLE, and FORCE.

00384 {
00385         switch ( action ) {
00386                 case DISABLE :
00387                         break;
00388                 case ENABLE :
00389                         break;
00390                 case FORCE :
00391                         break;
00392         }
00393 }

static void dmfe_transmit ( struct nic *  nic,
const char *  dest,
unsigned int  type,
unsigned int  size,
const char *  packet 
) [static]

Definition at line 398 of file dmfe.c.

References cpu_to_le32, dmfe_private::cr7_data, dmfe_private::cur_tx, DCR1, DCR7, ETH_ALEN, ETH_HLEN, ETH_ZLEN, htons, memcpy, nic::node_addr, outl, TX_DESC_CNT, txb, txd, u16, and u8.

00403 {       
00404         u16 nstype;
00405         u8 *ptxb;
00406 
00407         ptxb = &txb[db->cur_tx];
00408 
00409         /* Stop Tx */
00410         outl(0, BASE + DCR7);
00411         memcpy(ptxb, dest, ETH_ALEN);
00412         memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
00413         nstype = htons((u16) type);
00414         memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
00415         memcpy(ptxb + ETH_HLEN, packet, size);
00416 
00417         size += ETH_HLEN;
00418         while (size < ETH_ZLEN)
00419                 ptxb[size++] = '\0';
00420 
00421         /* setup the transmit descriptor */
00422         txd[db->cur_tx].tdes1 = cpu_to_le32(0xe1000000 | size);
00423         txd[db->cur_tx].tdes0 = cpu_to_le32(0x80000000);        /* give ownership to device */
00424 
00425         /* immediate transmit demand */
00426         outl(0x1, BASE + DCR1);
00427         outl(db->cr7_data, BASE + DCR7);
00428 
00429         /* Point to next TX descriptor */
00430         db->cur_tx++;
00431         db->cur_tx = db->cur_tx % TX_DESC_CNT;
00432 }

static void dmfe_disable ( struct nic *nic  __unused  )  [static]

Definition at line 437 of file dmfe.c.

References dmfe_private::chip_id, DCR0, DM910X_RESET, outl, dmfe_private::phy_addr, phy_write(), and udelay().

00437                                                       {
00438         /* Reset & stop DM910X board */
00439         outl(DM910X_RESET, BASE + DCR0);
00440         udelay(5);
00441         phy_write(BASE, db->phy_addr, 0, 0x8000, db->chip_id);
00442 
00443 }

static int dmfe_probe ( struct nic *  nic,
struct pci_device *  pci 
) [static]

Definition at line 451 of file dmfe.c.

References adjust_pci_device(), dmfe_private::chip_id, dmfe_private::chip_revision, dmfe_private::chip_type, cpu_to_le16, DBG, pci_device::device, dfx, dmfe_operations, dmfe_reset(), dprintf, pci_device::driver_name, eth_ntoa(), nic::ioaddr, pci_device::ioaddr, nic::irqno, nic::nic_op, nic::node_addr, pci_bar_start(), PCI_BASE_ADDRESS_0, pci_read_config_dword(), PCI_REVISION_ID, printf(), read_srom_word(), dmfe_private::srom, u16, u32, and pci_device::vendor.

00451                                                                   {
00452 
00453         uint32_t dev_rev, pci_pmr;
00454         int i;
00455 
00456         if (pci->ioaddr == 0)
00457                 return 0;
00458 
00459         BASE = pci->ioaddr;
00460         printf("dmfe.c: Found %s Vendor=0x%hX Device=0x%hX\n",
00461                pci->driver_name, pci->vendor, pci->device);
00462 
00463         /* Read Chip revision */
00464         pci_read_config_dword(pci, PCI_REVISION_ID, &dev_rev);
00465         dprintf(("Revision %lX\n", dev_rev));
00466 
00467         /* point to private storage */
00468         db = &dfx;
00469 
00470         db->chip_id = ((u32) pci->device << 16) | pci->vendor;
00471         BASE = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
00472         db->chip_revision = dev_rev;
00473 
00474         pci_read_config_dword(pci, 0x50, &pci_pmr);
00475         pci_pmr &= 0x70000;
00476         if ((pci_pmr == 0x10000) && (dev_rev == 0x02000031))
00477                 db->chip_type = 1;      /* DM9102A E3 */
00478         else
00479                 db->chip_type = 0;
00480 
00481         dprintf(("Chip type : %d\n", db->chip_type));
00482 
00483         /* read 64 word srom data */
00484         for (i = 0; i < 64; i++)
00485                 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(BASE, i));
00486 
00487         /* Set Node address */
00488         for (i = 0; i < 6; i++)
00489                 nic->node_addr[i] = db->srom[20 + i];
00490 
00491         /* Print out some hardware info */
00492         DBG ( "%s: %s at ioaddr %4.4lx\n", pci->driver_name, eth_ntoa ( nic->node_addr ), BASE );
00493 
00494         /* Set the card as PCI Bus Master */
00495         adjust_pci_device(pci);
00496 
00497         dmfe_reset(nic);
00498 
00499         nic->irqno  = 0;
00500         nic->ioaddr = pci->ioaddr;
00501 
00502         /* point to NIC specific routines */
00503         nic->nic_op     = &dmfe_operations;
00504 
00505         return 1;
00506 }

static void dmfe_descriptor_init ( struct nic *nic  __unused,
unsigned long  ioaddr 
) [static]

Definition at line 513 of file dmfe.c.

References cpu_to_le32, dmfe_private::cur_rx, dmfe_private::cur_tx, DCR3, DCR4, outl, RX_ALLOC_SIZE, RX_DESC_CNT, rxb, rxd, TX_DESC_CNT, txb, txd, virt_to_bus(), and virt_to_le32desc.

00514 {
00515         int i;
00516         db->cur_tx = 0;
00517         db->cur_rx = 0;
00518 
00519         /* tx descriptor start pointer */
00520         outl(virt_to_le32desc(&txd[0]), ioaddr + DCR4); /* TX DESC address */
00521 
00522         /* rx descriptor start pointer */
00523         outl(virt_to_le32desc(&rxd[0]), ioaddr + DCR3); /* RX DESC address */
00524 
00525         /* Init Transmit chain */
00526         for (i = 0; i < TX_DESC_CNT; i++) {
00527                 txd[i].tx_buf_ptr = &txb[i];
00528                 txd[i].tdes0 = cpu_to_le32(0);
00529                 txd[i].tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
00530                 txd[i].tdes2 = cpu_to_le32(virt_to_bus(&txb[i]));
00531                 txd[i].tdes3 = cpu_to_le32(virt_to_bus(&txd[i + 1]));
00532                 txd[i].next_tx_desc = &txd[i + 1];
00533         }
00534         /* Mark the last entry as wrapping the ring */
00535         txd[i - 1].tdes3 = virt_to_le32desc(&txd[0]);
00536         txd[i - 1].next_tx_desc = &txd[0];
00537 
00538         /* receive descriptor chain */
00539         for (i = 0; i < RX_DESC_CNT; i++) {
00540                 rxd[i].rx_skb_ptr = &rxb[i * RX_ALLOC_SIZE];
00541                 rxd[i].rdes0 = cpu_to_le32(0x80000000);
00542                 rxd[i].rdes1 = cpu_to_le32(0x01000600);
00543                 rxd[i].rdes2 =
00544                     cpu_to_le32(virt_to_bus(&rxb[i * RX_ALLOC_SIZE]));
00545                 rxd[i].rdes3 = cpu_to_le32(virt_to_bus(&rxd[i + 1]));
00546                 rxd[i].next_rx_desc = &rxd[i + 1];
00547         }
00548         /* Mark the last entry as wrapping the ring */
00549         rxd[i - 1].rdes3 = cpu_to_le32(virt_to_bus(&rxd[0]));
00550         rxd[i - 1].next_rx_desc = &rxd[0];
00551 
00552 }

static void dm9132_id_table ( struct nic *nic  __unused  )  [static]

Definition at line 576 of file dmfe.c.

References dprintf, ioaddr, outw, printf(), u16, u32, and u8.

00577 {
00578 #ifdef LINUX
00579         u16 *addrptr;
00580         u8 dmi_addr[8];
00581         unsigned long ioaddr = BASE + 0xc0;     /* ID Table */
00582         u32 hash_val;
00583         u16 i, hash_table[4];
00584 #endif
00585         dprintf(("dm9132_id_table\n"));
00586 
00587         printf("FIXME: This function is broken.  If you have this card contact "
00588                 "Timothy Legge at the etherboot-user list\n");
00589 
00590 #ifdef LINUX
00591         //DMFE_DBUG(0, "dm9132_id_table()", 0);
00592 
00593         /* Node address */
00594         addrptr = (u16 *) nic->node_addr;
00595         outw(addrptr[0], ioaddr);
00596         ioaddr += 4;
00597         outw(addrptr[1], ioaddr);
00598         ioaddr += 4;
00599         outw(addrptr[2], ioaddr);
00600         ioaddr += 4;
00601 
00602         /* Clear Hash Table */
00603         for (i = 0; i < 4; i++)
00604                 hash_table[i] = 0x0;
00605 
00606         /* broadcast address */
00607         hash_table[3] = 0x8000;
00608 
00609         /* the multicast address in Hash Table : 64 bits */
00610         for (mcptr = mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
00611                 hash_val = cal_CRC((char *) mcptr->dmi_addr, 6, 0) & 0x3f;
00612                 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
00613         }
00614 
00615         /* Write the hash table to MAC MD table */
00616         for (i = 0; i < 4; i++, ioaddr += 4)
00617                 outw(hash_table[i], ioaddr);
00618 #endif
00619 }

static void dmfe_set_phyxcer ( struct nic *nic  __unused  )  [static]

Definition at line 759 of file dmfe.c.

References dmfe_private::chip_id, dmfe_private::chip_type, dmfe_private::cr6_data, DMFE_100MFD, DMFE_100MHF, DMFE_10MFD, DMFE_10MHF, DMFE_AUTO, dmfe_private::media_mode, PCI_DM9009_ID, PCI_DM9102_ID, dmfe_private::phy_addr, phy_read(), dmfe_private::PHY_reg4, phy_write(), u16, and update_cr6().

00760 {
00761         u16 phy_reg;
00762 
00763         /* Select 10/100M phyxcer */
00764         db->cr6_data &= ~0x40000;
00765         update_cr6(db->cr6_data, BASE);
00766 
00767         /* DM9009 Chip: Phyxcer reg18 bit12=0 */
00768         if (db->chip_id == PCI_DM9009_ID) {
00769                 phy_reg =
00770                     phy_read(BASE, db->phy_addr, 18,
00771                              db->chip_id) & ~0x1000;
00772                 phy_write(BASE, db->phy_addr, 18, phy_reg, db->chip_id);
00773         }
00774 
00775         /* Phyxcer capability setting */
00776         phy_reg = phy_read(BASE, db->phy_addr, 4, db->chip_id) & ~0x01e0;
00777 
00778         if (db->media_mode & DMFE_AUTO) {
00779                 /* AUTO Mode */
00780                 phy_reg |= db->PHY_reg4;
00781         } else {
00782                 /* Force Mode */
00783                 switch (db->media_mode) {
00784                 case DMFE_10MHF:
00785                         phy_reg |= 0x20;
00786                         break;
00787                 case DMFE_10MFD:
00788                         phy_reg |= 0x40;
00789                         break;
00790                 case DMFE_100MHF:
00791                         phy_reg |= 0x80;
00792                         break;
00793                 case DMFE_100MFD:
00794                         phy_reg |= 0x100;
00795                         break;
00796                 }
00797                 if (db->chip_id == PCI_DM9009_ID)
00798                         phy_reg &= 0x61;
00799         }
00800 
00801         /* Write new capability to Phyxcer Reg4 */
00802         if (!(phy_reg & 0x01e0)) {
00803                 phy_reg |= db->PHY_reg4;
00804                 db->media_mode |= DMFE_AUTO;
00805         }
00806         phy_write(BASE, db->phy_addr, 4, phy_reg, db->chip_id);
00807 
00808         /* Restart Auto-Negotiation */
00809         if (db->chip_type && (db->chip_id == PCI_DM9102_ID))
00810                 phy_write(BASE, db->phy_addr, 0, 0x1800, db->chip_id);
00811         if (!db->chip_type)
00812                 phy_write(BASE, db->phy_addr, 0, 0x1200, db->chip_id);
00813 }

static void dmfe_program_DM9801 ( struct nic *nic  __unused,
int  HPNA_rev 
) [static]

Definition at line 1149 of file dmfe.c.

References dmfe_private::chip_id, DM9801_NOISE_FLOOR, dmfe_private::HPNA_command, dmfe_private::phy_addr, phy_read(), phy_write(), and u32.

01150 {
01151         u32 reg17, reg25;
01152 
01153         if (!HPNA_NoiseFloor)
01154                 HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
01155         switch (HPNA_rev) {
01156         case 0xb900:            /* DM9801 E3 */
01157                 db->HPNA_command |= 0x1000;
01158                 reg25 = phy_read(BASE, db->phy_addr, 24, db->chip_id);
01159                 reg25 = ((reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
01160                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
01161                 break;
01162         case 0xb901:            /* DM9801 E4 */
01163                 reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
01164                 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
01165                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
01166                 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
01167                 break;
01168         case 0xb902:            /* DM9801 E5 */
01169         case 0xb903:            /* DM9801 E6 */
01170         default:
01171                 db->HPNA_command |= 0x1000;
01172                 reg25 = phy_read(BASE, db->phy_addr, 25, db->chip_id);
01173                 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
01174                 reg17 = phy_read(BASE, db->phy_addr, 17, db->chip_id);
01175                 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
01176                 break;
01177         }
01178         phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id);
01179         phy_write(BASE, db->phy_addr, 17, reg17, db->chip_id);
01180         phy_write(BASE, db->phy_addr, 25, reg25, db->chip_id);
01181 }

static void dmfe_program_DM9802 ( struct nic *nic  __unused  )  [static]

Definition at line 1188 of file dmfe.c.

References dmfe_private::chip_id, DM9802_NOISE_FLOOR, dmfe_private::HPNA_command, dmfe_private::phy_addr, phy_read(), phy_write(), and u32.

01189 {
01190         u32 phy_reg;
01191 
01192         if (!HPNA_NoiseFloor)
01193                 HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
01194         phy_write(BASE, db->phy_addr, 16, db->HPNA_command, db->chip_id);
01195         phy_reg = phy_read(BASE, db->phy_addr, 25, db->chip_id);
01196         phy_reg = (phy_reg & 0xff00) + HPNA_NoiseFloor;
01197         phy_write(BASE, db->phy_addr, 25, phy_reg, db->chip_id);
01198 }

PCI_DRIVER ( dmfe_driver  ,
dmfe_nics  ,
PCI_NO_CLASS   
)

DRIVER ( "DMFE/PCI"  ,
nic_driver  ,
pci_driver  ,
dmfe_driver  ,
dmfe_probe  ,
dmfe_disable   
)

Variable Documentation

struct dmfe_private dfx [static]

Referenced by dmfe_probe().

struct dmfe_private* db [static]

Definition at line 176 of file dmfe.c.

static struct nic_operations dmfe_operations [static, read]

Initial value:

 {
        .connect        = dummy_connect,
        .poll           = dmfe_poll,
        .transmit       = dmfe_transmit,
        .irq            = dmfe_irq,

}

Definition at line 193 of file dmfe.c.

Referenced by dmfe_probe().

unsigned char dmfe_media_mode = DMFE_AUTO [static]

Definition at line 195 of file dmfe.c.

u32 dmfe_cr6_user_set [static]

Definition at line 196 of file dmfe.c.

u8 chkmode = 1 [static]

Definition at line 199 of file dmfe.c.

u8 HPNA_mode [static]

Definition at line 200 of file dmfe.c.

u8 HPNA_rx_cmd [static]

Definition at line 201 of file dmfe.c.

u8 HPNA_tx_cmd [static]

Definition at line 202 of file dmfe.c.

u8 HPNA_NoiseFloor [static]

Definition at line 203 of file dmfe.c.

u8 SF_mode [static]

Definition at line 204 of file dmfe.c.

struct tx_desc txd[TX_DESC_CNT]

Definition at line 212 of file dmfe.c.

unsigned char txb[TX_BUF_ALLOC *TX_DESC_CNT]

Definition at line 214 of file dmfe.c.

struct rx_desc rxd[RX_DESC_CNT]

Definition at line 215 of file dmfe.c.

unsigned char rxb[RX_ALLOC_SIZE *RX_DESC_CNT]

Definition at line 217 of file dmfe.c.

struct { ... } __shared

long int BASE [static]

Definition at line 225 of file dmfe.c.

struct pci_device_id dmfe_nics[] [static]

Initial value:

 {
        PCI_ROM(0x1282, 0x9100, "dmfe9100", "Davicom 9100", 0),
        PCI_ROM(0x1282, 0x9102, "dmfe9102", "Davicom 9102", 0),
        PCI_ROM(0x1282, 0x9009, "dmfe9009", "Davicom 9009", 0),
        PCI_ROM(0x1282, 0x9132, "dmfe9132", "Davicom 9132", 0), 
}

Definition at line 1208 of file dmfe.c.

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