cs89x0.h File Reference
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Define Documentation
| #define PP_CS8900_ISAINT 0x0022 |
| #define PP_CS8920_ISAINT 0x0370 |
| #define PP_CS8900_ISADMA 0x0024 |
| #define PP_CS8920_ISADMA 0x0374 |
| #define PP_DmaFrameCnt 0x0028 |
| #define PP_DmaByteCnt 0x002A |
| #define PP_CS8900_ISAMemB 0x002C |
| #define PP_CS8920_ISAMemB 0x0348 |
| #define PP_ISABootBase 0x0030 |
| #define PP_ISABootMask 0x0034 |
| #define PP_DebugReg 0x0044 |
| #define PP_LineCTL 0x0112 |
| #define PP_SelfCTL 0x0114 |
| #define PP_TestCTL 0x0118 |
| #define PP_AutoNegCTL 0x011C |
| #define PP_RxEvent 0x0124 |
| #define PP_TxEvent 0x0128 |
| #define PP_BufEvent 0x012C |
| #define PP_AutoNegST 0x013E |
| #define PP_TxCommand 0x0144 |
| #define PP_TxLength 0x0146 |
| #define PP_RxStatus 0x0400 |
| #define PP_RxLength 0x0402 |
| #define PP_RxFrame 0x0404 |
| #define PP_TxFrame 0x0A00 |
| #define DEFAULTIOBASE 0x0300 |
| #define CHIP_EISA_ID_SIG 0x630E |
| #define EISA_ID_SIG 0x630E |
| #define PART_NO_SIG 0x4000 |
| #define MONGOOSE_BIT 0x2000 |
| #define PRODUCT_ID_ADD 0x0002 |
| #define REG_TYPE_MASK 0x001F |
| #define ERSE_WR_ENBL 0x00F0 |
| #define ERSE_WR_DISABLE 0x0000 |
| #define RX_BUF_CFG 0x0003 |
| #define RX_CONTROL 0x0005 |
| #define TX_COMMAND 0x0009 |
| #define LINE_CONTROL 0x0013 |
| #define SELF_CONTROL 0x0015 |
| #define BUS_CONTROL 0x0017 |
| #define TEST_CONTROL 0x0019 |
| #define RX_MISS_COUNT 0x0010 |
| #define TX_COL_COUNT 0x0012 |
| #define LINE_STATUS 0x0014 |
| #define SELF_STATUS 0x0016 |
| #define BUS_STATUS 0x0018 |
| #define RX_STREAM_ENBL 0x0080 |
| #define RX_OK_ENBL 0x0100 |
| #define RX_DMA_ONLY 0x0200 |
| #define AUTO_RX_DMA 0x0400 |
| #define BUFFER_CRC 0x0800 |
| #define RX_CRC_ERROR_ENBL 0x1000 |
| #define RX_RUNT_ENBL 0x2000 |
| #define RX_EXTRA_DATA_ENBL 0x4000 |
| #define RX_IA_HASH_ACCEPT 0x0040 |
| #define RX_PROM_ACCEPT 0x0080 |
| #define RX_OK_ACCEPT 0x0100 |
| #define RX_MULTCAST_ACCEPT 0x0200 |
| #define RX_IA_ACCEPT 0x0400 |
| #define RX_BROADCAST_ACCEPT 0x0800 |
| #define RX_BAD_CRC_ACCEPT 0x1000 |
| #define RX_RUNT_ACCEPT 0x2000 |
| #define RX_EXTRA_DATA_ACCEPT 0x4000 |
| #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT) |
| #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) |
| #define TX_LOST_CRS_ENBL 0x0040 |
| #define TX_SQE_ERROR_ENBL 0x0080 |
| #define TX_OK_ENBL 0x0100 |
| #define TX_LATE_COL_ENBL 0x0200 |
| #define TX_JBR_ENBL 0x0400 |
| #define TX_ANY_COL_ENBL 0x0800 |
| #define TX_16_COL_ENBL 0x8000 |
| #define TX_START_4_BYTES 0x0000 |
| #define TX_START_64_BYTES 0x0040 |
| #define TX_START_128_BYTES 0x0080 |
| #define TX_START_ALL_BYTES 0x00C0 |
| #define TX_ONE_COL 0x0200 |
| #define TX_TWO_PART_DEFF_DISABLE 0x0400 |
| #define GENERATE_SW_INTERRUPT 0x0040 |
| #define RX_DMA_ENBL 0x0080 |
| #define READY_FOR_TX_ENBL 0x0100 |
| #define TX_UNDERRUN_ENBL 0x0200 |
| #define RX_MISS_ENBL 0x0400 |
| #define RX_128_BYTE_ENBL 0x0800 |
| #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000 |
| #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000 |
| #define RX_DEST_MATCH_ENBL 0x8000 |
| #define SERIAL_RX_ON 0x0040 |
| #define SERIAL_TX_ON 0x0080 |
| #define AUTO_AUI_10BASET 0x0200 |
| #define MODIFIED_BACKOFF 0x0800 |
| #define NO_AUTO_POLARITY 0x1000 |
| #define TWO_PART_DEFDIS 0x2000 |
| #define LOW_RX_SQUELCH 0x4000 |
| #define POWER_ON_RESET 0x0040 |
| #define AUTO_WAKEUP 0x0400 |
| #define RESET_RX_DMA 0x0040 |
| #define DMA_BURST_MODE 0x0800 |
| #define IO_CHANNEL_READY_ON 0x1000 |
| #define RX_DMA_SIZE_64K 0x2000 |
| #define ENABLE_IRQ 0x8000 |
| #define ENDEC_LOOPBACK 0x0200 |
| #define AUI_LOOPBACK 0x0400 |
| #define BACKOFF_OFF 0x0800 |
| #define RX_IA_HASHED 0x0040 |
| #define RX_DRIBBLE 0x0080 |
| #define RX_BROADCAST 0x0800 |
| #define RX_CRC_ERROR 0x1000 |
| #define RX_EXTRA_DATA 0x4000 |
| #define HASH_INDEX_MASK 0x0FC00 |
| #define TX_LOST_CRS 0x0040 |
| #define TX_SQE_ERROR 0x0080 |
| #define TX_LATE_COL 0x0200 |
| #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS) |
| #define TX_COL_COUNT_MASK 0x7800 |
| #define SW_INTERRUPT 0x0040 |
| #define READY_FOR_TX 0x0100 |
| #define TX_UNDERRUN 0x0200 |
| #define RX_128_BYTE 0x0800 |
| #define TX_COL_OVRFLW 0x1000 |
| #define RX_MISS_OVRFLW 0x2000 |
| #define RX_DEST_MATCH 0x8000 |
| #define TENBASET_ON 0x0200 |
| #define POLARITY_OK 0x1000 |
| #define ACTIVE_33V 0x0040 |
| #define EEPROM_PRESENT 0x0200 |
| #define EL_PRESENT 0x0800 |
| #define EE_SIZE_64 0x1000 |
| #define TX_BID_ERROR 0x0080 |
| #define READY_FOR_TX_NOW 0x0100 |
| #define RE_NEG_NOW 0x0040 |
| #define AUTO_NEG_ENABLE 0x0100 |
| #define NLP_ENABLE 0x0200 |
| #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE) |
| #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW) |
| #define AUTO_NEG_BUSY 0x0080 |
| #define FLP_LINK_GOOD 0x0800 |
| #define LINK_FAULT 0x1000 |
| #define HDX_ACTIVE 0x4000 |
| #define FDX_ACTIVE 0x8000 |
| #define ISQ_RECEIVER_EVENT 0x04 |
| #define ISQ_TRANSMITTER_EVENT 0x08 |
| #define ISQ_BUFFER_EVENT 0x0c |
| #define ISQ_RX_MISS_EVENT 0x10 |
| #define ISQ_TX_COL_EVENT 0x12 |
| #define ISQ_EVENT_MASK 0x003F |
| #define AUTOINCREMENT 0x8000 |
| #define TXRXBUFSIZE 0x0600 |
| #define RXDMABUFSIZE 0x8000 |
| #define TXRX_LENGTH_MASK 0x07FF |
| #define RCV_AUTO_DMA 0x100 |
| #define RCV_DMA_ALL 0x400 |
| #define RCV_FIXED_DATA 0x800 |
| #define RCV_MEMORY 0x2000 |
| #define PKT_START PP_TxFrame |
| #define RX_FRAME_PORT 0x0000 |
| #define TX_FRAME_PORT RX_FRAME_PORT |
| #define TX_CMD_PORT 0x0004 |
| #define TX_AFTER_381 0x0020 |
| #define TX_AFTER_ALL 0x00C0 |
| #define TX_LEN_PORT 0x0006 |
| #define EEPROM_WRITE_EN 0x00F0 |
| #define EEPROM_WRITE_DIS 0x0000 |
| #define EEPROM_WRITE_CMD 0x0100 |
| #define EEPROM_READ_CMD 0x0200 |
| #define RBUF_EVENT_HIGH 1 |
| #define BIOS_START_SEG 0x0c000 |
| #define BIOS_OFFSET_INC 0x0200 |
| #define BIOS_LAST_OFFSET 0x0fc00 |
| #define ISA_CNF_OFFSET 0x6 |
| #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) |
| #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) |
| #define EE_FORCE_FDX 0x8000 |
| #define EE_NLP_ENABLE 0x0200 |
| #define EE_AUTO_NEG_ENABLE 0x0100 |
| #define EE_ALLOW_FDX 0x0080 |
| #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX) |
| #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) |
| #define A_CNF_10B_T 0x0001 |
| #define A_CNF_10B_2 0x0004 |
| #define A_CNF_MEDIA_TYPE 0x0060 |
| #define A_CNF_MEDIA_AUTO 0x0000 |
| #define A_CNF_MEDIA_10B_T 0x0020 |
| #define A_CNF_MEDIA_AUI 0x0040 |
| #define A_CNF_MEDIA_10B_2 0x0060 |
| #define A_CNF_DC_DC_POLARITY 0x0080 |
| #define A_CNF_NO_AUTO_POLARITY 0x2000 |
| #define A_CNF_LOW_RX_SQUELCH 0x4000 |
| #define A_CNF_EXTND_10B_2 0x8000 |
| #define PACKET_PAGE_OFFSET 0x8 |
| #define INT_NO_MASK 0x000F |
| #define DMA_NO_MASK 0x0070 |
| #define ISA_DMA_SIZE 0x0200 |
| #define ISA_AUTO_RxDMA 0x0400 |
| #define STREAM_TRANSFER 0x2000 |
| #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) |
| #define DMA_RESETFF 0x0D8 |
| #define DMA_SIZE (16*1024) |
| #define REVISON_BITS 0x1F00 |
| #define EEVER_NUMBER 0x12 |
| #define CHKSUM_VAL 0x0000 |
| #define START_EEPROM_DATA 0x001c |
| #define IRQ_MAP_EEPROM_DATA 0x0046 |
| #define IRQ_MAP_LEN 0x0004 |
| #define PNP_IRQ_FRMT 0x0022 |
| #define CS8900_IRQ_MAP 0x1c20 |
| #define CS8920_NO_INTS 0x0F |
| #define PNP_ADD_PORT 0x0279 |
| #define PNP_WRITE_PORT 0x0A79 |
| #define GET_PNP_ISA_STRUCT 0x40 |
| #define PNP_ISA_STRUCT_LEN 0x06 |
| #define PNP_CSN_CNT_OFF 0x01 |
| #define PNP_RD_PORT_OFF 0x02 |
| #define PNP_FUNCTION_OK 0x00 |
| #define PNP_RSRC_DATA 0x04 |
| #define PNP_RSRC_READY 0x01 |
| #define PNP_ACTIVATE 0x30 |
| #define PNP_CNF_IO_H 0x60 |
| #define PNP_CNF_IO_L 0x61 |
Function Documentation
| FILE_LICENCE |
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GPL2_ONLY |
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Per an email message from Russ Nelson <nelson@crynwr.com> on 18 March 2008 this file is now licensed under GPL Version 2.
From: Russ Nelson <nelson@crynwr.com> Date: Tue, 18 Mar 2008 12:42:00 -0400 Subject: Re: [Etherboot-developers] cs89x0 driver in etherboot -- quote from email As copyright holder, if I say it doesn't conflict with the GPL, then it doesn't conflict with the GPL.
However, there's no point in causing people's brains to overheat, so yes, I grant permission for the code to be relicensed under the GPLv2. Please make sure that this change in licensing makes its way upstream. -russ -- quote from email
