#include "atl1e.h"Go to the source code of this file.
| #define TX_DESC_COUNT 32 |
| #define RX_MEM_SIZE 8192 |
| #define MAX_FRAME_SIZE 1500 |
Definition at line 31 of file atl1e.c.
Referenced by atl1e_configure(), atl1e_configure_tx(), and atl1e_init_ring_resources().
| #define PREAMBLE_LEN 7 |
| #define RX_JUMBO_THRESH |
Value:
((MAX_FRAME_SIZE + ETH_HLEN + \ VLAN_HLEN + ETH_FCS_LEN + 7) >> 3)
Definition at line 35 of file atl1e.c.
Referenced by atl1e_configure_rx().
| #define IMT_VAL 100 |
| #define ICT_VAL 50000 |
| #define SMB_TIMER 200000 |
| #define RRD_THRESH 1 |
| #define TPD_BURST 5 |
| #define TPD_THRESH (TX_DESC_COUNT / 2) |
| #define RX_COUNT_DOWN 4 |
| #define TX_COUNT_DOWN (IMT_VAL * 4 / 3) |
| #define DMAR_DLY_CNT 15 |
| #define DMAW_DLY_CNT 4 |
| FILE_LICENCE | ( | GPL2_OR_LATER | ) |
| static void atl1e_setup_mac_ctrl | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 617 of file atl1e.c.
References AT_WRITE_REG, FULL_DUPLEX, atl1e_adapter::hw, atl1e_adapter::link_duplex, atl1e_adapter::link_speed, MAC_CTRL_ADD_CRC, MAC_CTRL_BC_EN, MAC_CTRL_DUPLX, MAC_CTRL_MC_ALL_EN, MAC_CTRL_PAD, MAC_CTRL_PRMLEN_MASK, MAC_CTRL_PRMLEN_SHIFT, MAC_CTRL_RX_EN, MAC_CTRL_RX_FLOW, MAC_CTRL_SPEED_1000, MAC_CTRL_SPEED_10_100, MAC_CTRL_SPEED_SHIFT, MAC_CTRL_TX_EN, MAC_CTRL_TX_FLOW, PREAMBLE_LEN, REG_MAC_CTRL, SPEED_1000, and u32.
Referenced by atl1e_check_link().
00618 { 00619 u32 value; 00620 struct atl1e_hw *hw = &adapter->hw; 00621 00622 /* Config MAC CTRL Register */ 00623 value = MAC_CTRL_TX_EN | 00624 MAC_CTRL_RX_EN ; 00625 00626 if (FULL_DUPLEX == adapter->link_duplex) 00627 value |= MAC_CTRL_DUPLX; 00628 00629 value |= ((u32)((SPEED_1000 == adapter->link_speed) ? 00630 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) << 00631 MAC_CTRL_SPEED_SHIFT); 00632 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); 00633 00634 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); 00635 value |= ((PREAMBLE_LEN & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); 00636 00637 value |= MAC_CTRL_BC_EN; 00638 value |= MAC_CTRL_MC_ALL_EN; 00639 00640 AT_WRITE_REG(hw, REG_MAC_CTRL, value); 00641 }
| static void atl1e_irq_enable | ( | struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 92 of file atl1e.c.
References AT_WRITE_FLUSH, AT_WRITE_REG, atl1e_adapter::hw, IMR_NORMAL_MASK, REG_IMR, and REG_ISR.
Referenced by atl1e_irq().
00093 { 00094 AT_WRITE_REG(&adapter->hw, REG_ISR, 0); 00095 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); 00096 AT_WRITE_FLUSH(&adapter->hw); 00097 }
| static void atl1e_irq_disable | ( | struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 103 of file atl1e.c.
References AT_WRITE_FLUSH, AT_WRITE_REG, atl1e_adapter::hw, and REG_IMR.
Referenced by atl1e_irq(), and atl1e_up().
00104 { 00105 AT_WRITE_REG(&adapter->hw, REG_IMR, 0); 00106 AT_WRITE_FLUSH(&adapter->hw); 00107 }
| static void atl1e_irq_reset | ( | struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 113 of file atl1e.c.
References AT_WRITE_FLUSH, AT_WRITE_REG, atl1e_adapter::hw, REG_IMR, and REG_ISR.
Referenced by atl1e_poll().
00114 { 00115 AT_WRITE_REG(&adapter->hw, REG_ISR, 0); 00116 AT_WRITE_REG(&adapter->hw, REG_IMR, 0); 00117 AT_WRITE_FLUSH(&adapter->hw); 00118 }
| static void atl1e_reset | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 120 of file atl1e.c.
References atl1e_down(), and atl1e_up().
Referenced by atl1e_clean_rx_irq(), and atl1e_poll().
00121 { 00122 atl1e_down(adapter); 00123 atl1e_up(adapter); 00124 }
| static int atl1e_check_link | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 126 of file atl1e.c.
References AT_READ_REG, AT_WRITE_REG, atl1e_get_speed_and_duplex(), atl1e_read_phy_reg(), atl1e_setup_mac_ctrl(), BMSR_LSTATUS, DBG, FULL_DUPLEX, atl1e_adapter::hw, atl1e_adapter::link_duplex, atl1e_adapter::link_speed, MAC_CTRL_RX_EN, MII_BMSR, net_device::name, atl1e_adapter::netdev, netdev, netdev_link_down(), netdev_link_ok(), netdev_link_up(), REG_MAC_CTRL, SPEED_0, u16, and u32.
Referenced by atl1e_poll().
00127 { 00128 struct atl1e_hw *hw = &adapter->hw; 00129 struct net_device *netdev = adapter->netdev; 00130 int err = 0; 00131 u16 speed, duplex, phy_data; 00132 00133 /* MII_BMSR must read twise */ 00134 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); 00135 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); 00136 00137 if ((phy_data & BMSR_LSTATUS) == 0) { 00138 /* link down */ 00139 if (netdev_link_ok(netdev)) { /* old link state: Up */ 00140 u32 value; 00141 /* disable rx */ 00142 value = AT_READ_REG(hw, REG_MAC_CTRL); 00143 value &= ~MAC_CTRL_RX_EN; 00144 AT_WRITE_REG(hw, REG_MAC_CTRL, value); 00145 adapter->link_speed = SPEED_0; 00146 00147 DBG("atl1e: %s link is down\n", netdev->name); 00148 netdev_link_down(netdev); 00149 } 00150 } else { 00151 /* Link Up */ 00152 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex); 00153 if (err) 00154 return err; 00155 00156 /* link result is our setting */ 00157 if (adapter->link_speed != speed || 00158 adapter->link_duplex != duplex) { 00159 adapter->link_speed = speed; 00160 adapter->link_duplex = duplex; 00161 atl1e_setup_mac_ctrl(adapter); 00162 00163 DBG("atl1e: %s link is up, %d Mbps, %s duplex\n", 00164 netdev->name, adapter->link_speed, 00165 adapter->link_duplex == FULL_DUPLEX ? 00166 "full" : "half"); 00167 netdev_link_up(netdev); 00168 } 00169 } 00170 return 0; 00171 }
| static int atl1e_mdio_read | ( | struct net_device * | netdev, | |
| int phy_id | __unused, | |||
| int | reg_num | |||
| ) | [static] |
Definition at line 173 of file atl1e.c.
References atl1e_read_phy_reg(), atl1e_adapter::hw, MDIO_REG_ADDR_MASK, netdev_priv(), and u16.
Referenced by atl1e_probe().
00175 { 00176 struct atl1e_adapter *adapter = netdev_priv(netdev); 00177 u16 result; 00178 00179 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result); 00180 return result; 00181 }
| static void atl1e_mdio_write | ( | struct net_device * | netdev, | |
| int phy_id | __unused, | |||
| int | reg_num, | |||
| int | val | |||
| ) | [static] |
Definition at line 183 of file atl1e.c.
References atl1e_write_phy_reg(), atl1e_adapter::hw, MDIO_REG_ADDR_MASK, and netdev_priv().
Referenced by atl1e_probe().
00185 { 00186 struct atl1e_adapter *adapter = netdev_priv(netdev); 00187 00188 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val); 00189 }
| static void atl1e_setup_pcicmd | ( | struct pci_device * | pdev | ) | [static] |
Definition at line 191 of file atl1e.c.
References mdelay(), PCI_COMMAND, PCI_COMMAND_MASTER, PCI_COMMAND_MEM, pci_read_config_word(), pci_write_config_dword(), pci_write_config_word(), REG_PM_CTRLSTAT, and u16.
Referenced by atl1e_probe().
00192 { 00193 u16 cmd; 00194 00195 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 00196 cmd |= (PCI_COMMAND_MEM | PCI_COMMAND_MASTER); 00197 pci_write_config_word(pdev, PCI_COMMAND, cmd); 00198 00199 /* 00200 * some motherboards BIOS(PXE/EFI) driver may set PME 00201 * while they transfer control to OS (Windows/Linux) 00202 * so we should clear this bit before NIC work normally 00203 */ 00204 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); 00205 mdelay(1); 00206 }
| static int atl1e_sw_init | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 216 of file atl1e.c.
References AT_READ_REG, athr_l1e, athr_l2e_revA, athr_l2e_revB, atl1e_dma_req_1024, atl1e_hw::dmar_block, atl1e_hw::dmaw_block, atl1e_hw::emi_ca, FULL_DUPLEX, atl1e_adapter::hw, atl1e_adapter::link_duplex, atl1e_adapter::link_speed, atl1e_adapter::netdev, netdev_link_down(), atl1e_hw::nic_type, pci_read_config_byte(), PCI_REVISION_ID, atl1e_adapter::pdev, atl1e_hw::phy_configured, PHY_STATUS_100M, PHY_STATUS_EMI_CA, REG_PHY_STATUS, SPEED_0, u32, and u8.
Referenced by atl1e_probe().
00217 { 00218 struct atl1e_hw *hw = &adapter->hw; 00219 struct pci_device *pdev = adapter->pdev; 00220 u32 phy_status_data = 0; 00221 u8 rev_id = 0; 00222 00223 adapter->link_speed = SPEED_0; /* hardware init */ 00224 adapter->link_duplex = FULL_DUPLEX; 00225 00226 /* PCI config space info */ 00227 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id); 00228 00229 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS); 00230 /* nic type */ 00231 if (rev_id >= 0xF0) { 00232 hw->nic_type = athr_l2e_revB; 00233 } else { 00234 if (phy_status_data & PHY_STATUS_100M) 00235 hw->nic_type = athr_l1e; 00236 else 00237 hw->nic_type = athr_l2e_revA; 00238 } 00239 00240 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS); 00241 00242 hw->emi_ca = !!(phy_status_data & PHY_STATUS_EMI_CA); 00243 00244 hw->phy_configured = 0; 00245 00246 /* need confirm */ 00247 00248 hw->dmar_block = atl1e_dma_req_1024; 00249 hw->dmaw_block = atl1e_dma_req_1024; 00250 00251 netdev_link_down(adapter->netdev); 00252 00253 return 0; 00254 }
| static void atl1e_clean_tx_ring | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 260 of file atl1e.c.
References atl1e_tx_ring::count, atl1e_tx_ring::desc, atl1e_tx_buffer::dma, index, atl1e_tx_buffer::iob, memset(), atl1e_adapter::netdev, netdev_tx_complete(), NULL, atl1e_tx_ring::tx_buffer, atl1e_adapter::tx_ring, tx_ring, and u16.
Referenced by atl1e_down(), and atl1e_free_ring_resources().
00261 { 00262 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *) 00263 &adapter->tx_ring; 00264 struct atl1e_tx_buffer *tx_buffer = NULL; 00265 u16 index, ring_count = tx_ring->count; 00266 00267 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL) 00268 return; 00269 00270 for (index = 0; index < ring_count; index++) { 00271 tx_buffer = &tx_ring->tx_buffer[index]; 00272 if (tx_buffer->iob) { 00273 netdev_tx_complete(adapter->netdev, tx_buffer->iob); 00274 tx_buffer->dma = 0; 00275 tx_buffer->iob = NULL; 00276 } 00277 } 00278 00279 /* Zero out Tx-buffers */ 00280 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) * 00281 ring_count); 00282 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) * 00283 ring_count); 00284 }
| static void atl1e_clean_rx_ring | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 290 of file atl1e.c.
References atl1e_rx_page::addr, AT_PAGE_NUM_PER_QUEUE, memset(), NULL, atl1e_rx_ring::real_page_size, atl1e_adapter::ring_vir_addr, atl1e_rx_page_desc::rx_page, atl1e_rx_ring::rx_page_desc, atl1e_adapter::rx_ring, rx_ring, and u16.
Referenced by atl1e_down(), and atl1e_free_ring_resources().
00291 { 00292 struct atl1e_rx_ring *rx_ring = 00293 (struct atl1e_rx_ring *)&adapter->rx_ring; 00294 struct atl1e_rx_page_desc *rx_page_desc = &rx_ring->rx_page_desc; 00295 u16 j; 00296 00297 if (adapter->ring_vir_addr == NULL) 00298 return; 00299 00300 /* Zero out the descriptor ring */ 00301 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { 00302 if (rx_page_desc->rx_page[j].addr != NULL) { 00303 memset(rx_page_desc->rx_page[j].addr, 0, 00304 rx_ring->real_page_size); 00305 } 00306 } 00307 }
| static void atl1e_cal_ring_size | ( | struct atl1e_adapter * | adapter, | |
| u32 * | ring_size | |||
| ) | [static] |
Definition at line 309 of file atl1e.c.
References AT_PAGE_NUM_PER_QUEUE, atl1e_tx_ring::count, atl1e_rx_ring::real_page_size, atl1e_adapter::rx_ring, atl1e_adapter::tx_ring, and u32.
Referenced by atl1e_init_ring_resources().
00310 { 00311 *ring_size = ((u32)(adapter->tx_ring.count * 00312 sizeof(struct atl1e_tpd_desc) + 7 00313 /* tx ring, qword align */ 00314 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE 00315 + 31 00316 /* rx ring, 32 bytes align */ 00317 + (1 + AT_PAGE_NUM_PER_QUEUE) * 00318 sizeof(u32) + 3)); 00319 /* tx, rx cmd, dword align */ 00320 }
| static void atl1e_init_ring_resources | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 322 of file atl1e.c.
References atl1e_cal_ring_size(), atl1e_rx_ring::desc, ETH_FCS_LEN, ETH_HLEN, MAX_FRAME_SIZE, NULL, atl1e_rx_ring::page_size, atl1e_rx_ring::real_page_size, atl1e_adapter::ring_size, atl1e_adapter::ring_vir_addr, atl1e_adapter::rx_ring, rx_ring, atl1e_adapter::tx_ring, tx_ring, and VLAN_HLEN.
Referenced by atl1e_open().
00323 { 00324 struct atl1e_tx_ring *tx_ring = NULL; 00325 struct atl1e_rx_ring *rx_ring = NULL; 00326 00327 tx_ring = &adapter->tx_ring; 00328 rx_ring = &adapter->rx_ring; 00329 00330 rx_ring->real_page_size = adapter->rx_ring.page_size 00331 + MAX_FRAME_SIZE 00332 + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN; 00333 rx_ring->real_page_size = (rx_ring->real_page_size + 31) & ~31; 00334 atl1e_cal_ring_size(adapter, &adapter->ring_size); 00335 00336 adapter->ring_vir_addr = NULL; 00337 adapter->rx_ring.desc = NULL; 00338 00339 return; 00340 }
| static void atl1e_init_ring_ptrs | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 345 of file atl1e.c.
References AT_PAGE_NUM_PER_QUEUE, atl1e_tx_ring::next_to_clean, atl1e_tx_ring::next_to_use, NULL, atl1e_rx_page::read_offset, atl1e_rx_page_desc::rx_nxseq, atl1e_rx_page_desc::rx_page, atl1e_rx_ring::rx_page_desc, atl1e_adapter::rx_ring, rx_ring, atl1e_rx_page_desc::rx_using, atl1e_adapter::tx_ring, tx_ring, and atl1e_rx_page::write_offset_addr.
Referenced by atl1e_up().
00346 { 00347 struct atl1e_tx_ring *tx_ring = NULL; 00348 struct atl1e_rx_ring *rx_ring = NULL; 00349 struct atl1e_rx_page_desc *rx_page_desc = NULL; 00350 int j; 00351 00352 tx_ring = &adapter->tx_ring; 00353 rx_ring = &adapter->rx_ring; 00354 rx_page_desc = &rx_ring->rx_page_desc; 00355 00356 tx_ring->next_to_use = 0; 00357 tx_ring->next_to_clean = 0; 00358 00359 rx_page_desc->rx_using = 0; 00360 rx_page_desc->rx_nxseq = 0; 00361 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { 00362 *rx_page_desc->rx_page[j].write_offset_addr = 0; 00363 rx_page_desc->rx_page[j].read_offset = 0; 00364 } 00365 }
| static void atl1e_free_ring_resources | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 373 of file atl1e.c.
References atl1e_clean_rx_ring(), atl1e_clean_tx_ring(), free(), free_dma(), NULL, atl1e_adapter::ring_dma, atl1e_adapter::ring_size, atl1e_adapter::ring_vir_addr, atl1e_tx_ring::tx_buffer, and atl1e_adapter::tx_ring.
Referenced by atl1e_close(), atl1e_open(), atl1e_remove(), and atl1e_setup_ring_resources().
00374 { 00375 atl1e_clean_tx_ring(adapter); 00376 atl1e_clean_rx_ring(adapter); 00377 00378 if (adapter->ring_vir_addr) { 00379 free_dma(adapter->ring_vir_addr, adapter->ring_size); 00380 adapter->ring_vir_addr = NULL; 00381 adapter->ring_dma = 0; 00382 } 00383 00384 if (adapter->tx_ring.tx_buffer) { 00385 free(adapter->tx_ring.tx_buffer); 00386 adapter->tx_ring.tx_buffer = NULL; 00387 } 00388 }
| static int atl1e_setup_ring_resources | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 396 of file atl1e.c.
References atl1e_rx_page::addr, AT_PAGE_NUM_PER_QUEUE, atl1e_free_ring_resources(), atl1e_tx_ring::cmb, atl1e_tx_ring::cmb_dma, atl1e_tx_ring::count, DBG, atl1e_tx_ring::desc, atl1e_rx_page::dma, atl1e_tx_ring::dma, EINVAL, ENOMEM, malloc_dma(), memset(), net_device::name, atl1e_adapter::netdev, NULL, offset, atl1e_rx_ring::real_page_size, atl1e_adapter::ring_dma, atl1e_adapter::ring_size, atl1e_adapter::ring_vir_addr, atl1e_rx_page_desc::rx_page, atl1e_rx_ring::rx_page_desc, atl1e_adapter::rx_ring, rx_ring, size, atl1e_tx_ring::tx_buffer, atl1e_adapter::tx_ring, tx_ring, u32, virt_to_bus(), atl1e_rx_page::write_offset_addr, atl1e_rx_page::write_offset_dma, and zalloc().
Referenced by atl1e_open().
00397 { 00398 struct atl1e_tx_ring *tx_ring; 00399 struct atl1e_rx_ring *rx_ring; 00400 struct atl1e_rx_page_desc *rx_page_desc; 00401 int size, j; 00402 u32 offset = 0; 00403 int err = 0; 00404 00405 if (adapter->ring_vir_addr != NULL) 00406 return 0; /* alloced already */ 00407 00408 tx_ring = &adapter->tx_ring; 00409 rx_ring = &adapter->rx_ring; 00410 00411 /* real ring DMA buffer */ 00412 00413 size = adapter->ring_size; 00414 adapter->ring_vir_addr = malloc_dma(adapter->ring_size, 32); 00415 00416 if (adapter->ring_vir_addr == NULL) { 00417 DBG("atl1e: out of memory allocating %d bytes for %s ring\n", 00418 adapter->ring_size, adapter->netdev->name); 00419 return -ENOMEM; 00420 } 00421 00422 adapter->ring_dma = virt_to_bus(adapter->ring_vir_addr); 00423 memset(adapter->ring_vir_addr, 0, adapter->ring_size); 00424 00425 rx_page_desc = &rx_ring->rx_page_desc; 00426 00427 /* Init TPD Ring */ 00428 tx_ring->dma = (adapter->ring_dma + 7) & ~7; 00429 offset = tx_ring->dma - adapter->ring_dma; 00430 tx_ring->desc = (struct atl1e_tpd_desc *) 00431 (adapter->ring_vir_addr + offset); 00432 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count); 00433 tx_ring->tx_buffer = zalloc(size); 00434 if (tx_ring->tx_buffer == NULL) { 00435 DBG("atl1e: out of memory allocating %d bytes for %s txbuf\n", 00436 size, adapter->netdev->name); 00437 err = -ENOMEM; 00438 goto failed; 00439 } 00440 00441 /* Init RXF-Pages */ 00442 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count); 00443 offset = (offset + 31) & ~31; 00444 00445 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { 00446 rx_page_desc->rx_page[j].dma = 00447 adapter->ring_dma + offset; 00448 rx_page_desc->rx_page[j].addr = 00449 adapter->ring_vir_addr + offset; 00450 offset += rx_ring->real_page_size; 00451 } 00452 00453 /* Init CMB dma address */ 00454 tx_ring->cmb_dma = adapter->ring_dma + offset; 00455 tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset); 00456 offset += sizeof(u32); 00457 00458 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { 00459 rx_page_desc->rx_page[j].write_offset_dma = 00460 adapter->ring_dma + offset; 00461 rx_page_desc->rx_page[j].write_offset_addr = 00462 adapter->ring_vir_addr + offset; 00463 offset += sizeof(u32); 00464 } 00465 00466 if (offset > adapter->ring_size) { 00467 DBG("atl1e: ring miscalculation! need %d > %d bytes\n", 00468 offset, adapter->ring_size); 00469 err = -EINVAL; 00470 goto failed; 00471 } 00472 00473 return 0; 00474 failed: 00475 atl1e_free_ring_resources(adapter); 00476 return err; 00477 }
| static void atl1e_configure_des_ring | ( | const struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 479 of file atl1e.c.
References AT_PAGE_NUM_PER_QUEUE, AT_WRITE_REG, AT_WRITE_REGB, atl1e_rx_page_lo_addr_regs, atl1e_rx_page_vld_regs, atl1e_rx_page_write_offset_regs, atl1e_tx_ring::cmb_dma, atl1e_tx_ring::count, atl1e_tx_ring::dma, atl1e_adapter::hw, NULL, REG_DESC_BASE_ADDR_HI, REG_HOST_RXFPAGE_SIZE, REG_HOST_TX_CMB_LO, REG_LOAD_PTR, REG_RXF0_BASE_ADDR_HI, REG_TPD_BASE_ADDR_LO, REG_TPD_RING_SIZE, atl1e_adapter::rx_ring, rx_ring, atl1e_adapter::tx_ring, tx_ring, u16, and u32.
Referenced by atl1e_configure().
00480 { 00481 00482 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw; 00483 struct atl1e_rx_ring *rx_ring = 00484 (struct atl1e_rx_ring *)&adapter->rx_ring; 00485 struct atl1e_tx_ring *tx_ring = 00486 (struct atl1e_tx_ring *)&adapter->tx_ring; 00487 struct atl1e_rx_page_desc *rx_page_desc = NULL; 00488 int j; 00489 00490 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 0); 00491 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO, tx_ring->dma); 00492 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count)); 00493 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO, tx_ring->cmb_dma); 00494 00495 rx_page_desc = &rx_ring->rx_page_desc; 00496 00497 /* RXF Page Physical address / Page Length */ 00498 AT_WRITE_REG(hw, REG_RXF0_BASE_ADDR_HI, 0); 00499 00500 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) { 00501 u32 page_phy_addr; 00502 u32 offset_phy_addr; 00503 00504 page_phy_addr = rx_page_desc->rx_page[j].dma; 00505 offset_phy_addr = rx_page_desc->rx_page[j].write_offset_dma; 00506 00507 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[j], page_phy_addr); 00508 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[j], 00509 offset_phy_addr); 00510 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[j], 1); 00511 } 00512 00513 /* Page Length */ 00514 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size); 00515 /* Load all of base address above */ 00516 AT_WRITE_REG(hw, REG_LOAD_PTR, 1); 00517 00518 return; 00519 }
| static void atl1e_configure_tx | ( | struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 521 of file atl1e.c.
References AT_READ_REG, AT_WRITE_REG, AT_WRITE_REGW, athr_l2e_revB, atl1e_pay_load_size, DEVICE_CTRL_MAX_PAYLOAD_MASK, DEVICE_CTRL_MAX_PAYLOAD_SHIFT, DEVICE_CTRL_MAX_RREQ_SZ_MASK, DEVICE_CTRL_MAX_RREQ_SZ_SHIFT, atl1e_hw::dmar_block, atl1e_hw::dmaw_block, ETH_FCS_LEN, ETH_HLEN, atl1e_adapter::hw, MAX_FRAME_SIZE, atl1e_hw::nic_type, REG_DEVICE_CTRL, REG_TX_EARLY_TH, REG_TXQ_CTRL, TPD_BURST, TXQ_CTRL_EN, TXQ_CTRL_ENH_MODE, TXQ_CTRL_NUM_TPD_BURST_MASK, TXQ_CTRL_NUM_TPD_BURST_SHIFT, u32, and VLAN_HLEN.
Referenced by atl1e_configure().
00522 { 00523 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw; 00524 u32 dev_ctrl_data = 0; 00525 u32 max_pay_load = 0; 00526 u32 jumbo_thresh = 0; 00527 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */ 00528 00529 /* configure TXQ param */ 00530 if (hw->nic_type != athr_l2e_revB) { 00531 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN; 00532 jumbo_thresh = MAX_FRAME_SIZE + extra_size; 00533 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3); 00534 } 00535 00536 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL); 00537 00538 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) & 00539 DEVICE_CTRL_MAX_PAYLOAD_MASK; 00540 if (max_pay_load < hw->dmaw_block) 00541 hw->dmaw_block = max_pay_load; 00542 00543 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) & 00544 DEVICE_CTRL_MAX_RREQ_SZ_MASK; 00545 if (max_pay_load < hw->dmar_block) 00546 hw->dmar_block = max_pay_load; 00547 00548 if (hw->nic_type != athr_l2e_revB) 00549 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2, 00550 atl1e_pay_load_size[hw->dmar_block]); 00551 /* enable TXQ */ 00552 AT_WRITE_REGW(hw, REG_TXQ_CTRL, 00553 ((TPD_BURST & TXQ_CTRL_NUM_TPD_BURST_MASK) 00554 << TXQ_CTRL_NUM_TPD_BURST_SHIFT) 00555 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN); 00556 return; 00557 }
| static void atl1e_configure_rx | ( | struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 559 of file atl1e.c.
References AT_READ_REG, AT_WRITE_REG, AT_WRITE_REGW, athr_l2e_revB, atl1e_adapter::hw, atl1e_hw::nic_type, REG_BASE_CPU_NUMBER, REG_IDT_TABLE, REG_RXQ_CTRL, REG_RXQ_JMBOSZ_RRDTIM, REG_RXQ_RXF_PAUSE_THRESH, REG_SRAM_RXF_LEN, RX_JUMBO_THRESH, RXQ_CTRL_CUT_THRU_EN, RXQ_CTRL_EN, RXQ_CTRL_PBA_ALIGN_32, RXQ_JMBO_LKAH_MASK, RXQ_JMBO_LKAH_SHIFT, RXQ_JMBOSZ_TH_MASK, RXQ_JMBOSZ_TH_SHIFT, RXQ_RXF_PAUSE_TH_HI_MASK, RXQ_RXF_PAUSE_TH_HI_SHIFT, RXQ_RXF_PAUSE_TH_LO_MASK, RXQ_RXF_PAUSE_TH_LO_SHIFT, u16, and u32.
Referenced by atl1e_configure().
00560 { 00561 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw; 00562 u32 rxf_len = 0; 00563 u32 rxf_low = 0; 00564 u32 rxf_high = 0; 00565 u32 rxf_thresh_data = 0; 00566 u32 rxq_ctrl_data = 0; 00567 00568 if (hw->nic_type != athr_l2e_revB) { 00569 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM, 00570 (u16)((RX_JUMBO_THRESH & RXQ_JMBOSZ_TH_MASK) << 00571 RXQ_JMBOSZ_TH_SHIFT | 00572 (1 & RXQ_JMBO_LKAH_MASK) << 00573 RXQ_JMBO_LKAH_SHIFT)); 00574 00575 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN); 00576 rxf_high = rxf_len * 4 / 5; 00577 rxf_low = rxf_len / 5; 00578 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK) 00579 << RXQ_RXF_PAUSE_TH_HI_SHIFT) | 00580 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK) 00581 << RXQ_RXF_PAUSE_TH_LO_SHIFT); 00582 00583 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data); 00584 } 00585 00586 /* RRS */ 00587 AT_WRITE_REG(hw, REG_IDT_TABLE, 0); 00588 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, 0); 00589 00590 rxq_ctrl_data |= RXQ_CTRL_PBA_ALIGN_32 | 00591 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN; 00592 00593 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data); 00594 return; 00595 }
| static void atl1e_configure_dma | ( | struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 597 of file atl1e.c.
References AT_WRITE_REG, DMA_CTRL_DMAR_BURST_LEN_MASK, DMA_CTRL_DMAR_BURST_LEN_SHIFT, DMA_CTRL_DMAR_DLY_CNT_MASK, DMA_CTRL_DMAR_DLY_CNT_SHIFT, DMA_CTRL_DMAR_OUT_ORDER, DMA_CTRL_DMAR_REQ_PRI, DMA_CTRL_DMAW_BURST_LEN_MASK, DMA_CTRL_DMAW_BURST_LEN_SHIFT, DMA_CTRL_DMAW_DLY_CNT_MASK, DMA_CTRL_DMAW_DLY_CNT_SHIFT, DMA_CTRL_RXCMB_EN, atl1e_hw::dmar_block, DMAR_DLY_CNT, atl1e_hw::dmaw_block, DMAW_DLY_CNT, atl1e_adapter::hw, REG_DMA_CTRL, and u32.
Referenced by atl1e_configure().
00598 { 00599 struct atl1e_hw *hw = &adapter->hw; 00600 u32 dma_ctrl_data = 0; 00601 00602 dma_ctrl_data = DMA_CTRL_RXCMB_EN; 00603 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) 00604 << DMA_CTRL_DMAR_BURST_LEN_SHIFT; 00605 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK) 00606 << DMA_CTRL_DMAW_BURST_LEN_SHIFT; 00607 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER; 00608 dma_ctrl_data |= (DMAR_DLY_CNT & DMA_CTRL_DMAR_DLY_CNT_MASK) 00609 << DMA_CTRL_DMAR_DLY_CNT_SHIFT; 00610 dma_ctrl_data |= (DMAW_DLY_CNT & DMA_CTRL_DMAW_DLY_CNT_MASK) 00611 << DMA_CTRL_DMAW_DLY_CNT_SHIFT; 00612 00613 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data); 00614 return; 00615 }
| static int atl1e_configure | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 649 of file atl1e.c.
References AT_READ_REG, AT_WRITE_REG, AT_WRITE_REG_ARRAY, AT_WRITE_REGW, atl1e_configure_des_ring(), atl1e_configure_dma(), atl1e_configure_rx(), atl1e_configure_tx(), atl1e_hw_set_mac_addr(), DBG, ETH_FCS_LEN, ETH_HLEN, atl1e_adapter::hw, ICT_VAL, IMT_VAL, ISR_PHY_LINKDOWN, MASTER_CTRL_ITIMER2_EN, MASTER_CTRL_ITIMER_EN, MASTER_CTRL_LED_MODE, MAX_FRAME_SIZE, REG_CMBDISDMA_TIMER, REG_IRQ_MODU_TIMER2_INIT, REG_IRQ_MODU_TIMER_INIT, REG_ISR, REG_MASTER_CTRL, REG_MTU, REG_RX_HASH_TABLE, REG_SMB_STAT_TIMER, REG_TRIG_RRD_THRESH, REG_TRIG_RXTIMER, REG_TRIG_TPD_THRESH, REG_TRIG_TXTIMER, REG_WOL_CTRL, RRD_THRESH, RX_COUNT_DOWN, SMB_TIMER, TPD_THRESH, TX_COUNT_DOWN, u32, and VLAN_HLEN.
Referenced by atl1e_up().
00650 { 00651 struct atl1e_hw *hw = &adapter->hw; 00652 u32 intr_status_data = 0; 00653 00654 /* clear interrupt status */ 00655 AT_WRITE_REG(hw, REG_ISR, ~0); 00656 00657 /* 1. set MAC Address */ 00658 atl1e_hw_set_mac_addr(hw); 00659 00660 /* 2. Init the Multicast HASH table (clear) */ 00661 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 00662 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 00663 00664 /* 3. Clear any WOL status */ 00665 AT_WRITE_REG(hw, REG_WOL_CTRL, 0); 00666 00667 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr 00668 * TPD Ring/SMB/RXF0 Page CMBs, they use the same 00669 * High 32bits memory */ 00670 atl1e_configure_des_ring(adapter); 00671 00672 /* 5. set Interrupt Moderator Timer */ 00673 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, IMT_VAL); 00674 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, IMT_VAL); 00675 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE | 00676 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN); 00677 00678 /* 6. rx/tx threshold to trig interrupt */ 00679 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, RRD_THRESH); 00680 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, TPD_THRESH); 00681 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, RX_COUNT_DOWN); 00682 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, TX_COUNT_DOWN); 00683 00684 /* 7. set Interrupt Clear Timer */ 00685 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, ICT_VAL); 00686 00687 /* 8. set MTU */ 00688 AT_WRITE_REG(hw, REG_MTU, MAX_FRAME_SIZE + ETH_HLEN + 00689 VLAN_HLEN + ETH_FCS_LEN); 00690 00691 /* 9. config TXQ early tx threshold */ 00692 atl1e_configure_tx(adapter); 00693 00694 /* 10. config RXQ */ 00695 atl1e_configure_rx(adapter); 00696 00697 /* 11. config DMA Engine */ 00698 atl1e_configure_dma(adapter); 00699 00700 /* 12. smb timer to trig interrupt */ 00701 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, SMB_TIMER); 00702 00703 intr_status_data = AT_READ_REG(hw, REG_ISR); 00704 if ((intr_status_data & ISR_PHY_LINKDOWN) != 0) { 00705 DBG("atl1e: configure failed, PCIE phy link down\n"); 00706 return -1; 00707 } 00708 00709 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff); 00710 return 0; 00711 }
| static void atl1e_clear_phy_int | ( | struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 713 of file atl1e.c.
References atl1e_read_phy_reg(), atl1e_adapter::hw, MII_INT_STATUS, and u16.
Referenced by atl1e_poll().
00714 { 00715 u16 phy_data; 00716 00717 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data); 00718 }
| static int atl1e_clean_tx_irq | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 720 of file atl1e.c.
References AT_READ_REGW, atl1e_tx_ring::count, atl1e_tx_buffer::dma, atl1e_adapter::hw, atl1e_tx_buffer::iob, atl1e_adapter::netdev, netdev_tx_complete(), atl1e_tx_ring::next_to_clean, NULL, REG_TPD_CONS_IDX, atl1e_tx_ring::tx_buffer, atl1e_adapter::tx_ring, tx_ring, and u16.
Referenced by atl1e_poll().
00721 { 00722 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *) 00723 &adapter->tx_ring; 00724 struct atl1e_tx_buffer *tx_buffer = NULL; 00725 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX); 00726 u16 next_to_clean = tx_ring->next_to_clean; 00727 00728 while (next_to_clean != hw_next_to_clean) { 00729 tx_buffer = &tx_ring->tx_buffer[next_to_clean]; 00730 00731 tx_buffer->dma = 0; 00732 if (tx_buffer->iob) { 00733 netdev_tx_complete(adapter->netdev, tx_buffer->iob); 00734 tx_buffer->iob = NULL; 00735 } 00736 00737 if (++next_to_clean == tx_ring->count) 00738 next_to_clean = 0; 00739 } 00740 00741 tx_ring->next_to_clean = next_to_clean; 00742 00743 return 1; 00744 }
| static struct atl1e_rx_page* atl1e_get_rx_page | ( | struct atl1e_adapter * | adapter | ) | [static, read] |
Definition at line 746 of file atl1e.c.
References atl1e_rx_page_desc::rx_page, atl1e_rx_ring::rx_page_desc, atl1e_adapter::rx_ring, atl1e_rx_page_desc::rx_using, and u8.
Referenced by atl1e_clean_rx_irq().
00747 { 00748 struct atl1e_rx_page_desc *rx_page_desc = 00749 (struct atl1e_rx_page_desc *) &adapter->rx_ring.rx_page_desc; 00750 u8 rx_using = rx_page_desc->rx_using; 00751 00752 return (struct atl1e_rx_page *)&(rx_page_desc->rx_page[rx_using]); 00753 }
| static void atl1e_clean_rx_irq | ( | struct atl1e_adapter * | adapter | ) | [static] |
Definition at line 755 of file atl1e.c.
References atl1e_rx_page::addr, alloc_iob(), AT_WRITE_REGB, atl1e_get_rx_page(), atl1e_reset(), atl1e_rx_page_vld_regs, io_buffer::data, DBG, EIO, atl1e_recv_ret_status::err_flag, ETH_FCS_LEN, atl1e_adapter::hw, iob_put, iob_reserve, memcpy, net_device::name, NET_IP_ALIGN, atl1e_adapter::netdev, netdev, netdev_link_ok(), netdev_rx(), netdev_rx_err(), NULL, atl1e_rx_ring::page_size, atl1e_recv_ret_status::pkt_flag, atl1e_rx_page::read_offset, RRS_ERR_BAD_CRC, RRS_ERR_CODE, RRS_ERR_DRIBBLE, RRS_ERR_TRUNC, RRS_IS_ERR_FRAME, RRS_PKT_SIZE_MASK, RRS_PKT_SIZE_SHIFT, atl1e_rx_ring::rx_page_desc, atl1e_adapter::rx_ring, rx_ring, atl1e_recv_ret_status::seq_num, u16, u32, u8, atl1e_recv_ret_status::word1, and atl1e_rx_page::write_offset_addr.
Referenced by atl1e_poll().
00756 { 00757 struct net_device *netdev = adapter->netdev; 00758 struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *) 00759 &adapter->rx_ring; 00760 struct atl1e_rx_page_desc *rx_page_desc = 00761 (struct atl1e_rx_page_desc *) &rx_ring->rx_page_desc; 00762 struct io_buffer *iob = NULL; 00763 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter); 00764 u32 packet_size, write_offset; 00765 struct atl1e_recv_ret_status *prrs; 00766 00767 write_offset = *(rx_page->write_offset_addr); 00768 if (rx_page->read_offset >= write_offset) 00769 return; 00770 00771 do { 00772 /* get new packet's rrs */ 00773 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr + 00774 rx_page->read_offset); 00775 /* check sequence number */ 00776 if (prrs->seq_num != rx_page_desc->rx_nxseq) { 00777 DBG("atl1e %s: RX sequence number error (%d != %d)\n", 00778 netdev->name, prrs->seq_num, 00779 rx_page_desc->rx_nxseq); 00780 rx_page_desc->rx_nxseq++; 00781 goto fatal_err; 00782 } 00783 00784 rx_page_desc->rx_nxseq++; 00785 00786 /* error packet */ 00787 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) { 00788 if (prrs->err_flag & (RRS_ERR_BAD_CRC | 00789 RRS_ERR_DRIBBLE | RRS_ERR_CODE | 00790 RRS_ERR_TRUNC)) { 00791 /* hardware error, discard this 00792 packet */ 00793 netdev_rx_err(netdev, NULL, EIO); 00794 goto skip_pkt; 00795 } 00796 } 00797 00798 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) & 00799 RRS_PKT_SIZE_MASK) - ETH_FCS_LEN; 00800 iob = alloc_iob(packet_size + NET_IP_ALIGN); 00801 if (iob == NULL) { 00802 DBG("atl1e %s: dropping packet under memory pressure\n", 00803 netdev->name); 00804 goto skip_pkt; 00805 } 00806 iob_reserve(iob, NET_IP_ALIGN); 00807 memcpy(iob->data, (u8 *)(prrs + 1), packet_size); 00808 iob_put(iob, packet_size); 00809 00810 netdev_rx(netdev, iob); 00811 00812 skip_pkt: 00813 /* skip current packet whether it's ok or not. */ 00814 rx_page->read_offset += 00815 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) & 00816 RRS_PKT_SIZE_MASK) + 00817 sizeof(struct atl1e_recv_ret_status) + 31) & 00818 0xFFFFFFE0); 00819 00820 if (rx_page->read_offset >= rx_ring->page_size) { 00821 /* mark this page clean */ 00822 u16 reg_addr; 00823 u8 rx_using; 00824 00825 rx_page->read_offset = 00826 *(rx_page->write_offset_addr) = 0; 00827 rx_using = rx_page_desc->rx_using; 00828 reg_addr = 00829 atl1e_rx_page_vld_regs[rx_using]; 00830 AT_WRITE_REGB(&adapter->hw, reg_addr, 1); 00831 rx_page_desc->rx_using ^= 1; 00832 rx_page = atl1e_get_rx_page(adapter); 00833 } 00834 write_offset = *(rx_page->write_offset_addr); 00835 } while (rx_page->read_offset < write_offset); 00836 00837 return; 00838 00839 fatal_err: 00840 if (!netdev_link_ok(adapter->netdev)) 00841 atl1e_reset(adapter); 00842 }
| static void atl1e_poll | ( | struct net_device * | netdev | ) | [static] |
Definition at line 848 of file atl1e.c.
References AT_READ_REG, AT_WRITE_REG, atl1e_check_link(), atl1e_clean_rx_irq(), atl1e_clean_tx_irq(), atl1e_clear_phy_int(), atl1e_irq_reset(), atl1e_reset(), DBG, atl1e_adapter::hw, IMR_NORMAL_MASK, ISR_DIS_INT, ISR_DMAR_TO_RST, ISR_DMAW_TO_RST, ISR_GPHY, ISR_MANUAL, ISR_PHY_LINKDOWN, ISR_RX_EVENT, ISR_TX_EVENT, atl1e_adapter::netdev, netdev_link_ok(), netdev_priv(), REG_ISR, and u32.
00849 { 00850 struct atl1e_adapter *adapter = netdev_priv(netdev); 00851 struct atl1e_hw *hw = &adapter->hw; 00852 int max_ints = 64; 00853 u32 status; 00854 00855 do { 00856 status = AT_READ_REG(hw, REG_ISR); 00857 if ((status & IMR_NORMAL_MASK) == 0) 00858 break; 00859 00860 /* link event */ 00861 if (status & ISR_GPHY) 00862 atl1e_clear_phy_int(adapter); 00863 /* Ack ISR */ 00864 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); 00865 00866 /* check if PCIE PHY Link down */ 00867 if (status & ISR_PHY_LINKDOWN) { 00868 DBG("atl1e: PCI-E PHY link down: %x\n", status); 00869 if (netdev_link_ok(adapter->netdev)) { 00870 /* reset MAC */ 00871 atl1e_irq_reset(adapter); 00872 atl1e_reset(adapter); 00873 break; 00874 } 00875 } 00876 00877 /* check if DMA read/write error */ 00878 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { 00879 DBG("atl1e: PCI-E DMA RW error: %x\n", status); 00880 atl1e_irq_reset(adapter); 00881 atl1e_reset(adapter); 00882 break; 00883 } 00884 00885 /* link event */ 00886 if (status & (ISR_GPHY | ISR_MANUAL)) { 00887 atl1e_check_link(adapter); 00888 break; 00889 } 00890 00891 /* transmit event */ 00892 if (status & ISR_TX_EVENT) 00893 atl1e_clean_tx_irq(adapter); 00894 00895 if (status & ISR_RX_EVENT) 00896 atl1e_clean_rx_irq(adapter); 00897 } while (--max_ints > 0); 00898 00899 /* re-enable Interrupt*/ 00900 AT_WRITE_REG(&adapter->hw, REG_ISR, 0); 00901 00902 return; 00903 }
| static u16 atl1e_tpd_avail | ( | struct atl1e_adapter * | adapter | ) | [inline, static] |
Definition at line 905 of file atl1e.c.
References atl1e_tx_ring::count, atl1e_tx_ring::next_to_clean, atl1e_tx_ring::next_to_use, atl1e_adapter::tx_ring, tx_ring, and u16.
Referenced by atl1e_xmit_frame().
00906 { 00907 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring; 00908 u16 next_to_use = 0; 00909 u16 next_to_clean = 0; 00910 00911 next_to_clean = tx_ring->next_to_clean; 00912 next_to_use = tx_ring->next_to_use; 00913 00914 return (u16)(next_to_clean > next_to_use) ? 00915 (next_to_clean - next_to_use - 1) : 00916 (tx_ring->count + next_to_clean - next_to_use - 1); 00917 }
| static struct atl1e_tpd_desc* atl1e_get_tpd | ( | struct atl1e_adapter * | adapter | ) | [static, read] |
Definition at line 924 of file atl1e.c.
References atl1e_tx_ring::count, atl1e_tx_ring::desc, memset(), atl1e_tx_ring::next_to_use, atl1e_adapter::tx_ring, tx_ring, and u16.
Referenced by atl1e_xmit_frame().
00925 { 00926 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring; 00927 u16 next_to_use = 0; 00928 00929 next_to_use = tx_ring->next_to_use; 00930 if (++tx_ring->next_to_use == tx_ring->count) 00931 tx_ring->next_to_use = 0; 00932 00933 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc)); 00934 return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use]; 00935 }
| static struct atl1e_tx_buffer* atl1e_get_tx_buffer | ( | struct atl1e_adapter * | adapter, | |
| struct atl1e_tpd_desc * | tpd | |||
| ) | [static, read] |
Definition at line 938 of file atl1e.c.
References atl1e_tx_ring::desc, atl1e_tx_ring::tx_buffer, atl1e_adapter::tx_ring, and tx_ring.
Referenced by atl1e_tx_map().
00939 { 00940 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring; 00941 00942 return &tx_ring->tx_buffer[tpd - tx_ring->desc]; 00943 }
| static void atl1e_tx_map | ( | struct atl1e_adapter * | adapter, | |
| struct io_buffer * | iob, | |||
| struct atl1e_tpd_desc * | tpd | |||
| ) | [static] |
Definition at line 945 of file atl1e.c.
References atl1e_get_tx_buffer(), atl1e_tpd_desc::buffer_addr, cpu_to_le32, cpu_to_le64, io_buffer::data, atl1e_tx_buffer::dma, atl1e_tx_buffer::iob, iob_len(), atl1e_tx_buffer::length, NULL, TPD_BUFLEN_MASK, TPD_BUFLEN_SHIFT, TPD_EOP_SHIFT, u16, virt_to_bus(), atl1e_tpd_desc::word2, and atl1e_tpd_desc::word3.
Referenced by atl1e_xmit_frame().
00947 { 00948 struct atl1e_tx_buffer *tx_buffer = NULL; 00949 u16 buf_len = iob_len(iob); 00950 00951 tx_buffer = atl1e_get_tx_buffer(adapter, tpd); 00952 tx_buffer->iob = iob; 00953 tx_buffer->length = buf_len; 00954 tx_buffer->dma = virt_to_bus(iob->data); 00955 tpd->buffer_addr = cpu_to_le64(tx_buffer->dma); 00956 tpd->word2 = ((tpd->word2 & ~TPD_BUFLEN_MASK) | 00957 ((cpu_to_le32(buf_len) & TPD_BUFLEN_MASK) << 00958 TPD_BUFLEN_SHIFT)); 00959 tpd->word3 |= 1 << TPD_EOP_SHIFT; 00960 }
| static void atl1e_tx_queue | ( | struct atl1e_adapter * | adapter, | |
| u16 count | __unused, | |||
| struct atl1e_tpd_desc *tpd | __unused | |||
| ) | [static] |
Definition at line 962 of file atl1e.c.
References AT_WRITE_REG, atl1e_adapter::hw, atl1e_tx_ring::next_to_use, REG_MB_TPD_PROD_IDX, atl1e_adapter::tx_ring, tx_ring, and wmb.
Referenced by atl1e_xmit_frame().
00964 { 00965 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring; 00966 wmb(); 00967 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use); 00968 }
| static int atl1e_xmit_frame | ( | struct net_device * | netdev, | |
| struct io_buffer * | iob | |||
| ) | [static] |
Definition at line 970 of file atl1e.c.
References atl1e_get_tpd(), atl1e_tpd_avail(), atl1e_tx_map(), atl1e_tx_queue(), EBUSY, EINVAL, netdev_link_ok(), netdev_priv(), and u16.
00971 { 00972 struct atl1e_adapter *adapter = netdev_priv(netdev); 00973 u16 tpd_req = 1; 00974 struct atl1e_tpd_desc *tpd; 00975 00976 if (!netdev_link_ok(netdev)) { 00977 return -EINVAL; 00978 } 00979 00980 if (atl1e_tpd_avail(adapter) < tpd_req) { 00981 return -EBUSY; 00982 } 00983 00984 tpd = atl1e_get_tpd(adapter); 00985 00986 atl1e_tx_map(adapter, iob, tpd); 00987 atl1e_tx_queue(adapter, tpd_req, tpd); 00988 00989 return 0; 00990 }
| int atl1e_up | ( | struct atl1e_adapter * | adapter | ) |
Definition at line 992 of file atl1e.c.
References AT_READ_REG, AT_WRITE_REG, atl1e_configure(), atl1e_init_hw(), atl1e_init_ring_ptrs(), atl1e_irq_disable(), EIO, ETH_ALEN, atl1e_adapter::hw, net_device::ll_addr, atl1e_hw::mac_addr, MASTER_CTRL_MANUAL_INT, memcpy, atl1e_adapter::netdev, netdev, REG_MASTER_CTRL, and u32.
Referenced by atl1e_open(), and atl1e_reset().
00993 { 00994 struct net_device *netdev = adapter->netdev; 00995 int err = 0; 00996 u32 val; 00997 00998 /* hardware has been reset, we need to reload some things */ 00999 err = atl1e_init_hw(&adapter->hw); 01000 if (err) { 01001 return -EIO; 01002 } 01003 atl1e_init_ring_ptrs(adapter); 01004 01005 memcpy(adapter->hw.mac_addr, netdev->ll_addr, ETH_ALEN); 01006 01007 if (atl1e_configure(adapter) != 0) { 01008 return -EIO; 01009 } 01010 01011 atl1e_irq_disable(adapter); 01012 01013 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL); 01014 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, 01015 val | MASTER_CTRL_MANUAL_INT); 01016 01017 return err; 01018 }
| void atl1e_irq | ( | struct net_device * | netdev, | |
| int | enable | |||
| ) |
Definition at line 1020 of file atl1e.c.
References atl1e_irq_disable(), atl1e_irq_enable(), and netdev_priv().
01021 { 01022 struct atl1e_adapter *adapter = netdev_priv(netdev); 01023 01024 if (enable) 01025 atl1e_irq_enable(adapter); 01026 else 01027 atl1e_irq_disable(adapter); 01028 }
| void atl1e_down | ( | struct atl1e_adapter * | adapter | ) |
Definition at line 1030 of file atl1e.c.
References atl1e_clean_rx_ring(), atl1e_clean_tx_ring(), atl1e_reset_hw(), atl1e_adapter::hw, atl1e_adapter::link_duplex, atl1e_adapter::link_speed, mdelay(), atl1e_adapter::netdev, netdev, netdev_link_down(), and SPEED_0.
Referenced by atl1e_close(), and atl1e_reset().
01031 { 01032 struct net_device *netdev = adapter->netdev; 01033 01034 /* reset MAC to disable all RX/TX */ 01035 atl1e_reset_hw(&adapter->hw); 01036 mdelay(1); 01037 01038 netdev_link_down(netdev); 01039 adapter->link_speed = SPEED_0; 01040 adapter->link_duplex = -1; 01041 01042 atl1e_clean_tx_ring(adapter); 01043 atl1e_clean_rx_ring(adapter); 01044 }
| static int atl1e_open | ( | struct net_device * | netdev | ) | [static] |
Definition at line 1058 of file atl1e.c.
References atl1e_free_ring_resources(), atl1e_init_ring_resources(), atl1e_reset_hw(), atl1e_setup_ring_resources(), atl1e_up(), atl1e_adapter::hw, and netdev_priv().
01059 { 01060 struct atl1e_adapter *adapter = netdev_priv(netdev); 01061 int err; 01062 01063 /* allocate rx/tx dma buffer & descriptors */ 01064 atl1e_init_ring_resources(adapter); 01065 err = atl1e_setup_ring_resources(adapter); 01066 if (err) 01067 return err; 01068 01069 err = atl1e_up(adapter); 01070 if (err) 01071 goto err_up; 01072 01073 return 0; 01074 01075 err_up: 01076 atl1e_free_ring_resources(adapter); 01077 atl1e_reset_hw(&adapter->hw); 01078 01079 return err; 01080 }
| static void atl1e_close | ( | struct net_device * | netdev | ) | [static] |
Definition at line 1093 of file atl1e.c.
References atl1e_down(), atl1e_free_ring_resources(), and netdev_priv().
01094 { 01095 struct atl1e_adapter *adapter = netdev_priv(netdev); 01096 01097 atl1e_down(adapter); 01098 atl1e_free_ring_resources(adapter); 01099 }
| static void atl1e_init_netdev | ( | struct net_device * | netdev, | |
| struct pci_device * | pdev | |||
| ) | [static] |
Definition at line 1109 of file atl1e.c.
References pci_device::dev, net_device::dev, netdev_init(), and pci_set_drvdata().
Referenced by atl1e_probe().
01110 { 01111 netdev_init(netdev, &atl1e_netdev_ops); 01112 01113 netdev->dev = &pdev->dev; 01114 pci_set_drvdata(pdev, netdev); 01115 }
| static int atl1e_probe | ( | struct pci_device * | pdev, | |
| const struct pci_device_id *ent | __unused | |||
| ) | [static] |
Definition at line 1128 of file atl1e.c.
References atl1e_hw::adapter, adjust_pci_device(), alloc_etherdev(), atl1e_init_netdev(), atl1e_mdio_read(), atl1e_mdio_write(), atl1e_phy_init(), atl1e_read_mac_addr(), atl1e_reset_hw(), atl1e_restart_autoneg(), atl1e_setup_pcicmd(), atl1e_sw_init(), atl1e_adapter::bd_number, bus_to_virt(), cards_found, atl1e_tx_ring::count, DBG, mii_if_info::dev, EIO, ENOMEM, ETH_ALEN, atl1e_adapter::hw, net_device::hw_addr, atl1e_hw::hw_addr, net_device::ll_addr, atl1e_hw::mac_addr, mii_if_info::mdio_read, MDIO_REG_ADDR_MASK, mii_if_info::mdio_write, pci_device::membase, memcpy, atl1e_adapter::mii, net_device::name, atl1e_adapter::netdev, netdev, netdev_link_down(), netdev_nullify(), netdev_priv(), netdev_put(), NULL, atl1e_rx_ring::page_size, atl1e_adapter::pdev, atl1e_hw::perm_mac_addr, mii_if_info::phy_id_mask, mii_if_info::reg_num_mask, register_netdev(), RX_MEM_SIZE, atl1e_adapter::rx_ring, TX_DESC_COUNT, and atl1e_adapter::tx_ring.
01130 { 01131 struct net_device *netdev; 01132 struct atl1e_adapter *adapter = NULL; 01133 static int cards_found; 01134 01135 int err = 0; 01136 01137 adjust_pci_device(pdev); 01138 01139 netdev = alloc_etherdev(sizeof(struct atl1e_adapter)); 01140 if (netdev == NULL) { 01141 err = -ENOMEM; 01142 DBG("atl1e: out of memory allocating net_device\n"); 01143 goto err; 01144 } 01145 01146 atl1e_init_netdev(netdev, pdev); 01147 01148 adapter = netdev_priv(netdev); 01149 adapter->bd_number = cards_found; 01150 adapter->netdev = netdev; 01151 adapter->pdev = pdev; 01152 adapter->hw.adapter = adapter; 01153 if (!pdev->membase) { 01154 err = -EIO; 01155 DBG("atl1e: cannot map device registers\n"); 01156 goto err_free_netdev; 01157 } 01158 adapter->hw.hw_addr = bus_to_virt(pdev->membase); 01159 01160 /* init mii data */ 01161 adapter->mii.dev = netdev; 01162 adapter->mii.mdio_read = atl1e_mdio_read; 01163 adapter->mii.mdio_write = atl1e_mdio_write; 01164 adapter->mii.phy_id_mask = 0x1f; 01165 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK; 01166 01167 /* get user settings */ 01168 adapter->tx_ring.count = TX_DESC_COUNT; 01169 adapter->rx_ring.page_size = RX_MEM_SIZE; 01170 01171 atl1e_setup_pcicmd(pdev); 01172 01173 /* setup the private structure */ 01174 err = atl1e_sw_init(adapter); 01175 if (err) { 01176 DBG("atl1e: private data init failed\n"); 01177 goto err_free_netdev; 01178 } 01179 01180 /* Init GPHY as early as possible due to power saving issue */ 01181 atl1e_phy_init(&adapter->hw); 01182 01183 /* reset the controller to 01184 * put the device in a known good starting state */ 01185 err = atl1e_reset_hw(&adapter->hw); 01186 if (err) { 01187 err = -EIO; 01188 goto err_free_netdev; 01189 } 01190 01191 /* This may have been run by a zero-wait timer around 01192 now... unclear. */ 01193 atl1e_restart_autoneg(&adapter->hw); 01194 01195 if (atl1e_read_mac_addr(&adapter->hw) != 0) { 01196 DBG("atl1e: cannot read MAC address from EEPROM\n"); 01197 err = -EIO; 01198 goto err_free_netdev; 01199 } 01200 01201 memcpy(netdev->hw_addr, adapter->hw.perm_mac_addr, ETH_ALEN); 01202 memcpy(netdev->ll_addr, adapter->hw.mac_addr, ETH_ALEN); 01203 DBG("atl1e: Attansic L1E Ethernet controller on %s, " 01204 "%02x:%02x:%02x:%02x:%02x:%02x\n", adapter->netdev->name, 01205 adapter->hw.mac_addr[0], adapter->hw.mac_addr[1], 01206 adapter->hw.mac_addr[2], adapter->hw.mac_addr[3], 01207 adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]); 01208 01209 err = register_netdev(netdev); 01210 if (err) { 01211 DBG("atl1e: cannot register network device\n"); 01212 goto err_free_netdev; 01213 } 01214 01215 netdev_link_down(netdev); 01216 01217 cards_found++; 01218 return 0; 01219 01220 err_free_netdev: 01221 netdev_nullify(netdev); 01222 netdev_put(netdev); 01223 err: 01224 return err; 01225 }
| static void atl1e_remove | ( | struct pci_device * | pdev | ) | [static] |
Definition at line 1236 of file atl1e.c.
References atl1e_force_ps(), atl1e_free_ring_resources(), atl1e_adapter::hw, netdev, netdev_nullify(), netdev_priv(), netdev_put(), pci_get_drvdata(), and unregister_netdev().
01237 { 01238 struct net_device *netdev = pci_get_drvdata(pdev); 01239 struct atl1e_adapter *adapter = netdev_priv(netdev); 01240 01241 unregister_netdev(netdev); 01242 atl1e_free_ring_resources(adapter); 01243 atl1e_force_ps(&adapter->hw); 01244 netdev_nullify(netdev); 01245 netdev_put(netdev); 01246 }
| int atl1e_check_eeprom_exist | ( | struct atl1e_hw * | hw | ) |
Definition at line 1261 of file atl1e.c.
References AT_READ_REG, AT_READ_REGW, AT_WRITE_REG, REG_PCIE_CAP_LIST, REG_SPI_FLASH_CTRL, SPI_FLASH_CTRL_EN_VPD, and u32.
Referenced by atl1e_get_permanent_address().
01262 { 01263 u32 value; 01264 01265 value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL); 01266 if (value & SPI_FLASH_CTRL_EN_VPD) { 01267 value &= ~SPI_FLASH_CTRL_EN_VPD; 01268 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); 01269 } 01270 value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST); 01271 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; 01272 }
| void atl1e_hw_set_mac_addr | ( | struct atl1e_hw * | hw | ) |
Definition at line 1274 of file atl1e.c.
References AT_WRITE_REG_ARRAY, atl1e_hw::mac_addr, REG_MAC_STA_ADDR, and u32.
Referenced by atl1e_configure().
01275 { 01276 u32 value; 01277 /* 01278 * 00-0B-6A-F6-00-DC 01279 * 0: 6AF600DC 1: 000B 01280 * low dword 01281 */ 01282 value = (((u32)hw->mac_addr[2]) << 24) | 01283 (((u32)hw->mac_addr[3]) << 16) | 01284 (((u32)hw->mac_addr[4]) << 8) | 01285 (((u32)hw->mac_addr[5])) ; 01286 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); 01287 /* hight dword */ 01288 value = (((u32)hw->mac_addr[0]) << 8) | 01289 (((u32)hw->mac_addr[1])) ; 01290 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); 01291 }
| static int atl1e_get_permanent_address | ( | struct atl1e_hw * | hw | ) | [static] |
Definition at line 1297 of file atl1e.c.
References AT_ERR_TIMEOUT, AT_READ_REG, AT_TWSI_EEPROM_TIMEOUT, AT_WRITE_REG, atl1e_check_eeprom_exist(), ETH_ALEN, mdelay(), memcpy, atl1e_hw::perm_mac_addr, REG_MAC_STA_ADDR, REG_TWSI_CTRL, TWSI_CTRL_SW_LDSTART, u32, and u8.
Referenced by atl1e_read_mac_addr().
01298 { 01299 union { 01300 u32 dword[2]; 01301 u8 byte[8]; 01302 } hw_addr; 01303 u32 i; 01304 u32 twsi_ctrl_data; 01305 u8 eth_addr[ETH_ALEN]; 01306 01307 if (!atl1e_check_eeprom_exist(hw)) { 01308 /* eeprom exist */ 01309 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); 01310 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART; 01311 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data); 01312 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) { 01313 mdelay(10); 01314 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL); 01315 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0) 01316 break; 01317 } 01318 if (i >= AT_TWSI_EEPROM_TIMEOUT) 01319 return AT_ERR_TIMEOUT; 01320 } 01321 01322 /* maybe MAC-address is from BIOS */ 01323 hw_addr.dword[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR); 01324 hw_addr.dword[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4); 01325 for (i = 0; i < ETH_ALEN; i++) { 01326 eth_addr[ETH_ALEN - i - 1] = hw_addr.byte[i]; 01327 } 01328 01329 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN); 01330 return 0; 01331 }
| void atl1e_force_ps | ( | struct atl1e_hw * | hw | ) |
Definition at line 1333 of file atl1e.c.
References AT_WRITE_REGW, GPHY_CTRL_EXT_RESET, GPHY_CTRL_PW_WOL_DIS, and REG_GPHY_CTRL.
Referenced by atl1e_remove().
01334 { 01335 AT_WRITE_REGW(hw, REG_GPHY_CTRL, 01336 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET); 01337 }
| int atl1e_read_mac_addr | ( | struct atl1e_hw * | hw | ) |
Definition at line 1344 of file atl1e.c.
References AT_ERR_EEPROM, atl1e_get_permanent_address(), atl1e_hw::mac_addr, memcpy, and atl1e_hw::perm_mac_addr.
Referenced by atl1e_probe().
01345 { 01346 int err = 0; 01347 01348 err = atl1e_get_permanent_address(hw); 01349 if (err) 01350 return AT_ERR_EEPROM; 01351 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr)); 01352 return 0; 01353 }
Definition at line 1360 of file atl1e.c.
References AT_ERR_PHY, AT_READ_REG, AT_WRITE_REG, MDIO_BUSY, MDIO_CLK_25_4, MDIO_CLK_SEL_SHIFT, MDIO_REG_ADDR_MASK, MDIO_REG_ADDR_SHIFT, MDIO_RW, MDIO_START, MDIO_SUP_PREAMBLE, MDIO_WAIT_TIMES, REG_MDIO_CTRL, u16, u32, udelay(), and wmb.
Referenced by atl1e_check_link(), atl1e_clear_phy_int(), atl1e_get_speed_and_duplex(), and atl1e_mdio_read().
01361 { 01362 u32 val; 01363 int i; 01364 01365 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | 01366 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | 01367 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 01368 01369 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); 01370 01371 wmb(); 01372 01373 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 01374 udelay(2); 01375 val = AT_READ_REG(hw, REG_MDIO_CTRL); 01376 if (!(val & (MDIO_START | MDIO_BUSY))) 01377 break; 01378 wmb(); 01379 } 01380 if (!(val & (MDIO_START | MDIO_BUSY))) { 01381 *phy_data = (u16)val; 01382 return 0; 01383 } 01384 01385 return AT_ERR_PHY; 01386 }
Definition at line 1394 of file atl1e.c.
References AT_ERR_PHY, AT_READ_REG, AT_WRITE_REG, MDIO_BUSY, MDIO_CLK_25_4, MDIO_CLK_SEL_SHIFT, MDIO_DATA_MASK, MDIO_DATA_SHIFT, MDIO_REG_ADDR_MASK, MDIO_REG_ADDR_SHIFT, MDIO_START, MDIO_SUP_PREAMBLE, MDIO_WAIT_TIMES, REG_MDIO_CTRL, u32, udelay(), and wmb.
Referenced by atl1e_mdio_write(), atl1e_phy_commit(), atl1e_phy_init(), atl1e_phy_setup_autoneg_adv(), and atl1e_restart_autoneg().
01395 { 01396 int i; 01397 u32 val; 01398 01399 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | 01400 (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | 01401 MDIO_SUP_PREAMBLE | 01402 MDIO_START | 01403 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; 01404 01405 AT_WRITE_REG(hw, REG_MDIO_CTRL, val); 01406 wmb(); 01407 01408 for (i = 0; i < MDIO_WAIT_TIMES; i++) { 01409 udelay(2); 01410 val = AT_READ_REG(hw, REG_MDIO_CTRL); 01411 if (!(val & (MDIO_START | MDIO_BUSY))) 01412 break; 01413 wmb(); 01414 } 01415 01416 if (!(val & (MDIO_START | MDIO_BUSY))) 01417 return 0; 01418 01419 return AT_ERR_PHY; 01420 }
| static void atl1e_init_pcie | ( | struct atl1e_hw * | hw | ) | [static] |
Definition at line 1425 of file atl1e.c.
References AT_READ_REG, AT_WRITE_REG, and u32.
Referenced by atl1e_init_hw().
01426 { 01427 u32 value; 01428 /* comment 2lines below to save more power when sususpend 01429 value = LTSSM_TEST_MODE_DEF; 01430 AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); 01431 */ 01432 01433 /* pcie flow control mode change */ 01434 value = AT_READ_REG(hw, 0x1008); 01435 value |= 0x8000; 01436 AT_WRITE_REG(hw, 0x1008, value); 01437 }
| static int atl1e_phy_setup_autoneg_adv | ( | struct atl1e_hw * | hw | ) | [static] |
Definition at line 1443 of file atl1e.c.
References athr_l1e, athr_l2e_revA, atl1e_write_phy_reg(), atl1e_hw::mii_1000t_ctrl_reg, MII_ADVERTISE, MII_AR_100TX_FD_CAPS, MII_AR_100TX_HD_CAPS, MII_AR_10T_FD_CAPS, MII_AR_10T_HD_CAPS, MII_AR_ASM_DIR, MII_AR_DEFAULT_CAP_MASK, MII_AR_PAUSE, MII_AR_SPEED_MASK, MII_AT001_CR, MII_AT001_CR_1000T_DEFAULT_CAP_MASK, MII_AT001_CR_1000T_FD_CAPS, MII_AT001_CR_1000T_SPEED_MASK, atl1e_hw::mii_autoneg_adv_reg, atl1e_hw::nic_type, and u16.
Referenced by atl1e_phy_init().
01444 { 01445 s32 ret_val; 01446 u16 mii_autoneg_adv_reg; 01447 u16 mii_1000t_ctrl_reg; 01448 01449 if (0 != hw->mii_autoneg_adv_reg) 01450 return 0; 01451 /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */ 01452 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; 01453 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK; 01454 01455 /* 01456 * First we clear all the 10/100 mb speed bits in the Auto-Neg 01457 * Advertisement Register (Address 4) and the 1000 mb speed bits in 01458 * the 1000Base-T control Register (Address 9). 01459 */ 01460 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; 01461 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK; 01462 01463 /* Assume auto-detect media type */ 01464 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS | 01465 MII_AR_10T_FD_CAPS | 01466 MII_AR_100TX_HD_CAPS | 01467 MII_AR_100TX_FD_CAPS); 01468 if (hw->nic_type == athr_l1e) { 01469 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS; 01470 } 01471 01472 /* flow control fixed to enable all */ 01473 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); 01474 01475 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; 01476 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg; 01477 01478 ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); 01479 if (ret_val) 01480 return ret_val; 01481 01482 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { 01483 ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR, 01484 mii_1000t_ctrl_reg); 01485 if (ret_val) 01486 return ret_val; 01487 } 01488 01489 return 0; 01490 }
| int atl1e_phy_commit | ( | struct atl1e_hw * | hw | ) |
Definition at line 1500 of file atl1e.c.
References AT_READ_REG, atl1e_write_phy_reg(), DBG, mdelay(), MDIO_BUSY, MDIO_START, MII_BMCR, MII_CR_AUTO_NEG_EN, MII_CR_RESET, MII_CR_RESTART_AUTO_NEG, REG_MDIO_CTRL, u16, and u32.
Referenced by atl1e_phy_init().
01501 { 01502 int ret_val; 01503 u16 phy_data; 01504 01505 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; 01506 01507 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data); 01508 if (ret_val) { 01509 u32 val; 01510 int i; 01511 /************************************** 01512 * pcie serdes link may be down ! 01513 **************************************/ 01514 for (i = 0; i < 25; i++) { 01515 mdelay(1); 01516 val = AT_READ_REG(hw, REG_MDIO_CTRL); 01517 if (!(val & (MDIO_START | MDIO_BUSY))) 01518 break; 01519 } 01520 01521 if (0 != (val & (MDIO_START | MDIO_BUSY))) { 01522 DBG("atl1e: PCI-E link down for at least 25ms\n"); 01523 return ret_val; 01524 } 01525 01526 DBG("atl1e: PCI-E link up after %d ms\n", i); 01527 } 01528 return 0; 01529 }
| int atl1e_phy_init | ( | struct atl1e_hw * | hw | ) |
Definition at line 1531 of file atl1e.c.
References AT_WRITE_REGW, atl1e_phy_commit(), atl1e_phy_setup_autoneg_adv(), atl1e_restart_autoneg(), atl1e_write_phy_reg(), DBG, GPHY_CTRL_DEFAULT, GPHY_CTRL_EXT_RESET, mdelay(), MII_DBG_ADDR, MII_DBG_DATA, MII_INT_CTRL, atl1e_hw::phy_configured, atl1e_hw::re_autoneg, REG_GPHY_CTRL, and u16.
Referenced by atl1e_init_hw(), and atl1e_probe().
01532 { 01533 s32 ret_val; 01534 u16 phy_val; 01535 01536 if (hw->phy_configured) { 01537 if (hw->re_autoneg) { 01538 hw->re_autoneg = 0; 01539 return atl1e_restart_autoneg(hw); 01540 } 01541 return 0; 01542 } 01543 01544 /* RESET GPHY Core */ 01545 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT); 01546 mdelay(2); 01547 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT | 01548 GPHY_CTRL_EXT_RESET); 01549 mdelay(2); 01550 01551 /* patches */ 01552 /* p1. eable hibernation mode */ 01553 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB); 01554 if (ret_val) 01555 return ret_val; 01556 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00); 01557 if (ret_val) 01558 return ret_val; 01559 /* p2. set Class A/B for all modes */ 01560 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0); 01561 if (ret_val) 01562 return ret_val; 01563 phy_val = 0x02ef; 01564 /* remove Class AB */ 01565 /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */ 01566 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val); 01567 if (ret_val) 01568 return ret_val; 01569 /* p3. 10B ??? */ 01570 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12); 01571 if (ret_val) 01572 return ret_val; 01573 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04); 01574 if (ret_val) 01575 return ret_val; 01576 /* p4. 1000T power */ 01577 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4); 01578 if (ret_val) 01579 return ret_val; 01580 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB); 01581 if (ret_val) 01582 return ret_val; 01583 01584 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5); 01585 if (ret_val) 01586 return ret_val; 01587 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46); 01588 if (ret_val) 01589 return ret_val; 01590 01591 mdelay(1); 01592 01593 /*Enable PHY LinkChange Interrupt */ 01594 ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00); 01595 if (ret_val) { 01596 DBG("atl1e: Error enable PHY linkChange Interrupt\n"); 01597 return ret_val; 01598 } 01599 /* setup AutoNeg parameters */ 01600 ret_val = atl1e_phy_setup_autoneg_adv(hw); 01601 if (ret_val) { 01602 DBG("atl1e: Error Setting up Auto-Negotiation\n"); 01603 return ret_val; 01604 } 01605 /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/ 01606 DBG("atl1e: Restarting Auto-Neg"); 01607 ret_val = atl1e_phy_commit(hw); 01608 if (ret_val) { 01609 DBG("atl1e: Error Resetting the phy"); 01610 return ret_val; 01611 } 01612 01613 hw->phy_configured = 1; 01614 01615 return 0; 01616 }
Definition at line 1623 of file atl1e.c.
References atl1e_hw::adapter, AT_ERR_TIMEOUT, AT_HW_MAX_IDLE_DELAY, AT_READ_REG, AT_WRITE_REG, DBG, MASTER_CTRL_LED_MODE, MASTER_CTRL_SOFT_RST, mdelay(), PCI_COMMAND, PCI_COMMAND_IO, PCI_COMMAND_MASTER, PCI_COMMAND_MEM, pci_read_config_word(), pci_write_config_word(), atl1e_adapter::pdev, REG_IDLE_STATUS, REG_MASTER_CTRL, timeout(), u16, u32, and wmb.
Referenced by atl1e_down(), atl1e_open(), and atl1e_probe().
01624 { 01625 struct atl1e_adapter *adapter = hw->adapter; 01626 struct pci_device *pdev = adapter->pdev; 01627 int timeout = 0; 01628 u32 idle_status_data = 0; 01629 u16 pci_cfg_cmd_word = 0; 01630 01631 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ 01632 pci_read_config_word(pdev, PCI_COMMAND, &pci_cfg_cmd_word); 01633 if ((pci_cfg_cmd_word & (PCI_COMMAND_IO | PCI_COMMAND_MEM | 01634 PCI_COMMAND_MASTER)) 01635 != (PCI_COMMAND_IO | PCI_COMMAND_MEM | 01636 PCI_COMMAND_MASTER)) { 01637 pci_cfg_cmd_word |= (PCI_COMMAND_IO | PCI_COMMAND_MEM | 01638 PCI_COMMAND_MASTER); 01639 pci_write_config_word(pdev, PCI_COMMAND, pci_cfg_cmd_word); 01640 } 01641 01642 /* 01643 * Issue Soft Reset to the MAC. This will reset the chip's 01644 * transmit, receive, DMA. It will not effect 01645 * the current PCI configuration. The global reset bit is self- 01646 * clearing, and should clear within a microsecond. 01647 */ 01648 AT_WRITE_REG(hw, REG_MASTER_CTRL, 01649 MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST); 01650 wmb(); 01651 mdelay(1); 01652 01653 /* Wait at least 10ms for All module to be Idle */ 01654 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) { 01655 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS); 01656 if (idle_status_data == 0) 01657 break; 01658 mdelay(1); 01659 } 01660 01661 if (timeout >= AT_HW_MAX_IDLE_DELAY) { 01662 DBG("atl1e: MAC reset timeout\n"); 01663 return AT_ERR_TIMEOUT; 01664 } 01665 01666 return 0; 01667 }
| int atl1e_init_hw | ( | struct atl1e_hw * | hw | ) |
Definition at line 1679 of file atl1e.c.
References AT_WRITE_REG, AT_WRITE_REG_ARRAY, atl1e_init_pcie(), atl1e_phy_init(), and REG_RX_HASH_TABLE.
Referenced by atl1e_up().
01680 { 01681 s32 ret_val = 0; 01682 01683 atl1e_init_pcie(hw); 01684 01685 /* Zero out the Multicast HASH table */ 01686 /* clear the old settings from the multicast hash table */ 01687 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); 01688 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); 01689 01690 ret_val = atl1e_phy_init(hw); 01691 01692 return ret_val; 01693 }
Definition at line 1702 of file atl1e.c.
References AT_ERR_PHY_RES, AT_ERR_PHY_SPEED, atl1e_read_phy_reg(), FULL_DUPLEX, HALF_DUPLEX, MII_AT001_PSSR, MII_AT001_PSSR_1000MBS, MII_AT001_PSSR_100MBS, MII_AT001_PSSR_10MBS, MII_AT001_PSSR_DPLX, MII_AT001_PSSR_SPD_DPLX_RESOLVED, MII_AT001_PSSR_SPEED, SPEED_10, SPEED_100, SPEED_1000, and u16.
Referenced by atl1e_check_link().
01703 { 01704 int err; 01705 u16 phy_data; 01706 01707 /* Read PHY Specific Status Register (17) */ 01708 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data); 01709 if (err) 01710 return err; 01711 01712 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED)) 01713 return AT_ERR_PHY_RES; 01714 01715 switch (phy_data & MII_AT001_PSSR_SPEED) { 01716 case MII_AT001_PSSR_1000MBS: 01717 *speed = SPEED_1000; 01718 break; 01719 case MII_AT001_PSSR_100MBS: 01720 *speed = SPEED_100; 01721 break; 01722 case MII_AT001_PSSR_10MBS: 01723 *speed = SPEED_10; 01724 break; 01725 default: 01726 return AT_ERR_PHY_SPEED; 01727 break; 01728 } 01729 01730 if (phy_data & MII_AT001_PSSR_DPLX) 01731 *duplex = FULL_DUPLEX; 01732 else 01733 *duplex = HALF_DUPLEX; 01734 01735 return 0; 01736 }
| int atl1e_restart_autoneg | ( | struct atl1e_hw * | hw | ) |
Definition at line 1738 of file atl1e.c.
References athr_l1e, athr_l2e_revA, atl1e_write_phy_reg(), atl1e_hw::mii_1000t_ctrl_reg, MII_ADVERTISE, MII_AT001_CR, atl1e_hw::mii_autoneg_adv_reg, MII_BMCR, MII_CR_AUTO_NEG_EN, MII_CR_RESET, MII_CR_RESTART_AUTO_NEG, and atl1e_hw::nic_type.
Referenced by atl1e_phy_init(), and atl1e_probe().
01739 { 01740 int err = 0; 01741 01742 err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); 01743 if (err) 01744 return err; 01745 01746 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) { 01747 err = atl1e_write_phy_reg(hw, MII_AT001_CR, 01748 hw->mii_1000t_ctrl_reg); 01749 if (err) 01750 return err; 01751 } 01752 01753 err = atl1e_write_phy_reg(hw, MII_BMCR, 01754 MII_CR_RESET | MII_CR_AUTO_NEG_EN | 01755 MII_CR_RESTART_AUTO_NEG); 01756 return err; 01757 }
struct pci_device_id atl1e_pci_tbl[] [static] |
const u16 atl1e_rx_page_vld_regs[AT_PAGE_NUM_PER_QUEUE] [static] |
Initial value:
Definition at line 67 of file atl1e.c.
Referenced by atl1e_clean_rx_irq(), and atl1e_configure_des_ring().
const u16 atl1e_rx_page_lo_addr_regs[AT_PAGE_NUM_PER_QUEUE] [static] |
const u16 atl1e_rx_page_write_offset_regs[AT_PAGE_NUM_PER_QUEUE] [static] |
const u16 atl1e_pay_load_size[] [static] |
Initial value:
{
128, 256, 512, 1024, 2048, 4096,
}
Definition at line 84 of file atl1e.c.
Referenced by atl1e_configure_tx().
struct net_device_operations atl1e_netdev_ops [static] |
Initial value:
{
.open = atl1e_open,
.close = atl1e_close,
.transmit = atl1e_xmit_frame,
.poll = atl1e_poll,
.irq = atl1e_irq,
}
| struct pci_driver atl1e_driver __pci_driver |
Initial value:
{
.ids = atl1e_pci_tbl,
.id_count = (sizeof(atl1e_pci_tbl) / sizeof(atl1e_pci_tbl[0])),
.probe = atl1e_probe,
.remove = atl1e_remove,
}
1.5.7.1