#include "ath5k.h"#include "reg.h"#include "base.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (MIT) | |
| int | ath5k_hw_set_tx_queueprops (struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info) |
| int | ath5k_hw_setup_tx_queue (struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info) |
| void | ath5k_hw_release_tx_queue (struct ath5k_hw *ah) |
| int | ath5k_hw_reset_tx_queue (struct ath5k_hw *ah) |
| int | ath5k_hw_set_slot_time (struct ath5k_hw *ah, unsigned int slot_time) |
| FILE_LICENCE | ( | MIT | ) |
| int ath5k_hw_set_tx_queueprops | ( | struct ath5k_hw * | ah, | |
| const struct ath5k_txq_info * | queue_info | |||
| ) |
Definition at line 34 of file ath5k_qcu.c.
References ath5k_hw::ah_txq, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_INACTIVE, AR5K_TX_QUEUE_UAPSD, AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS, AR5K_WME_AC_VI, AR5K_WME_AC_VO, EIO, memcpy, ath5k_txq_info::tqi_flags, ath5k_txq_info::tqi_subtype, and ath5k_txq_info::tqi_type.
Referenced by ath5k_hw_setup_tx_queue().
00036 { 00037 if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE) 00038 return -EIO; 00039 00040 memcpy(&ah->ah_txq, queue_info, sizeof(struct ath5k_txq_info)); 00041 00042 /*XXX: Is this supported on 5210 ?*/ 00043 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && 00044 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || 00045 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || 00046 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) 00047 ah->ah_txq.tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; 00048 00049 return 0; 00050 }
| int ath5k_hw_setup_tx_queue | ( | struct ath5k_hw * | ah, | |
| enum ath5k_tx_queue | queue_type, | |||
| struct ath5k_txq_info * | queue_info | |||
| ) |
Definition at line 55 of file ath5k_qcu.c.
References ath5k_hw::ah_txq, ath5k_hw::ah_txq_status, AR5K_Q_ENABLE_BITS, ath5k_hw_set_tx_queueprops(), memset(), NULL, and ath5k_txq_info::tqi_type.
Referenced by ath5k_txq_setup().
00057 { 00058 unsigned int queue; 00059 int ret; 00060 00061 /* We only use one queue */ 00062 queue = 0; 00063 00064 /* 00065 * Setup internal queue structure 00066 */ 00067 memset(&ah->ah_txq, 0, sizeof(struct ath5k_txq_info)); 00068 ah->ah_txq.tqi_type = queue_type; 00069 00070 if (queue_info != NULL) { 00071 queue_info->tqi_type = queue_type; 00072 ret = ath5k_hw_set_tx_queueprops(ah, queue_info); 00073 if (ret) 00074 return ret; 00075 } 00076 00077 /* 00078 * We use ah_txq_status to hold a temp value for 00079 * the Secondary interrupt mask registers on 5211+ 00080 * check out ath5k_hw_reset_tx_queue 00081 */ 00082 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, 0); 00083 00084 return 0; 00085 }
| void ath5k_hw_release_tx_queue | ( | struct ath5k_hw * | ah | ) |
Definition at line 90 of file ath5k_qcu.c.
References ath5k_hw::ah_txq, ath5k_hw::ah_txq_status, AR5K_Q_DISABLE_BITS, AR5K_TX_QUEUE_INACTIVE, and ath5k_txq_info::tqi_type.
Referenced by ath5k_txq_release().
00091 { 00092 /* This queue will be skipped in further operations */ 00093 ah->ah_txq.tqi_type = AR5K_TX_QUEUE_INACTIVE; 00094 /*For SIMR setup*/ 00095 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, 0); 00096 }
| int ath5k_hw_reset_tx_queue | ( | struct ath5k_hw * | ah | ) |
Definition at line 101 of file ath5k_qcu.c.
References ath5k_hw::ah_aifs, ath5k_hw::ah_current_channel, ath5k_hw::ah_cw_max, ath5k_hw::ah_cw_min, ath5k_hw::ah_limit_tx_retries, ath5k_hw::ah_mac_version, ath5k_hw::ah_software_retry, ath5k_hw::ah_turbo, ath5k_hw::ah_txq, ath5k_hw::ah_txq_imr_cbrorn, ath5k_hw::ah_txq_imr_cbrurn, ath5k_hw::ah_txq_imr_nofrm, ath5k_hw::ah_txq_imr_qtrig, ath5k_hw::ah_txq_imr_txdesc, ath5k_hw::ah_txq_imr_txeol, ath5k_hw::ah_txq_imr_txerr, ath5k_hw::ah_txq_imr_txok, ath5k_hw::ah_txq_imr_txurn, ath5k_hw::ah_txq_status, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5212, AR5K_DCU_CHAN_TIME_DUR, AR5K_DCU_CHAN_TIME_ENABLE, AR5K_DCU_LCL_IFS_AIFS, AR5K_DCU_LCL_IFS_CW_MAX, AR5K_DCU_LCL_IFS_CW_MIN, AR5K_DCU_MISC_BACKOFF_FRAG, AR5K_DCU_MISC_FRAG_WAIT, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, AR5K_DCU_MISC_SEQNUM_CTL, AR5K_DCU_RETRY_LMT_LG_RETRY, AR5K_DCU_RETRY_LMT_SH_RETRY, AR5K_DCU_RETRY_LMT_SLG_RETRY, AR5K_DCU_RETRY_LMT_SSH_RETRY, AR5K_IFS0, AR5K_IFS0_DIFS_S, AR5K_IFS1, AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_INIT_ACK_CTS_TIMEOUT_TURBO, AR5K_INIT_LG_RETRY, AR5K_INIT_PROTO_TIME_CNTRL, AR5K_INIT_PROTO_TIME_CNTRL_TURBO, AR5K_INIT_SH_RETRY, AR5K_INIT_SIFS, AR5K_INIT_SIFS_TURBO, AR5K_INIT_SLG_RETRY, AR5K_INIT_SLOT_TIME, AR5K_INIT_SLOT_TIME_TURBO, AR5K_INIT_SSH_RETRY, AR5K_INIT_TRANSMIT_LATENCY, AR5K_INIT_TRANSMIT_LATENCY_TURBO, AR5K_NODCU_RETRY_LMT, AR5K_NODCU_RETRY_LMT_CW_MIN_S, AR5K_NODCU_RETRY_LMT_LG_RETRY, AR5K_NODCU_RETRY_LMT_SH_RETRY, AR5K_NODCU_RETRY_LMT_SLG_RETRY, AR5K_NODCU_RETRY_LMT_SSH_RETRY, AR5K_PHY_FRAME_CTL_5210, AR5K_PHY_FRAME_CTL_INI, AR5K_PHY_SETTLING, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_Q_ENABLE_BITS, AR5K_QCU_CBRCFG_INTVAL, AR5K_QCU_CBRCFG_ORN_THRES, AR5K_QCU_MISC_CBR_THRES_ENABLE, AR5K_QCU_MISC_DCU_EARLY, AR5K_QCU_MISC_FRSHED_CBR, AR5K_QCU_MISC_RDY_VEOL_POLICY, AR5K_QCU_RDYTIMECFG_ENABLE, AR5K_QCU_RDYTIMECFG_INTVAL, AR5K_QUEUE_CBRCFG, AR5K_QUEUE_DFS_CHANNEL_TIME, AR5K_QUEUE_DFS_LOCAL_IFS, AR5K_QUEUE_DFS_MISC, AR5K_QUEUE_DFS_RETRY_LIMIT, AR5K_QUEUE_MISC, AR5K_QUEUE_QCUMASK, AR5K_QUEUE_RDYTIMECFG, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SIMR0, AR5K_SIMR0_QCU_TXDESC, AR5K_SIMR0_QCU_TXOK, AR5K_SIMR1, AR5K_SIMR1_QCU_TXEOL, AR5K_SIMR1_QCU_TXERR, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR3, AR5K_SIMR3_QCBRORN, AR5K_SIMR3_QCBRURN, AR5K_SIMR4, AR5K_SIMR4_QTRIG, AR5K_SLOT_TIME, AR5K_SREV_AR5211, AR5K_TUNE_AIFS, AR5K_TUNE_AIFS_11B, AR5K_TUNE_AIFS_XR, AR5K_TUNE_CWMAX, AR5K_TUNE_CWMAX_11B, AR5K_TUNE_CWMAX_XR, AR5K_TUNE_CWMIN, AR5K_TUNE_CWMIN_11B, AR5K_TUNE_CWMIN_XR, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_ID_CAB, AR5K_TX_QUEUE_INACTIVE, AR5K_TXNOFRM, AR5K_TXNOFRM_QCU, AR5K_TXQ_FLAG_BACKOFF_DISABLE, AR5K_TXQ_FLAG_CBRORNINT_ENABLE, AR5K_TXQ_FLAG_CBRURNINT_ENABLE, AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, AR5K_TXQ_FLAG_QTRIGINT_ENABLE, AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, AR5K_TXQ_FLAG_TXDESCINT_ENABLE, AR5K_TXQ_FLAG_TXEOLINT_ENABLE, AR5K_TXQ_FLAG_TXERRINT_ENABLE, AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE, AR5K_TXQ_FLAG_TXOKINT_ENABLE, AR5K_TXQ_FLAG_TXURNINT_ENABLE, AR5K_USEC_5210, ath5k_hw_reg_read(), ath5k_hw_reg_write(), IS_CHAN_B, IS_CHAN_XR, ath5k_txq_info::tqi_aifs, ath5k_txq_info::tqi_burst_time, ath5k_txq_info::tqi_cbr_overflow_limit, ath5k_txq_info::tqi_cbr_period, ath5k_txq_info::tqi_cw_max, ath5k_txq_info::tqi_cw_min, ath5k_txq_info::tqi_flags, ath5k_txq_info::tqi_ready_time, ath5k_txq_info::tqi_type, and u32.
Referenced by ath5k_hw_reset().
00102 { 00103 u32 cw_min, cw_max, retry_lg, retry_sh; 00104 struct ath5k_txq_info *tq = &ah->ah_txq; 00105 const int queue = 0; 00106 00107 tq = &ah->ah_txq; 00108 00109 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) 00110 return 0; 00111 00112 if (ah->ah_version == AR5K_AR5210) { 00113 /* Only handle data queues, others will be ignored */ 00114 if (tq->tqi_type != AR5K_TX_QUEUE_DATA) 00115 return 0; 00116 00117 /* Set Slot time */ 00118 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00119 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, 00120 AR5K_SLOT_TIME); 00121 /* Set ACK_CTS timeout */ 00122 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00123 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : 00124 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); 00125 /* Set Transmit Latency */ 00126 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00127 AR5K_INIT_TRANSMIT_LATENCY_TURBO : 00128 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); 00129 00130 /* Set IFS0 */ 00131 if (ah->ah_turbo) { 00132 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + 00133 (ah->ah_aifs + tq->tqi_aifs) * 00134 AR5K_INIT_SLOT_TIME_TURBO) << 00135 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, 00136 AR5K_IFS0); 00137 } else { 00138 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS + 00139 (ah->ah_aifs + tq->tqi_aifs) * 00140 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) | 00141 AR5K_INIT_SIFS, AR5K_IFS0); 00142 } 00143 00144 /* Set IFS1 */ 00145 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00146 AR5K_INIT_PROTO_TIME_CNTRL_TURBO : 00147 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); 00148 /* Set AR5K_PHY_SETTLING */ 00149 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00150 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) 00151 | 0x38 : 00152 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) 00153 | 0x1C, 00154 AR5K_PHY_SETTLING); 00155 /* Set Frame Control Register */ 00156 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00157 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | 00158 AR5K_PHY_TURBO_SHORT | 0x2020) : 00159 (AR5K_PHY_FRAME_CTL_INI | 0x1020), 00160 AR5K_PHY_FRAME_CTL_5210); 00161 } 00162 00163 /* 00164 * Calculate cwmin/max by channel mode 00165 */ 00166 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN; 00167 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX; 00168 ah->ah_aifs = AR5K_TUNE_AIFS; 00169 /*XR is only supported on 5212*/ 00170 if (IS_CHAN_XR(ah->ah_current_channel) && 00171 ah->ah_version == AR5K_AR5212) { 00172 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR; 00173 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR; 00174 ah->ah_aifs = AR5K_TUNE_AIFS_XR; 00175 /*B mode is not supported on 5210*/ 00176 } else if (IS_CHAN_B(ah->ah_current_channel) && 00177 ah->ah_version != AR5K_AR5210) { 00178 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B; 00179 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B; 00180 ah->ah_aifs = AR5K_TUNE_AIFS_11B; 00181 } 00182 00183 cw_min = 1; 00184 while (cw_min < ah->ah_cw_min) 00185 cw_min = (cw_min << 1) | 1; 00186 00187 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) : 00188 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 00189 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) : 00190 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); 00191 00192 /* 00193 * Calculate and set retry limits 00194 */ 00195 if (ah->ah_software_retry) { 00196 /* XXX Need to test this */ 00197 retry_lg = ah->ah_limit_tx_retries; 00198 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? 00199 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; 00200 } else { 00201 retry_lg = AR5K_INIT_LG_RETRY; 00202 retry_sh = AR5K_INIT_SH_RETRY; 00203 } 00204 00205 /*No QCU/DCU [5210]*/ 00206 if (ah->ah_version == AR5K_AR5210) { 00207 ath5k_hw_reg_write(ah, 00208 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) 00209 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 00210 AR5K_NODCU_RETRY_LMT_SLG_RETRY) 00211 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 00212 AR5K_NODCU_RETRY_LMT_SSH_RETRY) 00213 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) 00214 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY), 00215 AR5K_NODCU_RETRY_LMT); 00216 } else { 00217 /*QCU/DCU [5211+]*/ 00218 ath5k_hw_reg_write(ah, 00219 AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 00220 AR5K_DCU_RETRY_LMT_SLG_RETRY) | 00221 AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 00222 AR5K_DCU_RETRY_LMT_SSH_RETRY) | 00223 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | 00224 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY), 00225 AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); 00226 00227 /*===Rest is also for QCU/DCU only [5211+]===*/ 00228 00229 /* 00230 * Set initial content window (cw_min/cw_max) 00231 * and arbitrated interframe space (aifs)... 00232 */ 00233 ath5k_hw_reg_write(ah, 00234 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | 00235 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | 00236 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs, 00237 AR5K_DCU_LCL_IFS_AIFS), 00238 AR5K_QUEUE_DFS_LOCAL_IFS(queue)); 00239 00240 /* 00241 * Set misc registers 00242 */ 00243 /* Enable DCU early termination for this queue */ 00244 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 00245 AR5K_QCU_MISC_DCU_EARLY); 00246 00247 /* Enable DCU to wait for next fragment from QCU */ 00248 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 00249 AR5K_DCU_MISC_FRAG_WAIT); 00250 00251 /* On Maui and Spirit use the global seqnum on DCU */ 00252 if (ah->ah_mac_version < AR5K_SREV_AR5211) 00253 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 00254 AR5K_DCU_MISC_SEQNUM_CTL); 00255 00256 if (tq->tqi_cbr_period) { 00257 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period, 00258 AR5K_QCU_CBRCFG_INTVAL) | 00259 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, 00260 AR5K_QCU_CBRCFG_ORN_THRES), 00261 AR5K_QUEUE_CBRCFG(queue)); 00262 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 00263 AR5K_QCU_MISC_FRSHED_CBR); 00264 if (tq->tqi_cbr_overflow_limit) 00265 AR5K_REG_ENABLE_BITS(ah, 00266 AR5K_QUEUE_MISC(queue), 00267 AR5K_QCU_MISC_CBR_THRES_ENABLE); 00268 } 00269 00270 if (tq->tqi_ready_time && 00271 (tq->tqi_type != AR5K_TX_QUEUE_ID_CAB)) 00272 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time, 00273 AR5K_QCU_RDYTIMECFG_INTVAL) | 00274 AR5K_QCU_RDYTIMECFG_ENABLE, 00275 AR5K_QUEUE_RDYTIMECFG(queue)); 00276 00277 if (tq->tqi_burst_time) { 00278 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time, 00279 AR5K_DCU_CHAN_TIME_DUR) | 00280 AR5K_DCU_CHAN_TIME_ENABLE, 00281 AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); 00282 00283 if (tq->tqi_flags 00284 & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) 00285 AR5K_REG_ENABLE_BITS(ah, 00286 AR5K_QUEUE_MISC(queue), 00287 AR5K_QCU_MISC_RDY_VEOL_POLICY); 00288 } 00289 00290 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) 00291 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, 00292 AR5K_QUEUE_DFS_MISC(queue)); 00293 00294 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) 00295 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG, 00296 AR5K_QUEUE_DFS_MISC(queue)); 00297 00298 /* TODO: Handle frame compression */ 00299 00300 /* 00301 * Enable interrupts for this tx queue 00302 * in the secondary interrupt mask registers 00303 */ 00304 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE) 00305 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue); 00306 00307 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE) 00308 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue); 00309 00310 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE) 00311 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue); 00312 00313 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE) 00314 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue); 00315 00316 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE) 00317 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue); 00318 00319 if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE) 00320 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue); 00321 00322 if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE) 00323 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue); 00324 00325 if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE) 00326 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue); 00327 00328 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE) 00329 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue); 00330 00331 /* Update secondary interrupt mask registers */ 00332 00333 /* Filter out inactive queues */ 00334 ah->ah_txq_imr_txok &= ah->ah_txq_status; 00335 ah->ah_txq_imr_txerr &= ah->ah_txq_status; 00336 ah->ah_txq_imr_txurn &= ah->ah_txq_status; 00337 ah->ah_txq_imr_txdesc &= ah->ah_txq_status; 00338 ah->ah_txq_imr_txeol &= ah->ah_txq_status; 00339 ah->ah_txq_imr_cbrorn &= ah->ah_txq_status; 00340 ah->ah_txq_imr_cbrurn &= ah->ah_txq_status; 00341 ah->ah_txq_imr_qtrig &= ah->ah_txq_status; 00342 ah->ah_txq_imr_nofrm &= ah->ah_txq_status; 00343 00344 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok, 00345 AR5K_SIMR0_QCU_TXOK) | 00346 AR5K_REG_SM(ah->ah_txq_imr_txdesc, 00347 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); 00348 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr, 00349 AR5K_SIMR1_QCU_TXERR) | 00350 AR5K_REG_SM(ah->ah_txq_imr_txeol, 00351 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1); 00352 /* Update simr2 but don't overwrite rest simr2 settings */ 00353 AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN); 00354 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, 00355 AR5K_REG_SM(ah->ah_txq_imr_txurn, 00356 AR5K_SIMR2_QCU_TXURN)); 00357 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn, 00358 AR5K_SIMR3_QCBRORN) | 00359 AR5K_REG_SM(ah->ah_txq_imr_cbrurn, 00360 AR5K_SIMR3_QCBRURN), AR5K_SIMR3); 00361 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig, 00362 AR5K_SIMR4_QTRIG), AR5K_SIMR4); 00363 /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */ 00364 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm, 00365 AR5K_TXNOFRM_QCU), AR5K_TXNOFRM); 00366 /* No queue has TXNOFRM enabled, disable the interrupt 00367 * by setting AR5K_TXNOFRM to zero */ 00368 if (ah->ah_txq_imr_nofrm == 0) 00369 ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM); 00370 00371 /* Set QCU mask for this DCU to save power */ 00372 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue); 00373 } 00374 00375 return 0; 00376 }
| int ath5k_hw_set_slot_time | ( | struct ath5k_hw * | ah, | |
| unsigned int | slot_time | |||
| ) |
Definition at line 381 of file ath5k_qcu.c.
References ath5k_hw::ah_turbo, ath5k_hw::ah_version, AR5K_AR5210, AR5K_DCU_GBL_IFS_SLOT, AR5K_SLOT_TIME, AR5K_SLOT_TIME_MAX, ath5k_hw_htoclock(), ath5k_hw_reg_write(), and EINVAL.
00382 { 00383 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) 00384 return -EINVAL; 00385 00386 if (ah->ah_version == AR5K_AR5210) 00387 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time, 00388 ah->ah_turbo), AR5K_SLOT_TIME); 00389 else 00390 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT); 00391 00392 return 0; 00393 }
1.5.7.1