#include <unistd.h>#include "ath5k.h"#include "reg.h"#include "base.h"Go to the source code of this file.
| FILE_LICENCE | ( | MIT | ) |
| static void ath5k_hw_ini_registers | ( | struct ath5k_hw * | ah, | |
| unsigned int | size, | |||
| const struct ath5k_ini * | ini_regs, | |||
| int | change_channel | |||
| ) | [static] |
Definition at line 1377 of file ath5k_initvals.c.
References ath5k_ini::AR5K_INI_READ, ath5k_ini::AR5K_INI_WRITE, AR5K_PCU_MAX, AR5K_PCU_MIN, AR5K_REG_WAIT, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_ini::ini_mode, ath5k_ini::ini_register, and ath5k_ini::ini_value.
Referenced by ath5k_hw_write_initvals().
01379 { 01380 unsigned int i; 01381 01382 /* Write initial registers */ 01383 for (i = 0; i < size; i++) { 01384 /* On channel change there is 01385 * no need to mess with PCU */ 01386 if (change_channel && 01387 ini_regs[i].ini_register >= AR5K_PCU_MIN && 01388 ini_regs[i].ini_register <= AR5K_PCU_MAX) 01389 continue; 01390 01391 switch (ini_regs[i].ini_mode) { 01392 case AR5K_INI_READ: 01393 /* Cleared on read */ 01394 ath5k_hw_reg_read(ah, ini_regs[i].ini_register); 01395 break; 01396 case AR5K_INI_WRITE: 01397 default: 01398 AR5K_REG_WAIT(i); 01399 ath5k_hw_reg_write(ah, ini_regs[i].ini_value, 01400 ini_regs[i].ini_register); 01401 } 01402 } 01403 }
| static void ath5k_hw_ini_mode_registers | ( | struct ath5k_hw * | ah, | |
| unsigned int | size, | |||
| const struct ath5k_ini_mode * | ini_mode, | |||
| u8 | mode | |||
| ) | [static] |
Definition at line 1405 of file ath5k_initvals.c.
References AR5K_REG_WAIT, ath5k_hw_reg_write(), and u32.
Referenced by ath5k_hw_write_initvals().
01408 { 01409 unsigned int i; 01410 01411 for (i = 0; i < size; i++) { 01412 AR5K_REG_WAIT(i); 01413 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode], 01414 (u32)ini_mode[i].mode_register); 01415 } 01416 }
Definition at line 1418 of file ath5k_initvals.c.
References ath5k_hw::ah_radio, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_PHY_AGC, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, ARRAY_SIZE, ath5k_hw_ini_mode_registers(), ath5k_hw_ini_registers(), ath5k_hw_reg_write(), DBG, and EINVAL.
Referenced by ath5k_hw_reset().
01419 { 01420 /* 01421 * Write initial register settings 01422 */ 01423 01424 /* For AR5212 and combatible */ 01425 if (ah->ah_version == AR5K_AR5212) { 01426 01427 /* First set of mode-specific settings */ 01428 ath5k_hw_ini_mode_registers(ah, 01429 ARRAY_SIZE(ar5212_ini_mode_start), 01430 ar5212_ini_mode_start, mode); 01431 01432 /* 01433 * Write initial settings common for all modes 01434 */ 01435 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start), 01436 ar5212_ini_common_start, change_channel); 01437 01438 /* Second set of mode-specific settings */ 01439 switch (ah->ah_radio) { 01440 case AR5K_RF5111: 01441 01442 ath5k_hw_ini_mode_registers(ah, 01443 ARRAY_SIZE(rf5111_ini_mode_end), 01444 rf5111_ini_mode_end, mode); 01445 01446 ath5k_hw_ini_registers(ah, 01447 ARRAY_SIZE(rf5111_ini_common_end), 01448 rf5111_ini_common_end, change_channel); 01449 01450 /* Baseband gain table */ 01451 ath5k_hw_ini_registers(ah, 01452 ARRAY_SIZE(rf5111_ini_bbgain), 01453 rf5111_ini_bbgain, change_channel); 01454 01455 break; 01456 case AR5K_RF5112: 01457 01458 ath5k_hw_ini_mode_registers(ah, 01459 ARRAY_SIZE(rf5112_ini_mode_end), 01460 rf5112_ini_mode_end, mode); 01461 01462 ath5k_hw_ini_registers(ah, 01463 ARRAY_SIZE(rf5112_ini_common_end), 01464 rf5112_ini_common_end, change_channel); 01465 01466 ath5k_hw_ini_registers(ah, 01467 ARRAY_SIZE(rf5112_ini_bbgain), 01468 rf5112_ini_bbgain, change_channel); 01469 01470 break; 01471 case AR5K_RF5413: 01472 01473 ath5k_hw_ini_mode_registers(ah, 01474 ARRAY_SIZE(rf5413_ini_mode_end), 01475 rf5413_ini_mode_end, mode); 01476 01477 ath5k_hw_ini_registers(ah, 01478 ARRAY_SIZE(rf5413_ini_common_end), 01479 rf5413_ini_common_end, change_channel); 01480 01481 ath5k_hw_ini_registers(ah, 01482 ARRAY_SIZE(rf5112_ini_bbgain), 01483 rf5112_ini_bbgain, change_channel); 01484 01485 break; 01486 case AR5K_RF2316: 01487 case AR5K_RF2413: 01488 01489 ath5k_hw_ini_mode_registers(ah, 01490 ARRAY_SIZE(rf2413_ini_mode_end), 01491 rf2413_ini_mode_end, mode); 01492 01493 ath5k_hw_ini_registers(ah, 01494 ARRAY_SIZE(rf2413_ini_common_end), 01495 rf2413_ini_common_end, change_channel); 01496 01497 /* Override settings from rf2413_ini_common_end */ 01498 if (ah->ah_radio == AR5K_RF2316) { 01499 ath5k_hw_reg_write(ah, 0x00004000, 01500 AR5K_PHY_AGC); 01501 ath5k_hw_reg_write(ah, 0x081b7caa, 01502 0xa274); 01503 } 01504 01505 ath5k_hw_ini_registers(ah, 01506 ARRAY_SIZE(rf5112_ini_bbgain), 01507 rf5112_ini_bbgain, change_channel); 01508 break; 01509 case AR5K_RF2317: 01510 case AR5K_RF2425: 01511 01512 ath5k_hw_ini_mode_registers(ah, 01513 ARRAY_SIZE(rf2425_ini_mode_end), 01514 rf2425_ini_mode_end, mode); 01515 01516 ath5k_hw_ini_registers(ah, 01517 ARRAY_SIZE(rf2425_ini_common_end), 01518 rf2425_ini_common_end, change_channel); 01519 01520 ath5k_hw_ini_registers(ah, 01521 ARRAY_SIZE(rf5112_ini_bbgain), 01522 rf5112_ini_bbgain, change_channel); 01523 break; 01524 default: 01525 return -EINVAL; 01526 01527 } 01528 01529 /* For AR5211 */ 01530 } else if (ah->ah_version == AR5K_AR5211) { 01531 01532 /* AR5K_MODE_11B */ 01533 if (mode > 2) { 01534 DBG("ath5k: unsupported channel mode %d\n", mode); 01535 return -EINVAL; 01536 } 01537 01538 /* Mode-specific settings */ 01539 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode), 01540 ar5211_ini_mode, mode); 01541 01542 /* 01543 * Write initial settings common for all modes 01544 */ 01545 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini), 01546 ar5211_ini, change_channel); 01547 01548 /* AR5211 only comes with 5111 */ 01549 01550 /* Baseband gain table */ 01551 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain), 01552 rf5111_ini_bbgain, change_channel); 01553 /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */ 01554 } else if (ah->ah_version == AR5K_AR5210) { 01555 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini), 01556 ar5210_ini, change_channel); 01557 } 01558 01559 return 0; 01560 }
struct ath5k_ini ar5210_ini[] [static] |
Definition at line 56 of file ath5k_initvals.c.
struct ath5k_ini ar5211_ini[] [static] |
Definition at line 268 of file ath5k_initvals.c.
struct ath5k_ini_mode ar5211_ini_mode[] [static] |
Definition at line 397 of file ath5k_initvals.c.
struct ath5k_ini ar5212_ini_common_start[] [static] |
Definition at line 472 of file ath5k_initvals.c.
struct ath5k_ini_mode ar5212_ini_mode_start[] [static] |
Definition at line 685 of file ath5k_initvals.c.
struct ath5k_ini_mode rf5111_ini_mode_end[] [static] |
Definition at line 740 of file ath5k_initvals.c.
struct ath5k_ini rf5111_ini_common_end[] [static] |
Initial value:
{
{ AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
{ AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
{ AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE },
{ 0x983c, 0x00020100, AR5K_INI_WRITE },
{ AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
{ AR5K_PHY_PAPD_PROBE, 0x00004883, AR5K_INI_WRITE },
{ 0x9940, 0x00000004, AR5K_INI_WRITE },
{ 0x9958, 0x000000ff, AR5K_INI_WRITE },
{ 0x9974, 0x00000000, AR5K_INI_WRITE },
{ AR5K_PHY_SPENDING, 0x00000018, AR5K_INI_WRITE },
{ AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE },
{ AR5K_PHY_CCK_CROSSCORR, 0xd03e6788, AR5K_INI_WRITE },
{ AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
{ 0xa23c, 0x13c889af, AR5K_INI_WRITE },
}
Definition at line 772 of file ath5k_initvals.c.
struct ath5k_ini_mode rf5112_ini_mode_end[] [static] |
Definition at line 790 of file ath5k_initvals.c.
struct ath5k_ini rf5112_ini_common_end[] [static] |
Initial value:
{
{ AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
{ AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
{ AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE },
{ 0x983c, 0x00020100, AR5K_INI_WRITE },
{ AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
{ AR5K_PHY_PAPD_PROBE, 0x00004882, AR5K_INI_WRITE },
{ 0x9940, 0x00000004, AR5K_INI_WRITE },
{ 0x9958, 0x000000ff, AR5K_INI_WRITE },
{ 0x9974, 0x00000000, AR5K_INI_WRITE },
{ AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
{ 0xa23c, 0x13c889af, AR5K_INI_WRITE },
}
Definition at line 826 of file ath5k_initvals.c.
struct ath5k_ini_mode rf5413_ini_mode_end[] [static] |
Definition at line 841 of file ath5k_initvals.c.
struct ath5k_ini rf5413_ini_common_end[] [static] |
Definition at line 905 of file ath5k_initvals.c.
struct ath5k_ini_mode rf2413_ini_mode_end[] [static] |
Definition at line 980 of file ath5k_initvals.c.
struct ath5k_ini rf2413_ini_common_end[] [static] |
Definition at line 1016 of file ath5k_initvals.c.
struct ath5k_ini_mode rf2425_ini_mode_end[] [static] |
Definition at line 1102 of file ath5k_initvals.c.
struct ath5k_ini rf2425_ini_common_end[] [static] |
Definition at line 1152 of file ath5k_initvals.c.
struct ath5k_ini rf5111_ini_bbgain[] [static] |
Definition at line 1238 of file ath5k_initvals.c.
struct ath5k_ini rf5112_ini_bbgain[] [static] |
Definition at line 1306 of file ath5k_initvals.c.
1.5.7.1