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00024 FILE_LICENCE ( MIT );
00025
00026 #include <unistd.h>
00027
00028 #include "ath5k.h"
00029 #include "reg.h"
00030 #include "base.h"
00031
00032
00033
00034
00035
00036 struct ath5k_ini {
00037 u16 ini_register;
00038 u32 ini_value;
00039
00040 enum {
00041 AR5K_INI_WRITE = 0,
00042 AR5K_INI_READ = 1,
00043 } ini_mode;
00044 };
00045
00046
00047
00048
00049
00050 struct ath5k_ini_mode {
00051 u16 mode_register;
00052 u32 mode_value[5];
00053 };
00054
00055
00056 static const struct ath5k_ini ar5210_ini[] = {
00057
00058 { AR5K_NOQCU_TXDP0, 0, AR5K_INI_WRITE },
00059 { AR5K_NOQCU_TXDP1, 0, AR5K_INI_WRITE },
00060 { AR5K_RXDP, 0, AR5K_INI_WRITE },
00061 { AR5K_CR, 0, AR5K_INI_WRITE },
00062 { AR5K_ISR, 0, AR5K_INI_READ },
00063 { AR5K_IMR, 0, AR5K_INI_WRITE },
00064 { AR5K_IER, AR5K_IER_DISABLE, AR5K_INI_WRITE },
00065 { AR5K_BSR, 0, AR5K_INI_READ },
00066 { AR5K_TXCFG, AR5K_DMASIZE_128B, AR5K_INI_WRITE },
00067 { AR5K_RXCFG, AR5K_DMASIZE_128B, AR5K_INI_WRITE },
00068 { AR5K_CFG, AR5K_INIT_CFG, AR5K_INI_WRITE },
00069 { AR5K_TOPS, 8, AR5K_INI_WRITE },
00070 { AR5K_RXNOFRM, 8, AR5K_INI_WRITE },
00071 { AR5K_RPGTO, 0, AR5K_INI_WRITE },
00072 { AR5K_TXNOFRM, 0, AR5K_INI_WRITE },
00073 { AR5K_SFR, 0, AR5K_INI_WRITE },
00074 { AR5K_MIBC, 0, AR5K_INI_WRITE },
00075 { AR5K_MISC, 0, AR5K_INI_WRITE },
00076 { AR5K_RX_FILTER_5210, 0, AR5K_INI_WRITE },
00077 { AR5K_MCAST_FILTER0_5210, 0, AR5K_INI_WRITE },
00078 { AR5K_MCAST_FILTER1_5210, 0, AR5K_INI_WRITE },
00079 { AR5K_TX_MASK0, 0, AR5K_INI_WRITE },
00080 { AR5K_TX_MASK1, 0, AR5K_INI_WRITE },
00081 { AR5K_CLR_TMASK, 0, AR5K_INI_WRITE },
00082 { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_INI_WRITE },
00083 { AR5K_DIAG_SW_5210, 0, AR5K_INI_WRITE },
00084 { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES, AR5K_INI_WRITE },
00085 { AR5K_TSF_L32_5210, 0, AR5K_INI_WRITE },
00086 { AR5K_TIMER0_5210, 0, AR5K_INI_WRITE },
00087 { AR5K_TIMER1_5210, 0xffffffff, AR5K_INI_WRITE },
00088 { AR5K_TIMER2_5210, 0xffffffff, AR5K_INI_WRITE },
00089 { AR5K_TIMER3_5210, 1, AR5K_INI_WRITE },
00090 { AR5K_CFP_DUR_5210, 0, AR5K_INI_WRITE },
00091 { AR5K_CFP_PERIOD_5210, 0, AR5K_INI_WRITE },
00092
00093 { AR5K_PHY(0), 0x00000047, AR5K_INI_WRITE },
00094 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
00095 { AR5K_PHY(3), 0x09848ea6, AR5K_INI_WRITE },
00096 { AR5K_PHY(4), 0x3d32e000, AR5K_INI_WRITE },
00097 { AR5K_PHY(5), 0x0000076b, AR5K_INI_WRITE },
00098 { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_INI_WRITE },
00099 { AR5K_PHY(8), 0x02020200, AR5K_INI_WRITE },
00100 { AR5K_PHY(9), 0x00000e0e, AR5K_INI_WRITE },
00101 { AR5K_PHY(10), 0x0a020201, AR5K_INI_WRITE },
00102 { AR5K_PHY(11), 0x00036ffc, AR5K_INI_WRITE },
00103 { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE },
00104 { AR5K_PHY(13), 0x00000e0e, AR5K_INI_WRITE },
00105 { AR5K_PHY(14), 0x00000007, AR5K_INI_WRITE },
00106 { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE },
00107 { AR5K_PHY(16), 0x89630000, AR5K_INI_WRITE },
00108 { AR5K_PHY(17), 0x1372169c, AR5K_INI_WRITE },
00109 { AR5K_PHY(18), 0x0018b633, AR5K_INI_WRITE },
00110 { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE },
00111 { AR5K_PHY(20), 0x0de8b8e0, AR5K_INI_WRITE },
00112 { AR5K_PHY(21), 0x00074859, AR5K_INI_WRITE },
00113 { AR5K_PHY(22), 0x7e80beba, AR5K_INI_WRITE },
00114 { AR5K_PHY(23), 0x313a665e, AR5K_INI_WRITE },
00115 { AR5K_PHY_AGCCTL, 0x00001d08, AR5K_INI_WRITE },
00116 { AR5K_PHY(25), 0x0001ce00, AR5K_INI_WRITE },
00117 { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE },
00118 { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE },
00119 { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE },
00120 { AR5K_PHY(30), 0x00000004, AR5K_INI_WRITE },
00121 { AR5K_PHY(31), 0x00000018, AR5K_INI_WRITE },
00122 { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE },
00123 { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE },
00124 { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE },
00125 { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE },
00126 { AR5K_PHY(68), 0x00000003, AR5K_INI_WRITE },
00127
00128 { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
00129 { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE },
00130 { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE },
00131 { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE },
00132 { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE },
00133 { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE },
00134 { AR5K_BB_GAIN(6), 0x00000028, AR5K_INI_WRITE },
00135 { AR5K_BB_GAIN(7), 0x00000004, AR5K_INI_WRITE },
00136 { AR5K_BB_GAIN(8), 0x00000024, AR5K_INI_WRITE },
00137 { AR5K_BB_GAIN(9), 0x00000014, AR5K_INI_WRITE },
00138 { AR5K_BB_GAIN(10), 0x00000034, AR5K_INI_WRITE },
00139 { AR5K_BB_GAIN(11), 0x0000000c, AR5K_INI_WRITE },
00140 { AR5K_BB_GAIN(12), 0x0000002c, AR5K_INI_WRITE },
00141 { AR5K_BB_GAIN(13), 0x00000002, AR5K_INI_WRITE },
00142 { AR5K_BB_GAIN(14), 0x00000022, AR5K_INI_WRITE },
00143 { AR5K_BB_GAIN(15), 0x00000012, AR5K_INI_WRITE },
00144 { AR5K_BB_GAIN(16), 0x00000032, AR5K_INI_WRITE },
00145 { AR5K_BB_GAIN(17), 0x0000000a, AR5K_INI_WRITE },
00146 { AR5K_BB_GAIN(18), 0x0000002a, AR5K_INI_WRITE },
00147 { AR5K_BB_GAIN(19), 0x00000001, AR5K_INI_WRITE },
00148 { AR5K_BB_GAIN(20), 0x00000021, AR5K_INI_WRITE },
00149 { AR5K_BB_GAIN(21), 0x00000011, AR5K_INI_WRITE },
00150 { AR5K_BB_GAIN(22), 0x00000031, AR5K_INI_WRITE },
00151 { AR5K_BB_GAIN(23), 0x00000009, AR5K_INI_WRITE },
00152 { AR5K_BB_GAIN(24), 0x00000029, AR5K_INI_WRITE },
00153 { AR5K_BB_GAIN(25), 0x00000005, AR5K_INI_WRITE },
00154 { AR5K_BB_GAIN(26), 0x00000025, AR5K_INI_WRITE },
00155 { AR5K_BB_GAIN(27), 0x00000015, AR5K_INI_WRITE },
00156 { AR5K_BB_GAIN(28), 0x00000035, AR5K_INI_WRITE },
00157 { AR5K_BB_GAIN(29), 0x0000000d, AR5K_INI_WRITE },
00158 { AR5K_BB_GAIN(30), 0x0000002d, AR5K_INI_WRITE },
00159 { AR5K_BB_GAIN(31), 0x00000003, AR5K_INI_WRITE },
00160 { AR5K_BB_GAIN(32), 0x00000023, AR5K_INI_WRITE },
00161 { AR5K_BB_GAIN(33), 0x00000013, AR5K_INI_WRITE },
00162 { AR5K_BB_GAIN(34), 0x00000033, AR5K_INI_WRITE },
00163 { AR5K_BB_GAIN(35), 0x0000000b, AR5K_INI_WRITE },
00164 { AR5K_BB_GAIN(36), 0x0000002b, AR5K_INI_WRITE },
00165 { AR5K_BB_GAIN(37), 0x00000007, AR5K_INI_WRITE },
00166 { AR5K_BB_GAIN(38), 0x00000027, AR5K_INI_WRITE },
00167 { AR5K_BB_GAIN(39), 0x00000017, AR5K_INI_WRITE },
00168 { AR5K_BB_GAIN(40), 0x00000037, AR5K_INI_WRITE },
00169 { AR5K_BB_GAIN(41), 0x0000000f, AR5K_INI_WRITE },
00170 { AR5K_BB_GAIN(42), 0x0000002f, AR5K_INI_WRITE },
00171 { AR5K_BB_GAIN(43), 0x0000002f, AR5K_INI_WRITE },
00172 { AR5K_BB_GAIN(44), 0x0000002f, AR5K_INI_WRITE },
00173 { AR5K_BB_GAIN(45), 0x0000002f, AR5K_INI_WRITE },
00174 { AR5K_BB_GAIN(46), 0x0000002f, AR5K_INI_WRITE },
00175 { AR5K_BB_GAIN(47), 0x0000002f, AR5K_INI_WRITE },
00176 { AR5K_BB_GAIN(48), 0x0000002f, AR5K_INI_WRITE },
00177 { AR5K_BB_GAIN(49), 0x0000002f, AR5K_INI_WRITE },
00178 { AR5K_BB_GAIN(50), 0x0000002f, AR5K_INI_WRITE },
00179 { AR5K_BB_GAIN(51), 0x0000002f, AR5K_INI_WRITE },
00180 { AR5K_BB_GAIN(52), 0x0000002f, AR5K_INI_WRITE },
00181 { AR5K_BB_GAIN(53), 0x0000002f, AR5K_INI_WRITE },
00182 { AR5K_BB_GAIN(54), 0x0000002f, AR5K_INI_WRITE },
00183 { AR5K_BB_GAIN(55), 0x0000002f, AR5K_INI_WRITE },
00184 { AR5K_BB_GAIN(56), 0x0000002f, AR5K_INI_WRITE },
00185 { AR5K_BB_GAIN(57), 0x0000002f, AR5K_INI_WRITE },
00186 { AR5K_BB_GAIN(58), 0x0000002f, AR5K_INI_WRITE },
00187 { AR5K_BB_GAIN(59), 0x0000002f, AR5K_INI_WRITE },
00188 { AR5K_BB_GAIN(60), 0x0000002f, AR5K_INI_WRITE },
00189 { AR5K_BB_GAIN(61), 0x0000002f, AR5K_INI_WRITE },
00190 { AR5K_BB_GAIN(62), 0x0000002f, AR5K_INI_WRITE },
00191 { AR5K_BB_GAIN(63), 0x0000002f, AR5K_INI_WRITE },
00192
00193 { AR5K_RF_GAIN(0), 0x0000001d, AR5K_INI_WRITE },
00194 { AR5K_RF_GAIN(1), 0x0000005d, AR5K_INI_WRITE },
00195 { AR5K_RF_GAIN(2), 0x0000009d, AR5K_INI_WRITE },
00196 { AR5K_RF_GAIN(3), 0x000000dd, AR5K_INI_WRITE },
00197 { AR5K_RF_GAIN(4), 0x0000011d, AR5K_INI_WRITE },
00198 { AR5K_RF_GAIN(5), 0x00000021, AR5K_INI_WRITE },
00199 { AR5K_RF_GAIN(6), 0x00000061, AR5K_INI_WRITE },
00200 { AR5K_RF_GAIN(7), 0x000000a1, AR5K_INI_WRITE },
00201 { AR5K_RF_GAIN(8), 0x000000e1, AR5K_INI_WRITE },
00202 { AR5K_RF_GAIN(9), 0x00000031, AR5K_INI_WRITE },
00203 { AR5K_RF_GAIN(10), 0x00000071, AR5K_INI_WRITE },
00204 { AR5K_RF_GAIN(11), 0x000000b1, AR5K_INI_WRITE },
00205 { AR5K_RF_GAIN(12), 0x0000001c, AR5K_INI_WRITE },
00206 { AR5K_RF_GAIN(13), 0x0000005c, AR5K_INI_WRITE },
00207 { AR5K_RF_GAIN(14), 0x00000029, AR5K_INI_WRITE },
00208 { AR5K_RF_GAIN(15), 0x00000069, AR5K_INI_WRITE },
00209 { AR5K_RF_GAIN(16), 0x000000a9, AR5K_INI_WRITE },
00210 { AR5K_RF_GAIN(17), 0x00000020, AR5K_INI_WRITE },
00211 { AR5K_RF_GAIN(18), 0x00000019, AR5K_INI_WRITE },
00212 { AR5K_RF_GAIN(19), 0x00000059, AR5K_INI_WRITE },
00213 { AR5K_RF_GAIN(20), 0x00000099, AR5K_INI_WRITE },
00214 { AR5K_RF_GAIN(21), 0x00000030, AR5K_INI_WRITE },
00215 { AR5K_RF_GAIN(22), 0x00000005, AR5K_INI_WRITE },
00216 { AR5K_RF_GAIN(23), 0x00000025, AR5K_INI_WRITE },
00217 { AR5K_RF_GAIN(24), 0x00000065, AR5K_INI_WRITE },
00218 { AR5K_RF_GAIN(25), 0x000000a5, AR5K_INI_WRITE },
00219 { AR5K_RF_GAIN(26), 0x00000028, AR5K_INI_WRITE },
00220 { AR5K_RF_GAIN(27), 0x00000068, AR5K_INI_WRITE },
00221 { AR5K_RF_GAIN(28), 0x0000001f, AR5K_INI_WRITE },
00222 { AR5K_RF_GAIN(29), 0x0000001e, AR5K_INI_WRITE },
00223 { AR5K_RF_GAIN(30), 0x00000018, AR5K_INI_WRITE },
00224 { AR5K_RF_GAIN(31), 0x00000058, AR5K_INI_WRITE },
00225 { AR5K_RF_GAIN(32), 0x00000098, AR5K_INI_WRITE },
00226 { AR5K_RF_GAIN(33), 0x00000003, AR5K_INI_WRITE },
00227 { AR5K_RF_GAIN(34), 0x00000004, AR5K_INI_WRITE },
00228 { AR5K_RF_GAIN(35), 0x00000044, AR5K_INI_WRITE },
00229 { AR5K_RF_GAIN(36), 0x00000084, AR5K_INI_WRITE },
00230 { AR5K_RF_GAIN(37), 0x00000013, AR5K_INI_WRITE },
00231 { AR5K_RF_GAIN(38), 0x00000012, AR5K_INI_WRITE },
00232 { AR5K_RF_GAIN(39), 0x00000052, AR5K_INI_WRITE },
00233 { AR5K_RF_GAIN(40), 0x00000092, AR5K_INI_WRITE },
00234 { AR5K_RF_GAIN(41), 0x000000d2, AR5K_INI_WRITE },
00235 { AR5K_RF_GAIN(42), 0x0000002b, AR5K_INI_WRITE },
00236 { AR5K_RF_GAIN(43), 0x0000002a, AR5K_INI_WRITE },
00237 { AR5K_RF_GAIN(44), 0x0000006a, AR5K_INI_WRITE },
00238 { AR5K_RF_GAIN(45), 0x000000aa, AR5K_INI_WRITE },
00239 { AR5K_RF_GAIN(46), 0x0000001b, AR5K_INI_WRITE },
00240 { AR5K_RF_GAIN(47), 0x0000001a, AR5K_INI_WRITE },
00241 { AR5K_RF_GAIN(48), 0x0000005a, AR5K_INI_WRITE },
00242 { AR5K_RF_GAIN(49), 0x0000009a, AR5K_INI_WRITE },
00243 { AR5K_RF_GAIN(50), 0x000000da, AR5K_INI_WRITE },
00244 { AR5K_RF_GAIN(51), 0x00000006, AR5K_INI_WRITE },
00245 { AR5K_RF_GAIN(52), 0x00000006, AR5K_INI_WRITE },
00246 { AR5K_RF_GAIN(53), 0x00000006, AR5K_INI_WRITE },
00247 { AR5K_RF_GAIN(54), 0x00000006, AR5K_INI_WRITE },
00248 { AR5K_RF_GAIN(55), 0x00000006, AR5K_INI_WRITE },
00249 { AR5K_RF_GAIN(56), 0x00000006, AR5K_INI_WRITE },
00250 { AR5K_RF_GAIN(57), 0x00000006, AR5K_INI_WRITE },
00251 { AR5K_RF_GAIN(58), 0x00000006, AR5K_INI_WRITE },
00252 { AR5K_RF_GAIN(59), 0x00000006, AR5K_INI_WRITE },
00253 { AR5K_RF_GAIN(60), 0x00000006, AR5K_INI_WRITE },
00254 { AR5K_RF_GAIN(61), 0x00000006, AR5K_INI_WRITE },
00255 { AR5K_RF_GAIN(62), 0x00000006, AR5K_INI_WRITE },
00256 { AR5K_RF_GAIN(63), 0x00000006, AR5K_INI_WRITE },
00257
00258 { AR5K_PHY(53), 0x00000020, AR5K_INI_WRITE },
00259 { AR5K_PHY(51), 0x00000004, AR5K_INI_WRITE },
00260 { AR5K_PHY(50), 0x00060106, AR5K_INI_WRITE },
00261 { AR5K_PHY(39), 0x0000006d, AR5K_INI_WRITE },
00262 { AR5K_PHY(48), 0x00000000, AR5K_INI_WRITE },
00263 { AR5K_PHY(52), 0x00000014, AR5K_INI_WRITE },
00264 { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE, AR5K_INI_WRITE },
00265 };
00266
00267
00268 static const struct ath5k_ini ar5211_ini[] = {
00269 { AR5K_RXDP, 0x00000000, AR5K_INI_WRITE },
00270 { AR5K_RTSD0, 0x84849c9c, AR5K_INI_WRITE },
00271 { AR5K_RTSD1, 0x7c7c7c7c, AR5K_INI_WRITE },
00272 { AR5K_RXCFG, 0x00000005, AR5K_INI_WRITE },
00273 { AR5K_MIBC, 0x00000000, AR5K_INI_WRITE },
00274 { AR5K_TOPS, 0x00000008, AR5K_INI_WRITE },
00275 { AR5K_RXNOFRM, 0x00000008, AR5K_INI_WRITE },
00276 { AR5K_TXNOFRM, 0x00000010, AR5K_INI_WRITE },
00277 { AR5K_RPGTO, 0x00000000, AR5K_INI_WRITE },
00278 { AR5K_RFCNT, 0x0000001f, AR5K_INI_WRITE },
00279 { AR5K_QUEUE_TXDP(0), 0x00000000, AR5K_INI_WRITE },
00280 { AR5K_QUEUE_TXDP(1), 0x00000000, AR5K_INI_WRITE },
00281 { AR5K_QUEUE_TXDP(2), 0x00000000, AR5K_INI_WRITE },
00282 { AR5K_QUEUE_TXDP(3), 0x00000000, AR5K_INI_WRITE },
00283 { AR5K_QUEUE_TXDP(4), 0x00000000, AR5K_INI_WRITE },
00284 { AR5K_QUEUE_TXDP(5), 0x00000000, AR5K_INI_WRITE },
00285 { AR5K_QUEUE_TXDP(6), 0x00000000, AR5K_INI_WRITE },
00286 { AR5K_QUEUE_TXDP(7), 0x00000000, AR5K_INI_WRITE },
00287 { AR5K_QUEUE_TXDP(8), 0x00000000, AR5K_INI_WRITE },
00288 { AR5K_QUEUE_TXDP(9), 0x00000000, AR5K_INI_WRITE },
00289 { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
00290 { AR5K_STA_ID1, 0x00000000, AR5K_INI_WRITE },
00291 { AR5K_BSS_ID0, 0x00000000, AR5K_INI_WRITE },
00292 { AR5K_BSS_ID1, 0x00000000, AR5K_INI_WRITE },
00293 { AR5K_RSSI_THR, 0x00000000, AR5K_INI_WRITE },
00294 { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE },
00295 { AR5K_TIMER0_5211, 0x00000030, AR5K_INI_WRITE },
00296 { AR5K_TIMER1_5211, 0x0007ffff, AR5K_INI_WRITE },
00297 { AR5K_TIMER2_5211, 0x01ffffff, AR5K_INI_WRITE },
00298 { AR5K_TIMER3_5211, 0x00000031, AR5K_INI_WRITE },
00299 { AR5K_CFP_DUR_5211, 0x00000000, AR5K_INI_WRITE },
00300 { AR5K_RX_FILTER_5211, 0x00000000, AR5K_INI_WRITE },
00301 { AR5K_MCAST_FILTER0_5211, 0x00000000, AR5K_INI_WRITE },
00302 { AR5K_MCAST_FILTER1_5211, 0x00000002, AR5K_INI_WRITE },
00303 { AR5K_DIAG_SW_5211, 0x00000000, AR5K_INI_WRITE },
00304 { AR5K_ADDAC_TEST, 0x00000000, AR5K_INI_WRITE },
00305 { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE },
00306
00307 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
00308 { AR5K_PHY(3), 0x2d849093, AR5K_INI_WRITE },
00309 { AR5K_PHY(4), 0x7d32e000, AR5K_INI_WRITE },
00310 { AR5K_PHY(5), 0x00000f6b, AR5K_INI_WRITE },
00311 { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE },
00312 { AR5K_PHY(11), 0x00026ffe, AR5K_INI_WRITE },
00313 { AR5K_PHY(12), 0x00000000, AR5K_INI_WRITE },
00314 { AR5K_PHY(15), 0x00020100, AR5K_INI_WRITE },
00315 { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE },
00316 { AR5K_PHY(19), 0x1284613c, AR5K_INI_WRITE },
00317 { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE },
00318 { AR5K_PHY(26), 0x409a4190, AR5K_INI_WRITE },
00319 { AR5K_PHY(27), 0x050cb081, AR5K_INI_WRITE },
00320 { AR5K_PHY(28), 0x0000000f, AR5K_INI_WRITE },
00321 { AR5K_PHY(29), 0x00000080, AR5K_INI_WRITE },
00322 { AR5K_PHY(30), 0x0000000c, AR5K_INI_WRITE },
00323 { AR5K_PHY(64), 0x00000000, AR5K_INI_WRITE },
00324 { AR5K_PHY(65), 0x00000000, AR5K_INI_WRITE },
00325 { AR5K_PHY(66), 0x00000000, AR5K_INI_WRITE },
00326 { AR5K_PHY(67), 0x00800000, AR5K_INI_WRITE },
00327 { AR5K_PHY(68), 0x00000001, AR5K_INI_WRITE },
00328 { AR5K_PHY(71), 0x0000092a, AR5K_INI_WRITE },
00329 { AR5K_PHY_IQ, 0x00000000, AR5K_INI_WRITE },
00330 { AR5K_PHY(73), 0x00058a05, AR5K_INI_WRITE },
00331 { AR5K_PHY(74), 0x00000001, AR5K_INI_WRITE },
00332 { AR5K_PHY(75), 0x00000000, AR5K_INI_WRITE },
00333 { AR5K_PHY_PAPD_PROBE, 0x00000000, AR5K_INI_WRITE },
00334 { AR5K_PHY(77), 0x00000000, AR5K_INI_WRITE },
00335 { AR5K_PHY(78), 0x00000000, AR5K_INI_WRITE },
00336 { AR5K_PHY(79), 0x0000003f, AR5K_INI_WRITE },
00337 { AR5K_PHY(80), 0x00000004, AR5K_INI_WRITE },
00338 { AR5K_PHY(82), 0x00000000, AR5K_INI_WRITE },
00339 { AR5K_PHY(83), 0x00000000, AR5K_INI_WRITE },
00340 { AR5K_PHY(84), 0x00000000, AR5K_INI_WRITE },
00341 { AR5K_PHY_RADAR, 0x5d50f14c, AR5K_INI_WRITE },
00342 { AR5K_PHY(86), 0x00000018, AR5K_INI_WRITE },
00343 { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE },
00344
00345
00346
00347
00348
00349 { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff, AR5K_INI_WRITE },
00350 { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff, AR5K_INI_WRITE },
00351 { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff, AR5K_INI_WRITE },
00352 { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff, AR5K_INI_WRITE },
00353 { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff, AR5K_INI_WRITE },
00354 { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff, AR5K_INI_WRITE },
00355 { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff, AR5K_INI_WRITE },
00356 { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff, AR5K_INI_WRITE },
00357 { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff, AR5K_INI_WRITE },
00358 { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff, AR5K_INI_WRITE },
00359 { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff, AR5K_INI_WRITE },
00360 { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff, AR5K_INI_WRITE },
00361 { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff, AR5K_INI_WRITE },
00362 { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff, AR5K_INI_WRITE },
00363 { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff, AR5K_INI_WRITE },
00364 { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff, AR5K_INI_WRITE },
00365 { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff, AR5K_INI_WRITE },
00366 { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff, AR5K_INI_WRITE },
00367 { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff, AR5K_INI_WRITE },
00368 { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff, AR5K_INI_WRITE },
00369 { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff, AR5K_INI_WRITE },
00370 { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff, AR5K_INI_WRITE },
00371 { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff, AR5K_INI_WRITE },
00372 { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff, AR5K_INI_WRITE },
00373 { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff, AR5K_INI_WRITE },
00374 { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff, AR5K_INI_WRITE },
00375 { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff, AR5K_INI_WRITE },
00376 { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff, AR5K_INI_WRITE },
00377 { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff, AR5K_INI_WRITE },
00378 { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff, AR5K_INI_WRITE },
00379 { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff, AR5K_INI_WRITE },
00380 { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE },
00381 { AR5K_PHY(642), 0x503e4646, AR5K_INI_WRITE },
00382 { AR5K_PHY_GAIN_2GHZ, 0x6480416c, AR5K_INI_WRITE },
00383 { AR5K_PHY(644), 0x0199a003, AR5K_INI_WRITE },
00384 { AR5K_PHY(645), 0x044cd610, AR5K_INI_WRITE },
00385 { AR5K_PHY(646), 0x13800040, AR5K_INI_WRITE },
00386 { AR5K_PHY(647), 0x1be00060, AR5K_INI_WRITE },
00387 { AR5K_PHY(648), 0x0c53800a, AR5K_INI_WRITE },
00388 { AR5K_PHY(649), 0x0014df3b, AR5K_INI_WRITE },
00389 { AR5K_PHY(650), 0x000001b5, AR5K_INI_WRITE },
00390 { AR5K_PHY(651), 0x00000020, AR5K_INI_WRITE },
00391 };
00392
00393
00394
00395
00396
00397 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
00398 { AR5K_TXCFG,
00399
00400 { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
00401 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
00402 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00403 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
00404 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00405 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
00406 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00407 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
00408 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00409 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
00410 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00411 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
00412 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00413 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
00414 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00415 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
00416 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00417 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
00418 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00419 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
00420 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
00421 { AR5K_DCU_GBL_IFS_SLOT,
00422 { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
00423 { AR5K_DCU_GBL_IFS_SIFS,
00424 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
00425 { AR5K_DCU_GBL_IFS_EIFS,
00426 { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
00427 { AR5K_DCU_GBL_IFS_MISC,
00428 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
00429 { AR5K_TIME_OUT,
00430 { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
00431 { AR5K_USEC_5211,
00432 { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
00433 { AR5K_PHY_TURBO,
00434 { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
00435 { AR5K_PHY(8),
00436 { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
00437 { AR5K_PHY(9),
00438 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
00439 { AR5K_PHY(10),
00440 { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
00441 { AR5K_PHY(13),
00442 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00443 { AR5K_PHY(14),
00444 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
00445 { AR5K_PHY(17),
00446 { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
00447 { AR5K_PHY(18),
00448 { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
00449 { AR5K_PHY(20),
00450 { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
00451 { AR5K_PHY_SIG,
00452 { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
00453 { AR5K_PHY_AGCCOARSE,
00454 { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
00455 { AR5K_PHY_AGCCTL,
00456 { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
00457 { AR5K_PHY_NF,
00458 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
00459 { AR5K_PHY_RX_DELAY,
00460 { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
00461 { AR5K_PHY(70),
00462 { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
00463 { AR5K_PHY_FRAME_CTL_5211,
00464 { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
00465 { AR5K_PHY_PCDAC_TXPOWER_BASE,
00466 { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
00467 { AR5K_RF_BUFFER_CONTROL_4,
00468 { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
00469 };
00470
00471
00472 static const struct ath5k_ini ar5212_ini_common_start[] = {
00473 { AR5K_RXDP, 0x00000000, AR5K_INI_WRITE },
00474 { AR5K_RXCFG, 0x00000005, AR5K_INI_WRITE },
00475 { AR5K_MIBC, 0x00000000, AR5K_INI_WRITE },
00476 { AR5K_TOPS, 0x00000008, AR5K_INI_WRITE },
00477 { AR5K_RXNOFRM, 0x00000008, AR5K_INI_WRITE },
00478 { AR5K_TXNOFRM, 0x00000010, AR5K_INI_WRITE },
00479 { AR5K_RPGTO, 0x00000000, AR5K_INI_WRITE },
00480 { AR5K_RFCNT, 0x0000001f, AR5K_INI_WRITE },
00481 { AR5K_QUEUE_TXDP(0), 0x00000000, AR5K_INI_WRITE },
00482 { AR5K_QUEUE_TXDP(1), 0x00000000, AR5K_INI_WRITE },
00483 { AR5K_QUEUE_TXDP(2), 0x00000000, AR5K_INI_WRITE },
00484 { AR5K_QUEUE_TXDP(3), 0x00000000, AR5K_INI_WRITE },
00485 { AR5K_QUEUE_TXDP(4), 0x00000000, AR5K_INI_WRITE },
00486 { AR5K_QUEUE_TXDP(5), 0x00000000, AR5K_INI_WRITE },
00487 { AR5K_QUEUE_TXDP(6), 0x00000000, AR5K_INI_WRITE },
00488 { AR5K_QUEUE_TXDP(7), 0x00000000, AR5K_INI_WRITE },
00489 { AR5K_QUEUE_TXDP(8), 0x00000000, AR5K_INI_WRITE },
00490 { AR5K_QUEUE_TXDP(9), 0x00000000, AR5K_INI_WRITE },
00491 { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
00492 { AR5K_DCU_TXP, 0x00000000, AR5K_INI_WRITE },
00493
00494 { AR5K_DCU_TX_FILTER_0(0), 0x00000000, AR5K_INI_WRITE },
00495 { AR5K_DCU_TX_FILTER_0(1), 0x00000000, AR5K_INI_WRITE },
00496 { AR5K_DCU_TX_FILTER_0(2), 0x00000000, AR5K_INI_WRITE },
00497 { AR5K_DCU_TX_FILTER_0(3), 0x00000000, AR5K_INI_WRITE },
00498 { AR5K_DCU_TX_FILTER_0(4), 0x00000000, AR5K_INI_WRITE },
00499 { AR5K_DCU_TX_FILTER_0(5), 0x00000000, AR5K_INI_WRITE },
00500 { AR5K_DCU_TX_FILTER_0(6), 0x00000000, AR5K_INI_WRITE },
00501 { AR5K_DCU_TX_FILTER_0(7), 0x00000000, AR5K_INI_WRITE },
00502 { AR5K_DCU_TX_FILTER_0(8), 0x00000000, AR5K_INI_WRITE },
00503 { AR5K_DCU_TX_FILTER_0(9), 0x00000000, AR5K_INI_WRITE },
00504 { AR5K_DCU_TX_FILTER_0(10), 0x00000000, AR5K_INI_WRITE },
00505 { AR5K_DCU_TX_FILTER_0(11), 0x00000000, AR5K_INI_WRITE },
00506 { AR5K_DCU_TX_FILTER_0(12), 0x00000000, AR5K_INI_WRITE },
00507 { AR5K_DCU_TX_FILTER_0(13), 0x00000000, AR5K_INI_WRITE },
00508 { AR5K_DCU_TX_FILTER_0(14), 0x00000000, AR5K_INI_WRITE },
00509 { AR5K_DCU_TX_FILTER_0(15), 0x00000000, AR5K_INI_WRITE },
00510 { AR5K_DCU_TX_FILTER_0(16), 0x00000000, AR5K_INI_WRITE },
00511 { AR5K_DCU_TX_FILTER_0(17), 0x00000000, AR5K_INI_WRITE },
00512 { AR5K_DCU_TX_FILTER_0(18), 0x00000000, AR5K_INI_WRITE },
00513 { AR5K_DCU_TX_FILTER_0(19), 0x00000000, AR5K_INI_WRITE },
00514 { AR5K_DCU_TX_FILTER_0(20), 0x00000000, AR5K_INI_WRITE },
00515 { AR5K_DCU_TX_FILTER_0(21), 0x00000000, AR5K_INI_WRITE },
00516 { AR5K_DCU_TX_FILTER_0(22), 0x00000000, AR5K_INI_WRITE },
00517 { AR5K_DCU_TX_FILTER_0(23), 0x00000000, AR5K_INI_WRITE },
00518 { AR5K_DCU_TX_FILTER_0(24), 0x00000000, AR5K_INI_WRITE },
00519 { AR5K_DCU_TX_FILTER_0(25), 0x00000000, AR5K_INI_WRITE },
00520 { AR5K_DCU_TX_FILTER_0(26), 0x00000000, AR5K_INI_WRITE },
00521 { AR5K_DCU_TX_FILTER_0(27), 0x00000000, AR5K_INI_WRITE },
00522 { AR5K_DCU_TX_FILTER_0(28), 0x00000000, AR5K_INI_WRITE },
00523 { AR5K_DCU_TX_FILTER_0(29), 0x00000000, AR5K_INI_WRITE },
00524 { AR5K_DCU_TX_FILTER_0(30), 0x00000000, AR5K_INI_WRITE },
00525 { AR5K_DCU_TX_FILTER_0(31), 0x00000000, AR5K_INI_WRITE },
00526
00527 { AR5K_DCU_TX_FILTER_1(0), 0x00000000, AR5K_INI_WRITE },
00528 { AR5K_DCU_TX_FILTER_1(1), 0x00000000, AR5K_INI_WRITE },
00529 { AR5K_DCU_TX_FILTER_1(2), 0x00000000, AR5K_INI_WRITE },
00530 { AR5K_DCU_TX_FILTER_1(3), 0x00000000, AR5K_INI_WRITE },
00531 { AR5K_DCU_TX_FILTER_1(4), 0x00000000, AR5K_INI_WRITE },
00532 { AR5K_DCU_TX_FILTER_1(5), 0x00000000, AR5K_INI_WRITE },
00533 { AR5K_DCU_TX_FILTER_1(6), 0x00000000, AR5K_INI_WRITE },
00534 { AR5K_DCU_TX_FILTER_1(7), 0x00000000, AR5K_INI_WRITE },
00535 { AR5K_DCU_TX_FILTER_1(8), 0x00000000, AR5K_INI_WRITE },
00536 { AR5K_DCU_TX_FILTER_1(9), 0x00000000, AR5K_INI_WRITE },
00537 { AR5K_DCU_TX_FILTER_1(10), 0x00000000, AR5K_INI_WRITE },
00538 { AR5K_DCU_TX_FILTER_1(11), 0x00000000, AR5K_INI_WRITE },
00539 { AR5K_DCU_TX_FILTER_1(12), 0x00000000, AR5K_INI_WRITE },
00540 { AR5K_DCU_TX_FILTER_1(13), 0x00000000, AR5K_INI_WRITE },
00541 { AR5K_DCU_TX_FILTER_1(14), 0x00000000, AR5K_INI_WRITE },
00542 { AR5K_DCU_TX_FILTER_1(15), 0x00000000, AR5K_INI_WRITE },
00543 { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE },
00544 { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE },
00545 { AR5K_DCU_TX_FILTER_CLR, 0x00000000, AR5K_INI_WRITE },
00546 { AR5K_DCU_TX_FILTER_SET, 0x00000000, AR5K_INI_WRITE },
00547 { AR5K_STA_ID1, 0x00000000, AR5K_INI_WRITE },
00548 { AR5K_BSS_ID0, 0x00000000, AR5K_INI_WRITE },
00549 { AR5K_BSS_ID1, 0x00000000, AR5K_INI_WRITE },
00550 { AR5K_BEACON_5211, 0x00000000, AR5K_INI_WRITE },
00551 { AR5K_CFP_PERIOD_5211, 0x00000000, AR5K_INI_WRITE },
00552 { AR5K_TIMER0_5211, 0x00000030, AR5K_INI_WRITE },
00553 { AR5K_TIMER1_5211, 0x0007ffff, AR5K_INI_WRITE },
00554 { AR5K_TIMER2_5211, 0x01ffffff, AR5K_INI_WRITE },
00555 { AR5K_TIMER3_5211, 0x00000031, AR5K_INI_WRITE },
00556 { AR5K_CFP_DUR_5211, 0x00000000, AR5K_INI_WRITE },
00557 { AR5K_RX_FILTER_5211, 0x00000000, AR5K_INI_WRITE },
00558 { AR5K_DIAG_SW_5211, 0x00000000, AR5K_INI_WRITE },
00559 { AR5K_ADDAC_TEST, 0x00000000, AR5K_INI_WRITE },
00560 { AR5K_DEFAULT_ANTENNA, 0x00000000, AR5K_INI_WRITE },
00561 { AR5K_FRAME_CTL_QOSM, 0x000fc78f, AR5K_INI_WRITE },
00562 { AR5K_XRMODE, 0x2a82301a, AR5K_INI_WRITE },
00563 { AR5K_XRDELAY, 0x05dc01e0, AR5K_INI_WRITE },
00564 { AR5K_XRTIMEOUT, 0x1f402710, AR5K_INI_WRITE },
00565 { AR5K_XRCHIRP, 0x01f40000, AR5K_INI_WRITE },
00566 { AR5K_XRSTOMP, 0x00001e1c, AR5K_INI_WRITE },
00567 { AR5K_SLEEP0, 0x0002aaaa, AR5K_INI_WRITE },
00568 { AR5K_SLEEP1, 0x02005555, AR5K_INI_WRITE },
00569 { AR5K_SLEEP2, 0x00000000, AR5K_INI_WRITE },
00570 { AR5K_BSS_IDM0, 0xffffffff, AR5K_INI_WRITE },
00571 { AR5K_BSS_IDM1, 0x0000ffff, AR5K_INI_WRITE },
00572 { AR5K_TXPC, 0x00000000, AR5K_INI_WRITE },
00573 { AR5K_PROFCNT_TX, 0x00000000, AR5K_INI_WRITE },
00574 { AR5K_PROFCNT_RX, 0x00000000, AR5K_INI_WRITE },
00575 { AR5K_PROFCNT_RXCLR, 0x00000000, AR5K_INI_WRITE },
00576 { AR5K_PROFCNT_CYCLE, 0x00000000, AR5K_INI_WRITE },
00577 { AR5K_QUIET_CTL1, 0x00000088, AR5K_INI_WRITE },
00578
00579 { AR5K_RATE_DUR(0), 0x00000000, AR5K_INI_WRITE },
00580 { AR5K_RATE_DUR(1), 0x0000008c, AR5K_INI_WRITE },
00581 { AR5K_RATE_DUR(2), 0x000000e4, AR5K_INI_WRITE },
00582 { AR5K_RATE_DUR(3), 0x000002d5, AR5K_INI_WRITE },
00583 { AR5K_RATE_DUR(4), 0x00000000, AR5K_INI_WRITE },
00584 { AR5K_RATE_DUR(5), 0x00000000, AR5K_INI_WRITE },
00585 { AR5K_RATE_DUR(6), 0x000000a0, AR5K_INI_WRITE },
00586 { AR5K_RATE_DUR(7), 0x000001c9, AR5K_INI_WRITE },
00587 { AR5K_RATE_DUR(8), 0x0000002c, AR5K_INI_WRITE },
00588 { AR5K_RATE_DUR(9), 0x0000002c, AR5K_INI_WRITE },
00589 { AR5K_RATE_DUR(10), 0x00000030, AR5K_INI_WRITE },
00590 { AR5K_RATE_DUR(11), 0x0000003c, AR5K_INI_WRITE },
00591 { AR5K_RATE_DUR(12), 0x0000002c, AR5K_INI_WRITE },
00592 { AR5K_RATE_DUR(13), 0x0000002c, AR5K_INI_WRITE },
00593 { AR5K_RATE_DUR(14), 0x00000030, AR5K_INI_WRITE },
00594 { AR5K_RATE_DUR(15), 0x0000003c, AR5K_INI_WRITE },
00595 { AR5K_RATE_DUR(16), 0x00000000, AR5K_INI_WRITE },
00596 { AR5K_RATE_DUR(17), 0x00000000, AR5K_INI_WRITE },
00597 { AR5K_RATE_DUR(18), 0x00000000, AR5K_INI_WRITE },
00598 { AR5K_RATE_DUR(19), 0x00000000, AR5K_INI_WRITE },
00599 { AR5K_RATE_DUR(20), 0x00000000, AR5K_INI_WRITE },
00600 { AR5K_RATE_DUR(21), 0x00000000, AR5K_INI_WRITE },
00601 { AR5K_RATE_DUR(22), 0x00000000, AR5K_INI_WRITE },
00602 { AR5K_RATE_DUR(23), 0x00000000, AR5K_INI_WRITE },
00603 { AR5K_RATE_DUR(24), 0x000000d5, AR5K_INI_WRITE },
00604 { AR5K_RATE_DUR(25), 0x000000df, AR5K_INI_WRITE },
00605 { AR5K_RATE_DUR(26), 0x00000102, AR5K_INI_WRITE },
00606 { AR5K_RATE_DUR(27), 0x0000013a, AR5K_INI_WRITE },
00607 { AR5K_RATE_DUR(28), 0x00000075, AR5K_INI_WRITE },
00608 { AR5K_RATE_DUR(29), 0x0000007f, AR5K_INI_WRITE },
00609 { AR5K_RATE_DUR(30), 0x000000a2, AR5K_INI_WRITE },
00610 { AR5K_RATE_DUR(31), 0x00000000, AR5K_INI_WRITE },
00611 { AR5K_QUIET_CTL2, 0x00010002, AR5K_INI_WRITE },
00612 { AR5K_TSF_PARM, 0x00000001, AR5K_INI_WRITE },
00613 { AR5K_QOS_NOACK, 0x000000c0, AR5K_INI_WRITE },
00614 { AR5K_PHY_ERR_FIL, 0x00000000, AR5K_INI_WRITE },
00615 { AR5K_XRLAT_TX, 0x00000168, AR5K_INI_WRITE },
00616 { AR5K_ACKSIFS, 0x00000000, AR5K_INI_WRITE },
00617
00618
00619 { AR5K_RATE2DB(0), 0x03020100, AR5K_INI_WRITE },
00620 { AR5K_RATE2DB(1), 0x07060504, AR5K_INI_WRITE },
00621 { AR5K_RATE2DB(2), 0x0b0a0908, AR5K_INI_WRITE },
00622 { AR5K_RATE2DB(3), 0x0f0e0d0c, AR5K_INI_WRITE },
00623 { AR5K_RATE2DB(4), 0x13121110, AR5K_INI_WRITE },
00624 { AR5K_RATE2DB(5), 0x17161514, AR5K_INI_WRITE },
00625 { AR5K_RATE2DB(6), 0x1b1a1918, AR5K_INI_WRITE },
00626 { AR5K_RATE2DB(7), 0x1f1e1d1c, AR5K_INI_WRITE },
00627
00628 { AR5K_DB2RATE(0), 0x03020100, AR5K_INI_WRITE },
00629 { AR5K_DB2RATE(1), 0x07060504, AR5K_INI_WRITE },
00630 { AR5K_DB2RATE(2), 0x0b0a0908, AR5K_INI_WRITE },
00631 { AR5K_DB2RATE(3), 0x0f0e0d0c, AR5K_INI_WRITE },
00632 { AR5K_DB2RATE(4), 0x13121110, AR5K_INI_WRITE },
00633 { AR5K_DB2RATE(5), 0x17161514, AR5K_INI_WRITE },
00634 { AR5K_DB2RATE(6), 0x1b1a1918, AR5K_INI_WRITE },
00635 { AR5K_DB2RATE(7), 0x1f1e1d1c, AR5K_INI_WRITE },
00636
00637
00638 { AR5K_PHY(3), 0xad848e19, AR5K_INI_WRITE },
00639 { AR5K_PHY(4), 0x7d28e000, AR5K_INI_WRITE },
00640 { AR5K_PHY_TIMING_3, 0x9c0a9f6b, AR5K_INI_WRITE },
00641 { AR5K_PHY_ACT, 0x00000000, AR5K_INI_WRITE },
00642 { AR5K_PHY(16), 0x206a017a, AR5K_INI_WRITE },
00643 { AR5K_PHY(21), 0x00000859, AR5K_INI_WRITE },
00644 { AR5K_PHY_BIN_MASK_1, 0x00000000, AR5K_INI_WRITE },
00645 { AR5K_PHY_BIN_MASK_2, 0x00000000, AR5K_INI_WRITE },
00646 { AR5K_PHY_BIN_MASK_3, 0x00000000, AR5K_INI_WRITE },
00647 { AR5K_PHY_BIN_MASK_CTL, 0x00800000, AR5K_INI_WRITE },
00648 { AR5K_PHY_ANT_CTL, 0x00000001, AR5K_INI_WRITE },
00649
00650 { AR5K_PHY_MAX_RX_LEN, 0x00000c80, AR5K_INI_WRITE },
00651 { AR5K_PHY_IQ, 0x05100000, AR5K_INI_WRITE },
00652 { AR5K_PHY_WARM_RESET, 0x00000001, AR5K_INI_WRITE },
00653 { AR5K_PHY_CTL, 0x00000004, AR5K_INI_WRITE },
00654 { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022, AR5K_INI_WRITE },
00655 { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d, AR5K_INI_WRITE },
00656 { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f, AR5K_INI_WRITE },
00657 { AR5K_PHY(82), 0x9280b212, AR5K_INI_WRITE },
00658 { AR5K_PHY_RADAR, 0x5d50e188, AR5K_INI_WRITE },
00659
00660 { AR5K_PHY(87), 0x004b6a8e, AR5K_INI_WRITE },
00661 { AR5K_PHY_NFTHRES, 0x000003ce, AR5K_INI_WRITE },
00662 { AR5K_PHY_RESTART, 0x192fb515, AR5K_INI_WRITE },
00663 { AR5K_PHY(94), 0x00000001, AR5K_INI_WRITE },
00664 { AR5K_PHY_RFBUS_REQ, 0x00000000, AR5K_INI_WRITE },
00665
00666
00667 { AR5K_PHY(644), 0x00806333, AR5K_INI_WRITE },
00668 { AR5K_PHY(645), 0x00106c10, AR5K_INI_WRITE },
00669 { AR5K_PHY(646), 0x009c4060, AR5K_INI_WRITE },
00670
00671
00672 { AR5K_PHY(648), 0x018830c6, AR5K_INI_WRITE },
00673 { AR5K_PHY(649), 0x00000400, AR5K_INI_WRITE },
00674
00675 { AR5K_PHY(651), 0x00000000, AR5K_INI_WRITE },
00676 { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE },
00677 { AR5K_PHY_TXPOWER_RATE2, 0x20202020, AR5K_INI_WRITE },
00678
00679 { AR5K_PHY(656), 0x38490a20, AR5K_INI_WRITE },
00680 { AR5K_PHY(657), 0x00007bb6, AR5K_INI_WRITE },
00681 { AR5K_PHY(658), 0x0fff3ffc, AR5K_INI_WRITE },
00682 };
00683
00684
00685 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
00686 { AR5K_QUEUE_DFS_LOCAL_IFS(0),
00687
00688 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00689 { AR5K_QUEUE_DFS_LOCAL_IFS(1),
00690 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00691 { AR5K_QUEUE_DFS_LOCAL_IFS(2),
00692 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00693 { AR5K_QUEUE_DFS_LOCAL_IFS(3),
00694 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00695 { AR5K_QUEUE_DFS_LOCAL_IFS(4),
00696 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00697 { AR5K_QUEUE_DFS_LOCAL_IFS(5),
00698 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00699 { AR5K_QUEUE_DFS_LOCAL_IFS(6),
00700 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00701 { AR5K_QUEUE_DFS_LOCAL_IFS(7),
00702 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00703 { AR5K_QUEUE_DFS_LOCAL_IFS(8),
00704 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00705 { AR5K_QUEUE_DFS_LOCAL_IFS(9),
00706 { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
00707 { AR5K_DCU_GBL_IFS_SIFS,
00708 { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
00709 { AR5K_DCU_GBL_IFS_SLOT,
00710 { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
00711 { AR5K_DCU_GBL_IFS_EIFS,
00712 { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
00713 { AR5K_DCU_GBL_IFS_MISC,
00714 { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
00715 { AR5K_TIME_OUT,
00716 { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
00717 { AR5K_PHY_TURBO,
00718 { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
00719 { AR5K_PHY(8),
00720 { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
00721 { AR5K_PHY_RF_CTL2,
00722 { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
00723 { AR5K_PHY_SETTLING,
00724 { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
00725 { AR5K_PHY_AGCCTL,
00726 { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } },
00727 { AR5K_PHY_NF,
00728 { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
00729 { AR5K_PHY_WEAK_OFDM_HIGH_THR,
00730 { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
00731 { AR5K_PHY(70),
00732 { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
00733 { AR5K_PHY_OFDM_SELFCORR,
00734 { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
00735 { 0xa230,
00736 { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
00737 };
00738
00739
00740 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
00741 { AR5K_TXCFG,
00742
00743 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
00744 { AR5K_USEC_5211,
00745 { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
00746 { AR5K_PHY_RF_CTL3,
00747 { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
00748 { AR5K_PHY_RF_CTL4,
00749 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00750 { AR5K_PHY_PA_CTL,
00751 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00752 { AR5K_PHY_GAIN,
00753 { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
00754 { AR5K_PHY_DESIRED_SIZE,
00755 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
00756 { AR5K_PHY_SIG,
00757 { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
00758 { AR5K_PHY_AGCCOARSE,
00759 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
00760 { AR5K_PHY_WEAK_OFDM_LOW_THR,
00761 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
00762 { AR5K_PHY_RX_DELAY,
00763 { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
00764 { AR5K_PHY_FRAME_CTL_5211,
00765 { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
00766 { AR5K_PHY_GAIN_2GHZ,
00767 { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
00768 { AR5K_PHY_CCK_RX_CTL_4,
00769 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
00770 };
00771
00772 static const struct ath5k_ini rf5111_ini_common_end[] = {
00773 { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
00774 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
00775 { AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE },
00776 { 0x983c, 0x00020100, AR5K_INI_WRITE },
00777 { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
00778 { AR5K_PHY_PAPD_PROBE, 0x00004883, AR5K_INI_WRITE },
00779 { 0x9940, 0x00000004, AR5K_INI_WRITE },
00780 { 0x9958, 0x000000ff, AR5K_INI_WRITE },
00781 { 0x9974, 0x00000000, AR5K_INI_WRITE },
00782 { AR5K_PHY_SPENDING, 0x00000018, AR5K_INI_WRITE },
00783 { AR5K_PHY_CCKTXCTL, 0x00000000, AR5K_INI_WRITE },
00784 { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788, AR5K_INI_WRITE },
00785 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
00786 { 0xa23c, 0x13c889af, AR5K_INI_WRITE },
00787 };
00788
00789
00790 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
00791 { AR5K_TXCFG,
00792
00793 { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
00794 { AR5K_USEC_5211,
00795 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
00796 { AR5K_PHY_RF_CTL3,
00797 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
00798 { AR5K_PHY_RF_CTL4,
00799 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00800 { AR5K_PHY_PA_CTL,
00801 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00802 { AR5K_PHY_GAIN,
00803 { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
00804 { AR5K_PHY_DESIRED_SIZE,
00805 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
00806 { AR5K_PHY_SIG,
00807 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } },
00808 { AR5K_PHY_AGCCOARSE,
00809 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
00810 { AR5K_PHY_WEAK_OFDM_LOW_THR,
00811 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
00812 { AR5K_PHY_RX_DELAY,
00813 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
00814 { AR5K_PHY_FRAME_CTL_5211,
00815 { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
00816 { AR5K_PHY_CCKTXCTL,
00817 { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
00818 { AR5K_PHY_CCK_CROSSCORR,
00819 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
00820 { AR5K_PHY_GAIN_2GHZ,
00821 { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
00822 { AR5K_PHY_CCK_RX_CTL_4,
00823 { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
00824 };
00825
00826 static const struct ath5k_ini rf5112_ini_common_end[] = {
00827 { AR5K_DCU_FP, 0x00000000, AR5K_INI_WRITE },
00828 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
00829 { AR5K_PHY_ADC_CTL, 0x00022ffe, AR5K_INI_WRITE },
00830 { 0x983c, 0x00020100, AR5K_INI_WRITE },
00831 { AR5K_PHY_GAIN_OFFSET, 0x1284613c, AR5K_INI_WRITE },
00832 { AR5K_PHY_PAPD_PROBE, 0x00004882, AR5K_INI_WRITE },
00833 { 0x9940, 0x00000004, AR5K_INI_WRITE },
00834 { 0x9958, 0x000000ff, AR5K_INI_WRITE },
00835 { 0x9974, 0x00000000, AR5K_INI_WRITE },
00836 { AR5K_PHY_DAG_CCK_CTL, 0x000001b5, AR5K_INI_WRITE },
00837 { 0xa23c, 0x13c889af, AR5K_INI_WRITE },
00838 };
00839
00840
00841 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
00842 { AR5K_TXCFG,
00843
00844 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
00845 { AR5K_USEC_5211,
00846 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
00847 { AR5K_PHY_RF_CTL3,
00848 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
00849 { AR5K_PHY_RF_CTL4,
00850 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
00851 { AR5K_PHY_PA_CTL,
00852 { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
00853 { AR5K_PHY_GAIN,
00854 { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
00855 { AR5K_PHY_DESIRED_SIZE,
00856 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
00857 { AR5K_PHY_SIG,
00858 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
00859 { AR5K_PHY_AGCCOARSE,
00860 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
00861 { AR5K_PHY_WEAK_OFDM_LOW_THR,
00862 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
00863 { AR5K_PHY_RX_DELAY,
00864 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
00865 { AR5K_PHY_FRAME_CTL_5211,
00866 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
00867 { AR5K_PHY_CCKTXCTL,
00868 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
00869 { AR5K_PHY_CCK_CROSSCORR,
00870 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
00871 { AR5K_PHY_GAIN_2GHZ,
00872 { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
00873 { AR5K_PHY_CCK_RX_CTL_4,
00874 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
00875 { 0xa300,
00876 { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
00877 { 0xa304,
00878 { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
00879 { 0xa308,
00880 { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
00881 { 0xa30c,
00882 { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
00883 { 0xa310,
00884 { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
00885 { 0xa314,
00886 { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
00887 { 0xa318,
00888 { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
00889 { 0xa31c,
00890 { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
00891 { 0xa320,
00892 { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
00893 { 0xa324,
00894 { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
00895 { 0xa328,
00896 { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
00897 { 0xa32c,
00898 { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
00899 { 0xa330,
00900 { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
00901 { 0xa334,
00902 { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
00903 };
00904
00905 static const struct ath5k_ini rf5413_ini_common_end[] = {
00906 { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
00907 { AR5K_5414_CBCFG, 0x00000010, AR5K_INI_WRITE },
00908 { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
00909 { 0x809c, 0x00000000, AR5K_INI_WRITE },
00910 { 0x80a0, 0x00000000, AR5K_INI_WRITE },
00911 { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
00912 { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
00913 { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
00914 { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
00915 { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
00916 { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
00917 { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
00918 { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
00919 { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
00920 { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
00921 { 0x8140, 0x800003f9, AR5K_INI_WRITE },
00922 { 0x8144, 0x00000000, AR5K_INI_WRITE },
00923 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
00924 { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
00925 { 0x983c, 0x00200400, AR5K_INI_WRITE },
00926 { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
00927 { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
00928 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
00929 { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
00930 { 0x9958, 0x00081fff, AR5K_INI_WRITE },
00931 { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
00932 { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
00933 { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
00934 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
00935 { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
00936 { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
00937 { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
00938 { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
00939 { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
00940 { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
00941 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
00942 { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
00943 { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
00944 { 0xa250, 0x0000a000, AR5K_INI_WRITE },
00945 { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
00946 { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
00947 { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
00948 { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
00949 { 0xa264, 0x00418a11, AR5K_INI_WRITE },
00950 { 0xa268, 0x00000000, AR5K_INI_WRITE },
00951 { AR5K_PHY_TPC_RG5, 0x0c30c16a, AR5K_INI_WRITE },
00952 { 0xa270, 0x00820820, AR5K_INI_WRITE },
00953 { 0xa274, 0x081b7caa, AR5K_INI_WRITE },
00954 { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
00955 { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
00956 { 0xa338, 0x00000000, AR5K_INI_WRITE },
00957 { 0xa33c, 0x00000000, AR5K_INI_WRITE },
00958 { 0xa340, 0x00000000, AR5K_INI_WRITE },
00959 { 0xa344, 0x00000000, AR5K_INI_WRITE },
00960 { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
00961 { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
00962 { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
00963 { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
00964 { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
00965 { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
00966 { 0xa360, 0x0f282207, AR5K_INI_WRITE },
00967 { 0xa364, 0x17601685, AR5K_INI_WRITE },
00968 { 0xa368, 0x1f801104, AR5K_INI_WRITE },
00969 { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
00970 { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
00971 { 0xa374, 0x57c00803, AR5K_INI_WRITE },
00972 { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
00973 { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
00974 { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
00975 { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
00976 };
00977
00978
00979
00980 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
00981 { AR5K_TXCFG,
00982
00983 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
00984 { AR5K_USEC_5211,
00985 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
00986 { AR5K_PHY_RF_CTL3,
00987 { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
00988 { AR5K_PHY_RF_CTL4,
00989 { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
00990 { AR5K_PHY_PA_CTL,
00991 { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
00992 { AR5K_PHY_GAIN,
00993 { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
00994 { AR5K_PHY_DESIRED_SIZE,
00995 { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
00996 { AR5K_PHY_SIG,
00997 { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
00998 { AR5K_PHY_AGCCOARSE,
00999 { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
01000 { AR5K_PHY_WEAK_OFDM_LOW_THR,
01001 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
01002 { AR5K_PHY_RX_DELAY,
01003 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
01004 { AR5K_PHY_FRAME_CTL_5211,
01005 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
01006 { AR5K_PHY_CCKTXCTL,
01007 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
01008 { AR5K_PHY_CCK_CROSSCORR,
01009 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
01010 { AR5K_PHY_GAIN_2GHZ,
01011 { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
01012 { AR5K_PHY_CCK_RX_CTL_4,
01013 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
01014 };
01015
01016 static const struct ath5k_ini rf2413_ini_common_end[] = {
01017 { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
01018 { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
01019 { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
01020 { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
01021 { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
01022 { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
01023 { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
01024 { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
01025 { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
01026 { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
01027 { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
01028 { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
01029 { 0x8140, 0x800000a8, AR5K_INI_WRITE },
01030 { 0x8144, 0x00000000, AR5K_INI_WRITE },
01031 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
01032 { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
01033 { 0x983c, 0x00200400, AR5K_INI_WRITE },
01034 { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
01035 { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
01036 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
01037 { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
01038 { 0x9958, 0x000000ff, AR5K_INI_WRITE },
01039 { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
01040 { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
01041 { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
01042 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
01043 { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
01044 { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
01045 { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
01046 { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
01047 { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
01048 { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
01049 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
01050 { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
01051 { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
01052 { 0xa250, 0x0000a000, AR5K_INI_WRITE },
01053 { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
01054 { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
01055 { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
01056 { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
01057 { 0xa264, 0x00418a11, AR5K_INI_WRITE },
01058 { 0xa268, 0x00000000, AR5K_INI_WRITE },
01059 { AR5K_PHY_TPC_RG5, 0x0c30c16a, AR5K_INI_WRITE },
01060 { 0xa270, 0x00820820, AR5K_INI_WRITE },
01061 { 0xa274, 0x001b7caa, AR5K_INI_WRITE },
01062 { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
01063 { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
01064 { 0xa300, 0x18010000, AR5K_INI_WRITE },
01065 { 0xa304, 0x30032602, AR5K_INI_WRITE },
01066 { 0xa308, 0x48073e06, AR5K_INI_WRITE },
01067 { 0xa30c, 0x560b4c0a, AR5K_INI_WRITE },
01068 { 0xa310, 0x641a600f, AR5K_INI_WRITE },
01069 { 0xa314, 0x784f6e1b, AR5K_INI_WRITE },
01070 { 0xa318, 0x868f7c5a, AR5K_INI_WRITE },
01071 { 0xa31c, 0x8ecf865b, AR5K_INI_WRITE },
01072 { 0xa320, 0x9d4f970f, AR5K_INI_WRITE },
01073 { 0xa324, 0xa5cfa18f, AR5K_INI_WRITE },
01074 { 0xa328, 0xb55faf1f, AR5K_INI_WRITE },
01075 { 0xa32c, 0xbddfb99f, AR5K_INI_WRITE },
01076 { 0xa330, 0xcd7fc73f, AR5K_INI_WRITE },
01077 { 0xa334, 0xd5ffd1bf, AR5K_INI_WRITE },
01078 { 0xa338, 0x00000000, AR5K_INI_WRITE },
01079 { 0xa33c, 0x00000000, AR5K_INI_WRITE },
01080 { 0xa340, 0x00000000, AR5K_INI_WRITE },
01081 { 0xa344, 0x00000000, AR5K_INI_WRITE },
01082 { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
01083 { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
01084 { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
01085 { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
01086 { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
01087 { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
01088 { 0xa360, 0x0f282207, AR5K_INI_WRITE },
01089 { 0xa364, 0x17601685, AR5K_INI_WRITE },
01090 { 0xa368, 0x1f801104, AR5K_INI_WRITE },
01091 { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
01092 { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
01093 { 0xa374, 0x57c00803, AR5K_INI_WRITE },
01094 { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
01095 { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
01096 { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
01097 { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
01098 };
01099
01100
01101
01102 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
01103 { AR5K_TXCFG,
01104
01105 { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
01106 { AR5K_USEC_5211,
01107 { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
01108 { AR5K_PHY_TURBO,
01109 { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
01110 { AR5K_PHY_RF_CTL3,
01111 { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
01112 { AR5K_PHY_RF_CTL4,
01113 { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
01114 { AR5K_PHY_PA_CTL,
01115 { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
01116 { AR5K_PHY_SETTLING,
01117 { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
01118 { AR5K_PHY_GAIN,
01119 { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
01120 { AR5K_PHY_DESIRED_SIZE,
01121 { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
01122 { AR5K_PHY_SIG,
01123 { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
01124 { AR5K_PHY_AGCCOARSE,
01125 { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
01126 { AR5K_PHY_WEAK_OFDM_LOW_THR,
01127 { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
01128 { AR5K_PHY_RX_DELAY,
01129 { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
01130 { AR5K_PHY_FRAME_CTL_5211,
01131 { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
01132 { AR5K_PHY_CCKTXCTL,
01133 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
01134 { AR5K_PHY_CCK_CROSSCORR,
01135 { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
01136 { AR5K_PHY_GAIN_2GHZ,
01137 { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
01138 { AR5K_PHY_CCK_RX_CTL_4,
01139 { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
01140 { 0xa324,
01141 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01142 { 0xa328,
01143 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01144 { 0xa32c,
01145 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01146 { 0xa330,
01147 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01148 { 0xa334,
01149 { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
01150 };
01151
01152 static const struct ath5k_ini rf2425_ini_common_end[] = {
01153 { AR5K_DCU_FP, 0x000003e0, AR5K_INI_WRITE },
01154 { AR5K_SEQ_MASK, 0x0000000f, AR5K_INI_WRITE },
01155 { 0x809c, 0x00000000, AR5K_INI_WRITE },
01156 { 0x80a0, 0x00000000, AR5K_INI_WRITE },
01157 { AR5K_MIC_QOS_CTL, 0x00000000, AR5K_INI_WRITE },
01158 { AR5K_MIC_QOS_SEL, 0x00000000, AR5K_INI_WRITE },
01159 { AR5K_MISC_MODE, 0x00000000, AR5K_INI_WRITE },
01160 { AR5K_OFDM_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
01161 { AR5K_CCK_FIL_CNT, 0x00000000, AR5K_INI_WRITE },
01162 { AR5K_PHYERR_CNT1, 0x00000000, AR5K_INI_WRITE },
01163 { AR5K_PHYERR_CNT1_MASK, 0x00000000, AR5K_INI_WRITE },
01164 { AR5K_PHYERR_CNT2, 0x00000000, AR5K_INI_WRITE },
01165 { AR5K_PHYERR_CNT2_MASK, 0x00000000, AR5K_INI_WRITE },
01166 { AR5K_TSF_THRES, 0x00000000, AR5K_INI_WRITE },
01167 { 0x8140, 0x800003f9, AR5K_INI_WRITE },
01168 { 0x8144, 0x00000000, AR5K_INI_WRITE },
01169 { AR5K_PHY_AGC, 0x00000000, AR5K_INI_WRITE },
01170 { AR5K_PHY_ADC_CTL, 0x0000a000, AR5K_INI_WRITE },
01171 { 0x983c, 0x00200400, AR5K_INI_WRITE },
01172 { AR5K_PHY_GAIN_OFFSET, 0x1284233c, AR5K_INI_WRITE },
01173 { AR5K_PHY_SCR, 0x0000001f, AR5K_INI_WRITE },
01174 { AR5K_PHY_SLMT, 0x00000080, AR5K_INI_WRITE },
01175 { AR5K_PHY_SCAL, 0x0000000e, AR5K_INI_WRITE },
01176 { 0x9958, 0x00081fff, AR5K_INI_WRITE },
01177 { AR5K_PHY_TIMING_7, 0x00000000, AR5K_INI_WRITE },
01178 { AR5K_PHY_TIMING_8, 0x02800000, AR5K_INI_WRITE },
01179 { AR5K_PHY_TIMING_11, 0x00000000, AR5K_INI_WRITE },
01180 { 0x99dc, 0xfebadbe8, AR5K_INI_WRITE },
01181 { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000, AR5K_INI_WRITE },
01182 { 0x99e4, 0xaaaaaaaa, AR5K_INI_WRITE },
01183 { 0x99e8, 0x3c466478, AR5K_INI_WRITE },
01184 { 0x99ec, 0x000000aa, AR5K_INI_WRITE },
01185 { AR5K_PHY_SCLOCK, 0x0000000c, AR5K_INI_WRITE },
01186 { AR5K_PHY_SDELAY, 0x000000ff, AR5K_INI_WRITE },
01187 { AR5K_PHY_SPENDING, 0x00000014, AR5K_INI_WRITE },
01188 { AR5K_PHY_DAG_CCK_CTL, 0x000009b5, AR5K_INI_WRITE },
01189 { AR5K_PHY_TXPOWER_RATE3, 0x20202020, AR5K_INI_WRITE },
01190 { AR5K_PHY_TXPOWER_RATE4, 0x20202020, AR5K_INI_WRITE },
01191 { 0xa23c, 0x93c889af, AR5K_INI_WRITE },
01192 { AR5K_PHY_FAST_ADC, 0x00000001, AR5K_INI_WRITE },
01193 { 0xa250, 0x0000a000, AR5K_INI_WRITE },
01194 { AR5K_PHY_BLUETOOTH, 0x00000000, AR5K_INI_WRITE },
01195 { AR5K_PHY_TPC_RG1, 0x0cc75380, AR5K_INI_WRITE },
01196 { 0xa25c, 0x0f0f0f01, AR5K_INI_WRITE },
01197 { 0xa260, 0x5f690f01, AR5K_INI_WRITE },
01198 { 0xa264, 0x00418a11, AR5K_INI_WRITE },
01199 { 0xa268, 0x00000000, AR5K_INI_WRITE },
01200 { AR5K_PHY_TPC_RG5, 0x0c30c166, AR5K_INI_WRITE },
01201 { 0xa270, 0x00820820, AR5K_INI_WRITE },
01202 { 0xa274, 0x081a3caa, AR5K_INI_WRITE },
01203 { 0xa278, 0x1ce739ce, AR5K_INI_WRITE },
01204 { 0xa27c, 0x051701ce, AR5K_INI_WRITE },
01205 { 0xa300, 0x16010000, AR5K_INI_WRITE },
01206 { 0xa304, 0x2c032402, AR5K_INI_WRITE },
01207 { 0xa308, 0x48433e42, AR5K_INI_WRITE },
01208 { 0xa30c, 0x5a0f500b, AR5K_INI_WRITE },
01209 { 0xa310, 0x6c4b624a, AR5K_INI_WRITE },
01210 { 0xa314, 0x7e8b748a, AR5K_INI_WRITE },
01211 { 0xa318, 0x96cf8ccb, AR5K_INI_WRITE },
01212 { 0xa31c, 0xa34f9d0f, AR5K_INI_WRITE },
01213 { 0xa320, 0xa7cfa58f, AR5K_INI_WRITE },
01214 { 0xa348, 0x3fffffff, AR5K_INI_WRITE },
01215 { 0xa34c, 0x3fffffff, AR5K_INI_WRITE },
01216 { 0xa350, 0x3fffffff, AR5K_INI_WRITE },
01217 { 0xa354, 0x0003ffff, AR5K_INI_WRITE },
01218 { 0xa358, 0x79a8aa1f, AR5K_INI_WRITE },
01219 { 0xa35c, 0x066c420f, AR5K_INI_WRITE },
01220 { 0xa360, 0x0f282207, AR5K_INI_WRITE },
01221 { 0xa364, 0x17601685, AR5K_INI_WRITE },
01222 { 0xa368, 0x1f801104, AR5K_INI_WRITE },
01223 { 0xa36c, 0x37a00c03, AR5K_INI_WRITE },
01224 { 0xa370, 0x3fc40883, AR5K_INI_WRITE },
01225 { 0xa374, 0x57c00803, AR5K_INI_WRITE },
01226 { 0xa378, 0x5fd80682, AR5K_INI_WRITE },
01227 { 0xa37c, 0x7fe00482, AR5K_INI_WRITE },
01228 { 0xa380, 0x7f3c7bba, AR5K_INI_WRITE },
01229 { 0xa384, 0xf3307ff0, AR5K_INI_WRITE },
01230 };
01231
01232
01233
01234
01235
01236
01237
01238 static const struct ath5k_ini rf5111_ini_bbgain[] = {
01239 { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
01240 { AR5K_BB_GAIN(1), 0x00000020, AR5K_INI_WRITE },
01241 { AR5K_BB_GAIN(2), 0x00000010, AR5K_INI_WRITE },
01242 { AR5K_BB_GAIN(3), 0x00000030, AR5K_INI_WRITE },
01243 { AR5K_BB_GAIN(4), 0x00000008, AR5K_INI_WRITE },
01244 { AR5K_BB_GAIN(5), 0x00000028, AR5K_INI_WRITE },
01245 { AR5K_BB_GAIN(6), 0x00000004, AR5K_INI_WRITE },
01246 { AR5K_BB_GAIN(7), 0x00000024, AR5K_INI_WRITE },
01247 { AR5K_BB_GAIN(8), 0x00000014, AR5K_INI_WRITE },
01248 { AR5K_BB_GAIN(9), 0x00000034, AR5K_INI_WRITE },
01249 { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE },
01250 { AR5K_BB_GAIN(11), 0x0000002c, AR5K_INI_WRITE },
01251 { AR5K_BB_GAIN(12), 0x00000002, AR5K_INI_WRITE },
01252 { AR5K_BB_GAIN(13), 0x00000022, AR5K_INI_WRITE },
01253 { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE },
01254 { AR5K_BB_GAIN(15), 0x00000032, AR5K_INI_WRITE },
01255 { AR5K_BB_GAIN(16), 0x0000000a, AR5K_INI_WRITE },
01256 { AR5K_BB_GAIN(17), 0x0000002a, AR5K_INI_WRITE },
01257 { AR5K_BB_GAIN(18), 0x00000006, AR5K_INI_WRITE },
01258 { AR5K_BB_GAIN(19), 0x00000026, AR5K_INI_WRITE },
01259 { AR5K_BB_GAIN(20), 0x00000016, AR5K_INI_WRITE },
01260 { AR5K_BB_GAIN(21), 0x00000036, AR5K_INI_WRITE },
01261 { AR5K_BB_GAIN(22), 0x0000000e, AR5K_INI_WRITE },
01262 { AR5K_BB_GAIN(23), 0x0000002e, AR5K_INI_WRITE },
01263 { AR5K_BB_GAIN(24), 0x00000001, AR5K_INI_WRITE },
01264 { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE },
01265 { AR5K_BB_GAIN(26), 0x00000011, AR5K_INI_WRITE },
01266 { AR5K_BB_GAIN(27), 0x00000031, AR5K_INI_WRITE },
01267 { AR5K_BB_GAIN(28), 0x00000009, AR5K_INI_WRITE },
01268 { AR5K_BB_GAIN(29), 0x00000029, AR5K_INI_WRITE },
01269 { AR5K_BB_GAIN(30), 0x00000005, AR5K_INI_WRITE },
01270 { AR5K_BB_GAIN(31), 0x00000025, AR5K_INI_WRITE },
01271 { AR5K_BB_GAIN(32), 0x00000015, AR5K_INI_WRITE },
01272 { AR5K_BB_GAIN(33), 0x00000035, AR5K_INI_WRITE },
01273 { AR5K_BB_GAIN(34), 0x0000000d, AR5K_INI_WRITE },
01274 { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE },
01275 { AR5K_BB_GAIN(36), 0x00000003, AR5K_INI_WRITE },
01276 { AR5K_BB_GAIN(37), 0x00000023, AR5K_INI_WRITE },
01277 { AR5K_BB_GAIN(38), 0x00000013, AR5K_INI_WRITE },
01278 { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE },
01279 { AR5K_BB_GAIN(40), 0x0000000b, AR5K_INI_WRITE },
01280 { AR5K_BB_GAIN(41), 0x0000002b, AR5K_INI_WRITE },
01281 { AR5K_BB_GAIN(42), 0x0000002b, AR5K_INI_WRITE },
01282 { AR5K_BB_GAIN(43), 0x0000002b, AR5K_INI_WRITE },
01283 { AR5K_BB_GAIN(44), 0x0000002b, AR5K_INI_WRITE },
01284 { AR5K_BB_GAIN(45), 0x0000002b, AR5K_INI_WRITE },
01285 { AR5K_BB_GAIN(46), 0x0000002b, AR5K_INI_WRITE },
01286 { AR5K_BB_GAIN(47), 0x0000002b, AR5K_INI_WRITE },
01287 { AR5K_BB_GAIN(48), 0x0000002b, AR5K_INI_WRITE },
01288 { AR5K_BB_GAIN(49), 0x0000002b, AR5K_INI_WRITE },
01289 { AR5K_BB_GAIN(50), 0x0000002b, AR5K_INI_WRITE },
01290 { AR5K_BB_GAIN(51), 0x0000002b, AR5K_INI_WRITE },
01291 { AR5K_BB_GAIN(52), 0x0000002b, AR5K_INI_WRITE },
01292 { AR5K_BB_GAIN(53), 0x0000002b, AR5K_INI_WRITE },
01293 { AR5K_BB_GAIN(54), 0x0000002b, AR5K_INI_WRITE },
01294 { AR5K_BB_GAIN(55), 0x0000002b, AR5K_INI_WRITE },
01295 { AR5K_BB_GAIN(56), 0x0000002b, AR5K_INI_WRITE },
01296 { AR5K_BB_GAIN(57), 0x0000002b, AR5K_INI_WRITE },
01297 { AR5K_BB_GAIN(58), 0x0000002b, AR5K_INI_WRITE },
01298 { AR5K_BB_GAIN(59), 0x0000002b, AR5K_INI_WRITE },
01299 { AR5K_BB_GAIN(60), 0x0000002b, AR5K_INI_WRITE },
01300 { AR5K_BB_GAIN(61), 0x0000002b, AR5K_INI_WRITE },
01301 { AR5K_BB_GAIN(62), 0x00000002, AR5K_INI_WRITE },
01302 { AR5K_BB_GAIN(63), 0x00000016, AR5K_INI_WRITE },
01303 };
01304
01305
01306 static const struct ath5k_ini rf5112_ini_bbgain[] = {
01307 { AR5K_BB_GAIN(0), 0x00000000, AR5K_INI_WRITE },
01308 { AR5K_BB_GAIN(1), 0x00000001, AR5K_INI_WRITE },
01309 { AR5K_BB_GAIN(2), 0x00000002, AR5K_INI_WRITE },
01310 { AR5K_BB_GAIN(3), 0x00000003, AR5K_INI_WRITE },
01311 { AR5K_BB_GAIN(4), 0x00000004, AR5K_INI_WRITE },
01312 { AR5K_BB_GAIN(5), 0x00000005, AR5K_INI_WRITE },
01313 { AR5K_BB_GAIN(6), 0x00000008, AR5K_INI_WRITE },
01314 { AR5K_BB_GAIN(7), 0x00000009, AR5K_INI_WRITE },
01315 { AR5K_BB_GAIN(8), 0x0000000a, AR5K_INI_WRITE },
01316 { AR5K_BB_GAIN(9), 0x0000000b, AR5K_INI_WRITE },
01317 { AR5K_BB_GAIN(10), 0x0000000c, AR5K_INI_WRITE },
01318 { AR5K_BB_GAIN(11), 0x0000000d, AR5K_INI_WRITE },
01319 { AR5K_BB_GAIN(12), 0x00000010, AR5K_INI_WRITE },
01320 { AR5K_BB_GAIN(13), 0x00000011, AR5K_INI_WRITE },
01321 { AR5K_BB_GAIN(14), 0x00000012, AR5K_INI_WRITE },
01322 { AR5K_BB_GAIN(15), 0x00000013, AR5K_INI_WRITE },
01323 { AR5K_BB_GAIN(16), 0x00000014, AR5K_INI_WRITE },
01324 { AR5K_BB_GAIN(17), 0x00000015, AR5K_INI_WRITE },
01325 { AR5K_BB_GAIN(18), 0x00000018, AR5K_INI_WRITE },
01326 { AR5K_BB_GAIN(19), 0x00000019, AR5K_INI_WRITE },
01327 { AR5K_BB_GAIN(20), 0x0000001a, AR5K_INI_WRITE },
01328 { AR5K_BB_GAIN(21), 0x0000001b, AR5K_INI_WRITE },
01329 { AR5K_BB_GAIN(22), 0x0000001c, AR5K_INI_WRITE },
01330 { AR5K_BB_GAIN(23), 0x0000001d, AR5K_INI_WRITE },
01331 { AR5K_BB_GAIN(24), 0x00000020, AR5K_INI_WRITE },
01332 { AR5K_BB_GAIN(25), 0x00000021, AR5K_INI_WRITE },
01333 { AR5K_BB_GAIN(26), 0x00000022, AR5K_INI_WRITE },
01334 { AR5K_BB_GAIN(27), 0x00000023, AR5K_INI_WRITE },
01335 { AR5K_BB_GAIN(28), 0x00000024, AR5K_INI_WRITE },
01336 { AR5K_BB_GAIN(29), 0x00000025, AR5K_INI_WRITE },
01337 { AR5K_BB_GAIN(30), 0x00000028, AR5K_INI_WRITE },
01338 { AR5K_BB_GAIN(31), 0x00000029, AR5K_INI_WRITE },
01339 { AR5K_BB_GAIN(32), 0x0000002a, AR5K_INI_WRITE },
01340 { AR5K_BB_GAIN(33), 0x0000002b, AR5K_INI_WRITE },
01341 { AR5K_BB_GAIN(34), 0x0000002c, AR5K_INI_WRITE },
01342 { AR5K_BB_GAIN(35), 0x0000002d, AR5K_INI_WRITE },
01343 { AR5K_BB_GAIN(36), 0x00000030, AR5K_INI_WRITE },
01344 { AR5K_BB_GAIN(37), 0x00000031, AR5K_INI_WRITE },
01345 { AR5K_BB_GAIN(38), 0x00000032, AR5K_INI_WRITE },
01346 { AR5K_BB_GAIN(39), 0x00000033, AR5K_INI_WRITE },
01347 { AR5K_BB_GAIN(40), 0x00000034, AR5K_INI_WRITE },
01348 { AR5K_BB_GAIN(41), 0x00000035, AR5K_INI_WRITE },
01349 { AR5K_BB_GAIN(42), 0x00000035, AR5K_INI_WRITE },
01350 { AR5K_BB_GAIN(43), 0x00000035, AR5K_INI_WRITE },
01351 { AR5K_BB_GAIN(44), 0x00000035, AR5K_INI_WRITE },
01352 { AR5K_BB_GAIN(45), 0x00000035, AR5K_INI_WRITE },
01353 { AR5K_BB_GAIN(46), 0x00000035, AR5K_INI_WRITE },
01354 { AR5K_BB_GAIN(47), 0x00000035, AR5K_INI_WRITE },
01355 { AR5K_BB_GAIN(48), 0x00000035, AR5K_INI_WRITE },
01356 { AR5K_BB_GAIN(49), 0x00000035, AR5K_INI_WRITE },
01357 { AR5K_BB_GAIN(50), 0x00000035, AR5K_INI_WRITE },
01358 { AR5K_BB_GAIN(51), 0x00000035, AR5K_INI_WRITE },
01359 { AR5K_BB_GAIN(52), 0x00000035, AR5K_INI_WRITE },
01360 { AR5K_BB_GAIN(53), 0x00000035, AR5K_INI_WRITE },
01361 { AR5K_BB_GAIN(54), 0x00000035, AR5K_INI_WRITE },
01362 { AR5K_BB_GAIN(55), 0x00000035, AR5K_INI_WRITE },
01363 { AR5K_BB_GAIN(56), 0x00000035, AR5K_INI_WRITE },
01364 { AR5K_BB_GAIN(57), 0x00000035, AR5K_INI_WRITE },
01365 { AR5K_BB_GAIN(58), 0x00000035, AR5K_INI_WRITE },
01366 { AR5K_BB_GAIN(59), 0x00000035, AR5K_INI_WRITE },
01367 { AR5K_BB_GAIN(60), 0x00000035, AR5K_INI_WRITE },
01368 { AR5K_BB_GAIN(61), 0x00000035, AR5K_INI_WRITE },
01369 { AR5K_BB_GAIN(62), 0x00000010, AR5K_INI_WRITE },
01370 { AR5K_BB_GAIN(63), 0x0000001a, AR5K_INI_WRITE },
01371 };
01372
01373
01374
01375
01376
01377 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
01378 const struct ath5k_ini *ini_regs, int change_channel)
01379 {
01380 unsigned int i;
01381
01382
01383 for (i = 0; i < size; i++) {
01384
01385
01386 if (change_channel &&
01387 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
01388 ini_regs[i].ini_register <= AR5K_PCU_MAX)
01389 continue;
01390
01391 switch (ini_regs[i].ini_mode) {
01392 case AR5K_INI_READ:
01393
01394 ath5k_hw_reg_read(ah, ini_regs[i].ini_register);
01395 break;
01396 case AR5K_INI_WRITE:
01397 default:
01398 AR5K_REG_WAIT(i);
01399 ath5k_hw_reg_write(ah, ini_regs[i].ini_value,
01400 ini_regs[i].ini_register);
01401 }
01402 }
01403 }
01404
01405 static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
01406 unsigned int size, const struct ath5k_ini_mode *ini_mode,
01407 u8 mode)
01408 {
01409 unsigned int i;
01410
01411 for (i = 0; i < size; i++) {
01412 AR5K_REG_WAIT(i);
01413 ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode],
01414 (u32)ini_mode[i].mode_register);
01415 }
01416 }
01417
01418 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel)
01419 {
01420
01421
01422
01423
01424
01425 if (ah->ah_version == AR5K_AR5212) {
01426
01427
01428 ath5k_hw_ini_mode_registers(ah,
01429 ARRAY_SIZE(ar5212_ini_mode_start),
01430 ar5212_ini_mode_start, mode);
01431
01432
01433
01434
01435 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
01436 ar5212_ini_common_start, change_channel);
01437
01438
01439 switch (ah->ah_radio) {
01440 case AR5K_RF5111:
01441
01442 ath5k_hw_ini_mode_registers(ah,
01443 ARRAY_SIZE(rf5111_ini_mode_end),
01444 rf5111_ini_mode_end, mode);
01445
01446 ath5k_hw_ini_registers(ah,
01447 ARRAY_SIZE(rf5111_ini_common_end),
01448 rf5111_ini_common_end, change_channel);
01449
01450
01451 ath5k_hw_ini_registers(ah,
01452 ARRAY_SIZE(rf5111_ini_bbgain),
01453 rf5111_ini_bbgain, change_channel);
01454
01455 break;
01456 case AR5K_RF5112:
01457
01458 ath5k_hw_ini_mode_registers(ah,
01459 ARRAY_SIZE(rf5112_ini_mode_end),
01460 rf5112_ini_mode_end, mode);
01461
01462 ath5k_hw_ini_registers(ah,
01463 ARRAY_SIZE(rf5112_ini_common_end),
01464 rf5112_ini_common_end, change_channel);
01465
01466 ath5k_hw_ini_registers(ah,
01467 ARRAY_SIZE(rf5112_ini_bbgain),
01468 rf5112_ini_bbgain, change_channel);
01469
01470 break;
01471 case AR5K_RF5413:
01472
01473 ath5k_hw_ini_mode_registers(ah,
01474 ARRAY_SIZE(rf5413_ini_mode_end),
01475 rf5413_ini_mode_end, mode);
01476
01477 ath5k_hw_ini_registers(ah,
01478 ARRAY_SIZE(rf5413_ini_common_end),
01479 rf5413_ini_common_end, change_channel);
01480
01481 ath5k_hw_ini_registers(ah,
01482 ARRAY_SIZE(rf5112_ini_bbgain),
01483 rf5112_ini_bbgain, change_channel);
01484
01485 break;
01486 case AR5K_RF2316:
01487 case AR5K_RF2413:
01488
01489 ath5k_hw_ini_mode_registers(ah,
01490 ARRAY_SIZE(rf2413_ini_mode_end),
01491 rf2413_ini_mode_end, mode);
01492
01493 ath5k_hw_ini_registers(ah,
01494 ARRAY_SIZE(rf2413_ini_common_end),
01495 rf2413_ini_common_end, change_channel);
01496
01497
01498 if (ah->ah_radio == AR5K_RF2316) {
01499 ath5k_hw_reg_write(ah, 0x00004000,
01500 AR5K_PHY_AGC);
01501 ath5k_hw_reg_write(ah, 0x081b7caa,
01502 0xa274);
01503 }
01504
01505 ath5k_hw_ini_registers(ah,
01506 ARRAY_SIZE(rf5112_ini_bbgain),
01507 rf5112_ini_bbgain, change_channel);
01508 break;
01509 case AR5K_RF2317:
01510 case AR5K_RF2425:
01511
01512 ath5k_hw_ini_mode_registers(ah,
01513 ARRAY_SIZE(rf2425_ini_mode_end),
01514 rf2425_ini_mode_end, mode);
01515
01516 ath5k_hw_ini_registers(ah,
01517 ARRAY_SIZE(rf2425_ini_common_end),
01518 rf2425_ini_common_end, change_channel);
01519
01520 ath5k_hw_ini_registers(ah,
01521 ARRAY_SIZE(rf5112_ini_bbgain),
01522 rf5112_ini_bbgain, change_channel);
01523 break;
01524 default:
01525 return -EINVAL;
01526
01527 }
01528
01529
01530 } else if (ah->ah_version == AR5K_AR5211) {
01531
01532
01533 if (mode > 2) {
01534 DBG("ath5k: unsupported channel mode %d\n", mode);
01535 return -EINVAL;
01536 }
01537
01538
01539 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode),
01540 ar5211_ini_mode, mode);
01541
01542
01543
01544
01545 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
01546 ar5211_ini, change_channel);
01547
01548
01549
01550
01551 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
01552 rf5111_ini_bbgain, change_channel);
01553
01554 } else if (ah->ah_version == AR5K_AR5210) {
01555 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
01556 ar5210_ini, change_channel);
01557 }
01558
01559 return 0;
01560 }
