#include "ath5k.h"#include "reg.h"#include "base.h"Go to the source code of this file.
Functions | |
| FILE_LICENCE (MIT) | |
| int | ath5k_hw_set_gpio_input (struct ath5k_hw *ah, u32 gpio) |
| int | ath5k_hw_set_gpio_output (struct ath5k_hw *ah, u32 gpio) |
| u32 | ath5k_hw_get_gpio (struct ath5k_hw *ah, u32 gpio) |
| int | ath5k_hw_set_gpio (struct ath5k_hw *ah, u32 gpio, u32 val) |
| void | ath5k_hw_set_gpio_intr (struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level) |
| FILE_LICENCE | ( | MIT | ) |
Definition at line 34 of file ath5k_gpio.c.
References AR5K_GPIOCR, AR5K_GPIOCR_IN, AR5K_GPIOCR_OUT, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and EINVAL.
Referenced by ath5k_hw_reset(), and ath5k_rfkill_set_intr().
00035 { 00036 if (gpio >= AR5K_NUM_GPIO) 00037 return -EINVAL; 00038 00039 ath5k_hw_reg_write(ah, 00040 (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio)) 00041 | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); 00042 00043 return 0; 00044 }
Definition at line 49 of file ath5k_gpio.c.
References AR5K_GPIOCR, AR5K_GPIOCR_OUT, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and EINVAL.
Referenced by ath5k_rfkill_disable(), and ath5k_rfkill_enable().
00050 { 00051 if (gpio >= AR5K_NUM_GPIO) 00052 return -EINVAL; 00053 00054 ath5k_hw_reg_write(ah, 00055 (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio)) 00056 | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); 00057 00058 return 0; 00059 }
Definition at line 64 of file ath5k_gpio.c.
References AR5K_GPIODI, AR5K_GPIODI_M, AR5K_NUM_GPIO, and ath5k_hw_reg_read().
Referenced by ath5k_hw_reset(), ath5k_is_rfkill_set(), and ath5k_rfkill_set_intr().
00065 { 00066 if (gpio >= AR5K_NUM_GPIO) 00067 return 0xffffffff; 00068 00069 /* GPIO input magic */ 00070 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) & 00071 0x1; 00072 }
Definition at line 77 of file ath5k_gpio.c.
References AR5K_GPIODO, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EINVAL, and u32.
Referenced by ath5k_rfkill_disable(), and ath5k_rfkill_enable().
00078 { 00079 u32 data; 00080 00081 if (gpio >= AR5K_NUM_GPIO) 00082 return -EINVAL; 00083 00084 /* GPIO output magic */ 00085 data = ath5k_hw_reg_read(ah, AR5K_GPIODO); 00086 00087 data &= ~(1 << gpio); 00088 data |= (val & 1) << gpio; 00089 00090 ath5k_hw_reg_write(ah, data, AR5K_GPIODO); 00091 00092 return 0; 00093 }
Definition at line 98 of file ath5k_gpio.c.
References ath5k_hw::ah_imr, AR5K_GPIOCR, AR5K_GPIOCR_INT_ENA, AR5K_GPIOCR_INT_SEL, AR5K_GPIOCR_INT_SELH, AR5K_GPIOCR_OUT, AR5K_IMR_GPIO, AR5K_NUM_GPIO, AR5K_PIMR, AR5K_REG_ENABLE_BITS, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and u32.
Referenced by ath5k_hw_reset(), and ath5k_rfkill_set_intr().
00100 { 00101 u32 data; 00102 00103 if (gpio >= AR5K_NUM_GPIO) 00104 return; 00105 00106 /* 00107 * Set the GPIO interrupt 00108 */ 00109 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & 00110 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | 00111 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | 00112 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); 00113 00114 ath5k_hw_reg_write(ah, interrupt_level ? data : 00115 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); 00116 00117 ah->ah_imr |= AR5K_IMR_GPIO; 00118 00119 /* Enable GPIO interrupts */ 00120 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO); 00121 }
1.5.7.1