#include <stddef.h>#include <byteswap.h>#include <gpxe/io.h>#include <gpxe/netdevice.h>#include <gpxe/net80211.h>#include <errno.h>#include "desc.h"#include "eeprom.h"Go to the source code of this file.
Data Structures | |
| struct | ath5k_srev_name |
| struct | ath5k_tx_status |
| struct | ath5k_txq_info |
| struct | ath5k_rx_status |
| struct | ath5k_gain |
| struct | ath5k_athchan_2ghz |
| struct | ath5k_capabilities |
| struct | ath5k_hw |
| ath5k_hw_get_isr - Get interrupt status More... | |
Defines | |
| #define | ERRFILE ERRFILE_ath5k |
| #define | ARRAY_SIZE(a) (sizeof(a)/sizeof((a)[0])) |
| #define | PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 |
| #define | PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 |
| #define | PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b |
| #define | PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 |
| #define | PCI_DEVICE_ID_ATHEROS_AR2413 0x001a |
| #define | PCI_DEVICE_ID_ATHEROS_AR5413 0x001b |
| #define | PCI_DEVICE_ID_ATHEROS_AR5424 0x001c |
| #define | PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 |
| #define | PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 |
| #define | AR5K_REG_SM(_val, _flags) (((_val) << _flags##_S) & (_flags)) |
| #define | AR5K_REG_MS(_val, _flags) (((_val) & (_flags)) >> _flags##_S) |
| #define | AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) |
| #define | AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) |
| #define | AR5K_REG_ENABLE_BITS(ah, _reg, _flags) ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) |
| #define | AR5K_REG_DISABLE_BITS(ah, _reg, _flags) ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) |
| #define | AR5K_PHY_READ(ah, _reg) ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) |
| #define | AR5K_PHY_WRITE(ah, _reg, _val) ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) |
| #define | AR5K_REG_READ_Q(ah, _reg, _queue) (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ |
| #define | AR5K_REG_WRITE_Q(ah, _reg, _queue) ath5k_hw_reg_write(ah, (1 << _queue), _reg) |
| #define | AR5K_Q_ENABLE_BITS(_reg, _queue) |
| #define | AR5K_Q_DISABLE_BITS(_reg, _queue) |
| #define | AR5K_REG_WAIT(_i) |
| #define | AR5K_INI_RFGAIN_5GHZ 0 |
| #define | AR5K_INI_RFGAIN_2GHZ 1 |
| #define | AR5K_INI_VAL_11A 0 |
| #define | AR5K_INI_VAL_11A_TURBO 1 |
| #define | AR5K_INI_VAL_11B 2 |
| #define | AR5K_INI_VAL_11G 3 |
| #define | AR5K_INI_VAL_11G_TURBO 4 |
| #define | AR5K_INI_VAL_XR 0 |
| #define | AR5K_INI_VAL_MAX 5 |
| #define | AR5K_LOW_ID(_a) |
| #define | AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8) |
| #define | IEEE80211_MAX_LEN 2352 |
| #define | AR5K_TUNE_DMA_BEACON_RESP 2 |
| #define | AR5K_TUNE_SW_BEACON_RESP 10 |
| #define | AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 |
| #define | AR5K_TUNE_RADAR_ALERT 0 |
| #define | AR5K_TUNE_MIN_TX_FIFO_THRES 1 |
| #define | AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) |
| #define | AR5K_TUNE_REGISTER_TIMEOUT 20000 |
| #define | AR5K_TUNE_RSSI_THRES 129 |
| #define | AR5K_TUNE_BMISS_THRES 7 |
| #define | AR5K_TUNE_REGISTER_DWELL_TIME 20000 |
| #define | AR5K_TUNE_BEACON_INTERVAL 100 |
| #define | AR5K_TUNE_AIFS 2 |
| #define | AR5K_TUNE_AIFS_11B 2 |
| #define | AR5K_TUNE_AIFS_XR 0 |
| #define | AR5K_TUNE_CWMIN 15 |
| #define | AR5K_TUNE_CWMIN_11B 31 |
| #define | AR5K_TUNE_CWMIN_XR 3 |
| #define | AR5K_TUNE_CWMAX 1023 |
| #define | AR5K_TUNE_CWMAX_11B 1023 |
| #define | AR5K_TUNE_CWMAX_XR 7 |
| #define | AR5K_TUNE_NOISE_FLOOR -72 |
| #define | AR5K_TUNE_MAX_TXPOWER 63 |
| #define | AR5K_TUNE_DEFAULT_TXPOWER 25 |
| #define | AR5K_TUNE_TPC_TXPOWER 0 |
| #define | AR5K_TUNE_ANT_DIVERSITY 1 |
| #define | AR5K_TUNE_HWTXTRIES 4 |
| #define | AR5K_INIT_CARR_SENSE_EN 1 |
| #define | AR5K_INIT_CFG 0x00000000 |
| #define | AR5K_INIT_CYCRSSI_THR1 2 |
| #define | AR5K_INIT_TX_LATENCY 502 |
| #define | AR5K_INIT_USEC 39 |
| #define | AR5K_INIT_USEC_TURBO 79 |
| #define | AR5K_INIT_USEC_32 31 |
| #define | AR5K_INIT_SLOT_TIME 396 |
| #define | AR5K_INIT_SLOT_TIME_TURBO 480 |
| #define | AR5K_INIT_ACK_CTS_TIMEOUT 1024 |
| #define | AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 |
| #define | AR5K_INIT_PROG_IFS 920 |
| #define | AR5K_INIT_PROG_IFS_TURBO 960 |
| #define | AR5K_INIT_EIFS 3440 |
| #define | AR5K_INIT_EIFS_TURBO 6880 |
| #define | AR5K_INIT_SIFS 560 |
| #define | AR5K_INIT_SIFS_TURBO 480 |
| #define | AR5K_INIT_SH_RETRY 10 |
| #define | AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY |
| #define | AR5K_INIT_SSH_RETRY 32 |
| #define | AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY |
| #define | AR5K_INIT_TX_RETRY 10 |
| #define | AR5K_INIT_TRANSMIT_LATENCY |
| #define | AR5K_INIT_TRANSMIT_LATENCY_TURBO |
| #define | AR5K_INIT_PROTO_TIME_CNTRL |
| #define | AR5K_INIT_PROTO_TIME_CNTRL_TURBO |
| #define | AR5K_TXQ_USEDEFAULT ((u32) -1) |
| #define | AR5K_SREV_UNKNOWN 0xffff |
| #define | AR5K_SREV_AR5210 0x00 |
| #define | AR5K_SREV_AR5311 0x10 |
| #define | AR5K_SREV_AR5311A 0x20 |
| #define | AR5K_SREV_AR5311B 0x30 |
| #define | AR5K_SREV_AR5211 0x40 |
| #define | AR5K_SREV_AR5212 0x50 |
| #define | AR5K_SREV_AR5213 0x55 |
| #define | AR5K_SREV_AR5213A 0x59 |
| #define | AR5K_SREV_AR2413 0x78 |
| #define | AR5K_SREV_AR2414 0x70 |
| #define | AR5K_SREV_AR5424 0x90 |
| #define | AR5K_SREV_AR5413 0xa4 |
| #define | AR5K_SREV_AR5414 0xa0 |
| #define | AR5K_SREV_AR2415 0xb0 |
| #define | AR5K_SREV_AR5416 0xc0 |
| #define | AR5K_SREV_AR5418 0xca |
| #define | AR5K_SREV_AR2425 0xe0 |
| #define | AR5K_SREV_AR2417 0xf0 |
| #define | AR5K_SREV_RAD_5110 0x00 |
| #define | AR5K_SREV_RAD_5111 0x10 |
| #define | AR5K_SREV_RAD_5111A 0x15 |
| #define | AR5K_SREV_RAD_2111 0x20 |
| #define | AR5K_SREV_RAD_5112 0x30 |
| #define | AR5K_SREV_RAD_5112A 0x35 |
| #define | AR5K_SREV_RAD_5112B 0x36 |
| #define | AR5K_SREV_RAD_2112 0x40 |
| #define | AR5K_SREV_RAD_2112A 0x45 |
| #define | AR5K_SREV_RAD_2112B 0x46 |
| #define | AR5K_SREV_RAD_2413 0x50 |
| #define | AR5K_SREV_RAD_5413 0x60 |
| #define | AR5K_SREV_RAD_2316 0x70 |
| #define | AR5K_SREV_RAD_2317 0x80 |
| #define | AR5K_SREV_RAD_5424 0xa0 |
| #define | AR5K_SREV_RAD_2425 0xa2 |
| #define | AR5K_SREV_RAD_5133 0xc0 |
| #define | AR5K_SREV_PHY_5211 0x30 |
| #define | AR5K_SREV_PHY_5212 0x41 |
| #define | AR5K_SREV_PHY_5212A 0x42 |
| #define | AR5K_SREV_PHY_5212B 0x43 |
| #define | AR5K_SREV_PHY_2413 0x45 |
| #define | AR5K_SREV_PHY_5413 0x61 |
| #define | AR5K_SREV_PHY_2425 0x70 |
| #define | MODULATION_XR 0x00000200 |
| #define | MODULATION_TURBO 0x00000080 |
| #define | AR5K_TXSTAT_ALTRATE 0x80 |
| #define | AR5K_TXERR_XRETRY 0x01 |
| #define | AR5K_TXERR_FILT 0x02 |
| #define | AR5K_TXERR_FIFO 0x04 |
| #define | AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 |
| #define | AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 |
| #define | AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 |
| #define | AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 |
| #define | AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 |
| #define | AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 |
| #define | AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 |
| #define | AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 |
| #define | AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 |
| #define | AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 |
| #define | AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 |
| #define | AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 |
| #define | AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 |
| #define | AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 |
| #define | AR5K_TXPOWER_OFDM(_r, _v) |
| #define | AR5K_TXPOWER_CCK(_r, _v) |
| #define | AR5K_RXERR_CRC 0x01 |
| #define | AR5K_RXERR_PHY 0x02 |
| #define | AR5K_RXERR_FIFO 0x04 |
| #define | AR5K_RXERR_DECRYPT 0x08 |
| #define | AR5K_RXERR_MIC 0x10 |
| #define | AR5K_RXKEYIX_INVALID ((u8) - 1) |
| #define | AR5K_TXKEYIX_INVALID ((u32) - 1) |
| #define | TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) |
| #define | AR5K_SLOT_TIME_9 396 |
| #define | AR5K_SLOT_TIME_20 880 |
| #define | AR5K_SLOT_TIME_MAX 0xffff |
| #define | CHANNEL_CW_INT 0x0008 |
| #define | CHANNEL_TURBO 0x0010 |
| #define | CHANNEL_CCK 0x0020 |
| #define | CHANNEL_OFDM 0x0040 |
| #define | CHANNEL_2GHZ 0x0080 |
| #define | CHANNEL_5GHZ 0x0100 |
| #define | CHANNEL_PASSIVE 0x0200 |
| #define | CHANNEL_DYN 0x0400 |
| #define | CHANNEL_XR 0x0800 |
| #define | CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
| #define | CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) |
| #define | CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) |
| #define | CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) |
| #define | CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) |
| #define | CHANNEL_108A CHANNEL_T |
| #define | CHANNEL_108G CHANNEL_TG |
| #define | CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) |
| #define | CHANNEL_ALL |
| #define | CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) |
| #define | CHANNEL_MODES CHANNEL_ALL |
| #define | IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) |
| #define | IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) |
| #define | AR5K_MAX_RATES 32 |
| Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. | |
| #define | ATH5K_RATE_CODE_1M 0x1B |
| #define | ATH5K_RATE_CODE_2M 0x1A |
| #define | ATH5K_RATE_CODE_5_5M 0x19 |
| #define | ATH5K_RATE_CODE_11M 0x18 |
| #define | ATH5K_RATE_CODE_6M 0x0B |
| #define | ATH5K_RATE_CODE_9M 0x0F |
| #define | ATH5K_RATE_CODE_12M 0x0A |
| #define | ATH5K_RATE_CODE_18M 0x0E |
| #define | ATH5K_RATE_CODE_24M 0x09 |
| #define | ATH5K_RATE_CODE_36M 0x0D |
| #define | ATH5K_RATE_CODE_48M 0x08 |
| #define | ATH5K_RATE_CODE_54M 0x0C |
| #define | ATH5K_RATE_CODE_XR_500K 0x07 |
| #define | ATH5K_RATE_CODE_XR_1M 0x02 |
| #define | ATH5K_RATE_CODE_XR_2M 0x06 |
| #define | ATH5K_RATE_CODE_XR_3M 0x01 |
| #define | AR5K_SET_SHORT_PREAMBLE 0x04 |
| #define | AR5K_KEYCACHE_SIZE 8 |
| #define | AR5K_RSSI_EP_MULTIPLIER (1<<7) |
| #define | AR5K_ASSERT_ENTRY(_e, _s) |
| #define | AR5K_SOFTLED_PIN 0 |
| #define | AR5K_SOFTLED_ON 0 |
| #define | AR5K_SOFTLED_OFF 1 |
| #define | AR5K_MAX_GPIO 10 |
| #define | AR5K_MAX_RF_BANKS 8 |
| #define | ah_regdomain ah_capabilities.cap_regdomain.reg_current |
| #define | ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw |
| #define | ah_modes ah_capabilities.cap_mode |
| #define | ah_ee_version ah_capabilities.cap_eeprom.ee_version |
Enumerations | |
| enum | ath5k_version { AR5K_AR5210 = 0, AR5K_AR5211 = 1, AR5K_AR5212 = 2 } |
| enum | ath5k_radio { AR5K_RF5110 = 0, AR5K_RF5111 = 1, AR5K_RF5112 = 2, AR5K_RF2413 = 3, AR5K_RF5413 = 4, AR5K_RF2316 = 5, AR5K_RF2317 = 6, AR5K_RF2425 = 7 } |
| enum | ath5k_srev_type { AR5K_VERSION_MAC, AR5K_VERSION_RAD } |
| enum | ath5k_driver_mode { AR5K_MODE_11A = 0, AR5K_MODE_11A_TURBO = 1, AR5K_MODE_11B = 2, AR5K_MODE_11G = 3, AR5K_MODE_11G_TURBO = 4, AR5K_MODE_XR = 5 } |
| enum | { AR5K_MODE_BIT_11A = (1 << AR5K_MODE_11A), AR5K_MODE_BIT_11A_TURBO = (1 << AR5K_MODE_11A_TURBO), AR5K_MODE_BIT_11B = (1 << AR5K_MODE_11B), AR5K_MODE_BIT_11G = (1 << AR5K_MODE_11G), AR5K_MODE_BIT_11G_TURBO = (1 << AR5K_MODE_11G_TURBO), AR5K_MODE_BIT_XR = (1 << AR5K_MODE_XR) } |
| enum | ath5k_tx_queue { AR5K_TX_QUEUE_INACTIVE = 0, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_XR_DATA, AR5K_TX_QUEUE_BEACON, AR5K_TX_QUEUE_CAB, AR5K_TX_QUEUE_UAPSD } |
| enum ath5k_tx_queue - Queue types used to classify tx queues. More... | |
| enum | ath5k_tx_queue_subtype { AR5K_WME_AC_BK = 0, AR5K_WME_AC_BE, AR5K_WME_AC_VI, AR5K_WME_AC_VO } |
| enum | ath5k_tx_queue_id { AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, AR5K_TX_QUEUE_ID_DATA_MIN = 0, AR5K_TX_QUEUE_ID_DATA_MAX = 4, AR5K_TX_QUEUE_ID_DATA_SVP = 5, AR5K_TX_QUEUE_ID_CAB = 6, AR5K_TX_QUEUE_ID_BEACON = 7, AR5K_TX_QUEUE_ID_UAPSD = 8, AR5K_TX_QUEUE_ID_XR_DATA = 9 } |
| enum | ath5k_pkt_type { AR5K_PKT_TYPE_NORMAL = 0, AR5K_PKT_TYPE_ATIM = 1, AR5K_PKT_TYPE_PSPOLL = 2, AR5K_PKT_TYPE_BEACON = 3, AR5K_PKT_TYPE_PROBE_RESP = 4, AR5K_PKT_TYPE_PIFS = 5 } |
| enum | ath5k_dmasize { AR5K_DMASIZE_4B = 0, AR5K_DMASIZE_8B, AR5K_DMASIZE_16B, AR5K_DMASIZE_32B, AR5K_DMASIZE_64B, AR5K_DMASIZE_128B, AR5K_DMASIZE_256B, AR5K_DMASIZE_512B } |
| enum | ath5k_rfgain { AR5K_RFGAIN_INACTIVE = 0, AR5K_RFGAIN_ACTIVE, AR5K_RFGAIN_READ_REQUESTED, AR5K_RFGAIN_NEED_CHANGE } |
| enum | ath5k_int { AR5K_INT_RXOK = 0x00000001, AR5K_INT_RXDESC = 0x00000002, AR5K_INT_RXERR = 0x00000004, AR5K_INT_RXNOFRM = 0x00000008, AR5K_INT_RXEOL = 0x00000010, AR5K_INT_RXORN = 0x00000020, AR5K_INT_TXOK = 0x00000040, AR5K_INT_TXDESC = 0x00000080, AR5K_INT_TXERR = 0x00000100, AR5K_INT_TXNOFRM = 0x00000200, AR5K_INT_TXEOL = 0x00000400, AR5K_INT_TXURN = 0x00000800, AR5K_INT_MIB = 0x00001000, AR5K_INT_SWI = 0x00002000, AR5K_INT_RXPHY = 0x00004000, AR5K_INT_RXKCM = 0x00008000, AR5K_INT_SWBA = 0x00010000, AR5K_INT_BRSSI = 0x00020000, AR5K_INT_BMISS = 0x00040000, AR5K_INT_FATAL = 0x00080000, AR5K_INT_BNR = 0x00100000, AR5K_INT_TIM = 0x00200000, AR5K_INT_DTIM = 0x00400000, AR5K_INT_DTIM_SYNC = 0x00800000, AR5K_INT_GPIO = 0x01000000, AR5K_INT_BCN_TIMEOUT = 0x02000000, AR5K_INT_CAB_TIMEOUT = 0x04000000, AR5K_INT_RX_DOPPLER = 0x08000000, AR5K_INT_QCBRORN = 0x10000000, AR5K_INT_QCBRURN = 0x20000000, AR5K_INT_QTRIG = 0x40000000, AR5K_INT_GLOBAL = 0x80000000, AR5K_INT_COMMON, AR5K_INT_NOCARD = 0xffffffff } |
| enum ath5k_int - Hardware interrupt masks helpers More... | |
| enum | ath5k_power_mode { AR5K_PM_UNDEFINED = 0, AR5K_PM_AUTO, AR5K_PM_AWAKE, AR5K_PM_FULL_SLEEP, AR5K_PM_NETWORK_SLEEP } |
| enum | ath5k_capability_type { AR5K_CAP_REG_DMN = 0, AR5K_CAP_TKIP_MIC = 2, AR5K_CAP_TKIP_SPLIT = 3, AR5K_CAP_PHYCOUNTERS = 4, AR5K_CAP_DIVERSITY = 5, AR5K_CAP_NUM_TXQUEUES = 6, AR5K_CAP_VEOL = 7, AR5K_CAP_COMPRESSION = 8, AR5K_CAP_BURST = 9, AR5K_CAP_FASTFRAME = 10, AR5K_CAP_TXPOW = 11, AR5K_CAP_TPC = 12, AR5K_CAP_BSSIDMASK = 13, AR5K_CAP_MCAST_KEYSRCH = 14, AR5K_CAP_TSF_ADJUST = 15, AR5K_CAP_XR = 16, AR5K_CAP_WME_TKIPMIC = 17, AR5K_CAP_CHAN_HALFRATE = 18, AR5K_CAP_CHAN_QUARTERRATE = 19, AR5K_CAP_RFSILENT = 20 } |
Functions | |
| FILE_LICENCE (MIT) | |
| int | ath5k_bitrate_to_hw_rix (int bitrate) |
| int | ath5k_hw_attach (struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah) |
| ath5k_hw_attach - Check if hw is supported and init the needed structs | |
| void | ath5k_hw_detach (struct ath5k_hw *ah) |
| ath5k_hw_detach - Free the ath5k_hw struct | |
| int | ath5k_init_leds (struct ath5k_softc *sc) |
| void | ath5k_led_enable (struct ath5k_softc *sc) |
| void | ath5k_led_off (struct ath5k_softc *sc) |
| void | ath5k_unregister_leds (struct ath5k_softc *sc) |
| int | ath5k_hw_nic_wakeup (struct ath5k_hw *ah, int flags, int initial) |
| int | ath5k_hw_reset (struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel) |
| int | ath5k_hw_set_power (struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration) |
| void | ath5k_hw_start_rx_dma (struct ath5k_hw *ah) |
| ath5k_hw_start_rx_dma - Start DMA receive | |
| int | ath5k_hw_stop_rx_dma (struct ath5k_hw *ah) |
| ath5k_hw_stop_rx_dma - Stop DMA receive | |
| u32 | ath5k_hw_get_rxdp (struct ath5k_hw *ah) |
| ath5k_hw_get_rxdp - Get RX Descriptor's address | |
| void | ath5k_hw_set_rxdp (struct ath5k_hw *ah, u32 phys_addr) |
| ath5k_hw_set_rxdp - Set RX Descriptor's address | |
| int | ath5k_hw_start_tx_dma (struct ath5k_hw *ah, unsigned int queue) |
| ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue | |
| int | ath5k_hw_stop_tx_dma (struct ath5k_hw *ah, unsigned int queue) |
| ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue | |
| u32 | ath5k_hw_get_txdp (struct ath5k_hw *ah, unsigned int queue) |
| ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue | |
| int | ath5k_hw_set_txdp (struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) |
| ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue | |
| int | ath5k_hw_update_tx_triglevel (struct ath5k_hw *ah, int increase) |
| ath5k_hw_update_tx_triglevel - Update tx trigger level | |
| int | ath5k_hw_is_intr_pending (struct ath5k_hw *ah) |
| ath5k_hw_is_intr_pending - Check if we have pending interrupts | |
| int | ath5k_hw_get_isr (struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) |
| enum ath5k_int | ath5k_hw_set_imr (struct ath5k_hw *ah, enum ath5k_int new_mask) |
| ath5k_hw_set_imr - Set interrupt mask | |
| int | ath5k_eeprom_init (struct ath5k_hw *ah) |
| void | ath5k_eeprom_detach (struct ath5k_hw *ah) |
| int | ath5k_eeprom_read_mac (struct ath5k_hw *ah, u8 *mac) |
| int | ath5k_eeprom_is_hb63 (struct ath5k_hw *ah) |
| int | ath5k_hw_set_opmode (struct ath5k_hw *ah) |
| ath5k_hw_set_opmode - Set PCU operating mode | |
| void | ath5k_hw_get_lladdr (struct ath5k_hw *ah, u8 *mac) |
| ath5k_hw_get_lladdr - Get station id | |
| int | ath5k_hw_set_lladdr (struct ath5k_hw *ah, const u8 *mac) |
| ath5k_hw_set_lladdr - Set station id | |
| void | ath5k_hw_set_associd (struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id) |
| ath5k_hw_set_associd - Set BSSID for association | |
| int | ath5k_hw_set_bssid_mask (struct ath5k_hw *ah, const u8 *mask) |
| ath5k_hw_set_bssid_mask - filter out bssids we listen | |
| void | ath5k_hw_start_rx_pcu (struct ath5k_hw *ah) |
| ath5k_hw_start_rx_pcu - Start RX engine | |
| void | ath5k_hw_stop_rx_pcu (struct ath5k_hw *ah) |
| at5k_hw_stop_rx_pcu - Stop RX engine | |
| void | ath5k_hw_set_mcast_filter (struct ath5k_hw *ah, u32 filter0, u32 filter1) |
| u32 | ath5k_hw_get_rx_filter (struct ath5k_hw *ah) |
| ath5k_hw_get_rx_filter - Get current rx filter | |
| void | ath5k_hw_set_rx_filter (struct ath5k_hw *ah, u32 filter) |
| ath5k_hw_set_rx_filter - Set rx filter | |
| void | ath5k_hw_set_ack_bitrate_high (struct ath5k_hw *ah, int high) |
| ath5k_hw_set_ack_bitrate - set bitrate for ACKs | |
| int | ath5k_hw_set_ack_timeout (struct ath5k_hw *ah, unsigned int timeout) |
| ath5k_hw_set_ack_timeout - Set ACK timeout on PCU | |
| unsigned int | ath5k_hw_get_ack_timeout (struct ath5k_hw *ah) |
| ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec | |
| int | ath5k_hw_set_cts_timeout (struct ath5k_hw *ah, unsigned int timeout) |
| ath5k_hw_set_cts_timeout - Set CTS timeout on PCU | |
| unsigned int | ath5k_hw_get_cts_timeout (struct ath5k_hw *ah) |
| ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec | |
| int | ath5k_hw_reset_key (struct ath5k_hw *ah, u16 entry) |
| int | ath5k_hw_set_tx_queueprops (struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info) |
| int | ath5k_hw_setup_tx_queue (struct ath5k_hw *ah, enum ath5k_tx_queue queue_type, struct ath5k_txq_info *queue_info) |
| u32 | ath5k_hw_num_tx_pending (struct ath5k_hw *ah) |
| void | ath5k_hw_release_tx_queue (struct ath5k_hw *ah) |
| int | ath5k_hw_reset_tx_queue (struct ath5k_hw *ah) |
| int | ath5k_hw_set_slot_time (struct ath5k_hw *ah, unsigned int slot_time) |
| int | ath5k_hw_init_desc_functions (struct ath5k_hw *ah) |
| int | ath5k_hw_set_gpio_input (struct ath5k_hw *ah, u32 gpio) |
| int | ath5k_hw_set_gpio_output (struct ath5k_hw *ah, u32 gpio) |
| u32 | ath5k_hw_get_gpio (struct ath5k_hw *ah, u32 gpio) |
| int | ath5k_hw_set_gpio (struct ath5k_hw *ah, u32 gpio, u32 val) |
| void | ath5k_hw_set_gpio_intr (struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level) |
| void | ath5k_rfkill_hw_start (struct ath5k_hw *ah) |
| void | ath5k_rfkill_hw_stop (struct ath5k_hw *ah) |
| int | ath5k_hw_set_capabilities (struct ath5k_hw *ah) |
| int | ath5k_hw_get_capability (struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result) |
| int | ath5k_hw_enable_pspoll (struct ath5k_hw *ah, u8 *bssid, u16 assoc_id) |
| int | ath5k_hw_disable_pspoll (struct ath5k_hw *ah) |
| int | ath5k_hw_write_initvals (struct ath5k_hw *ah, u8 mode, int change_channel) |
| int | ath5k_hw_rfregs_init (struct ath5k_hw *ah, struct net80211_channel *channel, unsigned int mode) |
| int | ath5k_hw_rfgain_init (struct ath5k_hw *ah, unsigned int freq) |
| enum ath5k_rfgain | ath5k_hw_gainf_calibrate (struct ath5k_hw *ah) |
| int | ath5k_hw_rfgain_opt_init (struct ath5k_hw *ah) |
| int | ath5k_channel_ok (struct ath5k_hw *ah, u16 freq, unsigned int flags) |
| int | ath5k_hw_channel (struct ath5k_hw *ah, struct net80211_channel *channel) |
| int | ath5k_hw_phy_calibrate (struct ath5k_hw *ah, struct net80211_channel *channel) |
| int | ath5k_hw_noise_floor_calibration (struct ath5k_hw *ah, short freq) |
| ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration | |
| u16 | ath5k_hw_radio_revision (struct ath5k_hw *ah, unsigned int chan) |
| void | ath5k_hw_set_def_antenna (struct ath5k_hw *ah, unsigned int ant) |
| unsigned int | ath5k_hw_get_def_antenna (struct ath5k_hw *ah) |
| int | ath5k_hw_phy_disable (struct ath5k_hw *ah) |
| int | ath5k_hw_txpower (struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower) |
| int | ath5k_hw_set_txpower_limit (struct ath5k_hw *ah, u8 ee_mode, u8 txpower) |
| static unsigned int | ath5k_hw_htoclock (unsigned int usec, int turbo) |
| static unsigned int | ath5k_hw_clocktoh (unsigned int clock, int turbo) |
| static u32 | ath5k_hw_reg_read (struct ath5k_hw *ah, u16 reg) |
| static void | ath5k_hw_reg_write (struct ath5k_hw *ah, u32 val, u16 reg) |
| static u32 | ath5k_hw_bitswap (u32 val, unsigned int bits) |
| #define ARRAY_SIZE | ( | a | ) | (sizeof(a)/sizeof((a)[0])) |
Definition at line 37 of file ath5k.h.
Referenced by __vxge_hw_ring_delete(), ath5k_get_pcdac_intercepts(), ath5k_hw_rf_check_gainf_readback(), ath5k_hw_rf_gainf_corr(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_write_initvals(), bcom_phy_init(), rtl8102e_hw_phy_config(), rtl8168bb_hw_phy_config(), rtl8168bef_hw_phy_config(), rtl8168c_1_hw_phy_config(), rtl8168c_2_hw_phy_config(), rtl8168c_3_hw_phy_config(), rtl8168cp_1_hw_phy_config(), rtl8168cp_2_hw_phy_config(), rtl8168d_hw_phy_config(), rtl8169_get_nic_variant(), rtl8169_probe(), rtl8169_set_magic_reg(), rtl8169s_hw_phy_config(), rtl8169sb_hw_phy_config(), rtl8225_rf_init(), rtl8225z2_rf_init(), rtl_hw_start_8102e_1(), rtl_hw_start_8168c_1(), rtl_hw_start_8168c_2(), rtl_hw_start_8168cp_1(), skge_board_name(), and vxge_hw_ring_replenish().
| #define AR5K_REG_SM | ( | _val, | |||
| _flags | ) | (((_val) << _flags##_S) & (_flags)) |
Definition at line 86 of file ath5k.h.
Referenced by ath5k_combine_pwr_to_pdadc_curves(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_request_rfgain_probe(), ath5k_hw_reset(), ath5k_hw_reset_tx_queue(), ath5k_hw_rf5110_calibrate(), ath5k_hw_setup_2word_tx_desc(), ath5k_hw_setup_4word_tx_desc(), ath5k_hw_stop_tx_dma(), ath5k_hw_tweak_initval_settings(), and ath5k_setup_pwr_to_pdadc_table().
| #define AR5K_REG_MS | ( | _val, | |||
| _flags | ) | (((_val) & (_flags)) >> _flags##_S) |
Definition at line 90 of file ath5k.h.
Referenced by ath5k_eeprom_init_header(), ath5k_hw_attach(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_ack_timeout(), ath5k_hw_get_cts_timeout(), ath5k_hw_get_isr(), ath5k_hw_proc_2word_tx_status(), ath5k_hw_proc_4word_tx_status(), ath5k_hw_proc_5210_rx_status(), ath5k_hw_proc_5212_rx_status(), ath5k_hw_set_ack_timeout(), ath5k_hw_set_cts_timeout(), ath5k_hw_txpower(), and ath5k_hw_update_tx_triglevel().
| #define AR5K_REG_WRITE_BITS | ( | ah, | |||
| _reg, | |||||
| _flags, | |||||
| _val | ) |
Value:
ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ (((_val) << _flags##_S) & (_flags)), _reg)
Definition at line 98 of file ath5k.h.
Referenced by ath5k_hw_commit_eeprom_settings(), ath5k_hw_reset(), ath5k_hw_rf511x_calibrate(), ath5k_hw_rfregs_init(), ath5k_hw_set_ack_timeout(), ath5k_hw_set_cts_timeout(), ath5k_hw_tweak_initval_settings(), ath5k_hw_update_tx_triglevel(), and ath5k_hw_write_ofdm_timings().
| #define AR5K_REG_MASKED_BITS | ( | ah, | |||
| _reg, | |||||
| _flags, | |||||
| _mask | ) |
Value:
ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ (_mask)) | (_flags), _reg)
| #define AR5K_REG_ENABLE_BITS | ( | ah, | |||
| _reg, | |||||
| _flags | ) | ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) |
Definition at line 106 of file ath5k.h.
Referenced by ath5k_hw_attach(), ath5k_hw_channel(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_eeprom_read(), ath5k_hw_noise_floor_calibration(), ath5k_hw_reset(), ath5k_hw_reset_tx_queue(), ath5k_hw_rf5110_calibrate(), ath5k_hw_rf511x_calibrate(), ath5k_hw_set_ack_bitrate_high(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_rx_filter(), ath5k_hw_stop_rx_pcu(), ath5k_hw_stop_tx_dma(), and ath5k_hw_tweak_initval_settings().
| #define AR5K_REG_DISABLE_BITS | ( | ah, | |||
| _reg, | |||||
| _flags | ) | ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) |
Definition at line 109 of file ath5k.h.
Referenced by ath5k_hw_reset(), ath5k_hw_reset_tx_queue(), ath5k_hw_rf5110_calibrate(), ath5k_hw_set_ack_bitrate_high(), ath5k_hw_set_rx_filter(), ath5k_hw_start_rx_pcu(), ath5k_hw_stop_tx_dma(), and ath5k_hw_tweak_initval_settings().
| #define AR5K_PHY_READ | ( | ah, | |||
| _reg | ) | ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) |
| #define AR5K_PHY_WRITE | ( | ah, | |||
| _reg, | |||||
| _val | ) | ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) |
| #define AR5K_REG_READ_Q | ( | ah, | |||
| _reg, | |||||
| _queue | ) | (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ |
Definition at line 120 of file ath5k.h.
Referenced by ath5k_hw_set_txdp(), and ath5k_hw_start_tx_dma().
| #define AR5K_REG_WRITE_Q | ( | ah, | |||
| _reg, | |||||
| _queue | ) | ath5k_hw_reg_write(ah, (1 << _queue), _reg) |
Definition at line 123 of file ath5k.h.
Referenced by ath5k_hw_reset_tx_queue(), ath5k_hw_start_tx_dma(), and ath5k_hw_stop_tx_dma().
| #define AR5K_Q_ENABLE_BITS | ( | _reg, | |||
| _queue | ) |
Value:
do { \ _reg |= 1 << _queue; \ } while (0)
Definition at line 126 of file ath5k.h.
Referenced by ath5k_hw_reset_tx_queue(), and ath5k_hw_setup_tx_queue().
| #define AR5K_Q_DISABLE_BITS | ( | _reg, | |||
| _queue | ) |
Value:
do { \ _reg &= ~(1 << _queue); \ } while (0)
Definition at line 130 of file ath5k.h.
Referenced by ath5k_hw_release_tx_queue().
| #define AR5K_REG_WAIT | ( | _i | ) |
Value:
do { \ if (_i % 64) \ udelay(1); \ } while (0)
Definition at line 135 of file ath5k.h.
Referenced by ath5k_hw_ini_mode_registers(), ath5k_hw_ini_registers(), ath5k_hw_rfgain_init(), and ath5k_hw_rfregs_init().
| #define AR5K_INI_RFGAIN_5GHZ 0 |
| #define AR5K_INI_RFGAIN_2GHZ 1 |
| #define AR5K_LOW_ID | ( | _a | ) |
Value:
( \ (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \ )
Definition at line 154 of file ath5k.h.
Referenced by ath5k_hw_reset(), ath5k_hw_set_associd(), ath5k_hw_set_bssid_mask(), ath5k_hw_set_lladdr(), and ath5k_hw_set_opmode().
| #define AR5K_HIGH_ID | ( | _a | ) | ((_a)[4] | (_a)[5] << 8) |
Definition at line 158 of file ath5k.h.
Referenced by ath5k_hw_reset(), ath5k_hw_set_associd(), ath5k_hw_set_bssid_mask(), ath5k_hw_set_lladdr(), and ath5k_hw_set_opmode().
| #define IEEE80211_MAX_LEN 2352 |
| #define AR5K_TUNE_MIN_TX_FIFO_THRES 1 |
| #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) |
| #define AR5K_TUNE_REGISTER_TIMEOUT 20000 |
| #define AR5K_TUNE_RSSI_THRES 129 |
| #define AR5K_TUNE_BMISS_THRES 7 |
| #define AR5K_TUNE_AIFS 2 |
Definition at line 183 of file ath5k.h.
Referenced by ath5k_hw_attach(), and ath5k_hw_reset_tx_queue().
| #define AR5K_TUNE_AIFS_11B 2 |
| #define AR5K_TUNE_AIFS_XR 0 |
| #define AR5K_TUNE_CWMIN 15 |
Definition at line 186 of file ath5k.h.
Referenced by ath5k_hw_attach(), and ath5k_hw_reset_tx_queue().
| #define AR5K_TUNE_CWMIN_11B 31 |
| #define AR5K_TUNE_CWMIN_XR 3 |
| #define AR5K_TUNE_CWMAX 1023 |
| #define AR5K_TUNE_CWMAX_11B 1023 |
| #define AR5K_TUNE_CWMAX_XR 7 |
| #define AR5K_TUNE_NOISE_FLOOR -72 |
| #define AR5K_TUNE_MAX_TXPOWER 63 |
Definition at line 193 of file ath5k.h.
Referenced by ath5k_combine_pwr_to_pdadc_curves(), ath5k_hw_setup_4word_tx_desc(), and ath5k_hw_txpower().
| #define AR5K_TUNE_DEFAULT_TXPOWER 25 |
| #define AR5K_TUNE_TPC_TXPOWER 0 |
| #define AR5K_TUNE_ANT_DIVERSITY 1 |
| #define AR5K_TUNE_HWTXTRIES 4 |
| #define AR5K_INIT_CFG 0x00000000 |
| #define AR5K_INIT_CYCRSSI_THR1 2 |
| #define AR5K_INIT_SLOT_TIME 396 |
| #define AR5K_INIT_SLOT_TIME_TURBO 480 |
| #define AR5K_INIT_ACK_CTS_TIMEOUT 1024 |
| #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 |
| #define AR5K_INIT_SIFS 560 |
| #define AR5K_INIT_SIFS_TURBO 480 |
| #define AR5K_INIT_SH_RETRY 10 |
| #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY |
| #define AR5K_INIT_SSH_RETRY 32 |
| #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY |
| #define AR5K_INIT_TX_RETRY 10 |
| #define AR5K_INIT_TRANSMIT_LATENCY |
Value:
( \
(AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
(AR5K_INIT_USEC) \
)
Definition at line 232 of file ath5k.h.
Referenced by ath5k_hw_reset_tx_queue().
| #define AR5K_INIT_TRANSMIT_LATENCY_TURBO |
Value:
( \
(AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
(AR5K_INIT_USEC_TURBO) \
)
Definition at line 236 of file ath5k.h.
Referenced by ath5k_hw_reset_tx_queue().
| #define AR5K_INIT_PROTO_TIME_CNTRL |
Value:
( \
(AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
(AR5K_INIT_PROG_IFS) \
)
Definition at line 240 of file ath5k.h.
Referenced by ath5k_hw_reset_tx_queue().
| #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO |
Value:
( \
(AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
(AR5K_INIT_PROG_IFS_TURBO) \
)
Definition at line 244 of file ath5k.h.
Referenced by ath5k_hw_reset_tx_queue().
| #define AR5K_TXQ_USEDEFAULT ((u32) -1) |
| #define AR5K_SREV_AR5211 0x40 |
Definition at line 294 of file ath5k.h.
Referenced by ath5k_hw_reset(), ath5k_hw_reset_tx_queue(), and ath5k_hw_tweak_initval_settings().
| #define AR5K_SREV_AR5213A 0x59 |
| #define AR5K_SREV_AR2413 0x78 |
| #define AR5K_SREV_AR2414 0x70 |
Definition at line 299 of file ath5k.h.
Referenced by ath5k_hw_attach(), and ath5k_hw_stop_tx_dma().
| #define AR5K_SREV_AR5424 0x90 |
| #define AR5K_SREV_AR5413 0xa4 |
| #define AR5K_SREV_AR5414 0xa0 |
| #define AR5K_SREV_AR2415 0xb0 |
| #define AR5K_SREV_AR5416 0xc0 |
| #define AR5K_SREV_AR2425 0xe0 |
Definition at line 306 of file ath5k.h.
Referenced by ath5k_eeprom_init_header(), ath5k_eeprom_is_hb63(), and ath5k_hw_attach().
| #define AR5K_SREV_AR2417 0xf0 |
Definition at line 307 of file ath5k.h.
Referenced by ath5k_hw_attach(), ath5k_hw_chan_has_spur_noise(), ath5k_hw_rfregs_init(), and ath5k_hw_tweak_initval_settings().
| #define AR5K_SREV_RAD_5111 0x10 |
| #define AR5K_SREV_RAD_5112 0x30 |
| #define AR5K_SREV_RAD_5112A 0x35 |
Definition at line 314 of file ath5k.h.
Referenced by ath5k_hw_gainf_calibrate(), ath5k_hw_rf_gainf_corr(), ath5k_hw_rfregs_init(), and ath5k_hw_tweak_initval_settings().
| #define AR5K_SREV_RAD_5112B 0x36 |
| #define AR5K_SREV_RAD_2112 0x40 |
| #define AR5K_SREV_RAD_2413 0x50 |
| #define AR5K_SREV_RAD_5413 0x60 |
| #define AR5K_SREV_RAD_2316 0x70 |
| #define AR5K_SREV_RAD_2317 0x80 |
| #define AR5K_SREV_RAD_5424 0xa0 |
| #define AR5K_SREV_RAD_2425 0xa2 |
| #define AR5K_SREV_PHY_5212A 0x42 |
Definition at line 329 of file ath5k.h.
Referenced by ath5k_hw_commit_eeprom_settings(), ath5k_hw_rfregs_init(), ath5k_hw_tweak_initval_settings(), and ath5k_setup_rate_powertable().
| #define AR5K_SREV_PHY_5212B 0x43 |
Definition at line 330 of file ath5k.h.
Referenced by ath5k_hw_attach(), and ath5k_hw_tweak_initval_settings().
| #define AR5K_SREV_PHY_2413 0x45 |
| #define AR5K_SREV_PHY_5413 0x61 |
| #define AR5K_SREV_PHY_2425 0x70 |
| #define AR5K_TXERR_XRETRY 0x01 |
Definition at line 433 of file ath5k.h.
Referenced by ath5k_hw_proc_2word_tx_status(), and ath5k_hw_proc_4word_tx_status().
| #define AR5K_TXERR_FILT 0x02 |
Definition at line 434 of file ath5k.h.
Referenced by ath5k_hw_proc_2word_tx_status(), and ath5k_hw_proc_4word_tx_status().
| #define AR5K_TXERR_FIFO 0x04 |
Definition at line 435 of file ath5k.h.
Referenced by ath5k_hw_proc_2word_tx_status(), and ath5k_hw_proc_4word_tx_status().
| #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 |
| #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 |
| #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 |
Definition at line 492 of file ath5k.h.
Referenced by ath5k_hw_reset_tx_queue(), and ath5k_txq_setup().
| #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 |
Definition at line 493 of file ath5k.h.
Referenced by ath5k_hw_reset_tx_queue(), and ath5k_txq_setup().
| #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 |
| #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 |
| #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 |
| #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 |
| #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 |
| #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 |
| #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 |
| #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 |
| #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 |
| #define AR5K_TXPOWER_OFDM | ( | _r, | |||
| _v | ) |
Value:
( \
((0 & 1) << ((_v) + 6)) | \
(((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
)
Definition at line 538 of file ath5k.h.
Referenced by ath5k_hw_txpower().
| #define AR5K_TXPOWER_CCK | ( | _r, | |||
| _v | ) |
Value:
( \
(ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
)
Definition at line 543 of file ath5k.h.
Referenced by ath5k_hw_txpower().
| #define AR5K_RXERR_CRC 0x01 |
Definition at line 581 of file ath5k.h.
Referenced by ath5k_handle_rx(), ath5k_hw_proc_5210_rx_status(), and ath5k_hw_proc_5212_rx_status().
| #define AR5K_RXERR_PHY 0x02 |
Definition at line 582 of file ath5k.h.
Referenced by ath5k_handle_rx(), ath5k_hw_proc_5210_rx_status(), and ath5k_hw_proc_5212_rx_status().
| #define AR5K_RXERR_FIFO 0x04 |
| #define AR5K_RXERR_DECRYPT 0x08 |
Definition at line 584 of file ath5k.h.
Referenced by ath5k_handle_rx(), ath5k_hw_proc_5210_rx_status(), and ath5k_hw_proc_5212_rx_status().
| #define AR5K_RXERR_MIC 0x10 |
| #define AR5K_RXKEYIX_INVALID ((u8) - 1) |
Definition at line 586 of file ath5k.h.
Referenced by ath5k_handle_rx(), ath5k_hw_proc_5210_rx_status(), and ath5k_hw_proc_5212_rx_status().
| #define AR5K_TXKEYIX_INVALID ((u32) - 1) |
| #define AR5K_SLOT_TIME_MAX 0xffff |
| #define CHANNEL_TURBO 0x0010 |
Definition at line 631 of file ath5k.h.
Referenced by ath5k_copy_channels(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_nic_wakeup(), and ath5k_hw_write_ofdm_timings().
| #define CHANNEL_CCK 0x0020 |
Definition at line 632 of file ath5k.h.
Referenced by ath5k_hw_nic_wakeup(), ath5k_hw_reset(), and ath5k_hw_rfregs_init().
| #define CHANNEL_OFDM 0x0040 |
Definition at line 633 of file ath5k.h.
Referenced by ath5k_copy_channels(), ath5k_get_chan_pcal_surrounding_piers(), ath5k_get_rate_pcal_data(), ath5k_hw_nic_wakeup(), ath5k_hw_reset(), ath5k_hw_rfregs_init(), and ath5k_hw_write_ofdm_timings().
| #define CHANNEL_2GHZ 0x0080 |
Definition at line 634 of file ath5k.h.
Referenced by ath5k_channel_ok(), ath5k_copy_channels(), ath5k_get_chan_pcal_surrounding_piers(), ath5k_get_rate_pcal_data(), ath5k_hw_attach(), ath5k_hw_nic_wakeup(), ath5k_hw_radio_revision(), ath5k_hw_rf5111_channel(), and ath5k_hw_rfregs_init().
| #define CHANNEL_5GHZ 0x0100 |
Definition at line 635 of file ath5k.h.
Referenced by ath5k_channel_ok(), ath5k_copy_channels(), ath5k_hw_attach(), ath5k_hw_nic_wakeup(), ath5k_hw_radio_revision(), ath5k_hw_rfregs_init(), and ath5k_hw_tweak_initval_settings().
| #define CHANNEL_XR 0x0800 |
Definition at line 638 of file ath5k.h.
Referenced by ath5k_get_max_ctl_power(), and ath5k_hw_reset().
| #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
Definition at line 640 of file ath5k.h.
Referenced by ath5k_get_max_ctl_power(), and ath5k_hw_reset().
| #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) |
Definition at line 641 of file ath5k.h.
Referenced by ath5k_copy_channels(), ath5k_get_max_ctl_power(), ath5k_hw_attach(), and ath5k_hw_reset().
| #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) |
Definition at line 642 of file ath5k.h.
Referenced by ath5k_get_max_ctl_power(), ath5k_hw_commit_eeprom_settings(), and ath5k_hw_reset().
| #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) |
Definition at line 643 of file ath5k.h.
Referenced by ath5k_get_max_ctl_power(), ath5k_hw_channel(), and ath5k_hw_reset().
| #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) |
Definition at line 644 of file ath5k.h.
Referenced by ath5k_get_max_ctl_power(), and ath5k_hw_reset().
| #define CHANNEL_ALL |
Value:
| #define CHANNEL_MODES CHANNEL_ALL |
Definition at line 653 of file ath5k.h.
Referenced by ath5k_get_max_ctl_power(), and ath5k_hw_reset().
| #define IS_CHAN_XR | ( | _c | ) | ((_c->hw_value & CHANNEL_XR) != 0) |
| #define IS_CHAN_B | ( | _c | ) | ((_c->hw_value & CHANNEL_B) != 0) |
| #define AR5K_MAX_RATES 32 |
Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
The rate code is used to get the RX rate or set the TX rate on the hardware descriptors. It is also used for internal modulation control and settings.
This is the hardware rate map we are aware of:
rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 rate_kbps 3000 1000 ? ? ? 2000 500 48000
rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
rate_code 17 18 19 20 21 22 23 24 rate_kbps ? ? ? ? ? ? ? 11000
rate_code 25 26 27 28 29 30 31 32 rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
"S" indicates CCK rates with short preamble.
AR5211 has different rate codes for CCK (802.11B) rates. It only uses the lowest 4 bits, so they are the same as below with a 0xF mask. (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). We handle this in ath5k_setup_bands().
| #define ATH5K_RATE_CODE_1M 0x1B |
| #define AR5K_SET_SHORT_PREAMBLE 0x04 |
| #define AR5K_KEYCACHE_SIZE 8 |
| #define AR5K_ASSERT_ENTRY | ( | _e, | |||
| _s | ) |
| #define AR5K_MAX_RF_BANKS 8 |
| #define ah_regdomain ah_capabilities.cap_regdomain.reg_current |
| #define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw |
| enum ath5k_version |
Definition at line 255 of file ath5k.h.
00255 { 00256 AR5K_AR5210 = 0, 00257 AR5K_AR5211 = 1, 00258 AR5K_AR5212 = 2, 00259 };
| enum ath5k_radio |
| AR5K_RF5110 | |
| AR5K_RF5111 | |
| AR5K_RF5112 | |
| AR5K_RF2413 | |
| AR5K_RF5413 | |
| AR5K_RF2316 | |
| AR5K_RF2317 | |
| AR5K_RF2425 |
Definition at line 262 of file ath5k.h.
00262 { 00263 AR5K_RF5110 = 0, 00264 AR5K_RF5111 = 1, 00265 AR5K_RF5112 = 2, 00266 AR5K_RF2413 = 3, 00267 AR5K_RF5413 = 4, 00268 AR5K_RF2316 = 5, 00269 AR5K_RF2317 = 6, 00270 AR5K_RF2425 = 7, 00271 };
| enum ath5k_srev_type |
Definition at line 277 of file ath5k.h.
00277 { 00278 AR5K_VERSION_MAC, 00279 AR5K_VERSION_RAD, 00280 };
| enum ath5k_driver_mode |
| AR5K_MODE_11A | |
| AR5K_MODE_11A_TURBO | |
| AR5K_MODE_11B | |
| AR5K_MODE_11G | |
| AR5K_MODE_11G_TURBO | |
| AR5K_MODE_XR |
Definition at line 393 of file ath5k.h.
00393 { 00394 AR5K_MODE_11A = 0, 00395 AR5K_MODE_11A_TURBO = 1, 00396 AR5K_MODE_11B = 2, 00397 AR5K_MODE_11G = 3, 00398 AR5K_MODE_11G_TURBO = 4, 00399 AR5K_MODE_XR = 5, 00400 };
| anonymous enum |
| AR5K_MODE_BIT_11A | |
| AR5K_MODE_BIT_11A_TURBO | |
| AR5K_MODE_BIT_11B | |
| AR5K_MODE_BIT_11G | |
| AR5K_MODE_BIT_11G_TURBO | |
| AR5K_MODE_BIT_XR |
Definition at line 402 of file ath5k.h.
00402 { 00403 AR5K_MODE_BIT_11A = (1 << AR5K_MODE_11A), 00404 AR5K_MODE_BIT_11A_TURBO = (1 << AR5K_MODE_11A_TURBO), 00405 AR5K_MODE_BIT_11B = (1 << AR5K_MODE_11B), 00406 AR5K_MODE_BIT_11G = (1 << AR5K_MODE_11G), 00407 AR5K_MODE_BIT_11G_TURBO = (1 << AR5K_MODE_11G_TURBO), 00408 AR5K_MODE_BIT_XR = (1 << AR5K_MODE_XR), 00409 };
| enum ath5k_tx_queue |
enum ath5k_tx_queue - Queue types used to classify tx queues.
: q is unused -- see ath5k_hw_release_tx_queue : A normal data queue : An XR-data queue : The beacon queue : The after-beacon queue : Unscheduled Automatic Power Save Delivery queue
| AR5K_TX_QUEUE_INACTIVE | |
| AR5K_TX_QUEUE_DATA | |
| AR5K_TX_QUEUE_XR_DATA | |
| AR5K_TX_QUEUE_BEACON | |
| AR5K_TX_QUEUE_CAB | |
| AR5K_TX_QUEUE_UAPSD |
Definition at line 446 of file ath5k.h.
00446 { 00447 AR5K_TX_QUEUE_INACTIVE = 0, 00448 AR5K_TX_QUEUE_DATA, 00449 AR5K_TX_QUEUE_XR_DATA, 00450 AR5K_TX_QUEUE_BEACON, 00451 AR5K_TX_QUEUE_CAB, 00452 AR5K_TX_QUEUE_UAPSD, 00453 };
Definition at line 462 of file ath5k.h.
00462 { 00463 AR5K_WME_AC_BK = 0, /*Background traffic*/ 00464 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 00465 AR5K_WME_AC_VI, /*Video traffic*/ 00466 AR5K_WME_AC_VO, /*Voice traffic*/ 00467 };
| enum ath5k_tx_queue_id |
Definition at line 475 of file ath5k.h.
00475 { 00476 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 00477 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 00478 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 00479 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 00480 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 00481 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 00482 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 00483 AR5K_TX_QUEUE_ID_UAPSD = 8, 00484 AR5K_TX_QUEUE_ID_XR_DATA = 9, 00485 };
| enum ath5k_pkt_type |
| AR5K_PKT_TYPE_NORMAL | |
| AR5K_PKT_TYPE_ATIM | |
| AR5K_PKT_TYPE_PSPOLL | |
| AR5K_PKT_TYPE_BEACON | |
| AR5K_PKT_TYPE_PROBE_RESP | |
| AR5K_PKT_TYPE_PIFS |
Definition at line 526 of file ath5k.h.
00526 { 00527 AR5K_PKT_TYPE_NORMAL = 0, 00528 AR5K_PKT_TYPE_ATIM = 1, 00529 AR5K_PKT_TYPE_PSPOLL = 2, 00530 AR5K_PKT_TYPE_BEACON = 3, 00531 AR5K_PKT_TYPE_PROBE_RESP = 4, 00532 AR5K_PKT_TYPE_PIFS = 5, 00533 };
| enum ath5k_dmasize |
| AR5K_DMASIZE_4B | |
| AR5K_DMASIZE_8B | |
| AR5K_DMASIZE_16B | |
| AR5K_DMASIZE_32B | |
| AR5K_DMASIZE_64B | |
| AR5K_DMASIZE_128B | |
| AR5K_DMASIZE_256B | |
| AR5K_DMASIZE_512B |
Definition at line 550 of file ath5k.h.
00550 { 00551 AR5K_DMASIZE_4B = 0, 00552 AR5K_DMASIZE_8B, 00553 AR5K_DMASIZE_16B, 00554 AR5K_DMASIZE_32B, 00555 AR5K_DMASIZE_64B, 00556 AR5K_DMASIZE_128B, 00557 AR5K_DMASIZE_256B, 00558 AR5K_DMASIZE_512B 00559 };
| enum ath5k_rfgain |
| AR5K_RFGAIN_INACTIVE | |
| AR5K_RFGAIN_ACTIVE | |
| AR5K_RFGAIN_READ_REQUESTED | |
| AR5K_RFGAIN_NEED_CHANGE |
Definition at line 604 of file ath5k.h.
00604 { 00605 AR5K_RFGAIN_INACTIVE = 0, 00606 AR5K_RFGAIN_ACTIVE, 00607 AR5K_RFGAIN_READ_REQUESTED, 00608 AR5K_RFGAIN_NEED_CHANGE, 00609 };
| enum ath5k_int |
enum ath5k_int - Hardware interrupt masks helpers
: mask to identify received frame interrupts, of type AR5K_ISR_RXOK or AR5K_ISR_RXERR : Request RX descriptor/Read RX descriptor (?) : No frame received (?) : received End Of List for VEOL (Virtual End Of List). The Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's LinkPtr is NULL. For more details, refer to: http://www.freepatentsonline.com/20030225739.html : Indicates we got RX overrun (eg. no more descriptors). Note that Rx overrun is not always fatal, on some chips we can continue operation without reseting the card, that's why int_fatal is not common for all chips. : mask to identify received frame interrupts, of type AR5K_ISR_TXOK or AR5K_ISR_TXERR : Request TX descriptor/Read TX status descriptor (?) : received when we should increase the TX trigger threshold We currently do increments on interrupt by (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 : Indicates the Management Information Base counters should be checked. We should do this with ath5k_hw_update_mib_counters() but it seems we should also then do some noise immunity work. : RX PHY Error : RX Key cache miss : SoftWare Beacon Alert - indicates its time to send a beacon that must be handled in software. The alternative is if you have VEOL support, in that case you let the hardware deal with things. : If in STA mode this indicates we have stopped seeing beacons from the AP have associated with, we should probably try to reassociate. When in IBSS mode this might mean we have not received any beacons from any local stations. Note that every station in an IBSS schedules to send beacons at the Target Beacon Transmission Time (TBTT) with a random backoff. : Beacon Not Ready interrupt - ?? : GPIO interrupt is used for RF Kill, disabled for now until properly handled : Fatal errors were encountered, typically caused by DMA errors. These types of errors we can enable seem to be of type AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. : Used to clear and set the IER : signals the card has been removed : common interrupts shared amogst MACs with the same bit value
These are mapped to take advantage of some common bits between the MACs, to be able to set intr properties easier. Some of them are not used yet inside hw.c. Most map to the respective hw interrupt value as they are common amogst different MACs.
Definition at line 806 of file ath5k.h.
00806 { 00807 AR5K_INT_RXOK = 0x00000001, 00808 AR5K_INT_RXDESC = 0x00000002, 00809 AR5K_INT_RXERR = 0x00000004, 00810 AR5K_INT_RXNOFRM = 0x00000008, 00811 AR5K_INT_RXEOL = 0x00000010, 00812 AR5K_INT_RXORN = 0x00000020, 00813 AR5K_INT_TXOK = 0x00000040, 00814 AR5K_INT_TXDESC = 0x00000080, 00815 AR5K_INT_TXERR = 0x00000100, 00816 AR5K_INT_TXNOFRM = 0x00000200, 00817 AR5K_INT_TXEOL = 0x00000400, 00818 AR5K_INT_TXURN = 0x00000800, 00819 AR5K_INT_MIB = 0x00001000, 00820 AR5K_INT_SWI = 0x00002000, 00821 AR5K_INT_RXPHY = 0x00004000, 00822 AR5K_INT_RXKCM = 0x00008000, 00823 AR5K_INT_SWBA = 0x00010000, 00824 AR5K_INT_BRSSI = 0x00020000, 00825 AR5K_INT_BMISS = 0x00040000, 00826 AR5K_INT_FATAL = 0x00080000, /* Non common */ 00827 AR5K_INT_BNR = 0x00100000, /* Non common */ 00828 AR5K_INT_TIM = 0x00200000, /* Non common */ 00829 AR5K_INT_DTIM = 0x00400000, /* Non common */ 00830 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 00831 AR5K_INT_GPIO = 0x01000000, 00832 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 00833 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 00834 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 00835 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 00836 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 00837 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 00838 AR5K_INT_GLOBAL = 0x80000000, 00839 00840 AR5K_INT_COMMON = AR5K_INT_RXOK 00841 | AR5K_INT_RXDESC 00842 | AR5K_INT_RXERR 00843 | AR5K_INT_RXNOFRM 00844 | AR5K_INT_RXEOL 00845 | AR5K_INT_RXORN 00846 | AR5K_INT_TXOK 00847 | AR5K_INT_TXDESC 00848 | AR5K_INT_TXERR 00849 | AR5K_INT_TXNOFRM 00850 | AR5K_INT_TXEOL 00851 | AR5K_INT_TXURN 00852 | AR5K_INT_MIB 00853 | AR5K_INT_SWI 00854 | AR5K_INT_RXPHY 00855 | AR5K_INT_RXKCM 00856 | AR5K_INT_SWBA 00857 | AR5K_INT_BRSSI 00858 | AR5K_INT_BMISS 00859 | AR5K_INT_GPIO 00860 | AR5K_INT_GLOBAL, 00861 00862 AR5K_INT_NOCARD = 0xffffffff 00863 };
| enum ath5k_power_mode |
Definition at line 868 of file ath5k.h.
00868 { 00869 AR5K_PM_UNDEFINED = 0, 00870 AR5K_PM_AUTO, 00871 AR5K_PM_AWAKE, 00872 AR5K_PM_FULL_SLEEP, 00873 AR5K_PM_NETWORK_SLEEP, 00874 };
Definition at line 887 of file ath5k.h.
00887 { 00888 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 00889 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 00890 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 00891 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 00892 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 00893 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 00894 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 00895 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 00896 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 00897 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 00898 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 00899 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 00900 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 00901 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 00902 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 00903 AR5K_CAP_XR = 16, /* Supports XR mode */ 00904 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 00905 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 00906 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 00907 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 00908 };
| FILE_LICENCE | ( | MIT | ) |
| int ath5k_bitrate_to_hw_rix | ( | int | bitrate | ) |
Definition at line 760 of file ath5k.c.
References ATH5K_NR_RATES, ATH5K_RATE_CODE_1M, ath5k_rates, and DBG.
Referenced by ath5k_hw_write_rate_duration().
00761 { 00762 int i; 00763 00764 for (i = 0; i < ATH5K_NR_RATES; i++) { 00765 if (ath5k_rates[i].bitrate == bitrate) 00766 return ath5k_rates[i].hw_code; 00767 } 00768 00769 DBG("ath5k: invalid bitrate %d\n", bitrate); 00770 return ATH5K_RATE_CODE_1M; /* use lowest rate */ 00771 }
| int ath5k_hw_attach | ( | struct ath5k_softc * | sc, | |
| u8 | mac_version, | |||
| struct ath5k_hw ** | hw | |||
| ) |
ath5k_hw_attach - Check if hw is supported and init the needed structs
: The &struct ath5k_softc we got from the driver's attach function : The mac version id (check out ath5k.h) based on pci id : Returned newly allocated hardware structure, on success
Check if the device is supported, perform a POST and initialize the needed structs. Returns -ENOMEM if we don't have memory for the needed structs, -ENODEV if the device is not supported or prints an error msg if something else went wrong.
Definition at line 112 of file ath5k_attach.c.
References ath5k_hw::ah_aifs, ath5k_hw::ah_ant_diversity, ath5k_hw::ah_atim_window, ath5k_hw::ah_bssid, ath5k_hw::ah_combined_mic, ath5k_hw::ah_cw_min, ath5k_hw::ah_imr, ath5k_hw::ah_iobase, ath5k_hw::ah_limit_tx_retries, ath5k_hw::ah_mac_revision, ath5k_hw::ah_mac_srev, ath5k_hw::ah_mac_version, ath5k_hw::ah_phy, ath5k_hw::ah_phy_revision, ath5k_hw::ah_radio, ath5k_hw::ah_radio_2ghz_revision, ath5k_hw::ah_radio_5ghz_revision, ath5k_hw::ah_sc, ath5k_hw::ah_single_chip, ath5k_hw::ah_software_retry, ath5k_hw::ah_turbo, ath5k_hw::ah_txpower, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_INIT_TX_RETRY, AR5K_MISC_MODE, AR5K_MISC_MODE_COMBINED_MIC, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX, AR5K_PCIE_SERDES, AR5K_PCIE_SERDES_RESET, AR5K_PHY, AR5K_PHY_CHIP_ID, AR5K_REG_ENABLE_BITS, AR5K_REG_MS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5110, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_SREV, AR5K_SREV_AR2414, AR5K_SREV_AR2415, AR5K_SREV_AR2417, AR5K_SREV_AR2425, AR5K_SREV_AR5213A, AR5K_SREV_AR5414, AR5K_SREV_AR5416, AR5K_SREV_PHY_2413, AR5K_SREV_PHY_2425, AR5K_SREV_PHY_5212B, AR5K_SREV_PHY_5413, AR5K_SREV_RAD_2112, AR5K_SREV_RAD_2316, AR5K_SREV_RAD_2317, AR5K_SREV_RAD_2413, AR5K_SREV_RAD_2425, AR5K_SREV_RAD_5111, AR5K_SREV_RAD_5112, AR5K_SREV_RAD_5112B, AR5K_SREV_RAD_5413, AR5K_SREV_RAD_5424, AR5K_SREV_REV, AR5K_SREV_VER, AR5K_TUNE_AIFS, AR5K_TUNE_ANT_DIVERSITY, AR5K_TUNE_CWMIN, ath5k_eeprom_init(), ath5k_hw_init_desc_functions(), ath5k_hw_nic_wakeup(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_rfgain_opt_init(), ath5k_hw_set_associd(), ath5k_hw_set_capabilities(), ath5k_hw_set_opmode(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_B, DBG, pci_device::device, ENOMEM, ENOTSUP, ETH_ALEN, free(), ath5k_softc::iobase, mdelay(), memset(), NULL, PCI_CAP_ID_EXP, pci_find_capability(), ath5k_softc::pdev, ath5k_hw::txp_tpc, u32, and zalloc().
Referenced by ath5k_probe().
00114 { 00115 struct ath5k_hw *ah; 00116 struct pci_device *pdev = sc->pdev; 00117 int ret; 00118 u32 srev; 00119 00120 ah = zalloc(sizeof(struct ath5k_hw)); 00121 if (ah == NULL) { 00122 ret = -ENOMEM; 00123 DBG("ath5k: out of memory\n"); 00124 goto err; 00125 } 00126 00127 ah->ah_sc = sc; 00128 ah->ah_iobase = sc->iobase; 00129 00130 /* 00131 * HW information 00132 */ 00133 ah->ah_turbo = 0; 00134 ah->ah_txpower.txp_tpc = 0; 00135 ah->ah_imr = 0; 00136 ah->ah_atim_window = 0; 00137 ah->ah_aifs = AR5K_TUNE_AIFS; 00138 ah->ah_cw_min = AR5K_TUNE_CWMIN; 00139 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY; 00140 ah->ah_software_retry = 0; 00141 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY; 00142 00143 /* 00144 * Set the mac version based on the pci id 00145 */ 00146 ah->ah_version = mac_version; 00147 00148 /*Fill the ath5k_hw struct with the needed functions*/ 00149 ret = ath5k_hw_init_desc_functions(ah); 00150 if (ret) 00151 goto err_free; 00152 00153 /* Bring device out of sleep and reset it's units */ 00154 ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, 1); 00155 if (ret) 00156 goto err_free; 00157 00158 /* Get MAC, PHY and RADIO revisions */ 00159 srev = ath5k_hw_reg_read(ah, AR5K_SREV); 00160 ah->ah_mac_srev = srev; 00161 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); 00162 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV); 00163 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID); 00164 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, CHANNEL_5GHZ); 00165 ah->ah_phy = AR5K_PHY(0); 00166 00167 /* Try to identify radio chip based on it's srev */ 00168 switch (ah->ah_radio_5ghz_revision & 0xf0) { 00169 case AR5K_SREV_RAD_5111: 00170 ah->ah_radio = AR5K_RF5111; 00171 ah->ah_single_chip = 0; 00172 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 00173 CHANNEL_2GHZ); 00174 break; 00175 case AR5K_SREV_RAD_5112: 00176 case AR5K_SREV_RAD_2112: 00177 ah->ah_radio = AR5K_RF5112; 00178 ah->ah_single_chip = 0; 00179 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 00180 CHANNEL_2GHZ); 00181 break; 00182 case AR5K_SREV_RAD_2413: 00183 ah->ah_radio = AR5K_RF2413; 00184 ah->ah_single_chip = 1; 00185 break; 00186 case AR5K_SREV_RAD_5413: 00187 ah->ah_radio = AR5K_RF5413; 00188 ah->ah_single_chip = 1; 00189 break; 00190 case AR5K_SREV_RAD_2316: 00191 ah->ah_radio = AR5K_RF2316; 00192 ah->ah_single_chip = 1; 00193 break; 00194 case AR5K_SREV_RAD_2317: 00195 ah->ah_radio = AR5K_RF2317; 00196 ah->ah_single_chip = 1; 00197 break; 00198 case AR5K_SREV_RAD_5424: 00199 if (ah->ah_mac_version == AR5K_SREV_AR2425 || 00200 ah->ah_mac_version == AR5K_SREV_AR2417) { 00201 ah->ah_radio = AR5K_RF2425; 00202 } else { 00203 ah->ah_radio = AR5K_RF5413; 00204 } 00205 ah->ah_single_chip = 1; 00206 break; 00207 default: 00208 /* Identify radio based on mac/phy srev */ 00209 if (ah->ah_version == AR5K_AR5210) { 00210 ah->ah_radio = AR5K_RF5110; 00211 ah->ah_single_chip = 0; 00212 } else if (ah->ah_version == AR5K_AR5211) { 00213 ah->ah_radio = AR5K_RF5111; 00214 ah->ah_single_chip = 0; 00215 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, 00216 CHANNEL_2GHZ); 00217 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) || 00218 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) || 00219 ah->ah_phy_revision == AR5K_SREV_PHY_2425) { 00220 ah->ah_radio = AR5K_RF2425; 00221 ah->ah_single_chip = 1; 00222 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425; 00223 } else if (srev == AR5K_SREV_AR5213A && 00224 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) { 00225 ah->ah_radio = AR5K_RF5112; 00226 ah->ah_single_chip = 0; 00227 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B; 00228 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) { 00229 ah->ah_radio = AR5K_RF2316; 00230 ah->ah_single_chip = 1; 00231 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316; 00232 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) || 00233 ah->ah_phy_revision == AR5K_SREV_PHY_5413) { 00234 ah->ah_radio = AR5K_RF5413; 00235 ah->ah_single_chip = 1; 00236 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413; 00237 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) || 00238 ah->ah_phy_revision == AR5K_SREV_PHY_2413) { 00239 ah->ah_radio = AR5K_RF2413; 00240 ah->ah_single_chip = 1; 00241 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413; 00242 } else { 00243 DBG("ath5k: Couldn't identify radio revision.\n"); 00244 ret = -ENOTSUP; 00245 goto err_free; 00246 } 00247 } 00248 00249 /* Return on unsuported chips (unsupported eeprom etc) */ 00250 if ((srev >= AR5K_SREV_AR5416) && 00251 (srev < AR5K_SREV_AR2425)) { 00252 DBG("ath5k: Device not yet supported.\n"); 00253 ret = -ENOTSUP; 00254 goto err_free; 00255 } 00256 00257 /* 00258 * Write PCI-E power save settings 00259 */ 00260 if ((ah->ah_version == AR5K_AR5212) && 00261 pci_find_capability(pdev, PCI_CAP_ID_EXP)) { 00262 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES); 00263 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES); 00264 /* Shut off RX when elecidle is asserted */ 00265 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES); 00266 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES); 00267 /* TODO: EEPROM work */ 00268 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES); 00269 /* Shut off PLL and CLKREQ active in L1 */ 00270 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES); 00271 /* Preserce other settings */ 00272 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES); 00273 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES); 00274 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES); 00275 /* Reset SERDES to load new settings */ 00276 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET); 00277 mdelay(1); 00278 } 00279 00280 /* 00281 * POST 00282 */ 00283 ret = ath5k_hw_post(ah); 00284 if (ret) 00285 goto err_free; 00286 00287 /* Enable pci core retry fix on Hainan (5213A) and later chips */ 00288 if (srev >= AR5K_SREV_AR5213A) 00289 ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG); 00290 00291 /* 00292 * Get card capabilities, calibration values etc 00293 * TODO: EEPROM work 00294 */ 00295 ret = ath5k_eeprom_init(ah); 00296 if (ret) { 00297 DBG("ath5k: unable to init EEPROM\n"); 00298 goto err_free; 00299 } 00300 00301 /* Get misc capabilities */ 00302 ret = ath5k_hw_set_capabilities(ah); 00303 if (ret) { 00304 DBG("ath5k: unable to get device capabilities: 0x%04x\n", 00305 sc->pdev->device); 00306 goto err_free; 00307 } 00308 00309 if (srev >= AR5K_SREV_AR2414) { 00310 ah->ah_combined_mic = 1; 00311 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE, 00312 AR5K_MISC_MODE_COMBINED_MIC); 00313 } 00314 00315 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */ 00316 memset(ah->ah_bssid, 0xff, ETH_ALEN); 00317 ath5k_hw_set_associd(ah, ah->ah_bssid, 0); 00318 ath5k_hw_set_opmode(ah); 00319 00320 ath5k_hw_rfgain_opt_init(ah); 00321 00322 *hw = ah; 00323 return 0; 00324 err_free: 00325 free(ah); 00326 err: 00327 return ret; 00328 }
| void ath5k_hw_detach | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_detach - Free the ath5k_hw struct
: The &struct ath5k_hw
Definition at line 335 of file ath5k_attach.c.
References ath5k_hw::ah_rf_banks, ath5k_eeprom_detach(), and free().
Referenced by ath5k_probe(), and ath5k_remove().
00336 { 00337 free(ah->ah_rf_banks); 00338 ath5k_eeprom_detach(ah); 00339 free(ah); 00340 }
| int ath5k_init_leds | ( | struct ath5k_softc * | sc | ) |
| void ath5k_led_enable | ( | struct ath5k_softc * | sc | ) |
| void ath5k_led_off | ( | struct ath5k_softc * | sc | ) |
| void ath5k_unregister_leds | ( | struct ath5k_softc * | sc | ) |
| int ath5k_hw_nic_wakeup | ( | struct ath5k_hw * | ah, | |
| int | flags, | |||
| int | initial | |||
| ) |
Definition at line 290 of file ath5k_reset.c.
References ath5k_hw::ah_radio, ath5k_hw::ah_sc, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_PHY_MODE, AR5K_PHY_MODE_FREQ_2GHZ, AR5K_PHY_MODE_FREQ_5GHZ, AR5K_PHY_MODE_MOD_CCK, AR5K_PHY_MODE_MOD_DYN, AR5K_PHY_MODE_MOD_OFDM, AR5K_PHY_MODE_RAD_RF5111, AR5K_PHY_MODE_RAD_RF5112, AR5K_PHY_PLL, AR5K_PHY_PLL_40MHZ, AR5K_PHY_PLL_40MHZ_5413, AR5K_PHY_PLL_44MHZ, AR5K_PHY_PLL_RF5111, AR5K_PHY_PLL_RF5112, AR5K_PHY_TURBO, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_RESET_CTL_BASEBAND, AR5K_RESET_CTL_DMA, AR5K_RESET_CTL_MAC, AR5K_RESET_CTL_PCI, AR5K_RESET_CTL_PCU, AR5K_RESET_CTL_PHY, AR5K_RF5112, AR5K_RF5413, ath5k_hw_nic_reset(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_wake(), CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_CCK, CHANNEL_OFDM, CHANNEL_TURBO, DBG, EINVAL, EIO, mdelay(), PCI_CAP_ID_EXP, pci_find_capability(), ath5k_softc::pdev, u32, and udelay().
Referenced by ath5k_hw_attach(), and ath5k_hw_reset().
00291 { 00292 struct pci_device *pdev = ah->ah_sc->pdev; 00293 u32 turbo, mode, clock, bus_flags; 00294 int ret; 00295 00296 turbo = 0; 00297 mode = 0; 00298 clock = 0; 00299 00300 /* Wakeup the device */ 00301 ret = ath5k_hw_wake(ah); 00302 if (ret) { 00303 DBG("ath5k: failed to wake up the MAC chip\n"); 00304 return ret; 00305 } 00306 00307 if (ah->ah_version != AR5K_AR5210) { 00308 /* 00309 * Get channel mode flags 00310 */ 00311 00312 if (ah->ah_radio >= AR5K_RF5112) { 00313 mode = AR5K_PHY_MODE_RAD_RF5112; 00314 clock = AR5K_PHY_PLL_RF5112; 00315 } else { 00316 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/ 00317 clock = AR5K_PHY_PLL_RF5111; /*Zero*/ 00318 } 00319 00320 if (flags & CHANNEL_2GHZ) { 00321 mode |= AR5K_PHY_MODE_FREQ_2GHZ; 00322 clock |= AR5K_PHY_PLL_44MHZ; 00323 00324 if (flags & CHANNEL_CCK) { 00325 mode |= AR5K_PHY_MODE_MOD_CCK; 00326 } else if (flags & CHANNEL_OFDM) { 00327 /* XXX Dynamic OFDM/CCK is not supported by the 00328 * AR5211 so we set MOD_OFDM for plain g (no 00329 * CCK headers) operation. We need to test 00330 * this, 5211 might support ofdm-only g after 00331 * all, there are also initial register values 00332 * in the code for g mode (see initvals.c). */ 00333 if (ah->ah_version == AR5K_AR5211) 00334 mode |= AR5K_PHY_MODE_MOD_OFDM; 00335 else 00336 mode |= AR5K_PHY_MODE_MOD_DYN; 00337 } else { 00338 DBG("ath5k: invalid radio modulation mode\n"); 00339 return -EINVAL; 00340 } 00341 } else if (flags & CHANNEL_5GHZ) { 00342 mode |= AR5K_PHY_MODE_FREQ_5GHZ; 00343 00344 if (ah->ah_radio == AR5K_RF5413) 00345 clock = AR5K_PHY_PLL_40MHZ_5413; 00346 else 00347 clock |= AR5K_PHY_PLL_40MHZ; 00348 00349 if (flags & CHANNEL_OFDM) 00350 mode |= AR5K_PHY_MODE_MOD_OFDM; 00351 else { 00352 DBG("ath5k: invalid radio modulation mode\n"); 00353 return -EINVAL; 00354 } 00355 } else { 00356 DBG("ath5k: invalid radio frequency mode\n"); 00357 return -EINVAL; 00358 } 00359 00360 if (flags & CHANNEL_TURBO) 00361 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT; 00362 } else { /* Reset the device */ 00363 00364 /* ...enable Atheros turbo mode if requested */ 00365 if (flags & CHANNEL_TURBO) 00366 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, 00367 AR5K_PHY_TURBO); 00368 } 00369 00370 /* reseting PCI on PCI-E cards results card to hang 00371 * and always return 0xffff... so we ingore that flag 00372 * for PCI-E cards */ 00373 if (pci_find_capability(pdev, PCI_CAP_ID_EXP)) 00374 bus_flags = 0; 00375 else 00376 bus_flags = AR5K_RESET_CTL_PCI; 00377 00378 /* Reset chipset */ 00379 if (ah->ah_version == AR5K_AR5210) { 00380 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 00381 AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA | 00382 AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI); 00383 mdelay(2); 00384 } else { 00385 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | 00386 AR5K_RESET_CTL_BASEBAND | bus_flags); 00387 } 00388 if (ret) { 00389 DBG("ath5k: failed to reset the MAC chip\n"); 00390 return -EIO; 00391 } 00392 00393 /* ...wakeup again!*/ 00394 ret = ath5k_hw_wake(ah); 00395 if (ret) { 00396 DBG("ath5k: failed to resume the MAC chip\n"); 00397 return ret; 00398 } 00399 00400 /* ...final warm reset */ 00401 if (ath5k_hw_nic_reset(ah, 0)) { 00402 DBG("ath5k: failed to warm reset the MAC chip\n"); 00403 return -EIO; 00404 } 00405 00406 if (ah->ah_version != AR5K_AR5210) { 00407 00408 /* ...update PLL if needed */ 00409 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) { 00410 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL); 00411 udelay(300); 00412 } 00413 00414 /* ...set the PHY operating mode */ 00415 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE); 00416 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO); 00417 } 00418 00419 return 0; 00420 }
| int ath5k_hw_reset | ( | struct ath5k_hw * | ah, | |
| struct net80211_channel * | channel, | |||
| int | change_channel | |||
| ) |
Definition at line 698 of file ath5k_reset.c.
References ath5k_hw::ah_bssid, ath5k_hw::ah_calibration, ath5k_hw::ah_capabilities, ath5k_hw::ah_gpio, ath5k_hw::ah_imr, ath5k_hw::ah_mac_srev, ath5k_hw::ah_radio, ath5k_hw::ah_rf_banks, ath5k_hw::ah_sta_id, ath5k_hw::ah_version, AR5K_ANT_FIXED_A, AR5K_ANT_FIXED_B, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_BEACON, AR5K_BEACON_ENABLE, AR5K_BEACON_RESET_TSF, AR5K_DEFAULT_ANTENNA, AR5K_DMASIZE_128B, AR5K_EEPROM_HDR_RFKILL, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11B, AR5K_EEPROM_MODE_11G, AR5K_GPIOCR, AR5K_GPIODO, AR5K_HIGH_ID, AR5K_INI_RFGAIN_2GHZ, AR5K_INI_RFGAIN_5GHZ, AR5K_LOW_ID, AR5K_MIC_QOS_CTL, AR5K_MIC_QOS_SEL, AR5K_MODE_11A, AR5K_MODE_11A_TURBO, AR5K_MODE_11B, AR5K_MODE_11G, AR5K_MODE_11G_TURBO, AR5K_MODE_XR, AR5K_PCICFG, AR5K_PCICFG_LEDSTATE, AR5K_PHY, AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ADC_TEST, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL, AR5K_PHY_IQ, AR5K_PHY_IQ_CAL_NUM_LOG_MAX, AR5K_PHY_IQ_RUN, AR5K_PHY_RX_DELAY, AR5K_PHY_RX_DELAY_M, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY_TST1, AR5K_PHY_TST1_TXHOLD, AR5K_PISR, AR5K_QOS_NOACK, AR5K_QOS_NOACK_2BIT_VALUES, AR5K_QOS_NOACK_BIT_OFFSET, AR5K_QOS_NOACK_BYTE_OFFSET, AR5K_QUEUE_DCU_SEQNUM, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_BITS, AR5K_RF5111, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS_S, AR5K_RXCFG, AR5K_RXCFG_SDMAMW, AR5K_SREV_AR2413, AR5K_SREV_AR5211, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ACKCTS_6MB, AR5K_STA_ID1_BASE_RATE_11B, AR5K_STA_ID1_DEFAULT_ANTENNA, AR5K_STA_ID1_DESC_ANTENNA, AR5K_STA_ID1_RTS_DEF_ANTENNA, AR5K_STA_ID1_SELFGEN_DEF_ANT, AR5K_TUNE_BMISS_THRES, AR5K_TUNE_DEFAULT_TXPOWER, AR5K_TUNE_RSSI_THRES, AR5K_TXCFG, AR5K_TXCFG_B_MODE, AR5K_TXCFG_SDMAMR, ath5k_hw_channel(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_gpio(), ath5k_hw_nic_wakeup(), ath5k_hw_noise_floor_calibration(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_reset_tx_queue(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_set_associd(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_imr(), ath5k_hw_set_opmode(), ath5k_hw_tweak_initval_settings(), ath5k_hw_txpower(), ath5k_hw_write_initvals(), ath5k_hw_write_ofdm_timings(), ath5k_hw_write_rate_duration(), ath5k_capabilities::cap_eeprom, net80211_channel::center_freq, CHANNEL_A, CHANNEL_B, CHANNEL_CCK, CHANNEL_G, CHANNEL_MODES, CHANNEL_OFDM, CHANNEL_T, CHANNEL_TG, CHANNEL_XR, DBG, delay, ath5k_eeprom_info::ee_header, EINVAL, net80211_channel::hw_value, mdelay(), NULL, u32, u8, and udelay().
Referenced by ath5k_reset().
00700 { 00701 u32 s_seq[10], s_ant, s_led[3], staid1_flags, tsf_up, tsf_lo; 00702 u32 phy_tst1; 00703 u8 mode, freq, ee_mode, ant[2]; 00704 int i, ret; 00705 00706 s_ant = 0; 00707 ee_mode = 0; 00708 staid1_flags = 0; 00709 tsf_up = 0; 00710 tsf_lo = 0; 00711 freq = 0; 00712 mode = 0; 00713 00714 /* 00715 * Save some registers before a reset 00716 */ 00717 /*DCU/Antenna selection not available on 5210*/ 00718 if (ah->ah_version != AR5K_AR5210) { 00719 00720 switch (channel->hw_value & CHANNEL_MODES) { 00721 case CHANNEL_A: 00722 mode = AR5K_MODE_11A; 00723 freq = AR5K_INI_RFGAIN_5GHZ; 00724 ee_mode = AR5K_EEPROM_MODE_11A; 00725 break; 00726 case CHANNEL_G: 00727 mode = AR5K_MODE_11G; 00728 freq = AR5K_INI_RFGAIN_2GHZ; 00729 ee_mode = AR5K_EEPROM_MODE_11G; 00730 break; 00731 case CHANNEL_B: 00732 mode = AR5K_MODE_11B; 00733 freq = AR5K_INI_RFGAIN_2GHZ; 00734 ee_mode = AR5K_EEPROM_MODE_11B; 00735 break; 00736 case CHANNEL_T: 00737 mode = AR5K_MODE_11A_TURBO; 00738 freq = AR5K_INI_RFGAIN_5GHZ; 00739 ee_mode = AR5K_EEPROM_MODE_11A; 00740 break; 00741 case CHANNEL_TG: 00742 if (ah->ah_version == AR5K_AR5211) { 00743 DBG("ath5k: TurboG not available on 5211\n"); 00744 return -EINVAL; 00745 } 00746 mode = AR5K_MODE_11G_TURBO; 00747 freq = AR5K_INI_RFGAIN_2GHZ; 00748 ee_mode = AR5K_EEPROM_MODE_11G; 00749 break; 00750 case CHANNEL_XR: 00751 if (ah->ah_version == AR5K_AR5211) { 00752 DBG("ath5k: XR mode not available on 5211\n"); 00753 return -EINVAL; 00754 } 00755 mode = AR5K_MODE_XR; 00756 freq = AR5K_INI_RFGAIN_5GHZ; 00757 ee_mode = AR5K_EEPROM_MODE_11A; 00758 break; 00759 default: 00760 DBG("ath5k: invalid channel (%d MHz)\n", 00761 channel->center_freq); 00762 return -EINVAL; 00763 } 00764 00765 if (change_channel) { 00766 /* 00767 * Save frame sequence count 00768 * For revs. after Oahu, only save 00769 * seq num for DCU 0 (Global seq num) 00770 */ 00771 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 00772 00773 for (i = 0; i < 10; i++) 00774 s_seq[i] = ath5k_hw_reg_read(ah, 00775 AR5K_QUEUE_DCU_SEQNUM(i)); 00776 00777 } else { 00778 s_seq[0] = ath5k_hw_reg_read(ah, 00779 AR5K_QUEUE_DCU_SEQNUM(0)); 00780 } 00781 } 00782 00783 /* Save default antenna */ 00784 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); 00785 00786 if (ah->ah_version == AR5K_AR5212) { 00787 /* Since we are going to write rf buffer 00788 * check if we have any pending gain_F 00789 * optimization settings */ 00790 if (change_channel && ah->ah_rf_banks != NULL) 00791 ath5k_hw_gainf_calibrate(ah); 00792 } 00793 } 00794 00795 /*GPIOs*/ 00796 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & 00797 AR5K_PCICFG_LEDSTATE; 00798 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR); 00799 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO); 00800 00801 /* AR5K_STA_ID1 flags, only preserve antenna 00802 * settings and ack/cts rate mode */ 00803 staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 00804 (AR5K_STA_ID1_DEFAULT_ANTENNA | 00805 AR5K_STA_ID1_DESC_ANTENNA | 00806 AR5K_STA_ID1_RTS_DEF_ANTENNA | 00807 AR5K_STA_ID1_ACKCTS_6MB | 00808 AR5K_STA_ID1_BASE_RATE_11B | 00809 AR5K_STA_ID1_SELFGEN_DEF_ANT); 00810 00811 /* Wakeup the device */ 00812 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, 0); 00813 if (ret) 00814 return ret; 00815 00816 /* PHY access enable */ 00817 if (ah->ah_mac_srev >= AR5K_SREV_AR5211) 00818 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 00819 else 00820 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40, 00821 AR5K_PHY(0)); 00822 00823 /* Write initial settings */ 00824 ret = ath5k_hw_write_initvals(ah, mode, change_channel); 00825 if (ret) 00826 return ret; 00827 00828 /* 00829 * 5211/5212 Specific 00830 */ 00831 if (ah->ah_version != AR5K_AR5210) { 00832 00833 /* 00834 * Write initial RF gain settings 00835 * This should work for both 5111/5112 00836 */ 00837 ret = ath5k_hw_rfgain_init(ah, freq); 00838 if (ret) 00839 return ret; 00840 00841 mdelay(1); 00842 00843 /* 00844 * Tweak initval settings for revised 00845 * chipsets and add some more config 00846 * bits 00847 */ 00848 ath5k_hw_tweak_initval_settings(ah, channel); 00849 00850 /* 00851 * Set TX power (FIXME) 00852 */ 00853 ret = ath5k_hw_txpower(ah, channel, ee_mode, 00854 AR5K_TUNE_DEFAULT_TXPOWER); 00855 if (ret) 00856 return ret; 00857 00858 /* Write rate duration table only on AR5212 */ 00859 if (ah->ah_version == AR5K_AR5212) 00860 ath5k_hw_write_rate_duration(ah, mode); 00861 00862 /* 00863 * Write RF buffer 00864 */ 00865 ret = ath5k_hw_rfregs_init(ah, channel, mode); 00866 if (ret) 00867 return ret; 00868 00869 00870 /* Write OFDM timings on 5212*/ 00871 if (ah->ah_version == AR5K_AR5212 && 00872 channel->hw_value & CHANNEL_OFDM) { 00873 ret = ath5k_hw_write_ofdm_timings(ah, channel); 00874 if (ret) 00875 return ret; 00876 } 00877 00878 /*Enable/disable 802.11b mode on 5111 00879 (enable 2111 frequency converter + CCK)*/ 00880 if (ah->ah_radio == AR5K_RF5111) { 00881 if (mode == AR5K_MODE_11B) 00882 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, 00883 AR5K_TXCFG_B_MODE); 00884 else 00885 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, 00886 AR5K_TXCFG_B_MODE); 00887 } 00888 00889 /* 00890 * In case a fixed antenna was set as default 00891 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE 00892 * registers. 00893 */ 00894 if (s_ant != 0) { 00895 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */ 00896 ant[0] = ant[1] = AR5K_ANT_FIXED_A; 00897 else /* 2 - Aux */ 00898 ant[0] = ant[1] = AR5K_ANT_FIXED_B; 00899 } else { 00900 ant[0] = AR5K_ANT_FIXED_A; 00901 ant[1] = AR5K_ANT_FIXED_B; 00902 } 00903 00904 /* Commit values from EEPROM */ 00905 ath5k_hw_commit_eeprom_settings(ah, channel, ant, ee_mode); 00906 00907 } else { 00908 /* 00909 * For 5210 we do all initialization using 00910 * initvals, so we don't have to modify 00911 * any settings (5210 also only supports 00912 * a/aturbo modes) 00913 */ 00914 mdelay(1); 00915 /* Disable phy and wait */ 00916 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 00917 mdelay(1); 00918 } 00919 00920 /* 00921 * Restore saved values 00922 */ 00923 00924 /*DCU/Antenna selection not available on 5210*/ 00925 if (ah->ah_version != AR5K_AR5210) { 00926 00927 if (change_channel) { 00928 if (ah->ah_mac_srev < AR5K_SREV_AR5211) { 00929 for (i = 0; i < 10; i++) 00930 ath5k_hw_reg_write(ah, s_seq[i], 00931 AR5K_QUEUE_DCU_SEQNUM(i)); 00932 } else { 00933 ath5k_hw_reg_write(ah, s_seq[0], 00934 AR5K_QUEUE_DCU_SEQNUM(0)); 00935 } 00936 } 00937 00938 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA); 00939 } 00940 00941 /* Ledstate */ 00942 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]); 00943 00944 /* Gpio settings */ 00945 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); 00946 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); 00947 00948 /* Restore sta_id flags and preserve our mac address*/ 00949 ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_sta_id), 00950 AR5K_STA_ID0); 00951 ath5k_hw_reg_write(ah, staid1_flags | AR5K_HIGH_ID(ah->ah_sta_id), 00952 AR5K_STA_ID1); 00953 00954 00955 /* 00956 * Configure PCU 00957 */ 00958 00959 /* Restore bssid and bssid mask */ 00960 /* XXX: add ah->aid once mac80211 gives this to us */ 00961 ath5k_hw_set_associd(ah, ah->ah_bssid, 0); 00962 00963 /* Set PCU config */ 00964 ath5k_hw_set_opmode(ah); 00965 00966 /* Clear any pending interrupts 00967 * PISR/SISR Not available on 5210 */ 00968 if (ah->ah_version != AR5K_AR5210) 00969 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); 00970 00971 /* Set RSSI/BRSSI thresholds 00972 * 00973 * Note: If we decide to set this value 00974 * dynamicaly, have in mind that when AR5K_RSSI_THR 00975 * register is read it might return 0x40 if we haven't 00976 * wrote anything to it plus BMISS RSSI threshold is zeroed. 00977 * So doing a save/restore procedure here isn't the right 00978 * choice. Instead store it on ath5k_hw */ 00979 ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES | 00980 AR5K_TUNE_BMISS_THRES << 00981 AR5K_RSSI_THR_BMISS_S), 00982 AR5K_RSSI_THR); 00983 00984 /* MIC QoS support */ 00985 if (ah->ah_mac_srev >= AR5K_SREV_AR2413) { 00986 ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL); 00987 ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL); 00988 } 00989 00990 /* QoS NOACK Policy */ 00991 if (ah->ah_version == AR5K_AR5212) { 00992 ath5k_hw_reg_write(ah, 00993 AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) | 00994 AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET) | 00995 AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET), 00996 AR5K_QOS_NOACK); 00997 } 00998 00999 01000 /* 01001 * Configure PHY 01002 */ 01003 01004 /* Set channel on PHY */ 01005 ret = ath5k_hw_channel(ah, channel); 01006 if (ret) 01007 return ret; 01008 01009 /* 01010 * Enable the PHY and wait until completion 01011 * This includes BaseBand and Synthesizer 01012 * activation. 01013 */ 01014 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); 01015 01016 /* 01017 * On 5211+ read activation -> rx delay 01018 * and use it. 01019 * 01020 * TODO: Half/quarter rate support 01021 */ 01022 if (ah->ah_version != AR5K_AR5210) { 01023 u32 delay; 01024 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & 01025 AR5K_PHY_RX_DELAY_M; 01026 delay = (channel->hw_value & CHANNEL_CCK) ? 01027 ((delay << 2) / 22) : (delay / 10); 01028 01029 udelay(100 + (2 * delay)); 01030 } else { 01031 mdelay(1); 01032 } 01033 01034 /* 01035 * Perform ADC test to see if baseband is ready 01036 * Set tx hold and check adc test register 01037 */ 01038 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); 01039 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); 01040 for (i = 0; i <= 20; i++) { 01041 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) 01042 break; 01043 udelay(200); 01044 } 01045 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); 01046 01047 /* 01048 * Start automatic gain control calibration 01049 * 01050 * During AGC calibration RX path is re-routed to 01051 * a power detector so we don't receive anything. 01052 * 01053 * This method is used to calibrate some static offsets 01054 * used together with on-the fly I/Q calibration (the 01055 * one performed via ath5k_hw_phy_calibrate), that doesn't 01056 * interrupt rx path. 01057 * 01058 * While rx path is re-routed to the power detector we also 01059 * start a noise floor calibration, to measure the 01060 * card's noise floor (the noise we measure when we are not 01061 * transmiting or receiving anything). 01062 * 01063 * If we are in a noisy environment AGC calibration may time 01064 * out and/or noise floor calibration might timeout. 01065 */ 01066 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 01067 AR5K_PHY_AGCCTL_CAL); 01068 01069 /* At the same time start I/Q calibration for QAM constellation 01070 * -no need for CCK- */ 01071 ah->ah_calibration = 0; 01072 if (!(mode == AR5K_MODE_11B)) { 01073 ah->ah_calibration = 1; 01074 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, 01075 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15); 01076 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, 01077 AR5K_PHY_IQ_RUN); 01078 } 01079 01080 /* Wait for gain calibration to finish (we check for I/Q calibration 01081 * during ath5k_phy_calibrate) */ 01082 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 01083 AR5K_PHY_AGCCTL_CAL, 0, 0)) { 01084 DBG("ath5k: gain calibration timeout (%d MHz)\n", 01085 channel->center_freq); 01086 } 01087 01088 /* 01089 * If we run NF calibration before AGC, it always times out. 01090 * Binary HAL starts NF and AGC calibration at the same time 01091 * and only waits for AGC to finish. Also if AGC or NF cal. 01092 * times out, reset doesn't fail on binary HAL. I believe 01093 * that's wrong because since rx path is routed to a detector, 01094 * if cal. doesn't finish we won't have RX. Sam's HAL for AR5210/5211 01095 * enables noise floor calibration after offset calibration and if noise 01096 * floor calibration fails, reset fails. I believe that's 01097 * a better approach, we just need to find a polling interval 01098 * that suits best, even if reset continues we need to make 01099 * sure that rx path is ready. 01100 */ 01101 ath5k_hw_noise_floor_calibration(ah, channel->center_freq); 01102 01103 01104 /* 01105 * Configure QCUs/DCUs 01106 */ 01107 01108 /* TODO: HW Compression support for data queues */ 01109 /* TODO: Burst prefetch for data queues */ 01110 01111 /* 01112 * Reset queues and start beacon timers at the end of the reset routine 01113 * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping 01114 * Note: If we want we can assign multiple qcus on one dcu. 01115 */ 01116 ret = ath5k_hw_reset_tx_queue(ah); 01117 if (ret) { 01118 DBG("ath5k: failed to reset TX queue\n"); 01119 return ret; 01120 } 01121 01122 /* 01123 * Configure DMA/Interrupts 01124 */ 01125 01126 /* 01127 * Set Rx/Tx DMA Configuration 01128 * 01129 * Set standard DMA size (128). Note that 01130 * a DMA size of 512 causes rx overruns and tx errors 01131 * on pci-e cards (tested on 5424 but since rx overruns 01132 * also occur on 5416/5418 with madwifi we set 128 01133 * for all PCI-E cards to be safe). 01134 * 01135 * XXX: need to check 5210 for this 01136 * TODO: Check out tx triger level, it's always 64 on dumps but I 01137 * guess we can tweak it and see how it goes ;-) 01138 */ 01139 if (ah->ah_version != AR5K_AR5210) { 01140 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 01141 AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B); 01142 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, 01143 AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B); 01144 } 01145 01146 /* Pre-enable interrupts on 5211/5212*/ 01147 if (ah->ah_version != AR5K_AR5210) 01148 ath5k_hw_set_imr(ah, ah->ah_imr); 01149 01150 /* 01151 * Setup RFKill interrupt if rfkill flag is set on eeprom. 01152 * TODO: Use gpio pin and polarity infos from eeprom 01153 * TODO: Handle this in ath5k_intr because it'll result 01154 * a nasty interrupt storm. 01155 */ 01156 #if 0 01157 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) { 01158 ath5k_hw_set_gpio_input(ah, 0); 01159 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0); 01160 if (ah->ah_gpio[0] == 0) 01161 ath5k_hw_set_gpio_intr(ah, 0, 1); 01162 else 01163 ath5k_hw_set_gpio_intr(ah, 0, 0); 01164 } 01165 #endif 01166 01167 /* 01168 * Disable beacons and reset the register 01169 */ 01170 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE | 01171 AR5K_BEACON_RESET_TSF); 01172 01173 return 0; 01174 }
| int ath5k_hw_set_power | ( | struct ath5k_hw * | ah, | |
| enum ath5k_power_mode | mode, | |||
| int | set_chip, | |||
| u16 | sleep_duration | |||
| ) |
| void ath5k_hw_start_rx_dma | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_start_rx_dma - Start DMA receive
: The &struct ath5k_hw
Definition at line 54 of file ath5k_dma.c.
References AR5K_CR, AR5K_CR_RXE, ath5k_hw_reg_read(), and ath5k_hw_reg_write().
Referenced by ath5k_rx_start().
00055 { 00056 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); 00057 ath5k_hw_reg_read(ah, AR5K_CR); 00058 }
| int ath5k_hw_stop_rx_dma | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_stop_rx_dma - Stop DMA receive
: The &struct ath5k_hw
Definition at line 65 of file ath5k_dma.c.
References AR5K_CR, AR5K_CR_RXD, AR5K_CR_RXE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, and udelay().
Referenced by ath5k_rx_stop().
00066 { 00067 unsigned int i; 00068 00069 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); 00070 00071 /* 00072 * It may take some time to disable the DMA receive unit 00073 */ 00074 for (i = 1000; i > 0 && 00075 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; 00076 i--) 00077 udelay(10); 00078 00079 return i ? 0 : -EBUSY; 00080 }
ath5k_hw_get_rxdp - Get RX Descriptor's address
: The &struct ath5k_hw
XXX: Is RXDP read and clear ?
Definition at line 89 of file ath5k_dma.c.
References AR5K_RXDP, and ath5k_hw_reg_read().
00090 { 00091 return ath5k_hw_reg_read(ah, AR5K_RXDP); 00092 }
ath5k_hw_set_rxdp - Set RX Descriptor's address
: The &struct ath5k_hw : RX descriptor address
XXX: Should we check if rx is enabled before setting rxdp ?
Definition at line 102 of file ath5k_dma.c.
References AR5K_RXDP, and ath5k_hw_reg_write().
Referenced by ath5k_rx_start().
00103 { 00104 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP); 00105 }
| int ath5k_hw_start_tx_dma | ( | struct ath5k_hw * | ah, | |
| unsigned int | queue | |||
| ) |
ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue
: The &struct ath5k_hw : The hw queue number
Start DMA transmit for a specific queue and since 5210 doesn't have QCU/DCU, set up queue parameters for 5210 here based on queue type (one queue for normal data and one queue for beacons). For queue setup on newer chips check out qcu.c. Returns -EINVAL if queue number is out of range or if queue is already disabled.
NOTE: Must be called after setting up tx control descriptor for that queue (see below).
Definition at line 127 of file ath5k_dma.c.
References ath5k_hw::ah_txq, ath5k_hw::ah_version, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_QCU_TXD, AR5K_QCU_TXE, AR5K_REG_READ_Q, AR5K_REG_WRITE_Q, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EIO, ath5k_txq_info::tqi_type, and u32.
Referenced by ath5k_txbuf_setup().
00128 { 00129 u32 tx_queue; 00130 00131 /* Return if queue is declared inactive */ 00132 if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE) 00133 return -EIO; 00134 00135 if (ah->ah_version == AR5K_AR5210) { 00136 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); 00137 00138 /* Assume always a data queue */ 00139 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; 00140 00141 /* Start queue */ 00142 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); 00143 ath5k_hw_reg_read(ah, AR5K_CR); 00144 } else { 00145 /* Return if queue is disabled */ 00146 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) 00147 return -EIO; 00148 00149 /* Start queue */ 00150 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue); 00151 } 00152 00153 return 0; 00154 }
| int ath5k_hw_stop_tx_dma | ( | struct ath5k_hw * | ah, | |
| unsigned int | queue | |||
| ) |
ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue
: The &struct ath5k_hw : The hw queue number
Stop DMA transmit on a specific hw queue and drain queue so we don't have any pending frames. Returns -EBUSY if we still have pending frames, -EINVAL if queue number is out of range.
Definition at line 167 of file ath5k_dma.c.
References ath5k_hw::ah_mac_version, ath5k_hw::ah_txq, ath5k_hw::ah_version, AR5K_AR5210, AR5K_CR, AR5K_CR_TXD0, AR5K_CR_TXE0, AR5K_DIAG_SW_5211, AR5K_DIAG_SW_CHANEL_IDLE_HIGH, AR5K_QCU_STS_FRMPENDCNT, AR5K_QCU_TXD, AR5K_QUEUE_STATUS, AR5K_QUIET_CTL1, AR5K_QUIET_CTL1_NEXT_QT_TSF, AR5K_QUIET_CTL1_QT_EN, AR5K_QUIET_CTL2, AR5K_QUIET_CTL2_QT_DUR, AR5K_QUIET_CTL2_QT_PER, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SREV_AR2414, AR5K_TSF_L32_5211, AR5K_TX_QUEUE_INACTIVE, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EBUSY, EIO, ath5k_txq_info::tqi_type, u32, and udelay().
Referenced by ath5k_txq_cleanup().
00168 { 00169 unsigned int i = 40; 00170 u32 tx_queue, pending; 00171 00172 /* Return if queue is declared inactive */ 00173 if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE) 00174 return -EIO; 00175 00176 if (ah->ah_version == AR5K_AR5210) { 00177 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); 00178 00179 /* Assume a data queue */ 00180 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; 00181 00182 /* Stop queue */ 00183 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); 00184 ath5k_hw_reg_read(ah, AR5K_CR); 00185 } else { 00186 /* 00187 * Schedule TX disable and wait until queue is empty 00188 */ 00189 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue); 00190 00191 /*Check for pending frames*/ 00192 do { 00193 pending = ath5k_hw_reg_read(ah, 00194 AR5K_QUEUE_STATUS(queue)) & 00195 AR5K_QCU_STS_FRMPENDCNT; 00196 udelay(100); 00197 } while (--i && pending); 00198 00199 /* For 2413+ order PCU to drop packets using 00200 * QUIET mechanism */ 00201 if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && pending) { 00202 /* Set periodicity and duration */ 00203 ath5k_hw_reg_write(ah, 00204 AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)| 00205 AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR), 00206 AR5K_QUIET_CTL2); 00207 00208 /* Enable quiet period for current TSF */ 00209 ath5k_hw_reg_write(ah, 00210 AR5K_QUIET_CTL1_QT_EN | 00211 AR5K_REG_SM(ath5k_hw_reg_read(ah, 00212 AR5K_TSF_L32_5211) >> 10, 00213 AR5K_QUIET_CTL1_NEXT_QT_TSF), 00214 AR5K_QUIET_CTL1); 00215 00216 /* Force channel idle high */ 00217 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, 00218 AR5K_DIAG_SW_CHANEL_IDLE_HIGH); 00219 00220 /* Wait a while and disable mechanism */ 00221 udelay(200); 00222 AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1, 00223 AR5K_QUIET_CTL1_QT_EN); 00224 00225 /* Re-check for pending frames */ 00226 i = 40; 00227 do { 00228 pending = ath5k_hw_reg_read(ah, 00229 AR5K_QUEUE_STATUS(queue)) & 00230 AR5K_QCU_STS_FRMPENDCNT; 00231 udelay(100); 00232 } while (--i && pending); 00233 00234 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211, 00235 AR5K_DIAG_SW_CHANEL_IDLE_HIGH); 00236 } 00237 00238 /* Clear register */ 00239 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD); 00240 if (pending) 00241 return -EBUSY; 00242 } 00243 00244 /* TODO: Check for success on 5210 else return error */ 00245 return 0; 00246 }
ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
: The &struct ath5k_hw : The hw queue number
Get TX descriptor's address for a specific queue. For 5210 we ignore the queue number and use tx queue type since we only have 2 queues. We use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just read the corresponding TXDP register.
XXX: Is TXDP read and clear ?
Definition at line 261 of file ath5k_dma.c.
References ath5k_hw::ah_version, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QUEUE_TXDP, ath5k_hw_reg_read(), and u16.
Referenced by ath5k_txq_cleanup().
00262 { 00263 u16 tx_reg; 00264 00265 /* 00266 * Get the transmit queue descriptor pointer from the selected queue 00267 */ 00268 /*5210 doesn't have QCU*/ 00269 if (ah->ah_version == AR5K_AR5210) { 00270 /* Assume a data queue */ 00271 tx_reg = AR5K_NOQCU_TXDP0; 00272 } else { 00273 tx_reg = AR5K_QUEUE_TXDP(queue); 00274 } 00275 00276 return ath5k_hw_reg_read(ah, tx_reg); 00277 }
ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue
: The &struct ath5k_hw : The hw queue number
Set TX descriptor's address for a specific queue. For 5210 we ignore the queue number and we use tx queue type since we only have 2 queues so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. For newer chips with QCU/DCU we just set the corresponding TXDP register. Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still active.
Definition at line 292 of file ath5k_dma.c.
References ath5k_hw::ah_version, AR5K_AR5210, AR5K_NOQCU_TXDP0, AR5K_QCU_TXE, AR5K_QUEUE_TXDP, AR5K_REG_READ_Q, ath5k_hw_reg_write(), EIO, and u16.
Referenced by ath5k_txbuf_setup().
00293 { 00294 u16 tx_reg; 00295 00296 /* 00297 * Set the transmit queue descriptor pointer register by type 00298 * on 5210 00299 */ 00300 if (ah->ah_version == AR5K_AR5210) { 00301 /* Assume a data queue */ 00302 tx_reg = AR5K_NOQCU_TXDP0; 00303 } else { 00304 /* 00305 * Set the transmit queue descriptor pointer for 00306 * the selected queue on QCU for 5211+ 00307 * (this won't work if the queue is still active) 00308 */ 00309 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) 00310 return -EIO; 00311 00312 tx_reg = AR5K_QUEUE_TXDP(queue); 00313 } 00314 00315 /* Set descriptor pointer */ 00316 ath5k_hw_reg_write(ah, phys_addr, tx_reg); 00317 00318 return 0; 00319 }
| int ath5k_hw_update_tx_triglevel | ( | struct ath5k_hw * | ah, | |
| int | increase | |||
| ) |
ath5k_hw_update_tx_triglevel - Update tx trigger level
: The &struct ath5k_hw : Flag to force increase of trigger level
This function increases/decreases the tx trigger level for the tx fifo buffer (aka FIFO threshold) that is used to indicate when PCU flushes the buffer and transmits it's data. Lowering this results sending small frames more quickly but can lead to tx underruns, raising it a lot can result other problems (i think bmiss is related). Right now we start with the lowest possible (64Bytes) and if we get tx underrun we increase it using the increase flag. Returns -EIO if we have have reached maximum/minimum.
XXX: Link this with tx DMA size ? XXX: Use it to save interrupts ? TODO: Needs testing, i think it's related to bmiss...
Definition at line 339 of file ath5k_dma.c.
References ath5k_hw::ah_imr, ath5k_hw::ah_version, AR5K_AR5210, AR5K_INT_GLOBAL, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TRIG_LVL, AR5K_TUNE_MAX_TX_FIFO_THRES, AR5K_TUNE_MIN_TX_FIFO_THRES, AR5K_TXCFG, AR5K_TXCFG_TXFULL, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ath5k_hw_set_imr(), EIO, imr, and u32.
Referenced by ath5k_poll().
00340 { 00341 u32 trigger_level, imr; 00342 int ret = -EIO; 00343 00344 /* 00345 * Disable interrupts by setting the mask 00346 */ 00347 imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL); 00348 00349 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), 00350 AR5K_TXCFG_TXFULL); 00351 00352 if (!increase) { 00353 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) 00354 goto done; 00355 } else 00356 trigger_level += 00357 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); 00358 00359 /* 00360 * Update trigger level on success 00361 */ 00362 if (ah->ah_version == AR5K_AR5210) 00363 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL); 00364 else 00365 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, 00366 AR5K_TXCFG_TXFULL, trigger_level); 00367 00368 ret = 0; 00369 00370 done: 00371 /* 00372 * Restore interrupt mask 00373 */ 00374 ath5k_hw_set_imr(ah, imr); 00375 00376 return ret; 00377 }
| int ath5k_hw_is_intr_pending | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_is_intr_pending - Check if we have pending interrupts
: The &struct ath5k_hw
Check if we have pending interrupts to process. Returns 1 if we have pending interrupts and 0 if we haven't.
Definition at line 391 of file ath5k_dma.c.
References AR5K_INTPEND, and ath5k_hw_reg_read().
Referenced by ath5k_poll().
00392 { 00393 return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0; 00394 }
Definition at line 412 of file ath5k_dma.c.
References ath5k_hw::ah_imr, ath5k_hw::ah_txq_isr, ath5k_hw::ah_version, AR5K_AR5210, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_NOCARD, AR5K_INT_QCBRORN, AR5K_INT_QCBRURN, AR5K_INT_QTRIG, AR5K_INT_RX_DOPPLER, AR5K_INT_TIM, AR5K_ISR, AR5K_ISR_BCNMISC, AR5K_ISR_BNR, AR5K_ISR_DPERR, AR5K_ISR_HIUERR, AR5K_ISR_MCABT, AR5K_ISR_QCBRORN, AR5K_ISR_QCBRURN, AR5K_ISR_QTRIG, AR5K_ISR_RXDOPPLER, AR5K_ISR_SSERR, AR5K_ISR_TIM, AR5K_ISR_TXDESC, AR5K_ISR_TXEOL, AR5K_ISR_TXERR, AR5K_ISR_TXOK, AR5K_ISR_TXURN, AR5K_RAC_PISR, AR5K_RAC_SISR0, AR5K_RAC_SISR1, AR5K_RAC_SISR2, AR5K_RAC_SISR3, AR5K_RAC_SISR4, AR5K_REG_MS, AR5K_SISR0_QCU_TXDESC, AR5K_SISR0_QCU_TXOK, AR5K_SISR1_QCU_TXEOL, AR5K_SISR1_QCU_TXERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DPERR, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_MCABT, AR5K_SISR2_QCU_TXURN, AR5K_SISR2_SSERR, AR5K_SISR2_TIM, AR5K_SISR3_QCBRORN, AR5K_SISR3_QCBRURN, AR5K_SISR4_QTRIG, ath5k_hw_reg_read(), ENODEV, and u32.
Referenced by ath5k_poll().
00413 { 00414 u32 data; 00415 00416 /* 00417 * Read interrupt status from the Interrupt Status register 00418 * on 5210 00419 */ 00420 if (ah->ah_version == AR5K_AR5210) { 00421 data = ath5k_hw_reg_read(ah, AR5K_ISR); 00422 if (data == AR5K_INT_NOCARD) { 00423 *interrupt_mask = data; 00424 return -ENODEV; 00425 } 00426 } else { 00427 /* 00428 * Read interrupt status from Interrupt 00429 * Status Register shadow copy (Read And Clear) 00430 * 00431 * Note: PISR/SISR Not available on 5210 00432 */ 00433 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR); 00434 if (data == AR5K_INT_NOCARD) { 00435 *interrupt_mask = data; 00436 return -ENODEV; 00437 } 00438 } 00439 00440 /* 00441 * Get abstract interrupt mask (driver-compatible) 00442 */ 00443 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr; 00444 00445 if (ah->ah_version != AR5K_AR5210) { 00446 u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2); 00447 00448 /*HIU = Host Interface Unit (PCI etc)*/ 00449 if (data & (AR5K_ISR_HIUERR)) 00450 *interrupt_mask |= AR5K_INT_FATAL; 00451 00452 /*Beacon Not Ready*/ 00453 if (data & (AR5K_ISR_BNR)) 00454 *interrupt_mask |= AR5K_INT_BNR; 00455 00456 if (sisr2 & (AR5K_SISR2_SSERR | AR5K_SISR2_DPERR | 00457 AR5K_SISR2_MCABT)) 00458 *interrupt_mask |= AR5K_INT_FATAL; 00459 00460 if (data & AR5K_ISR_TIM) 00461 *interrupt_mask |= AR5K_INT_TIM; 00462 00463 if (data & AR5K_ISR_BCNMISC) { 00464 if (sisr2 & AR5K_SISR2_TIM) 00465 *interrupt_mask |= AR5K_INT_TIM; 00466 if (sisr2 & AR5K_SISR2_DTIM) 00467 *interrupt_mask |= AR5K_INT_DTIM; 00468 if (sisr2 & AR5K_SISR2_DTIM_SYNC) 00469 *interrupt_mask |= AR5K_INT_DTIM_SYNC; 00470 if (sisr2 & AR5K_SISR2_BCN_TIMEOUT) 00471 *interrupt_mask |= AR5K_INT_BCN_TIMEOUT; 00472 if (sisr2 & AR5K_SISR2_CAB_TIMEOUT) 00473 *interrupt_mask |= AR5K_INT_CAB_TIMEOUT; 00474 } 00475 00476 if (data & AR5K_ISR_RXDOPPLER) 00477 *interrupt_mask |= AR5K_INT_RX_DOPPLER; 00478 if (data & AR5K_ISR_QCBRORN) { 00479 *interrupt_mask |= AR5K_INT_QCBRORN; 00480 ah->ah_txq_isr |= AR5K_REG_MS( 00481 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), 00482 AR5K_SISR3_QCBRORN); 00483 } 00484 if (data & AR5K_ISR_QCBRURN) { 00485 *interrupt_mask |= AR5K_INT_QCBRURN; 00486 ah->ah_txq_isr |= AR5K_REG_MS( 00487 ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), 00488 AR5K_SISR3_QCBRURN); 00489 } 00490 if (data & AR5K_ISR_QTRIG) { 00491 *interrupt_mask |= AR5K_INT_QTRIG; 00492 ah->ah_txq_isr |= AR5K_REG_MS( 00493 ath5k_hw_reg_read(ah, AR5K_RAC_SISR4), 00494 AR5K_SISR4_QTRIG); 00495 } 00496 00497 if (data & AR5K_ISR_TXOK) 00498 ah->ah_txq_isr |= AR5K_REG_MS( 00499 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), 00500 AR5K_SISR0_QCU_TXOK); 00501 00502 if (data & AR5K_ISR_TXDESC) 00503 ah->ah_txq_isr |= AR5K_REG_MS( 00504 ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), 00505 AR5K_SISR0_QCU_TXDESC); 00506 00507 if (data & AR5K_ISR_TXERR) 00508 ah->ah_txq_isr |= AR5K_REG_MS( 00509 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), 00510 AR5K_SISR1_QCU_TXERR); 00511 00512 if (data & AR5K_ISR_TXEOL) 00513 ah->ah_txq_isr |= AR5K_REG_MS( 00514 ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), 00515 AR5K_SISR1_QCU_TXEOL); 00516 00517 if (data & AR5K_ISR_TXURN) 00518 ah->ah_txq_isr |= AR5K_REG_MS( 00519 ath5k_hw_reg_read(ah, AR5K_RAC_SISR2), 00520 AR5K_SISR2_QCU_TXURN); 00521 } else { 00522 if (data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT | 00523 AR5K_ISR_HIUERR | AR5K_ISR_DPERR)) 00524 *interrupt_mask |= AR5K_INT_FATAL; 00525 00526 /* 00527 * XXX: BMISS interrupts may occur after association. 00528 * I found this on 5210 code but it needs testing. If this is 00529 * true we should disable them before assoc and re-enable them 00530 * after a successful assoc + some jiffies. 00531 interrupt_mask &= ~AR5K_INT_BMISS; 00532 */ 00533 } 00534 00535 return 0; 00536 }
ath5k_hw_set_imr - Set interrupt mask
: The &struct ath5k_hw : The new interrupt mask to be set
Set the interrupt mask in hw to save interrupts. We do that by mapping ath5k_int bits to hw-specific bits to remove abstraction and writing Interrupt Mask Register.
Definition at line 548 of file ath5k_dma.c.
References ath5k_hw::ah_ier, ath5k_hw::ah_imr, ath5k_hw::ah_version, AR5K_AR5210, AR5K_IER, AR5K_IER_DISABLE, AR5K_IMR, AR5K_IMR_DPERR, AR5K_IMR_HIUERR, AR5K_IMR_MCABT, AR5K_IMR_RXDOPPLER, AR5K_IMR_SSERR, AR5K_IMR_TIM, AR5K_INT_BCN_TIMEOUT, AR5K_INT_BNR, AR5K_INT_CAB_TIMEOUT, AR5K_INT_COMMON, AR5K_INT_DTIM, AR5K_INT_DTIM_SYNC, AR5K_INT_FATAL, AR5K_INT_GLOBAL, AR5K_INT_RX_DOPPLER, AR5K_INT_RXNOFRM, AR5K_INT_TIM, AR5K_PIMR, AR5K_RXNOFRM, AR5K_SIMR2, AR5K_SIMR2_DPERR, AR5K_SIMR2_MCABT, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR2_SSERR, AR5K_SISR2_BCN_TIMEOUT, AR5K_SISR2_CAB_TIMEOUT, AR5K_SISR2_DTIM, AR5K_SISR2_DTIM_SYNC, AR5K_SISR2_TIM, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and u32.
Referenced by ath5k_hw_reset(), ath5k_hw_update_tx_triglevel(), ath5k_irq(), ath5k_reset(), and ath5k_stop_hw().
00549 { 00550 enum ath5k_int old_mask, int_mask; 00551 00552 old_mask = ah->ah_imr; 00553 00554 /* 00555 * Disable card interrupts to prevent any race conditions 00556 * (they will be re-enabled afterwards if AR5K_INT GLOBAL 00557 * is set again on the new mask). 00558 */ 00559 if (old_mask & AR5K_INT_GLOBAL) { 00560 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); 00561 ath5k_hw_reg_read(ah, AR5K_IER); 00562 } 00563 00564 /* 00565 * Add additional, chipset-dependent interrupt mask flags 00566 * and write them to the IMR (interrupt mask register). 00567 */ 00568 int_mask = new_mask & AR5K_INT_COMMON; 00569 00570 if (ah->ah_version != AR5K_AR5210) { 00571 /* Preserve per queue TXURN interrupt mask */ 00572 u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2) 00573 & AR5K_SIMR2_QCU_TXURN; 00574 00575 if (new_mask & AR5K_INT_FATAL) { 00576 int_mask |= AR5K_IMR_HIUERR; 00577 simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR 00578 | AR5K_SIMR2_DPERR); 00579 } 00580 00581 /*Beacon Not Ready*/ 00582 if (new_mask & AR5K_INT_BNR) 00583 int_mask |= AR5K_INT_BNR; 00584 00585 if (new_mask & AR5K_INT_TIM) 00586 int_mask |= AR5K_IMR_TIM; 00587 00588 if (new_mask & AR5K_INT_TIM) 00589 simr2 |= AR5K_SISR2_TIM; 00590 if (new_mask & AR5K_INT_DTIM) 00591 simr2 |= AR5K_SISR2_DTIM; 00592 if (new_mask & AR5K_INT_DTIM_SYNC) 00593 simr2 |= AR5K_SISR2_DTIM_SYNC; 00594 if (new_mask & AR5K_INT_BCN_TIMEOUT) 00595 simr2 |= AR5K_SISR2_BCN_TIMEOUT; 00596 if (new_mask & AR5K_INT_CAB_TIMEOUT) 00597 simr2 |= AR5K_SISR2_CAB_TIMEOUT; 00598 00599 if (new_mask & AR5K_INT_RX_DOPPLER) 00600 int_mask |= AR5K_IMR_RXDOPPLER; 00601 00602 /* Note: Per queue interrupt masks 00603 * are set via reset_tx_queue (qcu.c) */ 00604 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); 00605 ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2); 00606 00607 } else { 00608 if (new_mask & AR5K_INT_FATAL) 00609 int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT 00610 | AR5K_IMR_HIUERR | AR5K_IMR_DPERR); 00611 00612 ath5k_hw_reg_write(ah, int_mask, AR5K_IMR); 00613 } 00614 00615 /* If RXNOFRM interrupt is masked disable it 00616 * by setting AR5K_RXNOFRM to zero */ 00617 if (!(new_mask & AR5K_INT_RXNOFRM)) 00618 ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM); 00619 00620 /* Store new interrupt mask */ 00621 ah->ah_imr = new_mask; 00622 00623 /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */ 00624 if (new_mask & AR5K_INT_GLOBAL) { 00625 ath5k_hw_reg_write(ah, ah->ah_ier, AR5K_IER); 00626 ath5k_hw_reg_read(ah, AR5K_IER); 00627 } 00628 00629 return old_mask; 00630 }
| int ath5k_eeprom_init | ( | struct ath5k_hw * | ah | ) |
Definition at line 1693 of file ath5k_eeprom.c.
References ath5k_eeprom_init_header(), ath5k_eeprom_init_modes(), ath5k_eeprom_read_ctl_info(), and ath5k_eeprom_read_pcal_info().
Referenced by ath5k_hw_attach().
01694 { 01695 int err; 01696 01697 err = ath5k_eeprom_init_header(ah); 01698 if (err < 0) 01699 return err; 01700 01701 err = ath5k_eeprom_init_modes(ah); 01702 if (err < 0) 01703 return err; 01704 01705 err = ath5k_eeprom_read_pcal_info(ah); 01706 if (err < 0) 01707 return err; 01708 01709 err = ath5k_eeprom_read_ctl_info(ah); 01710 if (err < 0) 01711 return err; 01712 01713 return 0; 01714 }
| void ath5k_eeprom_detach | ( | struct ath5k_hw * | ah | ) |
Definition at line 1572 of file ath5k_eeprom.c.
References AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11G, ath5k_eeprom_free_pcal_info(), and u8.
Referenced by ath5k_hw_detach().
01573 { 01574 u8 mode; 01575 01576 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) 01577 ath5k_eeprom_free_pcal_info(ah, mode); 01578 }
Definition at line 1719 of file ath5k_eeprom.c.
References ath5k_hw_eeprom_read(), EINVAL, ETH_ALEN, memcpy, offset, u16, u32, and u8.
Referenced by ath5k_attach().
01720 { 01721 u8 mac_d[ETH_ALEN] = {}; 01722 u32 total, offset; 01723 u16 data; 01724 int octet, ret; 01725 01726 ret = ath5k_hw_eeprom_read(ah, 0x20, &data); 01727 if (ret) 01728 return ret; 01729 01730 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) { 01731 ret = ath5k_hw_eeprom_read(ah, offset, &data); 01732 if (ret) 01733 return ret; 01734 01735 total += data; 01736 mac_d[octet + 1] = data & 0xff; 01737 mac_d[octet] = data >> 8; 01738 octet += 2; 01739 } 01740 01741 if (!total || total == 3 * 0xffff) 01742 return -EINVAL; 01743 01744 memcpy(mac, mac_d, ETH_ALEN); 01745 01746 return 0; 01747 }
| int ath5k_eeprom_is_hb63 | ( | struct ath5k_hw * | ah | ) |
Definition at line 1749 of file ath5k_eeprom.c.
References ath5k_hw::ah_mac_version, AR5K_EEPROM_IS_HB63, AR5K_SREV_AR2425, ath5k_hw_eeprom_read(), and u16.
Referenced by ath5k_hw_tweak_initval_settings().
01750 { 01751 u16 data; 01752 01753 ath5k_hw_eeprom_read(ah, AR5K_EEPROM_IS_HB63, &data); 01754 01755 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && data) 01756 return 1; 01757 else 01758 return 0; 01759 }
| int ath5k_hw_set_opmode | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_set_opmode - Set PCU operating mode
: The &struct ath5k_hw
Initialize PCU for the various operating modes (AP/STA etc)
For gPXE we always assume STA mode.
Definition at line 48 of file ath5k_pcu.c.
References ath5k_hw::ah_sta_id, ath5k_hw::ah_version, AR5K_AR5210, AR5K_BCR, AR5K_HIGH_ID, AR5K_LOW_ID, AR5K_STA_ID0, AR5K_STA_ID1, AR5K_STA_ID1_ADHOC, AR5K_STA_ID1_AP, AR5K_STA_ID1_KEYSRCH_MODE, AR5K_STA_ID1_NO_PSPOLL, AR5K_STA_ID1_PWR_SV, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and u32.
Referenced by ath5k_hw_attach(), ath5k_hw_reset(), and ath5k_mode_setup().
00049 { 00050 u32 pcu_reg, beacon_reg, low_id, high_id; 00051 00052 00053 /* Preserve rest settings */ 00054 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 00055 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP 00056 | AR5K_STA_ID1_KEYSRCH_MODE 00057 | (ah->ah_version == AR5K_AR5210 ? 00058 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0)); 00059 00060 beacon_reg = 0; 00061 00062 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE 00063 | (ah->ah_version == AR5K_AR5210 ? 00064 AR5K_STA_ID1_PWR_SV : 0); 00065 00066 /* 00067 * Set PCU registers 00068 */ 00069 low_id = AR5K_LOW_ID(ah->ah_sta_id); 00070 high_id = AR5K_HIGH_ID(ah->ah_sta_id); 00071 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 00072 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 00073 00074 /* 00075 * Set Beacon Control Register on 5210 00076 */ 00077 if (ah->ah_version == AR5K_AR5210) 00078 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR); 00079 00080 return 0; 00081 }
ath5k_hw_get_lladdr - Get station id
: The &struct ath5k_hw : The card's mac address
Initialize ah->ah_sta_id using the mac address provided (just a memcpy).
TODO: Remove it once we merge ath5k_softc and ath5k_hw
Definition at line 187 of file ath5k_pcu.c.
References ath5k_hw::ah_sta_id, ETH_ALEN, and memcpy.
ath5k_hw_set_lladdr - Set station id
: The &struct ath5k_hw : The card's mac address
Set station id on hw using the provided mac address
Definition at line 200 of file ath5k_pcu.c.
References ath5k_hw::ah_sta_id, AR5K_HIGH_ID, AR5K_LOW_ID, AR5K_STA_ID0, AR5K_STA_ID1, ath5k_hw_reg_read(), ath5k_hw_reg_write(), ETH_ALEN, memcpy, and u32.
Referenced by ath5k_start(), and ath5k_stop().
00201 { 00202 u32 low_id, high_id; 00203 u32 pcu_reg; 00204 00205 /* Set new station ID */ 00206 memcpy(ah->ah_sta_id, mac, ETH_ALEN); 00207 00208 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000; 00209 00210 low_id = AR5K_LOW_ID(mac); 00211 high_id = AR5K_HIGH_ID(mac); 00212 00213 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0); 00214 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1); 00215 00216 return 0; 00217 }
ath5k_hw_set_associd - Set BSSID for association
: The &struct ath5k_hw : BSSID : Assoc id
Sets the BSSID which trigers the "SME Join" operation
Definition at line 228 of file ath5k_pcu.c.
References ath5k_hw::ah_bssid_mask, ath5k_hw::ah_version, AR5K_AR5212, AR5K_BSS_ID0, AR5K_BSS_ID1, AR5K_BSS_ID1_AID_S, AR5K_BSS_IDM0, AR5K_BSS_IDM1, AR5K_HIGH_ID, AR5K_LOW_ID, ath5k_hw_reg_write(), and u32.
Referenced by ath5k_config(), ath5k_hw_attach(), and ath5k_hw_reset().
00229 { 00230 u32 low_id, high_id; 00231 00232 /* 00233 * Set simple BSSID mask on 5212 00234 */ 00235 if (ah->ah_version == AR5K_AR5212) { 00236 ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_bssid_mask), 00237 AR5K_BSS_IDM0); 00238 ath5k_hw_reg_write(ah, AR5K_HIGH_ID(ah->ah_bssid_mask), 00239 AR5K_BSS_IDM1); 00240 } 00241 00242 /* 00243 * Set BSSID which triggers the "SME Join" operation 00244 */ 00245 low_id = AR5K_LOW_ID(bssid); 00246 high_id = AR5K_HIGH_ID(bssid); 00247 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0); 00248 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) << 00249 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1); 00250 }
ath5k_hw_set_bssid_mask - filter out bssids we listen
: the &struct ath5k_hw : the bssid_mask, a u8 array of size ETH_ALEN
BSSID masking is a method used by AR5212 and newer hardware to inform PCU which bits of the interface's MAC address should be looked at when trying to decide which packets to ACK. In station mode and AP mode with a single BSS every bit matters since we lock to only one BSS. In AP mode with multiple BSSes (virtual interfaces) not every bit matters because hw must accept frames for all BSSes and so we tweak some bits of our mac address in order to have multiple BSSes.
NOTE: This is a simple filter and does *not* filter out all relevant frames. Some frames that are not for us might get ACKed from us by PCU because they just match the mask.
When handling multiple BSSes you can get the BSSID mask by computing the set of ~ ( MAC XOR BSSID ) for all bssids we handle.
When you do this you are essentially computing the common bits of all your BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with the MAC address to obtain the relevant bits and compare the result with (frame's BSSID & mask) to see if they match.
Definition at line 348 of file ath5k_pcu.c.
References ath5k_hw::ah_bssid_mask, ath5k_hw::ah_version, AR5K_AR5212, AR5K_BSS_IDM0, AR5K_BSS_IDM1, AR5K_HIGH_ID, AR5K_LOW_ID, ath5k_hw_reg_write(), EIO, ETH_ALEN, memcpy, and u32.
Referenced by ath5k_attach(), and ath5k_mode_setup().
00349 { 00350 u32 low_id, high_id; 00351 00352 /* Cache bssid mask so that we can restore it 00353 * on reset */ 00354 memcpy(ah->ah_bssid_mask, mask, ETH_ALEN); 00355 if (ah->ah_version == AR5K_AR5212) { 00356 low_id = AR5K_LOW_ID(mask); 00357 high_id = AR5K_HIGH_ID(mask); 00358 00359 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0); 00360 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1); 00361 00362 return 0; 00363 } 00364 00365 return -EIO; 00366 }
| void ath5k_hw_start_rx_pcu | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_start_rx_pcu - Start RX engine
: The &struct ath5k_hw
Starts RX engine on PCU so that hw can process RXed frames (ACK etc).
NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma TODO: Init ANI here
Definition at line 384 of file ath5k_pcu.c.
References AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX, and AR5K_REG_DISABLE_BITS.
Referenced by ath5k_rx_start().
00385 { 00386 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 00387 }
| void ath5k_hw_stop_rx_pcu | ( | struct ath5k_hw * | ah | ) |
at5k_hw_stop_rx_pcu - Stop RX engine
: The &struct ath5k_hw
Stops RX engine on PCU
TODO: Detach ANI here
Definition at line 398 of file ath5k_pcu.c.
References AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX, and AR5K_REG_ENABLE_BITS.
Referenced by ath5k_rx_stop().
00399 { 00400 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX); 00401 }
Definition at line 406 of file ath5k_pcu.c.
References AR5K_MCAST_FILTER0, AR5K_MCAST_FILTER1, and ath5k_hw_reg_write().
Referenced by ath5k_configure_filter(), and ath5k_mode_setup().
00407 { 00408 /* Set the multicat filter */ 00409 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0); 00410 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1); 00411 }
ath5k_hw_get_rx_filter - Get current rx filter
: The &struct ath5k_hw
Returns the RX filter by reading rx filter and phy error filter registers. RX filter is used to set the allowed frame types that PCU will accept and pass to the driver. For a list of frame types check out reg.h.
Definition at line 424 of file ath5k_pcu.c.
References ath5k_hw::ah_version, AR5K_AR5212, AR5K_PHY_ERR_FIL, AR5K_PHY_ERR_FIL_CCK, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHY_ERR_FIL_RADAR, AR5K_RX_FILTER, AR5K_RX_FILTER_PHYERR, AR5K_RX_FILTER_RADARERR, ath5k_hw_reg_read(), filter(), and u32.
00425 { 00426 u32 data, filter = 0; 00427 00428 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER); 00429 00430 /*Radar detection for 5212*/ 00431 if (ah->ah_version == AR5K_AR5212) { 00432 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL); 00433 00434 if (data & AR5K_PHY_ERR_FIL_RADAR) 00435 filter |= AR5K_RX_FILTER_RADARERR; 00436 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK)) 00437 filter |= AR5K_RX_FILTER_PHYERR; 00438 } 00439 00440 return filter; 00441 }
ath5k_hw_set_rx_filter - Set rx filter
: The &struct ath5k_hw : RX filter mask (see reg.h)
Sets RX filter register and also handles PHY error filter register on 5212 and newer chips so that we have proper PHY error reporting.
Definition at line 453 of file ath5k_pcu.c.
References ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5212, AR5K_PHY_ERR_FIL, AR5K_PHY_ERR_FIL_CCK, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHY_ERR_FIL_RADAR, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_RX_FILTER, AR5K_RX_FILTER_PHYERR, AR5K_RX_FILTER_PROM, AR5K_RX_FILTER_RADARERR, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA, ath5k_hw_reg_write(), and u32.
Referenced by ath5k_configure_filter(), ath5k_mode_setup(), and ath5k_rx_stop().
00454 { 00455 u32 data = 0; 00456 00457 /* Set PHY error filter register on 5212*/ 00458 if (ah->ah_version == AR5K_AR5212) { 00459 if (filter & AR5K_RX_FILTER_RADARERR) 00460 data |= AR5K_PHY_ERR_FIL_RADAR; 00461 if (filter & AR5K_RX_FILTER_PHYERR) 00462 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK; 00463 } 00464 00465 /* 00466 * The AR5210 uses promiscous mode to detect radar activity 00467 */ 00468 if (ah->ah_version == AR5K_AR5210 && 00469 (filter & AR5K_RX_FILTER_RADARERR)) { 00470 filter &= ~AR5K_RX_FILTER_RADARERR; 00471 filter |= AR5K_RX_FILTER_PROM; 00472 } 00473 00474 /*Zero length DMA (phy error reporting) */ 00475 if (data) 00476 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 00477 else 00478 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA); 00479 00480 /*Write RX Filter register*/ 00481 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER); 00482 00483 /*Write PHY error filter register on 5212*/ 00484 if (ah->ah_version == AR5K_AR5212) 00485 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL); 00486 00487 }
| void ath5k_hw_set_ack_bitrate_high | ( | struct ath5k_hw * | ah, | |
| int | high | |||
| ) |
ath5k_hw_set_ack_bitrate - set bitrate for ACKs
: The &struct ath5k_hw : Flag to determine if we want to use high transmition rate for ACKs or not
If high flag is set, we tell hw to use a set of control rates based on the current transmition rate (check out control_rates array inside reset.c). If not hw just uses the lowest rate available for the current modulation scheme being used (1Mbit for CCK and 6Mbits for OFDM).
Definition at line 95 of file ath5k_pcu.c.
References ath5k_hw::ah_version, AR5K_AR5212, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_STA_ID1, AR5K_STA_ID1_ACKCTS_6MB, AR5K_STA_ID1_BASE_RATE_11B, and u32.
Referenced by ath5k_init().
00096 { 00097 if (ah->ah_version != AR5K_AR5212) 00098 return; 00099 else { 00100 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB; 00101 if (high) 00102 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val); 00103 else 00104 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val); 00105 } 00106 }
| int ath5k_hw_set_ack_timeout | ( | struct ath5k_hw * | ah, | |
| unsigned int | timeout | |||
| ) |
ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
: The &struct ath5k_hw : Timeout in usec
Definition at line 130 of file ath5k_pcu.c.
References ath5k_hw::ah_turbo, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_clocktoh(), ath5k_hw_htoclock(), and EINVAL.
00131 { 00132 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK), 00133 ah->ah_turbo) <= timeout) 00134 return -EINVAL; 00135 00136 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, 00137 ath5k_hw_htoclock(timeout, ah->ah_turbo)); 00138 00139 return 0; 00140 }
| unsigned int ath5k_hw_get_ack_timeout | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec
: The &struct ath5k_hw
Definition at line 118 of file ath5k_pcu.c.
References ath5k_hw::ah_turbo, AR5K_REG_MS, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK, ath5k_hw_clocktoh(), and ath5k_hw_reg_read().
00119 { 00120 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, 00121 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo); 00122 }
| int ath5k_hw_set_cts_timeout | ( | struct ath5k_hw * | ah, | |
| unsigned int | timeout | |||
| ) |
ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
: The &struct ath5k_hw : Timeout in usec
Definition at line 159 of file ath5k_pcu.c.
References ath5k_hw::ah_turbo, AR5K_REG_MS, AR5K_REG_WRITE_BITS, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_clocktoh(), ath5k_hw_htoclock(), and EINVAL.
00160 { 00161 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS), 00162 ah->ah_turbo) <= timeout) 00163 return -EINVAL; 00164 00165 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, 00166 ath5k_hw_htoclock(timeout, ah->ah_turbo)); 00167 00168 return 0; 00169 }
| unsigned int ath5k_hw_get_cts_timeout | ( | struct ath5k_hw * | ah | ) |
ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
: The &struct ath5k_hw
Definition at line 147 of file ath5k_pcu.c.
References ath5k_hw::ah_turbo, AR5K_REG_MS, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS, ath5k_hw_clocktoh(), and ath5k_hw_reg_read().
00148 { 00149 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah, 00150 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo); 00151 }
Definition at line 496 of file ath5k_pcu.c.
References ath5k_hw::ah_version, AR5K_AR5211, AR5K_KEYCACHE_SIZE, AR5K_KEYTABLE_MIC_OFFSET, AR5K_KEYTABLE_OFF, AR5K_KEYTABLE_TYPE, AR5K_KEYTABLE_TYPE_NULL, AR5K_KEYTABLE_TYPE_TKIP, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and u16.
Referenced by ath5k_init().
00497 { 00498 unsigned int i, type; 00499 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET; 00500 00501 type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry)); 00502 00503 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++) 00504 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i)); 00505 00506 /* Reset associated MIC entry if TKIP 00507 * is enabled located at offset (entry + 64) */ 00508 if (type == AR5K_KEYTABLE_TYPE_TKIP) { 00509 for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++) 00510 ath5k_hw_reg_write(ah, 0, 00511 AR5K_KEYTABLE_OFF(micentry, i)); 00512 } 00513 00514 /* 00515 * Set NULL encryption on AR5212+ 00516 * 00517 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5) 00518 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007 00519 * 00520 * Note2: Windows driver (ndiswrapper) sets this to 00521 * 0x00000714 instead of 0x00000007 00522 */ 00523 if (ah->ah_version >= AR5K_AR5211) { 00524 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 00525 AR5K_KEYTABLE_TYPE(entry)); 00526 00527 if (type == AR5K_KEYTABLE_TYPE_TKIP) { 00528 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL, 00529 AR5K_KEYTABLE_TYPE(micentry)); 00530 } 00531 } 00532 00533 return 0; 00534 }
| int ath5k_hw_set_tx_queueprops | ( | struct ath5k_hw * | ah, | |
| const struct ath5k_txq_info * | queue_info | |||
| ) |
Definition at line 34 of file ath5k_qcu.c.
References ath5k_hw::ah_txq, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_INACTIVE, AR5K_TX_QUEUE_UAPSD, AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS, AR5K_WME_AC_VI, AR5K_WME_AC_VO, EIO, memcpy, ath5k_txq_info::tqi_flags, ath5k_txq_info::tqi_subtype, and ath5k_txq_info::tqi_type.
Referenced by ath5k_hw_setup_tx_queue().
00036 { 00037 if (ah->ah_txq.tqi_type == AR5K_TX_QUEUE_INACTIVE) 00038 return -EIO; 00039 00040 memcpy(&ah->ah_txq, queue_info, sizeof(struct ath5k_txq_info)); 00041 00042 /*XXX: Is this supported on 5210 ?*/ 00043 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA && 00044 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) || 00045 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) || 00046 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD) 00047 ah->ah_txq.tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS; 00048 00049 return 0; 00050 }
| int ath5k_hw_setup_tx_queue | ( | struct ath5k_hw * | ah, | |
| enum ath5k_tx_queue | queue_type, | |||
| struct ath5k_txq_info * | queue_info | |||
| ) |
Definition at line 55 of file ath5k_qcu.c.
References ath5k_hw::ah_txq, ath5k_hw::ah_txq_status, AR5K_Q_ENABLE_BITS, ath5k_hw_set_tx_queueprops(), memset(), NULL, and ath5k_txq_info::tqi_type.
Referenced by ath5k_txq_setup().
00057 { 00058 unsigned int queue; 00059 int ret; 00060 00061 /* We only use one queue */ 00062 queue = 0; 00063 00064 /* 00065 * Setup internal queue structure 00066 */ 00067 memset(&ah->ah_txq, 0, sizeof(struct ath5k_txq_info)); 00068 ah->ah_txq.tqi_type = queue_type; 00069 00070 if (queue_info != NULL) { 00071 queue_info->tqi_type = queue_type; 00072 ret = ath5k_hw_set_tx_queueprops(ah, queue_info); 00073 if (ret) 00074 return ret; 00075 } 00076 00077 /* 00078 * We use ah_txq_status to hold a temp value for 00079 * the Secondary interrupt mask registers on 5211+ 00080 * check out ath5k_hw_reset_tx_queue 00081 */ 00082 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, 0); 00083 00084 return 0; 00085 }
| void ath5k_hw_release_tx_queue | ( | struct ath5k_hw * | ah | ) |
Definition at line 90 of file ath5k_qcu.c.
References ath5k_hw::ah_txq, ath5k_hw::ah_txq_status, AR5K_Q_DISABLE_BITS, AR5K_TX_QUEUE_INACTIVE, and ath5k_txq_info::tqi_type.
Referenced by ath5k_txq_release().
00091 { 00092 /* This queue will be skipped in further operations */ 00093 ah->ah_txq.tqi_type = AR5K_TX_QUEUE_INACTIVE; 00094 /*For SIMR setup*/ 00095 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, 0); 00096 }
| int ath5k_hw_reset_tx_queue | ( | struct ath5k_hw * | ah | ) |
Definition at line 101 of file ath5k_qcu.c.
References ath5k_hw::ah_aifs, ath5k_hw::ah_current_channel, ath5k_hw::ah_cw_max, ath5k_hw::ah_cw_min, ath5k_hw::ah_limit_tx_retries, ath5k_hw::ah_mac_version, ath5k_hw::ah_software_retry, ath5k_hw::ah_turbo, ath5k_hw::ah_txq, ath5k_hw::ah_txq_imr_cbrorn, ath5k_hw::ah_txq_imr_cbrurn, ath5k_hw::ah_txq_imr_nofrm, ath5k_hw::ah_txq_imr_qtrig, ath5k_hw::ah_txq_imr_txdesc, ath5k_hw::ah_txq_imr_txeol, ath5k_hw::ah_txq_imr_txerr, ath5k_hw::ah_txq_imr_txok, ath5k_hw::ah_txq_imr_txurn, ath5k_hw::ah_txq_status, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5212, AR5K_DCU_CHAN_TIME_DUR, AR5K_DCU_CHAN_TIME_ENABLE, AR5K_DCU_LCL_IFS_AIFS, AR5K_DCU_LCL_IFS_CW_MAX, AR5K_DCU_LCL_IFS_CW_MIN, AR5K_DCU_MISC_BACKOFF_FRAG, AR5K_DCU_MISC_FRAG_WAIT, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, AR5K_DCU_MISC_SEQNUM_CTL, AR5K_DCU_RETRY_LMT_LG_RETRY, AR5K_DCU_RETRY_LMT_SH_RETRY, AR5K_DCU_RETRY_LMT_SLG_RETRY, AR5K_DCU_RETRY_LMT_SSH_RETRY, AR5K_IFS0, AR5K_IFS0_DIFS_S, AR5K_IFS1, AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_INIT_ACK_CTS_TIMEOUT_TURBO, AR5K_INIT_LG_RETRY, AR5K_INIT_PROTO_TIME_CNTRL, AR5K_INIT_PROTO_TIME_CNTRL_TURBO, AR5K_INIT_SH_RETRY, AR5K_INIT_SIFS, AR5K_INIT_SIFS_TURBO, AR5K_INIT_SLG_RETRY, AR5K_INIT_SLOT_TIME, AR5K_INIT_SLOT_TIME_TURBO, AR5K_INIT_SSH_RETRY, AR5K_INIT_TRANSMIT_LATENCY, AR5K_INIT_TRANSMIT_LATENCY_TURBO, AR5K_NODCU_RETRY_LMT, AR5K_NODCU_RETRY_LMT_CW_MIN_S, AR5K_NODCU_RETRY_LMT_LG_RETRY, AR5K_NODCU_RETRY_LMT_SH_RETRY, AR5K_NODCU_RETRY_LMT_SLG_RETRY, AR5K_NODCU_RETRY_LMT_SSH_RETRY, AR5K_PHY_FRAME_CTL_5210, AR5K_PHY_FRAME_CTL_INI, AR5K_PHY_SETTLING, AR5K_PHY_TURBO_MODE, AR5K_PHY_TURBO_SHORT, AR5K_Q_ENABLE_BITS, AR5K_QCU_CBRCFG_INTVAL, AR5K_QCU_CBRCFG_ORN_THRES, AR5K_QCU_MISC_CBR_THRES_ENABLE, AR5K_QCU_MISC_DCU_EARLY, AR5K_QCU_MISC_FRSHED_CBR, AR5K_QCU_MISC_RDY_VEOL_POLICY, AR5K_QCU_RDYTIMECFG_ENABLE, AR5K_QCU_RDYTIMECFG_INTVAL, AR5K_QUEUE_CBRCFG, AR5K_QUEUE_DFS_CHANNEL_TIME, AR5K_QUEUE_DFS_LOCAL_IFS, AR5K_QUEUE_DFS_MISC, AR5K_QUEUE_DFS_RETRY_LIMIT, AR5K_QUEUE_MISC, AR5K_QUEUE_QCUMASK, AR5K_QUEUE_RDYTIMECFG, AR5K_REG_DISABLE_BITS, AR5K_REG_ENABLE_BITS, AR5K_REG_SM, AR5K_REG_WRITE_Q, AR5K_SIMR0, AR5K_SIMR0_QCU_TXDESC, AR5K_SIMR0_QCU_TXOK, AR5K_SIMR1, AR5K_SIMR1_QCU_TXEOL, AR5K_SIMR1_QCU_TXERR, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN, AR5K_SIMR3, AR5K_SIMR3_QCBRORN, AR5K_SIMR3_QCBRURN, AR5K_SIMR4, AR5K_SIMR4_QTRIG, AR5K_SLOT_TIME, AR5K_SREV_AR5211, AR5K_TUNE_AIFS, AR5K_TUNE_AIFS_11B, AR5K_TUNE_AIFS_XR, AR5K_TUNE_CWMAX, AR5K_TUNE_CWMAX_11B, AR5K_TUNE_CWMAX_XR, AR5K_TUNE_CWMIN, AR5K_TUNE_CWMIN_11B, AR5K_TUNE_CWMIN_XR, AR5K_TX_QUEUE_DATA, AR5K_TX_QUEUE_ID_CAB, AR5K_TX_QUEUE_INACTIVE, AR5K_TXNOFRM, AR5K_TXNOFRM_QCU, AR5K_TXQ_FLAG_BACKOFF_DISABLE, AR5K_TXQ_FLAG_CBRORNINT_ENABLE, AR5K_TXQ_FLAG_CBRURNINT_ENABLE, AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE, AR5K_TXQ_FLAG_QTRIGINT_ENABLE, AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE, AR5K_TXQ_FLAG_TXDESCINT_ENABLE, AR5K_TXQ_FLAG_TXEOLINT_ENABLE, AR5K_TXQ_FLAG_TXERRINT_ENABLE, AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE, AR5K_TXQ_FLAG_TXOKINT_ENABLE, AR5K_TXQ_FLAG_TXURNINT_ENABLE, AR5K_USEC_5210, ath5k_hw_reg_read(), ath5k_hw_reg_write(), IS_CHAN_B, IS_CHAN_XR, ath5k_txq_info::tqi_aifs, ath5k_txq_info::tqi_burst_time, ath5k_txq_info::tqi_cbr_overflow_limit, ath5k_txq_info::tqi_cbr_period, ath5k_txq_info::tqi_cw_max, ath5k_txq_info::tqi_cw_min, ath5k_txq_info::tqi_flags, ath5k_txq_info::tqi_ready_time, ath5k_txq_info::tqi_type, and u32.
Referenced by ath5k_hw_reset().
00102 { 00103 u32 cw_min, cw_max, retry_lg, retry_sh; 00104 struct ath5k_txq_info *tq = &ah->ah_txq; 00105 const int queue = 0; 00106 00107 tq = &ah->ah_txq; 00108 00109 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE) 00110 return 0; 00111 00112 if (ah->ah_version == AR5K_AR5210) { 00113 /* Only handle data queues, others will be ignored */ 00114 if (tq->tqi_type != AR5K_TX_QUEUE_DATA) 00115 return 0; 00116 00117 /* Set Slot time */ 00118 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00119 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME, 00120 AR5K_SLOT_TIME); 00121 /* Set ACK_CTS timeout */ 00122 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00123 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO : 00124 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME); 00125 /* Set Transmit Latency */ 00126 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00127 AR5K_INIT_TRANSMIT_LATENCY_TURBO : 00128 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210); 00129 00130 /* Set IFS0 */ 00131 if (ah->ah_turbo) { 00132 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO + 00133 (ah->ah_aifs + tq->tqi_aifs) * 00134 AR5K_INIT_SLOT_TIME_TURBO) << 00135 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO, 00136 AR5K_IFS0); 00137 } else { 00138 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS + 00139 (ah->ah_aifs + tq->tqi_aifs) * 00140 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) | 00141 AR5K_INIT_SIFS, AR5K_IFS0); 00142 } 00143 00144 /* Set IFS1 */ 00145 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00146 AR5K_INIT_PROTO_TIME_CNTRL_TURBO : 00147 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1); 00148 /* Set AR5K_PHY_SETTLING */ 00149 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00150 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) 00151 | 0x38 : 00152 (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F) 00153 | 0x1C, 00154 AR5K_PHY_SETTLING); 00155 /* Set Frame Control Register */ 00156 ath5k_hw_reg_write(ah, ah->ah_turbo ? 00157 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE | 00158 AR5K_PHY_TURBO_SHORT | 0x2020) : 00159 (AR5K_PHY_FRAME_CTL_INI | 0x1020), 00160 AR5K_PHY_FRAME_CTL_5210); 00161 } 00162 00163 /* 00164 * Calculate cwmin/max by channel mode 00165 */ 00166 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN; 00167 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX; 00168 ah->ah_aifs = AR5K_TUNE_AIFS; 00169 /*XR is only supported on 5212*/ 00170 if (IS_CHAN_XR(ah->ah_current_channel) && 00171 ah->ah_version == AR5K_AR5212) { 00172 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR; 00173 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR; 00174 ah->ah_aifs = AR5K_TUNE_AIFS_XR; 00175 /*B mode is not supported on 5210*/ 00176 } else if (IS_CHAN_B(ah->ah_current_channel) && 00177 ah->ah_version != AR5K_AR5210) { 00178 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B; 00179 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B; 00180 ah->ah_aifs = AR5K_TUNE_AIFS_11B; 00181 } 00182 00183 cw_min = 1; 00184 while (cw_min < ah->ah_cw_min) 00185 cw_min = (cw_min << 1) | 1; 00186 00187 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) : 00188 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1); 00189 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) : 00190 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1); 00191 00192 /* 00193 * Calculate and set retry limits 00194 */ 00195 if (ah->ah_software_retry) { 00196 /* XXX Need to test this */ 00197 retry_lg = ah->ah_limit_tx_retries; 00198 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ? 00199 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg; 00200 } else { 00201 retry_lg = AR5K_INIT_LG_RETRY; 00202 retry_sh = AR5K_INIT_SH_RETRY; 00203 } 00204 00205 /*No QCU/DCU [5210]*/ 00206 if (ah->ah_version == AR5K_AR5210) { 00207 ath5k_hw_reg_write(ah, 00208 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S) 00209 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 00210 AR5K_NODCU_RETRY_LMT_SLG_RETRY) 00211 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 00212 AR5K_NODCU_RETRY_LMT_SSH_RETRY) 00213 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY) 00214 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY), 00215 AR5K_NODCU_RETRY_LMT); 00216 } else { 00217 /*QCU/DCU [5211+]*/ 00218 ath5k_hw_reg_write(ah, 00219 AR5K_REG_SM(AR5K_INIT_SLG_RETRY, 00220 AR5K_DCU_RETRY_LMT_SLG_RETRY) | 00221 AR5K_REG_SM(AR5K_INIT_SSH_RETRY, 00222 AR5K_DCU_RETRY_LMT_SSH_RETRY) | 00223 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) | 00224 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY), 00225 AR5K_QUEUE_DFS_RETRY_LIMIT(queue)); 00226 00227 /*===Rest is also for QCU/DCU only [5211+]===*/ 00228 00229 /* 00230 * Set initial content window (cw_min/cw_max) 00231 * and arbitrated interframe space (aifs)... 00232 */ 00233 ath5k_hw_reg_write(ah, 00234 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) | 00235 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) | 00236 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs, 00237 AR5K_DCU_LCL_IFS_AIFS), 00238 AR5K_QUEUE_DFS_LOCAL_IFS(queue)); 00239 00240 /* 00241 * Set misc registers 00242 */ 00243 /* Enable DCU early termination for this queue */ 00244 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 00245 AR5K_QCU_MISC_DCU_EARLY); 00246 00247 /* Enable DCU to wait for next fragment from QCU */ 00248 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 00249 AR5K_DCU_MISC_FRAG_WAIT); 00250 00251 /* On Maui and Spirit use the global seqnum on DCU */ 00252 if (ah->ah_mac_version < AR5K_SREV_AR5211) 00253 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue), 00254 AR5K_DCU_MISC_SEQNUM_CTL); 00255 00256 if (tq->tqi_cbr_period) { 00257 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period, 00258 AR5K_QCU_CBRCFG_INTVAL) | 00259 AR5K_REG_SM(tq->tqi_cbr_overflow_limit, 00260 AR5K_QCU_CBRCFG_ORN_THRES), 00261 AR5K_QUEUE_CBRCFG(queue)); 00262 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), 00263 AR5K_QCU_MISC_FRSHED_CBR); 00264 if (tq->tqi_cbr_overflow_limit) 00265 AR5K_REG_ENABLE_BITS(ah, 00266 AR5K_QUEUE_MISC(queue), 00267 AR5K_QCU_MISC_CBR_THRES_ENABLE); 00268 } 00269 00270 if (tq->tqi_ready_time && 00271 (tq->tqi_type != AR5K_TX_QUEUE_ID_CAB)) 00272 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time, 00273 AR5K_QCU_RDYTIMECFG_INTVAL) | 00274 AR5K_QCU_RDYTIMECFG_ENABLE, 00275 AR5K_QUEUE_RDYTIMECFG(queue)); 00276 00277 if (tq->tqi_burst_time) { 00278 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time, 00279 AR5K_DCU_CHAN_TIME_DUR) | 00280 AR5K_DCU_CHAN_TIME_ENABLE, 00281 AR5K_QUEUE_DFS_CHANNEL_TIME(queue)); 00282 00283 if (tq->tqi_flags 00284 & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE) 00285 AR5K_REG_ENABLE_BITS(ah, 00286 AR5K_QUEUE_MISC(queue), 00287 AR5K_QCU_MISC_RDY_VEOL_POLICY); 00288 } 00289 00290 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE) 00291 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS, 00292 AR5K_QUEUE_DFS_MISC(queue)); 00293 00294 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) 00295 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG, 00296 AR5K_QUEUE_DFS_MISC(queue)); 00297 00298 /* TODO: Handle frame compression */ 00299 00300 /* 00301 * Enable interrupts for this tx queue 00302 * in the secondary interrupt mask registers 00303 */ 00304 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE) 00305 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue); 00306 00307 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE) 00308 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue); 00309 00310 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE) 00311 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue); 00312 00313 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE) 00314 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue); 00315 00316 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE) 00317 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue); 00318 00319 if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE) 00320 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue); 00321 00322 if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE) 00323 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue); 00324 00325 if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE) 00326 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue); 00327 00328 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE) 00329 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue); 00330 00331 /* Update secondary interrupt mask registers */ 00332 00333 /* Filter out inactive queues */ 00334 ah->ah_txq_imr_txok &= ah->ah_txq_status; 00335 ah->ah_txq_imr_txerr &= ah->ah_txq_status; 00336 ah->ah_txq_imr_txurn &= ah->ah_txq_status; 00337 ah->ah_txq_imr_txdesc &= ah->ah_txq_status; 00338 ah->ah_txq_imr_txeol &= ah->ah_txq_status; 00339 ah->ah_txq_imr_cbrorn &= ah->ah_txq_status; 00340 ah->ah_txq_imr_cbrurn &= ah->ah_txq_status; 00341 ah->ah_txq_imr_qtrig &= ah->ah_txq_status; 00342 ah->ah_txq_imr_nofrm &= ah->ah_txq_status; 00343 00344 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok, 00345 AR5K_SIMR0_QCU_TXOK) | 00346 AR5K_REG_SM(ah->ah_txq_imr_txdesc, 00347 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0); 00348 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr, 00349 AR5K_SIMR1_QCU_TXERR) | 00350 AR5K_REG_SM(ah->ah_txq_imr_txeol, 00351 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1); 00352 /* Update simr2 but don't overwrite rest simr2 settings */ 00353 AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN); 00354 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, 00355 AR5K_REG_SM(ah->ah_txq_imr_txurn, 00356 AR5K_SIMR2_QCU_TXURN)); 00357 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn, 00358 AR5K_SIMR3_QCBRORN) | 00359 AR5K_REG_SM(ah->ah_txq_imr_cbrurn, 00360 AR5K_SIMR3_QCBRURN), AR5K_SIMR3); 00361 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig, 00362 AR5K_SIMR4_QTRIG), AR5K_SIMR4); 00363 /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */ 00364 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm, 00365 AR5K_TXNOFRM_QCU), AR5K_TXNOFRM); 00366 /* No queue has TXNOFRM enabled, disable the interrupt 00367 * by setting AR5K_TXNOFRM to zero */ 00368 if (ah->ah_txq_imr_nofrm == 0) 00369 ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM); 00370 00371 /* Set QCU mask for this DCU to save power */ 00372 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue); 00373 } 00374 00375 return 0; 00376 }
| int ath5k_hw_set_slot_time | ( | struct ath5k_hw * | ah, | |
| unsigned int | slot_time | |||
| ) |
Definition at line 381 of file ath5k_qcu.c.
References ath5k_hw::ah_turbo, ath5k_hw::ah_version, AR5K_AR5210, AR5K_DCU_GBL_IFS_SLOT, AR5K_SLOT_TIME, AR5K_SLOT_TIME_MAX, ath5k_hw_htoclock(), ath5k_hw_reg_write(), and EINVAL.
00382 { 00383 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX) 00384 return -EINVAL; 00385 00386 if (ah->ah_version == AR5K_AR5210) 00387 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time, 00388 ah->ah_turbo), AR5K_SLOT_TIME); 00389 else 00390 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT); 00391 00392 return 0; 00393 }
| int ath5k_hw_init_desc_functions | ( | struct ath5k_hw * | ah | ) |
Definition at line 519 of file ath5k_desc.c.
References ath5k_hw::ah_proc_rx_desc, ath5k_hw::ah_proc_tx_desc, ath5k_hw::ah_setup_rx_desc, ath5k_hw::ah_setup_tx_desc, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, ath5k_hw_proc_2word_tx_status(), ath5k_hw_proc_4word_tx_status(), ath5k_hw_proc_5210_rx_status(), ath5k_hw_proc_5212_rx_status(), ath5k_hw_setup_2word_tx_desc(), ath5k_hw_setup_4word_tx_desc(), ath5k_hw_setup_rx_desc(), and ENOTSUP.
Referenced by ath5k_hw_attach().
00520 { 00521 00522 if (ah->ah_version != AR5K_AR5210 && 00523 ah->ah_version != AR5K_AR5211 && 00524 ah->ah_version != AR5K_AR5212) 00525 return -ENOTSUP; 00526 00527 if (ah->ah_version == AR5K_AR5212) { 00528 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc; 00529 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; 00530 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; 00531 } else { 00532 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc; 00533 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; 00534 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; 00535 } 00536 00537 if (ah->ah_version == AR5K_AR5212) 00538 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status; 00539 else if (ah->ah_version <= AR5K_AR5211) 00540 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status; 00541 00542 return 0; 00543 }
Definition at line 34 of file ath5k_gpio.c.
References AR5K_GPIOCR, AR5K_GPIOCR_IN, AR5K_GPIOCR_OUT, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and EINVAL.
Referenced by ath5k_hw_reset(), and ath5k_rfkill_set_intr().
00035 { 00036 if (gpio >= AR5K_NUM_GPIO) 00037 return -EINVAL; 00038 00039 ath5k_hw_reg_write(ah, 00040 (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio)) 00041 | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR); 00042 00043 return 0; 00044 }
Definition at line 49 of file ath5k_gpio.c.
References AR5K_GPIOCR, AR5K_GPIOCR_OUT, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and EINVAL.
Referenced by ath5k_rfkill_disable(), and ath5k_rfkill_enable().
00050 { 00051 if (gpio >= AR5K_NUM_GPIO) 00052 return -EINVAL; 00053 00054 ath5k_hw_reg_write(ah, 00055 (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & ~AR5K_GPIOCR_OUT(gpio)) 00056 | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR); 00057 00058 return 0; 00059 }
Definition at line 64 of file ath5k_gpio.c.
References AR5K_GPIODI, AR5K_GPIODI_M, AR5K_NUM_GPIO, and ath5k_hw_reg_read().
Referenced by ath5k_hw_reset(), ath5k_is_rfkill_set(), and ath5k_rfkill_set_intr().
00065 { 00066 if (gpio >= AR5K_NUM_GPIO) 00067 return 0xffffffff; 00068 00069 /* GPIO input magic */ 00070 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) & 00071 0x1; 00072 }
Definition at line 77 of file ath5k_gpio.c.
References AR5K_GPIODO, AR5K_NUM_GPIO, ath5k_hw_reg_read(), ath5k_hw_reg_write(), EINVAL, and u32.
Referenced by ath5k_rfkill_disable(), and ath5k_rfkill_enable().
00078 { 00079 u32 data; 00080 00081 if (gpio >= AR5K_NUM_GPIO) 00082 return -EINVAL; 00083 00084 /* GPIO output magic */ 00085 data = ath5k_hw_reg_read(ah, AR5K_GPIODO); 00086 00087 data &= ~(1 << gpio); 00088 data |= (val & 1) << gpio; 00089 00090 ath5k_hw_reg_write(ah, data, AR5K_GPIODO); 00091 00092 return 0; 00093 }
Definition at line 98 of file ath5k_gpio.c.
References ath5k_hw::ah_imr, AR5K_GPIOCR, AR5K_GPIOCR_INT_ENA, AR5K_GPIOCR_INT_SEL, AR5K_GPIOCR_INT_SELH, AR5K_GPIOCR_OUT, AR5K_IMR_GPIO, AR5K_NUM_GPIO, AR5K_PIMR, AR5K_REG_ENABLE_BITS, ath5k_hw_reg_read(), ath5k_hw_reg_write(), and u32.
Referenced by ath5k_hw_reset(), and ath5k_rfkill_set_intr().
00100 { 00101 u32 data; 00102 00103 if (gpio >= AR5K_NUM_GPIO) 00104 return; 00105 00106 /* 00107 * Set the GPIO interrupt 00108 */ 00109 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) & 00110 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH | 00111 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) | 00112 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA); 00113 00114 ath5k_hw_reg_write(ah, interrupt_level ? data : 00115 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR); 00116 00117 ah->ah_imr |= AR5K_IMR_GPIO; 00118 00119 /* Enable GPIO interrupts */ 00120 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO); 00121 }
| void ath5k_rfkill_hw_start | ( | struct ath5k_hw * | ah | ) |
Definition at line 80 of file ath5k_rfkill.c.
References ath5k_hw::ah_capabilities, ath5k_hw::ah_sc, AR5K_EEPROM_HDR_RFKILL, ath5k_rfkill_disable(), ath5k_rfkill_set_intr(), ath5k_capabilities::cap_eeprom, ath5k_eeprom_info::ee_header, ath5k_eeprom_info::ee_rfkill_pin, ath5k_eeprom_info::ee_rfkill_pol, ath5k_softc::gpio, ath5k_softc::polarity, and ath5k_softc::rf_kill.
Referenced by ath5k_init().
00081 { 00082 struct ath5k_softc *sc = ah->ah_sc; 00083 00084 /* read rfkill GPIO configuration from EEPROM header */ 00085 sc->rf_kill.gpio = ah->ah_capabilities.cap_eeprom.ee_rfkill_pin; 00086 sc->rf_kill.polarity = ah->ah_capabilities.cap_eeprom.ee_rfkill_pol; 00087 00088 ath5k_rfkill_disable(sc); 00089 00090 /* enable interrupt for rfkill switch */ 00091 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) 00092 ath5k_rfkill_set_intr(sc, 1); 00093 }
| void ath5k_rfkill_hw_stop | ( | struct ath5k_hw * | ah | ) |
Definition at line 97 of file ath5k_rfkill.c.
References ath5k_hw::ah_capabilities, ath5k_hw::ah_sc, AR5K_EEPROM_HDR_RFKILL, ath5k_rfkill_enable(), ath5k_rfkill_set_intr(), ath5k_capabilities::cap_eeprom, and ath5k_eeprom_info::ee_header.
Referenced by ath5k_stop_hw().
00098 { 00099 struct ath5k_softc *sc = ah->ah_sc; 00100 00101 /* disable interrupt for rfkill switch */ 00102 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) 00103 ath5k_rfkill_set_intr(sc, 0); 00104 00105 /* enable RFKILL when stopping HW so Wifi LED is turned off */ 00106 ath5k_rfkill_enable(sc); 00107 }
| int ath5k_hw_set_capabilities | ( | struct ath5k_hw * | ah | ) |
Definition at line 36 of file ath5k_caps.c.
References ath5k_hw::ah_capabilities, ath5k_hw::ah_gpio_npins, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_EEPROM_HDR_11A, AR5K_EEPROM_HDR_11B, AR5K_EEPROM_HDR_11G, AR5K_MODE_BIT_11A, AR5K_MODE_BIT_11A_TURBO, AR5K_MODE_BIT_11B, AR5K_MODE_BIT_11G, AR5K_MODE_BIT_11G_TURBO, AR5K_NUM_GPIO, ath5k_capabilities::cap_eeprom, ath5k_capabilities::cap_mode, ath5k_capabilities::cap_queues, ath5k_capabilities::cap_range, ath5k_eeprom_info::ee_header, ath5k_capabilities::q_tx_num, ath5k_capabilities::range_2ghz_max, ath5k_capabilities::range_2ghz_min, ath5k_capabilities::range_5ghz_max, ath5k_capabilities::range_5ghz_min, and u16.
Referenced by ath5k_hw_attach().
00037 { 00038 u16 ee_header; 00039 00040 /* Capabilities stored in the EEPROM */ 00041 ee_header = ah->ah_capabilities.cap_eeprom.ee_header; 00042 00043 if (ah->ah_version == AR5K_AR5210) { 00044 /* 00045 * Set radio capabilities 00046 * (The AR5110 only supports the middle 5GHz band) 00047 */ 00048 ah->ah_capabilities.cap_range.range_5ghz_min = 5120; 00049 ah->ah_capabilities.cap_range.range_5ghz_max = 5430; 00050 ah->ah_capabilities.cap_range.range_2ghz_min = 0; 00051 ah->ah_capabilities.cap_range.range_2ghz_max = 0; 00052 00053 /* Set supported modes */ 00054 ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A; 00055 ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A_TURBO; 00056 } else { 00057 /* 00058 * XXX The tranceiver supports frequencies from 4920 to 6100GHz 00059 * XXX and from 2312 to 2732GHz. There are problems with the 00060 * XXX current ieee80211 implementation because the IEEE 00061 * XXX channel mapping does not support negative channel 00062 * XXX numbers (2312MHz is channel -19). Of course, this 00063 * XXX doesn't matter because these channels are out of range 00064 * XXX but some regulation domains like MKK (Japan) will 00065 * XXX support frequencies somewhere around 4.8GHz. 00066 */ 00067 00068 /* 00069 * Set radio capabilities 00070 */ 00071 00072 if (AR5K_EEPROM_HDR_11A(ee_header)) { 00073 /* 4920 */ 00074 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; 00075 ah->ah_capabilities.cap_range.range_5ghz_max = 6100; 00076 00077 /* Set supported modes */ 00078 ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A; 00079 ah->ah_capabilities.cap_mode |= AR5K_MODE_BIT_11A_TURBO; 00080 if (ah->ah_version == AR5K_AR5212) 00081 ah->ah_capabilities.cap_mode |= 00082 AR5K_MODE_BIT_11G_TURBO; 00083 } 00084 00085 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is 00086 * connected */ 00087 if (AR5K_EEPROM_HDR_11B(ee_header) || 00088 (AR5K_EEPROM_HDR_11G(ee_header) && 00089 ah->ah_version != AR5K_AR5211)) { 00090 /* 2312 */ 00091 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; 00092 ah->ah_capabilities.cap_range.range_2ghz_max = 2732; 00093 00094 if (AR5K_EEPROM_HDR_11B(ee_header)) 00095 ah->ah_capabilities.cap_mode |= 00096 AR5K_MODE_BIT_11B; 00097 00098 if (AR5K_EEPROM_HDR_11G(ee_header) && 00099 ah->ah_version != AR5K_AR5211) 00100 ah->ah_capabilities.cap_mode |= 00101 AR5K_MODE_BIT_11G; 00102 } 00103 } 00104 00105 /* GPIO */ 00106 ah->ah_gpio_npins = AR5K_NUM_GPIO; 00107 00108 /* Set number of supported TX queues */ 00109 ah->ah_capabilities.cap_queues.q_tx_num = 1; 00110 00111 return 0; 00112 }
| int ath5k_hw_get_capability | ( | struct ath5k_hw * | ah, | |
| enum ath5k_capability_type | cap_type, | |||
| u32 | capability, | |||
| u32 * | result | |||
| ) |
Definition at line 115 of file ath5k_caps.c.
References ath5k_hw::ah_version, AR5K_AR5212, AR5K_CAP_BSSIDMASK, AR5K_CAP_BURST, AR5K_CAP_COMPRESSION, AR5K_CAP_NUM_TXQUEUES, AR5K_CAP_TPC, AR5K_CAP_VEOL, AR5K_CAP_XR, and EINVAL.
00118 { 00119 switch (cap_type) { 00120 case AR5K_CAP_NUM_TXQUEUES: 00121 if (result) { 00122 *result = 1; 00123 goto yes; 00124 } 00125 case AR5K_CAP_VEOL: 00126 goto yes; 00127 case AR5K_CAP_COMPRESSION: 00128 if (ah->ah_version == AR5K_AR5212) 00129 goto yes; 00130 else 00131 goto no; 00132 case AR5K_CAP_BURST: 00133 goto yes; 00134 case AR5K_CAP_TPC: 00135 goto yes; 00136 case AR5K_CAP_BSSIDMASK: 00137 if (ah->ah_version == AR5K_AR5212) 00138 goto yes; 00139 else 00140 goto no; 00141 case AR5K_CAP_XR: 00142 if (ah->ah_version == AR5K_AR5212) 00143 goto yes; 00144 else 00145 goto no; 00146 default: 00147 goto no; 00148 } 00149 00150 no: 00151 return -EINVAL; 00152 yes: 00153 return 0; 00154 }
| int ath5k_hw_disable_pspoll | ( | struct ath5k_hw * | ah | ) |
Definition at line 1418 of file ath5k_initvals.c.
References ath5k_hw::ah_radio, ath5k_hw::ah_version, AR5K_AR5210, AR5K_AR5211, AR5K_AR5212, AR5K_PHY_AGC, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, ARRAY_SIZE, ath5k_hw_ini_mode_registers(), ath5k_hw_ini_registers(), ath5k_hw_reg_write(), DBG, and EINVAL.
Referenced by ath5k_hw_reset().
01419 { 01420 /* 01421 * Write initial register settings 01422 */ 01423 01424 /* For AR5212 and combatible */ 01425 if (ah->ah_version == AR5K_AR5212) { 01426 01427 /* First set of mode-specific settings */ 01428 ath5k_hw_ini_mode_registers(ah, 01429 ARRAY_SIZE(ar5212_ini_mode_start), 01430 ar5212_ini_mode_start, mode); 01431 01432 /* 01433 * Write initial settings common for all modes 01434 */ 01435 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start), 01436 ar5212_ini_common_start, change_channel); 01437 01438 /* Second set of mode-specific settings */ 01439 switch (ah->ah_radio) { 01440 case AR5K_RF5111: 01441 01442 ath5k_hw_ini_mode_registers(ah, 01443 ARRAY_SIZE(rf5111_ini_mode_end), 01444 rf5111_ini_mode_end, mode); 01445 01446 ath5k_hw_ini_registers(ah, 01447 ARRAY_SIZE(rf5111_ini_common_end), 01448 rf5111_ini_common_end, change_channel); 01449 01450 /* Baseband gain table */ 01451 ath5k_hw_ini_registers(ah, 01452 ARRAY_SIZE(rf5111_ini_bbgain), 01453 rf5111_ini_bbgain, change_channel); 01454 01455 break; 01456 case AR5K_RF5112: 01457 01458 ath5k_hw_ini_mode_registers(ah, 01459 ARRAY_SIZE(rf5112_ini_mode_end), 01460 rf5112_ini_mode_end, mode); 01461 01462 ath5k_hw_ini_registers(ah, 01463 ARRAY_SIZE(rf5112_ini_common_end), 01464 rf5112_ini_common_end, change_channel); 01465 01466 ath5k_hw_ini_registers(ah, 01467 ARRAY_SIZE(rf5112_ini_bbgain), 01468 rf5112_ini_bbgain, change_channel); 01469 01470 break; 01471 case AR5K_RF5413: 01472 01473 ath5k_hw_ini_mode_registers(ah, 01474 ARRAY_SIZE(rf5413_ini_mode_end), 01475 rf5413_ini_mode_end, mode); 01476 01477 ath5k_hw_ini_registers(ah, 01478 ARRAY_SIZE(rf5413_ini_common_end), 01479 rf5413_ini_common_end, change_channel); 01480 01481 ath5k_hw_ini_registers(ah, 01482 ARRAY_SIZE(rf5112_ini_bbgain), 01483 rf5112_ini_bbgain, change_channel); 01484 01485 break; 01486 case AR5K_RF2316: 01487 case AR5K_RF2413: 01488 01489 ath5k_hw_ini_mode_registers(ah, 01490 ARRAY_SIZE(rf2413_ini_mode_end), 01491 rf2413_ini_mode_end, mode); 01492 01493 ath5k_hw_ini_registers(ah, 01494 ARRAY_SIZE(rf2413_ini_common_end), 01495 rf2413_ini_common_end, change_channel); 01496 01497 /* Override settings from rf2413_ini_common_end */ 01498 if (ah->ah_radio == AR5K_RF2316) { 01499 ath5k_hw_reg_write(ah, 0x00004000, 01500 AR5K_PHY_AGC); 01501 ath5k_hw_reg_write(ah, 0x081b7caa, 01502 0xa274); 01503 } 01504 01505 ath5k_hw_ini_registers(ah, 01506 ARRAY_SIZE(rf5112_ini_bbgain), 01507 rf5112_ini_bbgain, change_channel); 01508 break; 01509 case AR5K_RF2317: 01510 case AR5K_RF2425: 01511 01512 ath5k_hw_ini_mode_registers(ah, 01513 ARRAY_SIZE(rf2425_ini_mode_end), 01514 rf2425_ini_mode_end, mode); 01515 01516 ath5k_hw_ini_registers(ah, 01517 ARRAY_SIZE(rf2425_ini_common_end), 01518 rf2425_ini_common_end, change_channel); 01519 01520 ath5k_hw_ini_registers(ah, 01521 ARRAY_SIZE(rf5112_ini_bbgain), 01522 rf5112_ini_bbgain, change_channel); 01523 break; 01524 default: 01525 return -EINVAL; 01526 01527 } 01528 01529 /* For AR5211 */ 01530 } else if (ah->ah_version == AR5K_AR5211) { 01531 01532 /* AR5K_MODE_11B */ 01533 if (mode > 2) { 01534 DBG("ath5k: unsupported channel mode %d\n", mode); 01535 return -EINVAL; 01536 } 01537 01538 /* Mode-specific settings */ 01539 ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode), 01540 ar5211_ini_mode, mode); 01541 01542 /* 01543 * Write initial settings common for all modes 01544 */ 01545 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini), 01546 ar5211_ini, change_channel); 01547 01548 /* AR5211 only comes with 5111 */ 01549 01550 /* Baseband gain table */ 01551 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain), 01552 rf5111_ini_bbgain, change_channel); 01553 /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */ 01554 } else if (ah->ah_version == AR5K_AR5210) { 01555 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini), 01556 ar5210_ini, change_channel); 01557 } 01558 01559 return 0; 01560 }
| int ath5k_hw_rfregs_init | ( | struct ath5k_hw * | ah, | |
| struct net80211_channel * | channel, | |||
| unsigned int | mode | |||
| ) |
Definition at line 519 of file ath5k_phy.c.
References ath5k_hw::ah_capabilities, ath5k_hw::ah_gain, ath5k_hw::ah_mac_srev, ath5k_hw::ah_offset, ath5k_hw::ah_phy_revision, ath5k_hw::ah_radio, ath5k_hw::ah_radio_5ghz_revision, ath5k_hw::ah_rf_banks, ath5k_hw::ah_rf_banks_size, ath5k_hw::ah_rf_regs_count, AR5K_EEPROM_MODE_11A, AR5K_EEPROM_MODE_11B, AR5K_EEPROM_MODE_11G, AR5K_MAX_RF_BANKS, AR5K_PHY_FRAME_CTL, AR5K_PHY_FRAME_CTL_TX_CLIP, AR5K_REG_WAIT, AR5K_REG_WRITE_BITS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_RF_DB_2GHZ, AR5K_RF_DB_5GHZ, AR5K_RF_DERBY_CHAN_SEL_MODE, AR5K_RF_GAIN_I, AR5K_RF_HIGH_VC_CP, AR5K_RF_LOW_VC_CP, AR5K_RF_MID_VC_CP, AR5K_RF_MIXGAIN_OVR, AR5K_RF_OB_2GHZ, AR5K_RF_OB_5GHZ, AR5K_RF_PAD2GND, AR5K_RF_PD_GAIN_HI, AR5K_RF_PD_GAIN_LO, AR5K_RF_PLO_SEL, AR5K_RF_PUSH_UP, AR5K_RF_PWD_130, AR5K_RF_PWD_131, AR5K_RF_PWD_132, AR5K_RF_PWD_136, AR5K_RF_PWD_137, AR5K_RF_PWD_138, AR5K_RF_PWD_166, AR5K_RF_PWD_167, AR5K_RF_PWD_84, AR5K_RF_PWD_90, AR5K_RF_PWD_ICLOBUF_2G, AR5K_RF_PWD_XPD, AR5K_RF_RFGAIN_SEL, AR5K_RF_XB2_LVL, AR5K_RF_XB5_LVL, AR5K_RF_XPD_GAIN, AR5K_RF_XPD_SEL, AR5K_RFGAIN_ACTIVE, AR5K_SREV_AR2417, AR5K_SREV_AR5413, AR5K_SREV_AR5424, AR5K_SREV_PHY_5212A, AR5K_SREV_RAD_5112A, ARRAY_SIZE, ath5k_hw_bitswap(), ath5k_hw_reg_write(), ath5k_hw_rfb_op(), ath5k_capabilities::cap_eeprom, net80211_channel::center_freq, CHANNEL_2GHZ, CHANNEL_5GHZ, CHANNEL_CCK, CHANNEL_OFDM, DBG, ath5k_eeprom_info::ee_db, ath5k_eeprom_info::ee_i_gain, ath5k_eeprom_info::ee_ob, ath5k_eeprom_info::ee_x_gain, ath5k_eeprom_info::ee_xpd, EINVAL, ENOMEM, ath5k_gain::g_state, ath5k_gain::g_step_idx, ath5k_gain_opt::go_step, ath5k_gain_opt_step::gos_param, net80211_channel::hw_value, malloc(), NULL, rf_regs_2316, rf_regs_2413, rf_regs_2425, rf_regs_5111, rf_regs_5112, rf_regs_5112a, rf_regs_5413, rfb_2316, rfb_2317, rfb_2413, rfb_2417, rfb_2425, rfb_5111, rfb_5112, rfb_5112a, rfb_5413, ath5k_ini_rfbuffer::rfb_bank, ath5k_ini_rfbuffer::rfb_mode_data, rfgain_opt_5111, rfgain_opt_5112, u32, and u8.
Referenced by ath5k_hw_reset().
00521 { 00522 const struct ath5k_rf_reg *rf_regs; 00523 const struct ath5k_ini_rfbuffer *ini_rfb; 00524 const struct ath5k_gain_opt *go = NULL; 00525 const struct ath5k_gain_opt_step *g_step; 00526 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 00527 u8 ee_mode = 0; 00528 u32 *rfb; 00529 int obdb = -1, bank = -1; 00530 unsigned i; 00531 00532 switch (ah->ah_radio) { 00533 case AR5K_RF5111: 00534 rf_regs = rf_regs_5111; 00535 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); 00536 ini_rfb = rfb_5111; 00537 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); 00538 go = &rfgain_opt_5111; 00539 break; 00540 case AR5K_RF5112: 00541 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 00542 rf_regs = rf_regs_5112a; 00543 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); 00544 ini_rfb = rfb_5112a; 00545 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); 00546 } else { 00547 rf_regs = rf_regs_5112; 00548 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); 00549 ini_rfb = rfb_5112; 00550 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); 00551 } 00552 go = &rfgain_opt_5112; 00553 break; 00554 case AR5K_RF2413: 00555 rf_regs = rf_regs_2413; 00556 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); 00557 ini_rfb = rfb_2413; 00558 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); 00559 break; 00560 case AR5K_RF2316: 00561 rf_regs = rf_regs_2316; 00562 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); 00563 ini_rfb = rfb_2316; 00564 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); 00565 break; 00566 case AR5K_RF5413: 00567 rf_regs = rf_regs_5413; 00568 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); 00569 ini_rfb = rfb_5413; 00570 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); 00571 break; 00572 case AR5K_RF2317: 00573 rf_regs = rf_regs_2425; 00574 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 00575 ini_rfb = rfb_2317; 00576 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); 00577 break; 00578 case AR5K_RF2425: 00579 rf_regs = rf_regs_2425; 00580 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); 00581 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { 00582 ini_rfb = rfb_2425; 00583 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); 00584 } else { 00585 ini_rfb = rfb_2417; 00586 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); 00587 } 00588 break; 00589 default: 00590 return -EINVAL; 00591 } 00592 00593 /* If it's the first time we set rf buffer, allocate 00594 * ah->ah_rf_banks based on ah->ah_rf_banks_size 00595 * we set above */ 00596 if (ah->ah_rf_banks == NULL) { 00597 ah->ah_rf_banks = malloc(sizeof(u32) * ah->ah_rf_banks_size); 00598 if (ah->ah_rf_banks == NULL) { 00599 return -ENOMEM; 00600 } 00601 } 00602 00603 /* Copy values to modify them */ 00604 rfb = ah->ah_rf_banks; 00605 00606 for (i = 0; i < ah->ah_rf_banks_size; i++) { 00607 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) { 00608 DBG("ath5k: invalid RF register bank\n"); 00609 return -EINVAL; 00610 } 00611 00612 /* Bank changed, write down the offset */ 00613 if (bank != ini_rfb[i].rfb_bank) { 00614 bank = ini_rfb[i].rfb_bank; 00615 ah->ah_offset[bank] = i; 00616 } 00617 00618 rfb[i] = ini_rfb[i].rfb_mode_data[mode]; 00619 } 00620 00621 /* Set Output and Driver bias current (OB/DB) */ 00622 if (channel->hw_value & CHANNEL_2GHZ) { 00623 00624 if (channel->hw_value & CHANNEL_CCK) 00625 ee_mode = AR5K_EEPROM_MODE_11B; 00626 else 00627 ee_mode = AR5K_EEPROM_MODE_11G; 00628 00629 /* For RF511X/RF211X combination we 00630 * use b_OB and b_DB parameters stored 00631 * in eeprom on ee->ee_ob[ee_mode][0] 00632 * 00633 * For all other chips we use OB/DB for 2Ghz 00634 * stored in the b/g modal section just like 00635 * 802.11a on ee->ee_ob[ee_mode][1] */ 00636 if ((ah->ah_radio == AR5K_RF5111) || 00637 (ah->ah_radio == AR5K_RF5112)) 00638 obdb = 0; 00639 else 00640 obdb = 1; 00641 00642 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 00643 AR5K_RF_OB_2GHZ, 1); 00644 00645 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 00646 AR5K_RF_DB_2GHZ, 1); 00647 00648 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */ 00649 } else if ((channel->hw_value & CHANNEL_5GHZ) || 00650 (ah->ah_radio == AR5K_RF5111)) { 00651 00652 /* For 11a, Turbo and XR we need to choose 00653 * OB/DB based on frequency range */ 00654 ee_mode = AR5K_EEPROM_MODE_11A; 00655 obdb = channel->center_freq >= 5725 ? 3 : 00656 (channel->center_freq >= 5500 ? 2 : 00657 (channel->center_freq >= 5260 ? 1 : 00658 (channel->center_freq > 4000 ? 0 : -1))); 00659 00660 if (obdb < 0) 00661 return -EINVAL; 00662 00663 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], 00664 AR5K_RF_OB_5GHZ, 1); 00665 00666 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], 00667 AR5K_RF_DB_5GHZ, 1); 00668 } 00669 00670 g_step = &go->go_step[ah->ah_gain.g_step_idx]; 00671 00672 /* Bank Modifications (chip-specific) */ 00673 if (ah->ah_radio == AR5K_RF5111) { 00674 00675 /* Set gain_F settings according to current step */ 00676 if (channel->hw_value & CHANNEL_OFDM) { 00677 00678 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, 00679 AR5K_PHY_FRAME_CTL_TX_CLIP, 00680 g_step->gos_param[0]); 00681 00682 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 00683 AR5K_RF_PWD_90, 1); 00684 00685 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 00686 AR5K_RF_PWD_84, 1); 00687 00688 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 00689 AR5K_RF_RFGAIN_SEL, 1); 00690 00691 /* We programmed gain_F parameters, switch back 00692 * to active state */ 00693 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 00694 00695 } 00696 00697 /* Bank 6/7 setup */ 00698 00699 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], 00700 AR5K_RF_PWD_XPD, 1); 00701 00702 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], 00703 AR5K_RF_XPD_GAIN, 1); 00704 00705 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 00706 AR5K_RF_GAIN_I, 1); 00707 00708 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 00709 AR5K_RF_PLO_SEL, 1); 00710 00711 /* TODO: Half/quarter channel support */ 00712 } 00713 00714 if (ah->ah_radio == AR5K_RF5112) { 00715 00716 /* Set gain_F settings according to current step */ 00717 if (channel->hw_value & CHANNEL_OFDM) { 00718 00719 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], 00720 AR5K_RF_MIXGAIN_OVR, 1); 00721 00722 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], 00723 AR5K_RF_PWD_138, 1); 00724 00725 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], 00726 AR5K_RF_PWD_137, 1); 00727 00728 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], 00729 AR5K_RF_PWD_136, 1); 00730 00731 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], 00732 AR5K_RF_PWD_132, 1); 00733 00734 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], 00735 AR5K_RF_PWD_131, 1); 00736 00737 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], 00738 AR5K_RF_PWD_130, 1); 00739 00740 /* We programmed gain_F parameters, switch back 00741 * to active state */ 00742 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 00743 } 00744 00745 /* Bank 6/7 setup */ 00746 00747 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], 00748 AR5K_RF_XPD_SEL, 1); 00749 00750 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { 00751 /* Rev. 1 supports only one xpd */ 00752 ath5k_hw_rfb_op(ah, rf_regs, 00753 ee->ee_x_gain[ee_mode], 00754 AR5K_RF_XPD_GAIN, 1); 00755 00756 } else { 00757 /* TODO: Set high and low gain bits */ 00758 ath5k_hw_rfb_op(ah, rf_regs, 00759 ee->ee_x_gain[ee_mode], 00760 AR5K_RF_PD_GAIN_LO, 1); 00761 ath5k_hw_rfb_op(ah, rf_regs, 00762 ee->ee_x_gain[ee_mode], 00763 AR5K_RF_PD_GAIN_HI, 1); 00764 00765 /* Lower synth voltage on Rev 2 */ 00766 ath5k_hw_rfb_op(ah, rf_regs, 2, 00767 AR5K_RF_HIGH_VC_CP, 1); 00768 00769 ath5k_hw_rfb_op(ah, rf_regs, 2, 00770 AR5K_RF_MID_VC_CP, 1); 00771 00772 ath5k_hw_rfb_op(ah, rf_regs, 2, 00773 AR5K_RF_LOW_VC_CP, 1); 00774 00775 ath5k_hw_rfb_op(ah, rf_regs, 2, 00776 AR5K_RF_PUSH_UP, 1); 00777 00778 /* Decrease power consumption on 5213+ BaseBand */ 00779 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { 00780 ath5k_hw_rfb_op(ah, rf_regs, 1, 00781 AR5K_RF_PAD2GND, 1); 00782 00783 ath5k_hw_rfb_op(ah, rf_regs, 1, 00784 AR5K_RF_XB2_LVL, 1); 00785 00786 ath5k_hw_rfb_op(ah, rf_regs, 1, 00787 AR5K_RF_XB5_LVL, 1); 00788 00789 ath5k_hw_rfb_op(ah, rf_regs, 1, 00790 AR5K_RF_PWD_167, 1); 00791 00792 ath5k_hw_rfb_op(ah, rf_regs, 1, 00793 AR5K_RF_PWD_166, 1); 00794 } 00795 } 00796 00797 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], 00798 AR5K_RF_GAIN_I, 1); 00799 00800 /* TODO: Half/quarter channel support */ 00801 00802 } 00803 00804 if (ah->ah_radio == AR5K_RF5413 && 00805 channel->hw_value & CHANNEL_2GHZ) { 00806 00807 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, 00808 1); 00809 00810 /* Set optimum value for early revisions (on pci-e chips) */ 00811 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && 00812 ah->ah_mac_srev < AR5K_SREV_AR5413) 00813 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), 00814 AR5K_RF_PWD_ICLOBUF_2G, 1); 00815 00816 } 00817 00818 /* Write RF banks on hw */ 00819 for (i = 0; i < ah->ah_rf_banks_size; i++) { 00820 AR5K_REG_WAIT(i); 00821 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); 00822 } 00823 00824 return 0; 00825 }
| int ath5k_hw_rfgain_init | ( | struct ath5k_hw * | ah, | |
| unsigned int | freq | |||
| ) |
Definition at line 457 of file ath5k_phy.c.
References ath5k_hw::ah_radio, AR5K_INI_RFGAIN_2GHZ, AR5K_INI_RFGAIN_5GHZ, AR5K_REG_WAIT, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, ARRAY_SIZE, ath5k_hw_reg_write(), EINVAL, ath5k_ini_rfgain::rfg_register, ath5k_ini_rfgain::rfg_value, rfgain_2316, rfgain_2413, rfgain_2425, rfgain_5111, rfgain_5112, rfgain_5413, size, and u32.
Referenced by ath5k_hw_reset().
00458 { 00459 const struct ath5k_ini_rfgain *ath5k_rfg; 00460 unsigned int i, size; 00461 00462 switch (ah->ah_radio) { 00463 case AR5K_RF5111: 00464 ath5k_rfg = rfgain_5111; 00465 size = ARRAY_SIZE(rfgain_5111); 00466 break; 00467 case AR5K_RF5112: 00468 ath5k_rfg = rfgain_5112; 00469 size = ARRAY_SIZE(rfgain_5112); 00470 break; 00471 case AR5K_RF2413: 00472 ath5k_rfg = rfgain_2413; 00473 size = ARRAY_SIZE(rfgain_2413); 00474 break; 00475 case AR5K_RF2316: 00476 ath5k_rfg = rfgain_2316; 00477 size = ARRAY_SIZE(rfgain_2316); 00478 break; 00479 case AR5K_RF5413: 00480 ath5k_rfg = rfgain_5413; 00481 size = ARRAY_SIZE(rfgain_5413); 00482 break; 00483 case AR5K_RF2317: 00484 case AR5K_RF2425: 00485 ath5k_rfg = rfgain_2425; 00486 size = ARRAY_SIZE(rfgain_2425); 00487 break; 00488 default: 00489 return -EINVAL; 00490 } 00491 00492 switch (freq) { 00493 case AR5K_INI_RFGAIN_2GHZ: 00494 case AR5K_INI_RFGAIN_5GHZ: 00495 break; 00496 default: 00497 return -EINVAL; 00498 } 00499 00500 for (i = 0; i < size; i++) { 00501 AR5K_REG_WAIT(i); 00502 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq], 00503 (u32)ath5k_rfg[i].rfg_register); 00504 } 00505 00506 return 0; 00507 }
| enum ath5k_rfgain ath5k_hw_gainf_calibrate | ( | struct ath5k_hw * | ah | ) |
Definition at line 394 of file ath5k_phy.c.
References ath5k_hw::ah_capabilities, ath5k_hw::ah_gain, ath5k_hw::ah_radio_5ghz_revision, ath5k_hw::ah_rf_banks, AR5K_GAIN_CCK_PROBE_CORR, AR5K_GAIN_CHECK_ADJUST, AR5K_PHY_PAPD_PROBE, AR5K_PHY_PAPD_PROBE_GAINF_S, AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE_TYPE, AR5K_PHY_PAPD_PROBE_TYPE_CCK, AR5K_REG_MS, AR5K_RFGAIN_ACTIVE, AR5K_RFGAIN_INACTIVE, AR5K_RFGAIN_NEED_CHANGE, AR5K_RFGAIN_READ_REQUESTED, AR5K_SREV_RAD_5112A, ath5k_hw_reg_read(), ath5k_hw_rf_check_gainf_readback(), ath5k_hw_rf_gainf_adjust(), ath5k_hw_rf_gainf_corr(), ath5k_capabilities::cap_eeprom, ath5k_eeprom_info::ee_cck_ofdm_gain_delta, ath5k_gain::g_current, ath5k_gain::g_f_corr, ath5k_gain::g_state, NULL, and u32.
Referenced by ath5k_calibrate(), and ath5k_hw_reset().
00395 { 00396 u32 data, type; 00397 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; 00398 00399 if (ah->ah_rf_banks == NULL || 00400 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) 00401 return AR5K_RFGAIN_INACTIVE; 00402 00403 /* No check requested, either engine is inactive 00404 * or an adjustment is already requested */ 00405 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) 00406 goto done; 00407 00408 /* Read the PAPD (Peak to Average Power Detector) 00409 * register */ 00410 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); 00411 00412 /* No probe is scheduled, read gain_F measurement */ 00413 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) { 00414 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; 00415 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE); 00416 00417 /* If tx packet is CCK correct the gain_F measurement 00418 * by cck ofdm gain delta */ 00419 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) { 00420 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) 00421 ah->ah_gain.g_current += 00422 ee->ee_cck_ofdm_gain_delta; 00423 else 00424 ah->ah_gain.g_current += 00425 AR5K_GAIN_CCK_PROBE_CORR; 00426 } 00427 00428 /* Further correct gain_F measurement for 00429 * RF5112A radios */ 00430 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { 00431 ath5k_hw_rf_gainf_corr(ah); 00432 ah->ah_gain.g_current = 00433 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? 00434 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) : 00435 0; 00436 } 00437 00438 /* Check if measurement is ok and if we need 00439 * to adjust gain, schedule a gain adjustment, 00440 * else switch back to the acive state */ 00441 if (ath5k_hw_rf_check_gainf_readback(ah) && 00442 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && 00443 ath5k_hw_rf_gainf_adjust(ah)) { 00444 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; 00445 } else { 00446 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 00447 } 00448 } 00449 00450 done: 00451 return ah->ah_gain.g_state; 00452 }
| int ath5k_hw_rfgain_opt_init | ( | struct ath5k_hw * | ah | ) |
Definition at line 158 of file ath5k_phy.c.
References ath5k_hw::ah_gain, ath5k_hw::ah_radio, AR5K_RF5111, AR5K_RF5112, AR5K_RFGAIN_ACTIVE, EINVAL, ath5k_gain::g_high, ath5k_gain::g_low, ath5k_gain::g_state, ath5k_gain::g_step_idx, ath5k_gain_opt::go_default, rfgain_opt_5111, and rfgain_opt_5112.
Referenced by ath5k_hw_attach().
00159 { 00160 /* Initialize the gain optimization values */ 00161 switch (ah->ah_radio) { 00162 case AR5K_RF5111: 00163 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; 00164 ah->ah_gain.g_low = 20; 00165 ah->ah_gain.g_high = 35; 00166 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 00167 break; 00168 case AR5K_RF5112: 00169 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; 00170 ah->ah_gain.g_low = 20; 00171 ah->ah_gain.g_high = 85; 00172 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; 00173 break; 00174 default: 00175 return -EINVAL; 00176 } 00177 00178 return 0; 00179 }
Definition at line 835 of file ath5k_phy.c.
References ath5k_hw::ah_capabilities, ath5k_capabilities::cap_range, CHANNEL_2GHZ, CHANNEL_5GHZ, ath5k_capabilities::range_2ghz_min, and ath5k_capabilities::range_5ghz_min.
Referenced by ath5k_copy_channels(), and ath5k_hw_channel().
00836 { 00837 /* Check if the channel is in our supported range */ 00838 if (flags & CHANNEL_2GHZ) { 00839 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && 00840 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) 00841 return 1; 00842 } else if (flags & CHANNEL_5GHZ) 00843 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && 00844 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) 00845 return 1; 00846 00847 return 0; 00848 }
| int ath5k_hw_channel | ( | struct ath5k_hw * | ah, | |
| struct net80211_channel * | channel | |||
| ) |
Definition at line 1053 of file ath5k_phy.c.
References ath5k_hw::ah_current_channel, ath5k_hw::ah_radio, ath5k_hw::ah_turbo, AR5K_PHY_CCKTXCTL, AR5K_PHY_CCKTXCTL_JAPAN, AR5K_PHY_CCKTXCTL_WORLD, AR5K_REG_ENABLE_BITS, AR5K_RF2425, AR5K_RF5110, AR5K_RF5111, ath5k_channel_ok(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_channel(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), net80211_channel::center_freq, CHANNEL_T, DBG, EINVAL, net80211_channel::hw_value, and strerror().
Referenced by ath5k_hw_reset(), and ath5k_hw_rf5110_calibrate().
01054 { 01055 int ret; 01056 /* 01057 * Check bounds supported by the PHY (we don't care about regultory 01058 * restrictions at this point). Note: hw_value already has the band 01059 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok() 01060 * of the band by that */ 01061 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) { 01062 DBG("ath5k: channel frequency (%d MHz) out of supported " 01063 "range\n", channel->center_freq); 01064 return -EINVAL; 01065 } 01066 01067 /* 01068 * Set the channel and wait 01069 */ 01070 switch (ah->ah_radio) { 01071 case AR5K_RF5110: 01072 ret = ath5k_hw_rf5110_channel(ah, channel); 01073 break; 01074 case AR5K_RF5111: 01075 ret = ath5k_hw_rf5111_channel(ah, channel); 01076 break; 01077 case AR5K_RF2425: 01078 ret = ath5k_hw_rf2425_channel(ah, channel); 01079 break; 01080 default: 01081 ret = ath5k_hw_rf5112_channel(ah, channel); 01082 break; 01083 } 01084 01085 if (ret) { 01086 DBG("ath5k: setting channel failed: %s\n", strerror(ret)); 01087 return ret; 01088 } 01089 01090 /* Set JAPAN setting for channel 14 */ 01091 if (channel->center_freq == 2484) { 01092 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 01093 AR5K_PHY_CCKTXCTL_JAPAN); 01094 } else { 01095 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, 01096 AR5K_PHY_CCKTXCTL_WORLD); 01097 } 01098 01099 ah->ah_current_channel = channel; 01100 ah->ah_turbo = (channel->hw_value == CHANNEL_T ? 1 : 0); 01101 01102 return 0; 01103 }
| int ath5k_hw_phy_calibrate | ( | struct ath5k_hw * | ah, | |
| struct net80211_channel * | channel | |||
| ) |
Definition at line 1350 of file ath5k_phy.c.
References ath5k_hw::ah_radio, AR5K_RF5110, ath5k_hw_rf5110_calibrate(), and ath5k_hw_rf511x_calibrate().
Referenced by ath5k_calibrate().
01352 { 01353 int ret; 01354 01355 if (ah->ah_radio == AR5K_RF5110) 01356 ret = ath5k_hw_rf5110_calibrate(ah, channel); 01357 else 01358 ret = ath5k_hw_rf511x_calibrate(ah, channel); 01359 01360 return ret; 01361 }
| int ath5k_hw_noise_floor_calibration | ( | struct ath5k_hw * | ah, | |
| short | freq | |||
| ) |
ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
: struct ath5k_hw pointer we are operating on : the channel frequency, just used for error logging
This function performs a noise floor calibration of the PHY and waits for it to complete. Then the noise floor value is compared to some maximum noise floor we consider valid.
Note that this is different from what the madwifi HAL does: it reads the noise floor and afterwards initiates the calibration. Since the noise floor calibration can take some time to finish, depending on the current channel use, that avoids the occasional timeout warnings we are seeing now.
See the following link for an Atheros patent on noise floor calibration: http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \ &p=1&u=2Fnetahtml2FPTO2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
XXX: Since during noise floor calibration antennas are detached according to the patent, we should stop tx queues here.
Definition at line 1132 of file ath5k_phy.c.
References ath5k_hw::ah_noise_floor, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, AR5K_PHY_NF, AR5K_PHY_NF_ACTIVE, AR5K_PHY_NF_AVAL, AR5K_PHY_NF_RVAL, AR5K_REG_ENABLE_BITS, AR5K_TUNE_NOISE_FLOOR, ath5k_hw_reg_read(), DBG, DBG2, EAGAIN, and mdelay().
Referenced by ath5k_hw_reset(), ath5k_hw_rf5110_calibrate(), and ath5k_hw_rf511x_calibrate().
01133 { 01134 int ret; 01135 unsigned int i; 01136 s32 noise_floor; 01137 01138 /* 01139 * Enable noise floor calibration 01140 */ 01141 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, 01142 AR5K_PHY_AGCCTL_NF); 01143 01144 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, 01145 AR5K_PHY_AGCCTL_NF, 0, 0); 01146 01147 if (ret) { 01148 DBG("ath5k: noise floor calibration timeout (%d MHz)\n", freq); 01149 return -EAGAIN; 01150 } 01151 01152 /* Wait until the noise floor is calibrated and read the value */ 01153 for (i = 20; i > 0; i--) { 01154 mdelay(1); 01155 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF); 01156 noise_floor = AR5K_PHY_NF_RVAL(noise_floor); 01157 if (noise_floor & AR5K_PHY_NF_ACTIVE) { 01158 noise_floor = AR5K_PHY_NF_AVAL(noise_floor); 01159 01160 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR) 01161 break; 01162 } 01163 } 01164 01165 DBG2("ath5k: noise floor %d\n", noise_floor); 01166 01167 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) { 01168 DBG("ath5k: noise floor calibration failed (%d MHz)\n", freq); 01169 return -EAGAIN; 01170 } 01171 01172 ah->ah_noise_floor = noise_floor; 01173 01174 return 0; 01175 }
Definition at line 1377 of file ath5k_phy.c.
References ath5k_hw::ah_version, AR5K_AR5210, AR5K_PHY, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY_SHIFT_5GHZ, ath5k_hw_bitswap(), ath5k_hw_reg_read(), ath5k_hw_reg_write(), CHANNEL_2GHZ, CHANNEL_5GHZ, mdelay(), u16, and u32.
Referenced by ath5k_hw_attach().
01378 { 01379 unsigned int i; 01380 u32 srev; 01381 u16 ret; 01382 01383 /* 01384 * Set the radio chip access register 01385 */ 01386 switch (chan) { 01387 case CHANNEL_2GHZ: 01388 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); 01389 break; 01390 case CHANNEL_5GHZ: 01391 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 01392 break; 01393 default: 01394 return 0; 01395 } 01396 01397 mdelay(2); 01398 01399 /* ...wait until PHY is ready and read the selected radio revision */ 01400 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); 01401 01402 for (i = 0; i < 8; i++) 01403 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); 01404 01405 if (ah->ah_version == AR5K_AR5210) { 01406 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf; 01407 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1; 01408 } else { 01409 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; 01410 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) | 01411 ((srev & 0x0f) << 4), 8); 01412 } 01413 01414 /* Reset to the 5GHz mode */ 01415 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); 01416 01417 return ret; 01418 }
| void ath5k_hw_set_def_antenna | ( | struct ath5k_hw * | ah, | |
| unsigned int | ant | |||
| ) |
Definition at line 1421 of file ath5k_phy.c.
References ath5k_hw::ah_version, AR5K_AR5210, AR5K_DEFAULT_ANTENNA, and ath5k_hw_reg_write().
01422 { 01423 if (ah->ah_version != AR5K_AR5210) 01424 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA); 01425 }
| unsigned int ath5k_hw_get_def_antenna | ( | struct ath5k_hw * | ah | ) |
Definition at line 1427 of file ath5k_phy.c.
References ath5k_hw::ah_version, AR5K_AR5210, AR5K_DEFAULT_ANTENNA, and ath5k_hw_reg_read().
01428 { 01429 if (ah->ah_version != AR5K_AR5210) 01430 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA); 01431 01432 return 0; /*XXX: What do we return for 5210 ?*/ 01433 }
| int ath5k_hw_phy_disable | ( | struct ath5k_hw * | ah | ) |
Definition at line 1363 of file ath5k_phy.c.
References AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE, and ath5k_hw_reg_write().
Referenced by ath5k_stop_hw().
01364 { 01365 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); 01366 01367 return 0; 01368 }
| int ath5k_hw_txpower | ( | struct ath5k_hw * | ah, | |
| struct net80211_channel * | channel, | |||
| u8 | ee_mode, | |||
| u8 | txpower | |||
| ) |
Definition at line 2479 of file ath5k_phy.c.
References ath5k_hw::ah_radio, ath5k_hw::ah_txpower, AR5K_PHY_TXPOWER_RATE1, AR5K_PHY_TXPOWER_RATE2, AR5K_PHY_TXPOWER_RATE3, AR5K_PHY_TXPOWER_RATE4, AR5K_PHY_TXPOWER_RATE_MAX, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE, AR5K_PWRTABLE_LINEAR_PCDAC, AR5K_PWRTABLE_PWR_TO_PCDAC, AR5K_PWRTABLE_PWR_TO_PDADC, AR5K_REG_MS, AR5K_RF2316, AR5K_RF2317, AR5K_RF2413, AR5K_RF2425, AR5K_RF5111, AR5K_RF5112, AR5K_RF5413, AR5K_TPC, AR5K_TPC_ACK, AR5K_TPC_CHIRP, AR5K_TPC_CTS, AR5K_TUNE_DEFAULT_TXPOWER, AR5K_TUNE_MAX_TXPOWER, AR5K_TUNE_TPC_TXPOWER, AR5K_TXPOWER_CCK, AR5K_TXPOWER_OFDM, ath5k_get_max_ctl_power(), ath5k_get_rate_pcal_data(), ath5k_hw_reg_write(), ath5k_setup_channel_powertable(), ath5k_setup_rate_powertable(), DBG, EINVAL, memset(), ath5k_hw::txp_max_pwr, ath5k_hw::txp_min_pwr, ath5k_hw::txp_tpc, and u8.
Referenced by ath5k_hw_reset(), and ath5k_hw_set_txpower_limit().
02481 { 02482 struct ath5k_rate_pcal_info rate_info; 02483 u8 type; 02484 int ret; 02485 02486 if (txpower > AR5K_TUNE_MAX_TXPOWER) { 02487 DBG("ath5k: invalid tx power %d\n", txpower); 02488 return -EINVAL; 02489 } 02490 if (txpower == 0) 02491 txpower = AR5K_TUNE_DEFAULT_TXPOWER; 02492 02493 /* Reset TX power values */ 02494 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); 02495 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; 02496 ah->ah_txpower.txp_min_pwr = 0; 02497 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER; 02498 02499 /* Initialize TX power table */ 02500 switch (ah->ah_radio) { 02501 case AR5K_RF5111: 02502 type = AR5K_PWRTABLE_PWR_TO_PCDAC; 02503 break; 02504 case AR5K_RF5112: 02505 type = AR5K_PWRTABLE_LINEAR_PCDAC; 02506 break; 02507 case AR5K_RF2413: 02508 case AR5K_RF5413: 02509 case AR5K_RF2316: 02510 case AR5K_RF2317: 02511 case AR5K_RF2425: 02512 type = AR5K_PWRTABLE_PWR_TO_PDADC; 02513 break; 02514 default: 02515 return -EINVAL; 02516 } 02517 02518 /* FIXME: Only on channel/mode change */ 02519 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type); 02520 if (ret) 02521 return ret; 02522 02523 /* Limit max power if we have a CTL available */ 02524 ath5k_get_max_ctl_power(ah, channel); 02525 02526 /* FIXME: Tx power limit for this regdomain 02527 * XXX: Mac80211/CRDA will do that anyway ? */ 02528 02529 /* FIXME: Antenna reduction stuff */ 02530 02531 /* FIXME: Limit power on turbo modes */ 02532 02533 /* FIXME: TPC scale reduction */ 02534 02535 /* Get surounding channels for per-rate power table 02536 * calibration */ 02537 ath5k_get_rate_pcal_data(ah, channel, &rate_info); 02538 02539 /* Setup rate power table */ 02540 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); 02541 02542 /* Write rate power table on hw */ 02543 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | 02544 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) | 02545 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1); 02546 02547 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | 02548 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) | 02549 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2); 02550 02551 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | 02552 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) | 02553 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3); 02554 02555 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | 02556 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) | 02557 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4); 02558 02559 /* FIXME: TPC support */ 02560 if (ah->ah_txpower.txp_tpc) { 02561 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | 02562 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 02563 02564 ath5k_hw_reg_write(ah, 02565 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) | 02566 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) | 02567 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP), 02568 AR5K_TPC); 02569 } else { 02570 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX | 02571 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX); 02572 } 02573 02574 return 0; 02575 }
Definition at line 2577 of file ath5k_phy.c.
References ath5k_hw::ah_current_channel, ath5k_hw_txpower(), and DBG2.
02578 { 02579 struct net80211_channel *channel = ah->ah_current_channel; 02580 02581 DBG2("ath5k: changing txpower to %d\n", txpower); 02582 02583 return ath5k_hw_txpower(ah, channel, mode, txpower); 02584 }
| static unsigned int ath5k_hw_htoclock | ( | unsigned int | usec, | |
| int | turbo | |||
| ) | [inline, static] |
Definition at line 1199 of file ath5k.h.
Referenced by ath5k_hw_set_ack_timeout(), ath5k_hw_set_cts_timeout(), ath5k_hw_set_slot_time(), and ath5k_hw_write_ofdm_timings().
| static unsigned int ath5k_hw_clocktoh | ( | unsigned int | clock, | |
| int | turbo | |||
| ) | [inline, static] |
Definition at line 1208 of file ath5k.h.
Referenced by ath5k_hw_get_ack_timeout(), ath5k_hw_get_cts_timeout(), ath5k_hw_set_ack_timeout(), and ath5k_hw_set_cts_timeout().
Definition at line 1216 of file ath5k.h.
References ath5k_hw::ah_iobase, and readl.
Referenced by ath5k_combine_pwr_to_pdadc_curves(), ath5k_hw_attach(), ath5k_hw_eeprom_read(), ath5k_hw_gainf_calibrate(), ath5k_hw_get_ack_timeout(), ath5k_hw_get_cts_timeout(), ath5k_hw_get_def_antenna(), ath5k_hw_get_gpio(), ath5k_hw_get_isr(), ath5k_hw_get_rx_filter(), ath5k_hw_get_rxdp(), ath5k_hw_get_txdp(), ath5k_hw_ini_registers(), ath5k_hw_is_intr_pending(), ath5k_hw_nic_reset(), ath5k_hw_nic_wakeup(), ath5k_hw_noise_floor_calibration(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_reset(), ath5k_hw_reset_key(), ath5k_hw_reset_tx_queue(), ath5k_hw_rf5110_calibrate(), ath5k_hw_rf511x_calibrate(), ath5k_hw_set_gpio(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_gpio_output(), ath5k_hw_set_imr(), ath5k_hw_set_lladdr(), ath5k_hw_set_opmode(), ath5k_hw_start_rx_dma(), ath5k_hw_start_tx_dma(), ath5k_hw_stop_rx_dma(), ath5k_hw_stop_tx_dma(), ath5k_hw_tweak_initval_settings(), ath5k_hw_update_tx_triglevel(), ath5k_hw_wake(), and ath5k_setup_pwr_to_pdadc_table().
Definition at line 1224 of file ath5k.h.
References ath5k_hw::ah_iobase, and writel.
Referenced by ath5k_combine_pwr_to_pdadc_curves(), ath5k_hw_attach(), ath5k_hw_commit_eeprom_settings(), ath5k_hw_eeprom_read(), ath5k_hw_ini_mode_registers(), ath5k_hw_ini_registers(), ath5k_hw_nic_reset(), ath5k_hw_nic_wakeup(), ath5k_hw_phy_disable(), ath5k_hw_post(), ath5k_hw_radio_revision(), ath5k_hw_request_rfgain_probe(), ath5k_hw_reset(), ath5k_hw_reset_key(), ath5k_hw_reset_tx_queue(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_calibrate(), ath5k_hw_rf5110_channel(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), ath5k_hw_rfgain_init(), ath5k_hw_rfregs_init(), ath5k_hw_set_associd(), ath5k_hw_set_bssid_mask(), ath5k_hw_set_def_antenna(), ath5k_hw_set_gpio(), ath5k_hw_set_gpio_input(), ath5k_hw_set_gpio_intr(), ath5k_hw_set_gpio_output(), ath5k_hw_set_imr(), ath5k_hw_set_lladdr(), ath5k_hw_set_mcast_filter(), ath5k_hw_set_opmode(), ath5k_hw_set_rx_filter(), ath5k_hw_set_rxdp(), ath5k_hw_set_slot_time(), ath5k_hw_set_txdp(), ath5k_hw_start_rx_dma(), ath5k_hw_start_tx_dma(), ath5k_hw_stop_rx_dma(), ath5k_hw_stop_tx_dma(), ath5k_hw_tweak_initval_settings(), ath5k_hw_txpower(), ath5k_hw_update_tx_triglevel(), ath5k_hw_wake(), ath5k_hw_write_initvals(), ath5k_hw_write_rate_duration(), ath5k_irq(), ath5k_setup_pcdac_table(), and ath5k_setup_pwr_to_pdadc_table().
Definition at line 1267 of file ath5k.h.
References u32.
Referenced by ath5k_hw_radio_revision(), ath5k_hw_rf2425_channel(), ath5k_hw_rf5110_chan2athchan(), ath5k_hw_rf5111_channel(), ath5k_hw_rf5112_channel(), ath5k_hw_rfb_op(), and ath5k_hw_rfregs_init().
01268 { 01269 u32 retval = 0, bit, i; 01270 01271 for (i = 0; i < bits; i++) { 01272 bit = (val >> i) & 1; 01273 retval = (retval << 1) | bit; 01274 } 01275 01276 return retval; 01277 }
1.5.7.1